diff --git a/pyrtl/corecircuits.py b/pyrtl/corecircuits.py
index 64e68c84..cecdf502 100644
--- a/pyrtl/corecircuits.py
+++ b/pyrtl/corecircuits.py
@@ -3,6 +3,7 @@
 from __future__ import annotations
 
 import itertools
+from collections.abc import Iterator, Sequence
 
 from pyrtl.conditional import otherwise
 from pyrtl.core import Block, LogicNet, working_block
@@ -228,7 +229,7 @@ def concat(*args: WireVectorLike) -> WireVector:
     return outwire
 
 
-def concat_list(wire_list: list[WireVectorLike]) -> WireVector:
+def concat_list(wire_list: Sequence[WireVectorLike]) -> WireVector:
     """Concatenates a list of :class:`WireVectors<WireVector>` into a single
     :class:`WireVector`.
 
@@ -706,7 +707,7 @@ def shift_right_logical(
     return barrel.barrel_shifter(bits_to_shift, bit_in, dir, shift_amount)
 
 
-def match_bitwidth(*args: WireVector, signed: bool = False) -> tuple[WireVector]:
+def match_bitwidth(*args: WireVector, signed: bool = False) -> Iterator[WireVector]:
     """Matches multiple :class:`WireVector` :attr:`bitwidths<~WireVector.bitwidth>` via
     zero- or sign-extension.
 
diff --git a/pyrtl/wire.py b/pyrtl/wire.py
index 61e3c493..254e881c 100644
--- a/pyrtl/wire.py
+++ b/pyrtl/wire.py
@@ -2041,7 +2041,7 @@ def __ior__(self, other: WireVectorLike):
         raise PyrtlError(msg)
 
     @next.setter
-    def next(self, other: WireVectorLike):
+    def next(self, other: Register._Next):
         if not isinstance(other, Register._Next):
             msg = 'error, .next should be set with "<<=" or "|=" operators'
             raise PyrtlError(msg)
diff --git a/www/examples/example-adder.py b/www/examples/example-adder.py
index cf072006..cdb7a90d 100644
--- a/www/examples/example-adder.py
+++ b/www/examples/example-adder.py
@@ -18,10 +18,11 @@ def adder(
     """n-bit ripple carry adder with carry in and carry out."""
     a, b = pyrtl.match_bitwidth(a, b)
 
-    sum = [None] * a.bitwidth
+    sum: list[pyrtl.WireVector] = []
+    cout = cin
     for i in range(a.bitwidth):
-        sum[i], cout = fa(a[i], b[i], cin)
-        cin = cout
+        s, cout = fa(a[i], b[i], cout)
+        sum.append(s)
 
     full_sum = pyrtl.concat_list(sum)
     return full_sum, cout
diff --git a/www/examples/example-fir.py b/www/examples/example-fir.py
index bf708882..b2ae51ab 100644
--- a/www/examples/example-fir.py
+++ b/www/examples/example-fir.py
@@ -1,4 +1,5 @@
 import pyrtl
+import itertools
 
 # # Finite impulse filter example.
 
@@ -7,9 +8,12 @@ def fir(x: pyrtl.WireVector, bs: list[int]):
     rwidth = x.bitwidth  # Bitwidth of the registers.
     ntaps = len(bs)  # Number of coefficients.
 
-    zs = [x] + [pyrtl.Register(rwidth) for _ in range(ntaps - 1)]
-    for i in range(1, ntaps):
-        zs[i].next <<= zs[i - 1]
+    # Create a chain of registers.
+    regs = [pyrtl.Register(rwidth) for _ in range(ntaps - 1)]
+    regs[0].next <<= x
+    for prev, curr in itertools.pairwise(regs):
+        curr.next <<= prev
+    zs = [x, *regs]
 
     # Produce the final sum of products.
     return sum(z * b for z, b in zip(zs, bs, strict=True))