From 9f3ccbafbf822dbf6474b43256317bffd1f47625 Mon Sep 17 00:00:00 2001 From: Sijie Kong Date: Thu, 20 Aug 2026 13:24:53 -0400 Subject: [PATCH 1/9] Fix: initialize adder sum as empty list --- www/examples/example-adder.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/www/examples/example-adder.py b/www/examples/example-adder.py index cf072006..4ad100af 100644 --- a/www/examples/example-adder.py +++ b/www/examples/example-adder.py @@ -18,9 +18,10 @@ def adder( """n-bit ripple carry adder with carry in and carry out.""" a, b = pyrtl.match_bitwidth(a, b) - sum = [None] * a.bitwidth + sum = [] for i in range(a.bitwidth): - sum[i], cout = fa(a[i], b[i], cin) + s, cout = fa(a[i], b[i], cin) + sum.append(s) cin = cout full_sum = pyrtl.concat_list(sum) From fc2e52885ef2e6b2b5feb8cf6c0cb7afa9b35f09 Mon Sep 17 00:00:00 2001 From: Sijie Kong Date: Thu, 20 Aug 2026 13:30:42 -0400 Subject: [PATCH 2/9] Fix: initialize adder sum as empty list --- www/examples/example-adder.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/www/examples/example-adder.py b/www/examples/example-adder.py index 4ad100af..91633b8d 100644 --- a/www/examples/example-adder.py +++ b/www/examples/example-adder.py @@ -18,7 +18,7 @@ def adder( """n-bit ripple carry adder with carry in and carry out.""" a, b = pyrtl.match_bitwidth(a, b) - sum = [] + sum: list[pyrtl.WireVector] = [] for i in range(a.bitwidth): s, cout = fa(a[i], b[i], cin) sum.append(s) From 6b072722b5ac41db6c17320ad0773bd453cd875e Mon Sep 17 00:00:00 2001 From: Sijie Kong Date: Thu, 20 Aug 2026 15:23:22 -0400 Subject: [PATCH 3/9] Fix: use explicit regs instead of mixed regs and wires --- www/examples/example-fir.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/www/examples/example-fir.py b/www/examples/example-fir.py index bf708882..6ddec96a 100644 --- a/www/examples/example-fir.py +++ b/www/examples/example-fir.py @@ -7,9 +7,11 @@ def fir(x: pyrtl.WireVector, bs: list[int]): rwidth = x.bitwidth # Bitwidth of the registers. ntaps = len(bs) # Number of coefficients. - zs = [x] + [pyrtl.Register(rwidth) for _ in range(ntaps - 1)] - for i in range(1, ntaps): - zs[i].next <<= zs[i - 1] + regs = [pyrtl.Register(rwidth) for _ in range(ntaps - 1)] + for i, reg in enumerate(regs): + reg.next <<= x if i == 0 else regs[i - 1] + + zs = [x, *regs] # Produce the final sum of products. return sum(z * b for z, b in zip(zs, bs, strict=True)) From 4e6181643a0b61f3cee0a44def917e429f745fa6 Mon Sep 17 00:00:00 2001 From: Sijie Kong Date: Fri, 21 Aug 2026 09:56:34 -0400 Subject: [PATCH 4/9] Fix: cout is Unbound --- www/examples/example-adder.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/www/examples/example-adder.py b/www/examples/example-adder.py index 91633b8d..cdb7a90d 100644 --- a/www/examples/example-adder.py +++ b/www/examples/example-adder.py @@ -19,10 +19,10 @@ def adder( a, b = pyrtl.match_bitwidth(a, b) sum: list[pyrtl.WireVector] = [] + cout = cin for i in range(a.bitwidth): - s, cout = fa(a[i], b[i], cin) + s, cout = fa(a[i], b[i], cout) sum.append(s) - cin = cout full_sum = pyrtl.concat_list(sum) return full_sum, cout From 6b8795087c9c1a7cd9fea686657c027e1e36a750 Mon Sep 17 00:00:00 2001 From: Sijie Kong Date: Fri, 21 Aug 2026 10:03:56 -0400 Subject: [PATCH 5/9] Add more accurate types --- pyrtl/corecircuits.py | 7 ++++--- pyrtl/wire.py | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/pyrtl/corecircuits.py b/pyrtl/corecircuits.py index 64e68c84..7e4b59b1 100644 --- a/pyrtl/corecircuits.py +++ b/pyrtl/corecircuits.py @@ -4,6 +4,8 @@ import itertools +from typing import Sequence, Iterable + from pyrtl.conditional import otherwise from pyrtl.core import Block, LogicNet, working_block from pyrtl.pyrtlexceptions import PyrtlError, PyrtlInternalError @@ -227,8 +229,7 @@ def concat(*args: WireVectorLike) -> WireVector: working_block().add_net(net) return outwire - -def concat_list(wire_list: list[WireVectorLike]) -> WireVector: +def concat_list(wire_list: Sequence[WireVectorLike]) -> WireVector: """Concatenates a list of :class:`WireVectors` into a single :class:`WireVector`. @@ -706,7 +707,7 @@ def shift_right_logical( return barrel.barrel_shifter(bits_to_shift, bit_in, dir, shift_amount) -def match_bitwidth(*args: WireVector, signed: bool = False) -> tuple[WireVector]: +def match_bitwidth(*args: WireVector, signed: bool = False) -> Iterable[WireVector, ...]: """Matches multiple :class:`WireVector` :attr:`bitwidths<~WireVector.bitwidth>` via zero- or sign-extension. diff --git a/pyrtl/wire.py b/pyrtl/wire.py index 61e3c493..728d9ecb 100644 --- a/pyrtl/wire.py +++ b/pyrtl/wire.py @@ -2041,7 +2041,7 @@ def __ior__(self, other: WireVectorLike): raise PyrtlError(msg) @next.setter - def next(self, other: WireVectorLike): + def next(self, other: Register._Next): # other: WireVectorLike if not isinstance(other, Register._Next): msg = 'error, .next should be set with "<<=" or "|=" operators' raise PyrtlError(msg) From 5c0899b83413126b09212410bea44f28d51ae5bc Mon Sep 17 00:00:00 2001 From: Sijie Kong Date: Fri, 21 Aug 2026 20:58:33 -0400 Subject: [PATCH 6/9] Fix: clean up --- pyrtl/wire.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pyrtl/wire.py b/pyrtl/wire.py index 728d9ecb..254e881c 100644 --- a/pyrtl/wire.py +++ b/pyrtl/wire.py @@ -2041,7 +2041,7 @@ def __ior__(self, other: WireVectorLike): raise PyrtlError(msg) @next.setter - def next(self, other: Register._Next): # other: WireVectorLike + def next(self, other: Register._Next): if not isinstance(other, Register._Next): msg = 'error, .next should be set with "<<=" or "|=" operators' raise PyrtlError(msg) From b2f28149c685ed47670a416ef465daab7184ccec Mon Sep 17 00:00:00 2001 From: Sijie Kong Date: Fri, 21 Aug 2026 21:02:09 -0400 Subject: [PATCH 7/9] Import abc instead of typing --- pyrtl/corecircuits.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/pyrtl/corecircuits.py b/pyrtl/corecircuits.py index 7e4b59b1..53a99801 100644 --- a/pyrtl/corecircuits.py +++ b/pyrtl/corecircuits.py @@ -3,8 +3,7 @@ from __future__ import annotations import itertools - -from typing import Sequence, Iterable +from collections.abc import Iterator, Sequence from pyrtl.conditional import otherwise from pyrtl.core import Block, LogicNet, working_block @@ -707,7 +706,7 @@ def shift_right_logical( return barrel.barrel_shifter(bits_to_shift, bit_in, dir, shift_amount) -def match_bitwidth(*args: WireVector, signed: bool = False) -> Iterable[WireVector, ...]: +def match_bitwidth(*args: WireVector, signed: bool = False) -> Iterator[WireVector]: """Matches multiple :class:`WireVector` :attr:`bitwidths<~WireVector.bitwidth>` via zero- or sign-extension. From d2809d7cecd51404164af21fbf826b52b4c6c8c0 Mon Sep 17 00:00:00 2001 From: Sijie Kong Date: Mon, 24 Aug 2026 15:42:36 -0400 Subject: [PATCH 8/9] Reformat corecircuits.py --- pyrtl/corecircuits.py | 1 + 1 file changed, 1 insertion(+) diff --git a/pyrtl/corecircuits.py b/pyrtl/corecircuits.py index 53a99801..cecdf502 100644 --- a/pyrtl/corecircuits.py +++ b/pyrtl/corecircuits.py @@ -228,6 +228,7 @@ def concat(*args: WireVectorLike) -> WireVector: working_block().add_net(net) return outwire + def concat_list(wire_list: Sequence[WireVectorLike]) -> WireVector: """Concatenates a list of :class:`WireVectors` into a single :class:`WireVector`. From 085b6e468d95568cd4c8eae4f1703743c7d35bb4 Mon Sep 17 00:00:00 2001 From: Sijie Kong Date: Mon, 24 Aug 2026 15:53:14 -0400 Subject: [PATCH 9/9] Chain registers via pairwise(). --- www/examples/example-fir.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/www/examples/example-fir.py b/www/examples/example-fir.py index 6ddec96a..b2ae51ab 100644 --- a/www/examples/example-fir.py +++ b/www/examples/example-fir.py @@ -1,4 +1,5 @@ import pyrtl +import itertools # # Finite impulse filter example. @@ -7,10 +8,11 @@ def fir(x: pyrtl.WireVector, bs: list[int]): rwidth = x.bitwidth # Bitwidth of the registers. ntaps = len(bs) # Number of coefficients. + # Create a chain of registers. regs = [pyrtl.Register(rwidth) for _ in range(ntaps - 1)] - for i, reg in enumerate(regs): - reg.next <<= x if i == 0 else regs[i - 1] - + regs[0].next <<= x + for prev, curr in itertools.pairwise(regs): + curr.next <<= prev zs = [x, *regs] # Produce the final sum of products.