Issues

• Improve static analysis (pana + new lints)

  enhancement
  intel/rohd-cosim#53 · Filter by author mkorbel1 opened on Sep 30, 2025

• Allow CosimPortConfig to accept non-localhost hosts

  enhancement
  intel/rohd-cosim#48 · Filter by author mkorbel1 opened on Mar 19, 2025

• Enable Modules to be run in SystemVerilog simulators

  enhancementhelp wanted
  intel/rohd-cosim#44 · Filter by author mkorbel1 opened on Jan 23, 2025

• Add support for Cosim mixin on any Module instead of just ExternalSystemVerilogModule

  enhancement
  intel/rohd-cosim#43 · Filter by author mkorbel1 opened on Jan 23, 2025

• Flaky test: "port test dart fail async"

  bughelp wanted
  intel/rohd-cosim#41 · Filter by author mkorbel1 opened on Jan 2, 2025

• Add testing for async reset (and async triggers in general)

  enhancement
  intel/rohd-cosim#38 · Filter by author mkorbel1 opened on Jan 2, 2025

• Add ability to configure build and sim arguments at connection time

  enhancement
  intel/rohd-cosim#26 · Filter by author mkorbel1 opened on Feb 28, 2023

• Resolve race condition in RohdConnector during interactive debug and SV timeout

  bug
  intel/rohd-cosim#15 · Filter by author mkorbel1 opened on Feb 8, 2023

• Add indication in RohdConnector when a failure was encountered

  intel/rohd-cosim#14 · Filter by author mkorbel1 opened on Feb 8, 2023

• Add testing that SV # delays are properly handled

  enhancement
  intel/rohd-cosim#13 · Filter by author mkorbel1 opened on Feb 8, 2023

• Add more extensive testing that throwOnUnexpectedEnd works with PortConfig

  enhancement
  intel/rohd-cosim#12 · Filter by author mkorbel1 opened on Feb 8, 2023

• Add a PortConfig test where the process crashes before Simulator.run

  enhancementgood first issue
  intel/rohd-cosim#11 · Filter by author mkorbel1 opened on Feb 8, 2023

• Add testing for 0-width input and output ports

  intel/rohd-cosim#9 · Filter by author mkorbel1 opened on Feb 8, 2023

• Don't send more ticks than necessary

  enhancement
  intel/rohd-cosim#8 · Filter by author mkorbel1 opened on Feb 8, 2023

• Add a test covering scenarios with multiple SV simulator ticks per timestamp

  enhancement
  intel/rohd-cosim#7 · Filter by author mkorbel1 opened on Feb 8, 2023

• Add testing for clock-divider logic with cosimulation

  enhancement
  intel/rohd-cosim#6 · Filter by author mkorbel1 opened on Feb 7, 2023

• Listeners linger after simulations end

  bughelp wanted
  intel/rohd-cosim#5 · Filter by author mkorbel1 opened on Feb 7, 2023

• Add more types of arguments for Cosim Modules

  enhancementhelp wanted
  intel/rohd-cosim#4 · Filter by author mkorbel1 opened on Feb 7, 2023

• Build an annotation-based cosim-wrapper code generator

  enhancement
  intel/rohd-cosim#3 · Filter by author mkorbel1 opened on Feb 7, 2023

• Enable cosim access to hierarchically reference signals in SystemVerilog modules and submodules

  enhancement
  intel/rohd-cosim#2 · Filter by author mkorbel1 opened on Feb 7, 2023

• Use typing for cosim messages

  enhancementhelp wanted
  intel/rohd-cosim#1 · Filter by author mkorbel1 opened on Feb 7, 2023