diff --git a/cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_enga_application.h b/cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_application.h similarity index 98% rename from cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_enga_application.h rename to cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_application.h index 8aec57b..75baba7 100644 --- a/cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_enga_application.h +++ b/cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_application.h @@ -31,8 +31,8 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef NRFX_IRQS_NRF54LM20A_ENGA_APPLICATION_H__ -#define NRFX_IRQS_NRF54LM20A_ENGA_APPLICATION_H__ +#ifndef NRFX_IRQS_NRF54LM20A_APPLICATION_H__ +#define NRFX_IRQS_NRF54LM20A_APPLICATION_H__ #include "drivers/nrfx_utils.h" @@ -255,4 +255,4 @@ extern "C" { } #endif -#endif // NRFX_IRQS_NRF54LM20A_ENGA_APPLICATION_H___ +#endif // NRFX_IRQS_NRF54LM20A_APPLICATION_H___ diff --git a/cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_enga_flpr.h b/cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_flpr.h similarity index 98% rename from cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_enga_flpr.h rename to cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_flpr.h index e0d863b..f9c31c6 100644 --- a/cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_enga_flpr.h +++ b/cores/nRF5/nordic/nrfx/bsp/stable/soc/irqs/nrfx_irqs_nrf54lm20a_flpr.h @@ -31,8 +31,8 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef NRFX_IRQS_NRF54LM20A_ENGA_FLPR_H__ -#define NRFX_IRQS_NRF54LM20A_ENGA_FLPR_H__ +#ifndef NRFX_IRQS_NRF54LM20A_FLPR_H__ +#define NRFX_IRQS_NRF54LM20A_FLPR_H__ #include "drivers/nrfx_utils.h" @@ -343,4 +343,4 @@ extern "C" { } #endif -#endif // NRFX_IRQS_NRF54LM20A_ENGA_FLPR_H___ +#endif // NRFX_IRQS_NRF54LM20A_FLPR_H___ diff --git a/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_irqs.h b/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_irqs.h index be44d06..b5152b1 100644 --- a/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_irqs.h +++ b/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_irqs.h @@ -74,10 +74,10 @@ #include "soc/irqs/nrfx_irqs_nrf54l15_application.h" #elif defined(NRF54L15_XXAA) && defined(NRF_FLPR) #include "soc/irqs/nrfx_irqs_nrf54l15_flpr.h" -#elif defined(NRF54LM20A_ENGA_XXAA) && defined(NRF_APPLICATION) - #include "soc/irqs/nrfx_irqs_nrf54lm20a_enga_application.h" -#elif defined(NRF54LM20A_ENGA_XXAA) && defined(NRF_FLPR) - #include "soc/irqs/nrfx_irqs_nrf54lm20a_enga_flpr.h" +#elif defined(NRF54LM20A_XXAA) && defined(NRF_APPLICATION) + #include "soc/irqs/nrfx_irqs_nrf54lm20a_application.h" +#elif defined(NRF54LM20A_XXAA) && defined(NRF_FLPR) + #include "soc/irqs/nrfx_irqs_nrf54lm20a_flpr.h" #elif defined(NRF54LS05B_ENGA_XXAA) && defined(NRF_APPLICATION) #include "soc/irqs/nrfx_irqs_nrf54ls05b_enga_application.h" #elif defined(NRF54LV10A_ENGA_XXAA) && defined(NRF_APPLICATION) diff --git a/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_mdk_fixups.h b/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_mdk_fixups.h index f8e0a2a..ccf218c 100644 --- a/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_mdk_fixups.h +++ b/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_mdk_fixups.h @@ -549,17 +549,17 @@ /**************************************************************************************************/ /**************************************************************************************************/ -/* Start fixups section for NRF54LM20A_ENGA_XXAA */ +/* Start fixups section for NRF54LM20A_XXAA */ /**************************************************************************************************/ -#if defined(NRF54LM20A_ENGA_XXAA) - #include "mdk/nrf54lm20a_enga_interim.h" +#if defined(NRF54LM20A_XXAA) + #include "mdk/nrf54lm20a_interim.h" #define TRNG_CLK_DIV 1 #define I2S_MCKFREQ_FACTOR 1048576 #endif /**************************************************************************************************/ -/* End fixups section for NRF54LM20A_ENGA_XXAA */ +/* End fixups section for NRF54LM20A_XXAA */ /**************************************************************************************************/ /**************************************************************************************************/ diff --git a/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_soc_defines.h b/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_soc_defines.h index 4db20a2..8a094ac 100644 --- a/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_soc_defines.h +++ b/cores/nRF5/nordic/nrfx/bsp/stable/soc/nrfx_soc_defines.h @@ -72,7 +72,7 @@ extern "C" { NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(13U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(14U, 1) -#elif defined(NRF54LM20A_ENGA_XXAA) +#elif defined(NRF54LM20A_XXAA) #define COMP_EXTERNAL_AIN_PSELS \ NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(31U, 1), \ @@ -151,7 +151,7 @@ extern "C" { NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(13U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(14U, 1), -#elif defined(NRF54LM20A_ENGA_XXAA) +#elif defined(NRF54LM20A_XXAA) #define COMP_EXTERNAL_REF_PSELS \ NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(31U, 1), \ @@ -230,7 +230,7 @@ extern "C" { NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(13U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(14U, 1), -#elif defined(NRF54LM20A_ENGA_XXAA) +#elif defined(NRF54LM20A_XXAA) #define LPCOMP_EXTERNAL_AIN_PSELS \ NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(31U, 1), \ @@ -305,7 +305,7 @@ extern "C" { NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(13U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(14U, 1), -#elif defined(NRF54LM20A_ENGA_XXAA) +#elif defined(NRF54LM20A_XXAA) #define LPCOMP_EXTERNAL_REF_PSELS \ NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(31U, 1), \ @@ -380,7 +380,7 @@ extern "C" { NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(13U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(14U, 1), -#elif defined(NRF54LM20A_ENGA_XXAA) +#elif defined(NRF54LM20A_XXAA) #define SAADC_EXTERNAL_AIN_PSELS \ NRF_PIN_PORT_TO_PIN_NUMBER(0U, 1), \ NRF_PIN_PORT_TO_PIN_NUMBER(31U, 1), \ @@ -454,7 +454,7 @@ extern "C" { NRF_SAADC_INPUT_AVDD, \ NRFX_COND_CODE_1(NRFX_ARG_HAS_PARENTHESIS(NRF_SAADC_INPUT_DVDD), \ (NRF_SAADC_INPUT_DVDD,), (NRFX_SAADC_INPUT_NOT_PRESENT,)) -#elif defined(NRF54LM20A_ENGA_XXAA) +#elif defined(NRF54LM20A_XXAA) #define SAADC_INTERNAL_AIN_PSELS \ NRF_SAADC_INPUT_VDD, \ NRFX_SAADC_INPUT_NOT_PRESENT, \ @@ -608,7 +608,7 @@ extern "C" { #define RAM_UNIFORM_BLOCKS 1 #define RAM_UNIFORM_SECTIONS_PER_BLOCK 8 #define RAM_UNIFORM_SECTIONS_TOTAL 8 -#elif defined(NRF54LM20A_ENGA_XXAA) +#elif defined(NRF54LM20A_XXAA) #define RAM_SECTION_UNIT_SIZE (32UL * 1024UL) #define RAM_UNIFORM_BLOCKS 1 #define RAM_UNIFORM_SECTIONS_PER_BLOCK 16 @@ -718,7 +718,7 @@ extern "C" { #define NRFX_PRS_BOX_4_ADDR NRF_UARTE30 // COMP, LPCOMP #define NRFX_PRS_BOX_5_ADDR NRF_COMP -#elif defined(NRF54LM20A_ENGA_XXAA) +#elif defined(NRF54LM20A_XXAA) // SPIM00, SPIS00, UARTE00 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE00 // SPIM20, SPIS20, TWIM20, TWIS20, UARTE20 diff --git a/cores/nRF5/nordic/nrfx/mdk/compiler_abstraction.h b/cores/nRF5/nordic/nrfx/mdk/compiler_abstraction.h index 8c1ebf2..4de4c3d 100644 --- a/cores/nRF5/nordic/nrfx/mdk/compiler_abstraction.h +++ b/cores/nRF5/nordic/nrfx/mdk/compiler_abstraction.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf.h b/cores/nRF5/nordic/nrfx/mdk/nrf.h index 2953c8e..044a31a 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -37,9 +37,12 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 73 -#define MDK_MICRO_VERSION 2 +#define MDK_MINOR_VERSION 75 +#define MDK_MICRO_VERSION 1 +#ifdef __ZEPHYR__ +#include +#endif /* Define coprocessor domains */ #if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK) @@ -124,7 +127,7 @@ POSSIBILITY OF SUCH DAMAGE. #endif /* Define NRF54L_SERIES for common use in nRF54L series devices */ -#if defined (NRF54L05_XXAA) || defined (NRF54LV10A_ENGA_XXAA) || defined (NRF54L10_XXAA) || defined (NRF54L15_XXAA) || defined (NRF54LM20A_ENGA_XXAA) || defined (NRF54LS05B_ENGA_XXAA) +#if defined (NRF54L05_XXAA) || defined (NRF54LV10A_XXAA) || defined (NRF54L10_XXAA) || defined (NRF54L15_XXAA) || defined (NRF54LM20A_XXAA) || defined (NRF54LM20B_XXAA) || defined (NRF54LS05B_XXAA) || defined (NRF54LC10A_XXAA) || defined (NRF54LS05A_XXAA) #ifndef NRF54L_SERIES #define NRF54L_SERIES #endif @@ -151,7 +154,7 @@ POSSIBILITY OF SUCH DAMAGE. #endif /* Define NRF92_SERIES for common use in nRF92 series devices. */ -#if defined(NRF9230_ENGB_XXAA) +#if defined(NRF9230_ENGB_XXAA) || defined (NRF9220_XXAA) #ifndef NRF92_SERIES #define NRF92_SERIES #endif @@ -234,10 +237,10 @@ POSSIBILITY OF SUCH DAMAGE. #include "nrf54l05_interim.h" #include "nrf54l05_name_change.h" -#elif defined (NRF54LV10A_ENGA_XXAA) - #include "nrf54lv10a_enga.h" - #include "nrf54lv10a_enga_interim.h" - #include "nrf54lv10a_enga_name_change.h" +#elif defined (NRF54LV10A_XXAA) + #include "nrf54lv10a.h" + #include "nrf54lv10a_interim.h" + #include "nrf54lv10a_name_change.h" #elif defined (NRF54L10_XXAA) #include "nrf54l10.h" @@ -249,15 +252,20 @@ POSSIBILITY OF SUCH DAMAGE. #include "nrf54l15_interim.h" #include "nrf54l15_name_change.h" -#elif defined (NRF54LM20A_ENGA_XXAA) - #include "nrf54lm20a_enga.h" - #include "nrf54lm20a_enga_interim.h" - #include "nrf54lm20a_enga_name_change.h" +#elif defined (NRF54LM20A_XXAA) + #include "nrf54lm20a.h" + #include "nrf54lm20a_interim.h" + #include "nrf54lm20a_name_change.h" + +#elif defined (NRF54LM20B_XXAA) + #include "nrf54lm20b.h" + #include "nrf54lm20b_interim.h" + #include "nrf54lm20b_name_change.h" -#elif defined (NRF54LS05B_ENGA_XXAA) - #include "nrf54ls05b_enga.h" - #include "nrf54ls05b_enga_interim.h" - #include "nrf54ls05b_enga_name_change.h" +#elif defined (NRF54LS05B_XXAA) + #include "nrf54ls05b.h" + #include "nrf54ls05b_interim.h" + #include "nrf54ls05b_name_change.h" #elif defined (NRF7120_ENGA_XXAA) #include "nrf7120_enga.h" @@ -291,6 +299,22 @@ POSSIBILITY OF SUCH DAMAGE. #include "nrf9230_engb_interim.h" #include "nrf9230_engb_name_change.h" +#elif defined (NRF54LC10A_XXAA) + #include "nrf54lc10a.h" + #include "nrf54lc10a_interim.h" + #include "nrf54lc10a_name_change.h" + +#elif defined (NRF54LS05A_XXAA) + #include "nrf54ls05a.h" + #include "nrf54ls05a_interim.h" + #include "nrf54ls05a_name_change.h" + +#elif defined (NRF9220_XXAA) + #include "nrf9220.h" + #include "nrf9220_interim.h" + #include "nrf9220_name_change.h" + +/* Ending device selection for device includes. */ #else #error "Device must be defined. See nrf.h." #endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05.h index 6909658..766802c 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_application.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_application.h index 38e3c39..a037d86 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_application.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_application.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_application_peripherals.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_application_peripherals.h index 02d6ccf..af96f66 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_application_peripherals.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_application_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -528,6 +528,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */ #define UARTE00_CORE_CLOCK_128 1 /*!< (unspecified) */ #define UARTE00_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE00_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -538,6 +539,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE20_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE20_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE20_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -548,6 +550,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE21_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE21_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE21_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -558,6 +561,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE22_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE22_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE22_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -568,6 +572,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE30_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE30_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE30_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ /*Voltage glitch detectors*/ @@ -897,6 +902,10 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_IRQ_COUNT 2 #define RADIO_WHITENINGPOLY 1 /*!< (unspecified) */ +#define RADIO_IEEE802154 1 /*!< IEEE 802.15.4 support */ +#define RADIO_LONGRANGE 1 /*!< Long range (LE Coded PHY) support */ +#define RADIO_DIRECTIONFINDING 1 /*!< Direction finding support (DFE) */ +#define RADIO_CHANNELSOUNDING 1 /*!< Channel sounding support (CSTONES) */ #define RADIO_ADPLLCOMPANION_INCLUDE_DMA 0 /*!< No internal instantiation of DmaChannelPeripheral */ /*I2C compatible Two-Wire Master Interface with EasyDMA*/ @@ -906,21 +915,25 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define TWIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define TWIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define TWIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ @@ -1014,7 +1027,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_TCONV_VALUE_RANGE_MIN 1 /*!< (unspecified) */ #define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ #define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ -#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< CURRENTAMOUNT register not included. */ +#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< CURRENTAMOUNT register included. */ /*NFC-A compatible radio NFC-A compatible radio*/ #define NFCT_PRESENT 1 @@ -1058,6 +1071,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TAMPC_PRESENT 1 #define TAMPC_COUNT 1 +#define TAMPC_GPIOSWD 0 /*!< (unspecified) */ #define TAMPC_APSPIDEN 0 /*!< (unspecified) */ #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 1 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 1 */ #define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_flpr.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_flpr.h index bb6f621..ce8ecf3 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_flpr.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_flpr.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_global.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_global.h index 63025b1..99dbeb4 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_global.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_global.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -101,6 +101,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_RRAMC_S_BASE 0x5004B000UL #define NRF_VPR00_NS_BASE 0x4004C000UL #define NRF_VPR00_S_BASE 0x5004C000UL +#define NRF_GPIOHSPADCTRL_NS_BASE 0x40050400UL #define NRF_P2_NS_BASE 0x40050400UL #define NRF_GPIOHSPADCTRL_S_BASE 0x50050400UL #define NRF_P2_S_BASE 0x50050400UL @@ -276,6 +277,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_RRAMC_S ((NRF_RRAMC_Type*) NRF_RRAMC_S_BASE) #define NRF_VPR00_NS ((NRF_VPR_Type*) NRF_VPR00_NS_BASE) #define NRF_VPR00_S ((NRF_VPR_Type*) NRF_VPR00_S_BASE) +#define NRF_GPIOHSPADCTRL_NS ((NRF_GPIOHSPADCTRL_Type*) NRF_GPIOHSPADCTRL_NS_BASE) #define NRF_P2_NS ((NRF_GPIO_Type*) NRF_P2_NS_BASE) #define NRF_GPIOHSPADCTRL_S ((NRF_GPIOHSPADCTRL_Type*) NRF_GPIOHSPADCTRL_S_BASE) #define NRF_P2_S ((NRF_GPIO_Type*) NRF_P2_S_BASE) @@ -433,6 +435,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_SPIS00 NRF_SPIS00_NS #define NRF_UARTE00 NRF_UARTE00_NS #define NRF_VPR00 NRF_VPR00_NS + #define NRF_GPIOHSPADCTRL NRF_GPIOHSPADCTRL_NS #define NRF_P2 NRF_P2_NS #define NRF_CTRLAP NRF_CTRLAP_NS #define NRF_TAD NRF_TAD_NS diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_interim.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_interim.h index 39af73c..a5210a4 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_interim.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_interim.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_name_change.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_name_change.h index 0bc4e6d..d182549 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_name_change.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_name_change.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_peripherals.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_peripherals.h index ddd9232..31733f0 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_peripherals.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_types.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_types.h index df8b516..0686d3e 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_types.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_types.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -12223,8 +12223,8 @@ typedef struct { #define GPIO_PIN_CNF_PULL_Min (0x0UL) /*!< Min enumerator value of PULL field. */ #define GPIO_PIN_CNF_PULL_Max (0x3UL) /*!< Max enumerator value of PULL field. */ #define GPIO_PIN_CNF_PULL_Disabled (0x0UL) /*!< No pull */ - #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull down on pin */ - #define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull up on pin */ + #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull-down on pin */ + #define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull-up on pin */ /* DRIVE0 @Bits 8..9 : Drive configuration for '0' */ #define GPIO_PIN_CNF_DRIVE0_Pos (8UL) /*!< Position of DRIVE0 field. */ @@ -12287,7 +12287,7 @@ typedef struct { /* GPIOHSPADCTRL_BIAS: Bias control */ #define GPIOHSPADCTRL_BIAS_ResetValue (0x00000000UL) /*!< Reset value of BIAS register. */ -/* HSBIAS @Bits 0..1 : Slew setting for high-speed pad (higher value is faster) */ +/* HSBIAS @Bits 0..1 : Slew setting for high-speed pad (Use highest/fastest value) */ #define GPIOHSPADCTRL_BIAS_HSBIAS_Pos (0UL) /*!< Position of HSBIAS field. */ #define GPIOHSPADCTRL_BIAS_HSBIAS_Msk (0x3UL << GPIOHSPADCTRL_BIAS_HSBIAS_Pos) /*!< Bit mask of HSBIAS field. */ #define GPIOHSPADCTRL_BIAS_HSBIAS_Min (0x0UL) /*!< Min value of HSBIAS field. */ @@ -24054,30 +24054,22 @@ typedef struct { * @brief AUXDATA [RADIO_AUXDATA] (unspecified) */ typedef struct { - __IOM uint32_t CNF[2]; /*!< (@ 0x00000000) AUXDATA configuration */ -} NRF_RADIO_AUXDATA_Type; /*!< Size = 8 (0x008) */ + __IOM uint32_t CNF[1]; /*!< (@ 0x00000000) AUXDATA configuration */ +} NRF_RADIO_AUXDATA_Type; /*!< Size = 4 (0x004) */ /* RADIO_AUXDATA_CNF: AUXDATA configuration */ - #define RADIO_AUXDATA_CNF_MaxCount (2UL) /*!< Max size of CNF[2] array. */ - #define RADIO_AUXDATA_CNF_MaxIndex (1UL) /*!< Max index of CNF[2] array. */ - #define RADIO_AUXDATA_CNF_MinIndex (0UL) /*!< Min index of CNF[2] array. */ - #define RADIO_AUXDATA_CNF_ResetValue (0x00000000UL) /*!< Reset value of CNF[2] register. */ + #define RADIO_AUXDATA_CNF_MaxCount (1UL) /*!< Max size of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_MaxIndex (0UL) /*!< Max index of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_MinIndex (0UL) /*!< Min index of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_ResetValue (0x00000000UL) /*!< Reset value of CNF[1] register. */ -/* ACQMODE @Bits 0..4 : Acquisition mode (data from RADIO written to memory) */ +/* ACQMODE @Bits 0..4 : Acquisition mode */ #define RADIO_AUXDATA_CNF_ACQMODE_Pos (0UL) /*!< Position of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Msk (0x1FUL << RADIO_AUXDATA_CNF_ACQMODE_Pos) /*!< Bit mask of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Min (0x07UL) /*!< Min enumerator value of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Max (0x07UL) /*!< Max enumerator value of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Rtt (0x07UL) /*!< Baseband Channel Sounding RTT Data */ -/* DIR @Bit 31 : Data acquisition or injection */ - #define RADIO_AUXDATA_CNF_DIR_Pos (31UL) /*!< Position of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Msk (0x1UL << RADIO_AUXDATA_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Min (0x0UL) /*!< Min enumerator value of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Max (0x1UL) /*!< Max enumerator value of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Acq (0x0UL) /*!< Peripheral to memory */ - #define RADIO_AUXDATA_CNF_DIR_Inj (0x1UL) /*!< Memory to peripheral */ - /* ================================================= Struct RADIO_AUXDATADMA ================================================= */ @@ -24091,9 +24083,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of 32-bit words transferred in the last transaction*/ } NRF_RADIO_AUXDATADMA_Type; /*!< Size = 16 (0x010) */ - #define RADIO_AUXDATADMA_MaxCount (2UL) /*!< Size of AUXDATADMA[2] array. */ - #define RADIO_AUXDATADMA_MaxIndex (1UL) /*!< Max index of AUXDATADMA[2] array. */ - #define RADIO_AUXDATADMA_MinIndex (0UL) /*!< Min index of AUXDATADMA[2] array. */ + #define RADIO_AUXDATADMA_MaxCount (1UL) /*!< Size of AUXDATADMA[1] array. */ + #define RADIO_AUXDATADMA_MaxIndex (0UL) /*!< Max index of AUXDATADMA[1] array. */ + #define RADIO_AUXDATADMA_MinIndex (0UL) /*!< Min index of AUXDATADMA[1] array. */ /* RADIO_AUXDATADMA_ENABLE: Enable or disable data acquisition */ #define RADIO_AUXDATADMA_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ @@ -24443,7 +24435,7 @@ typedef struct { /* RADIO_RTT_CONFIG: RTT Config. */ #define RADIO_RTT_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ -/* EN @Bit 0 : Enable RTT Functionality. Only valid for BLE 1MBPS and 2MBPS mode */ +/* EN @Bit 0 : Enable RTT functionality. Only valid for BLE 1MBPS and 2MBPS mode */ #define RADIO_RTT_CONFIG_EN_Pos (0UL) /*!< Position of EN field. */ #define RADIO_RTT_CONFIG_EN_Msk (0x1UL << RADIO_RTT_CONFIG_EN_Pos) /*!< Bit mask of EN field. */ #define RADIO_RTT_CONFIG_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ @@ -24473,7 +24465,7 @@ typedef struct { #define RADIO_RTT_CONFIG_NUMSEGMENTS_Msk (0xFUL << RADIO_RTT_CONFIG_NUMSEGMENTS_Pos) /*!< Bit mask of NUMSEGMENTS field. */ /* EFSDELAY @Bits 8..16 : Early Frame Sync Delay, i.e., number of cycles to wait for access address to anchor correctly. For - 2MBPSBLE mode, the EFSDELAY value is 64 (2us) and for 1MBPSBLE mode, it can be 256 (8us). */ + Ble_2Mbit, the EFSDELAY value is 64 (2us) and for Ble_1Mbit, it can be 256 (8us). */ #define RADIO_RTT_CONFIG_EFSDELAY_Pos (8UL) /*!< Position of EFSDELAY field. */ #define RADIO_RTT_CONFIG_EFSDELAY_Msk (0x1FFUL << RADIO_RTT_CONFIG_EFSDELAY_Pos) /*!< Bit mask of EFSDELAY field. */ @@ -24657,44 +24649,45 @@ typedef struct { __IOM uint32_t DATAWHITE; /*!< (@ 0x00000540) Data whitening configuration */ __IM uint32_t RESERVED25; __IOM NRF_RADIO_AUXDATA_Type AUXDATA; /*!< (@ 0x00000548) (unspecified) */ - __IOM NRF_RADIO_AUXDATADMA_Type AUXDATADMA[2]; /*!< (@ 0x00000550) (unspecified) */ - __IM uint32_t RESERVED26[101]; + __IM uint32_t RESERVED26; + __IOM NRF_RADIO_AUXDATADMA_Type AUXDATADMA[1]; /*!< (@ 0x00000550) (unspecified) */ + __IM uint32_t RESERVED27[105]; __IOM uint32_t TIMING; /*!< (@ 0x00000704) Timing */ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000708) Frequency */ - __IM uint32_t RESERVED27; + __IM uint32_t RESERVED28; __IOM uint32_t TXPOWER; /*!< (@ 0x00000710) Output power */ __IOM uint32_t TIFS; /*!< (@ 0x00000714) Interframe spacing in us */ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000718) RSSI sample */ - __IM uint32_t RESERVED28[45]; + __IM uint32_t RESERVED29[45]; __IOM NRF_RADIO_RXGAIN_Type RXGAIN; /*!< (@ 0x000007D0) (unspecified) */ - __IM uint32_t RESERVED29[11]; + __IM uint32_t RESERVED30[11]; __IOM uint32_t FREQFINETUNE; /*!< (@ 0x00000804) Fine tuning of the RF frequency */ - __IM uint32_t RESERVED30[64]; + __IM uint32_t RESERVED31[64]; __IOM uint32_t FECONFIG; /*!< (@ 0x00000908) Config register */ - __IM uint32_t RESERVED31[125]; + __IM uint32_t RESERVED32[125]; __IM uint32_t CFO_STAT; /*!< (@ 0x00000B00) Carrier freq. offset estimate */ - __IM uint32_t RESERVED32[15]; + __IM uint32_t RESERVED33[15]; __IOM uint32_t DBCCORR; /*!< (@ 0x00000B40) Correlator thresholds */ - __IM uint32_t RESERVED33[111]; + __IM uint32_t RESERVED34[111]; __IOM uint32_t DFEMODE; /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)*/ __IM uint32_t DFESTATUS; /*!< (@ 0x00000D04) DFE status information */ - __IM uint32_t RESERVED34[2]; + __IM uint32_t RESERVED35[2]; __IOM uint32_t DFECTRL1; /*!< (@ 0x00000D10) Various configuration for Direction finding */ __IOM uint32_t DFECTRL2; /*!< (@ 0x00000D14) Start offset for Direction finding */ - __IM uint32_t RESERVED35[4]; + __IM uint32_t RESERVED36[4]; __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna */ __OM uint32_t CLEARPATTERN; /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control */ __IOM NRF_RADIO_PSEL_Type PSEL; /*!< (@ 0x00000D30) (unspecified) */ __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000D50) DFE packet EasyDMA channel */ - __IM uint32_t RESERVED36[43]; + __IM uint32_t RESERVED37[43]; __IM uint32_t CRCSTATUS; /*!< (@ 0x00000E0C) CRC status */ __IM uint32_t RXMATCH; /*!< (@ 0x00000E10) Received address */ __IM uint32_t RXCRC; /*!< (@ 0x00000E14) CRC field of previously received packet */ __IM uint32_t DAI; /*!< (@ 0x00000E18) Device address match index */ __IM uint32_t PDUSTAT; /*!< (@ 0x00000E1C) Payload status */ __IOM uint32_t PCNF0; /*!< (@ 0x00000E20) Packet configuration register 0 */ - __IM uint32_t RESERVED37; + __IM uint32_t RESERVED38; __IOM uint32_t PCNF1; /*!< (@ 0x00000E28) Packet configuration register 1 */ __IOM uint32_t BASE0; /*!< (@ 0x00000E2C) Base address 0 */ __IOM uint32_t BASE1; /*!< (@ 0x00000E30) Base address 1 */ @@ -24709,18 +24702,18 @@ typedef struct { __IOM uint32_t DAP[8]; /*!< (@ 0x00000E70) Device address prefix n */ __IOM uint32_t DACNF; /*!< (@ 0x00000E90) Device address match configuration */ __IOM uint32_t BCC; /*!< (@ 0x00000E94) Bit counter compare */ - __IM uint32_t RESERVED38[3]; - __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ __IM uint32_t RESERVED39[3]; + __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ + __IM uint32_t RESERVED40[3]; __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000EB4) Search pattern configuration */ __IOM uint32_t MHRMATCHMASK; /*!< (@ 0x00000EB8) Pattern mask */ __IOM uint32_t SFD; /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter */ __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000EC0) Configuration for CTE inline mode */ - __IM uint32_t RESERVED40[3]; + __IM uint32_t RESERVED41[3]; __IOM uint32_t PACKETPTR; /*!< (@ 0x00000ED0) Packet pointer */ - __IM uint32_t RESERVED41[75]; + __IM uint32_t RESERVED42[75]; __IOM NRF_RADIO_CSTONES_Type CSTONES; /*!< (@ 0x00001000) (unspecified) */ - __IM uint32_t RESERVED42[2]; + __IM uint32_t RESERVED43[2]; __IOM NRF_RADIO_RTT_Type RTT; /*!< (@ 0x00001050) (unspecified) */ } NRF_RADIO_Type; /*!< Size = 4196 (0x1064) */ @@ -26129,6 +26122,14 @@ typedef struct { #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0x0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (0x1UL) /*!< Enable shortcut */ +/* PHYEND_PLLEN @Bit 7 : Shortcut between event PHYEND and task PLLEN */ + #define RADIO_SHORTS_PHYEND_PLLEN_Pos (7UL) /*!< Position of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Msk (0x1UL << RADIO_SHORTS_PHYEND_PLLEN_Pos) /*!< Bit mask of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Min (0x0UL) /*!< Min enumerator value of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Max (0x1UL) /*!< Max enumerator value of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PHYEND_PLLEN_Enabled (0x1UL) /*!< Enable shortcut */ + /* RXREADY_CCASTART @Bit 10 : Shortcut between event RXREADY and task CCASTART */ #define RADIO_SHORTS_RXREADY_CCASTART_Pos (10UL) /*!< Position of RXREADY_CCASTART field. */ #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART @@ -26219,6 +26220,22 @@ typedef struct { #define RADIO_SHORTS_PHYEND_START_Disabled (0x0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_PHYEND_START_Enabled (0x1UL) /*!< Enable shortcut */ +/* PLLREADY_TXEN @Bit 27 : Shortcut between event PLLREADY and task TXEN */ + #define RADIO_SHORTS_PLLREADY_TXEN_Pos (27UL) /*!< Position of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Msk (0x1UL << RADIO_SHORTS_PLLREADY_TXEN_Pos) /*!< Bit mask of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Min (0x0UL) /*!< Min enumerator value of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Max (0x1UL) /*!< Max enumerator value of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PLLREADY_TXEN_Enabled (0x1UL) /*!< Enable shortcut */ + +/* PLLREADY_RXEN @Bit 28 : Shortcut between event PLLREADY and task RXEN */ + #define RADIO_SHORTS_PLLREADY_RXEN_Pos (28UL) /*!< Position of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Msk (0x1UL << RADIO_SHORTS_PLLREADY_RXEN_Pos) /*!< Bit mask of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Min (0x0UL) /*!< Min enumerator value of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Max (0x1UL) /*!< Max enumerator value of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PLLREADY_RXEN_Enabled (0x1UL) /*!< Enable shortcut */ + /* RADIO_INTENSET00: Enable interrupt */ #define RADIO_INTENSET00_ResetValue (0x00000000UL) /*!< Reset value of INTENSET00 register. */ @@ -27260,8 +27277,8 @@ typedef struct { #define RADIO_PHYENDTXDELAY_RATE2M_Pos (4UL) /*!< Position of RATE2M field. */ #define RADIO_PHYENDTXDELAY_RATE2M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE2M_Pos) /*!< Bit mask of RATE2M field. */ -/* RATE1M @Bits 8..10 : For modes with 1 Mbps on-air bit rate, unit is 1/2 bit period (Nrf_1Mbit, Ble_1Mbit, Ble_LR125Kbit, and - Ble_LR500Kbit modes) */ +/* RATE1M @Bits 8..10 : For modes with 1 Mbps on-air bit rate, unit is 1/2 bit period (Nrf_1Mbit and Ble_1Mbit modes) Also used + for Coded phy (Ble_LR125Kbit and Ble_LR500Kbit modes) */ #define RADIO_PHYENDTXDELAY_RATE1M_Pos (8UL) /*!< Position of RATE1M field. */ #define RADIO_PHYENDTXDELAY_RATE1M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE1M_Pos) /*!< Bit mask of RATE1M field. */ @@ -27284,6 +27301,8 @@ typedef struct { #define RADIO_STATE_STATE_RxIdle (0x2UL) /*!< RADIO is in the RXIDLE state */ #define RADIO_STATE_STATE_Rx (0x3UL) /*!< RADIO is in the RX state */ #define RADIO_STATE_STATE_RxDisable (0x4UL) /*!< RADIO is in the RXDISABLE state */ + #define RADIO_STATE_STATE_Settle (0x5UL) /*!< RADIO is in the SETTLE state */ + #define RADIO_STATE_STATE_Pll (0x6UL) /*!< RADIO is in the PLL state */ #define RADIO_STATE_STATE_TxRu (0x9UL) /*!< RADIO is in the TXRU state */ #define RADIO_STATE_STATE_TxIdle (0xAUL) /*!< RADIO is in the TXIDLE state */ #define RADIO_STATE_STATE_Tx (0xBUL) /*!< RADIO is in the TX state */ @@ -29287,9 +29306,10 @@ typedef struct { #define SAADC_CH_PSELN_CONNECT_Pos (30UL) /*!< Position of CONNECT field. */ #define SAADC_CH_PSELN_CONNECT_Msk (0x3UL << SAADC_CH_PSELN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ #define SAADC_CH_PSELN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ - #define SAADC_CH_PSELN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SAADC_CH_PSELN_CONNECT_Max (0x2UL) /*!< Max enumerator value of CONNECT field. */ #define SAADC_CH_PSELN_CONNECT_NC (0x0UL) /*!< Not connected */ #define SAADC_CH_PSELN_CONNECT_AnalogInput (0x1UL) /*!< Select analog input */ + #define SAADC_CH_PSELN_CONNECT_Internal (0x2UL) /*!< Selects internal inputs. */ /* SAADC_CH_CONFIG: Input configuration for CH[n] */ @@ -32733,7 +32753,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -32772,6 +32794,18 @@ typedef struct { #define SPIS_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* SPIS_DMA_RX_LIST: EasyDMA list type */ + #define SPIS_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIS_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Msk (0x7UL << SPIS_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIS_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* SPIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define SPIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -32806,7 +32840,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -32843,6 +32879,18 @@ typedef struct { #define SPIS_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* SPIS_DMA_TX_LIST: EasyDMA list type */ + #define SPIS_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIS_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Msk (0x7UL << SPIS_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIS_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* SPIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define SPIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -36922,7 +36970,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -36961,6 +37011,18 @@ typedef struct { #define TWIM_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIM_DMA_RX_LIST: EasyDMA list type */ + #define TWIM_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIM_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Msk (0x7UL << TWIM_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIM_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIM_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIM_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -36995,7 +37057,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -37032,6 +37096,18 @@ typedef struct { #define TWIM_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIM_DMA_TX_LIST: EasyDMA list type */ + #define TWIM_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIM_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Msk (0x7UL << TWIM_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIM_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIM_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIM_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -38570,7 +38646,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -38609,6 +38687,18 @@ typedef struct { #define TWIS_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIS_DMA_RX_LIST: EasyDMA list type */ + #define TWIS_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIS_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Msk (0x7UL << TWIS_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIS_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -38643,7 +38733,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -38680,6 +38772,18 @@ typedef struct { #define TWIS_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIS_DMA_TX_LIST: EasyDMA list type */ + #define TWIS_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIS_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Msk (0x7UL << TWIS_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIS_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -39918,7 +40022,7 @@ typedef struct { * @brief RX [UARTE_EVENTS_DMA_RX] Peripheral events. */ typedef struct { - __IOM uint32_t END; /*!< (@ 0x00000000) Generated after EasyDMA has completed its operation. */ + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.*/ @@ -39926,10 +40030,10 @@ typedef struct { __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ } NRF_UARTE_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ -/* UARTE_EVENTS_DMA_RX_END: Generated after EasyDMA has completed its operation. */ +/* UARTE_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ -/* END @Bit 0 : Generated after EasyDMA has completed its operation. */ +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ #define UARTE_EVENTS_DMA_RX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ #define UARTE_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ @@ -39988,17 +40092,17 @@ typedef struct { * @brief TX [UARTE_EVENTS_DMA_TX] Peripheral events. */ typedef struct { - __IOM uint32_t END; /*!< (@ 0x00000000) Generated after EasyDMA has completed its operation. */ + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.*/ __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ } NRF_UARTE_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ -/* UARTE_EVENTS_DMA_TX_END: Generated after EasyDMA has completed its operation. */ +/* UARTE_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ -/* END @Bit 0 : Generated after EasyDMA has completed its operation. */ +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ #define UARTE_EVENTS_DMA_TX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ #define UARTE_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ @@ -40428,7 +40532,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -40467,6 +40573,18 @@ typedef struct { #define UARTE_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* UARTE_DMA_RX_LIST: EasyDMA list type */ + #define UARTE_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define UARTE_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Msk (0x7UL << UARTE_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define UARTE_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* UARTE_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define UARTE_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -40501,7 +40619,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -40538,6 +40658,18 @@ typedef struct { #define UARTE_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* UARTE_DMA_TX_LIST: EasyDMA list type */ + #define UARTE_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define UARTE_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Msk (0x7UL << UARTE_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define UARTE_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* UARTE_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define UARTE_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_version.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_version.h index 48bb915..2517d5e 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_version.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_version.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -40,8 +40,8 @@ POSSIBILITY OF SUCH DAMAGE. #endif -#define MDK_SOURCE_VERSION_MAJOR 0 /*!< Major version of the datasheet. */ -#define MDK_SOURCE_VERSION_MINOR 10a /*!< Minor version of the datasheet. */ +#define MDK_SOURCE_VERSION_MAJOR 1 /*!< Major version of the datasheet. */ +#define MDK_SOURCE_VERSION_MINOR 1 /*!< Minor version of the datasheet. */ #define MDK_SOURCE_VERSION_MICRO 0 /*!< Micro version of the datasheet. */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_xxaa_application_memory.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_xxaa_application_memory.h index 6fdc506..535a62c 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_xxaa_application_memory.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_xxaa_application_memory.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_xxaa_flpr_memory.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_xxaa_flpr_memory.h index e8b3c04..a5afce6 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l05_xxaa_flpr_memory.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l05_xxaa_flpr_memory.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10.h index 534c46f..5d8d79d 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_application.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_application.h index 562d3a4..daabc59 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_application.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_application.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_application_peripherals.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_application_peripherals.h index 8a0cc51..25ee6f0 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_application_peripherals.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_application_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -528,6 +528,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */ #define UARTE00_CORE_CLOCK_128 1 /*!< (unspecified) */ #define UARTE00_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE00_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -538,6 +539,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE20_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE20_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE20_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -548,6 +550,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE21_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE21_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE21_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -558,6 +561,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE22_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE22_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE22_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -568,6 +572,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE30_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE30_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE30_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ /*Voltage glitch detectors*/ @@ -897,6 +902,10 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_IRQ_COUNT 2 #define RADIO_WHITENINGPOLY 1 /*!< (unspecified) */ +#define RADIO_IEEE802154 1 /*!< IEEE 802.15.4 support */ +#define RADIO_LONGRANGE 1 /*!< Long range (LE Coded PHY) support */ +#define RADIO_DIRECTIONFINDING 1 /*!< Direction finding support (DFE) */ +#define RADIO_CHANNELSOUNDING 1 /*!< Channel sounding support (CSTONES) */ #define RADIO_ADPLLCOMPANION_INCLUDE_DMA 0 /*!< No internal instantiation of DmaChannelPeripheral */ /*I2C compatible Two-Wire Master Interface with EasyDMA*/ @@ -906,21 +915,25 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define TWIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define TWIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define TWIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ @@ -1014,7 +1027,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_TCONV_VALUE_RANGE_MIN 1 /*!< (unspecified) */ #define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ #define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ -#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< CURRENTAMOUNT register not included. */ +#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< CURRENTAMOUNT register included. */ /*NFC-A compatible radio NFC-A compatible radio*/ #define NFCT_PRESENT 1 @@ -1058,6 +1071,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TAMPC_PRESENT 1 #define TAMPC_COUNT 1 +#define TAMPC_GPIOSWD 0 /*!< (unspecified) */ #define TAMPC_APSPIDEN 0 /*!< (unspecified) */ #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 1 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 1 */ #define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_flpr.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_flpr.h index f88c913..330ef29 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_flpr.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_flpr.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_global.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_global.h index 58fc895..f48dc48 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_global.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_global.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -101,6 +101,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_RRAMC_S_BASE 0x5004B000UL #define NRF_VPR00_NS_BASE 0x4004C000UL #define NRF_VPR00_S_BASE 0x5004C000UL +#define NRF_GPIOHSPADCTRL_NS_BASE 0x40050400UL #define NRF_P2_NS_BASE 0x40050400UL #define NRF_GPIOHSPADCTRL_S_BASE 0x50050400UL #define NRF_P2_S_BASE 0x50050400UL @@ -276,6 +277,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_RRAMC_S ((NRF_RRAMC_Type*) NRF_RRAMC_S_BASE) #define NRF_VPR00_NS ((NRF_VPR_Type*) NRF_VPR00_NS_BASE) #define NRF_VPR00_S ((NRF_VPR_Type*) NRF_VPR00_S_BASE) +#define NRF_GPIOHSPADCTRL_NS ((NRF_GPIOHSPADCTRL_Type*) NRF_GPIOHSPADCTRL_NS_BASE) #define NRF_P2_NS ((NRF_GPIO_Type*) NRF_P2_NS_BASE) #define NRF_GPIOHSPADCTRL_S ((NRF_GPIOHSPADCTRL_Type*) NRF_GPIOHSPADCTRL_S_BASE) #define NRF_P2_S ((NRF_GPIO_Type*) NRF_P2_S_BASE) @@ -433,6 +435,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_SPIS00 NRF_SPIS00_NS #define NRF_UARTE00 NRF_UARTE00_NS #define NRF_VPR00 NRF_VPR00_NS + #define NRF_GPIOHSPADCTRL NRF_GPIOHSPADCTRL_NS #define NRF_P2 NRF_P2_NS #define NRF_CTRLAP NRF_CTRLAP_NS #define NRF_TAD NRF_TAD_NS diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_interim.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_interim.h index b776fcf..bfc696b 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_interim.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_interim.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_name_change.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_name_change.h index 0e324c9..0edd9e5 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_name_change.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_name_change.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_peripherals.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_peripherals.h index 2e03460..033e89e 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_peripherals.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_types.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_types.h index cf88a92..a7410c2 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_types.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_types.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -12223,8 +12223,8 @@ typedef struct { #define GPIO_PIN_CNF_PULL_Min (0x0UL) /*!< Min enumerator value of PULL field. */ #define GPIO_PIN_CNF_PULL_Max (0x3UL) /*!< Max enumerator value of PULL field. */ #define GPIO_PIN_CNF_PULL_Disabled (0x0UL) /*!< No pull */ - #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull down on pin */ - #define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull up on pin */ + #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull-down on pin */ + #define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull-up on pin */ /* DRIVE0 @Bits 8..9 : Drive configuration for '0' */ #define GPIO_PIN_CNF_DRIVE0_Pos (8UL) /*!< Position of DRIVE0 field. */ @@ -12287,7 +12287,7 @@ typedef struct { /* GPIOHSPADCTRL_BIAS: Bias control */ #define GPIOHSPADCTRL_BIAS_ResetValue (0x00000000UL) /*!< Reset value of BIAS register. */ -/* HSBIAS @Bits 0..1 : Slew setting for high-speed pad (higher value is faster) */ +/* HSBIAS @Bits 0..1 : Slew setting for high-speed pad (Use highest/fastest value) */ #define GPIOHSPADCTRL_BIAS_HSBIAS_Pos (0UL) /*!< Position of HSBIAS field. */ #define GPIOHSPADCTRL_BIAS_HSBIAS_Msk (0x3UL << GPIOHSPADCTRL_BIAS_HSBIAS_Pos) /*!< Bit mask of HSBIAS field. */ #define GPIOHSPADCTRL_BIAS_HSBIAS_Min (0x0UL) /*!< Min value of HSBIAS field. */ @@ -24054,30 +24054,22 @@ typedef struct { * @brief AUXDATA [RADIO_AUXDATA] (unspecified) */ typedef struct { - __IOM uint32_t CNF[2]; /*!< (@ 0x00000000) AUXDATA configuration */ -} NRF_RADIO_AUXDATA_Type; /*!< Size = 8 (0x008) */ + __IOM uint32_t CNF[1]; /*!< (@ 0x00000000) AUXDATA configuration */ +} NRF_RADIO_AUXDATA_Type; /*!< Size = 4 (0x004) */ /* RADIO_AUXDATA_CNF: AUXDATA configuration */ - #define RADIO_AUXDATA_CNF_MaxCount (2UL) /*!< Max size of CNF[2] array. */ - #define RADIO_AUXDATA_CNF_MaxIndex (1UL) /*!< Max index of CNF[2] array. */ - #define RADIO_AUXDATA_CNF_MinIndex (0UL) /*!< Min index of CNF[2] array. */ - #define RADIO_AUXDATA_CNF_ResetValue (0x00000000UL) /*!< Reset value of CNF[2] register. */ + #define RADIO_AUXDATA_CNF_MaxCount (1UL) /*!< Max size of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_MaxIndex (0UL) /*!< Max index of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_MinIndex (0UL) /*!< Min index of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_ResetValue (0x00000000UL) /*!< Reset value of CNF[1] register. */ -/* ACQMODE @Bits 0..4 : Acquisition mode (data from RADIO written to memory) */ +/* ACQMODE @Bits 0..4 : Acquisition mode */ #define RADIO_AUXDATA_CNF_ACQMODE_Pos (0UL) /*!< Position of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Msk (0x1FUL << RADIO_AUXDATA_CNF_ACQMODE_Pos) /*!< Bit mask of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Min (0x07UL) /*!< Min enumerator value of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Max (0x07UL) /*!< Max enumerator value of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Rtt (0x07UL) /*!< Baseband Channel Sounding RTT Data */ -/* DIR @Bit 31 : Data acquisition or injection */ - #define RADIO_AUXDATA_CNF_DIR_Pos (31UL) /*!< Position of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Msk (0x1UL << RADIO_AUXDATA_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Min (0x0UL) /*!< Min enumerator value of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Max (0x1UL) /*!< Max enumerator value of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Acq (0x0UL) /*!< Peripheral to memory */ - #define RADIO_AUXDATA_CNF_DIR_Inj (0x1UL) /*!< Memory to peripheral */ - /* ================================================= Struct RADIO_AUXDATADMA ================================================= */ @@ -24091,9 +24083,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of 32-bit words transferred in the last transaction*/ } NRF_RADIO_AUXDATADMA_Type; /*!< Size = 16 (0x010) */ - #define RADIO_AUXDATADMA_MaxCount (2UL) /*!< Size of AUXDATADMA[2] array. */ - #define RADIO_AUXDATADMA_MaxIndex (1UL) /*!< Max index of AUXDATADMA[2] array. */ - #define RADIO_AUXDATADMA_MinIndex (0UL) /*!< Min index of AUXDATADMA[2] array. */ + #define RADIO_AUXDATADMA_MaxCount (1UL) /*!< Size of AUXDATADMA[1] array. */ + #define RADIO_AUXDATADMA_MaxIndex (0UL) /*!< Max index of AUXDATADMA[1] array. */ + #define RADIO_AUXDATADMA_MinIndex (0UL) /*!< Min index of AUXDATADMA[1] array. */ /* RADIO_AUXDATADMA_ENABLE: Enable or disable data acquisition */ #define RADIO_AUXDATADMA_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ @@ -24443,7 +24435,7 @@ typedef struct { /* RADIO_RTT_CONFIG: RTT Config. */ #define RADIO_RTT_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ -/* EN @Bit 0 : Enable RTT Functionality. Only valid for BLE 1MBPS and 2MBPS mode */ +/* EN @Bit 0 : Enable RTT functionality. Only valid for BLE 1MBPS and 2MBPS mode */ #define RADIO_RTT_CONFIG_EN_Pos (0UL) /*!< Position of EN field. */ #define RADIO_RTT_CONFIG_EN_Msk (0x1UL << RADIO_RTT_CONFIG_EN_Pos) /*!< Bit mask of EN field. */ #define RADIO_RTT_CONFIG_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ @@ -24473,7 +24465,7 @@ typedef struct { #define RADIO_RTT_CONFIG_NUMSEGMENTS_Msk (0xFUL << RADIO_RTT_CONFIG_NUMSEGMENTS_Pos) /*!< Bit mask of NUMSEGMENTS field. */ /* EFSDELAY @Bits 8..16 : Early Frame Sync Delay, i.e., number of cycles to wait for access address to anchor correctly. For - 2MBPSBLE mode, the EFSDELAY value is 64 (2us) and for 1MBPSBLE mode, it can be 256 (8us). */ + Ble_2Mbit, the EFSDELAY value is 64 (2us) and for Ble_1Mbit, it can be 256 (8us). */ #define RADIO_RTT_CONFIG_EFSDELAY_Pos (8UL) /*!< Position of EFSDELAY field. */ #define RADIO_RTT_CONFIG_EFSDELAY_Msk (0x1FFUL << RADIO_RTT_CONFIG_EFSDELAY_Pos) /*!< Bit mask of EFSDELAY field. */ @@ -24657,44 +24649,45 @@ typedef struct { __IOM uint32_t DATAWHITE; /*!< (@ 0x00000540) Data whitening configuration */ __IM uint32_t RESERVED25; __IOM NRF_RADIO_AUXDATA_Type AUXDATA; /*!< (@ 0x00000548) (unspecified) */ - __IOM NRF_RADIO_AUXDATADMA_Type AUXDATADMA[2]; /*!< (@ 0x00000550) (unspecified) */ - __IM uint32_t RESERVED26[101]; + __IM uint32_t RESERVED26; + __IOM NRF_RADIO_AUXDATADMA_Type AUXDATADMA[1]; /*!< (@ 0x00000550) (unspecified) */ + __IM uint32_t RESERVED27[105]; __IOM uint32_t TIMING; /*!< (@ 0x00000704) Timing */ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000708) Frequency */ - __IM uint32_t RESERVED27; + __IM uint32_t RESERVED28; __IOM uint32_t TXPOWER; /*!< (@ 0x00000710) Output power */ __IOM uint32_t TIFS; /*!< (@ 0x00000714) Interframe spacing in us */ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000718) RSSI sample */ - __IM uint32_t RESERVED28[45]; + __IM uint32_t RESERVED29[45]; __IOM NRF_RADIO_RXGAIN_Type RXGAIN; /*!< (@ 0x000007D0) (unspecified) */ - __IM uint32_t RESERVED29[11]; + __IM uint32_t RESERVED30[11]; __IOM uint32_t FREQFINETUNE; /*!< (@ 0x00000804) Fine tuning of the RF frequency */ - __IM uint32_t RESERVED30[64]; + __IM uint32_t RESERVED31[64]; __IOM uint32_t FECONFIG; /*!< (@ 0x00000908) Config register */ - __IM uint32_t RESERVED31[125]; + __IM uint32_t RESERVED32[125]; __IM uint32_t CFO_STAT; /*!< (@ 0x00000B00) Carrier freq. offset estimate */ - __IM uint32_t RESERVED32[15]; + __IM uint32_t RESERVED33[15]; __IOM uint32_t DBCCORR; /*!< (@ 0x00000B40) Correlator thresholds */ - __IM uint32_t RESERVED33[111]; + __IM uint32_t RESERVED34[111]; __IOM uint32_t DFEMODE; /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)*/ __IM uint32_t DFESTATUS; /*!< (@ 0x00000D04) DFE status information */ - __IM uint32_t RESERVED34[2]; + __IM uint32_t RESERVED35[2]; __IOM uint32_t DFECTRL1; /*!< (@ 0x00000D10) Various configuration for Direction finding */ __IOM uint32_t DFECTRL2; /*!< (@ 0x00000D14) Start offset for Direction finding */ - __IM uint32_t RESERVED35[4]; + __IM uint32_t RESERVED36[4]; __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna */ __OM uint32_t CLEARPATTERN; /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control */ __IOM NRF_RADIO_PSEL_Type PSEL; /*!< (@ 0x00000D30) (unspecified) */ __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000D50) DFE packet EasyDMA channel */ - __IM uint32_t RESERVED36[43]; + __IM uint32_t RESERVED37[43]; __IM uint32_t CRCSTATUS; /*!< (@ 0x00000E0C) CRC status */ __IM uint32_t RXMATCH; /*!< (@ 0x00000E10) Received address */ __IM uint32_t RXCRC; /*!< (@ 0x00000E14) CRC field of previously received packet */ __IM uint32_t DAI; /*!< (@ 0x00000E18) Device address match index */ __IM uint32_t PDUSTAT; /*!< (@ 0x00000E1C) Payload status */ __IOM uint32_t PCNF0; /*!< (@ 0x00000E20) Packet configuration register 0 */ - __IM uint32_t RESERVED37; + __IM uint32_t RESERVED38; __IOM uint32_t PCNF1; /*!< (@ 0x00000E28) Packet configuration register 1 */ __IOM uint32_t BASE0; /*!< (@ 0x00000E2C) Base address 0 */ __IOM uint32_t BASE1; /*!< (@ 0x00000E30) Base address 1 */ @@ -24709,18 +24702,18 @@ typedef struct { __IOM uint32_t DAP[8]; /*!< (@ 0x00000E70) Device address prefix n */ __IOM uint32_t DACNF; /*!< (@ 0x00000E90) Device address match configuration */ __IOM uint32_t BCC; /*!< (@ 0x00000E94) Bit counter compare */ - __IM uint32_t RESERVED38[3]; - __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ __IM uint32_t RESERVED39[3]; + __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ + __IM uint32_t RESERVED40[3]; __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000EB4) Search pattern configuration */ __IOM uint32_t MHRMATCHMASK; /*!< (@ 0x00000EB8) Pattern mask */ __IOM uint32_t SFD; /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter */ __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000EC0) Configuration for CTE inline mode */ - __IM uint32_t RESERVED40[3]; + __IM uint32_t RESERVED41[3]; __IOM uint32_t PACKETPTR; /*!< (@ 0x00000ED0) Packet pointer */ - __IM uint32_t RESERVED41[75]; + __IM uint32_t RESERVED42[75]; __IOM NRF_RADIO_CSTONES_Type CSTONES; /*!< (@ 0x00001000) (unspecified) */ - __IM uint32_t RESERVED42[2]; + __IM uint32_t RESERVED43[2]; __IOM NRF_RADIO_RTT_Type RTT; /*!< (@ 0x00001050) (unspecified) */ } NRF_RADIO_Type; /*!< Size = 4196 (0x1064) */ @@ -26129,6 +26122,14 @@ typedef struct { #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0x0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (0x1UL) /*!< Enable shortcut */ +/* PHYEND_PLLEN @Bit 7 : Shortcut between event PHYEND and task PLLEN */ + #define RADIO_SHORTS_PHYEND_PLLEN_Pos (7UL) /*!< Position of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Msk (0x1UL << RADIO_SHORTS_PHYEND_PLLEN_Pos) /*!< Bit mask of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Min (0x0UL) /*!< Min enumerator value of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Max (0x1UL) /*!< Max enumerator value of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PHYEND_PLLEN_Enabled (0x1UL) /*!< Enable shortcut */ + /* RXREADY_CCASTART @Bit 10 : Shortcut between event RXREADY and task CCASTART */ #define RADIO_SHORTS_RXREADY_CCASTART_Pos (10UL) /*!< Position of RXREADY_CCASTART field. */ #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART @@ -26219,6 +26220,22 @@ typedef struct { #define RADIO_SHORTS_PHYEND_START_Disabled (0x0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_PHYEND_START_Enabled (0x1UL) /*!< Enable shortcut */ +/* PLLREADY_TXEN @Bit 27 : Shortcut between event PLLREADY and task TXEN */ + #define RADIO_SHORTS_PLLREADY_TXEN_Pos (27UL) /*!< Position of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Msk (0x1UL << RADIO_SHORTS_PLLREADY_TXEN_Pos) /*!< Bit mask of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Min (0x0UL) /*!< Min enumerator value of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Max (0x1UL) /*!< Max enumerator value of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PLLREADY_TXEN_Enabled (0x1UL) /*!< Enable shortcut */ + +/* PLLREADY_RXEN @Bit 28 : Shortcut between event PLLREADY and task RXEN */ + #define RADIO_SHORTS_PLLREADY_RXEN_Pos (28UL) /*!< Position of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Msk (0x1UL << RADIO_SHORTS_PLLREADY_RXEN_Pos) /*!< Bit mask of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Min (0x0UL) /*!< Min enumerator value of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Max (0x1UL) /*!< Max enumerator value of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PLLREADY_RXEN_Enabled (0x1UL) /*!< Enable shortcut */ + /* RADIO_INTENSET00: Enable interrupt */ #define RADIO_INTENSET00_ResetValue (0x00000000UL) /*!< Reset value of INTENSET00 register. */ @@ -27260,8 +27277,8 @@ typedef struct { #define RADIO_PHYENDTXDELAY_RATE2M_Pos (4UL) /*!< Position of RATE2M field. */ #define RADIO_PHYENDTXDELAY_RATE2M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE2M_Pos) /*!< Bit mask of RATE2M field. */ -/* RATE1M @Bits 8..10 : For modes with 1 Mbps on-air bit rate, unit is 1/2 bit period (Nrf_1Mbit, Ble_1Mbit, Ble_LR125Kbit, and - Ble_LR500Kbit modes) */ +/* RATE1M @Bits 8..10 : For modes with 1 Mbps on-air bit rate, unit is 1/2 bit period (Nrf_1Mbit and Ble_1Mbit modes) Also used + for Coded phy (Ble_LR125Kbit and Ble_LR500Kbit modes) */ #define RADIO_PHYENDTXDELAY_RATE1M_Pos (8UL) /*!< Position of RATE1M field. */ #define RADIO_PHYENDTXDELAY_RATE1M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE1M_Pos) /*!< Bit mask of RATE1M field. */ @@ -27284,6 +27301,8 @@ typedef struct { #define RADIO_STATE_STATE_RxIdle (0x2UL) /*!< RADIO is in the RXIDLE state */ #define RADIO_STATE_STATE_Rx (0x3UL) /*!< RADIO is in the RX state */ #define RADIO_STATE_STATE_RxDisable (0x4UL) /*!< RADIO is in the RXDISABLE state */ + #define RADIO_STATE_STATE_Settle (0x5UL) /*!< RADIO is in the SETTLE state */ + #define RADIO_STATE_STATE_Pll (0x6UL) /*!< RADIO is in the PLL state */ #define RADIO_STATE_STATE_TxRu (0x9UL) /*!< RADIO is in the TXRU state */ #define RADIO_STATE_STATE_TxIdle (0xAUL) /*!< RADIO is in the TXIDLE state */ #define RADIO_STATE_STATE_Tx (0xBUL) /*!< RADIO is in the TX state */ @@ -29287,9 +29306,10 @@ typedef struct { #define SAADC_CH_PSELN_CONNECT_Pos (30UL) /*!< Position of CONNECT field. */ #define SAADC_CH_PSELN_CONNECT_Msk (0x3UL << SAADC_CH_PSELN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ #define SAADC_CH_PSELN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ - #define SAADC_CH_PSELN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SAADC_CH_PSELN_CONNECT_Max (0x2UL) /*!< Max enumerator value of CONNECT field. */ #define SAADC_CH_PSELN_CONNECT_NC (0x0UL) /*!< Not connected */ #define SAADC_CH_PSELN_CONNECT_AnalogInput (0x1UL) /*!< Select analog input */ + #define SAADC_CH_PSELN_CONNECT_Internal (0x2UL) /*!< Selects internal inputs. */ /* SAADC_CH_CONFIG: Input configuration for CH[n] */ @@ -32733,7 +32753,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -32772,6 +32794,18 @@ typedef struct { #define SPIS_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* SPIS_DMA_RX_LIST: EasyDMA list type */ + #define SPIS_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIS_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Msk (0x7UL << SPIS_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIS_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* SPIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define SPIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -32806,7 +32840,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -32843,6 +32879,18 @@ typedef struct { #define SPIS_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* SPIS_DMA_TX_LIST: EasyDMA list type */ + #define SPIS_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIS_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Msk (0x7UL << SPIS_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIS_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* SPIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define SPIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -36922,7 +36970,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -36961,6 +37011,18 @@ typedef struct { #define TWIM_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIM_DMA_RX_LIST: EasyDMA list type */ + #define TWIM_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIM_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Msk (0x7UL << TWIM_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIM_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIM_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIM_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -36995,7 +37057,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -37032,6 +37096,18 @@ typedef struct { #define TWIM_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIM_DMA_TX_LIST: EasyDMA list type */ + #define TWIM_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIM_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Msk (0x7UL << TWIM_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIM_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIM_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIM_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -38570,7 +38646,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -38609,6 +38687,18 @@ typedef struct { #define TWIS_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIS_DMA_RX_LIST: EasyDMA list type */ + #define TWIS_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIS_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Msk (0x7UL << TWIS_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIS_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -38643,7 +38733,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -38680,6 +38772,18 @@ typedef struct { #define TWIS_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIS_DMA_TX_LIST: EasyDMA list type */ + #define TWIS_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIS_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Msk (0x7UL << TWIS_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIS_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -39918,7 +40022,7 @@ typedef struct { * @brief RX [UARTE_EVENTS_DMA_RX] Peripheral events. */ typedef struct { - __IOM uint32_t END; /*!< (@ 0x00000000) Generated after EasyDMA has completed its operation. */ + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.*/ @@ -39926,10 +40030,10 @@ typedef struct { __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ } NRF_UARTE_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ -/* UARTE_EVENTS_DMA_RX_END: Generated after EasyDMA has completed its operation. */ +/* UARTE_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ -/* END @Bit 0 : Generated after EasyDMA has completed its operation. */ +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ #define UARTE_EVENTS_DMA_RX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ #define UARTE_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ @@ -39988,17 +40092,17 @@ typedef struct { * @brief TX [UARTE_EVENTS_DMA_TX] Peripheral events. */ typedef struct { - __IOM uint32_t END; /*!< (@ 0x00000000) Generated after EasyDMA has completed its operation. */ + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.*/ __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ } NRF_UARTE_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ -/* UARTE_EVENTS_DMA_TX_END: Generated after EasyDMA has completed its operation. */ +/* UARTE_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ -/* END @Bit 0 : Generated after EasyDMA has completed its operation. */ +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ #define UARTE_EVENTS_DMA_TX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ #define UARTE_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ @@ -40428,7 +40532,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -40467,6 +40573,18 @@ typedef struct { #define UARTE_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* UARTE_DMA_RX_LIST: EasyDMA list type */ + #define UARTE_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define UARTE_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Msk (0x7UL << UARTE_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define UARTE_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* UARTE_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define UARTE_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -40501,7 +40619,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -40538,6 +40658,18 @@ typedef struct { #define UARTE_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* UARTE_DMA_TX_LIST: EasyDMA list type */ + #define UARTE_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define UARTE_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Msk (0x7UL << UARTE_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define UARTE_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* UARTE_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define UARTE_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_version.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_version.h index b637cff..ea06550 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_version.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_version.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -40,8 +40,8 @@ POSSIBILITY OF SUCH DAMAGE. #endif -#define MDK_SOURCE_VERSION_MAJOR 0 /*!< Major version of the datasheet. */ -#define MDK_SOURCE_VERSION_MINOR 10a /*!< Minor version of the datasheet. */ +#define MDK_SOURCE_VERSION_MAJOR 1 /*!< Major version of the datasheet. */ +#define MDK_SOURCE_VERSION_MINOR 1 /*!< Minor version of the datasheet. */ #define MDK_SOURCE_VERSION_MICRO 0 /*!< Micro version of the datasheet. */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_xxaa_application_memory.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_xxaa_application_memory.h index 5c09634..12ea291 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_xxaa_application_memory.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_xxaa_application_memory.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_xxaa_flpr_memory.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_xxaa_flpr_memory.h index 75a651f..5c809cb 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l10_xxaa_flpr_memory.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l10_xxaa_flpr_memory.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15.h index 6f821e9..c16020d 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_application.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_application.h index 8fad64b..1925cb8 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_application.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_application.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_application_peripherals.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_application_peripherals.h index 25c7241..27de67d 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_application_peripherals.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_application_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -528,6 +528,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */ #define UARTE00_CORE_CLOCK_128 1 /*!< (unspecified) */ #define UARTE00_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE00_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -538,6 +539,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE20_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE20_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE20_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -548,6 +550,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE21_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE21_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE21_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -558,6 +561,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE22_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE22_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE22_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ @@ -568,6 +572,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define UARTE30_CORE_CLOCK_16 1 /*!< (unspecified) */ #define UARTE30_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE30_DMAEND_PRESENT 0 /*!< (unspecified) */ #define UARTE30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ /*Voltage glitch detectors*/ @@ -897,6 +902,10 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_IRQ_COUNT 2 #define RADIO_WHITENINGPOLY 1 /*!< (unspecified) */ +#define RADIO_IEEE802154 1 /*!< IEEE 802.15.4 support */ +#define RADIO_LONGRANGE 1 /*!< Long range (LE Coded PHY) support */ +#define RADIO_DIRECTIONFINDING 1 /*!< Direction finding support (DFE) */ +#define RADIO_CHANNELSOUNDING 1 /*!< Channel sounding support (CSTONES) */ #define RADIO_ADPLLCOMPANION_INCLUDE_DMA 0 /*!< No internal instantiation of DmaChannelPeripheral */ /*I2C compatible Two-Wire Master Interface with EasyDMA*/ @@ -906,21 +915,25 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define TWIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define TWIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define TWIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ #define TWIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ #define TWIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ #define TWIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ @@ -1014,7 +1027,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_TCONV_VALUE_RANGE_MIN 1 /*!< (unspecified) */ #define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ #define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ -#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< CURRENTAMOUNT register not included. */ +#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< CURRENTAMOUNT register included. */ /*NFC-A compatible radio NFC-A compatible radio*/ #define NFCT_PRESENT 1 @@ -1058,6 +1071,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TAMPC_PRESENT 1 #define TAMPC_COUNT 1 +#define TAMPC_GPIOSWD 0 /*!< (unspecified) */ #define TAMPC_APSPIDEN 0 /*!< (unspecified) */ #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 1 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 1 */ #define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_flpr.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_flpr.h index 96543ea..f6d796f 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_flpr.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_flpr.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_global.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_global.h index 77c703f..95310d3 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_global.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_global.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -101,6 +101,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_RRAMC_S_BASE 0x5004B000UL #define NRF_VPR00_NS_BASE 0x4004C000UL #define NRF_VPR00_S_BASE 0x5004C000UL +#define NRF_GPIOHSPADCTRL_NS_BASE 0x40050400UL #define NRF_P2_NS_BASE 0x40050400UL #define NRF_GPIOHSPADCTRL_S_BASE 0x50050400UL #define NRF_P2_S_BASE 0x50050400UL @@ -276,6 +277,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_RRAMC_S ((NRF_RRAMC_Type*) NRF_RRAMC_S_BASE) #define NRF_VPR00_NS ((NRF_VPR_Type*) NRF_VPR00_NS_BASE) #define NRF_VPR00_S ((NRF_VPR_Type*) NRF_VPR00_S_BASE) +#define NRF_GPIOHSPADCTRL_NS ((NRF_GPIOHSPADCTRL_Type*) NRF_GPIOHSPADCTRL_NS_BASE) #define NRF_P2_NS ((NRF_GPIO_Type*) NRF_P2_NS_BASE) #define NRF_GPIOHSPADCTRL_S ((NRF_GPIOHSPADCTRL_Type*) NRF_GPIOHSPADCTRL_S_BASE) #define NRF_P2_S ((NRF_GPIO_Type*) NRF_P2_S_BASE) @@ -433,6 +435,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_SPIS00 NRF_SPIS00_NS #define NRF_UARTE00 NRF_UARTE00_NS #define NRF_VPR00 NRF_VPR00_NS + #define NRF_GPIOHSPADCTRL NRF_GPIOHSPADCTRL_NS #define NRF_P2 NRF_P2_NS #define NRF_CTRLAP NRF_CTRLAP_NS #define NRF_TAD NRF_TAD_NS diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_interim.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_interim.h index febb700..05560d9 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_interim.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_interim.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_name_change.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_name_change.h index 787d643..8264f40 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_name_change.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_name_change.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_peripherals.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_peripherals.h index c09f690..00961b0 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_peripherals.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_types.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_types.h index cb3c755..f5ea07a 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_types.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_types.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -12223,8 +12223,8 @@ typedef struct { #define GPIO_PIN_CNF_PULL_Min (0x0UL) /*!< Min enumerator value of PULL field. */ #define GPIO_PIN_CNF_PULL_Max (0x3UL) /*!< Max enumerator value of PULL field. */ #define GPIO_PIN_CNF_PULL_Disabled (0x0UL) /*!< No pull */ - #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull down on pin */ - #define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull up on pin */ + #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull-down on pin */ + #define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull-up on pin */ /* DRIVE0 @Bits 8..9 : Drive configuration for '0' */ #define GPIO_PIN_CNF_DRIVE0_Pos (8UL) /*!< Position of DRIVE0 field. */ @@ -12287,7 +12287,7 @@ typedef struct { /* GPIOHSPADCTRL_BIAS: Bias control */ #define GPIOHSPADCTRL_BIAS_ResetValue (0x00000000UL) /*!< Reset value of BIAS register. */ -/* HSBIAS @Bits 0..1 : Slew setting for high-speed pad (higher value is faster) */ +/* HSBIAS @Bits 0..1 : Slew setting for high-speed pad (Use highest/fastest value) */ #define GPIOHSPADCTRL_BIAS_HSBIAS_Pos (0UL) /*!< Position of HSBIAS field. */ #define GPIOHSPADCTRL_BIAS_HSBIAS_Msk (0x3UL << GPIOHSPADCTRL_BIAS_HSBIAS_Pos) /*!< Bit mask of HSBIAS field. */ #define GPIOHSPADCTRL_BIAS_HSBIAS_Min (0x0UL) /*!< Min value of HSBIAS field. */ @@ -24054,30 +24054,22 @@ typedef struct { * @brief AUXDATA [RADIO_AUXDATA] (unspecified) */ typedef struct { - __IOM uint32_t CNF[2]; /*!< (@ 0x00000000) AUXDATA configuration */ -} NRF_RADIO_AUXDATA_Type; /*!< Size = 8 (0x008) */ + __IOM uint32_t CNF[1]; /*!< (@ 0x00000000) AUXDATA configuration */ +} NRF_RADIO_AUXDATA_Type; /*!< Size = 4 (0x004) */ /* RADIO_AUXDATA_CNF: AUXDATA configuration */ - #define RADIO_AUXDATA_CNF_MaxCount (2UL) /*!< Max size of CNF[2] array. */ - #define RADIO_AUXDATA_CNF_MaxIndex (1UL) /*!< Max index of CNF[2] array. */ - #define RADIO_AUXDATA_CNF_MinIndex (0UL) /*!< Min index of CNF[2] array. */ - #define RADIO_AUXDATA_CNF_ResetValue (0x00000000UL) /*!< Reset value of CNF[2] register. */ + #define RADIO_AUXDATA_CNF_MaxCount (1UL) /*!< Max size of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_MaxIndex (0UL) /*!< Max index of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_MinIndex (0UL) /*!< Min index of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_ResetValue (0x00000000UL) /*!< Reset value of CNF[1] register. */ -/* ACQMODE @Bits 0..4 : Acquisition mode (data from RADIO written to memory) */ +/* ACQMODE @Bits 0..4 : Acquisition mode */ #define RADIO_AUXDATA_CNF_ACQMODE_Pos (0UL) /*!< Position of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Msk (0x1FUL << RADIO_AUXDATA_CNF_ACQMODE_Pos) /*!< Bit mask of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Min (0x07UL) /*!< Min enumerator value of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Max (0x07UL) /*!< Max enumerator value of ACQMODE field. */ #define RADIO_AUXDATA_CNF_ACQMODE_Rtt (0x07UL) /*!< Baseband Channel Sounding RTT Data */ -/* DIR @Bit 31 : Data acquisition or injection */ - #define RADIO_AUXDATA_CNF_DIR_Pos (31UL) /*!< Position of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Msk (0x1UL << RADIO_AUXDATA_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Min (0x0UL) /*!< Min enumerator value of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Max (0x1UL) /*!< Max enumerator value of DIR field. */ - #define RADIO_AUXDATA_CNF_DIR_Acq (0x0UL) /*!< Peripheral to memory */ - #define RADIO_AUXDATA_CNF_DIR_Inj (0x1UL) /*!< Memory to peripheral */ - /* ================================================= Struct RADIO_AUXDATADMA ================================================= */ @@ -24091,9 +24083,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of 32-bit words transferred in the last transaction*/ } NRF_RADIO_AUXDATADMA_Type; /*!< Size = 16 (0x010) */ - #define RADIO_AUXDATADMA_MaxCount (2UL) /*!< Size of AUXDATADMA[2] array. */ - #define RADIO_AUXDATADMA_MaxIndex (1UL) /*!< Max index of AUXDATADMA[2] array. */ - #define RADIO_AUXDATADMA_MinIndex (0UL) /*!< Min index of AUXDATADMA[2] array. */ + #define RADIO_AUXDATADMA_MaxCount (1UL) /*!< Size of AUXDATADMA[1] array. */ + #define RADIO_AUXDATADMA_MaxIndex (0UL) /*!< Max index of AUXDATADMA[1] array. */ + #define RADIO_AUXDATADMA_MinIndex (0UL) /*!< Min index of AUXDATADMA[1] array. */ /* RADIO_AUXDATADMA_ENABLE: Enable or disable data acquisition */ #define RADIO_AUXDATADMA_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ @@ -24443,7 +24435,7 @@ typedef struct { /* RADIO_RTT_CONFIG: RTT Config. */ #define RADIO_RTT_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ -/* EN @Bit 0 : Enable RTT Functionality. Only valid for BLE 1MBPS and 2MBPS mode */ +/* EN @Bit 0 : Enable RTT functionality. Only valid for BLE 1MBPS and 2MBPS mode */ #define RADIO_RTT_CONFIG_EN_Pos (0UL) /*!< Position of EN field. */ #define RADIO_RTT_CONFIG_EN_Msk (0x1UL << RADIO_RTT_CONFIG_EN_Pos) /*!< Bit mask of EN field. */ #define RADIO_RTT_CONFIG_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ @@ -24473,7 +24465,7 @@ typedef struct { #define RADIO_RTT_CONFIG_NUMSEGMENTS_Msk (0xFUL << RADIO_RTT_CONFIG_NUMSEGMENTS_Pos) /*!< Bit mask of NUMSEGMENTS field. */ /* EFSDELAY @Bits 8..16 : Early Frame Sync Delay, i.e., number of cycles to wait for access address to anchor correctly. For - 2MBPSBLE mode, the EFSDELAY value is 64 (2us) and for 1MBPSBLE mode, it can be 256 (8us). */ + Ble_2Mbit, the EFSDELAY value is 64 (2us) and for Ble_1Mbit, it can be 256 (8us). */ #define RADIO_RTT_CONFIG_EFSDELAY_Pos (8UL) /*!< Position of EFSDELAY field. */ #define RADIO_RTT_CONFIG_EFSDELAY_Msk (0x1FFUL << RADIO_RTT_CONFIG_EFSDELAY_Pos) /*!< Bit mask of EFSDELAY field. */ @@ -24657,44 +24649,45 @@ typedef struct { __IOM uint32_t DATAWHITE; /*!< (@ 0x00000540) Data whitening configuration */ __IM uint32_t RESERVED25; __IOM NRF_RADIO_AUXDATA_Type AUXDATA; /*!< (@ 0x00000548) (unspecified) */ - __IOM NRF_RADIO_AUXDATADMA_Type AUXDATADMA[2]; /*!< (@ 0x00000550) (unspecified) */ - __IM uint32_t RESERVED26[101]; + __IM uint32_t RESERVED26; + __IOM NRF_RADIO_AUXDATADMA_Type AUXDATADMA[1]; /*!< (@ 0x00000550) (unspecified) */ + __IM uint32_t RESERVED27[105]; __IOM uint32_t TIMING; /*!< (@ 0x00000704) Timing */ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000708) Frequency */ - __IM uint32_t RESERVED27; + __IM uint32_t RESERVED28; __IOM uint32_t TXPOWER; /*!< (@ 0x00000710) Output power */ __IOM uint32_t TIFS; /*!< (@ 0x00000714) Interframe spacing in us */ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000718) RSSI sample */ - __IM uint32_t RESERVED28[45]; + __IM uint32_t RESERVED29[45]; __IOM NRF_RADIO_RXGAIN_Type RXGAIN; /*!< (@ 0x000007D0) (unspecified) */ - __IM uint32_t RESERVED29[11]; + __IM uint32_t RESERVED30[11]; __IOM uint32_t FREQFINETUNE; /*!< (@ 0x00000804) Fine tuning of the RF frequency */ - __IM uint32_t RESERVED30[64]; + __IM uint32_t RESERVED31[64]; __IOM uint32_t FECONFIG; /*!< (@ 0x00000908) Config register */ - __IM uint32_t RESERVED31[125]; + __IM uint32_t RESERVED32[125]; __IM uint32_t CFO_STAT; /*!< (@ 0x00000B00) Carrier freq. offset estimate */ - __IM uint32_t RESERVED32[15]; + __IM uint32_t RESERVED33[15]; __IOM uint32_t DBCCORR; /*!< (@ 0x00000B40) Correlator thresholds */ - __IM uint32_t RESERVED33[111]; + __IM uint32_t RESERVED34[111]; __IOM uint32_t DFEMODE; /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)*/ __IM uint32_t DFESTATUS; /*!< (@ 0x00000D04) DFE status information */ - __IM uint32_t RESERVED34[2]; + __IM uint32_t RESERVED35[2]; __IOM uint32_t DFECTRL1; /*!< (@ 0x00000D10) Various configuration for Direction finding */ __IOM uint32_t DFECTRL2; /*!< (@ 0x00000D14) Start offset for Direction finding */ - __IM uint32_t RESERVED35[4]; + __IM uint32_t RESERVED36[4]; __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna */ __OM uint32_t CLEARPATTERN; /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control */ __IOM NRF_RADIO_PSEL_Type PSEL; /*!< (@ 0x00000D30) (unspecified) */ __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000D50) DFE packet EasyDMA channel */ - __IM uint32_t RESERVED36[43]; + __IM uint32_t RESERVED37[43]; __IM uint32_t CRCSTATUS; /*!< (@ 0x00000E0C) CRC status */ __IM uint32_t RXMATCH; /*!< (@ 0x00000E10) Received address */ __IM uint32_t RXCRC; /*!< (@ 0x00000E14) CRC field of previously received packet */ __IM uint32_t DAI; /*!< (@ 0x00000E18) Device address match index */ __IM uint32_t PDUSTAT; /*!< (@ 0x00000E1C) Payload status */ __IOM uint32_t PCNF0; /*!< (@ 0x00000E20) Packet configuration register 0 */ - __IM uint32_t RESERVED37; + __IM uint32_t RESERVED38; __IOM uint32_t PCNF1; /*!< (@ 0x00000E28) Packet configuration register 1 */ __IOM uint32_t BASE0; /*!< (@ 0x00000E2C) Base address 0 */ __IOM uint32_t BASE1; /*!< (@ 0x00000E30) Base address 1 */ @@ -24709,18 +24702,18 @@ typedef struct { __IOM uint32_t DAP[8]; /*!< (@ 0x00000E70) Device address prefix n */ __IOM uint32_t DACNF; /*!< (@ 0x00000E90) Device address match configuration */ __IOM uint32_t BCC; /*!< (@ 0x00000E94) Bit counter compare */ - __IM uint32_t RESERVED38[3]; - __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ __IM uint32_t RESERVED39[3]; + __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ + __IM uint32_t RESERVED40[3]; __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000EB4) Search pattern configuration */ __IOM uint32_t MHRMATCHMASK; /*!< (@ 0x00000EB8) Pattern mask */ __IOM uint32_t SFD; /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter */ __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000EC0) Configuration for CTE inline mode */ - __IM uint32_t RESERVED40[3]; + __IM uint32_t RESERVED41[3]; __IOM uint32_t PACKETPTR; /*!< (@ 0x00000ED0) Packet pointer */ - __IM uint32_t RESERVED41[75]; + __IM uint32_t RESERVED42[75]; __IOM NRF_RADIO_CSTONES_Type CSTONES; /*!< (@ 0x00001000) (unspecified) */ - __IM uint32_t RESERVED42[2]; + __IM uint32_t RESERVED43[2]; __IOM NRF_RADIO_RTT_Type RTT; /*!< (@ 0x00001050) (unspecified) */ } NRF_RADIO_Type; /*!< Size = 4196 (0x1064) */ @@ -26129,6 +26122,14 @@ typedef struct { #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0x0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (0x1UL) /*!< Enable shortcut */ +/* PHYEND_PLLEN @Bit 7 : Shortcut between event PHYEND and task PLLEN */ + #define RADIO_SHORTS_PHYEND_PLLEN_Pos (7UL) /*!< Position of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Msk (0x1UL << RADIO_SHORTS_PHYEND_PLLEN_Pos) /*!< Bit mask of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Min (0x0UL) /*!< Min enumerator value of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Max (0x1UL) /*!< Max enumerator value of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PHYEND_PLLEN_Enabled (0x1UL) /*!< Enable shortcut */ + /* RXREADY_CCASTART @Bit 10 : Shortcut between event RXREADY and task CCASTART */ #define RADIO_SHORTS_RXREADY_CCASTART_Pos (10UL) /*!< Position of RXREADY_CCASTART field. */ #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART @@ -26219,6 +26220,22 @@ typedef struct { #define RADIO_SHORTS_PHYEND_START_Disabled (0x0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_PHYEND_START_Enabled (0x1UL) /*!< Enable shortcut */ +/* PLLREADY_TXEN @Bit 27 : Shortcut between event PLLREADY and task TXEN */ + #define RADIO_SHORTS_PLLREADY_TXEN_Pos (27UL) /*!< Position of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Msk (0x1UL << RADIO_SHORTS_PLLREADY_TXEN_Pos) /*!< Bit mask of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Min (0x0UL) /*!< Min enumerator value of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Max (0x1UL) /*!< Max enumerator value of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PLLREADY_TXEN_Enabled (0x1UL) /*!< Enable shortcut */ + +/* PLLREADY_RXEN @Bit 28 : Shortcut between event PLLREADY and task RXEN */ + #define RADIO_SHORTS_PLLREADY_RXEN_Pos (28UL) /*!< Position of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Msk (0x1UL << RADIO_SHORTS_PLLREADY_RXEN_Pos) /*!< Bit mask of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Min (0x0UL) /*!< Min enumerator value of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Max (0x1UL) /*!< Max enumerator value of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PLLREADY_RXEN_Enabled (0x1UL) /*!< Enable shortcut */ + /* RADIO_INTENSET00: Enable interrupt */ #define RADIO_INTENSET00_ResetValue (0x00000000UL) /*!< Reset value of INTENSET00 register. */ @@ -27260,8 +27277,8 @@ typedef struct { #define RADIO_PHYENDTXDELAY_RATE2M_Pos (4UL) /*!< Position of RATE2M field. */ #define RADIO_PHYENDTXDELAY_RATE2M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE2M_Pos) /*!< Bit mask of RATE2M field. */ -/* RATE1M @Bits 8..10 : For modes with 1 Mbps on-air bit rate, unit is 1/2 bit period (Nrf_1Mbit, Ble_1Mbit, Ble_LR125Kbit, and - Ble_LR500Kbit modes) */ +/* RATE1M @Bits 8..10 : For modes with 1 Mbps on-air bit rate, unit is 1/2 bit period (Nrf_1Mbit and Ble_1Mbit modes) Also used + for Coded phy (Ble_LR125Kbit and Ble_LR500Kbit modes) */ #define RADIO_PHYENDTXDELAY_RATE1M_Pos (8UL) /*!< Position of RATE1M field. */ #define RADIO_PHYENDTXDELAY_RATE1M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE1M_Pos) /*!< Bit mask of RATE1M field. */ @@ -27284,6 +27301,8 @@ typedef struct { #define RADIO_STATE_STATE_RxIdle (0x2UL) /*!< RADIO is in the RXIDLE state */ #define RADIO_STATE_STATE_Rx (0x3UL) /*!< RADIO is in the RX state */ #define RADIO_STATE_STATE_RxDisable (0x4UL) /*!< RADIO is in the RXDISABLE state */ + #define RADIO_STATE_STATE_Settle (0x5UL) /*!< RADIO is in the SETTLE state */ + #define RADIO_STATE_STATE_Pll (0x6UL) /*!< RADIO is in the PLL state */ #define RADIO_STATE_STATE_TxRu (0x9UL) /*!< RADIO is in the TXRU state */ #define RADIO_STATE_STATE_TxIdle (0xAUL) /*!< RADIO is in the TXIDLE state */ #define RADIO_STATE_STATE_Tx (0xBUL) /*!< RADIO is in the TX state */ @@ -29287,9 +29306,10 @@ typedef struct { #define SAADC_CH_PSELN_CONNECT_Pos (30UL) /*!< Position of CONNECT field. */ #define SAADC_CH_PSELN_CONNECT_Msk (0x3UL << SAADC_CH_PSELN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ #define SAADC_CH_PSELN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ - #define SAADC_CH_PSELN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SAADC_CH_PSELN_CONNECT_Max (0x2UL) /*!< Max enumerator value of CONNECT field. */ #define SAADC_CH_PSELN_CONNECT_NC (0x0UL) /*!< Not connected */ #define SAADC_CH_PSELN_CONNECT_AnalogInput (0x1UL) /*!< Select analog input */ + #define SAADC_CH_PSELN_CONNECT_Internal (0x2UL) /*!< Selects internal inputs. */ /* SAADC_CH_CONFIG: Input configuration for CH[n] */ @@ -32733,7 +32753,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -32772,6 +32794,18 @@ typedef struct { #define SPIS_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* SPIS_DMA_RX_LIST: EasyDMA list type */ + #define SPIS_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIS_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Msk (0x7UL << SPIS_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIS_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* SPIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define SPIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -32806,7 +32840,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -32843,6 +32879,18 @@ typedef struct { #define SPIS_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* SPIS_DMA_TX_LIST: EasyDMA list type */ + #define SPIS_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIS_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Msk (0x7UL << SPIS_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIS_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* SPIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define SPIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -36922,7 +36970,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -36961,6 +37011,18 @@ typedef struct { #define TWIM_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIM_DMA_RX_LIST: EasyDMA list type */ + #define TWIM_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIM_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Msk (0x7UL << TWIM_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIM_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIM_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIM_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -36995,7 +37057,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -37032,6 +37096,18 @@ typedef struct { #define TWIM_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIM_DMA_TX_LIST: EasyDMA list type */ + #define TWIM_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIM_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Msk (0x7UL << TWIM_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIM_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIM_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIM_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -38570,7 +38646,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -38609,6 +38687,18 @@ typedef struct { #define TWIS_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIS_DMA_RX_LIST: EasyDMA list type */ + #define TWIS_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIS_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Msk (0x7UL << TWIS_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIS_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -38643,7 +38733,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -38680,6 +38772,18 @@ typedef struct { #define TWIS_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* TWIS_DMA_TX_LIST: EasyDMA list type */ + #define TWIS_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIS_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Msk (0x7UL << TWIS_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIS_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* TWIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define TWIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -39918,7 +40022,7 @@ typedef struct { * @brief RX [UARTE_EVENTS_DMA_RX] Peripheral events. */ typedef struct { - __IOM uint32_t END; /*!< (@ 0x00000000) Generated after EasyDMA has completed its operation. */ + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.*/ @@ -39926,10 +40030,10 @@ typedef struct { __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ } NRF_UARTE_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ -/* UARTE_EVENTS_DMA_RX_END: Generated after EasyDMA has completed its operation. */ +/* UARTE_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ -/* END @Bit 0 : Generated after EasyDMA has completed its operation. */ +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ #define UARTE_EVENTS_DMA_RX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ #define UARTE_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ @@ -39988,17 +40092,17 @@ typedef struct { * @brief TX [UARTE_EVENTS_DMA_TX] Peripheral events. */ typedef struct { - __IOM uint32_t END; /*!< (@ 0x00000000) Generated after EasyDMA has completed its operation. */ + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.*/ __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ } NRF_UARTE_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ -/* UARTE_EVENTS_DMA_TX_END: Generated after EasyDMA has completed its operation. */ +/* UARTE_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ -/* END @Bit 0 : Generated after EasyDMA has completed its operation. */ +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ #define UARTE_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ #define UARTE_EVENTS_DMA_TX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ #define UARTE_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ @@ -40428,7 +40532,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -40467,6 +40573,18 @@ typedef struct { #define UARTE_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* UARTE_DMA_RX_LIST: EasyDMA list type */ + #define UARTE_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define UARTE_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Msk (0x7UL << UARTE_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define UARTE_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* UARTE_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define UARTE_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ @@ -40501,7 +40619,9 @@ typedef struct { __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event.*/ - __IM uint32_t RESERVED1[3]; + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is detected.*/ __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR @@ -40538,6 +40658,18 @@ typedef struct { #define UARTE_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ +/* UARTE_DMA_TX_LIST: EasyDMA list type */ + #define UARTE_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define UARTE_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Msk (0x7UL << UARTE_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define UARTE_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + /* UARTE_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ #define UARTE_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_version.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_version.h index 0937f50..92b7a22 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_version.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_version.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -41,7 +41,7 @@ POSSIBILITY OF SUCH DAMAGE. #define MDK_SOURCE_VERSION_MAJOR 1 /*!< Major version of the datasheet. */ -#define MDK_SOURCE_VERSION_MINOR 0 /*!< Minor version of the datasheet. */ +#define MDK_SOURCE_VERSION_MINOR 1 /*!< Minor version of the datasheet. */ #define MDK_SOURCE_VERSION_MICRO 0 /*!< Micro version of the datasheet. */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_xxaa_application_memory.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_xxaa_application_memory.h index 61cbf2e..95bff32 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_xxaa_application_memory.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_xxaa_application_memory.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_xxaa_flpr_memory.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_xxaa_flpr_memory.h index d2ea224..d0dad54 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l15_xxaa_flpr_memory.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l15_xxaa_flpr_memory.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54l_erratas.h b/cores/nRF5/nordic/nrfx/mdk/nrf54l_erratas.h index 16e8e4d..4c68809 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf54l_erratas.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54l_erratas.h @@ -3,7 +3,7 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -39,77 +39,90 @@ POSSIBILITY OF SUCH DAMAGE. #include #include "compiler_abstraction.h" -static bool nrf54l_errata_1(void) __UNUSED; -static bool nrf54l_errata_2(void) __UNUSED; -static bool nrf54l_errata_3(void) __UNUSED; -static bool nrf54l_errata_4(void) __UNUSED; -static bool nrf54l_errata_6(void) __UNUSED; -static bool nrf54l_errata_7(void) __UNUSED; -static bool nrf54l_errata_8(void) __UNUSED; -static bool nrf54l_errata_9(void) __UNUSED; -static bool nrf54l_errata_10(void) __UNUSED; -static bool nrf54l_errata_13(void) __UNUSED; -static bool nrf54l_errata_16(void) __UNUSED; -static bool nrf54l_errata_17(void) __UNUSED; -static bool nrf54l_errata_18(void) __UNUSED; -static bool nrf54l_errata_19(void) __UNUSED; -static bool nrf54l_errata_20(void) __UNUSED; -static bool nrf54l_errata_21(void) __UNUSED; -static bool nrf54l_errata_22(void) __UNUSED; -static bool nrf54l_errata_23(void) __UNUSED; -static bool nrf54l_errata_24(void) __UNUSED; -static bool nrf54l_errata_25(void) __UNUSED; -static bool nrf54l_errata_26(void) __UNUSED; -static bool nrf54l_errata_27(void) __UNUSED; -static bool nrf54l_errata_30(void) __UNUSED; -static bool nrf54l_errata_31(void) __UNUSED; -static bool nrf54l_errata_32(void) __UNUSED; -static bool nrf54l_errata_33(void) __UNUSED; -static bool nrf54l_errata_35(void) __UNUSED; -static bool nrf54l_errata_37(void) __UNUSED; -static bool nrf54l_errata_38(void) __UNUSED; -static bool nrf54l_errata_39(void) __UNUSED; -static bool nrf54l_errata_40(void) __UNUSED; -static bool nrf54l_errata_41(void) __UNUSED; -static bool nrf54l_errata_42(void) __UNUSED; -static bool nrf54l_errata_43(void) __UNUSED; -static bool nrf54l_errata_44(void) __UNUSED; -static bool nrf54l_errata_45(void) __UNUSED; -static bool nrf54l_errata_46(void) __UNUSED; -static bool nrf54l_errata_47(void) __UNUSED; -static bool nrf54l_errata_48(void) __UNUSED; -static bool nrf54l_errata_49(void) __UNUSED; -static bool nrf54l_errata_50(void) __UNUSED; -static bool nrf54l_errata_55(void) __UNUSED; -static bool nrf54l_configuration_56(void) __UNUSED; -static bool nrf54l_errata_57(void) __UNUSED; -static bool nrf54l_errata_60(void) __UNUSED; -static bool nrf54l_errata_61(void) __UNUSED; -static bool nrf54l_errata_63(void) __UNUSED; -static bool nrf54l_errata_65(void) __UNUSED; -static bool nrf54l_errata_66(void) __UNUSED; -static bool nrf54l_errata_68(void) __UNUSED; -static bool nrf54l_errata_69(void) __UNUSED; -static bool nrf54l_errata_70(void) __UNUSED; -static bool nrf54l_errata_71(void) __UNUSED; -static bool nrf54l_errata_72(void) __UNUSED; -static bool nrf54l_errata_73(void) __UNUSED; -static bool nrf54l_errata_74(void) __UNUSED; -static bool nrf54l_errata_78(void) __UNUSED; -static bool nrf54l_errata_79(void) __UNUSED; -static bool nrf54l_errata_81(void) __UNUSED; -static bool nrf54l_errata_83(void) __UNUSED; -static bool nrf54l_errata_85(void) __UNUSED; -static bool nrf54l_errata_86(void) __UNUSED; -static bool nrf54l_errata_87(void) __UNUSED; -static bool nrf54l_errata_88(void) __UNUSED; -static bool nrf54l_errata_89(void) __UNUSED; -static bool nrf54l_errata_90(void) __UNUSED; -static bool nrf54l_errata_91(void) __UNUSED; -static bool nrf54l_errata_92(void) __UNUSED; -static bool nrf54l_errata_93(void) __UNUSED; -static bool nrf54l_errata_94(void) __UNUSED; -static bool nrf54l_errata_95(void) __UNUSED; +static inline bool nrf54l_errata_1(void); +static inline bool nrf54l_errata_2(void); +static inline bool nrf54l_errata_3(void); +static inline bool nrf54l_errata_4(void); +static inline bool nrf54l_errata_6(void); +static inline bool nrf54l_errata_7(void); +static inline bool nrf54l_errata_8(void); +static inline bool nrf54l_errata_9(void); +static inline bool nrf54l_errata_10(void); +static inline bool nrf54l_errata_13(void); +static inline bool nrf54l_errata_15(void); +static inline bool nrf54l_errata_16(void); +static inline bool nrf54l_errata_17(void); +static inline bool nrf54l_errata_18(void); +static inline bool nrf54l_errata_19(void); +static inline bool nrf54l_errata_20(void); +static inline bool nrf54l_errata_21(void); +static inline bool nrf54l_errata_22(void); +static inline bool nrf54l_errata_23(void); +static inline bool nrf54l_errata_24(void); +static inline bool nrf54l_errata_25(void); +static inline bool nrf54l_errata_26(void); +static inline bool nrf54l_errata_27(void); +static inline bool nrf54l_errata_28(void); +static inline bool nrf54l_errata_30(void); +static inline bool nrf54l_errata_31(void); +static inline bool nrf54l_errata_32(void); +static inline bool nrf54l_errata_33(void); +static inline bool nrf54l_errata_35(void); +static inline bool nrf54l_errata_37(void); +static inline bool nrf54l_errata_38(void); +static inline bool nrf54l_errata_39(void); +static inline bool nrf54l_errata_40(void); +static inline bool nrf54l_errata_41(void); +static inline bool nrf54l_errata_42(void); +static inline bool nrf54l_errata_43(void); +static inline bool nrf54l_errata_44(void); +static inline bool nrf54l_errata_45(void); +static inline bool nrf54l_errata_46(void); +static inline bool nrf54l_errata_47(void); +static inline bool nrf54l_errata_48(void); +static inline bool nrf54l_errata_49(void); +static inline bool nrf54l_errata_50(void); +static inline bool nrf54l_errata_54(void); +static inline bool nrf54l_errata_55(void); +static inline bool nrf54l_configuration_56(void); +static inline bool nrf54l_errata_57(void); +static inline bool nrf54l_errata_58(void); +static inline bool nrf54l_errata_59(void); +static inline bool nrf54l_errata_60(void); +static inline bool nrf54l_errata_63(void); +static inline bool nrf54l_errata_65(void); +static inline bool nrf54l_errata_66(void); +static inline bool nrf54l_errata_68(void); +static inline bool nrf54l_errata_69(void); +static inline bool nrf54l_errata_70(void); +static inline bool nrf54l_errata_71(void); +static inline bool nrf54l_errata_72(void); +static inline bool nrf54l_errata_73(void); +static inline bool nrf54l_errata_74(void); +static inline bool nrf54l_errata_78(void); +static inline bool nrf54l_errata_79(void); +static inline bool nrf54l_errata_81(void); +static inline bool nrf54l_errata_83(void); +static inline bool nrf54l_errata_85(void); +static inline bool nrf54l_errata_86(void); +static inline bool nrf54l_errata_87(void); +static inline bool nrf54l_errata_88(void); +static inline bool nrf54l_errata_89(void); +static inline bool nrf54l_errata_90(void); +static inline bool nrf54l_errata_91(void); +static inline bool nrf54l_errata_92(void); +static inline bool nrf54l_errata_93(void); +static inline bool nrf54l_errata_94(void); +static inline bool nrf54l_errata_95(void); +static inline bool nrf54l_errata_100(void); +static inline bool nrf54l_errata_102(void); +static inline bool nrf54l_errata_103(void); +static inline bool nrf54l_errata_104(void); +static inline bool nrf54l_errata_105(void); +static inline bool nrf54l_errata_106(void); +static inline bool nrf54l_errata_115(void); +static inline bool nrf54l_errata_116(void); +static inline bool nrf54l_errata_121(void); /* ========= Errata 1 ========= */ #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ @@ -124,7 +137,7 @@ static bool nrf54l_errata_95(void) __UNUSED; #define NRF54L_ERRATA_1_ENABLE_WORKAROUND NRF54L_ERRATA_1_PRESENT #endif -static bool nrf54l_errata_1(void) +static inline bool nrf54l_errata_1(void) { #ifndef NRF54L_SERIES return false; @@ -188,7 +201,7 @@ static bool nrf54l_errata_1(void) #define NRF54L_ERRATA_2_ENABLE_WORKAROUND NRF54L_ERRATA_2_PRESENT #endif -static bool nrf54l_errata_2(void) +static inline bool nrf54l_errata_2(void) { #ifndef NRF54L_SERIES return false; @@ -204,7 +217,7 @@ static bool nrf54l_errata_2(void) #define NRF54L_ERRATA_3_ENABLE_WORKAROUND NRF54L_ERRATA_3_PRESENT #endif -static bool nrf54l_errata_3(void) +static inline bool nrf54l_errata_3(void) { #ifndef NRF54L_SERIES return false; @@ -220,7 +233,7 @@ static bool nrf54l_errata_3(void) #define NRF54L_ERRATA_4_ENABLE_WORKAROUND NRF54L_ERRATA_4_PRESENT #endif -static bool nrf54l_errata_4(void) +static inline bool nrf54l_errata_4(void) { #ifndef NRF54L_SERIES return false; @@ -233,7 +246,7 @@ static bool nrf54l_errata_4(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_6_PRESENT 1 #else #define NRF54L_ERRATA_6_PRESENT 0 @@ -243,7 +256,7 @@ static bool nrf54l_errata_4(void) #define NRF54L_ERRATA_6_ENABLE_WORKAROUND NRF54L_ERRATA_6_PRESENT #endif -static bool nrf54l_errata_6(void) +static inline bool nrf54l_errata_6(void) { #ifndef NRF54L_SERIES return false; @@ -251,7 +264,7 @@ static bool nrf54l_errata_6(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -269,7 +282,7 @@ static bool nrf54l_errata_6(void) } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -319,8 +332,11 @@ static bool nrf54l_errata_6(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) #define NRF54L_ERRATA_7_PRESENT 1 #else #define NRF54L_ERRATA_7_PRESENT 0 @@ -330,7 +346,7 @@ static bool nrf54l_errata_6(void) #define NRF54L_ERRATA_7_ENABLE_WORKAROUND NRF54L_ERRATA_7_PRESENT #endif -static bool nrf54l_errata_7(void) +static inline bool nrf54l_errata_7(void) { #ifndef NRF54L_SERIES return false; @@ -338,8 +354,11 @@ static bool nrf54l_errata_7(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -357,19 +376,21 @@ static bool nrf54l_errata_7(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -411,6 +432,42 @@ static bool nrf54l_errata_7(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -419,8 +476,11 @@ static bool nrf54l_errata_7(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) #define NRF54L_ERRATA_8_PRESENT 1 #else #define NRF54L_ERRATA_8_PRESENT 0 @@ -430,7 +490,7 @@ static bool nrf54l_errata_7(void) #define NRF54L_ERRATA_8_ENABLE_WORKAROUND NRF54L_ERRATA_8_PRESENT #endif -static bool nrf54l_errata_8(void) +static inline bool nrf54l_errata_8(void) { #ifndef NRF54L_SERIES return false; @@ -438,8 +498,11 @@ static bool nrf54l_errata_8(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -457,19 +520,21 @@ static bool nrf54l_errata_8(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -477,9 +542,9 @@ static bool nrf54l_errata_8(void) case 0x00ul: return true; case 0x01ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -511,6 +576,42 @@ static bool nrf54l_errata_8(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -528,7 +629,7 @@ static bool nrf54l_errata_8(void) #define NRF54L_ERRATA_9_ENABLE_WORKAROUND NRF54L_ERRATA_9_PRESENT #endif -static bool nrf54l_errata_9(void) +static inline bool nrf54l_errata_9(void) { #ifndef NRF54L_SERIES return false; @@ -598,7 +699,7 @@ static bool nrf54l_errata_9(void) #define NRF54L_ERRATA_10_ENABLE_WORKAROUND NRF54L_ERRATA_10_PRESENT #endif -static bool nrf54l_errata_10(void) +static inline bool nrf54l_errata_10(void) { #ifndef NRF54L_SERIES return false; @@ -668,7 +769,77 @@ static bool nrf54l_errata_10(void) #define NRF54L_ERRATA_13_ENABLE_WORKAROUND NRF54L_ERRATA_13_PRESENT #endif -static bool nrf54l_errata_13(void) +static inline bool nrf54l_errata_13(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 15 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + #define NRF54L_ERRATA_15_PRESENT 1 +#else + #define NRF54L_ERRATA_15_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_15_ENABLE_WORKAROUND + #define NRF54L_ERRATA_15_ENABLE_WORKAROUND NRF54L_ERRATA_15_PRESENT +#endif + +static inline bool nrf54l_errata_15(void) { #ifndef NRF54L_SERIES return false; @@ -738,7 +909,7 @@ static bool nrf54l_errata_13(void) #define NRF54L_ERRATA_16_ENABLE_WORKAROUND NRF54L_ERRATA_16_PRESENT #endif -static bool nrf54l_errata_16(void) +static inline bool nrf54l_errata_16(void) { #ifndef NRF54L_SERIES return false; @@ -808,7 +979,7 @@ static bool nrf54l_errata_16(void) #define NRF54L_ERRATA_17_ENABLE_WORKAROUND NRF54L_ERRATA_17_PRESENT #endif -static bool nrf54l_errata_17(void) +static inline bool nrf54l_errata_17(void) { #ifndef NRF54L_SERIES return false; @@ -878,7 +1049,7 @@ static bool nrf54l_errata_17(void) #define NRF54L_ERRATA_18_ENABLE_WORKAROUND NRF54L_ERRATA_18_PRESENT #endif -static bool nrf54l_errata_18(void) +static inline bool nrf54l_errata_18(void) { #ifndef NRF54L_SERIES return false; @@ -948,7 +1119,7 @@ static bool nrf54l_errata_18(void) #define NRF54L_ERRATA_19_ENABLE_WORKAROUND NRF54L_ERRATA_19_PRESENT #endif -static bool nrf54l_errata_19(void) +static inline bool nrf54l_errata_19(void) { #ifndef NRF54L_SERIES return false; @@ -1009,8 +1180,11 @@ static bool nrf54l_errata_19(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) #define NRF54L_ERRATA_20_PRESENT 1 #else #define NRF54L_ERRATA_20_PRESENT 0 @@ -1020,7 +1194,7 @@ static bool nrf54l_errata_19(void) #define NRF54L_ERRATA_20_ENABLE_WORKAROUND NRF54L_ERRATA_20_PRESENT #endif -static bool nrf54l_errata_20(void) +static inline bool nrf54l_errata_20(void) { #ifndef NRF54L_SERIES return false; @@ -1028,8 +1202,11 @@ static bool nrf54l_errata_20(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -1047,19 +1224,21 @@ static bool nrf54l_errata_20(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -1101,6 +1280,42 @@ static bool nrf54l_errata_20(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -1118,7 +1333,7 @@ static bool nrf54l_errata_20(void) #define NRF54L_ERRATA_21_ENABLE_WORKAROUND NRF54L_ERRATA_21_PRESENT #endif -static bool nrf54l_errata_21(void) +static inline bool nrf54l_errata_21(void) { #ifndef NRF54L_SERIES return false; @@ -1188,7 +1403,7 @@ static bool nrf54l_errata_21(void) #define NRF54L_ERRATA_22_ENABLE_WORKAROUND NRF54L_ERRATA_22_PRESENT #endif -static bool nrf54l_errata_22(void) +static inline bool nrf54l_errata_22(void) { #ifndef NRF54L_SERIES return false; @@ -1258,7 +1473,7 @@ static bool nrf54l_errata_22(void) #define NRF54L_ERRATA_23_ENABLE_WORKAROUND NRF54L_ERRATA_23_PRESENT #endif -static bool nrf54l_errata_23(void) +static inline bool nrf54l_errata_23(void) { #ifndef NRF54L_SERIES return false; @@ -1328,7 +1543,7 @@ static bool nrf54l_errata_23(void) #define NRF54L_ERRATA_24_ENABLE_WORKAROUND NRF54L_ERRATA_24_PRESENT #endif -static bool nrf54l_errata_24(void) +static inline bool nrf54l_errata_24(void) { #ifndef NRF54L_SERIES return false; @@ -1398,7 +1613,7 @@ static bool nrf54l_errata_24(void) #define NRF54L_ERRATA_25_ENABLE_WORKAROUND NRF54L_ERRATA_25_PRESENT #endif -static bool nrf54l_errata_25(void) +static inline bool nrf54l_errata_25(void) { #ifndef NRF54L_SERIES return false; @@ -1459,7 +1674,9 @@ static bool nrf54l_errata_25(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) #define NRF54L_ERRATA_26_PRESENT 1 #else #define NRF54L_ERRATA_26_PRESENT 0 @@ -1469,7 +1686,7 @@ static bool nrf54l_errata_25(void) #define NRF54L_ERRATA_26_ENABLE_WORKAROUND NRF54L_ERRATA_26_PRESENT #endif -static bool nrf54l_errata_26(void) +static inline bool nrf54l_errata_26(void) { #ifndef NRF54L_SERIES return false; @@ -1477,7 +1694,9 @@ static bool nrf54l_errata_26(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -1495,7 +1714,7 @@ static bool nrf54l_errata_26(void) } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -1537,6 +1756,30 @@ static bool nrf54l_errata_26(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -1554,7 +1797,7 @@ static bool nrf54l_errata_26(void) #define NRF54L_ERRATA_27_ENABLE_WORKAROUND NRF54L_ERRATA_27_PRESENT #endif -static bool nrf54l_errata_27(void) +static inline bool nrf54l_errata_27(void) { #ifndef NRF54L_SERIES return false; @@ -1611,31 +1854,27 @@ static bool nrf54l_errata_27(void) #endif } -/* ========= Errata 30 ========= */ +/* ========= Errata 28 ========= */ #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) - #define NRF54L_ERRATA_30_PRESENT 1 + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + #define NRF54L_ERRATA_28_PRESENT 1 #else - #define NRF54L_ERRATA_30_PRESENT 0 + #define NRF54L_ERRATA_28_PRESENT 0 #endif -#ifndef NRF54L_ERRATA_30_ENABLE_WORKAROUND - #define NRF54L_ERRATA_30_ENABLE_WORKAROUND NRF54L_ERRATA_30_PRESENT +#ifndef NRF54L_ERRATA_28_ENABLE_WORKAROUND + #define NRF54L_ERRATA_28_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_30(void) +static inline bool nrf54l_errata_28(void) { #ifndef NRF54L_SERIES return false; #else #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -1653,32 +1892,6 @@ static bool nrf54l_errata_30(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) - if (var1 == 0x27) - { - switch(var2) - { - case 0x00ul: - return true; - default: - return true; - } - } - #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) - if (var1 == 0x29) - { - switch(var2) - { - case 0x00ul: - return true; - case 0x01ul: - return true; - default: - return true; - } - } - #endif #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) if (var1 == 0x2E) { @@ -1711,27 +1924,37 @@ static bool nrf54l_errata_30(void) #endif } -/* ========= Errata 31 ========= */ +/* ========= Errata 30 ========= */ #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) - #define NRF54L_ERRATA_31_PRESENT 1 + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + #define NRF54L_ERRATA_30_PRESENT 1 #else - #define NRF54L_ERRATA_31_PRESENT 0 + #define NRF54L_ERRATA_30_PRESENT 0 #endif -#ifndef NRF54L_ERRATA_31_ENABLE_WORKAROUND - #define NRF54L_ERRATA_31_ENABLE_WORKAROUND NRF54L_ERRATA_31_PRESENT +#ifndef NRF54L_ERRATA_30_ENABLE_WORKAROUND + #define NRF54L_ERRATA_30_ENABLE_WORKAROUND NRF54L_ERRATA_30_PRESENT #endif -static bool nrf54l_errata_31(void) +static inline bool nrf54l_errata_30(void) { #ifndef NRF54L_SERIES return false; #else #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ - || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -1743,43 +1966,177 @@ static bool nrf54l_errata_31(void) case 0x01ul: return true; case 0x02ul: - return false; + return true; default: - return false; + return true; } } #endif - #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) - if (var1 == 0x2E) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) + if (var1 == 0x27) { switch(var2) { + case 0x00ul: + return true; case 0x01ul: return true; - case 0x02ul: - return false; default: - return false; + return true; } } #endif - #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) - if (var1 == 0x2F) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) + if (var1 == 0x29) { switch(var2) { + case 0x00ul: + return true; case 0x01ul: return true; - case 0x02ul: - return false; default: - return false; + return true; } } #endif - return false; - #endif -} + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 31 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + #define NRF54L_ERRATA_31_PRESENT 1 +#else + #define NRF54L_ERRATA_31_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_31_ENABLE_WORKAROUND + #define NRF54L_ERRATA_31_ENABLE_WORKAROUND NRF54L_ERRATA_31_PRESENT +#endif + +static inline bool nrf54l_errata_31(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} /* ========= Errata 32 ========= */ #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) @@ -1792,7 +2149,7 @@ static bool nrf54l_errata_31(void) #define NRF54L_ERRATA_32_ENABLE_WORKAROUND NRF54L_ERRATA_32_PRESENT #endif -static bool nrf54l_errata_32(void) +static inline bool nrf54l_errata_32(void) { #ifndef NRF54L_SERIES return false; @@ -1830,7 +2187,7 @@ static bool nrf54l_errata_32(void) #define NRF54L_ERRATA_33_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_33(void) +static inline bool nrf54l_errata_33(void) { #ifndef NRF54L_SERIES return false; @@ -1870,7 +2227,7 @@ static bool nrf54l_errata_33(void) #define NRF54L_ERRATA_35_ENABLE_WORKAROUND NRF54L_ERRATA_35_PRESENT #endif -static bool nrf54l_errata_35(void) +static inline bool nrf54l_errata_35(void) { #ifndef NRF54L_SERIES return false; @@ -1931,8 +2288,11 @@ static bool nrf54l_errata_35(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) #define NRF54L_ERRATA_37_PRESENT 1 #else #define NRF54L_ERRATA_37_PRESENT 0 @@ -1942,7 +2302,7 @@ static bool nrf54l_errata_35(void) #define NRF54L_ERRATA_37_ENABLE_WORKAROUND NRF54L_ERRATA_37_PRESENT #endif -static bool nrf54l_errata_37(void) +static inline bool nrf54l_errata_37(void) { #ifndef NRF54L_SERIES return false; @@ -1950,8 +2310,11 @@ static bool nrf54l_errata_37(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -1969,19 +2332,21 @@ static bool nrf54l_errata_37(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -2023,6 +2388,42 @@ static bool nrf54l_errata_37(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -2038,7 +2439,7 @@ static bool nrf54l_errata_37(void) #define NRF54L_ERRATA_38_ENABLE_WORKAROUND NRF54L_ERRATA_38_PRESENT #endif -static bool nrf54l_errata_38(void) +static inline bool nrf54l_errata_38(void) { #ifndef NRF54L_SERIES return false; @@ -2069,8 +2470,11 @@ static bool nrf54l_errata_38(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) #define NRF54L_ERRATA_39_PRESENT 1 #else #define NRF54L_ERRATA_39_PRESENT 0 @@ -2080,7 +2484,7 @@ static bool nrf54l_errata_38(void) #define NRF54L_ERRATA_39_ENABLE_WORKAROUND NRF54L_ERRATA_39_PRESENT #endif -static bool nrf54l_errata_39(void) +static inline bool nrf54l_errata_39(void) { #ifndef NRF54L_SERIES return false; @@ -2088,8 +2492,11 @@ static bool nrf54l_errata_39(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -2107,19 +2514,21 @@ static bool nrf54l_errata_39(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -2161,6 +2570,42 @@ static bool nrf54l_errata_39(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -2176,7 +2621,7 @@ static bool nrf54l_errata_39(void) #define NRF54L_ERRATA_40_ENABLE_WORKAROUND NRF54L_ERRATA_40_PRESENT #endif -static bool nrf54l_errata_40(void) +static inline bool nrf54l_errata_40(void) { #ifndef NRF54L_SERIES return false; @@ -2216,7 +2661,7 @@ static bool nrf54l_errata_40(void) #define NRF54L_ERRATA_41_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_41(void) +static inline bool nrf54l_errata_41(void) { #ifndef NRF54L_SERIES return false; @@ -2277,8 +2722,9 @@ static bool nrf54l_errata_41(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) #define NRF54L_ERRATA_42_PRESENT 1 #else #define NRF54L_ERRATA_42_PRESENT 0 @@ -2288,7 +2734,7 @@ static bool nrf54l_errata_41(void) #define NRF54L_ERRATA_42_ENABLE_WORKAROUND NRF54L_ERRATA_42_PRESENT #endif -static bool nrf54l_errata_42(void) +static inline bool nrf54l_errata_42(void) { #ifndef NRF54L_SERIES return false; @@ -2296,8 +2742,9 @@ static bool nrf54l_errata_42(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -2315,19 +2762,21 @@ static bool nrf54l_errata_42(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -2369,6 +2818,18 @@ static bool nrf54l_errata_42(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -2377,7 +2838,8 @@ static bool nrf54l_errata_42(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) #define NRF54L_ERRATA_43_PRESENT 1 #else #define NRF54L_ERRATA_43_PRESENT 0 @@ -2387,7 +2849,7 @@ static bool nrf54l_errata_42(void) #define NRF54L_ERRATA_43_ENABLE_WORKAROUND NRF54L_ERRATA_43_PRESENT #endif -static bool nrf54l_errata_43(void) +static inline bool nrf54l_errata_43(void) { #ifndef NRF54L_SERIES return false; @@ -2395,7 +2857,8 @@ static bool nrf54l_errata_43(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -2413,7 +2876,7 @@ static bool nrf54l_errata_43(void) } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -2455,6 +2918,18 @@ static bool nrf54l_errata_43(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -2463,8 +2938,11 @@ static bool nrf54l_errata_43(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) #define NRF54L_ERRATA_44_PRESENT 1 #else #define NRF54L_ERRATA_44_PRESENT 0 @@ -2474,7 +2952,7 @@ static bool nrf54l_errata_43(void) #define NRF54L_ERRATA_44_ENABLE_WORKAROUND NRF54L_ERRATA_44_PRESENT #endif -static bool nrf54l_errata_44(void) +static inline bool nrf54l_errata_44(void) { #ifndef NRF54L_SERIES return false; @@ -2482,8 +2960,11 @@ static bool nrf54l_errata_44(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -2501,19 +2982,21 @@ static bool nrf54l_errata_44(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -2555,6 +3038,42 @@ static bool nrf54l_errata_44(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -2563,8 +3082,11 @@ static bool nrf54l_errata_44(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) #define NRF54L_ERRATA_45_PRESENT 1 #else #define NRF54L_ERRATA_45_PRESENT 0 @@ -2574,7 +3096,7 @@ static bool nrf54l_errata_44(void) #define NRF54L_ERRATA_45_ENABLE_WORKAROUND NRF54L_ERRATA_45_PRESENT #endif -static bool nrf54l_errata_45(void) +static inline bool nrf54l_errata_45(void) { #ifndef NRF54L_SERIES return false; @@ -2582,8 +3104,11 @@ static bool nrf54l_errata_45(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -2601,19 +3126,21 @@ static bool nrf54l_errata_45(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -2655,12 +3182,48 @@ static bool nrf54l_errata_45(void) } } #endif - return false; - #endif -} - -/* ========= Errata 46 ========= */ -#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 46 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) #define NRF54L_ERRATA_46_PRESENT 1 @@ -2672,7 +3235,7 @@ static bool nrf54l_errata_45(void) #define NRF54L_ERRATA_46_ENABLE_WORKAROUND NRF54L_ERRATA_46_PRESENT #endif -static bool nrf54l_errata_46(void) +static inline bool nrf54l_errata_46(void) { #ifndef NRF54L_SERIES return false; @@ -2733,17 +3296,18 @@ static bool nrf54l_errata_46(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) #define NRF54L_ERRATA_47_PRESENT 1 #else #define NRF54L_ERRATA_47_PRESENT 0 #endif #ifndef NRF54L_ERRATA_47_ENABLE_WORKAROUND - #define NRF54L_ERRATA_47_ENABLE_WORKAROUND NRF54L_ERRATA_47_PRESENT + #define NRF54L_ERRATA_47_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_47(void) +static inline bool nrf54l_errata_47(void) { #ifndef NRF54L_SERIES return false; @@ -2751,7 +3315,8 @@ static bool nrf54l_errata_47(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -2769,7 +3334,7 @@ static bool nrf54l_errata_47(void) } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -2811,6 +3376,18 @@ static bool nrf54l_errata_47(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -2828,7 +3405,7 @@ static bool nrf54l_errata_47(void) #define NRF54L_ERRATA_48_ENABLE_WORKAROUND NRF54L_ERRATA_48_PRESENT #endif -static bool nrf54l_errata_48(void) +static inline bool nrf54l_errata_48(void) { #ifndef NRF54L_SERIES return false; @@ -2889,8 +3466,11 @@ static bool nrf54l_errata_48(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) #define NRF54L_ERRATA_49_PRESENT 1 #else #define NRF54L_ERRATA_49_PRESENT 0 @@ -2900,7 +3480,7 @@ static bool nrf54l_errata_48(void) #define NRF54L_ERRATA_49_ENABLE_WORKAROUND NRF54L_ERRATA_49_PRESENT #endif -static bool nrf54l_errata_49(void) +static inline bool nrf54l_errata_49(void) { #ifndef NRF54L_SERIES return false; @@ -2908,8 +3488,11 @@ static bool nrf54l_errata_49(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -2927,19 +3510,21 @@ static bool nrf54l_errata_49(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -2981,6 +3566,42 @@ static bool nrf54l_errata_49(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -2989,7 +3610,8 @@ static bool nrf54l_errata_49(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) #define NRF54L_ERRATA_50_PRESENT 1 #else #define NRF54L_ERRATA_50_PRESENT 0 @@ -2999,7 +3621,7 @@ static bool nrf54l_errata_49(void) #define NRF54L_ERRATA_50_ENABLE_WORKAROUND NRF54L_ERRATA_50_PRESENT #endif -static bool nrf54l_errata_50(void) +static inline bool nrf54l_errata_50(void) { #ifndef NRF54L_SERIES return false; @@ -3007,7 +3629,8 @@ static bool nrf54l_errata_50(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -3025,7 +3648,7 @@ static bool nrf54l_errata_50(void) } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3067,13 +3690,98 @@ static bool nrf54l_errata_50(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 54 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + #define NRF54L_ERRATA_54_PRESENT 1 +#else + #define NRF54L_ERRATA_54_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_54_ENABLE_WORKAROUND + #define NRF54L_ERRATA_54_ENABLE_WORKAROUND 0 +#endif + +static inline bool nrf54l_errata_54(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif return false; #endif } /* ========= Errata 55 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) #define NRF54L_ERRATA_55_PRESENT 1 #else #define NRF54L_ERRATA_55_PRESENT 0 @@ -3083,29 +3791,34 @@ static bool nrf54l_errata_50(void) #define NRF54L_ERRATA_55_ENABLE_WORKAROUND NRF54L_ERRATA_55_PRESENT #endif -static bool nrf54l_errata_55(void) +static inline bool nrf54l_errata_55(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3115,7 +3828,43 @@ static bool nrf54l_errata_55(void) case 0x01ul: return true; default: - return false; + return true; + } + } + #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; } } #endif @@ -3136,7 +3885,7 @@ static bool nrf54l_errata_55(void) #define NRF54L_CONFIGURATION_56_ENABLE NRF54L_CONFIGURATION_56_PRESENT #endif -static bool nrf54l_configuration_56(void) +static inline bool nrf54l_configuration_56(void) { #ifndef NRF54L_SERIES return false; @@ -3194,8 +3943,9 @@ static bool nrf54l_configuration_56(void) } /* ========= Errata 57 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) #define NRF54L_ERRATA_57_PRESENT 1 #else #define NRF54L_ERRATA_57_PRESENT 0 @@ -3205,29 +3955,32 @@ static bool nrf54l_configuration_56(void) #define NRF54L_ERRATA_57_ENABLE_WORKAROUND NRF54L_ERRATA_57_PRESENT #endif -static bool nrf54l_errata_57(void) +static inline bool nrf54l_errata_57(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3241,25 +3994,37 @@ static bool nrf54l_errata_57(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif return false; #endif } -/* ========= Errata 60 ========= */ +/* ========= Errata 58 ========= */ #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) - #define NRF54L_ERRATA_60_PRESENT 1 + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) + #define NRF54L_ERRATA_58_PRESENT 1 #else - #define NRF54L_ERRATA_60_PRESENT 0 + #define NRF54L_ERRATA_58_PRESENT 0 #endif -#ifndef NRF54L_ERRATA_60_ENABLE_WORKAROUND - #define NRF54L_ERRATA_60_ENABLE_WORKAROUND NRF54L_ERRATA_60_PRESENT +#ifndef NRF54L_ERRATA_58_ENABLE_WORKAROUND + #define NRF54L_ERRATA_58_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_60(void) +static inline bool nrf54l_errata_58(void) { #ifndef NRF54L_SERIES return false; @@ -3267,7 +4032,7 @@ static bool nrf54l_errata_60(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -3285,8 +4050,8 @@ static bool nrf54l_errata_60(void) } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) - if (var1 == 0x29) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) + if (var1 == 0x27) { switch(var2) { @@ -3331,22 +4096,24 @@ static bool nrf54l_errata_60(void) #endif } -/* ========= Errata 61 ========= */ +/* ========= Errata 59 ========= */ #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) - #define NRF54L_ERRATA_61_PRESENT 1 + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) + #define NRF54L_ERRATA_59_PRESENT 1 #else - #define NRF54L_ERRATA_61_PRESENT 0 + #define NRF54L_ERRATA_59_PRESENT 0 #endif -#ifndef NRF54L_ERRATA_61_ENABLE_WORKAROUND - #define NRF54L_ERRATA_61_ENABLE_WORKAROUND NRF54L_ERRATA_61_PRESENT +#ifndef NRF54L_ERRATA_59_ENABLE_WORKAROUND + #define NRF54L_ERRATA_59_ENABLE_WORKAROUND NRF54L_ERRATA_59_PRESENT #endif -static bool nrf54l_errata_61(void) +static inline bool nrf54l_errata_59(void) { #ifndef NRF54L_SERIES return false; @@ -3354,8 +4121,10 @@ static bool nrf54l_errata_61(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -3373,19 +4142,21 @@ static bool nrf54l_errata_61(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return false; default: - return true; + return false; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3393,9 +4164,9 @@ static bool nrf54l_errata_61(void) case 0x00ul: return true; case 0x01ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -3427,25 +4198,53 @@ static bool nrf54l_errata_61(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif return false; #endif } -/* ========= Errata 63 ========= */ +/* ========= Errata 60 ========= */ #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) - #define NRF54L_ERRATA_63_PRESENT 1 + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + #define NRF54L_ERRATA_60_PRESENT 1 #else - #define NRF54L_ERRATA_63_PRESENT 0 + #define NRF54L_ERRATA_60_PRESENT 0 #endif -#ifndef NRF54L_ERRATA_63_ENABLE_WORKAROUND - #define NRF54L_ERRATA_63_ENABLE_WORKAROUND NRF54L_ERRATA_63_PRESENT +#ifndef NRF54L_ERRATA_60_ENABLE_WORKAROUND + #define NRF54L_ERRATA_60_ENABLE_WORKAROUND NRF54L_ERRATA_60_PRESENT #endif -static bool nrf54l_errata_63(void) +static inline bool nrf54l_errata_60(void) { #ifndef NRF54L_SERIES return false; @@ -3453,7 +4252,11 @@ static bool nrf54l_errata_63(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -3471,7 +4274,21 @@ static bool nrf54l_errata_63(void) } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) + if (var1 == 0x27) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3513,12 +4330,192 @@ static bool nrf54l_errata_63(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 63 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + #define NRF54L_ERRATA_63_PRESENT 1 +#else + #define NRF54L_ERRATA_63_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_63_ENABLE_WORKAROUND + #define NRF54L_ERRATA_63_ENABLE_WORKAROUND NRF54L_ERRATA_63_PRESENT +#endif + +static inline bool nrf54l_errata_63(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) + if (var1 == 0x27) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif return false; #endif } /* ========= Errata 65 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_65_PRESENT 1 #else #define NRF54L_ERRATA_65_PRESENT 0 @@ -3528,16 +4525,16 @@ static bool nrf54l_errata_63(void) #define NRF54L_ERRATA_65_ENABLE_WORKAROUND NRF54L_ERRATA_65_PRESENT #endif -static bool nrf54l_errata_65(void) +static inline bool nrf54l_errata_65(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3556,7 +4553,7 @@ static bool nrf54l_errata_65(void) } /* ========= Errata 66 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_66_PRESENT 1 #else #define NRF54L_ERRATA_66_PRESENT 0 @@ -3566,16 +4563,16 @@ static bool nrf54l_errata_65(void) #define NRF54L_ERRATA_66_ENABLE_WORKAROUND NRF54L_ERRATA_66_PRESENT #endif -static bool nrf54l_errata_66(void) +static inline bool nrf54l_errata_66(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3597,8 +4594,8 @@ static bool nrf54l_errata_66(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) #define NRF54L_ERRATA_68_PRESENT 1 #else #define NRF54L_ERRATA_68_PRESENT 0 @@ -3608,7 +4605,7 @@ static bool nrf54l_errata_66(void) #define NRF54L_ERRATA_68_ENABLE_WORKAROUND NRF54L_ERRATA_68_PRESENT #endif -static bool nrf54l_errata_68(void) +static inline bool nrf54l_errata_68(void) { #ifndef NRF54L_SERIES return false; @@ -3616,8 +4613,8 @@ static bool nrf54l_errata_68(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -3635,19 +4632,21 @@ static bool nrf54l_errata_68(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return false; default: - return true; + return false; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3694,8 +4693,11 @@ static bool nrf54l_errata_68(void) } /* ========= Errata 69 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) #define NRF54L_ERRATA_69_PRESENT 1 #else #define NRF54L_ERRATA_69_PRESENT 0 @@ -3705,29 +4707,34 @@ static bool nrf54l_errata_68(void) #define NRF54L_ERRATA_69_ENABLE_WORKAROUND NRF54L_ERRATA_69_PRESENT #endif -static bool nrf54l_errata_69(void) +static inline bool nrf54l_errata_69(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3741,12 +4748,49 @@ static bool nrf54l_errata_69(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif return false; #endif } /* ========= Errata 70 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) #define NRF54L_ERRATA_70_PRESENT 1 #else #define NRF54L_ERRATA_70_PRESENT 0 @@ -3756,16 +4800,17 @@ static bool nrf54l_errata_69(void) #define NRF54L_ERRATA_70_ENABLE_WORKAROUND NRF54L_ERRATA_70_PRESENT #endif -static bool nrf54l_errata_70(void) +static inline bool nrf54l_errata_70(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3779,12 +4824,25 @@ static bool nrf54l_errata_70(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif return false; #endif } /* ========= Errata 71 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) #define NRF54L_ERRATA_71_PRESENT 1 #else #define NRF54L_ERRATA_71_PRESENT 0 @@ -3794,16 +4852,17 @@ static bool nrf54l_errata_70(void) #define NRF54L_ERRATA_71_ENABLE_WORKAROUND NRF54L_ERRATA_71_PRESENT #endif -static bool nrf54l_errata_71(void) +static inline bool nrf54l_errata_71(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3817,6 +4876,18 @@ static bool nrf54l_errata_71(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -3825,8 +4896,9 @@ static bool nrf54l_errata_71(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) #define NRF54L_ERRATA_72_PRESENT 1 #else #define NRF54L_ERRATA_72_PRESENT 0 @@ -3836,7 +4908,7 @@ static bool nrf54l_errata_71(void) #define NRF54L_ERRATA_72_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_72(void) +static inline bool nrf54l_errata_72(void) { #ifndef NRF54L_SERIES return false; @@ -3844,8 +4916,9 @@ static bool nrf54l_errata_72(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -3863,19 +4936,21 @@ static bool nrf54l_errata_72(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; default: return true; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -3917,6 +4992,18 @@ static bool nrf54l_errata_72(void) } } #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -3925,8 +5012,8 @@ static bool nrf54l_errata_72(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) \ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) #define NRF54L_ERRATA_73_PRESENT 1 #else #define NRF54L_ERRATA_73_PRESENT 0 @@ -3936,7 +5023,7 @@ static bool nrf54l_errata_72(void) #define NRF54L_ERRATA_73_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_73(void) +static inline bool nrf54l_errata_73(void) { #ifndef NRF54L_SERIES return false; @@ -3944,8 +5031,8 @@ static bool nrf54l_errata_73(void) #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ - || defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA)\ - || defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif @@ -3963,19 +5050,21 @@ static bool nrf54l_errata_73(void) } } #endif - #if defined (NRF54LV10A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LV10A_ENGA) + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) if (var1 == 0x27) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return false; default: - return true; + return false; } } #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4022,7 +5111,7 @@ static bool nrf54l_errata_73(void) } /* ========= Errata 74 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_74_PRESENT 1 #else #define NRF54L_ERRATA_74_PRESENT 0 @@ -4032,16 +5121,16 @@ static bool nrf54l_errata_73(void) #define NRF54L_ERRATA_74_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_74(void) +static inline bool nrf54l_errata_74(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4060,7 +5149,7 @@ static bool nrf54l_errata_74(void) } /* ========= Errata 78 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_78_PRESENT 1 #else #define NRF54L_ERRATA_78_PRESENT 0 @@ -4070,16 +5159,16 @@ static bool nrf54l_errata_74(void) #define NRF54L_ERRATA_78_ENABLE_WORKAROUND NRF54L_ERRATA_78_PRESENT #endif -static bool nrf54l_errata_78(void) +static inline bool nrf54l_errata_78(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4098,7 +5187,7 @@ static bool nrf54l_errata_78(void) } /* ========= Errata 79 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_79_PRESENT 1 #else #define NRF54L_ERRATA_79_PRESENT 0 @@ -4108,16 +5197,16 @@ static bool nrf54l_errata_78(void) #define NRF54L_ERRATA_79_ENABLE_WORKAROUND NRF54L_ERRATA_79_PRESENT #endif -static bool nrf54l_errata_79(void) +static inline bool nrf54l_errata_79(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4136,7 +5225,7 @@ static bool nrf54l_errata_79(void) } /* ========= Errata 81 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_81_PRESENT 1 #else #define NRF54L_ERRATA_81_PRESENT 0 @@ -4146,16 +5235,16 @@ static bool nrf54l_errata_79(void) #define NRF54L_ERRATA_81_ENABLE_WORKAROUND NRF54L_ERRATA_81_PRESENT #endif -static bool nrf54l_errata_81(void) +static inline bool nrf54l_errata_81(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4174,7 +5263,7 @@ static bool nrf54l_errata_81(void) } /* ========= Errata 83 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_83_PRESENT 1 #else #define NRF54L_ERRATA_83_PRESENT 0 @@ -4184,16 +5273,16 @@ static bool nrf54l_errata_81(void) #define NRF54L_ERRATA_83_ENABLE_WORKAROUND NRF54L_ERRATA_83_PRESENT #endif -static bool nrf54l_errata_83(void) +static inline bool nrf54l_errata_83(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4212,7 +5301,7 @@ static bool nrf54l_errata_83(void) } /* ========= Errata 85 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_85_PRESENT 1 #else #define NRF54L_ERRATA_85_PRESENT 0 @@ -4222,16 +5311,16 @@ static bool nrf54l_errata_83(void) #define NRF54L_ERRATA_85_ENABLE_WORKAROUND NRF54L_ERRATA_85_PRESENT #endif -static bool nrf54l_errata_85(void) +static inline bool nrf54l_errata_85(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4250,7 +5339,7 @@ static bool nrf54l_errata_85(void) } /* ========= Errata 86 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_86_PRESENT 1 #else #define NRF54L_ERRATA_86_PRESENT 0 @@ -4260,16 +5349,16 @@ static bool nrf54l_errata_85(void) #define NRF54L_ERRATA_86_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_86(void) +static inline bool nrf54l_errata_86(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4288,7 +5377,7 @@ static bool nrf54l_errata_86(void) } /* ========= Errata 87 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_87_PRESENT 1 #else #define NRF54L_ERRATA_87_PRESENT 0 @@ -4298,16 +5387,16 @@ static bool nrf54l_errata_86(void) #define NRF54L_ERRATA_87_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_87(void) +static inline bool nrf54l_errata_87(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4326,7 +5415,7 @@ static bool nrf54l_errata_87(void) } /* ========= Errata 88 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_88_PRESENT 1 #else #define NRF54L_ERRATA_88_PRESENT 0 @@ -4336,16 +5425,16 @@ static bool nrf54l_errata_87(void) #define NRF54L_ERRATA_88_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_88(void) +static inline bool nrf54l_errata_88(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4364,7 +5453,7 @@ static bool nrf54l_errata_88(void) } /* ========= Errata 89 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_89_PRESENT 1 #else #define NRF54L_ERRATA_89_PRESENT 0 @@ -4374,16 +5463,16 @@ static bool nrf54l_errata_88(void) #define NRF54L_ERRATA_89_ENABLE_WORKAROUND NRF54L_ERRATA_89_PRESENT #endif -static bool nrf54l_errata_89(void) +static inline bool nrf54l_errata_89(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4402,7 +5491,7 @@ static bool nrf54l_errata_89(void) } /* ========= Errata 90 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_90_PRESENT 1 #else #define NRF54L_ERRATA_90_PRESENT 0 @@ -4412,16 +5501,16 @@ static bool nrf54l_errata_89(void) #define NRF54L_ERRATA_90_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_90(void) +static inline bool nrf54l_errata_90(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4440,7 +5529,7 @@ static bool nrf54l_errata_90(void) } /* ========= Errata 91 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_91_PRESENT 1 #else #define NRF54L_ERRATA_91_PRESENT 0 @@ -4450,16 +5539,16 @@ static bool nrf54l_errata_90(void) #define NRF54L_ERRATA_91_ENABLE_WORKAROUND NRF54L_ERRATA_91_PRESENT #endif -static bool nrf54l_errata_91(void) +static inline bool nrf54l_errata_91(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4478,7 +5567,7 @@ static bool nrf54l_errata_91(void) } /* ========= Errata 92 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_92_PRESENT 1 #else #define NRF54L_ERRATA_92_PRESENT 0 @@ -4488,16 +5577,16 @@ static bool nrf54l_errata_91(void) #define NRF54L_ERRATA_92_ENABLE_WORKAROUND NRF54L_ERRATA_92_PRESENT #endif -static bool nrf54l_errata_92(void) +static inline bool nrf54l_errata_92(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4516,7 +5605,7 @@ static bool nrf54l_errata_92(void) } /* ========= Errata 93 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_93_PRESENT 1 #else #define NRF54L_ERRATA_93_PRESENT 0 @@ -4526,16 +5615,16 @@ static bool nrf54l_errata_92(void) #define NRF54L_ERRATA_93_ENABLE_WORKAROUND NRF54L_ERRATA_93_PRESENT #endif -static bool nrf54l_errata_93(void) +static inline bool nrf54l_errata_93(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4554,7 +5643,7 @@ static bool nrf54l_errata_93(void) } /* ========= Errata 94 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_94_PRESENT 1 #else #define NRF54L_ERRATA_94_PRESENT 0 @@ -4564,16 +5653,16 @@ static bool nrf54l_errata_93(void) #define NRF54L_ERRATA_94_ENABLE_WORKAROUND NRF54L_ERRATA_94_PRESENT #endif -static bool nrf54l_errata_94(void) +static inline bool nrf54l_errata_94(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4592,7 +5681,7 @@ static bool nrf54l_errata_94(void) } /* ========= Errata 95 ========= */ -#if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) #define NRF54L_ERRATA_95_PRESENT 1 #else #define NRF54L_ERRATA_95_PRESENT 0 @@ -4602,16 +5691,16 @@ static bool nrf54l_errata_94(void) #define NRF54L_ERRATA_95_ENABLE_WORKAROUND 0 #endif -static bool nrf54l_errata_95(void) +static inline bool nrf54l_errata_95(void) { #ifndef NRF54L_SERIES return false; #else - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) uint32_t var1 = *(uint32_t *)0x00FFC340ul; uint32_t var2 = *(uint32_t *)0x00FFC344ul; #endif - #if defined (NRF54LM20A_ENGA_XXAA) || defined (DEVELOP_IN_NRF54LM20A_ENGA) + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) if (var1 == 0x29) { switch(var2) @@ -4629,4 +5718,778 @@ static bool nrf54l_errata_95(void) #endif } +/* ========= Errata 100 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + #define NRF54L_ERRATA_100_PRESENT 1 +#else + #define NRF54L_ERRATA_100_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_100_ENABLE_WORKAROUND + #define NRF54L_ERRATA_100_ENABLE_WORKAROUND 0 +#endif + +static inline bool nrf54l_errata_100(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 102 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) + #define NRF54L_ERRATA_102_PRESENT 1 +#else + #define NRF54L_ERRATA_102_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_102_ENABLE_WORKAROUND + #define NRF54L_ERRATA_102_ENABLE_WORKAROUND NRF54L_ERRATA_102_PRESENT +#endif + +static inline bool nrf54l_errata_102(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) + if (var1 == 0x27) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 103 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + #define NRF54L_ERRATA_103_PRESENT 1 +#else + #define NRF54L_ERRATA_103_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_103_ENABLE_WORKAROUND + #define NRF54L_ERRATA_103_ENABLE_WORKAROUND 0 +#endif + +static inline bool nrf54l_errata_103(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 104 ========= */ +#if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + #define NRF54L_ERRATA_104_PRESENT 1 +#else + #define NRF54L_ERRATA_104_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_104_ENABLE_WORKAROUND + #define NRF54L_ERRATA_104_ENABLE_WORKAROUND 0 +#endif + +static inline bool nrf54l_errata_104(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 105 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + #define NRF54L_ERRATA_105_PRESENT 1 +#else + #define NRF54L_ERRATA_105_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_105_ENABLE_WORKAROUND + #define NRF54L_ERRATA_105_ENABLE_WORKAROUND NRF54L_ERRATA_105_PRESENT +#endif + +static inline bool nrf54l_errata_105(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) + if (var1 == 0x27) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 106 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + #define NRF54L_ERRATA_106_PRESENT 1 +#else + #define NRF54L_ERRATA_106_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_106_ENABLE_WORKAROUND + #define NRF54L_ERRATA_106_ENABLE_WORKAROUND 0 +#endif + +static inline bool nrf54l_errata_106(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 115 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) \ + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) \ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) \ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) \ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) \ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + #define NRF54L_ERRATA_115_PRESENT 1 +#else + #define NRF54L_ERRATA_115_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_115_ENABLE_WORKAROUND + #define NRF54L_ERRATA_115_ENABLE_WORKAROUND NRF54L_ERRATA_115_PRESENT +#endif + +static inline bool nrf54l_errata_115(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15)\ + || defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A)\ + || defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B)\ + || defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B)\ + || defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A)\ + || defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LV10A_XXAA) || defined (DEVELOP_IN_NRF54LV10A) + if (var1 == 0x27) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20A_XXAA) || defined (DEVELOP_IN_NRF54LM20A) + if (var1 == 0x29) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LM20B_XXAA) || defined (DEVELOP_IN_NRF54LM20B) + if (var1 == 0x33) + { + switch(var2) + { + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05B_XXAA) || defined (DEVELOP_IN_NRF54LS05B) + if (var1 == 0x34) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54LS05A_XXAA) || defined (DEVELOP_IN_NRF54LS05A) + if (var1 == 0x36) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 116 ========= */ +#if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) \ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) \ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + #define NRF54L_ERRATA_116_PRESENT 1 +#else + #define NRF54L_ERRATA_116_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_116_ENABLE_WORKAROUND + #define NRF54L_ERRATA_116_ENABLE_WORKAROUND NRF54L_ERRATA_116_PRESENT +#endif + +static inline bool nrf54l_errata_116(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05)\ + || defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10)\ + || defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L10_XXAA) || defined (DEVELOP_IN_NRF54L10) + if (var1 == 0x2E) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF54L05_XXAA) || defined (DEVELOP_IN_NRF54L05) + if (var1 == 0x2F) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 121 ========= */ +#if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + #define NRF54L_ERRATA_121_PRESENT 1 +#else + #define NRF54L_ERRATA_121_PRESENT 0 +#endif + +#ifndef NRF54L_ERRATA_121_ENABLE_WORKAROUND + #define NRF54L_ERRATA_121_ENABLE_WORKAROUND NRF54L_ERRATA_121_PRESENT +#endif + +static inline bool nrf54l_errata_121(void) +{ + #ifndef NRF54L_SERIES + return false; + #else + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + uint32_t var1 = *(uint32_t *)0x00FFC340ul; + uint32_t var2 = *(uint32_t *)0x00FFC344ul; + #endif + #if defined (NRF54L15_XXAA) || defined (DEVELOP_IN_NRF54L15) + if (var1 == 0x1C) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + #endif /* NRF54L_ERRATAS_H */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a.h new file mode 100644 index 0000000..a8be168 --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a.h @@ -0,0 +1,52 @@ +/* + +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF54LM20A_H +#define NRF54LM20A_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "nrf54lm20a_types.h" + +#include "nrf54lm20a_global.h" +#include "nrf54lm20a_application.h" +#include "nrf54lm20a_flpr.h" + +#ifdef __cplusplus +} +#endif +#endif /* NRF54LM20A_H */ + diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_application.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_application.h new file mode 100644 index 0000000..203500c --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_application.h @@ -0,0 +1,364 @@ +/* + +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF54LM20A_APPLICATION_H +#define NRF54LM20A_APPLICATION_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#ifdef NRF_APPLICATION /*!< Processor information is domain local. */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ===================================================== Core Interrupts ===================================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No + Match*/ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault*/ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ============================================== Processor Specific Interrupts ============================================== */ + SWI00_IRQn = 28, /*!< 28 SWI00 */ + SWI01_IRQn = 29, /*!< 29 SWI01 */ + SWI02_IRQn = 30, /*!< 30 SWI02 */ + SWI03_IRQn = 31, /*!< 31 SWI03 */ + SPU00_IRQn = 64, /*!< 64 SPU00 */ + MPC00_IRQn = 65, /*!< 65 MPC00 */ + AAR00_CCM00_IRQn = 74, /*!< 74 AAR00_CCM00 */ + ECB00_IRQn = 75, /*!< 75 ECB00 */ + VPR00_IRQn = 76, /*!< 76 VPR00 */ + SERIAL00_IRQn = 77, /*!< 77 SERIAL00 */ + RRAMC_IRQn = 78, /*!< 78 RRAMC */ + CTRLAP_IRQn = 82, /*!< 82 CTRLAP */ + CM33SS_IRQn = 84, /*!< 84 CM33SS */ + TIMER00_IRQn = 85, /*!< 85 TIMER00 */ + EGU00_IRQn = 88, /*!< 88 EGU00 */ + CRACEN_IRQn = 89, /*!< 89 CRACEN */ + USBHS_IRQn = 90, /*!< 90 USBHS */ + SPU10_IRQn = 128, /*!< 128 SPU10 */ + TIMER10_IRQn = 133, /*!< 133 TIMER10 */ + EGU10_IRQn = 135, /*!< 135 EGU10 */ + RADIO_0_IRQn = 138, /*!< 138 RADIO_0 */ + RADIO_1_IRQn = 139, /*!< 139 RADIO_1 */ + SPU20_IRQn = 192, /*!< 192 SPU20 */ + SERIAL20_IRQn = 198, /*!< 198 SERIAL20 */ + SERIAL21_IRQn = 199, /*!< 199 SERIAL21 */ + SERIAL22_IRQn = 200, /*!< 200 SERIAL22 */ + EGU20_IRQn = 201, /*!< 201 EGU20 */ + TIMER20_IRQn = 202, /*!< 202 TIMER20 */ + TIMER21_IRQn = 203, /*!< 203 TIMER21 */ + TIMER22_IRQn = 204, /*!< 204 TIMER22 */ + TIMER23_IRQn = 205, /*!< 205 TIMER23 */ + TIMER24_IRQn = 206, /*!< 206 TIMER24 */ + PDM20_IRQn = 208, /*!< 208 PDM20 */ + PDM21_IRQn = 209, /*!< 209 PDM21 */ + PWM20_IRQn = 210, /*!< 210 PWM20 */ + PWM21_IRQn = 211, /*!< 211 PWM21 */ + PWM22_IRQn = 212, /*!< 212 PWM22 */ + SAADC_IRQn = 213, /*!< 213 SAADC */ + NFCT_IRQn = 214, /*!< 214 NFCT */ + TEMP_IRQn = 215, /*!< 215 TEMP */ + GPIOTE20_0_IRQn = 218, /*!< 218 GPIOTE20_0 */ + GPIOTE20_1_IRQn = 219, /*!< 219 GPIOTE20_1 */ + QDEC20_IRQn = 224, /*!< 224 QDEC20 */ + QDEC21_IRQn = 225, /*!< 225 QDEC21 */ + GRTC_0_IRQn = 226, /*!< 226 GRTC_0 */ + GRTC_1_IRQn = 227, /*!< 227 GRTC_1 */ + GRTC_2_IRQn = 228, /*!< 228 GRTC_2 */ + GRTC_3_IRQn = 229, /*!< 229 GRTC_3 */ + TDM_IRQn = 232, /*!< 232 TDM */ + SERIAL23_IRQn = 237, /*!< 237 SERIAL23 */ + SERIAL24_IRQn = 238, /*!< 238 SERIAL24 */ + TAMPC_IRQn = 239, /*!< 239 TAMPC */ + SPU30_IRQn = 256, /*!< 256 SPU30 */ + SERIAL30_IRQn = 260, /*!< 260 SERIAL30 */ + COMP_LPCOMP_IRQn = 262, /*!< 262 COMP_LPCOMP */ + WDT30_IRQn = 264, /*!< 264 WDT30 */ + WDT31_IRQn = 265, /*!< 265 WDT31 */ + GPIOTE30_0_IRQn = 268, /*!< 268 GPIOTE30_0 */ + GPIOTE30_1_IRQn = 269, /*!< 269 GPIOTE30_1 */ + CLOCK_POWER_IRQn = 270, /*!< 270 CLOCK_POWER */ + VREGUSB_IRQn = 289, /*!< 289 VREGUSB */ +} IRQn_Type; + +/* ==================================================== Interrupt Aliases ==================================================== */ +#define AAR00_IRQn AAR00_CCM00_IRQn +#define AAR00_IRQHandler AAR00_CCM00_IRQHandler +#define CCM00_IRQn AAR00_CCM00_IRQn +#define CCM00_IRQHandler AAR00_CCM00_IRQHandler +#define SPIM00_IRQn SERIAL00_IRQn +#define SPIM00_IRQHandler SERIAL00_IRQHandler +#define SPIS00_IRQn SERIAL00_IRQn +#define SPIS00_IRQHandler SERIAL00_IRQHandler +#define UARTE00_IRQn SERIAL00_IRQn +#define UARTE00_IRQHandler SERIAL00_IRQHandler +#define CPUC_IRQn CM33SS_IRQn +#define CPUC_IRQHandler CM33SS_IRQHandler +#define SPIM20_IRQn SERIAL20_IRQn +#define SPIM20_IRQHandler SERIAL20_IRQHandler +#define SPIS20_IRQn SERIAL20_IRQn +#define SPIS20_IRQHandler SERIAL20_IRQHandler +#define TWIM20_IRQn SERIAL20_IRQn +#define TWIM20_IRQHandler SERIAL20_IRQHandler +#define TWIS20_IRQn SERIAL20_IRQn +#define TWIS20_IRQHandler SERIAL20_IRQHandler +#define UARTE20_IRQn SERIAL20_IRQn +#define UARTE20_IRQHandler SERIAL20_IRQHandler +#define SPIM21_IRQn SERIAL21_IRQn +#define SPIM21_IRQHandler SERIAL21_IRQHandler +#define SPIS21_IRQn SERIAL21_IRQn +#define SPIS21_IRQHandler SERIAL21_IRQHandler +#define TWIM21_IRQn SERIAL21_IRQn +#define TWIM21_IRQHandler SERIAL21_IRQHandler +#define TWIS21_IRQn SERIAL21_IRQn +#define TWIS21_IRQHandler SERIAL21_IRQHandler +#define UARTE21_IRQn SERIAL21_IRQn +#define UARTE21_IRQHandler SERIAL21_IRQHandler +#define SPIM22_IRQn SERIAL22_IRQn +#define SPIM22_IRQHandler SERIAL22_IRQHandler +#define SPIS22_IRQn SERIAL22_IRQn +#define SPIS22_IRQHandler SERIAL22_IRQHandler +#define TWIM22_IRQn SERIAL22_IRQn +#define TWIM22_IRQHandler SERIAL22_IRQHandler +#define TWIS22_IRQn SERIAL22_IRQn +#define TWIS22_IRQHandler SERIAL22_IRQHandler +#define UARTE22_IRQn SERIAL22_IRQn +#define UARTE22_IRQHandler SERIAL22_IRQHandler +#define SPIM23_IRQn SERIAL23_IRQn +#define SPIM23_IRQHandler SERIAL23_IRQHandler +#define SPIS23_IRQn SERIAL23_IRQn +#define SPIS23_IRQHandler SERIAL23_IRQHandler +#define TWIM23_IRQn SERIAL23_IRQn +#define TWIM23_IRQHandler SERIAL23_IRQHandler +#define TWIS23_IRQn SERIAL23_IRQn +#define TWIS23_IRQHandler SERIAL23_IRQHandler +#define UARTE23_IRQn SERIAL23_IRQn +#define UARTE23_IRQHandler SERIAL23_IRQHandler +#define SPIM24_IRQn SERIAL24_IRQn +#define SPIM24_IRQHandler SERIAL24_IRQHandler +#define SPIS24_IRQn SERIAL24_IRQn +#define SPIS24_IRQHandler SERIAL24_IRQHandler +#define TWIM24_IRQn SERIAL24_IRQn +#define TWIM24_IRQHandler SERIAL24_IRQHandler +#define TWIS24_IRQn SERIAL24_IRQn +#define TWIS24_IRQHandler SERIAL24_IRQHandler +#define UARTE24_IRQn SERIAL24_IRQn +#define UARTE24_IRQHandler SERIAL24_IRQHandler +#define SPIM30_IRQn SERIAL30_IRQn +#define SPIM30_IRQHandler SERIAL30_IRQHandler +#define SPIS30_IRQn SERIAL30_IRQn +#define SPIS30_IRQHandler SERIAL30_IRQHandler +#define TWIM30_IRQn SERIAL30_IRQn +#define TWIM30_IRQHandler SERIAL30_IRQHandler +#define TWIS30_IRQn SERIAL30_IRQn +#define TWIS30_IRQHandler SERIAL30_IRQHandler +#define UARTE30_IRQn SERIAL30_IRQn +#define UARTE30_IRQHandler SERIAL30_IRQHandler +#define COMP_IRQn COMP_LPCOMP_IRQn +#define COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define CLOCK_IRQn CLOCK_POWER_IRQn +#define CLOCK_IRQHandler CLOCK_POWER_IRQHandler +#define POWER_IRQn CLOCK_POWER_IRQn +#define POWER_IRQHandler CLOCK_POWER_IRQHandler + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals ============================ */ +#define __CM33_REV r0p4 /*!< CM33 Core Revision */ +#define __DSP_PRESENT 1 /*!< DSP present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< CPU supports alternate Vector Table address */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __FPU_DP 0 /*!< Double Precision FPU */ +#define __INTERRUPTS_MAX 270 /*!< Size of interrupt vector table */ +#define __Vendor_SysTickConfig 0 /*!< Vendor SysTick Config implementation is used */ +#define __SAUREGION_PRESENT 1 /*!< SAU present */ +#define __NUM_SAUREGIONS 4 /*!< Number of regions */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_nrf.h" /*!< nrf54lm20a_application System Library */ + +#endif /*!< NRF_APPLICATION */ + + +#ifdef NRF_APPLICATION + + #define NRF_DOMAIN NRF_DOMAIN_NONE + #define NRF_PROCESSOR NRF_PROCESSOR_CM33 + +#endif /*!< NRF_APPLICATION */ + + +/* ========================================= Start of section using anonymous unions ========================================= */ + +#include "compiler_abstraction.h" + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Unsupported compiler type +#endif + +/* =========================================================================================================================== */ +/* ================ Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define NRF_APPLICATION_ICACHEDATA_S_BASE 0x02F00000UL +#define NRF_APPLICATION_ICACHEINFO_S_BASE 0x02F10000UL +#define NRF_APPLICATION_TPIU_NS_BASE 0xE0040000UL +#define NRF_APPLICATION_ETM_NS_BASE 0xE0041000UL +#define NRF_APPLICATION_CPUC_S_BASE 0xE0080000UL +#define NRF_APPLICATION_ICACHE_S_BASE 0xE0082000UL +#define NRF_APPLICATION_SWI00_S_BASE 0x5001C000UL +#define NRF_APPLICATION_SWI01_S_BASE 0x5001D000UL +#define NRF_APPLICATION_SWI02_S_BASE 0x5001E000UL +#define NRF_APPLICATION_SWI03_S_BASE 0x5001F000UL + +/* =========================================================================================================================== */ +/* ================ Peripheral Declaration ================ */ +/* =========================================================================================================================== */ + +#define NRF_APPLICATION_ICACHEDATA_S ((NRF_CACHEDATA_Type*) NRF_APPLICATION_ICACHEDATA_S_BASE) +#define NRF_APPLICATION_ICACHEINFO_S ((NRF_CACHEINFO_Type*) NRF_APPLICATION_ICACHEINFO_S_BASE) +#define NRF_APPLICATION_TPIU_NS ((NRF_TPIU_Type*) NRF_APPLICATION_TPIU_NS_BASE) +#define NRF_APPLICATION_ETM_NS ((NRF_ETM_Type*) NRF_APPLICATION_ETM_NS_BASE) +#define NRF_APPLICATION_CPUC_S ((NRF_CPUC_Type*) NRF_APPLICATION_CPUC_S_BASE) +#define NRF_APPLICATION_ICACHE_S ((NRF_CACHE_Type*) NRF_APPLICATION_ICACHE_S_BASE) +#define NRF_APPLICATION_SWI00_S ((NRF_SWI_Type*) NRF_APPLICATION_SWI00_S_BASE) +#define NRF_APPLICATION_SWI01_S ((NRF_SWI_Type*) NRF_APPLICATION_SWI01_S_BASE) +#define NRF_APPLICATION_SWI02_S ((NRF_SWI_Type*) NRF_APPLICATION_SWI02_S_BASE) +#define NRF_APPLICATION_SWI03_S ((NRF_SWI_Type*) NRF_APPLICATION_SWI03_S_BASE) + +/* =========================================================================================================================== */ +/* ================ TrustZone Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ + #define NRF_APPLICATION_TPIU NRF_APPLICATION_TPIU_NS + #define NRF_APPLICATION_ETM NRF_APPLICATION_ETM_NS +#else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ + #define NRF_APPLICATION_ICACHEDATA NRF_APPLICATION_ICACHEDATA_S + #define NRF_APPLICATION_ICACHEINFO NRF_APPLICATION_ICACHEINFO_S + #define NRF_APPLICATION_TPIU NRF_APPLICATION_TPIU_NS + #define NRF_APPLICATION_ETM NRF_APPLICATION_ETM_NS + #define NRF_APPLICATION_CPUC NRF_APPLICATION_CPUC_S + #define NRF_APPLICATION_ICACHE NRF_APPLICATION_ICACHE_S + #define NRF_APPLICATION_SWI00 NRF_APPLICATION_SWI00_S + #define NRF_APPLICATION_SWI01 NRF_APPLICATION_SWI01_S + #define NRF_APPLICATION_SWI02 NRF_APPLICATION_SWI02_S + #define NRF_APPLICATION_SWI03 NRF_APPLICATION_SWI03_S +#endif /*!< NRF_TRUSTZONE_NONSECURE */ + +/* =========================================================================================================================== */ +/* ================ Local Domain Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_APPLICATION /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ + #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ + #define NRF_TPIU NRF_APPLICATION_TPIU + #define NRF_ETM NRF_APPLICATION_ETM + #else /*!< Remap all instances. */ + #define NRF_ICACHEDATA NRF_APPLICATION_ICACHEDATA + #define NRF_ICACHEINFO NRF_APPLICATION_ICACHEINFO + #define NRF_TPIU NRF_APPLICATION_TPIU + #define NRF_ETM NRF_APPLICATION_ETM + #define NRF_CPUC NRF_APPLICATION_CPUC + #define NRF_ICACHE NRF_APPLICATION_ICACHE + #define NRF_SWI00 NRF_APPLICATION_SWI00 + #define NRF_SWI01 NRF_APPLICATION_SWI01 + #define NRF_SWI02 NRF_APPLICATION_SWI02 + #define NRF_SWI03 NRF_APPLICATION_SWI03 + #endif /*!< NRF_TRUSTZONE_NONSECURE */ +#endif /*!< NRF_APPLICATION */ + +/* ========================================== End of section using anonymous unions ========================================== */ + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif +#endif /* NRF54LM20A_APPLICATION_H */ + diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_application_peripherals.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_application_peripherals.h new file mode 100644 index 0000000..2a8629b --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_application_peripherals.h @@ -0,0 +1,1672 @@ +/* + +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF54LM20A_APPLICATION_PERIPHERALS_H +#define NRF54LM20A_APPLICATION_PERIPHERALS_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include +/*CACHEDATA*/ +#define CACHEDATA_PRESENT 1 +#define CACHEDATA_COUNT 1 + +#define ICACHEDATA_NUMSETS_MIN 0 /*!< Number of sets : 0..127 */ +#define ICACHEDATA_NUMSETS_MAX 127 /*!< Number of sets : 0..127 */ +#define ICACHEDATA_NUMSETS_SIZE 128 /*!< Number of sets : 0..127 */ +#define ICACHEDATA_NUMWAYS_MIN 0 /*!< Number of ways : 0..1 */ +#define ICACHEDATA_NUMWAYS_MAX 1 /*!< Number of ways : 0..1 */ +#define ICACHEDATA_NUMWAYS_SIZE 2 /*!< Number of ways : 0..1 */ +#define ICACHEDATA_NUMDATAUNIT_MIN 0 /*!< Number of data units : 0..3 */ +#define ICACHEDATA_NUMDATAUNIT_MAX 3 /*!< Number of data units : 0..3 */ +#define ICACHEDATA_NUMDATAUNIT_SIZE 4 /*!< Number of data units : 0..3 */ +#define ICACHEDATA_DATAWIDTH_MIN 0 /*!< Data width of a data unit : 0..1 words */ +#define ICACHEDATA_DATAWIDTH_MAX 1 /*!< Data width of a data unit : 0..1 words */ +#define ICACHEDATA_DATAWIDTH_SIZE 2 /*!< Data width of a data unit : 0..1 words */ + +/*CACHEINFO*/ +#define CACHEINFO_PRESENT 1 +#define CACHEINFO_COUNT 1 + +#define ICACHEINFO_NUMSETS_MIN 0 /*!< Number of sets : 0..127 */ +#define ICACHEINFO_NUMSETS_MAX 127 /*!< Number of sets : 0..127 */ +#define ICACHEINFO_NUMSETS_SIZE 128 /*!< Number of sets : 0..127 */ +#define ICACHEINFO_NUMWAYS_MIN 0 /*!< Number of ways : 0..1 */ +#define ICACHEINFO_NUMWAYS_MAX 1 /*!< Number of ways : 0..1 */ +#define ICACHEINFO_NUMWAYS_SIZE 2 /*!< Number of ways : 0..1 */ +#define ICACHEINFO_NUMDATAUNIT_MIN 0 /*!< Number of data units : 0..3 */ +#define ICACHEINFO_NUMDATAUNIT_MAX 3 /*!< Number of data units : 0..3 */ +#define ICACHEINFO_NUMDATAUNIT_SIZE 4 /*!< Number of data units : 0..3 */ +#define ICACHEINFO_DATAWIDTH_MIN 0 /*!< Data width of a data unit : 0..1 words */ +#define ICACHEINFO_DATAWIDTH_MAX 1 /*!< Data width of a data unit : 0..1 words */ +#define ICACHEINFO_DATAWIDTH_SIZE 2 /*!< Data width of a data unit : 0..1 words */ +#define ICACHEINFO_TAGWIDTH_MIN 0 /*!< TAG width : 0..19 */ +#define ICACHEINFO_TAGWIDTH_MAX 19 /*!< TAG width : 0..19 */ +#define ICACHEINFO_TAGWIDTH_SIZE 20 /*!< TAG width : 0..19 */ +#define ICACHEINFO_DU_EXTENSION 0 /*!< (unspecified) */ + +/*Trace Port Interface Unit*/ +#define TPIU_PRESENT 1 +#define TPIU_COUNT 1 + +/*Embedded Trace Macrocell*/ +#define ETM_PRESENT 1 +#define ETM_COUNT 1 + +/*CPU control*/ +#define CPUC_PRESENT 1 +#define CPUC_COUNT 1 + +/*Cache*/ +#define CACHE_PRESENT 1 +#define CACHE_COUNT 1 + +#define ICACHE_VIRTUALCACHE 0 /*!< (unspecified) */ +#define ICACHE_FLUSH 0 /*!< (unspecified) */ +#define ICACHE_CLEAN 0 /*!< (unspecified) */ +#define ICACHE_INVALIDATELINE 1 /*!< Supports line invalidation */ +#define ICACHE_ERASE 1 /*!< Supports cache erase */ +#define ICACHE_LINEMAINTAIN 1 /*!< Supports cache line maintain */ +#define ICACHE_EXTENDEDPROFILING 1 /*!< Supports extended profiling registers (LMISS / READS / WRITES) */ +#define ICACHE_DEBUGLOCK 1 /*!< Supports debug lock */ +#define ICACHE_WRITELOCK 1 /*!< Supports write lock */ +#define ICACHE_NONCACHEABLEMISS 0 /*!< (unspecified) */ +#define ICACHE_BUSWIDTH_MIN 0 /*!< Data bus width : 0..63 */ +#define ICACHE_BUSWIDTH_MAX 63 /*!< Data bus width : 0..63 */ +#define ICACHE_BUSWIDTH_SIZE 64 /*!< Data bus width : 0..63 */ + +/*Software interrupt*/ +#define SWI_PRESENT 1 +#define SWI_COUNT 4 + +/*Factory Information Configuration Registers*/ +#define FICR_PRESENT 1 +#define FICR_COUNT 1 + +/*User Information Configuration Registers*/ +#define UICR_PRESENT 1 +#define UICR_COUNT 1 + +/*Factory Information Configuration Registers*/ +#define SICR_PRESENT 1 +#define SICR_COUNT 1 + +/*CRACENCORE*/ +#define CRACENCORE_PRESENT 1 +#define CRACENCORE_COUNT 1 + +#define CRACENCORE_CRYPTMSTRDMAREGS 1 /*!< CRYPTMSTRDMA registers included */ +#define CRACENCORE_CRYPTMSTRHWREGS 1 /*!< CRYPTMSTRHW registers included */ +#define CRACENCORE_RNGCONTROLREGS 1 /*!< RNGCONTROL registers included */ +#define CRACENCORE_PKREGS 1 /*!< PK registers included */ +#define CRACENCORE_IKGREGS 1 /*!< IKG registers included */ +#define CRACENCORE_RNGDATAREGS 1 /*!< RNGDATA registers included */ +#define CRACENCORE_EXTPRIVKEYSREGS 0 /*!< (unspecified) */ +#define CRACENCORE_LITESMALLRESETVALUES 0 /*!< (unspecified) */ +#define CRACENCORE_LITEMEDIUMRESETVALUES 1 /*!< Apply reset values for registers in Lite Medium configuration */ +#define CRACENCORE_FULLRESETVALUES 0 /*!< (unspecified) */ +#define CRACENCORE_CRACENRESETVALUES 1 /*!< Using CRACENCORE configuration reset values */ +#define CRACENCORE_SHA3RESETVALUES 0 /*!< (unspecified) */ +#define CRACENCORE_PKE_DATA_MEMORY 0x50018000 /*!< (unspecified) */ +#define CRACENCORE_PKE_DATA_MEMORY_SIZE 16384 /*!< (unspecified) */ +#define CRACENCORE_PKE_CODE_MEMORY 0x5001C000 /*!< (unspecified) */ +#define CRACENCORE_PKE_CODE_MEMORY_SIZE 8192 /*!< (unspecified) */ + +/*USBHSCORE*/ +#define USBHSCORE_PRESENT 1 +#define USBHSCORE_COUNT 1 + +/*System protection unit*/ +#define SPU_PRESENT 1 +#define SPU_COUNT 4 + +#define SPU00_BELLS 0 /*!< (unspecified) */ +#define SPU00_IPCT 0 /*!< (unspecified) */ +#define SPU00_DPPI 1 /*!< Supports FEATURE.DPPIC[n] */ +#define SPU00_GPIOTE 0 /*!< (unspecified) */ +#define SPU00_GRTC 0 /*!< (unspecified) */ +#define SPU00_GPIO 1 /*!< Supports FEATURE.GPIO[n] */ +#define SPU00_CRACEN 0 /*!< (unspecified) */ +#define SPU00_MRAMC 0 /*!< (unspecified) */ +#define SPU00_COEXC 0 /*!< (unspecified) */ +#define SPU00_ANTSWC 0 /*!< (unspecified) */ +#define SPU00_TDD 0 /*!< (unspecified) */ +#define SPU00_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the + peripheral slave index)*/ + +#define SPU10_BELLS 0 /*!< (unspecified) */ +#define SPU10_IPCT 0 /*!< (unspecified) */ +#define SPU10_DPPI 1 /*!< Supports FEATURE.DPPIC[n] */ +#define SPU10_GPIOTE 0 /*!< (unspecified) */ +#define SPU10_GRTC 0 /*!< (unspecified) */ +#define SPU10_GPIO 0 /*!< (unspecified) */ +#define SPU10_CRACEN 0 /*!< (unspecified) */ +#define SPU10_MRAMC 0 /*!< (unspecified) */ +#define SPU10_COEXC 0 /*!< (unspecified) */ +#define SPU10_ANTSWC 0 /*!< (unspecified) */ +#define SPU10_TDD 0 /*!< (unspecified) */ +#define SPU10_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the + peripheral slave index)*/ + +#define SPU20_BELLS 0 /*!< (unspecified) */ +#define SPU20_IPCT 0 /*!< (unspecified) */ +#define SPU20_DPPI 1 /*!< Supports FEATURE.DPPIC[n] */ +#define SPU20_GPIOTE 1 /*!< Supports FEATURE.GPIOTE[n] */ +#define SPU20_GRTC 1 /*!< Supports FEATURE.GRTC[n] */ +#define SPU20_GPIO 1 /*!< Supports FEATURE.GPIO[n] */ +#define SPU20_CRACEN 0 /*!< (unspecified) */ +#define SPU20_MRAMC 0 /*!< (unspecified) */ +#define SPU20_COEXC 0 /*!< (unspecified) */ +#define SPU20_ANTSWC 0 /*!< (unspecified) */ +#define SPU20_TDD 0 /*!< (unspecified) */ +#define SPU20_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the + peripheral slave index)*/ + +#define SPU30_BELLS 0 /*!< (unspecified) */ +#define SPU30_IPCT 0 /*!< (unspecified) */ +#define SPU30_DPPI 1 /*!< Supports FEATURE.DPPIC[n] */ +#define SPU30_GPIOTE 1 /*!< Supports FEATURE.GPIOTE[n] */ +#define SPU30_GRTC 0 /*!< (unspecified) */ +#define SPU30_GPIO 1 /*!< Supports FEATURE.GPIO[n] */ +#define SPU30_CRACEN 0 /*!< (unspecified) */ +#define SPU30_MRAMC 0 /*!< (unspecified) */ +#define SPU30_COEXC 0 /*!< (unspecified) */ +#define SPU30_ANTSWC 0 /*!< (unspecified) */ +#define SPU30_TDD 0 /*!< (unspecified) */ +#define SPU30_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the + peripheral slave index)*/ + +/*Memory Privilege Controller*/ +#define MPC_PRESENT 1 +#define MPC_COUNT 1 + +#define MPC00_EXTEND_CLOCK_REQ 1 /*!< (unspecified) */ +#define MPC00_RTCHOKE 0 /*!< (unspecified) */ +#define MPC00_OVERRIDE_GRAN 4096 /*!< The override region granularity is 4096 bytes */ + +/*Distributed programmable peripheral interconnect controller*/ +#define DPPIC_PRESENT 1 +#define DPPIC_COUNT 4 + +#define DPPIC00_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC00_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC00_CH_NUM_MAX 15 /*!< (unspecified) */ +#define DPPIC00_CH_NUM_SIZE 16 /*!< (unspecified) */ +#define DPPIC00_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC00_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC00_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC10_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC10_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC10_CH_NUM_MAX 23 /*!< (unspecified) */ +#define DPPIC10_CH_NUM_SIZE 24 /*!< (unspecified) */ +#define DPPIC10_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC10_GROUP_NUM_MAX 5 /*!< (unspecified) */ +#define DPPIC10_GROUP_NUM_SIZE 6 /*!< (unspecified) */ + +#define DPPIC20_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC20_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC20_CH_NUM_MAX 15 /*!< (unspecified) */ +#define DPPIC20_CH_NUM_SIZE 16 /*!< (unspecified) */ +#define DPPIC20_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC20_GROUP_NUM_MAX 5 /*!< (unspecified) */ +#define DPPIC20_GROUP_NUM_SIZE 6 /*!< (unspecified) */ + +#define DPPIC30_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC30_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC30_CH_NUM_MAX 3 /*!< (unspecified) */ +#define DPPIC30_CH_NUM_SIZE 4 /*!< (unspecified) */ +#define DPPIC30_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC30_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC30_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +/*PPIB APB registers*/ +#define PPIB_PRESENT 1 +#define PPIB_COUNT 8 + +#define PPIB00_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ +#define PPIB00_NTASKSEVENTS_MAX 11 /*!< (unspecified) */ +#define PPIB00_NTASKSEVENTS_SIZE 12 /*!< (unspecified) */ + +#define PPIB01_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ +#define PPIB01_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ +#define PPIB01_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ + +#define PPIB10_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ +#define PPIB10_NTASKSEVENTS_MAX 11 /*!< (unspecified) */ +#define PPIB10_NTASKSEVENTS_SIZE 12 /*!< (unspecified) */ + +#define PPIB11_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ +#define PPIB11_NTASKSEVENTS_MAX 15 /*!< (unspecified) */ +#define PPIB11_NTASKSEVENTS_SIZE 16 /*!< (unspecified) */ + +#define PPIB20_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ +#define PPIB20_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ +#define PPIB20_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ + +#define PPIB21_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ +#define PPIB21_NTASKSEVENTS_MAX 15 /*!< (unspecified) */ +#define PPIB21_NTASKSEVENTS_SIZE 16 /*!< (unspecified) */ + +#define PPIB22_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ +#define PPIB22_NTASKSEVENTS_MAX 3 /*!< (unspecified) */ +#define PPIB22_NTASKSEVENTS_SIZE 4 /*!< (unspecified) */ + +#define PPIB30_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ +#define PPIB30_NTASKSEVENTS_MAX 3 /*!< (unspecified) */ +#define PPIB30_NTASKSEVENTS_SIZE 4 /*!< (unspecified) */ + +/*Key management unit*/ +#define KMU_PRESENT 1 +#define KMU_COUNT 1 + +#define KMU_KEYSLOTNUM 250 /*!< Number of keyslots is 250 */ +#define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot is 128 */ +#define KMU_PUSHBLOCK 1 /*!< (unspecified) */ +#define KMU_BLOCK 1 /*!< (unspecified) */ + +/*Accelerated Address Resolver*/ +#define AAR_PRESENT 1 +#define AAR_COUNT 1 + +#define AAR00_DMAERROR 1 /*!< (unspecified) */ +#define AAR00_ERRORSTATUS 1 /*!< (unspecified) */ +#define AAR00_ERROREVENT 1 /*!< (unspecified) */ +#define AAR00_ERROREVENT_IRQ 1 /*!< (unspecified) */ +#define AAR00_PREMATUREOUTPUTPTR 1 /*!< (unspecified) */ + +/*AES CCM Mode Encryption*/ +#define CCM_PRESENT 1 +#define CCM_COUNT 1 + +#define CCM00_AMOUNTREG 0 /*!< (unspecified) */ +#define CCM00_ONTHEFLYDECRYPTION 0 /*!< Does not support on-the-fly decryption. */ +#define CCM00_DMAERROR 1 /*!< (unspecified) */ +#define CCM00_BYPASSMODE 0 /*!< No bypass mode available in the MODE register. */ + +/*AES ECB Mode Encryption*/ +#define ECB_PRESENT 1 +#define ECB_COUNT 1 + +#define ECB00_AMOUNTREG 0 /*!< (unspecified) */ +#define ECB00_DMAERROR 1 /*!< (unspecified) */ +#define ECB00_ERRORSTATUS 1 /*!< (unspecified) */ + +/*VPR peripheral registers*/ +#define VPR_PRESENT 1 +#define VPR_COUNT 1 + +#define VPR00_RISCV_EXTN_E 1 /*!< Supports RV32E (Base Integer Instruction Set embedded) */ +#define VPR00_RISCV_EXTN_M 1 /*!< Supports M extension (Integer Multiplication and Division) */ +#define VPR00_RISCV_EXTN_C 1 /*!< Supports C extension (compressed instructions) */ +#define VPR00_RISCV_EXTN_ZBA 1 /*!< Supports Zba extension (Bit Manipulation - Address generation + instructions)*/ +#define VPR00_RISCV_EXTN_ZBB 1 /*!< Supports Zbb extension (Bit Manipulation - Basic bit manipulation) */ +#define VPR00_RISCV_EXTN_ZBC 1 /*!< Supports Zbc extension (Bit Manipulation - Carry-less multiplication)*/ +#define VPR00_RISCV_EXTN_ZBS 1 /*!< Supports Zbs extension (Bit Manipulation - Single bit instructions) */ +#define VPR00_RISCV_EXTN_ZCB 1 /*!< Supports Zcb extension (code-size saving instructions) */ +#define VPR00_RISCV_EXTN_ZIFENCEI 0 /*!< Does not support FENCE.I instruction (use FENCE instruction instead) */ +#define VPR00_RISCV_EXTN_ZICSR 1 /*!< Supports CSR (Control and Status Register) instructions */ +#define VPR00_RISCV_EXTN_ZICNTR 0 /*!< Does not support CNTR (base counter) instructions */ +#define VPR00_RISCV_EXTN_SMCLIC 1 /*!< Supports M-mode CLIC (interrupt controller) */ +#define VPR00_RISCV_EXTN_SMCLICCONFIG 1 /*!< Supports MCLICCFG register */ +#define VPR00_RISCV_EXTN_SDEXT 1 /*!< Supports external debugger */ +#define VPR00_RISCV_EXTN_SDTRIG 1 /*!< Debugger supports triggers (breakpoints) */ +#define VPR00_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ +#define VPR00_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ +#define VPR00_RAM_BASE_ADDR 0x20000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x20000000 */ +#define VPR00_RAM_SZ 20 /*!< VPR RAM size (RAM_SZ): 20 (Value in bytes is computed as 2^(RAM + size))*/ +#define VPR00_VPRSAVEDCTX_REGNAME NRF_MEMCONF->POWER[1].RET /*!< (unspecified) */ +#define VPR00_VPRSAVEDCTX_REGBIT 0 /*!< (unspecified) */ +#define VPR00_RETAINED 0 /*!< Retain registers in Deep Sleep mode: 0 */ +#define VPR00_VPRSAVEDCTX 1 /*!< Restore VPR context at VPR reset using register + [NRF_MEMCONF->POWER1.RET].MEM[0]*/ +#define VPR00_VPRSAVEADDR 0x2007FD40 /*!< VPR context save address: 0x2007FD40 */ +#define VPR00_VPRSAVESIZE 512 /*!< VPR context save size: 512 bytes */ +#define VPR00_VPRREMAPADDRVTOB 0x00000000 /*!< VPR remap address: 0x00000000 */ +#define VPR00_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_NTASKS_MAX 22 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_NTASKS_SIZE 23 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_TASKS_MASK 0x007F0000 /*!< Mask of supported VEVIF tasks: 0x007F0000 */ +#define VPR00_VEVIF_NDPPI_MIN 16 /*!< VEVIF DPPI indices: 16..19 */ +#define VPR00_VEVIF_NDPPI_MAX 19 /*!< VEVIF DPPI indices: 16..19 */ +#define VPR00_VEVIF_NDPPI_SIZE 20 /*!< VEVIF DPPI indices: 16..19 */ +#define VPR00_VEVIF_DPPI_MASK 0x000F0000 /*!< Mask of supported VEVIF DPPI channels: 0x000F0000 */ +#define VPR00_VEVIF_NEVENTS_MIN 16 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_NEVENTS_MAX 22 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_NEVENTS_SIZE 23 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_EVENTS_MASK 0x00100000 /*!< Mask of supported VEVIF events: 0x00100000 */ +#define VPR00_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5004C400 */ +#define VPR00_RTP_VPR_1_5 1 /*!< New RTP features */ + +/*Serial Peripheral Interface Master with EasyDMA*/ +#define SPIM_PRESENT 1 +#define SPIM_COUNT 7 + +#define SPIM00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ +#define SPIM00_MAX_DATARATE 32 /*!< (unspecified) */ +#define SPIM00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIM00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIM00_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< CSN functionality is supported. */ +#define SPIM00_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< DCX functionality is supported. */ +#define SPIM00_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM00_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM00_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ +#define SPIM00_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM00_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM00_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM00_CORE_FREQUENCY 128 /*!< Peripheral core frequency is 128 MHz. */ +#define SPIM00_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM00_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< Prescaler divisor range is 4..126 */ +#define SPIM00_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< Prescaler divisor range is 4..126 */ +#define SPIM00_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< Prescaler divisor range is 4..126 */ +#define SPIM00_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM00_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM00_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM00_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM00_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM00_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM00_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ +#define SPIM20_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIM20_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< CSN functionality is supported. */ +#define SPIM20_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< DCX functionality is supported. */ +#define SPIM20_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM20_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM20_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM20_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM20_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM20_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM20_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM20_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM20_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< Prescaler divisor range is 2..126 */ +#define SPIM20_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< Prescaler divisor range is 2..126 */ +#define SPIM20_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< Prescaler divisor range is 2..126 */ +#define SPIM20_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM20_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM20_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM20_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ +#define SPIM20_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM20_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM20_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ +#define SPIM21_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIM21_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< CSN functionality is supported. */ +#define SPIM21_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< DCX functionality is supported. */ +#define SPIM21_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM21_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM21_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM21_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM21_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM21_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM21_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM21_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM21_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< Prescaler divisor range is 2..126 */ +#define SPIM21_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< Prescaler divisor range is 2..126 */ +#define SPIM21_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< Prescaler divisor range is 2..126 */ +#define SPIM21_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM21_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM21_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM21_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ +#define SPIM21_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM21_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM21_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ +#define SPIM22_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIM22_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< CSN functionality is supported. */ +#define SPIM22_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< DCX functionality is supported. */ +#define SPIM22_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM22_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM22_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM22_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM22_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM22_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM22_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM22_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM22_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< Prescaler divisor range is 2..126 */ +#define SPIM22_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< Prescaler divisor range is 2..126 */ +#define SPIM22_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< Prescaler divisor range is 2..126 */ +#define SPIM22_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM22_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM22_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM22_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ +#define SPIM22_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM22_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM22_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ +#define SPIM23_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIM23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIM23_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< CSN functionality is supported. */ +#define SPIM23_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< DCX functionality is supported. */ +#define SPIM23_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM23_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM23_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM23_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM23_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM23_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM23_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM23_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM23_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< Prescaler divisor range is 2..126 */ +#define SPIM23_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< Prescaler divisor range is 2..126 */ +#define SPIM23_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< Prescaler divisor range is 2..126 */ +#define SPIM23_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM23_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM23_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM23_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ +#define SPIM23_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM23_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM23_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ +#define SPIM24_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIM24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIM24_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< CSN functionality is supported. */ +#define SPIM24_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< DCX functionality is supported. */ +#define SPIM24_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM24_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM24_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM24_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM24_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM24_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM24_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM24_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM24_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< Prescaler divisor range is 2..126 */ +#define SPIM24_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< Prescaler divisor range is 2..126 */ +#define SPIM24_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< Prescaler divisor range is 2..126 */ +#define SPIM24_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM24_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM24_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM24_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ +#define SPIM24_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM24_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM24_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ +#define SPIM30_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIM30_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< CSN functionality is supported. */ +#define SPIM30_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< DCX functionality is supported. */ +#define SPIM30_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM30_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM30_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM30_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM30_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM30_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM30_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM30_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM30_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< Prescaler divisor range is 2..126 */ +#define SPIM30_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< Prescaler divisor range is 2..126 */ +#define SPIM30_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< Prescaler divisor range is 2..126 */ +#define SPIM30_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM30_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM30_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM30_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ +#define SPIM30_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM30_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM30_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +/*SPI Slave*/ +#define SPIS_PRESENT 1 +#define SPIS_COUNT 7 + +#define SPIS00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIS00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIS00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define SPIS20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIS20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIS20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define SPIS21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIS21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIS21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define SPIS22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIS22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIS22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define SPIS23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIS23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIS23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define SPIS24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIS24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIS24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define SPIS30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define SPIS30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define SPIS30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +/*UART with EasyDMA*/ +#define UARTE_PRESENT 1 +#define UARTE_COUNT 7 + +#define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define UARTE00_TIMEOUT_INTERRUPT 1 /*!< Timeout interrupt is included. */ +#define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< Supports data frame sizes 4, 5, 6, 7, 8, and 9 bits. */ +#define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */ +#define UARTE00_CORE_CLOCK_128 1 /*!< (unspecified) */ +#define UARTE00_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE00_DMAEND_PRESENT 0 /*!< (unspecified) */ +#define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define UARTE20_TIMEOUT_INTERRUPT 1 /*!< Timeout interrupt is included. */ +#define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< Supports data frame sizes 4, 5, 6, 7, 8, and 9 bits. */ +#define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE20_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE20_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE20_DMAEND_PRESENT 0 /*!< (unspecified) */ +#define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define UARTE21_TIMEOUT_INTERRUPT 1 /*!< Timeout interrupt is included. */ +#define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< Supports data frame sizes 4, 5, 6, 7, 8, and 9 bits. */ +#define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE21_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE21_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE21_DMAEND_PRESENT 0 /*!< (unspecified) */ +#define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define UARTE22_TIMEOUT_INTERRUPT 1 /*!< Timeout interrupt is included. */ +#define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< Supports data frame sizes 4, 5, 6, 7, 8, and 9 bits. */ +#define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE22_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE22_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE22_DMAEND_PRESENT 0 /*!< (unspecified) */ +#define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define UARTE23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define UARTE23_TIMEOUT_INTERRUPT 1 /*!< Timeout interrupt is included. */ +#define UARTE23_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< Supports data frame sizes 4, 5, 6, 7, 8, and 9 bits. */ +#define UARTE23_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE23_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE23_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE23_DMAEND_PRESENT 0 /*!< (unspecified) */ +#define UARTE23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define UARTE24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define UARTE24_TIMEOUT_INTERRUPT 1 /*!< Timeout interrupt is included. */ +#define UARTE24_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< Supports data frame sizes 4, 5, 6, 7, 8, and 9 bits. */ +#define UARTE24_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE24_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE24_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE24_DMAEND_PRESENT 0 /*!< (unspecified) */ +#define UARTE24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define UARTE30_TIMEOUT_INTERRUPT 1 /*!< Timeout interrupt is included. */ +#define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< Supports data frame sizes 4, 5, 6, 7, 8, and 9 bits. */ +#define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE30_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE30_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE30_DMAEND_PRESENT 0 /*!< (unspecified) */ +#define UARTE30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +/*Voltage glitch detectors*/ +#define GLITCHDET_PRESENT 1 +#define GLITCHDET_COUNT 1 + +/*RRAM controller GLITCH detector*/ +#define RRAMC_PRESENT 1 +#define RRAMC_COUNT 1 + +#define RRAMC_NAPMODE 0 /*!< (unspecified) */ +#define RRAMC_NRRAMWORDSIZE 128 /*!< RRAM word size : 128 bits per wordline */ +#define RRAMC_NWRITEBUFSIZE 32 /*!< Maximum write buffer size : 32 */ +#define RRAMC_LOWPOWERCONFIGOPTION2 1 /*!< (unspecified) */ +#define RRAMC_REGION0ADDR_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION0SIZE 4 /*!< (unspecified) */ +#define RRAMC_REGION0SIZE_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION0READ 1 /*!< (unspecified) */ +#define RRAMC_REGION0READ_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION0WRITE 1 /*!< (unspecified) */ +#define RRAMC_REGION0WRITE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION0EXECUTE 0 /*!< (unspecified) */ +#define RRAMC_REGION0EXECUTE_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION0SECURE 0 /*!< (unspecified) */ +#define RRAMC_REGION0SECURE_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION0OWNER 0 /*!< (unspecified) */ +#define RRAMC_REGION0OWNER_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION0WRITEONCE 1 /*!< (unspecified) */ +#define RRAMC_REGION0WRITEONCE_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION0LOCK 0 /*!< (unspecified) */ +#define RRAMC_REGION0LOCK_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION1ADDR_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION1SIZE 4 /*!< (unspecified) */ +#define RRAMC_REGION1SIZE_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION1READ 1 /*!< (unspecified) */ +#define RRAMC_REGION1READ_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION1WRITE 1 /*!< (unspecified) */ +#define RRAMC_REGION1WRITE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION1EXECUTE 0 /*!< (unspecified) */ +#define RRAMC_REGION1EXECUTE_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION1SECURE 1 /*!< (unspecified) */ +#define RRAMC_REGION1SECURE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION1OWNER 0 /*!< (unspecified) */ +#define RRAMC_REGION1OWNER_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION1WRITEONCE 1 /*!< (unspecified) */ +#define RRAMC_REGION1WRITEONCE_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION1LOCK 0 /*!< (unspecified) */ +#define RRAMC_REGION1LOCK_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION2ADDR_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION2SIZE 8 /*!< (unspecified) */ +#define RRAMC_REGION2SIZE_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION2READ 1 /*!< (unspecified) */ +#define RRAMC_REGION2READ_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION2WRITE 1 /*!< (unspecified) */ +#define RRAMC_REGION2WRITE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION2EXECUTE 0 /*!< (unspecified) */ +#define RRAMC_REGION2EXECUTE_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION2SECURE 1 /*!< (unspecified) */ +#define RRAMC_REGION2SECURE_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION2OWNER 2 /*!< (unspecified) */ +#define RRAMC_REGION2OWNER_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION2WRITEONCE 0 /*!< (unspecified) */ +#define RRAMC_REGION2WRITEONCE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION2LOCK 0 /*!< (unspecified) */ +#define RRAMC_REGION2LOCK_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION3ADDR_WRITABLE 0 /*!< (unspecified) */ +#define RRAMC_REGION3SIZE 0 /*!< (unspecified) */ +#define RRAMC_REGION3SIZE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION3READ 1 /*!< (unspecified) */ +#define RRAMC_REGION3READ_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION3WRITE 1 /*!< (unspecified) */ +#define RRAMC_REGION3WRITE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION3EXECUTE 1 /*!< (unspecified) */ +#define RRAMC_REGION3EXECUTE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION3SECURE 1 /*!< (unspecified) */ +#define RRAMC_REGION3SECURE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION3OWNER 0 /*!< (unspecified) */ +#define RRAMC_REGION3OWNER_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION3WRITEONCE 0 /*!< (unspecified) */ +#define RRAMC_REGION3WRITEONCE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION3LOCK 0 /*!< (unspecified) */ +#define RRAMC_REGION3LOCK_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION4ADDR_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION4SIZE 0 /*!< (unspecified) */ +#define RRAMC_REGION4SIZE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION4READ 1 /*!< (unspecified) */ +#define RRAMC_REGION4READ_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION4WRITE 1 /*!< (unspecified) */ +#define RRAMC_REGION4WRITE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION4EXECUTE 1 /*!< (unspecified) */ +#define RRAMC_REGION4EXECUTE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION4SECURE 1 /*!< (unspecified) */ +#define RRAMC_REGION4SECURE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION4OWNER 0 /*!< (unspecified) */ +#define RRAMC_REGION4OWNER_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION4WRITEONCE 0 /*!< (unspecified) */ +#define RRAMC_REGION4WRITEONCE_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_REGION4LOCK 0 /*!< (unspecified) */ +#define RRAMC_REGION4LOCK_WRITABLE 1 /*!< (unspecified) */ +#define RRAMC_GLITCHDETECTORS 0 /*!< (unspecified) */ + +/*GPIO high-speed pad control*/ +#define GPIOHSPADCTRL_PRESENT 1 +#define GPIOHSPADCTRL_COUNT 1 + +/*GPIO Port*/ +#define GPIO_PRESENT 1 +#define GPIO_COUNT 4 + +#define P2_CTRLSEL_MAP1 0 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP2 1 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP4 0 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP5 0 /*!< (unspecified) */ +#define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P2_PIN_NUM_MAX 10 /*!< (unspecified) */ +#define P2_PIN_NUM_SIZE 11 /*!< (unspecified) */ +#define P2_FEATURE_PINS_PRESENT 2047 /*!< (unspecified) */ +#define P2_FEATURE_I5_LIBRARY 0 /*!< (unspecified) */ +#define P2_PIN_SENSE_MECHANISM 0 /*!< (unspecified) */ +#define P2_DRIVECTRL 0 /*!< (unspecified) */ +#define P2_WEAKPU 0 /*!< (unspecified) */ +#define P2_RETAIN 0 /*!< (unspecified) */ +#define P2_PWRCTRL 0 /*!< (unspecified) */ +#define P2_SLEWMODE 0 /*!< (unspecified) */ +#define P2_PULLSTR 0 /*!< (unspecified) */ +#define P2_SUPPORT_1V2 0 /*!< (unspecified) */ +#define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P2_BIASCTRL 0 /*!< (unspecified) */ + +#define P1_CTRLSEL_MAP1 0 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP2 1 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP4 0 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP5 0 /*!< (unspecified) */ +#define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P1_PIN_NUM_MAX 31 /*!< (unspecified) */ +#define P1_PIN_NUM_SIZE 32 /*!< (unspecified) */ +#define P1_FEATURE_PINS_PRESENT 4294967295 /*!< (unspecified) */ +#define P1_FEATURE_I5_LIBRARY 0 /*!< (unspecified) */ +#define P1_PIN_SENSE_MECHANISM 1 /*!< I/O pins on this port have pin sense mechanism */ +#define P1_DRIVECTRL 0 /*!< (unspecified) */ +#define P1_WEAKPU 0 /*!< (unspecified) */ +#define P1_RETAIN 0 /*!< (unspecified) */ +#define P1_PWRCTRL 0 /*!< (unspecified) */ +#define P1_SLEWMODE 0 /*!< (unspecified) */ +#define P1_PULLSTR 0 /*!< (unspecified) */ +#define P1_SUPPORT_1V2 0 /*!< (unspecified) */ +#define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P1_BIASCTRL 0 /*!< (unspecified) */ + +#define P3_CTRLSEL_MAP1 0 /*!< (unspecified) */ +#define P3_CTRLSEL_MAP2 1 /*!< (unspecified) */ +#define P3_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P3_CTRLSEL_MAP4 0 /*!< (unspecified) */ +#define P3_CTRLSEL_MAP5 0 /*!< (unspecified) */ +#define P3_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P3_PIN_NUM_MAX 12 /*!< (unspecified) */ +#define P3_PIN_NUM_SIZE 13 /*!< (unspecified) */ +#define P3_FEATURE_PINS_PRESENT 8191 /*!< (unspecified) */ +#define P3_FEATURE_I5_LIBRARY 0 /*!< (unspecified) */ +#define P3_PIN_SENSE_MECHANISM 1 /*!< I/O pins on this port have pin sense mechanism */ +#define P3_DRIVECTRL 0 /*!< (unspecified) */ +#define P3_WEAKPU 0 /*!< (unspecified) */ +#define P3_RETAIN 0 /*!< (unspecified) */ +#define P3_PWRCTRL 0 /*!< (unspecified) */ +#define P3_SLEWMODE 0 /*!< (unspecified) */ +#define P3_PULLSTR 0 /*!< (unspecified) */ +#define P3_SUPPORT_1V2 0 /*!< (unspecified) */ +#define P3_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P3_BIASCTRL 0 /*!< (unspecified) */ + +#define P0_CTRLSEL_MAP1 0 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP2 1 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP4 0 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP5 0 /*!< (unspecified) */ +#define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P0_PIN_NUM_MAX 9 /*!< (unspecified) */ +#define P0_PIN_NUM_SIZE 10 /*!< (unspecified) */ +#define P0_FEATURE_PINS_PRESENT 1023 /*!< (unspecified) */ +#define P0_FEATURE_I5_LIBRARY 0 /*!< (unspecified) */ +#define P0_PIN_SENSE_MECHANISM 1 /*!< I/O pins on this port have pin sense mechanism */ +#define P0_DRIVECTRL 0 /*!< (unspecified) */ +#define P0_WEAKPU 0 /*!< (unspecified) */ +#define P0_RETAIN 0 /*!< (unspecified) */ +#define P0_PWRCTRL 0 /*!< (unspecified) */ +#define P0_SLEWMODE 0 /*!< (unspecified) */ +#define P0_PULLSTR 0 /*!< (unspecified) */ +#define P0_SUPPORT_1V2 0 /*!< (unspecified) */ +#define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P0_BIASCTRL 0 /*!< (unspecified) */ + +/*Control access port*/ +#define CTRLAPPERI_PRESENT 1 +#define CTRLAPPERI_COUNT 1 + +/*Trace and debug control*/ +#define TAD_PRESENT 1 +#define TAD_COUNT 1 + +#define TAD_TADFORCEON 0 /*!< (unspecified) */ +#define TAD_TAD_HAS_TASKS 0 /*!< (unspecified) */ +#define TAD_PDREQCLR 1 /*!< (unspecified) */ +#define TAD_TAD_HAS_DBGWAKEUPREQ 1 /*!< (unspecified) */ + +/*Timer/Counter*/ +#define TIMER_PRESENT 1 +#define TIMER_COUNT 7 + +#define TIMER00_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER00_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER00_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER00_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER00_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER00_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER00_PCLK_MHZ 128 /*!< Peripheral clock frequency (PCLK) is 128 MHz */ +#define TIMER00_PCLK_VARIABLE 1 /*!< The system is able to configure the TIMER peripheral input clock + frequency (PCLK) before it reaches TIMER, and calculations of + PRESCALER value must take the actual PCLK frequency into account*/ +#define TIMER00_SHUTDOWN_TASK 0 /*!< (unspecified) */ + +#define TIMER10_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER10_CC_NUM_MAX 7 /*!< (unspecified) */ +#define TIMER10_CC_NUM_SIZE 8 /*!< (unspecified) */ +#define TIMER10_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER10_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER10_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER10_PCLK_MHZ 32 /*!< Peripheral clock frequency (PCLK) is 32 MHz */ +#define TIMER10_PCLK_VARIABLE 0 /*!< (unspecified) */ +#define TIMER10_SHUTDOWN_TASK 0 /*!< (unspecified) */ + +#define TIMER20_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER20_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER20_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER20_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER20_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER20_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER20_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER20_PCLK_VARIABLE 0 /*!< (unspecified) */ +#define TIMER20_SHUTDOWN_TASK 0 /*!< (unspecified) */ + +#define TIMER21_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER21_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER21_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER21_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER21_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER21_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER21_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER21_PCLK_VARIABLE 0 /*!< (unspecified) */ +#define TIMER21_SHUTDOWN_TASK 0 /*!< (unspecified) */ + +#define TIMER22_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER22_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER22_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER22_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER22_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER22_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER22_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER22_PCLK_VARIABLE 0 /*!< (unspecified) */ +#define TIMER22_SHUTDOWN_TASK 0 /*!< (unspecified) */ + +#define TIMER23_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER23_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER23_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER23_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER23_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER23_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER23_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER23_PCLK_VARIABLE 0 /*!< (unspecified) */ +#define TIMER23_SHUTDOWN_TASK 0 /*!< (unspecified) */ + +#define TIMER24_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER24_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER24_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER24_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER24_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER24_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER24_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER24_PCLK_VARIABLE 0 /*!< (unspecified) */ +#define TIMER24_SHUTDOWN_TASK 0 /*!< (unspecified) */ + +/*Event generator unit*/ +#define EGU_PRESENT 1 +#define EGU_COUNT 3 + +#define EGU00_PEND 0 /*!< (unspecified) */ +#define EGU00_CH_NUM_MIN 0 /*!< (unspecified) */ +#define EGU00_CH_NUM_MAX 5 /*!< (unspecified) */ +#define EGU00_CH_NUM_SIZE 6 /*!< (unspecified) */ + +#define EGU10_PEND 0 /*!< (unspecified) */ +#define EGU10_CH_NUM_MIN 0 /*!< (unspecified) */ +#define EGU10_CH_NUM_MAX 15 /*!< (unspecified) */ +#define EGU10_CH_NUM_SIZE 16 /*!< (unspecified) */ + +#define EGU20_PEND 0 /*!< (unspecified) */ +#define EGU20_CH_NUM_MIN 0 /*!< (unspecified) */ +#define EGU20_CH_NUM_MAX 5 /*!< (unspecified) */ +#define EGU20_CH_NUM_SIZE 6 /*!< (unspecified) */ + +/*CRACEN*/ +#define CRACEN_PRESENT 1 +#define CRACEN_COUNT 1 + +#define CRACEN_CRYPTOACCELERATOR 1 /*!< CRACEN CRYPTOACCELERATOR specific configuration registers included */ +#define CRACEN_SEEDRAMLOCK 0 /*!< (unspecified) */ +#define CRACEN_SPLITKEYRAMLOCK 1 /*!< (unspecified) */ +#define CRACEN_SEEDALIGNED 1 /*!< (unspecified) */ +#define CRACEN_ONLYPROTECTEDRAMLOCK 0 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_SEED 0x51810000 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_SEED_SIZE 64 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_AES_KEY0 0x2007FF00 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_AES_KEY0_SIZE 32 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_AES_KEY1 0x2007FF20 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_AES_KEY1_SIZE 32 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_SM4_KEY0 0x51810080 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_SM4_KEY0_SIZE 16 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_SM4_KEY1 0x51810090 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_SM4_KEY1_SIZE 16 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_SM4_KEY2 0x518100A0 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_SM4_KEY2_SIZE 16 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_SM4_KEY3 0x518100B0 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_SM4_KEY3_SIZE 16 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_RESERVED 0x518100C0 /*!< (unspecified) */ +#define CRACEN_PROTECTED_RAM_RESERVED_SIZE 64 /*!< (unspecified) */ +#define CRACEN_PKEDATA 0x50018000 /*!< PKE data (address 0x50018000) must be read and written using aligned + access, i.e. using an operation where a word-aligned address is used + for a word, or a halfword-aligned address is used for a halfword + access.*/ +#define CRACEN_PKECODE 0x5001C000 /*!< PKE code (address 0x5001C000) must be read and written using aligned + access, i.e. using an operation where a word-aligned address is used + for a word, or a halfword-aligned address is used for a halfword + access.*/ + +/*USBHS*/ +#define USBHS_PRESENT 1 +#define USBHS_COUNT 1 + +#define USBHS_HAS_CORE_EVENT 0 /*!< (unspecified) */ +#define USBHS_HAS_SOF_EVENT 1 /*!< Has Start of Frame (SOF) event. */ +#define USBHS_RTUNE_AVAILABLE 1 /*!< RTUNE method for calibrating DP and DM 45Ohm source impedance without + external TXRTUNE resistor available.*/ +#define USBHS_HAS_STATUS_REGISTER 0 /*!< (unspecified) */ + +/*2.4 GHz radio*/ +#define RADIO_PRESENT 1 +#define RADIO_COUNT 1 + +#define RADIO_IRQ_COUNT 2 +#define RADIO_WHITENINGPOLY 1 /*!< (unspecified) */ +#define RADIO_IEEE802154 1 /*!< IEEE 802.15.4 support */ +#define RADIO_LONGRANGE 1 /*!< Long range (LE Coded PHY) support */ +#define RADIO_DIRECTIONFINDING 1 /*!< Direction finding support (DFE) */ +#define RADIO_CHANNELSOUNDING 1 /*!< Channel sounding support (CSTONES) */ +#define RADIO_ADPLLCOMPANION_INCLUDE_DMA 0 /*!< No internal instantiation of DmaChannelPeripheral */ + +/*I2C compatible Two-Wire Master Interface with EasyDMA*/ +#define TWIM_PRESENT 1 +#define TWIM_COUNT 6 + +#define TWIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define TWIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define TWIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define TWIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define TWIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define TWIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define TWIM23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIM23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM23_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define TWIM23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define TWIM24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIM24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM24_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define TWIM24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define TWIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIM30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define TWIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +/*I2C compatible Two-Wire Slave Interface with EasyDMA*/ +#define TWIS_PRESENT 1 +#define TWIS_COUNT 6 + +#define TWIS20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIS20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIS20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define TWIS21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIS21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIS21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define TWIS22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIS22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIS22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define TWIS23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIS23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIS23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define TWIS24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIS24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIS24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +#define TWIS30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define TWIS30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ +#define TWIS30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +/*Memory configuration*/ +#define MEMCONF_PRESENT 1 +#define MEMCONF_COUNT 1 + +#define MEMCONF_RETTRIM 1 /*!< (unspecified) */ +#define MEMCONF_REPAIR 0 /*!< (unspecified) */ +#define MEMCONF_POWER 1 /*!< (unspecified) */ + +/*Pulse Density Modulation (Digital Microphone) Interface*/ +#define PDM_PRESENT 1 +#define PDM_COUNT 2 + +#define PDM20_SAMPLE16 0 /*!< (unspecified) */ +#define PDM20_SAMPLE48 1 /*!< Supports 8, 16, 32, 48 kHz sample rate. */ +#define PDM20_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define PDM20_PDMV2 1 /*!< (unspecified) */ +#define PDM20_PCLK24M 1 /*!< (unspecified) */ +#define PDM20_AUDIOPLL 0 /*!< (unspecified) */ +#define PDM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< CURRENTAMOUNT register included. */ + +#define PDM21_SAMPLE16 0 /*!< (unspecified) */ +#define PDM21_SAMPLE48 1 /*!< Supports 8, 16, 32, 48 kHz sample rate. */ +#define PDM21_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define PDM21_PDMV2 1 /*!< (unspecified) */ +#define PDM21_PCLK24M 1 /*!< (unspecified) */ +#define PDM21_AUDIOPLL 0 /*!< (unspecified) */ +#define PDM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< CURRENTAMOUNT register included. */ + +/*Pulse width modulation unit*/ +#define PWM_PRESENT 1 +#define PWM_COUNT 3 + +#define PWM20_IDLE_OUT 1 /*!< IDLEOUT register is available. */ +#define PWM20_COMPARE_MATCH 1 /*!< EVENTS_COMPAREMATCH events are available. */ +#define PWM20_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM20_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< CURRENTAMOUNT register included. */ + +#define PWM21_IDLE_OUT 1 /*!< IDLEOUT register is available. */ +#define PWM21_COMPARE_MATCH 1 /*!< EVENTS_COMPAREMATCH events are available. */ +#define PWM21_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM21_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< CURRENTAMOUNT register included. */ + +#define PWM22_IDLE_OUT 1 /*!< IDLEOUT register is available. */ +#define PWM22_COMPARE_MATCH 1 /*!< EVENTS_COMPAREMATCH events are available. */ +#define PWM22_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM22_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< CURRENTAMOUNT register included. */ + +/*Analog to Digital Converter*/ +#define SAADC_PRESENT 1 +#define SAADC_COUNT 1 + +#define SAADC_CHOPPING 1 /*!< (unspecified) */ +#define SAADC_BURSTREG 1 /*!< (unspecified) */ +#define SAADC_PSEL_V2 1 /*!< (unspecified) */ +#define SAADC_TASKS_CALIBRATEGAIN 1 /*!< (unspecified) */ +#define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 8 /*!< (unspecified) */ +#define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ +#define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ +#define SAADC_TACQ_VALUE_RANGE_MIN 1 /*!< (unspecified) */ +#define SAADC_TACQ_VALUE_RANGE_MAX 319 /*!< (unspecified) */ +#define SAADC_TACQ_VALUE_RANGE_SIZE 320 /*!< (unspecified) */ +#define SAADC_TCONV_VALUE_RANGE_MIN 1 /*!< (unspecified) */ +#define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< CURRENTAMOUNT register included. */ + +/*NFC-A compatible radio NFC-A compatible radio*/ +#define NFCT_PRESENT 1 +#define NFCT_COUNT 1 + +#define NFCT_NFCTFIELDDETCFG_RESET 1 /*!< Reset value of register NFCTFIELDDETCFG: 1 */ + +/*Temperature Sensor*/ +#define TEMP_PRESENT 1 +#define TEMP_COUNT 1 + +/*GPIO Tasks and Events*/ +#define GPIOTE_PRESENT 1 +#define GPIOTE_COUNT 2 + +#define GPIOTE20_IRQ_COUNT 2 +#define GPIOTE20_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE20_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE20_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE20_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..0 */ +#define GPIOTE20_GPIOTE_NPORTEVENTS_MAX 0 /*!< Number of GPIOTE port events: 0..0 */ +#define GPIOTE20_GPIOTE_NPORTEVENTS_SIZE 1 /*!< Number of GPIOTE port events: 0..0 */ +#define GPIOTE20_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE20_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE20_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE20_HAS_PORT_EVENT 1 /*!< (unspecified) */ + +#define GPIOTE30_IRQ_COUNT 2 +#define GPIOTE30_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..3 */ +#define GPIOTE30_GPIOTE_NCHANNELS_MAX 3 /*!< Number of GPIOTE channels: 0..3 */ +#define GPIOTE30_GPIOTE_NCHANNELS_SIZE 4 /*!< Number of GPIOTE channels: 0..3 */ +#define GPIOTE30_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..0 */ +#define GPIOTE30_GPIOTE_NPORTEVENTS_MAX 0 /*!< Number of GPIOTE port events: 0..0 */ +#define GPIOTE30_GPIOTE_NPORTEVENTS_SIZE 1 /*!< Number of GPIOTE port events: 0..0 */ +#define GPIOTE30_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE30_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE30_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE30_HAS_PORT_EVENT 1 /*!< (unspecified) */ + +/*Quadrature Decoder*/ +#define QDEC_PRESENT 1 +#define QDEC_COUNT 2 + +/*Global Real-time counter*/ +#define GRTC_PRESENT 1 +#define GRTC_COUNT 1 + +#define GRTC_IRQ_COUNT 4 +#define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..11 */ +#define GRTC_NCC_MAX 11 /*!< Number of compare/capture registers : 0..11 */ +#define GRTC_NCC_SIZE 12 /*!< Number of compare/capture registers : 0..11 */ +#define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..3 */ +#define GRTC_GRTC_NINTERRUPTS_MAX 3 /*!< Number of GRTC interrupts : 0..3 */ +#define GRTC_GRTC_NINTERRUPTS_SIZE 4 /*!< Number of GRTC interrupts : 0..3 */ +#define GRTC_PWMREGS 1 /*!< The PWM registers are available. */ +#define GRTC_CLKOUTREG 1 /*!< The CLKOUT register is available. */ +#define GRTC_CLKSELREG 1 /*!< The CLKCFG.CLKSEL register is available. */ +#define GRTC_CLKSELLFLPRC 1 /*!< The CLKCFG.CLKSEL register supports LFLPRC. */ +#define GRTC_CCADD_WRITE_ONLY 1 /*!< The CC[n].CCADD register has write access only. */ +#define GRTC_READY_STATUS_AND_EVENTS 1 /*!< The ready status and events are available. */ +#define GRTC_MULTIINTERVAL 0 /*!< (unspecified) */ +#define GRTC_STATUSDEBUGREG 0 /*!< (unspecified) */ +#define GRTC_SYSCOUNTER_LOADED_STATUS 1 /*!< SYSCOUNTER[n].SYSCOUNTERH.LOADED status is available */ +#define GRTC_CC_PAST_STATUS 1 /*!< CC[n].CCEN.PASTCC status is available */ +#define GRTC_SYSCOUNTER_WRITEABLE 1 /*!< (unspecified) */ + +/*Time division multiplexed audio interface*/ +#define TDM_PRESENT 1 +#define TDM_COUNT 1 + +#define TDM_NUM_CHANNELS_MIN 0 /*!< (unspecified) */ +#define TDM_NUM_CHANNELS_MAX 7 /*!< (unspecified) */ +#define TDM_NUM_CHANNELS_SIZE 8 /*!< (unspecified) */ +#define TDM_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< CURRENTAMOUNT register included. */ + +/*Tamper controller*/ +#define TAMPC_PRESENT 1 +#define TAMPC_COUNT 1 + +#define TAMPC_GPIOSWD 0 /*!< (unspecified) */ +#define TAMPC_APSPIDEN 0 /*!< (unspecified) */ +#define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 1 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 1 */ +#define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ +#define TAMPC_SM4DISABLECM 0 /*!< (unspecified) */ +#define TAMPC_PROTECTRESETBEHAVIOR 0 /*!< (unspecified) */ +#define TAMPC_SPIDEN 1 /*!< (unspecified) */ +#define TAMPC_SPNIDEN 1 /*!< (unspecified) */ +#define TAMPC_ACTIVESHIELD 1 /*!< (unspecified) */ + +/*Comparator*/ +#define COMP_PRESENT 1 +#define COMP_COUNT 1 + +/*Low-power comparator*/ +#define LPCOMP_PRESENT 1 +#define LPCOMP_COUNT 1 + +/*Watchdog Timer*/ +#define WDT_PRESENT 1 +#define WDT_COUNT 2 + +#define WDT30_ALLOW_STOP 1 /*!< (unspecified) */ +#define WDT30_HAS_INTEN 0 /*!< (unspecified) */ + +#define WDT31_ALLOW_STOP 1 /*!< (unspecified) */ +#define WDT31_HAS_INTEN 0 /*!< (unspecified) */ + +/*Clock management*/ +#define CLOCK_PRESENT 1 +#define CLOCK_COUNT 1 + +#define CLOCK_XOTUNE 1 /*!< (unspecified) */ +#define CLOCK_PLL24M 1 /*!< (unspecified) */ +#define CLOCK_VAR1_NXT 0 /*!< (unspecified) */ + +/*Power control*/ +#define POWER_PRESENT 1 +#define POWER_COUNT 1 + +#define POWER_CONSTLATSTAT 1 /*!< (unspecified) */ + +/*Reset control*/ +#define RESET_PRESENT 1 +#define RESET_COUNT 1 + +/*Oscillator control*/ +#define OSCILLATORS_PRESENT 1 +#define OSCILLATORS_COUNT 1 + +/*Voltage regulators*/ +#define REGULATORS_PRESENT 1 +#define REGULATORS_COUNT 1 + +#define REGULATORS_POF 1 /*!< (unspecified) */ + +/*VREGUSB peripheral*/ +#define VREGUSB_PRESENT 1 +#define VREGUSB_COUNT 1 + +#define VREGUSB_PROLONGED_WAKEUP 0 /*!< (unspecified) */ +#define VREGUSB_VAR1 1 /*!< (unspecified) */ + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core64M = 77824, /*!< 1200 baud (actual rate: 1159, -3.4 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core64M = 159744, /*!< 2400 baud (actual rate: 2380, -0.8 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core64M = 319488, /*!< 4800 baud (actual rate: 4760, -0.8 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core64M = 643072, /*!< 9600 baud (actual rate: 9583, -0.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core64M = 962560, /*!< 14400 baud (actual rate: 14343, -0.4 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core64M = 1286144, /*!< 19200 baud (actual rate: 19167, -0.2 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core64M = 1929216, /*!< 28800 baud (actual rate: 28751, -0.2 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core64M = 2097152, /*!< 31250 baud (actual rate: 31250, 0.0 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core64M = 2576384, /*!< 38400 baud (actual rate: 38392, -0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core64M = 3756032, /*!< 56000 baud (actual rate: 55993, -0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core64M = 3862528, /*!< 57600 baud (actual rate: 57605, 0.0 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core64M = 5152768, /*!< 76800 baud (actual rate: 76830, 0.0 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core64M = 7720960, /*!< 115200 baud (actual rate: 115107, -0.1 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core64M = 15446016, /*!< 230400 baud (actual rate: 230215, -0.1 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core64M = 16777216, /*!< 250000 baud (actual rate: 250000, 0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core64M = 30896128, /*!< 460800 baud (actual rate: 460431, -0.1 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core64M = 62242816, /*!< 921600 baud (actual rate: 927536, 0.6 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core64M = 67108864, /*!< 1000000 baud (actual rate: 1000000, 0.0 percent error), 64 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core128M = 36864, /*!< 1200 baud (actual rate: 1098, -8.4 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core128M = 77824, /*!< 2400 baud (actual rate: 2319, -3.4 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core128M = 159744, /*!< 4800 baud (actual rate: 4760, -0.8 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core128M = 319488, /*!< 9600 baud (actual rate: 9521, -0.8 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core128M = 479232, /*!< 14400 baud (actual rate: 14282, -0.8 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core128M = 643072, /*!< 19200 baud (actual rate: 19167, -0.2 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core128M = 962560, /*!< 28800 baud (actual rate: 28686, -0.4 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core128M = 1048576, /*!< 31250 baud (actual rate: 31250, 0.0 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core128M = 1286144, /*!< 38400 baud (actual rate: 38334, -0.2 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core128M = 1875968, /*!< 56000 baud (actual rate: 55919, -0.1 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core128M = 1929216, /*!< 57600 baud (actual rate: 57502, -0.2 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core128M = 2576384, /*!< 76800 baud (actual rate: 76784, -0.0 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core128M = 3862528, /*!< 115200 baud (actual rate: 115211, 0.0 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core128M = 7720960, /*!< 230400 baud (actual rate: 230215, -0.1 percent error), 128 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core128M = 8388608, /*!< 250000 baud (actual rate: 250000, 0.0 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core128M = 15446016, /*!< 460800 baud (actual rate: 460431, -0.1 percent error), 128 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core128M = 30896128, /*!< 921600 baud (actual rate: 920863, -0.1 percent error), 128 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core128M = 33554432, /*!< 1000000 baud (actual rate: 1000000, 0.0 percent error), 128 + MHz core frequency*/ +} NRF_UARTE00_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1190, -0.8 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2395, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4791, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14401, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19207, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28776, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31250, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38369, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 55944, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57553, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 76923, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115107, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 231884, 0.6 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250000, 0.0 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457142, -0.8 percent error), 16 + MHz core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 941176, 2.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1000000, 0.0 percent error), 16 + MHz core frequency*/ +} NRF_UARTE20_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1190, -0.8 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2395, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4791, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14401, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19207, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28776, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31250, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38369, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 55944, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57553, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 76923, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115107, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 231884, 0.6 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250000, 0.0 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457142, -0.8 percent error), 16 + MHz core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 941176, 2.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1000000, 0.0 percent error), 16 + MHz core frequency*/ +} NRF_UARTE21_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1190, -0.8 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2395, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4791, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14401, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19207, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28776, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31250, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38369, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 55944, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57553, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 76923, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115107, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 231884, 0.6 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250000, 0.0 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457142, -0.8 percent error), 16 + MHz core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 941176, 2.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1000000, 0.0 percent error), 16 + MHz core frequency*/ +} NRF_UARTE22_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1190, -0.8 percent error), 16 MHz core + frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2395, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4791, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14401, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19207, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28776, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31250, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38369, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 55944, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57553, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 76923, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115107, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 231884, 0.6 percent error), 16 MHz + core frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250000, 0.0 percent error), 16 MHz + core frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457142, -0.8 percent error), 16 + MHz core frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 941176, 2.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE23_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1000000, 0.0 percent error), 16 + MHz core frequency*/ +} NRF_UARTE23_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1190, -0.8 percent error), 16 MHz core + frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2395, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4791, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14401, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19207, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28776, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31250, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38369, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 55944, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57553, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 76923, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115107, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 231884, 0.6 percent error), 16 MHz + core frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250000, 0.0 percent error), 16 MHz + core frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457142, -0.8 percent error), 16 + MHz core frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 941176, 2.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE24_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1000000, 0.0 percent error), 16 + MHz core frequency*/ +} NRF_UARTE24_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1190, -0.8 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2395, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4791, -0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14401, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19207, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28776, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31250, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38369, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 55944, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57553, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 76923, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115107, -0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 231884, 0.6 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250000, 0.0 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457142, -0.8 percent error), 16 + MHz core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 941176, 2.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1000000, 0.0 percent error), 16 + MHz core frequency*/ +} NRF_UARTE30_BAUDRATE_BAUDRATE_ENUM_t; + + +#ifdef __cplusplus +} +#endif +#endif /* NRF54LM20A_APPLICATION_PERIPHERALS_H */ + diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_flpr.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_flpr.h new file mode 100644 index 0000000..bf5fc8e --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_flpr.h @@ -0,0 +1,342 @@ +/* + +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF54LM20A_FLPR_H +#define NRF54LM20A_FLPR_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#ifdef NRF_FLPR /*!< Processor information is domain local. */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ===================================================== Core Interrupts ===================================================== */ +/* ============================================== Processor Specific Interrupts ============================================== */ + VPRCLIC_0_IRQn = 0, /*!< 0 VPRCLIC_0 */ + VPRCLIC_1_IRQn = 1, /*!< 1 VPRCLIC_1 */ + VPRCLIC_2_IRQn = 2, /*!< 2 VPRCLIC_2 */ + VPRCLIC_3_IRQn = 3, /*!< 3 VPRCLIC_3 */ + VPRCLIC_4_IRQn = 4, /*!< 4 VPRCLIC_4 */ + VPRCLIC_5_IRQn = 5, /*!< 5 VPRCLIC_5 */ + VPRCLIC_6_IRQn = 6, /*!< 6 VPRCLIC_6 */ + VPRCLIC_7_IRQn = 7, /*!< 7 VPRCLIC_7 */ + VPRCLIC_8_IRQn = 8, /*!< 8 VPRCLIC_8 */ + VPRCLIC_9_IRQn = 9, /*!< 9 VPRCLIC_9 */ + VPRCLIC_10_IRQn = 10, /*!< 10 VPRCLIC_10 */ + VPRCLIC_11_IRQn = 11, /*!< 11 VPRCLIC_11 */ + VPRCLIC_12_IRQn = 12, /*!< 12 VPRCLIC_12 */ + VPRCLIC_13_IRQn = 13, /*!< 13 VPRCLIC_13 */ + VPRCLIC_14_IRQn = 14, /*!< 14 VPRCLIC_14 */ + VPRCLIC_15_IRQn = 15, /*!< 15 VPRCLIC_15 */ + VPRCLIC_16_IRQn = 16, /*!< 16 VPRCLIC_16 */ + VPRCLIC_17_IRQn = 17, /*!< 17 VPRCLIC_17 */ + VPRCLIC_18_IRQn = 18, /*!< 18 VPRCLIC_18 */ + VPRCLIC_19_IRQn = 19, /*!< 19 VPRCLIC_19 */ + VPRCLIC_20_IRQn = 20, /*!< 20 VPRCLIC_20 */ + VPRCLIC_21_IRQn = 21, /*!< 21 VPRCLIC_21 */ + VPRCLIC_22_IRQn = 22, /*!< 22 VPRCLIC_22 */ + VPRCLIC_23_IRQn = 23, /*!< 23 VPRCLIC_23 */ + VPRCLIC_24_IRQn = 24, /*!< 24 VPRCLIC_24 */ + VPRCLIC_25_IRQn = 25, /*!< 25 VPRCLIC_25 */ + VPRCLIC_26_IRQn = 26, /*!< 26 VPRCLIC_26 */ + VPRCLIC_27_IRQn = 27, /*!< 27 VPRCLIC_27 */ + VPRCLIC_28_IRQn = 28, /*!< 28 VPRCLIC_28 */ + VPRCLIC_29_IRQn = 29, /*!< 29 VPRCLIC_29 */ + VPRCLIC_30_IRQn = 30, /*!< 30 VPRCLIC_30 */ + VPRCLIC_31_IRQn = 31, /*!< 31 VPRCLIC_31 */ + SPU00_IRQn = 64, /*!< 64 SPU00 */ + MPC00_IRQn = 65, /*!< 65 MPC00 */ + AAR00_CCM00_IRQn = 74, /*!< 74 AAR00_CCM00 */ + ECB00_IRQn = 75, /*!< 75 ECB00 */ + VPR00_IRQn = 76, /*!< 76 VPR00 */ + SERIAL00_IRQn = 77, /*!< 77 SERIAL00 */ + RRAMC_IRQn = 78, /*!< 78 RRAMC */ + CTRLAP_IRQn = 82, /*!< 82 CTRLAP */ + CM33SS_IRQn = 84, /*!< 84 CM33SS */ + TIMER00_IRQn = 85, /*!< 85 TIMER00 */ + EGU00_IRQn = 88, /*!< 88 EGU00 */ + CRACEN_IRQn = 89, /*!< 89 CRACEN */ + USBHS_IRQn = 90, /*!< 90 USBHS */ + SPU10_IRQn = 128, /*!< 128 SPU10 */ + TIMER10_IRQn = 133, /*!< 133 TIMER10 */ + EGU10_IRQn = 135, /*!< 135 EGU10 */ + RADIO_0_IRQn = 138, /*!< 138 RADIO_0 */ + RADIO_1_IRQn = 139, /*!< 139 RADIO_1 */ + SPU20_IRQn = 192, /*!< 192 SPU20 */ + SERIAL20_IRQn = 198, /*!< 198 SERIAL20 */ + SERIAL21_IRQn = 199, /*!< 199 SERIAL21 */ + SERIAL22_IRQn = 200, /*!< 200 SERIAL22 */ + EGU20_IRQn = 201, /*!< 201 EGU20 */ + TIMER20_IRQn = 202, /*!< 202 TIMER20 */ + TIMER21_IRQn = 203, /*!< 203 TIMER21 */ + TIMER22_IRQn = 204, /*!< 204 TIMER22 */ + TIMER23_IRQn = 205, /*!< 205 TIMER23 */ + TIMER24_IRQn = 206, /*!< 206 TIMER24 */ + PDM20_IRQn = 208, /*!< 208 PDM20 */ + PDM21_IRQn = 209, /*!< 209 PDM21 */ + PWM20_IRQn = 210, /*!< 210 PWM20 */ + PWM21_IRQn = 211, /*!< 211 PWM21 */ + PWM22_IRQn = 212, /*!< 212 PWM22 */ + SAADC_IRQn = 213, /*!< 213 SAADC */ + NFCT_IRQn = 214, /*!< 214 NFCT */ + TEMP_IRQn = 215, /*!< 215 TEMP */ + GPIOTE20_0_IRQn = 218, /*!< 218 GPIOTE20_0 */ + GPIOTE20_1_IRQn = 219, /*!< 219 GPIOTE20_1 */ + QDEC20_IRQn = 224, /*!< 224 QDEC20 */ + QDEC21_IRQn = 225, /*!< 225 QDEC21 */ + GRTC_0_IRQn = 226, /*!< 226 GRTC_0 */ + GRTC_1_IRQn = 227, /*!< 227 GRTC_1 */ + GRTC_2_IRQn = 228, /*!< 228 GRTC_2 */ + GRTC_3_IRQn = 229, /*!< 229 GRTC_3 */ + TDM_IRQn = 232, /*!< 232 TDM */ + SERIAL23_IRQn = 237, /*!< 237 SERIAL23 */ + SERIAL24_IRQn = 238, /*!< 238 SERIAL24 */ + TAMPC_IRQn = 239, /*!< 239 TAMPC */ + SPU30_IRQn = 256, /*!< 256 SPU30 */ + SERIAL30_IRQn = 260, /*!< 260 SERIAL30 */ + COMP_LPCOMP_IRQn = 262, /*!< 262 COMP_LPCOMP */ + WDT30_IRQn = 264, /*!< 264 WDT30 */ + WDT31_IRQn = 265, /*!< 265 WDT31 */ + GPIOTE30_0_IRQn = 268, /*!< 268 GPIOTE30_0 */ + GPIOTE30_1_IRQn = 269, /*!< 269 GPIOTE30_1 */ + CLOCK_POWER_IRQn = 270, /*!< 270 CLOCK_POWER */ + VREGUSB_IRQn = 289, /*!< 289 VREGUSB */ +} IRQn_Type; + +/* ==================================================== Interrupt Aliases ==================================================== */ +#define AAR00_IRQn AAR00_CCM00_IRQn +#define AAR00_IRQHandler AAR00_CCM00_IRQHandler +#define CCM00_IRQn AAR00_CCM00_IRQn +#define CCM00_IRQHandler AAR00_CCM00_IRQHandler +#define SPIM00_IRQn SERIAL00_IRQn +#define SPIM00_IRQHandler SERIAL00_IRQHandler +#define SPIS00_IRQn SERIAL00_IRQn +#define SPIS00_IRQHandler SERIAL00_IRQHandler +#define UARTE00_IRQn SERIAL00_IRQn +#define UARTE00_IRQHandler SERIAL00_IRQHandler +#define CPUC_IRQn CM33SS_IRQn +#define CPUC_IRQHandler CM33SS_IRQHandler +#define SPIM20_IRQn SERIAL20_IRQn +#define SPIM20_IRQHandler SERIAL20_IRQHandler +#define SPIS20_IRQn SERIAL20_IRQn +#define SPIS20_IRQHandler SERIAL20_IRQHandler +#define TWIM20_IRQn SERIAL20_IRQn +#define TWIM20_IRQHandler SERIAL20_IRQHandler +#define TWIS20_IRQn SERIAL20_IRQn +#define TWIS20_IRQHandler SERIAL20_IRQHandler +#define UARTE20_IRQn SERIAL20_IRQn +#define UARTE20_IRQHandler SERIAL20_IRQHandler +#define SPIM21_IRQn SERIAL21_IRQn +#define SPIM21_IRQHandler SERIAL21_IRQHandler +#define SPIS21_IRQn SERIAL21_IRQn +#define SPIS21_IRQHandler SERIAL21_IRQHandler +#define TWIM21_IRQn SERIAL21_IRQn +#define TWIM21_IRQHandler SERIAL21_IRQHandler +#define TWIS21_IRQn SERIAL21_IRQn +#define TWIS21_IRQHandler SERIAL21_IRQHandler +#define UARTE21_IRQn SERIAL21_IRQn +#define UARTE21_IRQHandler SERIAL21_IRQHandler +#define SPIM22_IRQn SERIAL22_IRQn +#define SPIM22_IRQHandler SERIAL22_IRQHandler +#define SPIS22_IRQn SERIAL22_IRQn +#define SPIS22_IRQHandler SERIAL22_IRQHandler +#define TWIM22_IRQn SERIAL22_IRQn +#define TWIM22_IRQHandler SERIAL22_IRQHandler +#define TWIS22_IRQn SERIAL22_IRQn +#define TWIS22_IRQHandler SERIAL22_IRQHandler +#define UARTE22_IRQn SERIAL22_IRQn +#define UARTE22_IRQHandler SERIAL22_IRQHandler +#define SPIM23_IRQn SERIAL23_IRQn +#define SPIM23_IRQHandler SERIAL23_IRQHandler +#define SPIS23_IRQn SERIAL23_IRQn +#define SPIS23_IRQHandler SERIAL23_IRQHandler +#define TWIM23_IRQn SERIAL23_IRQn +#define TWIM23_IRQHandler SERIAL23_IRQHandler +#define TWIS23_IRQn SERIAL23_IRQn +#define TWIS23_IRQHandler SERIAL23_IRQHandler +#define UARTE23_IRQn SERIAL23_IRQn +#define UARTE23_IRQHandler SERIAL23_IRQHandler +#define SPIM24_IRQn SERIAL24_IRQn +#define SPIM24_IRQHandler SERIAL24_IRQHandler +#define SPIS24_IRQn SERIAL24_IRQn +#define SPIS24_IRQHandler SERIAL24_IRQHandler +#define TWIM24_IRQn SERIAL24_IRQn +#define TWIM24_IRQHandler SERIAL24_IRQHandler +#define TWIS24_IRQn SERIAL24_IRQn +#define TWIS24_IRQHandler SERIAL24_IRQHandler +#define UARTE24_IRQn SERIAL24_IRQn +#define UARTE24_IRQHandler SERIAL24_IRQHandler +#define SPIM30_IRQn SERIAL30_IRQn +#define SPIM30_IRQHandler SERIAL30_IRQHandler +#define SPIS30_IRQn SERIAL30_IRQn +#define SPIS30_IRQHandler SERIAL30_IRQHandler +#define TWIM30_IRQn SERIAL30_IRQn +#define TWIM30_IRQHandler SERIAL30_IRQHandler +#define TWIS30_IRQn SERIAL30_IRQn +#define TWIS30_IRQHandler SERIAL30_IRQHandler +#define UARTE30_IRQn SERIAL30_IRQn +#define UARTE30_IRQHandler SERIAL30_IRQHandler +#define COMP_IRQn COMP_LPCOMP_IRQn +#define COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define CLOCK_IRQn CLOCK_POWER_IRQn +#define CLOCK_IRQHandler CLOCK_POWER_IRQHandler +#define POWER_IRQn CLOCK_POWER_IRQn +#define POWER_IRQHandler CLOCK_POWER_IRQHandler + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ +#define __VPR_REV 1.4.1 /*!< VPR Core Revision */ +#define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ +#define __VPR_REV_MINOR 4 /*!< VPR Core Minor Revision */ +#define __VPR_REV_PATCH 1 /*!< VPR Core Patch Revision */ +#define __DSP_PRESENT 0 /*!< DSP present or not */ +#define __CLIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ +#define __FPU_DP 0 /*!< Double Precision FPU */ +#define __INTERRUPTS_MAX 270 /*!< Size of interrupt vector table */ + +#define NRF_VPR NRF_VPR00 /*!< VPR instance name */ +#include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ +#include "system_nrf.h" /*!< nrf54lm20a_flpr System Library */ + +#endif /*!< NRF_FLPR */ + + +#ifdef NRF_FLPR + + #define NRF_DOMAIN NRF_DOMAIN_NONE + #define NRF_PROCESSOR NRF_PROCESSOR_VPR + +#endif /*!< NRF_FLPR */ + + +/* ========================================= Start of section using anonymous unions ========================================= */ + +#include "compiler_abstraction.h" + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Unsupported compiler type +#endif + +/* =========================================================================================================================== */ +/* ================ Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define NRF_FLPR_VPRCLIC_NS_BASE 0xF0000000UL + +/* =========================================================================================================================== */ +/* ================ Peripheral Declaration ================ */ +/* =========================================================================================================================== */ + +#define NRF_FLPR_VPRCLIC_NS ((NRF_CLIC_Type*) NRF_FLPR_VPRCLIC_NS_BASE) + +/* =========================================================================================================================== */ +/* ================ TrustZone Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ + #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_NS +#else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ + #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_NS +#endif /*!< NRF_TRUSTZONE_NONSECURE */ + +/* =========================================================================================================================== */ +/* ================ Local Domain Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_FLPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ + #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ + #define NRF_VPRCLIC NRF_FLPR_VPRCLIC + #else /*!< Remap all instances. */ + #define NRF_VPRCLIC NRF_FLPR_VPRCLIC + #endif /*!< NRF_TRUSTZONE_NONSECURE */ +#endif /*!< NRF_FLPR */ + +/* ========================================== End of section using anonymous unions ========================================== */ + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif +#endif /* NRF54LM20A_FLPR_H */ + diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_global.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_global.h new file mode 100644 index 0000000..dfec076 --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_global.h @@ -0,0 +1,715 @@ +/* + +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF54LM20A_GLOBAL_H +#define NRF54LM20A_GLOBAL_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ========================================= Start of section using anonymous unions ========================================= */ + +#include "compiler_abstraction.h" + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Unsupported compiler type +#endif + +/* =========================================================================================================================== */ +/* ================ Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define NRF_FICR_NS_BASE 0x00FFC000UL +#define NRF_UICR_S_BASE 0x00FFD000UL +#define NRF_SICR_S_BASE 0x00FFE000UL +#define NRF_CRACENCORE_S_BASE 0x50010000UL +#define NRF_USBHSCORE_NS_BASE 0x40020000UL +#define NRF_USBHSCORE_S_BASE 0x50020000UL +#define NRF_SPU00_S_BASE 0x50040000UL +#define NRF_MPC00_S_BASE 0x50041000UL +#define NRF_DPPIC00_NS_BASE 0x40042000UL +#define NRF_DPPIC00_S_BASE 0x50042000UL +#define NRF_PPIB00_NS_BASE 0x40044000UL +#define NRF_PPIB00_S_BASE 0x50044000UL +#define NRF_PPIB01_NS_BASE 0x40045000UL +#define NRF_PPIB01_S_BASE 0x50045000UL +#define NRF_KMU_S_BASE 0x50049000UL +#define NRF_AAR00_NS_BASE 0x4004A000UL +#define NRF_CCM00_NS_BASE 0x4004A000UL +#define NRF_AAR00_S_BASE 0x5004A000UL +#define NRF_CCM00_S_BASE 0x5004A000UL +#define NRF_ECB00_NS_BASE 0x4004B000UL +#define NRF_ECB00_S_BASE 0x5004B000UL +#define NRF_VPR00_NS_BASE 0x4004C000UL +#define NRF_VPR00_S_BASE 0x5004C000UL +#define NRF_SPIM00_NS_BASE 0x4004D000UL +#define NRF_SPIS00_NS_BASE 0x4004D000UL +#define NRF_UARTE00_NS_BASE 0x4004D000UL +#define NRF_SPIM00_S_BASE 0x5004D000UL +#define NRF_SPIS00_S_BASE 0x5004D000UL +#define NRF_UARTE00_S_BASE 0x5004D000UL +#define NRF_GLITCHDET_S_BASE 0x5004E000UL +#define NRF_RRAMC_S_BASE 0x5004E000UL +#define NRF_GPIOHSPADCTRL_NS_BASE 0x40050400UL +#define NRF_P2_NS_BASE 0x40050400UL +#define NRF_GPIOHSPADCTRL_S_BASE 0x50050400UL +#define NRF_P2_S_BASE 0x50050400UL +#define NRF_CTRLAP_NS_BASE 0x40052000UL +#define NRF_CTRLAP_S_BASE 0x50052000UL +#define NRF_TAD_NS_BASE 0x40053000UL +#define NRF_TAD_S_BASE 0x50053000UL +#define NRF_TIMER00_NS_BASE 0x40055000UL +#define NRF_TIMER00_S_BASE 0x50055000UL +#define NRF_EGU00_NS_BASE 0x40058000UL +#define NRF_EGU00_S_BASE 0x50058000UL +#define NRF_CRACEN_S_BASE 0x50059000UL +#define NRF_USBHS_NS_BASE 0x4005A000UL +#define NRF_USBHS_S_BASE 0x5005A000UL +#define NRF_SPU10_S_BASE 0x50080000UL +#define NRF_DPPIC10_NS_BASE 0x40082000UL +#define NRF_DPPIC10_S_BASE 0x50082000UL +#define NRF_PPIB10_NS_BASE 0x40083000UL +#define NRF_PPIB10_S_BASE 0x50083000UL +#define NRF_PPIB11_NS_BASE 0x40084000UL +#define NRF_PPIB11_S_BASE 0x50084000UL +#define NRF_TIMER10_NS_BASE 0x40085000UL +#define NRF_TIMER10_S_BASE 0x50085000UL +#define NRF_EGU10_NS_BASE 0x40087000UL +#define NRF_EGU10_S_BASE 0x50087000UL +#define NRF_RADIO_NS_BASE 0x4008A000UL +#define NRF_RADIO_S_BASE 0x5008A000UL +#define NRF_SPU20_S_BASE 0x500C0000UL +#define NRF_DPPIC20_NS_BASE 0x400C2000UL +#define NRF_DPPIC20_S_BASE 0x500C2000UL +#define NRF_PPIB20_NS_BASE 0x400C3000UL +#define NRF_PPIB20_S_BASE 0x500C3000UL +#define NRF_PPIB21_NS_BASE 0x400C4000UL +#define NRF_PPIB21_S_BASE 0x500C4000UL +#define NRF_PPIB22_NS_BASE 0x400C5000UL +#define NRF_PPIB22_S_BASE 0x500C5000UL +#define NRF_SPIM20_NS_BASE 0x400C6000UL +#define NRF_SPIS20_NS_BASE 0x400C6000UL +#define NRF_TWIM20_NS_BASE 0x400C6000UL +#define NRF_TWIS20_NS_BASE 0x400C6000UL +#define NRF_UARTE20_NS_BASE 0x400C6000UL +#define NRF_SPIM20_S_BASE 0x500C6000UL +#define NRF_SPIS20_S_BASE 0x500C6000UL +#define NRF_TWIM20_S_BASE 0x500C6000UL +#define NRF_TWIS20_S_BASE 0x500C6000UL +#define NRF_UARTE20_S_BASE 0x500C6000UL +#define NRF_SPIM21_NS_BASE 0x400C7000UL +#define NRF_SPIS21_NS_BASE 0x400C7000UL +#define NRF_TWIM21_NS_BASE 0x400C7000UL +#define NRF_TWIS21_NS_BASE 0x400C7000UL +#define NRF_UARTE21_NS_BASE 0x400C7000UL +#define NRF_SPIM21_S_BASE 0x500C7000UL +#define NRF_SPIS21_S_BASE 0x500C7000UL +#define NRF_TWIM21_S_BASE 0x500C7000UL +#define NRF_TWIS21_S_BASE 0x500C7000UL +#define NRF_UARTE21_S_BASE 0x500C7000UL +#define NRF_SPIM22_NS_BASE 0x400C8000UL +#define NRF_SPIS22_NS_BASE 0x400C8000UL +#define NRF_TWIM22_NS_BASE 0x400C8000UL +#define NRF_TWIS22_NS_BASE 0x400C8000UL +#define NRF_UARTE22_NS_BASE 0x400C8000UL +#define NRF_SPIM22_S_BASE 0x500C8000UL +#define NRF_SPIS22_S_BASE 0x500C8000UL +#define NRF_TWIM22_S_BASE 0x500C8000UL +#define NRF_TWIS22_S_BASE 0x500C8000UL +#define NRF_UARTE22_S_BASE 0x500C8000UL +#define NRF_EGU20_NS_BASE 0x400C9000UL +#define NRF_EGU20_S_BASE 0x500C9000UL +#define NRF_TIMER20_NS_BASE 0x400CA000UL +#define NRF_TIMER20_S_BASE 0x500CA000UL +#define NRF_TIMER21_NS_BASE 0x400CB000UL +#define NRF_TIMER21_S_BASE 0x500CB000UL +#define NRF_TIMER22_NS_BASE 0x400CC000UL +#define NRF_TIMER22_S_BASE 0x500CC000UL +#define NRF_TIMER23_NS_BASE 0x400CD000UL +#define NRF_TIMER23_S_BASE 0x500CD000UL +#define NRF_TIMER24_NS_BASE 0x400CE000UL +#define NRF_TIMER24_S_BASE 0x500CE000UL +#define NRF_MEMCONF_NS_BASE 0x400CF000UL +#define NRF_MEMCONF_S_BASE 0x500CF000UL +#define NRF_PDM20_NS_BASE 0x400D0000UL +#define NRF_PDM20_S_BASE 0x500D0000UL +#define NRF_PDM21_NS_BASE 0x400D1000UL +#define NRF_PDM21_S_BASE 0x500D1000UL +#define NRF_PWM20_NS_BASE 0x400D2000UL +#define NRF_PWM20_S_BASE 0x500D2000UL +#define NRF_PWM21_NS_BASE 0x400D3000UL +#define NRF_PWM21_S_BASE 0x500D3000UL +#define NRF_PWM22_NS_BASE 0x400D4000UL +#define NRF_PWM22_S_BASE 0x500D4000UL +#define NRF_SAADC_NS_BASE 0x400D5000UL +#define NRF_SAADC_S_BASE 0x500D5000UL +#define NRF_NFCT_NS_BASE 0x400D6000UL +#define NRF_NFCT_S_BASE 0x500D6000UL +#define NRF_TEMP_NS_BASE 0x400D7000UL +#define NRF_TEMP_S_BASE 0x500D7000UL +#define NRF_P1_NS_BASE 0x400D8200UL +#define NRF_P3_NS_BASE 0x400D8600UL +#define NRF_P1_S_BASE 0x500D8200UL +#define NRF_P3_S_BASE 0x500D8600UL +#define NRF_GPIOTE20_NS_BASE 0x400DA000UL +#define NRF_GPIOTE20_S_BASE 0x500DA000UL +#define NRF_QDEC20_NS_BASE 0x400E0000UL +#define NRF_QDEC20_S_BASE 0x500E0000UL +#define NRF_QDEC21_NS_BASE 0x400E1000UL +#define NRF_QDEC21_S_BASE 0x500E1000UL +#define NRF_GRTC_NS_BASE 0x400E2000UL +#define NRF_GRTC_S_BASE 0x500E2000UL +#define NRF_TDM_NS_BASE 0x400E8000UL +#define NRF_TDM_S_BASE 0x500E8000UL +#define NRF_SPIM23_NS_BASE 0x400ED000UL +#define NRF_SPIS23_NS_BASE 0x400ED000UL +#define NRF_TWIM23_NS_BASE 0x400ED000UL +#define NRF_TWIS23_NS_BASE 0x400ED000UL +#define NRF_UARTE23_NS_BASE 0x400ED000UL +#define NRF_SPIM23_S_BASE 0x500ED000UL +#define NRF_SPIS23_S_BASE 0x500ED000UL +#define NRF_TWIM23_S_BASE 0x500ED000UL +#define NRF_TWIS23_S_BASE 0x500ED000UL +#define NRF_UARTE23_S_BASE 0x500ED000UL +#define NRF_SPIM24_NS_BASE 0x400EE000UL +#define NRF_SPIS24_NS_BASE 0x400EE000UL +#define NRF_TWIM24_NS_BASE 0x400EE000UL +#define NRF_TWIS24_NS_BASE 0x400EE000UL +#define NRF_UARTE24_NS_BASE 0x400EE000UL +#define NRF_SPIM24_S_BASE 0x500EE000UL +#define NRF_SPIS24_S_BASE 0x500EE000UL +#define NRF_TWIM24_S_BASE 0x500EE000UL +#define NRF_TWIS24_S_BASE 0x500EE000UL +#define NRF_UARTE24_S_BASE 0x500EE000UL +#define NRF_TAMPC_S_BASE 0x500EF000UL +#define NRF_SPU30_S_BASE 0x50100000UL +#define NRF_DPPIC30_NS_BASE 0x40102000UL +#define NRF_DPPIC30_S_BASE 0x50102000UL +#define NRF_PPIB30_NS_BASE 0x40103000UL +#define NRF_PPIB30_S_BASE 0x50103000UL +#define NRF_SPIM30_NS_BASE 0x40104000UL +#define NRF_SPIS30_NS_BASE 0x40104000UL +#define NRF_TWIM30_NS_BASE 0x40104000UL +#define NRF_TWIS30_NS_BASE 0x40104000UL +#define NRF_UARTE30_NS_BASE 0x40104000UL +#define NRF_SPIM30_S_BASE 0x50104000UL +#define NRF_SPIS30_S_BASE 0x50104000UL +#define NRF_TWIM30_S_BASE 0x50104000UL +#define NRF_TWIS30_S_BASE 0x50104000UL +#define NRF_UARTE30_S_BASE 0x50104000UL +#define NRF_COMP_NS_BASE 0x40106000UL +#define NRF_LPCOMP_NS_BASE 0x40106000UL +#define NRF_COMP_S_BASE 0x50106000UL +#define NRF_LPCOMP_S_BASE 0x50106000UL +#define NRF_WDT30_S_BASE 0x50108000UL +#define NRF_WDT31_NS_BASE 0x40109000UL +#define NRF_WDT31_S_BASE 0x50109000UL +#define NRF_P0_NS_BASE 0x4010A000UL +#define NRF_P0_S_BASE 0x5010A000UL +#define NRF_GPIOTE30_NS_BASE 0x4010C000UL +#define NRF_GPIOTE30_S_BASE 0x5010C000UL +#define NRF_CLOCK_NS_BASE 0x4010E000UL +#define NRF_POWER_NS_BASE 0x4010E000UL +#define NRF_RESET_NS_BASE 0x4010E000UL +#define NRF_CLOCK_S_BASE 0x5010E000UL +#define NRF_POWER_S_BASE 0x5010E000UL +#define NRF_RESET_S_BASE 0x5010E000UL +#define NRF_OSCILLATORS_NS_BASE 0x40120000UL +#define NRF_REGULATORS_NS_BASE 0x40120000UL +#define NRF_OSCILLATORS_S_BASE 0x50120000UL +#define NRF_REGULATORS_S_BASE 0x50120000UL +#define NRF_VREGUSB_NS_BASE 0x40121000UL +#define NRF_VREGUSB_S_BASE 0x50121000UL + +/* =========================================================================================================================== */ +/* ================ Peripheral Declaration ================ */ +/* =========================================================================================================================== */ + +#define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE) +#define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE) +#define NRF_SICR_S ((NRF_SICR_Type*) NRF_SICR_S_BASE) +#define NRF_CRACENCORE_S ((NRF_CRACENCORE_Type*) NRF_CRACENCORE_S_BASE) +#define NRF_USBHSCORE_NS ((NRF_USBHSCORE_Type*) NRF_USBHSCORE_NS_BASE) +#define NRF_USBHSCORE_S ((NRF_USBHSCORE_Type*) NRF_USBHSCORE_S_BASE) +#define NRF_SPU00_S ((NRF_SPU_Type*) NRF_SPU00_S_BASE) +#define NRF_MPC00_S ((NRF_MPC_Type*) NRF_MPC00_S_BASE) +#define NRF_DPPIC00_NS ((NRF_DPPIC_Type*) NRF_DPPIC00_NS_BASE) +#define NRF_DPPIC00_S ((NRF_DPPIC_Type*) NRF_DPPIC00_S_BASE) +#define NRF_PPIB00_NS ((NRF_PPIB_Type*) NRF_PPIB00_NS_BASE) +#define NRF_PPIB00_S ((NRF_PPIB_Type*) NRF_PPIB00_S_BASE) +#define NRF_PPIB01_NS ((NRF_PPIB_Type*) NRF_PPIB01_NS_BASE) +#define NRF_PPIB01_S ((NRF_PPIB_Type*) NRF_PPIB01_S_BASE) +#define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE) +#define NRF_AAR00_NS ((NRF_AAR_Type*) NRF_AAR00_NS_BASE) +#define NRF_CCM00_NS ((NRF_CCM_Type*) NRF_CCM00_NS_BASE) +#define NRF_AAR00_S ((NRF_AAR_Type*) NRF_AAR00_S_BASE) +#define NRF_CCM00_S ((NRF_CCM_Type*) NRF_CCM00_S_BASE) +#define NRF_ECB00_NS ((NRF_ECB_Type*) NRF_ECB00_NS_BASE) +#define NRF_ECB00_S ((NRF_ECB_Type*) NRF_ECB00_S_BASE) +#define NRF_VPR00_NS ((NRF_VPR_Type*) NRF_VPR00_NS_BASE) +#define NRF_VPR00_S ((NRF_VPR_Type*) NRF_VPR00_S_BASE) +#define NRF_SPIM00_NS ((NRF_SPIM_Type*) NRF_SPIM00_NS_BASE) +#define NRF_SPIS00_NS ((NRF_SPIS_Type*) NRF_SPIS00_NS_BASE) +#define NRF_UARTE00_NS ((NRF_UARTE_Type*) NRF_UARTE00_NS_BASE) +#define NRF_SPIM00_S ((NRF_SPIM_Type*) NRF_SPIM00_S_BASE) +#define NRF_SPIS00_S ((NRF_SPIS_Type*) NRF_SPIS00_S_BASE) +#define NRF_UARTE00_S ((NRF_UARTE_Type*) NRF_UARTE00_S_BASE) +#define NRF_GLITCHDET_S ((NRF_GLITCHDET_Type*) NRF_GLITCHDET_S_BASE) +#define NRF_RRAMC_S ((NRF_RRAMC_Type*) NRF_RRAMC_S_BASE) +#define NRF_GPIOHSPADCTRL_NS ((NRF_GPIOHSPADCTRL_Type*) NRF_GPIOHSPADCTRL_NS_BASE) +#define NRF_P2_NS ((NRF_GPIO_Type*) NRF_P2_NS_BASE) +#define NRF_GPIOHSPADCTRL_S ((NRF_GPIOHSPADCTRL_Type*) NRF_GPIOHSPADCTRL_S_BASE) +#define NRF_P2_S ((NRF_GPIO_Type*) NRF_P2_S_BASE) +#define NRF_CTRLAP_NS ((NRF_CTRLAPPERI_Type*) NRF_CTRLAP_NS_BASE) +#define NRF_CTRLAP_S ((NRF_CTRLAPPERI_Type*) NRF_CTRLAP_S_BASE) +#define NRF_TAD_NS ((NRF_TAD_Type*) NRF_TAD_NS_BASE) +#define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE) +#define NRF_TIMER00_NS ((NRF_TIMER_Type*) NRF_TIMER00_NS_BASE) +#define NRF_TIMER00_S ((NRF_TIMER_Type*) NRF_TIMER00_S_BASE) +#define NRF_EGU00_NS ((NRF_EGU_Type*) NRF_EGU00_NS_BASE) +#define NRF_EGU00_S ((NRF_EGU_Type*) NRF_EGU00_S_BASE) +#define NRF_CRACEN_S ((NRF_CRACEN_Type*) NRF_CRACEN_S_BASE) +#define NRF_USBHS_NS ((NRF_USBHS_Type*) NRF_USBHS_NS_BASE) +#define NRF_USBHS_S ((NRF_USBHS_Type*) NRF_USBHS_S_BASE) +#define NRF_SPU10_S ((NRF_SPU_Type*) NRF_SPU10_S_BASE) +#define NRF_DPPIC10_NS ((NRF_DPPIC_Type*) NRF_DPPIC10_NS_BASE) +#define NRF_DPPIC10_S ((NRF_DPPIC_Type*) NRF_DPPIC10_S_BASE) +#define NRF_PPIB10_NS ((NRF_PPIB_Type*) NRF_PPIB10_NS_BASE) +#define NRF_PPIB10_S ((NRF_PPIB_Type*) NRF_PPIB10_S_BASE) +#define NRF_PPIB11_NS ((NRF_PPIB_Type*) NRF_PPIB11_NS_BASE) +#define NRF_PPIB11_S ((NRF_PPIB_Type*) NRF_PPIB11_S_BASE) +#define NRF_TIMER10_NS ((NRF_TIMER_Type*) NRF_TIMER10_NS_BASE) +#define NRF_TIMER10_S ((NRF_TIMER_Type*) NRF_TIMER10_S_BASE) +#define NRF_EGU10_NS ((NRF_EGU_Type*) NRF_EGU10_NS_BASE) +#define NRF_EGU10_S ((NRF_EGU_Type*) NRF_EGU10_S_BASE) +#define NRF_RADIO_NS ((NRF_RADIO_Type*) NRF_RADIO_NS_BASE) +#define NRF_RADIO_S ((NRF_RADIO_Type*) NRF_RADIO_S_BASE) +#define NRF_SPU20_S ((NRF_SPU_Type*) NRF_SPU20_S_BASE) +#define NRF_DPPIC20_NS ((NRF_DPPIC_Type*) NRF_DPPIC20_NS_BASE) +#define NRF_DPPIC20_S ((NRF_DPPIC_Type*) NRF_DPPIC20_S_BASE) +#define NRF_PPIB20_NS ((NRF_PPIB_Type*) NRF_PPIB20_NS_BASE) +#define NRF_PPIB20_S ((NRF_PPIB_Type*) NRF_PPIB20_S_BASE) +#define NRF_PPIB21_NS ((NRF_PPIB_Type*) NRF_PPIB21_NS_BASE) +#define NRF_PPIB21_S ((NRF_PPIB_Type*) NRF_PPIB21_S_BASE) +#define NRF_PPIB22_NS ((NRF_PPIB_Type*) NRF_PPIB22_NS_BASE) +#define NRF_PPIB22_S ((NRF_PPIB_Type*) NRF_PPIB22_S_BASE) +#define NRF_SPIM20_NS ((NRF_SPIM_Type*) NRF_SPIM20_NS_BASE) +#define NRF_SPIS20_NS ((NRF_SPIS_Type*) NRF_SPIS20_NS_BASE) +#define NRF_TWIM20_NS ((NRF_TWIM_Type*) NRF_TWIM20_NS_BASE) +#define NRF_TWIS20_NS ((NRF_TWIS_Type*) NRF_TWIS20_NS_BASE) +#define NRF_UARTE20_NS ((NRF_UARTE_Type*) NRF_UARTE20_NS_BASE) +#define NRF_SPIM20_S ((NRF_SPIM_Type*) NRF_SPIM20_S_BASE) +#define NRF_SPIS20_S ((NRF_SPIS_Type*) NRF_SPIS20_S_BASE) +#define NRF_TWIM20_S ((NRF_TWIM_Type*) NRF_TWIM20_S_BASE) +#define NRF_TWIS20_S ((NRF_TWIS_Type*) NRF_TWIS20_S_BASE) +#define NRF_UARTE20_S ((NRF_UARTE_Type*) NRF_UARTE20_S_BASE) +#define NRF_SPIM21_NS ((NRF_SPIM_Type*) NRF_SPIM21_NS_BASE) +#define NRF_SPIS21_NS ((NRF_SPIS_Type*) NRF_SPIS21_NS_BASE) +#define NRF_TWIM21_NS ((NRF_TWIM_Type*) NRF_TWIM21_NS_BASE) +#define NRF_TWIS21_NS ((NRF_TWIS_Type*) NRF_TWIS21_NS_BASE) +#define NRF_UARTE21_NS ((NRF_UARTE_Type*) NRF_UARTE21_NS_BASE) +#define NRF_SPIM21_S ((NRF_SPIM_Type*) NRF_SPIM21_S_BASE) +#define NRF_SPIS21_S ((NRF_SPIS_Type*) NRF_SPIS21_S_BASE) +#define NRF_TWIM21_S ((NRF_TWIM_Type*) NRF_TWIM21_S_BASE) +#define NRF_TWIS21_S ((NRF_TWIS_Type*) NRF_TWIS21_S_BASE) +#define NRF_UARTE21_S ((NRF_UARTE_Type*) NRF_UARTE21_S_BASE) +#define NRF_SPIM22_NS ((NRF_SPIM_Type*) NRF_SPIM22_NS_BASE) +#define NRF_SPIS22_NS ((NRF_SPIS_Type*) NRF_SPIS22_NS_BASE) +#define NRF_TWIM22_NS ((NRF_TWIM_Type*) NRF_TWIM22_NS_BASE) +#define NRF_TWIS22_NS ((NRF_TWIS_Type*) NRF_TWIS22_NS_BASE) +#define NRF_UARTE22_NS ((NRF_UARTE_Type*) NRF_UARTE22_NS_BASE) +#define NRF_SPIM22_S ((NRF_SPIM_Type*) NRF_SPIM22_S_BASE) +#define NRF_SPIS22_S ((NRF_SPIS_Type*) NRF_SPIS22_S_BASE) +#define NRF_TWIM22_S ((NRF_TWIM_Type*) NRF_TWIM22_S_BASE) +#define NRF_TWIS22_S ((NRF_TWIS_Type*) NRF_TWIS22_S_BASE) +#define NRF_UARTE22_S ((NRF_UARTE_Type*) NRF_UARTE22_S_BASE) +#define NRF_EGU20_NS ((NRF_EGU_Type*) NRF_EGU20_NS_BASE) +#define NRF_EGU20_S ((NRF_EGU_Type*) NRF_EGU20_S_BASE) +#define NRF_TIMER20_NS ((NRF_TIMER_Type*) NRF_TIMER20_NS_BASE) +#define NRF_TIMER20_S ((NRF_TIMER_Type*) NRF_TIMER20_S_BASE) +#define NRF_TIMER21_NS ((NRF_TIMER_Type*) NRF_TIMER21_NS_BASE) +#define NRF_TIMER21_S ((NRF_TIMER_Type*) NRF_TIMER21_S_BASE) +#define NRF_TIMER22_NS ((NRF_TIMER_Type*) NRF_TIMER22_NS_BASE) +#define NRF_TIMER22_S ((NRF_TIMER_Type*) NRF_TIMER22_S_BASE) +#define NRF_TIMER23_NS ((NRF_TIMER_Type*) NRF_TIMER23_NS_BASE) +#define NRF_TIMER23_S ((NRF_TIMER_Type*) NRF_TIMER23_S_BASE) +#define NRF_TIMER24_NS ((NRF_TIMER_Type*) NRF_TIMER24_NS_BASE) +#define NRF_TIMER24_S ((NRF_TIMER_Type*) NRF_TIMER24_S_BASE) +#define NRF_MEMCONF_NS ((NRF_MEMCONF_Type*) NRF_MEMCONF_NS_BASE) +#define NRF_MEMCONF_S ((NRF_MEMCONF_Type*) NRF_MEMCONF_S_BASE) +#define NRF_PDM20_NS ((NRF_PDM_Type*) NRF_PDM20_NS_BASE) +#define NRF_PDM20_S ((NRF_PDM_Type*) NRF_PDM20_S_BASE) +#define NRF_PDM21_NS ((NRF_PDM_Type*) NRF_PDM21_NS_BASE) +#define NRF_PDM21_S ((NRF_PDM_Type*) NRF_PDM21_S_BASE) +#define NRF_PWM20_NS ((NRF_PWM_Type*) NRF_PWM20_NS_BASE) +#define NRF_PWM20_S ((NRF_PWM_Type*) NRF_PWM20_S_BASE) +#define NRF_PWM21_NS ((NRF_PWM_Type*) NRF_PWM21_NS_BASE) +#define NRF_PWM21_S ((NRF_PWM_Type*) NRF_PWM21_S_BASE) +#define NRF_PWM22_NS ((NRF_PWM_Type*) NRF_PWM22_NS_BASE) +#define NRF_PWM22_S ((NRF_PWM_Type*) NRF_PWM22_S_BASE) +#define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) +#define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) +#define NRF_NFCT_NS ((NRF_NFCT_Type*) NRF_NFCT_NS_BASE) +#define NRF_NFCT_S ((NRF_NFCT_Type*) NRF_NFCT_S_BASE) +#define NRF_TEMP_NS ((NRF_TEMP_Type*) NRF_TEMP_NS_BASE) +#define NRF_TEMP_S ((NRF_TEMP_Type*) NRF_TEMP_S_BASE) +#define NRF_P1_NS ((NRF_GPIO_Type*) NRF_P1_NS_BASE) +#define NRF_P3_NS ((NRF_GPIO_Type*) NRF_P3_NS_BASE) +#define NRF_P1_S ((NRF_GPIO_Type*) NRF_P1_S_BASE) +#define NRF_P3_S ((NRF_GPIO_Type*) NRF_P3_S_BASE) +#define NRF_GPIOTE20_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE20_NS_BASE) +#define NRF_GPIOTE20_S ((NRF_GPIOTE_Type*) NRF_GPIOTE20_S_BASE) +#define NRF_QDEC20_NS ((NRF_QDEC_Type*) NRF_QDEC20_NS_BASE) +#define NRF_QDEC20_S ((NRF_QDEC_Type*) NRF_QDEC20_S_BASE) +#define NRF_QDEC21_NS ((NRF_QDEC_Type*) NRF_QDEC21_NS_BASE) +#define NRF_QDEC21_S ((NRF_QDEC_Type*) NRF_QDEC21_S_BASE) +#define NRF_GRTC_NS ((NRF_GRTC_Type*) NRF_GRTC_NS_BASE) +#define NRF_GRTC_S ((NRF_GRTC_Type*) NRF_GRTC_S_BASE) +#define NRF_TDM_NS ((NRF_TDM_Type*) NRF_TDM_NS_BASE) +#define NRF_TDM_S ((NRF_TDM_Type*) NRF_TDM_S_BASE) +#define NRF_SPIM23_NS ((NRF_SPIM_Type*) NRF_SPIM23_NS_BASE) +#define NRF_SPIS23_NS ((NRF_SPIS_Type*) NRF_SPIS23_NS_BASE) +#define NRF_TWIM23_NS ((NRF_TWIM_Type*) NRF_TWIM23_NS_BASE) +#define NRF_TWIS23_NS ((NRF_TWIS_Type*) NRF_TWIS23_NS_BASE) +#define NRF_UARTE23_NS ((NRF_UARTE_Type*) NRF_UARTE23_NS_BASE) +#define NRF_SPIM23_S ((NRF_SPIM_Type*) NRF_SPIM23_S_BASE) +#define NRF_SPIS23_S ((NRF_SPIS_Type*) NRF_SPIS23_S_BASE) +#define NRF_TWIM23_S ((NRF_TWIM_Type*) NRF_TWIM23_S_BASE) +#define NRF_TWIS23_S ((NRF_TWIS_Type*) NRF_TWIS23_S_BASE) +#define NRF_UARTE23_S ((NRF_UARTE_Type*) NRF_UARTE23_S_BASE) +#define NRF_SPIM24_NS ((NRF_SPIM_Type*) NRF_SPIM24_NS_BASE) +#define NRF_SPIS24_NS ((NRF_SPIS_Type*) NRF_SPIS24_NS_BASE) +#define NRF_TWIM24_NS ((NRF_TWIM_Type*) NRF_TWIM24_NS_BASE) +#define NRF_TWIS24_NS ((NRF_TWIS_Type*) NRF_TWIS24_NS_BASE) +#define NRF_UARTE24_NS ((NRF_UARTE_Type*) NRF_UARTE24_NS_BASE) +#define NRF_SPIM24_S ((NRF_SPIM_Type*) NRF_SPIM24_S_BASE) +#define NRF_SPIS24_S ((NRF_SPIS_Type*) NRF_SPIS24_S_BASE) +#define NRF_TWIM24_S ((NRF_TWIM_Type*) NRF_TWIM24_S_BASE) +#define NRF_TWIS24_S ((NRF_TWIS_Type*) NRF_TWIS24_S_BASE) +#define NRF_UARTE24_S ((NRF_UARTE_Type*) NRF_UARTE24_S_BASE) +#define NRF_TAMPC_S ((NRF_TAMPC_Type*) NRF_TAMPC_S_BASE) +#define NRF_SPU30_S ((NRF_SPU_Type*) NRF_SPU30_S_BASE) +#define NRF_DPPIC30_NS ((NRF_DPPIC_Type*) NRF_DPPIC30_NS_BASE) +#define NRF_DPPIC30_S ((NRF_DPPIC_Type*) NRF_DPPIC30_S_BASE) +#define NRF_PPIB30_NS ((NRF_PPIB_Type*) NRF_PPIB30_NS_BASE) +#define NRF_PPIB30_S ((NRF_PPIB_Type*) NRF_PPIB30_S_BASE) +#define NRF_SPIM30_NS ((NRF_SPIM_Type*) NRF_SPIM30_NS_BASE) +#define NRF_SPIS30_NS ((NRF_SPIS_Type*) NRF_SPIS30_NS_BASE) +#define NRF_TWIM30_NS ((NRF_TWIM_Type*) NRF_TWIM30_NS_BASE) +#define NRF_TWIS30_NS ((NRF_TWIS_Type*) NRF_TWIS30_NS_BASE) +#define NRF_UARTE30_NS ((NRF_UARTE_Type*) NRF_UARTE30_NS_BASE) +#define NRF_SPIM30_S ((NRF_SPIM_Type*) NRF_SPIM30_S_BASE) +#define NRF_SPIS30_S ((NRF_SPIS_Type*) NRF_SPIS30_S_BASE) +#define NRF_TWIM30_S ((NRF_TWIM_Type*) NRF_TWIM30_S_BASE) +#define NRF_TWIS30_S ((NRF_TWIS_Type*) NRF_TWIS30_S_BASE) +#define NRF_UARTE30_S ((NRF_UARTE_Type*) NRF_UARTE30_S_BASE) +#define NRF_COMP_NS ((NRF_COMP_Type*) NRF_COMP_NS_BASE) +#define NRF_LPCOMP_NS ((NRF_LPCOMP_Type*) NRF_LPCOMP_NS_BASE) +#define NRF_COMP_S ((NRF_COMP_Type*) NRF_COMP_S_BASE) +#define NRF_LPCOMP_S ((NRF_LPCOMP_Type*) NRF_LPCOMP_S_BASE) +#define NRF_WDT30_S ((NRF_WDT_Type*) NRF_WDT30_S_BASE) +#define NRF_WDT31_NS ((NRF_WDT_Type*) NRF_WDT31_NS_BASE) +#define NRF_WDT31_S ((NRF_WDT_Type*) NRF_WDT31_S_BASE) +#define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) +#define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) +#define NRF_GPIOTE30_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE30_NS_BASE) +#define NRF_GPIOTE30_S ((NRF_GPIOTE_Type*) NRF_GPIOTE30_S_BASE) +#define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) +#define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) +#define NRF_RESET_NS ((NRF_RESET_Type*) NRF_RESET_NS_BASE) +#define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE) +#define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE) +#define NRF_RESET_S ((NRF_RESET_Type*) NRF_RESET_S_BASE) +#define NRF_OSCILLATORS_NS ((NRF_OSCILLATORS_Type*) NRF_OSCILLATORS_NS_BASE) +#define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE) +#define NRF_OSCILLATORS_S ((NRF_OSCILLATORS_Type*) NRF_OSCILLATORS_S_BASE) +#define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE) +#define NRF_VREGUSB_NS ((NRF_VREGUSB_Type*) NRF_VREGUSB_NS_BASE) +#define NRF_VREGUSB_S ((NRF_VREGUSB_Type*) NRF_VREGUSB_S_BASE) + +/* =========================================================================================================================== */ +/* ================ TrustZone Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ + #define NRF_FICR NRF_FICR_NS + #define NRF_USBHSCORE NRF_USBHSCORE_NS + #define NRF_DPPIC00 NRF_DPPIC00_NS + #define NRF_PPIB00 NRF_PPIB00_NS + #define NRF_PPIB01 NRF_PPIB01_NS + #define NRF_AAR00 NRF_AAR00_NS + #define NRF_CCM00 NRF_CCM00_NS + #define NRF_ECB00 NRF_ECB00_NS + #define NRF_VPR00 NRF_VPR00_NS + #define NRF_SPIM00 NRF_SPIM00_NS + #define NRF_SPIS00 NRF_SPIS00_NS + #define NRF_UARTE00 NRF_UARTE00_NS + #define NRF_GPIOHSPADCTRL NRF_GPIOHSPADCTRL_NS + #define NRF_P2 NRF_P2_NS + #define NRF_CTRLAP NRF_CTRLAP_NS + #define NRF_TAD NRF_TAD_NS + #define NRF_TIMER00 NRF_TIMER00_NS + #define NRF_EGU00 NRF_EGU00_NS + #define NRF_USBHS NRF_USBHS_NS + #define NRF_DPPIC10 NRF_DPPIC10_NS + #define NRF_PPIB10 NRF_PPIB10_NS + #define NRF_PPIB11 NRF_PPIB11_NS + #define NRF_TIMER10 NRF_TIMER10_NS + #define NRF_EGU10 NRF_EGU10_NS + #define NRF_RADIO NRF_RADIO_NS + #define NRF_DPPIC20 NRF_DPPIC20_NS + #define NRF_PPIB20 NRF_PPIB20_NS + #define NRF_PPIB21 NRF_PPIB21_NS + #define NRF_PPIB22 NRF_PPIB22_NS + #define NRF_SPIM20 NRF_SPIM20_NS + #define NRF_SPIS20 NRF_SPIS20_NS + #define NRF_TWIM20 NRF_TWIM20_NS + #define NRF_TWIS20 NRF_TWIS20_NS + #define NRF_UARTE20 NRF_UARTE20_NS + #define NRF_SPIM21 NRF_SPIM21_NS + #define NRF_SPIS21 NRF_SPIS21_NS + #define NRF_TWIM21 NRF_TWIM21_NS + #define NRF_TWIS21 NRF_TWIS21_NS + #define NRF_UARTE21 NRF_UARTE21_NS + #define NRF_SPIM22 NRF_SPIM22_NS + #define NRF_SPIS22 NRF_SPIS22_NS + #define NRF_TWIM22 NRF_TWIM22_NS + #define NRF_TWIS22 NRF_TWIS22_NS + #define NRF_UARTE22 NRF_UARTE22_NS + #define NRF_EGU20 NRF_EGU20_NS + #define NRF_TIMER20 NRF_TIMER20_NS + #define NRF_TIMER21 NRF_TIMER21_NS + #define NRF_TIMER22 NRF_TIMER22_NS + #define NRF_TIMER23 NRF_TIMER23_NS + #define NRF_TIMER24 NRF_TIMER24_NS + #define NRF_MEMCONF NRF_MEMCONF_NS + #define NRF_PDM20 NRF_PDM20_NS + #define NRF_PDM21 NRF_PDM21_NS + #define NRF_PWM20 NRF_PWM20_NS + #define NRF_PWM21 NRF_PWM21_NS + #define NRF_PWM22 NRF_PWM22_NS + #define NRF_SAADC NRF_SAADC_NS + #define NRF_NFCT NRF_NFCT_NS + #define NRF_TEMP NRF_TEMP_NS + #define NRF_P1 NRF_P1_NS + #define NRF_P3 NRF_P3_NS + #define NRF_GPIOTE20 NRF_GPIOTE20_NS + #define NRF_QDEC20 NRF_QDEC20_NS + #define NRF_QDEC21 NRF_QDEC21_NS + #define NRF_GRTC NRF_GRTC_NS + #define NRF_TDM NRF_TDM_NS + #define NRF_SPIM23 NRF_SPIM23_NS + #define NRF_SPIS23 NRF_SPIS23_NS + #define NRF_TWIM23 NRF_TWIM23_NS + #define NRF_TWIS23 NRF_TWIS23_NS + #define NRF_UARTE23 NRF_UARTE23_NS + #define NRF_SPIM24 NRF_SPIM24_NS + #define NRF_SPIS24 NRF_SPIS24_NS + #define NRF_TWIM24 NRF_TWIM24_NS + #define NRF_TWIS24 NRF_TWIS24_NS + #define NRF_UARTE24 NRF_UARTE24_NS + #define NRF_DPPIC30 NRF_DPPIC30_NS + #define NRF_PPIB30 NRF_PPIB30_NS + #define NRF_SPIM30 NRF_SPIM30_NS + #define NRF_SPIS30 NRF_SPIS30_NS + #define NRF_TWIM30 NRF_TWIM30_NS + #define NRF_TWIS30 NRF_TWIS30_NS + #define NRF_UARTE30 NRF_UARTE30_NS + #define NRF_COMP NRF_COMP_NS + #define NRF_LPCOMP NRF_LPCOMP_NS + #define NRF_WDT31 NRF_WDT31_NS + #define NRF_P0 NRF_P0_NS + #define NRF_GPIOTE30 NRF_GPIOTE30_NS + #define NRF_CLOCK NRF_CLOCK_NS + #define NRF_POWER NRF_POWER_NS + #define NRF_RESET NRF_RESET_NS + #define NRF_OSCILLATORS NRF_OSCILLATORS_NS + #define NRF_REGULATORS NRF_REGULATORS_NS + #define NRF_VREGUSB NRF_VREGUSB_NS +#else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ + #define NRF_FICR NRF_FICR_NS + #define NRF_UICR NRF_UICR_S + #define NRF_SICR NRF_SICR_S + #define NRF_CRACENCORE NRF_CRACENCORE_S + #define NRF_USBHSCORE NRF_USBHSCORE_S + #define NRF_SPU00 NRF_SPU00_S + #define NRF_MPC00 NRF_MPC00_S + #define NRF_DPPIC00 NRF_DPPIC00_S + #define NRF_PPIB00 NRF_PPIB00_S + #define NRF_PPIB01 NRF_PPIB01_S + #define NRF_KMU NRF_KMU_S + #define NRF_AAR00 NRF_AAR00_S + #define NRF_CCM00 NRF_CCM00_S + #define NRF_ECB00 NRF_ECB00_S + #define NRF_VPR00 NRF_VPR00_S + #define NRF_SPIM00 NRF_SPIM00_S + #define NRF_SPIS00 NRF_SPIS00_S + #define NRF_UARTE00 NRF_UARTE00_S + #define NRF_GLITCHDET NRF_GLITCHDET_S + #define NRF_RRAMC NRF_RRAMC_S + #define NRF_GPIOHSPADCTRL NRF_GPIOHSPADCTRL_S + #define NRF_P2 NRF_P2_S + #define NRF_CTRLAP NRF_CTRLAP_S + #define NRF_TAD NRF_TAD_S + #define NRF_TIMER00 NRF_TIMER00_S + #define NRF_EGU00 NRF_EGU00_S + #define NRF_CRACEN NRF_CRACEN_S + #define NRF_USBHS NRF_USBHS_S + #define NRF_SPU10 NRF_SPU10_S + #define NRF_DPPIC10 NRF_DPPIC10_S + #define NRF_PPIB10 NRF_PPIB10_S + #define NRF_PPIB11 NRF_PPIB11_S + #define NRF_TIMER10 NRF_TIMER10_S + #define NRF_EGU10 NRF_EGU10_S + #define NRF_RADIO NRF_RADIO_S + #define NRF_SPU20 NRF_SPU20_S + #define NRF_DPPIC20 NRF_DPPIC20_S + #define NRF_PPIB20 NRF_PPIB20_S + #define NRF_PPIB21 NRF_PPIB21_S + #define NRF_PPIB22 NRF_PPIB22_S + #define NRF_SPIM20 NRF_SPIM20_S + #define NRF_SPIS20 NRF_SPIS20_S + #define NRF_TWIM20 NRF_TWIM20_S + #define NRF_TWIS20 NRF_TWIS20_S + #define NRF_UARTE20 NRF_UARTE20_S + #define NRF_SPIM21 NRF_SPIM21_S + #define NRF_SPIS21 NRF_SPIS21_S + #define NRF_TWIM21 NRF_TWIM21_S + #define NRF_TWIS21 NRF_TWIS21_S + #define NRF_UARTE21 NRF_UARTE21_S + #define NRF_SPIM22 NRF_SPIM22_S + #define NRF_SPIS22 NRF_SPIS22_S + #define NRF_TWIM22 NRF_TWIM22_S + #define NRF_TWIS22 NRF_TWIS22_S + #define NRF_UARTE22 NRF_UARTE22_S + #define NRF_EGU20 NRF_EGU20_S + #define NRF_TIMER20 NRF_TIMER20_S + #define NRF_TIMER21 NRF_TIMER21_S + #define NRF_TIMER22 NRF_TIMER22_S + #define NRF_TIMER23 NRF_TIMER23_S + #define NRF_TIMER24 NRF_TIMER24_S + #define NRF_MEMCONF NRF_MEMCONF_S + #define NRF_PDM20 NRF_PDM20_S + #define NRF_PDM21 NRF_PDM21_S + #define NRF_PWM20 NRF_PWM20_S + #define NRF_PWM21 NRF_PWM21_S + #define NRF_PWM22 NRF_PWM22_S + #define NRF_SAADC NRF_SAADC_S + #define NRF_NFCT NRF_NFCT_S + #define NRF_TEMP NRF_TEMP_S + #define NRF_P1 NRF_P1_S + #define NRF_P3 NRF_P3_S + #define NRF_GPIOTE20 NRF_GPIOTE20_S + #define NRF_QDEC20 NRF_QDEC20_S + #define NRF_QDEC21 NRF_QDEC21_S + #define NRF_GRTC NRF_GRTC_S + #define NRF_TDM NRF_TDM_S + #define NRF_SPIM23 NRF_SPIM23_S + #define NRF_SPIS23 NRF_SPIS23_S + #define NRF_TWIM23 NRF_TWIM23_S + #define NRF_TWIS23 NRF_TWIS23_S + #define NRF_UARTE23 NRF_UARTE23_S + #define NRF_SPIM24 NRF_SPIM24_S + #define NRF_SPIS24 NRF_SPIS24_S + #define NRF_TWIM24 NRF_TWIM24_S + #define NRF_TWIS24 NRF_TWIS24_S + #define NRF_UARTE24 NRF_UARTE24_S + #define NRF_TAMPC NRF_TAMPC_S + #define NRF_SPU30 NRF_SPU30_S + #define NRF_DPPIC30 NRF_DPPIC30_S + #define NRF_PPIB30 NRF_PPIB30_S + #define NRF_SPIM30 NRF_SPIM30_S + #define NRF_SPIS30 NRF_SPIS30_S + #define NRF_TWIM30 NRF_TWIM30_S + #define NRF_TWIS30 NRF_TWIS30_S + #define NRF_UARTE30 NRF_UARTE30_S + #define NRF_COMP NRF_COMP_S + #define NRF_LPCOMP NRF_LPCOMP_S + #define NRF_WDT30 NRF_WDT30_S + #define NRF_WDT31 NRF_WDT31_S + #define NRF_P0 NRF_P0_S + #define NRF_GPIOTE30 NRF_GPIOTE30_S + #define NRF_CLOCK NRF_CLOCK_S + #define NRF_POWER NRF_POWER_S + #define NRF_RESET NRF_RESET_S + #define NRF_OSCILLATORS NRF_OSCILLATORS_S + #define NRF_REGULATORS NRF_REGULATORS_S + #define NRF_VREGUSB NRF_VREGUSB_S +#endif /*!< NRF_TRUSTZONE_NONSECURE */ + +/* ========================================== End of section using anonymous unions ========================================== */ + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif +#endif /* NRF54LM20A_GLOBAL_H */ + diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_interim.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_interim.h new file mode 100644 index 0000000..e460d85 --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_interim.h @@ -0,0 +1,149 @@ +/* + +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF54LM20A_INTERIM_H__ +#define NRF54LM20A_INTERIM_H__ + +#if defined(NRF54LM20A_XXAA) + + + #define NRF_DOMAIN_COUNT NRF_DOMAIN_NONE + 1 + + #define ADDRESS_BUS_Pos (18UL) + #define ADDRESS_BUS_Msk (0x3FUL << ADDRESS_BUS_Pos) + + + #define PPIB00_CH_NUM 8 + #define PPIB10_CH_NUM 8 + #define PPIB11_CH_NUM 16 + #define PPIB21_CH_NUM 16 + #define PPIB22_CH_NUM 4 + #define PPIB30_CH_NUM 4 + #define PPIB20_CH_NUM 8 + #define PPIB01_CH_NUM 8 + + typedef enum + { + NRF_APB_INDEX_MCU = 1, + NRF_APB_INDEX_RADIO = 2, + NRF_APB_INDEX_PERI = 3, + NRF_APB_INDEX_LP = 4 + } nrf_apb_index_t; + + #if defined(NRF_FLPR) + #define GRTC_IRQ_GROUP 0 + #define GPIOTE_IRQ_GROUP 0 + #elif defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + #define GPIOTE_IRQ_GROUP 0 + #define GRTC_IRQ_GROUP 1 + #else + #define GPIOTE_IRQ_GROUP 1 + #define GRTC_IRQ_GROUP 2 + #endif + #endif + + #define EASYVDMA_PRESENT + + #define SAADC_CH_NUM SAADC_CH_MaxCount + #define SAADC_EASYDMA_MAXCNT_SIZE 15 + + #define LPCOMP_REFSEL_RESOLUTION 16 + + #define MPC_MASTER_PORTS_MaxCount (15UL) /*!< Max number of master ports. */ + + #define GPIOTE20_CH_NUM GPIOTE20_GPIOTE_NCHANNELS_SIZE + #define GPIOTE30_CH_NUM GPIOTE30_GPIOTE_NCHANNELS_SIZE + + #define GPIOTE_CH_NUM 8 + #define GPIOTE20_AVAILABLE_GPIO_PORTS 0xAUL + #define GPIOTE30_AVAILABLE_GPIO_PORTS 0x1UL + #define GPIOTE_FEATURE_SET_PRESENT + #define GPIOTE_FEATURE_CLR_PRESENT + #define GPIOTE_PORT_NUM GPIOTE_EVENTS_PORT_MaxCount + + #define DPPI_PRESENT DPPIC_PRESENT + + #define DPPIC00_CH_NUM DPPIC00_CH_NUM_SIZE + #define DPPIC10_CH_NUM DPPIC10_CH_NUM_SIZE + #define DPPIC20_CH_NUM DPPIC20_CH_NUM_SIZE + #define DPPIC30_CH_NUM DPPIC30_CH_NUM_SIZE + + #define DPPIC00_GROUP_NUM DPPIC00_GROUP_NUM_SIZE + #define DPPIC10_GROUP_NUM DPPIC10_GROUP_NUM_SIZE + #define DPPIC20_GROUP_NUM DPPIC20_GROUP_NUM_SIZE + #define DPPIC30_GROUP_NUM DPPIC30_GROUP_NUM_SIZE + + #define PPIB_CHANNEL_MAX_COUNT 24UL + + #define P0_PIN_NUM P0_PIN_NUM_SIZE + #define P1_PIN_NUM P1_PIN_NUM_SIZE + #define P2_PIN_NUM P2_PIN_NUM_SIZE + #define P3_PIN_NUM P3_PIN_NUM_SIZE + + + #define TIMER00_CC_NUM TIMER00_CC_NUM_SIZE + #define TIMER10_CC_NUM TIMER10_CC_NUM_SIZE + #define TIMER20_CC_NUM TIMER20_CC_NUM_SIZE + #define TIMER21_CC_NUM TIMER21_CC_NUM_SIZE + #define TIMER22_CC_NUM TIMER22_CC_NUM_SIZE + #define TIMER23_CC_NUM TIMER23_CC_NUM_SIZE + #define TIMER24_CC_NUM TIMER24_CC_NUM_SIZE + + #define TIMER00_MAX_SIZE TIMER00_MAX_SIZE_SIZE + #define TIMER10_MAX_SIZE TIMER10_MAX_SIZE_SIZE + #define TIMER20_MAX_SIZE TIMER20_MAX_SIZE_SIZE + #define TIMER21_MAX_SIZE TIMER21_MAX_SIZE_SIZE + #define TIMER22_MAX_SIZE TIMER22_MAX_SIZE_SIZE + #define TIMER23_MAX_SIZE TIMER23_MAX_SIZE_SIZE + #define TIMER24_MAX_SIZE TIMER24_MAX_SIZE_SIZE + + #define EGU00_CH_NUM EGU00_CH_NUM_SIZE + #define EGU10_CH_NUM EGU10_CH_NUM_SIZE + #define EGU20_CH_NUM EGU20_CH_NUM_SIZE + + + #define RTC10_CC_NUM RTC10_CC_NUM_SIZE + #define RTC30_CC_NUM RTC30_CC_NUM_SIZE + + + #define VPR_VEVIF_EVENT_MaxCount 32 + #define VPR_CLIC_PRIO_COUNT 4 + #define ADDRESS_SLAVE_Pos (12UL) + #define ADDRESS_SLAVE_Msk (0x3FUL << ADDRESS_SLAVE_Pos) + + +#endif + +#endif \ No newline at end of file diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_name_change.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_name_change.h new file mode 100644 index 0000000..2fda159 --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_name_change.h @@ -0,0 +1,57 @@ +/* + +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF54LM20A_NAME_CHANGE_H +#define NRF54LM20A_NAME_CHANGE_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ========================================= Enumerator NoDelay AltName Definitions ========================================== */ +#define PDM_FILTER_SAMPLEDELAY_DELAY_no_delay PDM_FILTER_SAMPLEDELAY_DELAY_NoDelay + +/* ========================================= Enumerator Delay1Ck AltName Definitions ========================================= */ +#define PDM_FILTER_SAMPLEDELAY_DELAY_x1 PDM_FILTER_SAMPLEDELAY_DELAY_Delay1Ck + +/* ========================================= Enumerator INACTIVE AltName Definitions ========================================= */ +#define USBHSCORE_GINTSTS_SOF_INTACTIVE USBHSCORE_GINTSTS_SOF_INACTIVE + + +#ifdef __cplusplus +} +#endif +#endif /* NRF54LM20A_NAME_CHANGE_H */ + diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_peripherals.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_peripherals.h new file mode 100644 index 0000000..1a26d72 --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_peripherals.h @@ -0,0 +1,54 @@ +/* + +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF54LM20A_PERIPHERALS_H +#define NRF54LM20A_PERIPHERALS_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(NRF_APPLICATION) + #include "nrf54lm20a_application_peripherals.h" +#elif defined(NRF_FLPR) + #include "nrf54lm20a_flpr_peripherals.h" +#else + #error "No processor selected" +#endif + +#ifdef __cplusplus +} +#endif +#endif /* NRF54LM20A_PERIPHERALS_H */ + diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_types.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_types.h new file mode 100644 index 0000000..f928970 --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_types.h @@ -0,0 +1,63797 @@ +/* + +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF54LM20A_TYPES_H +#define NRF54LM20A_TYPES_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include +#include "compiler_abstraction.h" + + +/* ============================================ Include required type specifiers ============================================= */ + +#ifndef __I + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif +#endif +#ifndef __O + #define __O volatile /*!< Defines 'write only' permissions */ +#endif +#ifndef __IO + #define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + +/* The following defines should be used for structure members */ +#ifndef __IM + #define __IM volatile const /*!< Defines 'read only' structure member permissions */ +#endif +#ifndef __OM + #define __OM volatile /*!< Defines 'write only' structure member permissions */ +#endif +#ifndef __IOM + #define __IOM volatile /*!< Defines 'read / write' structure member permissions */ +#endif + +/* ======================================================= Domain IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_DOMAIN_NONE = 0, /*!< No domain */ +} NRF_DOMAINID_Type; + +/* ====================================================== Processor IDs ====================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_PROCESSOR_CM33 = 1, /*!< (unspecified) */ + NRF_PROCESSOR_VPR = 2, /*!< (unspecified) */ +} NRF_PROCESSORID_Type; + +/* ======================================================== Owner IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_OWNER_NONE = 0, /*!< Used to denote that ownership is not enforced */ + NRF_OWNER_APPLICATION = 1, /*!< Application Core */ + NRF_OWNER_KMU = 2, /*!< KMU Accesses */ +} NRF_OWNERID_Type; + + +/* ========================================= Start of section using anonymous unions ========================================= */ + +#include "compiler_abstraction.h" + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Unsupported compiler type +#endif + +/* =========================================================================================================================== */ +/* ================ Peripherals Section ================ */ +/* =========================================================================================================================== */ + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ====================================================== Struct AAR_IN ====================================================== */ +/** + * @brief IN [AAR_IN] IN EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Input pointer */ +} NRF_AAR_IN_Type; /*!< Size = 4 (0x004) */ + +/* AAR_IN_PTR: Input pointer */ + #define AAR_IN_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Points to a job list containing AAR data structure */ + #define AAR_IN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define AAR_IN_PTR_PTR_Msk (0xFFFFFFFFUL << AAR_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + + +/* ===================================================== Struct AAR_OUT ====================================================== */ +/** + * @brief OUT [AAR_OUT] OUT EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Output pointer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Number of bytes transferred in the last transaction */ +} NRF_AAR_OUT_Type; /*!< Size = 8 (0x008) */ + +/* AAR_OUT_PTR: Output pointer */ + #define AAR_OUT_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Output pointer */ + #define AAR_OUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define AAR_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << AAR_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* AAR_OUT_AMOUNT: Number of bytes transferred in the last transaction */ + #define AAR_OUT_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..7 : Number of bytes written to memory after triggering the START task. */ + #define AAR_OUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define AAR_OUT_AMOUNT_AMOUNT_Msk (0xFFUL << AAR_OUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define AAR_OUT_AMOUNT_AMOUNT_Min (0x01UL) /*!< Min value of AMOUNT field. */ + #define AAR_OUT_AMOUNT_AMOUNT_Max (0xFFUL) /*!< Max size of AMOUNT field. */ + + +/* ======================================================= Struct AAR ======================================================== */ +/** + * @brief Accelerated Address Resolver + */ + typedef struct { /*!< AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified in + the IRK data structure*/ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop resolving addresses */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete or ended due to + an error*/ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000010C) Operation aborted because of a STOP task or due to an + error*/ + __IM uint32_t RESERVED2[28]; + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000180) Publish configuration for event END */ + __IOM uint32_t PUBLISH_RESOLVED; /*!< (@ 0x00000184) Publish configuration for event RESOLVED */ + __IOM uint32_t PUBLISH_NOTRESOLVED; /*!< (@ 0x00000188) Publish configuration for event NOTRESOLVED */ + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x0000018C) Publish configuration for event ERROR */ + __IM uint32_t RESERVED3[93]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[62]; + __IM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) Error status */ + __IM uint32_t RESERVED5[62]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IM uint32_t RESERVED6; + __IOM uint32_t MAXRESOLVED; /*!< (@ 0x00000508) Maximum number of IRKs to resolve */ + __IM uint32_t RESERVED7[9]; + __IOM NRF_AAR_IN_Type IN; /*!< (@ 0x00000530) IN EasyDMA channel */ + __IM uint32_t RESERVED8; + __IOM NRF_AAR_OUT_Type OUT; /*!< (@ 0x00000538) OUT EasyDMA channel */ + } NRF_AAR_Type; /*!< Size = 1344 (0x540) */ + +/* AAR_TASKS_START: Start resolving addresses based on IRKs specified in the IRK data structure */ + #define AAR_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ + #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define AAR_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define AAR_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define AAR_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* AAR_TASKS_STOP: Stop resolving addresses */ + #define AAR_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop resolving addresses */ + #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define AAR_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define AAR_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define AAR_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* AAR_SUBSCRIBE_START: Subscribe configuration for task START */ + #define AAR_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define AAR_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define AAR_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define AAR_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define AAR_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define AAR_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define AAR_SUBSCRIBE_START_EN_Msk (0x1UL << AAR_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define AAR_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define AAR_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define AAR_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define AAR_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* AAR_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define AAR_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define AAR_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define AAR_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define AAR_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define AAR_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define AAR_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define AAR_SUBSCRIBE_STOP_EN_Msk (0x1UL << AAR_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define AAR_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define AAR_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define AAR_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define AAR_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* AAR_EVENTS_END: Address resolution procedure complete or ended due to an error */ + #define AAR_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : Address resolution procedure complete or ended due to an error */ + #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define AAR_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define AAR_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define AAR_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* AAR_EVENTS_RESOLVED: Address resolved */ + #define AAR_EVENTS_RESOLVED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RESOLVED register. */ + +/* EVENTS_RESOLVED @Bit 0 : Address resolved */ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of + EVENTS_RESOLVED field.*/ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Min (0x0UL) /*!< Min enumerator value of EVENTS_RESOLVED field. */ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Max (0x1UL) /*!< Max enumerator value of EVENTS_RESOLVED field. */ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0x0UL) /*!< Event not generated */ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (0x1UL) /*!< Event generated */ + + +/* AAR_EVENTS_NOTRESOLVED: Address not resolved */ + #define AAR_EVENTS_NOTRESOLVED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_NOTRESOLVED register. */ + +/* EVENTS_NOTRESOLVED @Bit 0 : Address not resolved */ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask + of EVENTS_NOTRESOLVED field.*/ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Min (0x0UL) /*!< Min enumerator value of EVENTS_NOTRESOLVED field. */ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Max (0x1UL) /*!< Max enumerator value of EVENTS_NOTRESOLVED field. */ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0x0UL) /*!< Event not generated */ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (0x1UL) /*!< Event generated */ + + +/* AAR_EVENTS_ERROR: Operation aborted because of a STOP task or due to an error */ + #define AAR_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : Operation aborted because of a STOP task or due to an error */ + #define AAR_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define AAR_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << AAR_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + #define AAR_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define AAR_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define AAR_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define AAR_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* AAR_PUBLISH_END: Publish configuration for event END */ + #define AAR_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define AAR_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define AAR_PUBLISH_END_CHIDX_Msk (0xFFUL << AAR_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define AAR_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define AAR_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define AAR_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define AAR_PUBLISH_END_EN_Msk (0x1UL << AAR_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define AAR_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define AAR_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define AAR_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define AAR_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* AAR_PUBLISH_RESOLVED: Publish configuration for event RESOLVED */ + #define AAR_PUBLISH_RESOLVED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RESOLVED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RESOLVED will publish to */ + #define AAR_PUBLISH_RESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define AAR_PUBLISH_RESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_RESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define AAR_PUBLISH_RESOLVED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define AAR_PUBLISH_RESOLVED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define AAR_PUBLISH_RESOLVED_EN_Pos (31UL) /*!< Position of EN field. */ + #define AAR_PUBLISH_RESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_RESOLVED_EN_Pos) /*!< Bit mask of EN field. */ + #define AAR_PUBLISH_RESOLVED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define AAR_PUBLISH_RESOLVED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define AAR_PUBLISH_RESOLVED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define AAR_PUBLISH_RESOLVED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* AAR_PUBLISH_NOTRESOLVED: Publish configuration for event NOTRESOLVED */ + #define AAR_PUBLISH_NOTRESOLVED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_NOTRESOLVED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event NOTRESOLVED will publish to */ + #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Pos (31UL) /*!< Position of EN field. */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_NOTRESOLVED_EN_Pos) /*!< Bit mask of EN field. */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* AAR_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define AAR_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define AAR_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define AAR_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << AAR_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define AAR_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define AAR_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define AAR_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define AAR_PUBLISH_ERROR_EN_Msk (0x1UL << AAR_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define AAR_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define AAR_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define AAR_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define AAR_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* AAR_INTENSET: Enable interrupt */ + #define AAR_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* END @Bit 0 : Write '1' to enable interrupt for event END */ + #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ + #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define AAR_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define AAR_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define AAR_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define AAR_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RESOLVED @Bit 1 : Write '1' to enable interrupt for event RESOLVED */ + #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ + #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ + #define AAR_INTENSET_RESOLVED_Min (0x0UL) /*!< Min enumerator value of RESOLVED field. */ + #define AAR_INTENSET_RESOLVED_Max (0x1UL) /*!< Max enumerator value of RESOLVED field. */ + #define AAR_INTENSET_RESOLVED_Set (0x1UL) /*!< Enable */ + #define AAR_INTENSET_RESOLVED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENSET_RESOLVED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* NOTRESOLVED @Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ + #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ + #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ + #define AAR_INTENSET_NOTRESOLVED_Min (0x0UL) /*!< Min enumerator value of NOTRESOLVED field. */ + #define AAR_INTENSET_NOTRESOLVED_Max (0x1UL) /*!< Max enumerator value of NOTRESOLVED field. */ + #define AAR_INTENSET_NOTRESOLVED_Set (0x1UL) /*!< Enable */ + #define AAR_INTENSET_NOTRESOLVED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENSET_NOTRESOLVED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 3 : Write '1' to enable interrupt for event ERROR */ + #define AAR_INTENSET_ERROR_Pos (3UL) /*!< Position of ERROR field. */ + #define AAR_INTENSET_ERROR_Msk (0x1UL << AAR_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define AAR_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define AAR_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define AAR_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define AAR_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* AAR_INTENCLR: Disable interrupt */ + #define AAR_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* END @Bit 0 : Write '1' to disable interrupt for event END */ + #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ + #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define AAR_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define AAR_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define AAR_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define AAR_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RESOLVED @Bit 1 : Write '1' to disable interrupt for event RESOLVED */ + #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ + #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ + #define AAR_INTENCLR_RESOLVED_Min (0x0UL) /*!< Min enumerator value of RESOLVED field. */ + #define AAR_INTENCLR_RESOLVED_Max (0x1UL) /*!< Max enumerator value of RESOLVED field. */ + #define AAR_INTENCLR_RESOLVED_Clear (0x1UL) /*!< Disable */ + #define AAR_INTENCLR_RESOLVED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENCLR_RESOLVED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* NOTRESOLVED @Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ + #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ + #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ + #define AAR_INTENCLR_NOTRESOLVED_Min (0x0UL) /*!< Min enumerator value of NOTRESOLVED field. */ + #define AAR_INTENCLR_NOTRESOLVED_Max (0x1UL) /*!< Max enumerator value of NOTRESOLVED field. */ + #define AAR_INTENCLR_NOTRESOLVED_Clear (0x1UL) /*!< Disable */ + #define AAR_INTENCLR_NOTRESOLVED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENCLR_NOTRESOLVED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 3 : Write '1' to disable interrupt for event ERROR */ + #define AAR_INTENCLR_ERROR_Pos (3UL) /*!< Position of ERROR field. */ + #define AAR_INTENCLR_ERROR_Msk (0x1UL << AAR_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define AAR_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define AAR_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define AAR_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define AAR_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* AAR_ERRORSTATUS: Error status */ + #define AAR_ERRORSTATUS_ResetValue (0x00000000UL) /*!< Reset value of ERRORSTATUS register. */ + +/* ERRORSTATUS @Bits 0..2 : Error status when the ERROR event is generated */ + #define AAR_ERRORSTATUS_ERRORSTATUS_Pos (0UL) /*!< Position of ERRORSTATUS field. */ + #define AAR_ERRORSTATUS_ERRORSTATUS_Msk (0x7UL << AAR_ERRORSTATUS_ERRORSTATUS_Pos) /*!< Bit mask of ERRORSTATUS field. */ + #define AAR_ERRORSTATUS_ERRORSTATUS_Min (0x0UL) /*!< Min enumerator value of ERRORSTATUS field. */ + #define AAR_ERRORSTATUS_ERRORSTATUS_Max (0x4UL) /*!< Max enumerator value of ERRORSTATUS field. */ + #define AAR_ERRORSTATUS_ERRORSTATUS_NoError (0x0UL) /*!< No errors have occurred */ + #define AAR_ERRORSTATUS_ERRORSTATUS_PrematureInptrEnd (0x1UL) /*!< End of INPTR job list before data structure was read. */ + #define AAR_ERRORSTATUS_ERRORSTATUS_PrematureOutptrEnd (0x2UL) /*!< End of OUTPTR job list before data structure was read. */ + #define AAR_ERRORSTATUS_ERRORSTATUS_DmaError (0x4UL) /*!< Bus error during DMA access. */ + + +/* AAR_ENABLE: Enable AAR */ + #define AAR_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..1 : Enable or disable AAR */ + #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define AAR_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define AAR_ENABLE_ENABLE_Max (0x3UL) /*!< Max enumerator value of ENABLE field. */ + #define AAR_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define AAR_ENABLE_ENABLE_Enabled (0x3UL) /*!< Enable */ + + +/* AAR_MAXRESOLVED: Maximum number of IRKs to resolve */ + #define AAR_MAXRESOLVED_ResetValue (0x00000001UL) /*!< Reset value of MAXRESOLVED register. */ + +/* MAXRESOLVED @Bits 0..11 : The maximum number of IRKs to resolve */ + #define AAR_MAXRESOLVED_MAXRESOLVED_Pos (0UL) /*!< Position of MAXRESOLVED field. */ + #define AAR_MAXRESOLVED_MAXRESOLVED_Msk (0xFFFUL << AAR_MAXRESOLVED_MAXRESOLVED_Pos) /*!< Bit mask of MAXRESOLVED field. */ + #define AAR_MAXRESOLVED_MAXRESOLVED_Min (0x001UL) /*!< Min value of MAXRESOLVED field. */ + #define AAR_MAXRESOLVED_MAXRESOLVED_Max (0xFFFUL) /*!< Max size of MAXRESOLVED field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CACHE ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================= Struct CACHE_PROFILING ================================================== */ +/** + * @brief PROFILING [CACHE_PROFILING] (unspecified) + */ +typedef struct { + __IOM uint32_t ENABLE; /*!< (@ 0x00000000) Enable the profiling counters. */ + __OM uint32_t CLEAR; /*!< (@ 0x00000004) Clear the profiling counters. */ + __IM uint32_t HIT; /*!< (@ 0x00000008) The cache hit counter for cache region. */ + __IM uint32_t MISS; /*!< (@ 0x0000000C) The cache miss counter for cache region. */ + __IM uint32_t LMISS; /*!< (@ 0x00000010) The cache line miss counter for cache region. */ + __IM uint32_t READS; /*!< (@ 0x00000014) Number of reads for cache region. */ + __IM uint32_t WRITES; /*!< (@ 0x00000018) Number of writes for cache region. */ +} NRF_CACHE_PROFILING_Type; /*!< Size = 28 (0x01C) */ + +/* CACHE_PROFILING_ENABLE: Enable the profiling counters. */ + #define CACHE_PROFILING_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable the profiling counters */ + #define CACHE_PROFILING_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define CACHE_PROFILING_ENABLE_ENABLE_Msk (0x1UL << CACHE_PROFILING_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define CACHE_PROFILING_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define CACHE_PROFILING_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define CACHE_PROFILING_ENABLE_ENABLE_Disable (0x0UL) /*!< Disable profiling */ + #define CACHE_PROFILING_ENABLE_ENABLE_Enable (0x1UL) /*!< Enable profiling */ + + +/* CACHE_PROFILING_CLEAR: Clear the profiling counters. */ + #define CACHE_PROFILING_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of CLEAR register. */ + +/* CLEAR @Bit 0 : Clearing the profiling counters */ + #define CACHE_PROFILING_CLEAR_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */ + #define CACHE_PROFILING_CLEAR_CLEAR_Msk (0x1UL << CACHE_PROFILING_CLEAR_CLEAR_Pos) /*!< Bit mask of CLEAR field. */ + #define CACHE_PROFILING_CLEAR_CLEAR_Min (0x1UL) /*!< Min enumerator value of CLEAR field. */ + #define CACHE_PROFILING_CLEAR_CLEAR_Max (0x1UL) /*!< Max enumerator value of CLEAR field. */ + #define CACHE_PROFILING_CLEAR_CLEAR_Clear (0x1UL) /*!< Clear the profiling counters */ + + +/* CACHE_PROFILING_HIT: The cache hit counter for cache region. */ + #define CACHE_PROFILING_HIT_ResetValue (0x00000000UL) /*!< Reset value of HIT register. */ + +/* HITS @Bits 0..31 : Number of cache hits */ + #define CACHE_PROFILING_HIT_HITS_Pos (0UL) /*!< Position of HITS field. */ + #define CACHE_PROFILING_HIT_HITS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_HIT_HITS_Pos) /*!< Bit mask of HITS field. */ + + +/* CACHE_PROFILING_MISS: The cache miss counter for cache region. */ + #define CACHE_PROFILING_MISS_ResetValue (0x00000000UL) /*!< Reset value of MISS register. */ + +/* MISSES @Bits 0..31 : Number of cache misses */ + #define CACHE_PROFILING_MISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ + #define CACHE_PROFILING_MISS_MISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_MISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ + + +/* CACHE_PROFILING_LMISS: The cache line miss counter for cache region. */ + #define CACHE_PROFILING_LMISS_ResetValue (0x00000000UL) /*!< Reset value of LMISS register. */ + +/* LMISSES @Bits 0..31 : Number of cache line misses */ + #define CACHE_PROFILING_LMISS_LMISSES_Pos (0UL) /*!< Position of LMISSES field. */ + #define CACHE_PROFILING_LMISS_LMISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_LMISS_LMISSES_Pos) /*!< Bit mask of LMISSES field.*/ + + +/* CACHE_PROFILING_READS: Number of reads for cache region. */ + #define CACHE_PROFILING_READS_ResetValue (0x00000000UL) /*!< Reset value of READS register. */ + +/* READS @Bits 0..31 : Number of reads for cache region. */ + #define CACHE_PROFILING_READS_READS_Pos (0UL) /*!< Position of READS field. */ + #define CACHE_PROFILING_READS_READS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_READS_READS_Pos) /*!< Bit mask of READS field. */ + + +/* CACHE_PROFILING_WRITES: Number of writes for cache region. */ + #define CACHE_PROFILING_WRITES_ResetValue (0x00000000UL) /*!< Reset value of WRITES register. */ + +/* WRITES @Bits 0..31 : Number of writes for cache region. */ + #define CACHE_PROFILING_WRITES_WRITES_Pos (0UL) /*!< Position of WRITES field. */ + #define CACHE_PROFILING_WRITES_WRITES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_WRITES_WRITES_Pos) /*!< Bit mask of WRITES field. */ + + +/* ====================================================== Struct CACHE ======================================================= */ +/** + * @brief Cache + */ + typedef struct { /*!< CACHE Structure */ + __IM uint32_t RESERVED[2]; + __OM uint32_t TASKS_INVALIDATECACHE; /*!< (@ 0x00000008) Invalidate the cache. */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_INVALIDATELINE; /*!< (@ 0x00000014) Invalidate the line. */ + __IM uint32_t RESERVED2[2]; + __OM uint32_t TASKS_ERASE; /*!< (@ 0x00000020) Erase the cache. */ + __IM uint32_t RESERVED3[247]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status of the cache activities. */ + __IOM uint32_t ENABLE; /*!< (@ 0x00000404) Enable cache. */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t LINEADDR; /*!< (@ 0x00000410) Memory address covered by the line to be maintained. */ + __IOM NRF_CACHE_PROFILING_Type PROFILING; /*!< (@ 0x00000414) (unspecified) */ + __IOM uint32_t DEBUGLOCK; /*!< (@ 0x00000430) Lock debug mode. */ + __IOM uint32_t WRITELOCK; /*!< (@ 0x00000434) Lock cache updates. */ + } NRF_CACHE_Type; /*!< Size = 1080 (0x438) */ + +/* CACHE_TASKS_INVALIDATECACHE: Invalidate the cache. */ + #define CACHE_TASKS_INVALIDATECACHE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_INVALIDATECACHE register. */ + +/* TASKS_INVALIDATECACHE @Bit 0 : Invalidate the cache. */ + #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Pos (0UL) /*!< Position of TASKS_INVALIDATECACHE field. */ + #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Msk (0x1UL << CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Pos) + /*!< Bit mask of TASKS_INVALIDATECACHE field.*/ + #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Min (0x1UL) /*!< Min enumerator value of TASKS_INVALIDATECACHE + field.*/ + #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Max (0x1UL) /*!< Max enumerator value of TASKS_INVALIDATECACHE + field.*/ + #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_TASKS_INVALIDATELINE: Invalidate the line. */ + #define CACHE_TASKS_INVALIDATELINE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_INVALIDATELINE register. */ + +/* TASKS_INVALIDATELINE @Bit 0 : Invalidate the line. */ + #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Pos (0UL) /*!< Position of TASKS_INVALIDATELINE field. */ + #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Msk (0x1UL << CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Pos) + /*!< Bit mask of TASKS_INVALIDATELINE field.*/ + #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Min (0x1UL) /*!< Min enumerator value of TASKS_INVALIDATELINE field. */ + #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Max (0x1UL) /*!< Max enumerator value of TASKS_INVALIDATELINE field. */ + #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_TASKS_ERASE: Erase the cache. */ + #define CACHE_TASKS_ERASE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ERASE register. */ + +/* TASKS_ERASE @Bit 0 : Erase the cache. */ + #define CACHE_TASKS_ERASE_TASKS_ERASE_Pos (0UL) /*!< Position of TASKS_ERASE field. */ + #define CACHE_TASKS_ERASE_TASKS_ERASE_Msk (0x1UL << CACHE_TASKS_ERASE_TASKS_ERASE_Pos) /*!< Bit mask of TASKS_ERASE field. */ + #define CACHE_TASKS_ERASE_TASKS_ERASE_Min (0x1UL) /*!< Min enumerator value of TASKS_ERASE field. */ + #define CACHE_TASKS_ERASE_TASKS_ERASE_Max (0x1UL) /*!< Max enumerator value of TASKS_ERASE field. */ + #define CACHE_TASKS_ERASE_TASKS_ERASE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_STATUS: Status of the cache activities. */ + #define CACHE_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* READY @Bit 0 : Ready status. */ + #define CACHE_STATUS_READY_Pos (0UL) /*!< Position of READY field. */ + #define CACHE_STATUS_READY_Msk (0x1UL << CACHE_STATUS_READY_Pos) /*!< Bit mask of READY field. */ + #define CACHE_STATUS_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define CACHE_STATUS_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define CACHE_STATUS_READY_Ready (0x0UL) /*!< Activity is done and ready for the next activity. */ + #define CACHE_STATUS_READY_Busy (0x1UL) /*!< Activity is in progress. */ + + +/* CACHE_ENABLE: Enable cache. */ + #define CACHE_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable cache */ + #define CACHE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define CACHE_ENABLE_ENABLE_Msk (0x1UL << CACHE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define CACHE_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define CACHE_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define CACHE_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable cache */ + #define CACHE_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable cache */ + + +/* CACHE_LINEADDR: Memory address covered by the line to be maintained. */ + #define CACHE_LINEADDR_ResetValue (0x00000000UL) /*!< Reset value of LINEADDR register. */ + +/* ADDR @Bits 0..31 : Address. */ + #define CACHE_LINEADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ + #define CACHE_LINEADDR_ADDR_Msk (0xFFFFFFFFUL << CACHE_LINEADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + + +/* CACHE_DEBUGLOCK: Lock debug mode. */ + #define CACHE_DEBUGLOCK_ResetValue (0x00000000UL) /*!< Reset value of DEBUGLOCK register. */ + +/* DEBUGLOCK @Bit 0 : Lock debug mode */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Pos (0UL) /*!< Position of DEBUGLOCK field. */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Msk (0x1UL << CACHE_DEBUGLOCK_DEBUGLOCK_Pos) /*!< Bit mask of DEBUGLOCK field. */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Min (0x0UL) /*!< Min enumerator value of DEBUGLOCK field. */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Max (0x1UL) /*!< Max enumerator value of DEBUGLOCK field. */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Unlocked (0x0UL) /*!< Debug mode unlocked */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Locked (0x1UL) /*!< Debug mode locked. Ignores any other value written. */ + + +/* CACHE_WRITELOCK: Lock cache updates. */ + #define CACHE_WRITELOCK_ResetValue (0x00000000UL) /*!< Reset value of WRITELOCK register. */ + +/* WRITELOCK @Bit 0 : Lock cache updates */ + #define CACHE_WRITELOCK_WRITELOCK_Pos (0UL) /*!< Position of WRITELOCK field. */ + #define CACHE_WRITELOCK_WRITELOCK_Msk (0x1UL << CACHE_WRITELOCK_WRITELOCK_Pos) /*!< Bit mask of WRITELOCK field. */ + #define CACHE_WRITELOCK_WRITELOCK_Min (0x0UL) /*!< Min enumerator value of WRITELOCK field. */ + #define CACHE_WRITELOCK_WRITELOCK_Max (0x1UL) /*!< Max enumerator value of WRITELOCK field. */ + #define CACHE_WRITELOCK_WRITELOCK_Unlocked (0x0UL) /*!< Cache updates unlocked */ + #define CACHE_WRITELOCK_WRITELOCK_Locked (0x1UL) /*!< Cache updates locked */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CACHEDATA ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =============================================== Struct CACHEDATA_SET_WAY_DU =============================================== */ +/** + * @brief DU [CACHEDATA_SET_WAY_DU] (unspecified) + */ +typedef struct { + __IOM uint32_t DATA[2]; /*!< (@ 0x00000000) Cache data bits for DATA[q] in DU[p] (DataUnit) of + SET[n], WAY[o].*/ +} NRF_CACHEDATA_SET_WAY_DU_Type; /*!< Size = 8 (0x008) */ + #define CACHEDATA_SET_WAY_DU_MaxCount (4UL) /*!< Size of DU[4] array. */ + #define CACHEDATA_SET_WAY_DU_MaxIndex (3UL) /*!< Max index of DU[4] array. */ + #define CACHEDATA_SET_WAY_DU_MinIndex (0UL) /*!< Min index of DU[4] array. */ + +/* CACHEDATA_SET_WAY_DU_DATA: Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o]. */ + #define CACHEDATA_SET_WAY_DU_DATA_MaxCount (2UL) /*!< Max size of DATA[2] array. */ + #define CACHEDATA_SET_WAY_DU_DATA_MaxIndex (1UL) /*!< Max index of DATA[2] array. */ + #define CACHEDATA_SET_WAY_DU_DATA_MinIndex (0UL) /*!< Min index of DATA[2] array. */ + #define CACHEDATA_SET_WAY_DU_DATA_ResetValue (0x00000000UL) /*!< Reset value of DATA[2] register. */ + +/* Data @Bits 0..31 : Data */ + #define CACHEDATA_SET_WAY_DU_DATA_Data_Pos (0UL) /*!< Position of Data field. */ + #define CACHEDATA_SET_WAY_DU_DATA_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DU_DATA_Data_Pos) /*!< Bit mask of Data field. */ + + + +/* ================================================ Struct CACHEDATA_SET_WAY ================================================= */ +/** + * @brief WAY [CACHEDATA_SET_WAY] (unspecified) + */ +typedef struct { + __IOM NRF_CACHEDATA_SET_WAY_DU_Type DU[4]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_CACHEDATA_SET_WAY_Type; /*!< Size = 32 (0x020) */ + #define CACHEDATA_SET_WAY_MaxCount (2UL) /*!< Size of WAY[2] array. */ + #define CACHEDATA_SET_WAY_MaxIndex (1UL) /*!< Max index of WAY[2] array. */ + #define CACHEDATA_SET_WAY_MinIndex (0UL) /*!< Min index of WAY[2] array. */ + + +/* ================================================== Struct CACHEDATA_SET =================================================== */ +/** + * @brief SET [CACHEDATA_SET] (unspecified) + */ +typedef struct { + __IOM NRF_CACHEDATA_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_CACHEDATA_SET_Type; /*!< Size = 64 (0x040) */ + #define CACHEDATA_SET_MaxCount (128UL) /*!< Size of SET[128] array. */ + #define CACHEDATA_SET_MaxIndex (127UL) /*!< Max index of SET[128] array. */ + #define CACHEDATA_SET_MinIndex (0UL) /*!< Min index of SET[128] array. */ + +/* ==================================================== Struct CACHEDATA ===================================================== */ +/** + * @brief CACHEDATA + */ + typedef struct { /*!< CACHEDATA Structure */ + __IOM NRF_CACHEDATA_SET_Type SET[128]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_CACHEDATA_Type; /*!< Size = 8192 (0x2000) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CACHEINFO ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct CACHEINFO_SET_WAY ================================================= */ +/** + * @brief WAY [CACHEINFO_SET_WAY] (unspecified) + */ +typedef struct { + __IOM uint32_t INFO; /*!< (@ 0x00000000) Cache information for SET[n], WAY[o]. */ +} NRF_CACHEINFO_SET_WAY_Type; /*!< Size = 4 (0x004) */ + #define CACHEINFO_SET_WAY_MaxCount (2UL) /*!< Size of WAY[2] array. */ + #define CACHEINFO_SET_WAY_MaxIndex (1UL) /*!< Max index of WAY[2] array. */ + #define CACHEINFO_SET_WAY_MinIndex (0UL) /*!< Min index of WAY[2] array. */ + +/* CACHEINFO_SET_WAY_INFO: Cache information for SET[n], WAY[o]. */ + #define CACHEINFO_SET_WAY_INFO_ResetValue (0x00000000UL) /*!< Reset value of INFO register. */ + +/* TAG @Bits 0..19 : Cache tag. */ + #define CACHEINFO_SET_WAY_INFO_TAG_Pos (0UL) /*!< Position of TAG field. */ + #define CACHEINFO_SET_WAY_INFO_TAG_Msk (0xFFFFFUL << CACHEINFO_SET_WAY_INFO_TAG_Pos) /*!< Bit mask of TAG field. */ + +/* DUV0 @Bit 24 : Data unit valid info. */ + #define CACHEINFO_SET_WAY_INFO_DUV0_Pos (24UL) /*!< Position of DUV0 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV0_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_DUV0_Pos) /*!< Bit mask of DUV0 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV0_Min (0x0UL) /*!< Min enumerator value of DUV0 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV0_Max (0x1UL) /*!< Max enumerator value of DUV0 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV0_Invalid (0x0UL) /*!< Invalid data unit */ + #define CACHEINFO_SET_WAY_INFO_DUV0_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV1 @Bit 25 : Data unit valid info. */ + #define CACHEINFO_SET_WAY_INFO_DUV1_Pos (25UL) /*!< Position of DUV1 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV1_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_DUV1_Pos) /*!< Bit mask of DUV1 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV1_Min (0x0UL) /*!< Min enumerator value of DUV1 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV1_Max (0x1UL) /*!< Max enumerator value of DUV1 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV1_Invalid (0x0UL) /*!< Invalid data unit */ + #define CACHEINFO_SET_WAY_INFO_DUV1_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV2 @Bit 26 : Data unit valid info. */ + #define CACHEINFO_SET_WAY_INFO_DUV2_Pos (26UL) /*!< Position of DUV2 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV2_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_DUV2_Pos) /*!< Bit mask of DUV2 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV2_Min (0x0UL) /*!< Min enumerator value of DUV2 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV2_Max (0x1UL) /*!< Max enumerator value of DUV2 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV2_Invalid (0x0UL) /*!< Invalid data unit */ + #define CACHEINFO_SET_WAY_INFO_DUV2_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV3 @Bit 27 : Data unit valid info. */ + #define CACHEINFO_SET_WAY_INFO_DUV3_Pos (27UL) /*!< Position of DUV3 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV3_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_DUV3_Pos) /*!< Bit mask of DUV3 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV3_Min (0x0UL) /*!< Min enumerator value of DUV3 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV3_Max (0x1UL) /*!< Max enumerator value of DUV3 field. */ + #define CACHEINFO_SET_WAY_INFO_DUV3_Invalid (0x0UL) /*!< Invalid data unit */ + #define CACHEINFO_SET_WAY_INFO_DUV3_Valid (0x1UL) /*!< Valid data unit */ + +/* V @Bit 30 : Line valid bit. */ + #define CACHEINFO_SET_WAY_INFO_V_Pos (30UL) /*!< Position of V field. */ + #define CACHEINFO_SET_WAY_INFO_V_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_V_Pos) /*!< Bit mask of V field. */ + #define CACHEINFO_SET_WAY_INFO_V_Min (0x0UL) /*!< Min enumerator value of V field. */ + #define CACHEINFO_SET_WAY_INFO_V_Max (0x1UL) /*!< Max enumerator value of V field. */ + #define CACHEINFO_SET_WAY_INFO_V_Invalid (0x0UL) /*!< Invalid cache line */ + #define CACHEINFO_SET_WAY_INFO_V_Valid (0x1UL) /*!< Valid cache line */ + +/* MRU @Bit 31 : Most recently used way. */ + #define CACHEINFO_SET_WAY_INFO_MRU_Pos (31UL) /*!< Position of MRU field. */ + #define CACHEINFO_SET_WAY_INFO_MRU_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_MRU_Pos) /*!< Bit mask of MRU field. */ + #define CACHEINFO_SET_WAY_INFO_MRU_Min (0x0UL) /*!< Min enumerator value of MRU field. */ + #define CACHEINFO_SET_WAY_INFO_MRU_Max (0x1UL) /*!< Max enumerator value of MRU field. */ + #define CACHEINFO_SET_WAY_INFO_MRU_Way0 (0x0UL) /*!< Way0 was most recently used */ + #define CACHEINFO_SET_WAY_INFO_MRU_Way1 (0x1UL) /*!< Way1 was most recently used */ + + + +/* ================================================== Struct CACHEINFO_SET =================================================== */ +/** + * @brief SET [CACHEINFO_SET] (unspecified) + */ +typedef struct { + __IOM NRF_CACHEINFO_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_CACHEINFO_SET_Type; /*!< Size = 8 (0x008) */ + #define CACHEINFO_SET_MaxCount (128UL) /*!< Size of SET[128] array. */ + #define CACHEINFO_SET_MaxIndex (127UL) /*!< Max index of SET[128] array. */ + #define CACHEINFO_SET_MinIndex (0UL) /*!< Min index of SET[128] array. */ + +/* ==================================================== Struct CACHEINFO ===================================================== */ +/** + * @brief CACHEINFO + */ + typedef struct { /*!< CACHEINFO Structure */ + __IOM NRF_CACHEINFO_SET_Type SET[128]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_CACHEINFO_Type; /*!< Size = 1024 (0x400) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ===================================================== Struct CCM_KEY ====================================================== */ +/** + * @brief KEY [CCM_KEY] (unspecified) + */ +typedef struct { + __OM uint32_t VALUE[4]; /*!< (@ 0x00000000) 128-bit AES key */ +} NRF_CCM_KEY_Type; /*!< Size = 16 (0x010) */ + +/* CCM_KEY_VALUE: 128-bit AES key */ + #define CCM_KEY_VALUE_MaxCount (4UL) /*!< Max size of VALUE[4] array. */ + #define CCM_KEY_VALUE_MaxIndex (3UL) /*!< Max index of VALUE[4] array. */ + #define CCM_KEY_VALUE_MinIndex (0UL) /*!< Min index of VALUE[4] array. */ + #define CCM_KEY_VALUE_ResetValue (0x00000000UL) /*!< Reset value of VALUE[4] register. */ + +/* VALUE @Bits 0..31 : AES 128-bit key value, bits (32*(i+1))-1 : (32*i) */ + #define CCM_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define CCM_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << CCM_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + + +/* ==================================================== Struct CCM_NONCE ===================================================== */ +/** + * @brief NONCE [CCM_NONCE] (unspecified) + */ +typedef struct { + __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) 13-byte NONCE vector Only the lower 13 bytes are used */ +} NRF_CCM_NONCE_Type; /*!< Size = 16 (0x010) */ + +/* CCM_NONCE_VALUE: 13-byte NONCE vector Only the lower 13 bytes are used */ + #define CCM_NONCE_VALUE_MaxCount (4UL) /*!< Max size of VALUE[4] array. */ + #define CCM_NONCE_VALUE_MaxIndex (3UL) /*!< Max index of VALUE[4] array. */ + #define CCM_NONCE_VALUE_MinIndex (0UL) /*!< Min index of VALUE[4] array. */ + #define CCM_NONCE_VALUE_ResetValue (0x00000000UL) /*!< Reset value of VALUE[4] register. */ + +/* VALUE @Bits 0..31 : NONCE value, bits (32*(n+1))-1 : (32*n) */ + #define CCM_NONCE_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define CCM_NONCE_VALUE_VALUE_Msk (0xFFFFFFFFUL << CCM_NONCE_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + + +/* ====================================================== Struct CCM_IN ====================================================== */ +/** + * @brief IN [CCM_IN] IN EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Input pointer Points to a job list containing + unencrypted CCM data structure in Encryption mode + Points to a job list containing encrypted CCM data + structure in Decryption mode*/ +} NRF_CCM_IN_Type; /*!< Size = 4 (0x004) */ + +/* CCM_IN_PTR: Input pointer Points to a job list containing unencrypted CCM data structure in Encryption mode Points to a job + list containing encrypted CCM data structure in Decryption mode */ + + #define CCM_IN_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Input pointer */ + #define CCM_IN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define CCM_IN_PTR_PTR_Msk (0xFFFFFFFFUL << CCM_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + + +/* ===================================================== Struct CCM_OUT ====================================================== */ +/** + * @brief OUT [CCM_OUT] OUT EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Output pointer Points to a job list containing + encrypted CCM data structure in Encryption mode Points + to a job list containing decrypted CCM data structure + in Decryption mode*/ +} NRF_CCM_OUT_Type; /*!< Size = 4 (0x004) */ + +/* CCM_OUT_PTR: Output pointer Points to a job list containing encrypted CCM data structure in Encryption mode Points to a job + list containing decrypted CCM data structure in Decryption mode */ + + #define CCM_OUT_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Output pointer */ + #define CCM_OUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define CCM_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << CCM_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* ======================================================= Struct CCM ======================================================== */ +/** + * @brief AES CCM Mode Encryption + */ + typedef struct { /*!< CCM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start encryption/decryption. This operation will stop + by itself when completed.*/ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop encryption/decryption */ + __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x00000008) Override DATARATE setting in MODE register with the + contents of the RATEOVERRIDE register for any ongoing + encryption/decryption*/ + __IM uint32_t RESERVED[29]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_RATEOVERRIDE; /*!< (@ 0x00000088) Subscribe configuration for task RATEOVERRIDE */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Encrypt/decrypt complete or ended because of an error */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */ + __IM uint32_t RESERVED2[30]; + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000188) Publish configuration for event ERROR */ + __IM uint32_t RESERVED3[94]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IM uint32_t MACSTATUS; /*!< (@ 0x00000400) MAC check result */ + __IM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) Error status */ + __IM uint32_t RESERVED5[62]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IM uint32_t RESERVED6[2]; + __IOM NRF_CCM_KEY_Type KEY; /*!< (@ 0x00000510) (unspecified) */ + __IOM NRF_CCM_NONCE_Type NONCE; /*!< (@ 0x00000520) (unspecified) */ + __IOM NRF_CCM_IN_Type IN; /*!< (@ 0x00000530) IN EasyDMA channel */ + __IM uint32_t RESERVED7; + __IOM NRF_CCM_OUT_Type OUT; /*!< (@ 0x00000538) OUT EasyDMA channel */ + __IM uint32_t RESERVED8[2]; + __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x00000544) Data rate override setting. */ + __IOM uint32_t ADATAMASK; /*!< (@ 0x00000548) CCM adata mask. */ + } NRF_CCM_Type; /*!< Size = 1356 (0x54C) */ + +/* CCM_TASKS_START: Start encryption/decryption. This operation will stop by itself when completed. */ + #define CCM_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ + #define CCM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define CCM_TASKS_START_TASKS_START_Msk (0x1UL << CCM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define CCM_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define CCM_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define CCM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* CCM_TASKS_STOP: Stop encryption/decryption */ + #define CCM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop encryption/decryption */ + #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define CCM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define CCM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define CCM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* CCM_TASKS_RATEOVERRIDE: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any + ongoing encryption/decryption */ + + #define CCM_TASKS_RATEOVERRIDE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RATEOVERRIDE register. */ + +/* TASKS_RATEOVERRIDE @Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any + ongoing encryption/decryption */ + + #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ + #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask + of TASKS_RATEOVERRIDE field.*/ + #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Min (0x1UL) /*!< Min enumerator value of TASKS_RATEOVERRIDE field. */ + #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Max (0x1UL) /*!< Max enumerator value of TASKS_RATEOVERRIDE field. */ + #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CCM_SUBSCRIBE_START: Subscribe configuration for task START */ + #define CCM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define CCM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CCM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CCM_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CCM_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CCM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define CCM_SUBSCRIBE_START_EN_Msk (0x1UL << CCM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define CCM_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CCM_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CCM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CCM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CCM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define CCM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define CCM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CCM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CCM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CCM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CCM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define CCM_SUBSCRIBE_STOP_EN_Msk (0x1UL << CCM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define CCM_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CCM_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CCM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CCM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CCM_SUBSCRIBE_RATEOVERRIDE: Subscribe configuration for task RATEOVERRIDE */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RATEOVERRIDE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RATEOVERRIDE will subscribe to */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos (31UL) /*!< Position of EN field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Msk (0x1UL << CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos) /*!< Bit mask of EN field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CCM_EVENTS_END: Encrypt/decrypt complete or ended because of an error */ + #define CCM_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : Encrypt/decrypt complete or ended because of an error */ + #define CCM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define CCM_EVENTS_END_EVENTS_END_Msk (0x1UL << CCM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define CCM_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define CCM_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define CCM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define CCM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* CCM_EVENTS_ERROR: CCM error event */ + #define CCM_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : CCM error event */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* CCM_PUBLISH_END: Publish configuration for event END */ + #define CCM_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define CCM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CCM_PUBLISH_END_CHIDX_Msk (0xFFUL << CCM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CCM_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CCM_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CCM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define CCM_PUBLISH_END_EN_Msk (0x1UL << CCM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define CCM_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CCM_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CCM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CCM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CCM_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define CCM_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define CCM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CCM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CCM_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CCM_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CCM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define CCM_PUBLISH_ERROR_EN_Msk (0x1UL << CCM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define CCM_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CCM_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CCM_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CCM_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CCM_INTENSET: Enable interrupt */ + #define CCM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* END @Bit 1 : Write '1' to enable interrupt for event END */ + #define CCM_INTENSET_END_Pos (1UL) /*!< Position of END field. */ + #define CCM_INTENSET_END_Msk (0x1UL << CCM_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define CCM_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define CCM_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define CCM_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define CCM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define CCM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 2 : Write '1' to enable interrupt for event ERROR */ + #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ + #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define CCM_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define CCM_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define CCM_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define CCM_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define CCM_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CCM_INTENCLR: Disable interrupt */ + #define CCM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* END @Bit 1 : Write '1' to disable interrupt for event END */ + #define CCM_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ + #define CCM_INTENCLR_END_Msk (0x1UL << CCM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define CCM_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define CCM_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define CCM_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define CCM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define CCM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 2 : Write '1' to disable interrupt for event ERROR */ + #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ + #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define CCM_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define CCM_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define CCM_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define CCM_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define CCM_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CCM_MACSTATUS: MAC check result */ + #define CCM_MACSTATUS_ResetValue (0x00000000UL) /*!< Reset value of MACSTATUS register. */ + +/* MACSTATUS @Bit 0 : The result of the MAC check performed during the previous decryption operation */ + #define CCM_MACSTATUS_MACSTATUS_Pos (0UL) /*!< Position of MACSTATUS field. */ + #define CCM_MACSTATUS_MACSTATUS_Msk (0x1UL << CCM_MACSTATUS_MACSTATUS_Pos) /*!< Bit mask of MACSTATUS field. */ + #define CCM_MACSTATUS_MACSTATUS_Min (0x0UL) /*!< Min enumerator value of MACSTATUS field. */ + #define CCM_MACSTATUS_MACSTATUS_Max (0x1UL) /*!< Max enumerator value of MACSTATUS field. */ + #define CCM_MACSTATUS_MACSTATUS_CheckFailed (0x0UL) /*!< MAC check failed */ + #define CCM_MACSTATUS_MACSTATUS_CheckPassed (0x1UL) /*!< MAC check passed */ + + +/* CCM_ERRORSTATUS: Error status */ + #define CCM_ERRORSTATUS_ResetValue (0x00000000UL) /*!< Reset value of ERRORSTATUS register. */ + +/* ERRORSTATUS @Bits 0..2 : Error status when the ERROR event is generated */ + #define CCM_ERRORSTATUS_ERRORSTATUS_Pos (0UL) /*!< Position of ERRORSTATUS field. */ + #define CCM_ERRORSTATUS_ERRORSTATUS_Msk (0x7UL << CCM_ERRORSTATUS_ERRORSTATUS_Pos) /*!< Bit mask of ERRORSTATUS field. */ + #define CCM_ERRORSTATUS_ERRORSTATUS_Min (0x0UL) /*!< Min enumerator value of ERRORSTATUS field. */ + #define CCM_ERRORSTATUS_ERRORSTATUS_Max (0x4UL) /*!< Max enumerator value of ERRORSTATUS field. */ + #define CCM_ERRORSTATUS_ERRORSTATUS_NoError (0x0UL) /*!< No errors have occurred */ + #define CCM_ERRORSTATUS_ERRORSTATUS_PrematureInptrEnd (0x1UL) /*!< End of INPTR job list before CCM data structure was read. */ + #define CCM_ERRORSTATUS_ERRORSTATUS_PrematureOutptrEnd (0x2UL) /*!< End of OUTPTR job list before CCM data structure was + read.*/ + #define CCM_ERRORSTATUS_ERRORSTATUS_EncryptionTooSlow (0x3UL) /*!< Encryption of the unencrypted CCM data structure did not + complete in time.*/ + #define CCM_ERRORSTATUS_ERRORSTATUS_DmaError (0x4UL) /*!< Bus error during DMA access. */ + + +/* CCM_ENABLE: Enable */ + #define CCM_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..1 : Enable or disable CCM */ + #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define CCM_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define CCM_ENABLE_ENABLE_Max (0x2UL) /*!< Max enumerator value of ENABLE field. */ + #define CCM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define CCM_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable */ + + +/* CCM_MODE: Operation mode */ + #define CCM_MODE_ResetValue (0x00000001UL) /*!< Reset value of MODE register. */ + +/* MODE @Bits 0..1 : The mode of operation to be used. The settings in this register apply when the CRYPT task is triggered. */ + #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define CCM_MODE_MODE_Msk (0x3UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define CCM_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define CCM_MODE_MODE_Max (0x2UL) /*!< Max enumerator value of MODE field. */ + #define CCM_MODE_MODE_Encryption (0x0UL) /*!< AES CCM packet encryption mode */ + #define CCM_MODE_MODE_Decryption (0x1UL) /*!< This mode will run CCM decryption in the speed of the DATARATE field.*/ + #define CCM_MODE_MODE_FastDecryption (0x2UL) /*!< AES CCM decryption mode. */ + +/* PROTOCOL @Bits 8..9 : Protocol and packet format selection */ + #define CCM_MODE_PROTOCOL_Pos (8UL) /*!< Position of PROTOCOL field. */ + #define CCM_MODE_PROTOCOL_Msk (0x3UL << CCM_MODE_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ + #define CCM_MODE_PROTOCOL_Min (0x0UL) /*!< Min enumerator value of PROTOCOL field. */ + #define CCM_MODE_PROTOCOL_Max (0x1UL) /*!< Max enumerator value of PROTOCOL field. */ + #define CCM_MODE_PROTOCOL_Ble (0x0UL) /*!< Bluetooth Low Energy packet format */ + #define CCM_MODE_PROTOCOL_Ieee802154 (0x1UL) /*!< 802.15.4 packet format */ + +/* DATARATE @Bits 16..18 : Radio data rate that the CCM shall run synchronous with */ + #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ + #define CCM_MODE_DATARATE_Msk (0x7UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ + #define CCM_MODE_DATARATE_Min (0x0UL) /*!< Min enumerator value of DATARATE field. */ + #define CCM_MODE_DATARATE_Max (0x5UL) /*!< Max enumerator value of DATARATE field. */ + #define CCM_MODE_DATARATE_125Kbit (0x0UL) /*!< 125 Kbps */ + #define CCM_MODE_DATARATE_250Kbit (0x1UL) /*!< 250 Kbps */ + #define CCM_MODE_DATARATE_500Kbit (0x2UL) /*!< 500 Kbps */ + #define CCM_MODE_DATARATE_1Mbit (0x3UL) /*!< 1 Mbps */ + #define CCM_MODE_DATARATE_2Mbit (0x4UL) /*!< 2 Mbps */ + #define CCM_MODE_DATARATE_4Mbit (0x5UL) /*!< 4 Mbps */ + +/* MACLEN @Bits 24..26 : CCM MAC length (bytes) */ + #define CCM_MODE_MACLEN_Pos (24UL) /*!< Position of MACLEN field. */ + #define CCM_MODE_MACLEN_Msk (0x7UL << CCM_MODE_MACLEN_Pos) /*!< Bit mask of MACLEN field. */ + #define CCM_MODE_MACLEN_Min (0x0UL) /*!< Min enumerator value of MACLEN field. */ + #define CCM_MODE_MACLEN_Max (0x7UL) /*!< Max enumerator value of MACLEN field. */ + #define CCM_MODE_MACLEN_M0 (0x0UL) /*!< M = 0 This is a special case for CCM* where encryption is required but + not authentication*/ + #define CCM_MODE_MACLEN_M4 (0x1UL) /*!< M = 4 */ + #define CCM_MODE_MACLEN_M6 (0x2UL) /*!< M = 6 */ + #define CCM_MODE_MACLEN_M8 (0x3UL) /*!< M = 8 */ + #define CCM_MODE_MACLEN_M10 (0x4UL) /*!< M = 10 */ + #define CCM_MODE_MACLEN_M12 (0x5UL) /*!< M = 12 */ + #define CCM_MODE_MACLEN_M14 (0x6UL) /*!< M = 14 */ + #define CCM_MODE_MACLEN_M16 (0x7UL) /*!< M = 16 */ + + +/* CCM_RATEOVERRIDE: Data rate override setting. */ + #define CCM_RATEOVERRIDE_ResetValue (0x00000002UL) /*!< Reset value of RATEOVERRIDE register. */ + +/* RATEOVERRIDE @Bits 0..2 : Data rate override setting. */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x7UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_Min (0x0UL) /*!< Min enumerator value of RATEOVERRIDE field. */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_Max (0x5UL) /*!< Max enumerator value of RATEOVERRIDE field. */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbit (0x0UL) /*!< 125 Kbps */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbit (0x2UL) /*!< 500 Kbps */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0x3UL) /*!< 1 Mbps */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (0x4UL) /*!< 2 Mbps */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_4Mbit (0x5UL) /*!< 4 Mbps */ + + +/* CCM_ADATAMASK: CCM adata mask. */ + #define CCM_ADATAMASK_ResetValue (0x000000E3UL) /*!< Reset value of ADATAMASK register. */ + +/* ADATAMASK @Bits 0..7 : CCM adata mask. */ + #define CCM_ADATAMASK_ADATAMASK_Pos (0UL) /*!< Position of ADATAMASK field. */ + #define CCM_ADATAMASK_ADATAMASK_Msk (0xFFUL << CCM_ADATAMASK_ADATAMASK_Pos) /*!< Bit mask of ADATAMASK field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CLIC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ==================================================== Struct CLIC_CLIC ===================================================== */ +/** + * @brief CLIC [CLIC_CLIC] (unspecified) + */ +typedef struct { + __IM uint32_t CLICCFG; /*!< (@ 0x00000000) CLIC configuration. */ + __IM uint32_t CLICINFO; /*!< (@ 0x00000004) CLIC information. */ + __IM uint32_t RESERVED[1022]; + __IOM uint32_t CLICINT[271]; /*!< (@ 0x00001000) Interrupt control register for IRQ number [n]. */ +} NRF_CLIC_CLIC_Type; /*!< Size = 5180 (0x143C) */ + +/* CLIC_CLIC_CLICCFG: CLIC configuration. */ + #define CLIC_CLIC_CLICCFG_ResetValue (0x00000011UL) /*!< Reset value of CLICCFG register. */ + +/* NVBITS @Bit 0 : Selective interrupt hardware vectoring. */ + #define CLIC_CLIC_CLICCFG_NVBITS_Pos (0UL) /*!< Position of NVBITS field. */ + #define CLIC_CLIC_CLICCFG_NVBITS_Msk (0x1UL << CLIC_CLIC_CLICCFG_NVBITS_Pos) /*!< Bit mask of NVBITS field. */ + #define CLIC_CLIC_CLICCFG_NVBITS_Min (0x1UL) /*!< Min enumerator value of NVBITS field. */ + #define CLIC_CLIC_CLICCFG_NVBITS_Max (0x1UL) /*!< Max enumerator value of NVBITS field. */ + #define CLIC_CLIC_CLICCFG_NVBITS_Implemented (0x1UL) /*!< Selective interrupt hardware vectoring is implemented */ + +/* NLBITS @Bits 1..4 : Interrupt level encoding. */ + #define CLIC_CLIC_CLICCFG_NLBITS_Pos (1UL) /*!< Position of NLBITS field. */ + #define CLIC_CLIC_CLICCFG_NLBITS_Msk (0xFUL << CLIC_CLIC_CLICCFG_NLBITS_Pos) /*!< Bit mask of NLBITS field. */ + #define CLIC_CLIC_CLICCFG_NLBITS_Min (0x8UL) /*!< Min enumerator value of NLBITS field. */ + #define CLIC_CLIC_CLICCFG_NLBITS_Max (0x8UL) /*!< Max enumerator value of NLBITS field. */ + #define CLIC_CLIC_CLICCFG_NLBITS_Eight (0x8UL) /*!< 8 bits = interrupt levels encoded in eight bits */ + +/* NMBITS @Bits 5..6 : Interrupt privilege mode. */ + #define CLIC_CLIC_CLICCFG_NMBITS_Pos (5UL) /*!< Position of NMBITS field. */ + #define CLIC_CLIC_CLICCFG_NMBITS_Msk (0x3UL << CLIC_CLIC_CLICCFG_NMBITS_Pos) /*!< Bit mask of NMBITS field. */ + #define CLIC_CLIC_CLICCFG_NMBITS_Min (0x0UL) /*!< Min enumerator value of NMBITS field. */ + #define CLIC_CLIC_CLICCFG_NMBITS_Max (0x0UL) /*!< Max enumerator value of NMBITS field. */ + #define CLIC_CLIC_CLICCFG_NMBITS_ModeM (0x0UL) /*!< All interrupts are M-mode only */ + + +/* CLIC_CLIC_CLICINFO: CLIC information. */ + #define CLIC_CLIC_CLICINFO_ResetValue (0x00401FFFUL) /*!< Reset value of CLICINFO register. */ + +/* NUMINTERRUPTS @Bits 0..12 : Maximum number of interrupts supported. */ + #define CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Pos (0UL) /*!< Position of NUMINTERRUPTS field. */ + #define CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Msk (0x1FFFUL << CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Pos) /*!< Bit mask of NUMINTERRUPTS + field.*/ + +/* VERSION @Bits 13..20 : Version */ + #define CLIC_CLIC_CLICINFO_VERSION_Pos (13UL) /*!< Position of VERSION field. */ + #define CLIC_CLIC_CLICINFO_VERSION_Msk (0xFFUL << CLIC_CLIC_CLICINFO_VERSION_Pos) /*!< Bit mask of VERSION field. */ + +/* NUMTRIGGER @Bits 25..30 : Number of maximum interrupt triggers supported */ + #define CLIC_CLIC_CLICINFO_NUMTRIGGER_Pos (25UL) /*!< Position of NUMTRIGGER field. */ + #define CLIC_CLIC_CLICINFO_NUMTRIGGER_Msk (0x3FUL << CLIC_CLIC_CLICINFO_NUMTRIGGER_Pos) /*!< Bit mask of NUMTRIGGER field. */ + + +/* CLIC_CLIC_CLICINT: Interrupt control register for IRQ number [n]. */ + #define CLIC_CLIC_CLICINT_MaxCount (271UL) /*!< Max size of CLICINT[271] array. */ + #define CLIC_CLIC_CLICINT_MaxIndex (270UL) /*!< Max index of CLICINT[271] array. */ + #define CLIC_CLIC_CLICINT_MinIndex (0UL) /*!< Min index of CLICINT[271] array. */ + #define CLIC_CLIC_CLICINT_ResetValue (0x3FC30000UL) /*!< Reset value of CLICINT[271] register. */ + +/* IP @Bit 0 : Interrupt Pending bit. */ + #define CLIC_CLIC_CLICINT_IP_Pos (0UL) /*!< Position of IP field. */ + #define CLIC_CLIC_CLICINT_IP_Msk (0x1UL << CLIC_CLIC_CLICINT_IP_Pos) /*!< Bit mask of IP field. */ + #define CLIC_CLIC_CLICINT_IP_Min (0x0UL) /*!< Min enumerator value of IP field. */ + #define CLIC_CLIC_CLICINT_IP_Max (0x1UL) /*!< Max enumerator value of IP field. */ + #define CLIC_CLIC_CLICINT_IP_NotPending (0x0UL) /*!< Interrupt not pending */ + #define CLIC_CLIC_CLICINT_IP_Pending (0x1UL) /*!< Interrupt pending */ + +/* READ1 @Bits 1..7 : Read as 0, write ignored. */ + #define CLIC_CLIC_CLICINT_READ1_Pos (1UL) /*!< Position of READ1 field. */ + #define CLIC_CLIC_CLICINT_READ1_Msk (0x7FUL << CLIC_CLIC_CLICINT_READ1_Pos) /*!< Bit mask of READ1 field. */ + +/* IE @Bit 8 : Interrupt enable bit. */ + #define CLIC_CLIC_CLICINT_IE_Pos (8UL) /*!< Position of IE field. */ + #define CLIC_CLIC_CLICINT_IE_Msk (0x1UL << CLIC_CLIC_CLICINT_IE_Pos) /*!< Bit mask of IE field. */ + #define CLIC_CLIC_CLICINT_IE_Min (0x0UL) /*!< Min enumerator value of IE field. */ + #define CLIC_CLIC_CLICINT_IE_Max (0x1UL) /*!< Max enumerator value of IE field. */ + #define CLIC_CLIC_CLICINT_IE_Disabled (0x0UL) /*!< Interrupt disabled */ + #define CLIC_CLIC_CLICINT_IE_Enabled (0x1UL) /*!< Interrupt enabled */ + +/* READ2 @Bits 9..15 : Read as 0, write ignored. */ + #define CLIC_CLIC_CLICINT_READ2_Pos (9UL) /*!< Position of READ2 field. */ + #define CLIC_CLIC_CLICINT_READ2_Msk (0x7FUL << CLIC_CLIC_CLICINT_READ2_Pos) /*!< Bit mask of READ2 field. */ + +/* SHV @Bit 16 : Selective Hardware Vectoring. */ + #define CLIC_CLIC_CLICINT_SHV_Pos (16UL) /*!< Position of SHV field. */ + #define CLIC_CLIC_CLICINT_SHV_Msk (0x1UL << CLIC_CLIC_CLICINT_SHV_Pos) /*!< Bit mask of SHV field. */ + #define CLIC_CLIC_CLICINT_SHV_Min (0x1UL) /*!< Min enumerator value of SHV field. */ + #define CLIC_CLIC_CLICINT_SHV_Max (0x1UL) /*!< Max enumerator value of SHV field. */ + #define CLIC_CLIC_CLICINT_SHV_Vectored (0x1UL) /*!< Hardware vectored */ + +/* TRIG @Bits 17..18 : Trigger type and polarity for each interrupt input. */ + #define CLIC_CLIC_CLICINT_TRIG_Pos (17UL) /*!< Position of TRIG field. */ + #define CLIC_CLIC_CLICINT_TRIG_Msk (0x3UL << CLIC_CLIC_CLICINT_TRIG_Pos) /*!< Bit mask of TRIG field. */ + #define CLIC_CLIC_CLICINT_TRIG_Min (0x1UL) /*!< Min enumerator value of TRIG field. */ + #define CLIC_CLIC_CLICINT_TRIG_Max (0x1UL) /*!< Max enumerator value of TRIG field. */ + #define CLIC_CLIC_CLICINT_TRIG_EdgeTriggered (0x1UL) /*!< Interrupts are edge-triggered */ + +/* MODE @Bits 22..23 : Privilege mode. */ + #define CLIC_CLIC_CLICINT_MODE_Pos (22UL) /*!< Position of MODE field. */ + #define CLIC_CLIC_CLICINT_MODE_Msk (0x3UL << CLIC_CLIC_CLICINT_MODE_Pos) /*!< Bit mask of MODE field. */ + #define CLIC_CLIC_CLICINT_MODE_Min (0x3UL) /*!< Min enumerator value of MODE field. */ + #define CLIC_CLIC_CLICINT_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field. */ + #define CLIC_CLIC_CLICINT_MODE_MachineMode (0x3UL) /*!< Machine mode */ + +/* PRIORITY @Bits 24..31 : Interrupt priority level */ + #define CLIC_CLIC_CLICINT_PRIORITY_Pos (24UL) /*!< Position of PRIORITY field. */ + #define CLIC_CLIC_CLICINT_PRIORITY_Msk (0xFFUL << CLIC_CLIC_CLICINT_PRIORITY_Pos) /*!< Bit mask of PRIORITY field. */ + #define CLIC_CLIC_CLICINT_PRIORITY_Min (0x3FUL) /*!< Min enumerator value of PRIORITY field. */ + #define CLIC_CLIC_CLICINT_PRIORITY_Max (0xFFUL) /*!< Max enumerator value of PRIORITY field. */ + #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL0 (0x3FUL) /*!< Priority level 0 */ + #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL1 (0x7FUL) /*!< Priority level 1 */ + #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL2 (0xBFUL) /*!< Priority level 2 */ + #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL3 (0xFFUL) /*!< Priority level 3 */ + + +/* ======================================================= Struct CLIC ======================================================= */ +/** + * @brief VPR CLIC registers + */ + typedef struct { /*!< CLIC Structure */ + __IOM NRF_CLIC_CLIC_Type CLIC; /*!< (@ 0x00000000) (unspecified) */ + } NRF_CLIC_Type; /*!< Size = 5180 (0x143C) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ===================================================== Struct CLOCK_XO ===================================================== */ +/** + * @brief XO [CLOCK_XO] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IM uint32_t RUN; /*!< (@ 0x00000008) Indicates that XOSTART task was triggered */ + __IM uint32_t STAT; /*!< (@ 0x0000000C) XO status */ +} NRF_CLOCK_XO_Type; /*!< Size = 16 (0x010) */ + +/* CLOCK_XO_RUN: Indicates that XOSTART task was triggered */ + #define CLOCK_XO_RUN_ResetValue (0x00000000UL) /*!< Reset value of RUN register. */ + +/* STATUS @Bit 0 : XOSTART task triggered or not */ + #define CLOCK_XO_RUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define CLOCK_XO_RUN_STATUS_Msk (0x1UL << CLOCK_XO_RUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define CLOCK_XO_RUN_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define CLOCK_XO_RUN_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define CLOCK_XO_RUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */ + #define CLOCK_XO_RUN_STATUS_Triggered (0x1UL) /*!< Task triggered */ + + +/* CLOCK_XO_STAT: XO status */ + #define CLOCK_XO_STAT_ResetValue (0x00000000UL) /*!< Reset value of STAT register. */ + +/* STATE @Bit 16 : XO state (Running between START task and STOPPED event) */ + #define CLOCK_XO_STAT_STATE_Pos (16UL) /*!< Position of STATE field. */ + #define CLOCK_XO_STAT_STATE_Msk (0x1UL << CLOCK_XO_STAT_STATE_Pos) /*!< Bit mask of STATE field. */ + #define CLOCK_XO_STAT_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field. */ + #define CLOCK_XO_STAT_STATE_Max (0x1UL) /*!< Max enumerator value of STATE field. */ + #define CLOCK_XO_STAT_STATE_NotRunning (0x0UL) /*!< XO is not running */ + #define CLOCK_XO_STAT_STATE_Running (0x1UL) /*!< XO is running */ + + + +/* ==================================================== Struct CLOCK_PLL ===================================================== */ +/** + * @brief PLL [CLOCK_PLL] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IM uint32_t RUN; /*!< (@ 0x00000008) Indicates that PLLSTART task was triggered */ + __IM uint32_t STAT; /*!< (@ 0x0000000C) Which PLL settings were selected when triggering START + task*/ +} NRF_CLOCK_PLL_Type; /*!< Size = 16 (0x010) */ + +/* CLOCK_PLL_RUN: Indicates that PLLSTART task was triggered */ + #define CLOCK_PLL_RUN_ResetValue (0x00000000UL) /*!< Reset value of RUN register. */ + +/* STATUS @Bit 0 : PLLSTART task triggered or not */ + #define CLOCK_PLL_RUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define CLOCK_PLL_RUN_STATUS_Msk (0x1UL << CLOCK_PLL_RUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define CLOCK_PLL_RUN_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define CLOCK_PLL_RUN_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define CLOCK_PLL_RUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */ + #define CLOCK_PLL_RUN_STATUS_Triggered (0x1UL) /*!< Task triggered */ + + +/* CLOCK_PLL_STAT: Which PLL settings were selected when triggering START task */ + #define CLOCK_PLL_STAT_ResetValue (0x00000000UL) /*!< Reset value of STAT register. */ + +/* STATE @Bit 16 : PLL state (Running between START task and STOPPED event) */ + #define CLOCK_PLL_STAT_STATE_Pos (16UL) /*!< Position of STATE field. */ + #define CLOCK_PLL_STAT_STATE_Msk (0x1UL << CLOCK_PLL_STAT_STATE_Pos) /*!< Bit mask of STATE field. */ + #define CLOCK_PLL_STAT_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field. */ + #define CLOCK_PLL_STAT_STATE_Max (0x1UL) /*!< Max enumerator value of STATE field. */ + #define CLOCK_PLL_STAT_STATE_NotRunning (0x0UL) /*!< PLL is not running */ + #define CLOCK_PLL_STAT_STATE_Running (0x1UL) /*!< PLL is running */ + + + +/* =================================================== Struct CLOCK_LFCLK ==================================================== */ +/** + * @brief LFCLK [CLOCK_LFCLK] (unspecified) + */ +typedef struct { + __IOM uint32_t SRC; /*!< (@ 0x00000000) Clock source for LFCLK */ + __IM uint32_t RESERVED; + __IM uint32_t RUN; /*!< (@ 0x00000008) Indicates that LFCLKSTART task was triggered */ + __IM uint32_t STAT; /*!< (@ 0x0000000C) Copy of LFCLK.SRCCOPY register, set when LFCLKSTARTED + event is triggered.*/ + __IOM uint32_t SRCCOPY; /*!< (@ 0x00000010) Copy of LFCLK.SRC register, set when LFCLKSTART task is + triggered*/ +} NRF_CLOCK_LFCLK_Type; /*!< Size = 20 (0x014) */ + +/* CLOCK_LFCLK_SRC: Clock source for LFCLK */ + #define CLOCK_LFCLK_SRC_ResetValue (0x00000000UL) /*!< Reset value of SRC register. */ + +/* SRC @Bits 0..1 : Select which LFCLK source is started by the LFCLKSTART task */ + #define CLOCK_LFCLK_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */ + #define CLOCK_LFCLK_SRC_SRC_Msk (0x3UL << CLOCK_LFCLK_SRC_SRC_Pos) /*!< Bit mask of SRC field. */ + #define CLOCK_LFCLK_SRC_SRC_Min (0x0UL) /*!< Min enumerator value of SRC field. */ + #define CLOCK_LFCLK_SRC_SRC_Max (0x2UL) /*!< Max enumerator value of SRC field. */ + #define CLOCK_LFCLK_SRC_SRC_LFRC (0x0UL) /*!< 32.768 kHz RC oscillator */ + #define CLOCK_LFCLK_SRC_SRC_LFXO (0x1UL) /*!< 32.768 kHz crystal oscillator */ + #define CLOCK_LFCLK_SRC_SRC_LFSYNT (0x2UL) /*!< 32.768 kHz synthesized from HFCLK */ + + +/* CLOCK_LFCLK_RUN: Indicates that LFCLKSTART task was triggered */ + #define CLOCK_LFCLK_RUN_ResetValue (0x00000000UL) /*!< Reset value of RUN register. */ + +/* STATUS @Bit 0 : LFCLKSTART task triggered or not */ + #define CLOCK_LFCLK_RUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define CLOCK_LFCLK_RUN_STATUS_Msk (0x1UL << CLOCK_LFCLK_RUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define CLOCK_LFCLK_RUN_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define CLOCK_LFCLK_RUN_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define CLOCK_LFCLK_RUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */ + #define CLOCK_LFCLK_RUN_STATUS_Triggered (0x1UL) /*!< Task triggered */ + + +/* CLOCK_LFCLK_STAT: Copy of LFCLK.SRCCOPY register, set when LFCLKSTARTED event is triggered. */ + #define CLOCK_LFCLK_STAT_ResetValue (0x00000000UL) /*!< Reset value of STAT register. */ + +/* SRC @Bits 0..1 : Value of LFCLK.SRCCOPY register when LFCLKSTARTED event was triggered */ + #define CLOCK_LFCLK_STAT_SRC_Pos (0UL) /*!< Position of SRC field. */ + #define CLOCK_LFCLK_STAT_SRC_Msk (0x3UL << CLOCK_LFCLK_STAT_SRC_Pos) /*!< Bit mask of SRC field. */ + #define CLOCK_LFCLK_STAT_SRC_Min (0x0UL) /*!< Min enumerator value of SRC field. */ + #define CLOCK_LFCLK_STAT_SRC_Max (0x2UL) /*!< Max enumerator value of SRC field. */ + #define CLOCK_LFCLK_STAT_SRC_LFRC (0x0UL) /*!< 32.768 kHz RC oscillator */ + #define CLOCK_LFCLK_STAT_SRC_LFXO (0x1UL) /*!< 32.768 kHz crystal oscillator */ + #define CLOCK_LFCLK_STAT_SRC_LFSYNT (0x2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* STATE @Bit 16 : LFCLK state (Running between START task and STOPPED event) */ + #define CLOCK_LFCLK_STAT_STATE_Pos (16UL) /*!< Position of STATE field. */ + #define CLOCK_LFCLK_STAT_STATE_Msk (0x1UL << CLOCK_LFCLK_STAT_STATE_Pos) /*!< Bit mask of STATE field. */ + #define CLOCK_LFCLK_STAT_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field. */ + #define CLOCK_LFCLK_STAT_STATE_Max (0x1UL) /*!< Max enumerator value of STATE field. */ + #define CLOCK_LFCLK_STAT_STATE_NotRunning (0x0UL) /*!< LFCLK not running */ + #define CLOCK_LFCLK_STAT_STATE_Running (0x1UL) /*!< LFCLK running */ + + +/* CLOCK_LFCLK_SRCCOPY: Copy of LFCLK.SRC register, set when LFCLKSTART task is triggered */ + #define CLOCK_LFCLK_SRCCOPY_ResetValue (0x00000000UL) /*!< Reset value of SRCCOPY register. */ + +/* SRC @Bits 0..1 : Value of LFCLK.SRC register when LFCLKSTART task was triggered */ + #define CLOCK_LFCLK_SRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ + #define CLOCK_LFCLK_SRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLK_SRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ + #define CLOCK_LFCLK_SRCCOPY_SRC_Min (0x0UL) /*!< Min enumerator value of SRC field. */ + #define CLOCK_LFCLK_SRCCOPY_SRC_Max (0x2UL) /*!< Max enumerator value of SRC field. */ + #define CLOCK_LFCLK_SRCCOPY_SRC_LFRC (0x0UL) /*!< 32.768 kHz RC oscillator */ + #define CLOCK_LFCLK_SRCCOPY_SRC_LFXO (0x1UL) /*!< 32.768 kHz crystal oscillator */ + #define CLOCK_LFCLK_SRCCOPY_SRC_LFSYNT (0x2UL) /*!< 32.768 kHz synthesized from HFCLK */ + + + +/* =================================================== Struct CLOCK_PLL24M =================================================== */ +/** + * @brief PLL24M [CLOCK_PLL24M] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IM uint32_t RUN; /*!< (@ 0x00000008) Indicates that XO24MSTART task was triggered */ + __IM uint32_t STAT; /*!< (@ 0x0000000C) Which PLL settings were selected when triggering START + task*/ +} NRF_CLOCK_PLL24M_Type; /*!< Size = 16 (0x010) */ + +/* CLOCK_PLL24M_RUN: Indicates that XO24MSTART task was triggered */ + #define CLOCK_PLL24M_RUN_ResetValue (0x00000000UL) /*!< Reset value of RUN register. */ + +/* STATUS @Bit 0 : XO24MSTART task triggered or not */ + #define CLOCK_PLL24M_RUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define CLOCK_PLL24M_RUN_STATUS_Msk (0x1UL << CLOCK_PLL24M_RUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define CLOCK_PLL24M_RUN_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define CLOCK_PLL24M_RUN_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define CLOCK_PLL24M_RUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */ + #define CLOCK_PLL24M_RUN_STATUS_Triggered (0x1UL) /*!< Task triggered */ + + +/* CLOCK_PLL24M_STAT: Which PLL settings were selected when triggering START task */ + #define CLOCK_PLL24M_STAT_ResetValue (0x00000000UL) /*!< Reset value of STAT register. */ + +/* STATE @Bit 16 : PLL state (Running between START task and STOPPED event) */ + #define CLOCK_PLL24M_STAT_STATE_Pos (16UL) /*!< Position of STATE field. */ + #define CLOCK_PLL24M_STAT_STATE_Msk (0x1UL << CLOCK_PLL24M_STAT_STATE_Pos) /*!< Bit mask of STATE field. */ + #define CLOCK_PLL24M_STAT_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field. */ + #define CLOCK_PLL24M_STAT_STATE_Max (0x1UL) /*!< Max enumerator value of STATE field. */ + #define CLOCK_PLL24M_STAT_STATE_NotRunning (0x0UL) /*!< PLL24M is not running */ + #define CLOCK_PLL24M_STAT_STATE_Running (0x1UL) /*!< PLL24M is running */ + + +/* ====================================================== Struct CLOCK ======================================================= */ +/** + * @brief Clock management + */ + typedef struct { /*!< CLOCK Structure */ + __OM uint32_t TASKS_XOSTART; /*!< (@ 0x00000000) Start crystal oscillator (HFXO) */ + __OM uint32_t TASKS_XOSTOP; /*!< (@ 0x00000004) Stop crystal oscillator (HFXO) */ + __OM uint32_t TASKS_PLLSTART; /*!< (@ 0x00000008) Start PLL and keep it running, regardless of the + automatic clock requests*/ + __OM uint32_t TASKS_PLLSTOP; /*!< (@ 0x0000000C) Stop PLL */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000010) Start LFCLK source as selected in LFCLK.SRC */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x00000014) Stop LFCLK source */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000018) Start calibration of LFRC oscillator */ + __OM uint32_t TASKS_XOTUNE; /*!< (@ 0x0000001C) Request tuning for HFXO */ + __OM uint32_t TASKS_XOTUNEABORT; /*!< (@ 0x00000020) Abort tuning for HFXO */ + __OM uint32_t TASKS_XO24MSTART; /*!< (@ 0x00000024) Request HFXO to provide a crystal clock for PCLK24M */ + __OM uint32_t TASKS_XO24MSTOP; /*!< (@ 0x00000028) Stop request HFXO for PCLK24M. When all requests for + HFXO are stopped, HFXO will also stop.*/ + __IM uint32_t RESERVED[21]; + __IOM uint32_t SUBSCRIBE_XOSTART; /*!< (@ 0x00000080) Subscribe configuration for task XOSTART */ + __IOM uint32_t SUBSCRIBE_XOSTOP; /*!< (@ 0x00000084) Subscribe configuration for task XOSTOP */ + __IOM uint32_t SUBSCRIBE_PLLSTART; /*!< (@ 0x00000088) Subscribe configuration for task PLLSTART */ + __IOM uint32_t SUBSCRIBE_PLLSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task PLLSTOP */ + __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000090) Subscribe configuration for task LFCLKSTART */ + __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x00000094) Subscribe configuration for task LFCLKSTOP */ + __IOM uint32_t SUBSCRIBE_CAL; /*!< (@ 0x00000098) Subscribe configuration for task CAL */ + __IOM uint32_t SUBSCRIBE_XOTUNE; /*!< (@ 0x0000009C) Subscribe configuration for task XOTUNE */ + __IOM uint32_t SUBSCRIBE_XOTUNEABORT; /*!< (@ 0x000000A0) Subscribe configuration for task XOTUNEABORT */ + __IOM uint32_t SUBSCRIBE_XO24MSTART; /*!< (@ 0x000000A4) Subscribe configuration for task XO24MSTART */ + __IOM uint32_t SUBSCRIBE_XO24MSTOP; /*!< (@ 0x000000A8) Subscribe configuration for task XO24MSTOP */ + __IM uint32_t RESERVED1[21]; + __IOM uint32_t EVENTS_XOSTARTED; /*!< (@ 0x00000100) Crystal oscillator has started */ + __IOM uint32_t EVENTS_PLLSTARTED; /*!< (@ 0x00000104) PLL started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000108) LFCLK source started */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC oscillator complete event */ + __IOM uint32_t EVENTS_XOTUNED; /*!< (@ 0x00000110) HFXO tuning is done. XOTUNED is generated after + TASKS_XOSTART or after TASKS_XOTUNE has completed*/ + __IOM uint32_t EVENTS_XOTUNEERROR; /*!< (@ 0x00000114) HFXO quality issue detected, XOTUNE is needed */ + __IOM uint32_t EVENTS_XOTUNEFAILED; /*!< (@ 0x00000118) HFXO tuning could not be completed */ + __IOM uint32_t EVENTS_XO24MSTARTED; /*!< (@ 0x0000011C) XO24M started */ + __IM uint32_t RESERVED2[24]; + __IOM uint32_t PUBLISH_XOSTARTED; /*!< (@ 0x00000180) Publish configuration for event XOSTARTED */ + __IOM uint32_t PUBLISH_PLLSTARTED; /*!< (@ 0x00000184) Publish configuration for event PLLSTARTED */ + __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000188) Publish configuration for event LFCLKSTARTED */ + __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x0000018C) Publish configuration for event DONE */ + __IOM uint32_t PUBLISH_XOTUNED; /*!< (@ 0x00000190) Publish configuration for event XOTUNED */ + __IOM uint32_t PUBLISH_XOTUNEERROR; /*!< (@ 0x00000194) Publish configuration for event XOTUNEERROR */ + __IOM uint32_t PUBLISH_XOTUNEFAILED; /*!< (@ 0x00000198) Publish configuration for event XOTUNEFAILED */ + __IOM uint32_t PUBLISH_XO24MSTARTED; /*!< (@ 0x0000019C) Publish configuration for event XO24MSTARTED */ + __IM uint32_t RESERVED3[88]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED4[60]; + __IOM NRF_CLOCK_XO_Type XO; /*!< (@ 0x00000400) (unspecified) */ + __IM uint32_t RESERVED5[4]; + __IOM NRF_CLOCK_PLL_Type PLL; /*!< (@ 0x00000420) (unspecified) */ + __IM uint32_t RESERVED6[4]; + __IOM NRF_CLOCK_LFCLK_Type LFCLK; /*!< (@ 0x00000440) (unspecified) */ + __IM uint32_t RESERVED7[3]; + __IOM NRF_CLOCK_PLL24M_Type PLL24M; /*!< (@ 0x00000460) (unspecified) */ + } NRF_CLOCK_Type; /*!< Size = 1136 (0x470) */ + +/* CLOCK_TASKS_XOSTART: Start crystal oscillator (HFXO) */ + #define CLOCK_TASKS_XOSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_XOSTART register. */ + +/* TASKS_XOSTART @Bit 0 : Start crystal oscillator (HFXO) */ + #define CLOCK_TASKS_XOSTART_TASKS_XOSTART_Pos (0UL) /*!< Position of TASKS_XOSTART field. */ + #define CLOCK_TASKS_XOSTART_TASKS_XOSTART_Msk (0x1UL << CLOCK_TASKS_XOSTART_TASKS_XOSTART_Pos) /*!< Bit mask of TASKS_XOSTART + field.*/ + #define CLOCK_TASKS_XOSTART_TASKS_XOSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_XOSTART field. */ + #define CLOCK_TASKS_XOSTART_TASKS_XOSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_XOSTART field. */ + #define CLOCK_TASKS_XOSTART_TASKS_XOSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* CLOCK_TASKS_XOSTOP: Stop crystal oscillator (HFXO) */ + #define CLOCK_TASKS_XOSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_XOSTOP register. */ + +/* TASKS_XOSTOP @Bit 0 : Stop crystal oscillator (HFXO) */ + #define CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Pos (0UL) /*!< Position of TASKS_XOSTOP field. */ + #define CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Msk (0x1UL << CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Pos) /*!< Bit mask of TASKS_XOSTOP + field.*/ + #define CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_XOSTOP field. */ + #define CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_XOSTOP field. */ + #define CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* CLOCK_TASKS_PLLSTART: Start PLL and keep it running, regardless of the automatic clock requests */ + #define CLOCK_TASKS_PLLSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PLLSTART register. */ + +/* TASKS_PLLSTART @Bit 0 : Start PLL and keep it running, regardless of the automatic clock requests */ + #define CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Pos (0UL) /*!< Position of TASKS_PLLSTART field. */ + #define CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Msk (0x1UL << CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Pos) /*!< Bit mask of + TASKS_PLLSTART field.*/ + #define CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_PLLSTART field. */ + #define CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_PLLSTART field. */ + #define CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* CLOCK_TASKS_PLLSTOP: Stop PLL */ + #define CLOCK_TASKS_PLLSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PLLSTOP register. */ + +/* TASKS_PLLSTOP @Bit 0 : Stop PLL */ + #define CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Pos (0UL) /*!< Position of TASKS_PLLSTOP field. */ + #define CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Msk (0x1UL << CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Pos) /*!< Bit mask of TASKS_PLLSTOP + field.*/ + #define CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_PLLSTOP field. */ + #define CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_PLLSTOP field. */ + #define CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* CLOCK_TASKS_LFCLKSTART: Start LFCLK source as selected in LFCLK.SRC */ + #define CLOCK_TASKS_LFCLKSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_LFCLKSTART register. */ + +/* TASKS_LFCLKSTART @Bit 0 : Start LFCLK source as selected in LFCLK.SRC */ + #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ + #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of + TASKS_LFCLKSTART field.*/ + #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_LFCLKSTART field. */ + #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_LFCLKSTART field. */ + #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* CLOCK_TASKS_LFCLKSTOP: Stop LFCLK source */ + #define CLOCK_TASKS_LFCLKSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_LFCLKSTOP register. */ + +/* TASKS_LFCLKSTOP @Bit 0 : Stop LFCLK source */ + #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ + #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of + TASKS_LFCLKSTOP field.*/ + #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_LFCLKSTOP field. */ + #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_LFCLKSTOP field. */ + #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* CLOCK_TASKS_CAL: Start calibration of LFRC oscillator */ + #define CLOCK_TASKS_CAL_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CAL register. */ + +/* TASKS_CAL @Bit 0 : Start calibration of LFRC oscillator */ + #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ + #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ + #define CLOCK_TASKS_CAL_TASKS_CAL_Min (0x1UL) /*!< Min enumerator value of TASKS_CAL field. */ + #define CLOCK_TASKS_CAL_TASKS_CAL_Max (0x1UL) /*!< Max enumerator value of TASKS_CAL field. */ + #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (0x1UL) /*!< Trigger task */ + + +/* CLOCK_TASKS_XOTUNE: Request tuning for HFXO */ + #define CLOCK_TASKS_XOTUNE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_XOTUNE register. */ + +/* TASKS_XOTUNE @Bit 0 : Request tuning for HFXO */ + #define CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Pos (0UL) /*!< Position of TASKS_XOTUNE field. */ + #define CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Msk (0x1UL << CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Pos) /*!< Bit mask of TASKS_XOTUNE + field.*/ + #define CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Min (0x1UL) /*!< Min enumerator value of TASKS_XOTUNE field. */ + #define CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Max (0x1UL) /*!< Max enumerator value of TASKS_XOTUNE field. */ + #define CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CLOCK_TASKS_XOTUNEABORT: Abort tuning for HFXO */ + #define CLOCK_TASKS_XOTUNEABORT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_XOTUNEABORT register. */ + +/* TASKS_XOTUNEABORT @Bit 0 : Abort tuning for HFXO */ + #define CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Pos (0UL) /*!< Position of TASKS_XOTUNEABORT field. */ + #define CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Msk (0x1UL << CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Pos) /*!< Bit mask + of TASKS_XOTUNEABORT field.*/ + #define CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Min (0x1UL) /*!< Min enumerator value of TASKS_XOTUNEABORT field. */ + #define CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Max (0x1UL) /*!< Max enumerator value of TASKS_XOTUNEABORT field. */ + #define CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Trigger (0x1UL) /*!< Trigger task */ + + +/* CLOCK_TASKS_XO24MSTART: Request HFXO to provide a crystal clock for PCLK24M */ + #define CLOCK_TASKS_XO24MSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_XO24MSTART register. */ + +/* TASKS_XO24MSTART @Bit 0 : Request HFXO to provide a crystal clock for PCLK24M */ + #define CLOCK_TASKS_XO24MSTART_TASKS_XO24MSTART_Pos (0UL) /*!< Position of TASKS_XO24MSTART field. */ + #define CLOCK_TASKS_XO24MSTART_TASKS_XO24MSTART_Msk (0x1UL << CLOCK_TASKS_XO24MSTART_TASKS_XO24MSTART_Pos) /*!< Bit mask of + TASKS_XO24MSTART field.*/ + #define CLOCK_TASKS_XO24MSTART_TASKS_XO24MSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_XO24MSTART field. */ + #define CLOCK_TASKS_XO24MSTART_TASKS_XO24MSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_XO24MSTART field. */ + #define CLOCK_TASKS_XO24MSTART_TASKS_XO24MSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* CLOCK_TASKS_XO24MSTOP: Stop request HFXO for PCLK24M. When all requests for HFXO are stopped, HFXO will also stop. */ + #define CLOCK_TASKS_XO24MSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_XO24MSTOP register. */ + +/* TASKS_XO24MSTOP @Bit 0 : Stop request HFXO for PCLK24M. When all requests for HFXO are stopped, HFXO will also stop. */ + #define CLOCK_TASKS_XO24MSTOP_TASKS_XO24MSTOP_Pos (0UL) /*!< Position of TASKS_XO24MSTOP field. */ + #define CLOCK_TASKS_XO24MSTOP_TASKS_XO24MSTOP_Msk (0x1UL << CLOCK_TASKS_XO24MSTOP_TASKS_XO24MSTOP_Pos) /*!< Bit mask of + TASKS_XO24MSTOP field.*/ + #define CLOCK_TASKS_XO24MSTOP_TASKS_XO24MSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_XO24MSTOP field. */ + #define CLOCK_TASKS_XO24MSTOP_TASKS_XO24MSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_XO24MSTOP field. */ + #define CLOCK_TASKS_XO24MSTOP_TASKS_XO24MSTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* CLOCK_SUBSCRIBE_XOSTART: Subscribe configuration for task XOSTART */ + #define CLOCK_SUBSCRIBE_XOSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_XOSTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task XOSTART will subscribe to */ + #define CLOCK_SUBSCRIBE_XOSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XOSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_XOSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XOSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XOSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_SUBSCRIBE_XOSTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_SUBSCRIBE_XOSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_XOSTART_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_SUBSCRIBE_XOSTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XOSTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XOSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CLOCK_SUBSCRIBE_XOSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CLOCK_SUBSCRIBE_XOSTOP: Subscribe configuration for task XOSTOP */ + #define CLOCK_SUBSCRIBE_XOSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_XOSTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task XOSTOP will subscribe to */ + #define CLOCK_SUBSCRIBE_XOSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XOSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_XOSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XOSTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XOSTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_SUBSCRIBE_XOSTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_SUBSCRIBE_XOSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_XOSTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_SUBSCRIBE_XOSTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XOSTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XOSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CLOCK_SUBSCRIBE_XOSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CLOCK_SUBSCRIBE_PLLSTART: Subscribe configuration for task PLLSTART */ + #define CLOCK_SUBSCRIBE_PLLSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PLLSTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task PLLSTART will subscribe to */ + #define CLOCK_SUBSCRIBE_PLLSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_SUBSCRIBE_PLLSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_PLLSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_SUBSCRIBE_PLLSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_SUBSCRIBE_PLLSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_SUBSCRIBE_PLLSTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_SUBSCRIBE_PLLSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_PLLSTART_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_SUBSCRIBE_PLLSTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_PLLSTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_PLLSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CLOCK_SUBSCRIBE_PLLSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CLOCK_SUBSCRIBE_PLLSTOP: Subscribe configuration for task PLLSTOP */ + #define CLOCK_SUBSCRIBE_PLLSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PLLSTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task PLLSTOP will subscribe to */ + #define CLOCK_SUBSCRIBE_PLLSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_SUBSCRIBE_PLLSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_PLLSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_SUBSCRIBE_PLLSTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_SUBSCRIBE_PLLSTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_PLLSTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CLOCK_SUBSCRIBE_LFCLKSTART: Subscribe configuration for task LFCLKSTART */ + #define CLOCK_SUBSCRIBE_LFCLKSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_LFCLKSTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task LFCLKSTART will subscribe to */ + #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CLOCK_SUBSCRIBE_LFCLKSTOP: Subscribe configuration for task LFCLKSTOP */ + #define CLOCK_SUBSCRIBE_LFCLKSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_LFCLKSTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task LFCLKSTOP will subscribe to */ + #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CLOCK_SUBSCRIBE_CAL: Subscribe configuration for task CAL */ + #define CLOCK_SUBSCRIBE_CAL_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAL register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CAL will subscribe to */ + #define CLOCK_SUBSCRIBE_CAL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_SUBSCRIBE_CAL_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_CAL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_SUBSCRIBE_CAL_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_SUBSCRIBE_CAL_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_SUBSCRIBE_CAL_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_SUBSCRIBE_CAL_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_CAL_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_SUBSCRIBE_CAL_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_CAL_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_CAL_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CLOCK_SUBSCRIBE_CAL_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CLOCK_SUBSCRIBE_XOTUNE: Subscribe configuration for task XOTUNE */ + #define CLOCK_SUBSCRIBE_XOTUNE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_XOTUNE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task XOTUNE will subscribe to */ + #define CLOCK_SUBSCRIBE_XOTUNE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XOTUNE_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_XOTUNE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XOTUNE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XOTUNE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_SUBSCRIBE_XOTUNE_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_SUBSCRIBE_XOTUNE_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_XOTUNE_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_SUBSCRIBE_XOTUNE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XOTUNE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XOTUNE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CLOCK_SUBSCRIBE_XOTUNE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CLOCK_SUBSCRIBE_XOTUNEABORT: Subscribe configuration for task XOTUNEABORT */ + #define CLOCK_SUBSCRIBE_XOTUNEABORT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_XOTUNEABORT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task XOTUNEABORT will subscribe to */ + #define CLOCK_SUBSCRIBE_XOTUNEABORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XOTUNEABORT_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_XOTUNEABORT_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define CLOCK_SUBSCRIBE_XOTUNEABORT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XOTUNEABORT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_SUBSCRIBE_XOTUNEABORT_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_SUBSCRIBE_XOTUNEABORT_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_XOTUNEABORT_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_SUBSCRIBE_XOTUNEABORT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XOTUNEABORT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XOTUNEABORT_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CLOCK_SUBSCRIBE_XOTUNEABORT_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CLOCK_SUBSCRIBE_XO24MSTART: Subscribe configuration for task XO24MSTART */ + #define CLOCK_SUBSCRIBE_XO24MSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_XO24MSTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task XO24MSTART will subscribe to */ + #define CLOCK_SUBSCRIBE_XO24MSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XO24MSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_XO24MSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XO24MSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XO24MSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_SUBSCRIBE_XO24MSTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_SUBSCRIBE_XO24MSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_XO24MSTART_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_SUBSCRIBE_XO24MSTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XO24MSTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XO24MSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CLOCK_SUBSCRIBE_XO24MSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CLOCK_SUBSCRIBE_XO24MSTOP: Subscribe configuration for task XO24MSTOP */ + #define CLOCK_SUBSCRIBE_XO24MSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_XO24MSTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task XO24MSTOP will subscribe to */ + #define CLOCK_SUBSCRIBE_XO24MSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XO24MSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_XO24MSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XO24MSTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_SUBSCRIBE_XO24MSTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_SUBSCRIBE_XO24MSTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_SUBSCRIBE_XO24MSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_XO24MSTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_SUBSCRIBE_XO24MSTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XO24MSTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_SUBSCRIBE_XO24MSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CLOCK_SUBSCRIBE_XO24MSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CLOCK_EVENTS_XOSTARTED: Crystal oscillator has started */ + #define CLOCK_EVENTS_XOSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_XOSTARTED register. */ + +/* EVENTS_XOSTARTED @Bit 0 : Crystal oscillator has started */ + #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Pos (0UL) /*!< Position of EVENTS_XOSTARTED field. */ + #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Msk (0x1UL << CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Pos) /*!< Bit mask of + EVENTS_XOSTARTED field.*/ + #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_XOSTARTED field. */ + #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_XOSTARTED field. */ + #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Generated (0x1UL) /*!< Event generated */ + + +/* CLOCK_EVENTS_PLLSTARTED: PLL started */ + #define CLOCK_EVENTS_PLLSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PLLSTARTED register. */ + +/* EVENTS_PLLSTARTED @Bit 0 : PLL started */ + #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Pos (0UL) /*!< Position of EVENTS_PLLSTARTED field. */ + #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Msk (0x1UL << CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Pos) /*!< Bit mask + of EVENTS_PLLSTARTED field.*/ + #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_PLLSTARTED field. */ + #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_PLLSTARTED field. */ + #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Generated (0x1UL) /*!< Event generated */ + + +/* CLOCK_EVENTS_LFCLKSTARTED: LFCLK source started */ + #define CLOCK_EVENTS_LFCLKSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LFCLKSTARTED register. */ + +/* EVENTS_LFCLKSTARTED @Bit 0 : LFCLK source started */ + #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ + #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< + Bit mask of EVENTS_LFCLKSTARTED field.*/ + #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_LFCLKSTARTED field. */ + #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_LFCLKSTARTED field. */ + #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (0x1UL) /*!< Event generated */ + + +/* CLOCK_EVENTS_DONE: Calibration of LFRC oscillator complete event */ + #define CLOCK_EVENTS_DONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DONE register. */ + +/* EVENTS_DONE @Bit 0 : Calibration of LFRC oscillator complete event */ + #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ + #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ + #define CLOCK_EVENTS_DONE_EVENTS_DONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_DONE field. */ + #define CLOCK_EVENTS_DONE_EVENTS_DONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_DONE field. */ + #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated */ + + +/* CLOCK_EVENTS_XOTUNED: HFXO tuning is done. XOTUNED is generated after TASKS_XOSTART or after TASKS_XOTUNE has completed */ + #define CLOCK_EVENTS_XOTUNED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_XOTUNED register. */ + +/* EVENTS_XOTUNED @Bit 0 : HFXO tuning is done. XOTUNED is generated after TASKS_XOSTART or after TASKS_XOTUNE has completed */ + #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Pos (0UL) /*!< Position of EVENTS_XOTUNED field. */ + #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Msk (0x1UL << CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Pos) /*!< Bit mask of + EVENTS_XOTUNED field.*/ + #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Min (0x0UL) /*!< Min enumerator value of EVENTS_XOTUNED field. */ + #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Max (0x1UL) /*!< Max enumerator value of EVENTS_XOTUNED field. */ + #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_NotGenerated (0x0UL) /*!< Event not generated */ + #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Generated (0x1UL) /*!< Event generated */ + + +/* CLOCK_EVENTS_XOTUNEERROR: HFXO quality issue detected, XOTUNE is needed */ + #define CLOCK_EVENTS_XOTUNEERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_XOTUNEERROR register. */ + +/* EVENTS_XOTUNEERROR @Bit 0 : HFXO quality issue detected, XOTUNE is needed */ + #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Pos (0UL) /*!< Position of EVENTS_XOTUNEERROR field. */ + #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Msk (0x1UL << CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Pos) /*!< Bit + mask of EVENTS_XOTUNEERROR field.*/ + #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_XOTUNEERROR field. */ + #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_XOTUNEERROR field. */ + #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Generated (0x1UL) /*!< Event generated */ + + +/* CLOCK_EVENTS_XOTUNEFAILED: HFXO tuning could not be completed */ + #define CLOCK_EVENTS_XOTUNEFAILED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_XOTUNEFAILED register. */ + +/* EVENTS_XOTUNEFAILED @Bit 0 : HFXO tuning could not be completed */ + #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Pos (0UL) /*!< Position of EVENTS_XOTUNEFAILED field. */ + #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Msk (0x1UL << CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Pos) /*!< + Bit mask of EVENTS_XOTUNEFAILED field.*/ + #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Min (0x0UL) /*!< Min enumerator value of EVENTS_XOTUNEFAILED field. */ + #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Max (0x1UL) /*!< Max enumerator value of EVENTS_XOTUNEFAILED field. */ + #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_NotGenerated (0x0UL) /*!< Event not generated */ + #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Generated (0x1UL) /*!< Event generated */ + + +/* CLOCK_EVENTS_XO24MSTARTED: XO24M started */ + #define CLOCK_EVENTS_XO24MSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_XO24MSTARTED register. */ + +/* EVENTS_XO24MSTARTED @Bit 0 : XO24M started */ + #define CLOCK_EVENTS_XO24MSTARTED_EVENTS_XO24MSTARTED_Pos (0UL) /*!< Position of EVENTS_XO24MSTARTED field. */ + #define CLOCK_EVENTS_XO24MSTARTED_EVENTS_XO24MSTARTED_Msk (0x1UL << CLOCK_EVENTS_XO24MSTARTED_EVENTS_XO24MSTARTED_Pos) /*!< + Bit mask of EVENTS_XO24MSTARTED field.*/ + #define CLOCK_EVENTS_XO24MSTARTED_EVENTS_XO24MSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_XO24MSTARTED field. */ + #define CLOCK_EVENTS_XO24MSTARTED_EVENTS_XO24MSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_XO24MSTARTED field. */ + #define CLOCK_EVENTS_XO24MSTARTED_EVENTS_XO24MSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define CLOCK_EVENTS_XO24MSTARTED_EVENTS_XO24MSTARTED_Generated (0x1UL) /*!< Event generated */ + + +/* CLOCK_PUBLISH_XOSTARTED: Publish configuration for event XOSTARTED */ + #define CLOCK_PUBLISH_XOSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_XOSTARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event XOSTARTED will publish to */ + #define CLOCK_PUBLISH_XOSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_PUBLISH_XOSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_XOSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_PUBLISH_XOSTARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_PUBLISH_XOSTARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_PUBLISH_XOSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_PUBLISH_XOSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_XOSTARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_PUBLISH_XOSTARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_PUBLISH_XOSTARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_PUBLISH_XOSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CLOCK_PUBLISH_XOSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CLOCK_PUBLISH_PLLSTARTED: Publish configuration for event PLLSTARTED */ + #define CLOCK_PUBLISH_PLLSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PLLSTARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PLLSTARTED will publish to */ + #define CLOCK_PUBLISH_PLLSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_PUBLISH_PLLSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_PLLSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_PUBLISH_PLLSTARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_PUBLISH_PLLSTARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_PUBLISH_PLLSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_PUBLISH_PLLSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_PLLSTARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_PUBLISH_PLLSTARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_PUBLISH_PLLSTARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_PUBLISH_PLLSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CLOCK_PUBLISH_PLLSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CLOCK_PUBLISH_LFCLKSTARTED: Publish configuration for event LFCLKSTARTED */ + #define CLOCK_PUBLISH_LFCLKSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LFCLKSTARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event LFCLKSTARTED will publish to */ + #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CLOCK_PUBLISH_DONE: Publish configuration for event DONE */ + #define CLOCK_PUBLISH_DONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DONE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DONE will publish to */ + #define CLOCK_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_PUBLISH_DONE_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_PUBLISH_DONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_PUBLISH_DONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_PUBLISH_DONE_EN_Msk (0x1UL << CLOCK_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_PUBLISH_DONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_PUBLISH_DONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_PUBLISH_DONE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CLOCK_PUBLISH_DONE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CLOCK_PUBLISH_XOTUNED: Publish configuration for event XOTUNED */ + #define CLOCK_PUBLISH_XOTUNED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_XOTUNED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event XOTUNED will publish to */ + #define CLOCK_PUBLISH_XOTUNED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_PUBLISH_XOTUNED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_XOTUNED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_PUBLISH_XOTUNED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_PUBLISH_XOTUNED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_PUBLISH_XOTUNED_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_PUBLISH_XOTUNED_EN_Msk (0x1UL << CLOCK_PUBLISH_XOTUNED_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_PUBLISH_XOTUNED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_PUBLISH_XOTUNED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_PUBLISH_XOTUNED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CLOCK_PUBLISH_XOTUNED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CLOCK_PUBLISH_XOTUNEERROR: Publish configuration for event XOTUNEERROR */ + #define CLOCK_PUBLISH_XOTUNEERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_XOTUNEERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event XOTUNEERROR will publish to */ + #define CLOCK_PUBLISH_XOTUNEERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_PUBLISH_XOTUNEERROR_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_XOTUNEERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_PUBLISH_XOTUNEERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_PUBLISH_XOTUNEERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_PUBLISH_XOTUNEERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_PUBLISH_XOTUNEERROR_EN_Msk (0x1UL << CLOCK_PUBLISH_XOTUNEERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_PUBLISH_XOTUNEERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_PUBLISH_XOTUNEERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_PUBLISH_XOTUNEERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CLOCK_PUBLISH_XOTUNEERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CLOCK_PUBLISH_XOTUNEFAILED: Publish configuration for event XOTUNEFAILED */ + #define CLOCK_PUBLISH_XOTUNEFAILED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_XOTUNEFAILED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event XOTUNEFAILED will publish to */ + #define CLOCK_PUBLISH_XOTUNEFAILED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_PUBLISH_XOTUNEFAILED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_XOTUNEFAILED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_PUBLISH_XOTUNEFAILED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_PUBLISH_XOTUNEFAILED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_PUBLISH_XOTUNEFAILED_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_PUBLISH_XOTUNEFAILED_EN_Msk (0x1UL << CLOCK_PUBLISH_XOTUNEFAILED_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_PUBLISH_XOTUNEFAILED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_PUBLISH_XOTUNEFAILED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_PUBLISH_XOTUNEFAILED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CLOCK_PUBLISH_XOTUNEFAILED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CLOCK_PUBLISH_XO24MSTARTED: Publish configuration for event XO24MSTARTED */ + #define CLOCK_PUBLISH_XO24MSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_XO24MSTARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event XO24MSTARTED will publish to */ + #define CLOCK_PUBLISH_XO24MSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CLOCK_PUBLISH_XO24MSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_XO24MSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CLOCK_PUBLISH_XO24MSTARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CLOCK_PUBLISH_XO24MSTARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CLOCK_PUBLISH_XO24MSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define CLOCK_PUBLISH_XO24MSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_XO24MSTARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define CLOCK_PUBLISH_XO24MSTARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CLOCK_PUBLISH_XO24MSTARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CLOCK_PUBLISH_XO24MSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CLOCK_PUBLISH_XO24MSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CLOCK_INTEN: Enable or disable interrupt */ + #define CLOCK_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* XOSTARTED @Bit 0 : Enable or disable interrupt for event XOSTARTED */ + #define CLOCK_INTEN_XOSTARTED_Pos (0UL) /*!< Position of XOSTARTED field. */ + #define CLOCK_INTEN_XOSTARTED_Msk (0x1UL << CLOCK_INTEN_XOSTARTED_Pos) /*!< Bit mask of XOSTARTED field. */ + #define CLOCK_INTEN_XOSTARTED_Min (0x0UL) /*!< Min enumerator value of XOSTARTED field. */ + #define CLOCK_INTEN_XOSTARTED_Max (0x1UL) /*!< Max enumerator value of XOSTARTED field. */ + #define CLOCK_INTEN_XOSTARTED_Disabled (0x0UL) /*!< Disable */ + #define CLOCK_INTEN_XOSTARTED_Enabled (0x1UL) /*!< Enable */ + +/* PLLSTARTED @Bit 1 : Enable or disable interrupt for event PLLSTARTED */ + #define CLOCK_INTEN_PLLSTARTED_Pos (1UL) /*!< Position of PLLSTARTED field. */ + #define CLOCK_INTEN_PLLSTARTED_Msk (0x1UL << CLOCK_INTEN_PLLSTARTED_Pos) /*!< Bit mask of PLLSTARTED field. */ + #define CLOCK_INTEN_PLLSTARTED_Min (0x0UL) /*!< Min enumerator value of PLLSTARTED field. */ + #define CLOCK_INTEN_PLLSTARTED_Max (0x1UL) /*!< Max enumerator value of PLLSTARTED field. */ + #define CLOCK_INTEN_PLLSTARTED_Disabled (0x0UL) /*!< Disable */ + #define CLOCK_INTEN_PLLSTARTED_Enabled (0x1UL) /*!< Enable */ + +/* LFCLKSTARTED @Bit 2 : Enable or disable interrupt for event LFCLKSTARTED */ + #define CLOCK_INTEN_LFCLKSTARTED_Pos (2UL) /*!< Position of LFCLKSTARTED field. */ + #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ + #define CLOCK_INTEN_LFCLKSTARTED_Min (0x0UL) /*!< Min enumerator value of LFCLKSTARTED field. */ + #define CLOCK_INTEN_LFCLKSTARTED_Max (0x1UL) /*!< Max enumerator value of LFCLKSTARTED field. */ + #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0x0UL) /*!< Disable */ + #define CLOCK_INTEN_LFCLKSTARTED_Enabled (0x1UL) /*!< Enable */ + +/* DONE @Bit 3 : Enable or disable interrupt for event DONE */ + #define CLOCK_INTEN_DONE_Pos (3UL) /*!< Position of DONE field. */ + #define CLOCK_INTEN_DONE_Msk (0x1UL << CLOCK_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ + #define CLOCK_INTEN_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define CLOCK_INTEN_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define CLOCK_INTEN_DONE_Disabled (0x0UL) /*!< Disable */ + #define CLOCK_INTEN_DONE_Enabled (0x1UL) /*!< Enable */ + +/* XOTUNED @Bit 4 : Enable or disable interrupt for event XOTUNED */ + #define CLOCK_INTEN_XOTUNED_Pos (4UL) /*!< Position of XOTUNED field. */ + #define CLOCK_INTEN_XOTUNED_Msk (0x1UL << CLOCK_INTEN_XOTUNED_Pos) /*!< Bit mask of XOTUNED field. */ + #define CLOCK_INTEN_XOTUNED_Min (0x0UL) /*!< Min enumerator value of XOTUNED field. */ + #define CLOCK_INTEN_XOTUNED_Max (0x1UL) /*!< Max enumerator value of XOTUNED field. */ + #define CLOCK_INTEN_XOTUNED_Disabled (0x0UL) /*!< Disable */ + #define CLOCK_INTEN_XOTUNED_Enabled (0x1UL) /*!< Enable */ + +/* XOTUNEERROR @Bit 5 : Enable or disable interrupt for event XOTUNEERROR */ + #define CLOCK_INTEN_XOTUNEERROR_Pos (5UL) /*!< Position of XOTUNEERROR field. */ + #define CLOCK_INTEN_XOTUNEERROR_Msk (0x1UL << CLOCK_INTEN_XOTUNEERROR_Pos) /*!< Bit mask of XOTUNEERROR field. */ + #define CLOCK_INTEN_XOTUNEERROR_Min (0x0UL) /*!< Min enumerator value of XOTUNEERROR field. */ + #define CLOCK_INTEN_XOTUNEERROR_Max (0x1UL) /*!< Max enumerator value of XOTUNEERROR field. */ + #define CLOCK_INTEN_XOTUNEERROR_Disabled (0x0UL) /*!< Disable */ + #define CLOCK_INTEN_XOTUNEERROR_Enabled (0x1UL) /*!< Enable */ + +/* XOTUNEFAILED @Bit 6 : Enable or disable interrupt for event XOTUNEFAILED */ + #define CLOCK_INTEN_XOTUNEFAILED_Pos (6UL) /*!< Position of XOTUNEFAILED field. */ + #define CLOCK_INTEN_XOTUNEFAILED_Msk (0x1UL << CLOCK_INTEN_XOTUNEFAILED_Pos) /*!< Bit mask of XOTUNEFAILED field. */ + #define CLOCK_INTEN_XOTUNEFAILED_Min (0x0UL) /*!< Min enumerator value of XOTUNEFAILED field. */ + #define CLOCK_INTEN_XOTUNEFAILED_Max (0x1UL) /*!< Max enumerator value of XOTUNEFAILED field. */ + #define CLOCK_INTEN_XOTUNEFAILED_Disabled (0x0UL) /*!< Disable */ + #define CLOCK_INTEN_XOTUNEFAILED_Enabled (0x1UL) /*!< Enable */ + +/* XO24MSTARTED @Bit 7 : Enable or disable interrupt for event XO24MSTARTED */ + #define CLOCK_INTEN_XO24MSTARTED_Pos (7UL) /*!< Position of XO24MSTARTED field. */ + #define CLOCK_INTEN_XO24MSTARTED_Msk (0x1UL << CLOCK_INTEN_XO24MSTARTED_Pos) /*!< Bit mask of XO24MSTARTED field. */ + #define CLOCK_INTEN_XO24MSTARTED_Min (0x0UL) /*!< Min enumerator value of XO24MSTARTED field. */ + #define CLOCK_INTEN_XO24MSTARTED_Max (0x1UL) /*!< Max enumerator value of XO24MSTARTED field. */ + #define CLOCK_INTEN_XO24MSTARTED_Disabled (0x0UL) /*!< Disable */ + #define CLOCK_INTEN_XO24MSTARTED_Enabled (0x1UL) /*!< Enable */ + + +/* CLOCK_INTENSET: Enable interrupt */ + #define CLOCK_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* XOSTARTED @Bit 0 : Write '1' to enable interrupt for event XOSTARTED */ + #define CLOCK_INTENSET_XOSTARTED_Pos (0UL) /*!< Position of XOSTARTED field. */ + #define CLOCK_INTENSET_XOSTARTED_Msk (0x1UL << CLOCK_INTENSET_XOSTARTED_Pos) /*!< Bit mask of XOSTARTED field. */ + #define CLOCK_INTENSET_XOSTARTED_Min (0x0UL) /*!< Min enumerator value of XOSTARTED field. */ + #define CLOCK_INTENSET_XOSTARTED_Max (0x1UL) /*!< Max enumerator value of XOSTARTED field. */ + #define CLOCK_INTENSET_XOSTARTED_Set (0x1UL) /*!< Enable */ + #define CLOCK_INTENSET_XOSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENSET_XOSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PLLSTARTED @Bit 1 : Write '1' to enable interrupt for event PLLSTARTED */ + #define CLOCK_INTENSET_PLLSTARTED_Pos (1UL) /*!< Position of PLLSTARTED field. */ + #define CLOCK_INTENSET_PLLSTARTED_Msk (0x1UL << CLOCK_INTENSET_PLLSTARTED_Pos) /*!< Bit mask of PLLSTARTED field. */ + #define CLOCK_INTENSET_PLLSTARTED_Min (0x0UL) /*!< Min enumerator value of PLLSTARTED field. */ + #define CLOCK_INTENSET_PLLSTARTED_Max (0x1UL) /*!< Max enumerator value of PLLSTARTED field. */ + #define CLOCK_INTENSET_PLLSTARTED_Set (0x1UL) /*!< Enable */ + #define CLOCK_INTENSET_PLLSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENSET_PLLSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LFCLKSTARTED @Bit 2 : Write '1' to enable interrupt for event LFCLKSTARTED */ + #define CLOCK_INTENSET_LFCLKSTARTED_Pos (2UL) /*!< Position of LFCLKSTARTED field. */ + #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ + #define CLOCK_INTENSET_LFCLKSTARTED_Min (0x0UL) /*!< Min enumerator value of LFCLKSTARTED field. */ + #define CLOCK_INTENSET_LFCLKSTARTED_Max (0x1UL) /*!< Max enumerator value of LFCLKSTARTED field. */ + #define CLOCK_INTENSET_LFCLKSTARTED_Set (0x1UL) /*!< Enable */ + #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DONE @Bit 3 : Write '1' to enable interrupt for event DONE */ + #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ + #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ + #define CLOCK_INTENSET_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define CLOCK_INTENSET_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define CLOCK_INTENSET_DONE_Set (0x1UL) /*!< Enable */ + #define CLOCK_INTENSET_DONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENSET_DONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* XOTUNED @Bit 4 : Write '1' to enable interrupt for event XOTUNED */ + #define CLOCK_INTENSET_XOTUNED_Pos (4UL) /*!< Position of XOTUNED field. */ + #define CLOCK_INTENSET_XOTUNED_Msk (0x1UL << CLOCK_INTENSET_XOTUNED_Pos) /*!< Bit mask of XOTUNED field. */ + #define CLOCK_INTENSET_XOTUNED_Min (0x0UL) /*!< Min enumerator value of XOTUNED field. */ + #define CLOCK_INTENSET_XOTUNED_Max (0x1UL) /*!< Max enumerator value of XOTUNED field. */ + #define CLOCK_INTENSET_XOTUNED_Set (0x1UL) /*!< Enable */ + #define CLOCK_INTENSET_XOTUNED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENSET_XOTUNED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* XOTUNEERROR @Bit 5 : Write '1' to enable interrupt for event XOTUNEERROR */ + #define CLOCK_INTENSET_XOTUNEERROR_Pos (5UL) /*!< Position of XOTUNEERROR field. */ + #define CLOCK_INTENSET_XOTUNEERROR_Msk (0x1UL << CLOCK_INTENSET_XOTUNEERROR_Pos) /*!< Bit mask of XOTUNEERROR field. */ + #define CLOCK_INTENSET_XOTUNEERROR_Min (0x0UL) /*!< Min enumerator value of XOTUNEERROR field. */ + #define CLOCK_INTENSET_XOTUNEERROR_Max (0x1UL) /*!< Max enumerator value of XOTUNEERROR field. */ + #define CLOCK_INTENSET_XOTUNEERROR_Set (0x1UL) /*!< Enable */ + #define CLOCK_INTENSET_XOTUNEERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENSET_XOTUNEERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* XOTUNEFAILED @Bit 6 : Write '1' to enable interrupt for event XOTUNEFAILED */ + #define CLOCK_INTENSET_XOTUNEFAILED_Pos (6UL) /*!< Position of XOTUNEFAILED field. */ + #define CLOCK_INTENSET_XOTUNEFAILED_Msk (0x1UL << CLOCK_INTENSET_XOTUNEFAILED_Pos) /*!< Bit mask of XOTUNEFAILED field. */ + #define CLOCK_INTENSET_XOTUNEFAILED_Min (0x0UL) /*!< Min enumerator value of XOTUNEFAILED field. */ + #define CLOCK_INTENSET_XOTUNEFAILED_Max (0x1UL) /*!< Max enumerator value of XOTUNEFAILED field. */ + #define CLOCK_INTENSET_XOTUNEFAILED_Set (0x1UL) /*!< Enable */ + #define CLOCK_INTENSET_XOTUNEFAILED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENSET_XOTUNEFAILED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* XO24MSTARTED @Bit 7 : Write '1' to enable interrupt for event XO24MSTARTED */ + #define CLOCK_INTENSET_XO24MSTARTED_Pos (7UL) /*!< Position of XO24MSTARTED field. */ + #define CLOCK_INTENSET_XO24MSTARTED_Msk (0x1UL << CLOCK_INTENSET_XO24MSTARTED_Pos) /*!< Bit mask of XO24MSTARTED field. */ + #define CLOCK_INTENSET_XO24MSTARTED_Min (0x0UL) /*!< Min enumerator value of XO24MSTARTED field. */ + #define CLOCK_INTENSET_XO24MSTARTED_Max (0x1UL) /*!< Max enumerator value of XO24MSTARTED field. */ + #define CLOCK_INTENSET_XO24MSTARTED_Set (0x1UL) /*!< Enable */ + #define CLOCK_INTENSET_XO24MSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENSET_XO24MSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CLOCK_INTENCLR: Disable interrupt */ + #define CLOCK_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* XOSTARTED @Bit 0 : Write '1' to disable interrupt for event XOSTARTED */ + #define CLOCK_INTENCLR_XOSTARTED_Pos (0UL) /*!< Position of XOSTARTED field. */ + #define CLOCK_INTENCLR_XOSTARTED_Msk (0x1UL << CLOCK_INTENCLR_XOSTARTED_Pos) /*!< Bit mask of XOSTARTED field. */ + #define CLOCK_INTENCLR_XOSTARTED_Min (0x0UL) /*!< Min enumerator value of XOSTARTED field. */ + #define CLOCK_INTENCLR_XOSTARTED_Max (0x1UL) /*!< Max enumerator value of XOSTARTED field. */ + #define CLOCK_INTENCLR_XOSTARTED_Clear (0x1UL) /*!< Disable */ + #define CLOCK_INTENCLR_XOSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENCLR_XOSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PLLSTARTED @Bit 1 : Write '1' to disable interrupt for event PLLSTARTED */ + #define CLOCK_INTENCLR_PLLSTARTED_Pos (1UL) /*!< Position of PLLSTARTED field. */ + #define CLOCK_INTENCLR_PLLSTARTED_Msk (0x1UL << CLOCK_INTENCLR_PLLSTARTED_Pos) /*!< Bit mask of PLLSTARTED field. */ + #define CLOCK_INTENCLR_PLLSTARTED_Min (0x0UL) /*!< Min enumerator value of PLLSTARTED field. */ + #define CLOCK_INTENCLR_PLLSTARTED_Max (0x1UL) /*!< Max enumerator value of PLLSTARTED field. */ + #define CLOCK_INTENCLR_PLLSTARTED_Clear (0x1UL) /*!< Disable */ + #define CLOCK_INTENCLR_PLLSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENCLR_PLLSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LFCLKSTARTED @Bit 2 : Write '1' to disable interrupt for event LFCLKSTARTED */ + #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (2UL) /*!< Position of LFCLKSTARTED field. */ + #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ + #define CLOCK_INTENCLR_LFCLKSTARTED_Min (0x0UL) /*!< Min enumerator value of LFCLKSTARTED field. */ + #define CLOCK_INTENCLR_LFCLKSTARTED_Max (0x1UL) /*!< Max enumerator value of LFCLKSTARTED field. */ + #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (0x1UL) /*!< Disable */ + #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DONE @Bit 3 : Write '1' to disable interrupt for event DONE */ + #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ + #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ + #define CLOCK_INTENCLR_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define CLOCK_INTENCLR_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define CLOCK_INTENCLR_DONE_Clear (0x1UL) /*!< Disable */ + #define CLOCK_INTENCLR_DONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENCLR_DONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* XOTUNED @Bit 4 : Write '1' to disable interrupt for event XOTUNED */ + #define CLOCK_INTENCLR_XOTUNED_Pos (4UL) /*!< Position of XOTUNED field. */ + #define CLOCK_INTENCLR_XOTUNED_Msk (0x1UL << CLOCK_INTENCLR_XOTUNED_Pos) /*!< Bit mask of XOTUNED field. */ + #define CLOCK_INTENCLR_XOTUNED_Min (0x0UL) /*!< Min enumerator value of XOTUNED field. */ + #define CLOCK_INTENCLR_XOTUNED_Max (0x1UL) /*!< Max enumerator value of XOTUNED field. */ + #define CLOCK_INTENCLR_XOTUNED_Clear (0x1UL) /*!< Disable */ + #define CLOCK_INTENCLR_XOTUNED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENCLR_XOTUNED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* XOTUNEERROR @Bit 5 : Write '1' to disable interrupt for event XOTUNEERROR */ + #define CLOCK_INTENCLR_XOTUNEERROR_Pos (5UL) /*!< Position of XOTUNEERROR field. */ + #define CLOCK_INTENCLR_XOTUNEERROR_Msk (0x1UL << CLOCK_INTENCLR_XOTUNEERROR_Pos) /*!< Bit mask of XOTUNEERROR field. */ + #define CLOCK_INTENCLR_XOTUNEERROR_Min (0x0UL) /*!< Min enumerator value of XOTUNEERROR field. */ + #define CLOCK_INTENCLR_XOTUNEERROR_Max (0x1UL) /*!< Max enumerator value of XOTUNEERROR field. */ + #define CLOCK_INTENCLR_XOTUNEERROR_Clear (0x1UL) /*!< Disable */ + #define CLOCK_INTENCLR_XOTUNEERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENCLR_XOTUNEERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* XOTUNEFAILED @Bit 6 : Write '1' to disable interrupt for event XOTUNEFAILED */ + #define CLOCK_INTENCLR_XOTUNEFAILED_Pos (6UL) /*!< Position of XOTUNEFAILED field. */ + #define CLOCK_INTENCLR_XOTUNEFAILED_Msk (0x1UL << CLOCK_INTENCLR_XOTUNEFAILED_Pos) /*!< Bit mask of XOTUNEFAILED field. */ + #define CLOCK_INTENCLR_XOTUNEFAILED_Min (0x0UL) /*!< Min enumerator value of XOTUNEFAILED field. */ + #define CLOCK_INTENCLR_XOTUNEFAILED_Max (0x1UL) /*!< Max enumerator value of XOTUNEFAILED field. */ + #define CLOCK_INTENCLR_XOTUNEFAILED_Clear (0x1UL) /*!< Disable */ + #define CLOCK_INTENCLR_XOTUNEFAILED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENCLR_XOTUNEFAILED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* XO24MSTARTED @Bit 7 : Write '1' to disable interrupt for event XO24MSTARTED */ + #define CLOCK_INTENCLR_XO24MSTARTED_Pos (7UL) /*!< Position of XO24MSTARTED field. */ + #define CLOCK_INTENCLR_XO24MSTARTED_Msk (0x1UL << CLOCK_INTENCLR_XO24MSTARTED_Pos) /*!< Bit mask of XO24MSTARTED field. */ + #define CLOCK_INTENCLR_XO24MSTARTED_Min (0x0UL) /*!< Min enumerator value of XO24MSTARTED field. */ + #define CLOCK_INTENCLR_XO24MSTARTED_Max (0x1UL) /*!< Max enumerator value of XO24MSTARTED field. */ + #define CLOCK_INTENCLR_XO24MSTARTED_Clear (0x1UL) /*!< Disable */ + #define CLOCK_INTENCLR_XO24MSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define CLOCK_INTENCLR_XO24MSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CLOCK_INTPEND: Pending interrupts */ + #define CLOCK_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* XOSTARTED @Bit 0 : Read pending status of interrupt for event XOSTARTED */ + #define CLOCK_INTPEND_XOSTARTED_Pos (0UL) /*!< Position of XOSTARTED field. */ + #define CLOCK_INTPEND_XOSTARTED_Msk (0x1UL << CLOCK_INTPEND_XOSTARTED_Pos) /*!< Bit mask of XOSTARTED field. */ + #define CLOCK_INTPEND_XOSTARTED_Min (0x0UL) /*!< Min enumerator value of XOSTARTED field. */ + #define CLOCK_INTPEND_XOSTARTED_Max (0x1UL) /*!< Max enumerator value of XOSTARTED field. */ + #define CLOCK_INTPEND_XOSTARTED_NotPending (0x0UL) /*!< Read: Not pending */ + #define CLOCK_INTPEND_XOSTARTED_Pending (0x1UL) /*!< Read: Pending */ + +/* PLLSTARTED @Bit 1 : Read pending status of interrupt for event PLLSTARTED */ + #define CLOCK_INTPEND_PLLSTARTED_Pos (1UL) /*!< Position of PLLSTARTED field. */ + #define CLOCK_INTPEND_PLLSTARTED_Msk (0x1UL << CLOCK_INTPEND_PLLSTARTED_Pos) /*!< Bit mask of PLLSTARTED field. */ + #define CLOCK_INTPEND_PLLSTARTED_Min (0x0UL) /*!< Min enumerator value of PLLSTARTED field. */ + #define CLOCK_INTPEND_PLLSTARTED_Max (0x1UL) /*!< Max enumerator value of PLLSTARTED field. */ + #define CLOCK_INTPEND_PLLSTARTED_NotPending (0x0UL) /*!< Read: Not pending */ + #define CLOCK_INTPEND_PLLSTARTED_Pending (0x1UL) /*!< Read: Pending */ + +/* LFCLKSTARTED @Bit 2 : Read pending status of interrupt for event LFCLKSTARTED */ + #define CLOCK_INTPEND_LFCLKSTARTED_Pos (2UL) /*!< Position of LFCLKSTARTED field. */ + #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ + #define CLOCK_INTPEND_LFCLKSTARTED_Min (0x0UL) /*!< Min enumerator value of LFCLKSTARTED field. */ + #define CLOCK_INTPEND_LFCLKSTARTED_Max (0x1UL) /*!< Max enumerator value of LFCLKSTARTED field. */ + #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0x0UL) /*!< Read: Not pending */ + #define CLOCK_INTPEND_LFCLKSTARTED_Pending (0x1UL) /*!< Read: Pending */ + +/* DONE @Bit 3 : Read pending status of interrupt for event DONE */ + #define CLOCK_INTPEND_DONE_Pos (3UL) /*!< Position of DONE field. */ + #define CLOCK_INTPEND_DONE_Msk (0x1UL << CLOCK_INTPEND_DONE_Pos) /*!< Bit mask of DONE field. */ + #define CLOCK_INTPEND_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define CLOCK_INTPEND_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define CLOCK_INTPEND_DONE_NotPending (0x0UL) /*!< Read: Not pending */ + #define CLOCK_INTPEND_DONE_Pending (0x1UL) /*!< Read: Pending */ + +/* XOTUNED @Bit 4 : Read pending status of interrupt for event XOTUNED */ + #define CLOCK_INTPEND_XOTUNED_Pos (4UL) /*!< Position of XOTUNED field. */ + #define CLOCK_INTPEND_XOTUNED_Msk (0x1UL << CLOCK_INTPEND_XOTUNED_Pos) /*!< Bit mask of XOTUNED field. */ + #define CLOCK_INTPEND_XOTUNED_Min (0x0UL) /*!< Min enumerator value of XOTUNED field. */ + #define CLOCK_INTPEND_XOTUNED_Max (0x1UL) /*!< Max enumerator value of XOTUNED field. */ + #define CLOCK_INTPEND_XOTUNED_NotPending (0x0UL) /*!< Read: Not pending */ + #define CLOCK_INTPEND_XOTUNED_Pending (0x1UL) /*!< Read: Pending */ + +/* XOTUNEERROR @Bit 5 : Read pending status of interrupt for event XOTUNEERROR */ + #define CLOCK_INTPEND_XOTUNEERROR_Pos (5UL) /*!< Position of XOTUNEERROR field. */ + #define CLOCK_INTPEND_XOTUNEERROR_Msk (0x1UL << CLOCK_INTPEND_XOTUNEERROR_Pos) /*!< Bit mask of XOTUNEERROR field. */ + #define CLOCK_INTPEND_XOTUNEERROR_Min (0x0UL) /*!< Min enumerator value of XOTUNEERROR field. */ + #define CLOCK_INTPEND_XOTUNEERROR_Max (0x1UL) /*!< Max enumerator value of XOTUNEERROR field. */ + #define CLOCK_INTPEND_XOTUNEERROR_NotPending (0x0UL) /*!< Read: Not pending */ + #define CLOCK_INTPEND_XOTUNEERROR_Pending (0x1UL) /*!< Read: Pending */ + +/* XOTUNEFAILED @Bit 6 : Read pending status of interrupt for event XOTUNEFAILED */ + #define CLOCK_INTPEND_XOTUNEFAILED_Pos (6UL) /*!< Position of XOTUNEFAILED field. */ + #define CLOCK_INTPEND_XOTUNEFAILED_Msk (0x1UL << CLOCK_INTPEND_XOTUNEFAILED_Pos) /*!< Bit mask of XOTUNEFAILED field. */ + #define CLOCK_INTPEND_XOTUNEFAILED_Min (0x0UL) /*!< Min enumerator value of XOTUNEFAILED field. */ + #define CLOCK_INTPEND_XOTUNEFAILED_Max (0x1UL) /*!< Max enumerator value of XOTUNEFAILED field. */ + #define CLOCK_INTPEND_XOTUNEFAILED_NotPending (0x0UL) /*!< Read: Not pending */ + #define CLOCK_INTPEND_XOTUNEFAILED_Pending (0x1UL) /*!< Read: Pending */ + +/* XO24MSTARTED @Bit 7 : Read pending status of interrupt for event XO24MSTARTED */ + #define CLOCK_INTPEND_XO24MSTARTED_Pos (7UL) /*!< Position of XO24MSTARTED field. */ + #define CLOCK_INTPEND_XO24MSTARTED_Msk (0x1UL << CLOCK_INTPEND_XO24MSTARTED_Pos) /*!< Bit mask of XO24MSTARTED field. */ + #define CLOCK_INTPEND_XO24MSTARTED_Min (0x0UL) /*!< Min enumerator value of XO24MSTARTED field. */ + #define CLOCK_INTPEND_XO24MSTARTED_Max (0x1UL) /*!< Max enumerator value of XO24MSTARTED field. */ + #define CLOCK_INTPEND_XO24MSTARTED_NotPending (0x0UL) /*!< Read: Not pending */ + #define CLOCK_INTPEND_XO24MSTARTED_Pending (0x1UL) /*!< Read: Pending */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct COMP ======================================================= */ +/** + * @brief Comparator + */ + typedef struct { /*!< COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value. This task requires that COMP + has been started by the START Task.*/ + __IM uint32_t RESERVED[29]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE */ + __IM uint32_t RESERVED1[29]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED2[28]; + __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ + __IOM uint32_t PUBLISH_DOWN; /*!< (@ 0x00000184) Publish configuration for event DOWN */ + __IOM uint32_t PUBLISH_UP; /*!< (@ 0x00000188) Publish configuration for event UP */ + __IOM uint32_t PUBLISH_CROSS; /*!< (@ 0x0000018C) Publish configuration for event CROSS */ + __IM uint32_t RESERVED3[28]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED5[60]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED6[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED7[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ + __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ + } NRF_COMP_Type; /*!< Size = 1344 (0x540) */ + +/* COMP_TASKS_START: Start comparator */ + #define COMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start comparator */ + #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define COMP_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define COMP_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define COMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* COMP_TASKS_STOP: Stop comparator */ + #define COMP_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop comparator */ + #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define COMP_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define COMP_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define COMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* COMP_TASKS_SAMPLE: Sample comparator value. This task requires that COMP has been started by the START Task. */ + #define COMP_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register. */ + +/* TASKS_SAMPLE @Bit 0 : Sample comparator value. This task requires that COMP has been started by the START Task. */ + #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ + #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field.*/ + #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field. */ + #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field. */ + #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */ + + +/* COMP_SUBSCRIBE_START: Subscribe configuration for task START */ + #define COMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define COMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_SUBSCRIBE_START_EN_Msk (0x1UL << COMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define COMP_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* COMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define COMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define COMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << COMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define COMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* COMP_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */ + #define COMP_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */ + #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << COMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* COMP_EVENTS_READY: COMP is ready and output is valid */ + #define COMP_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register. */ + +/* EVENTS_READY @Bit 0 : COMP is ready and output is valid */ + #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ + #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field.*/ + #define COMP_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field. */ + #define COMP_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field. */ + #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define COMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */ + + +/* COMP_EVENTS_DOWN: Downward crossing */ + #define COMP_EVENTS_DOWN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DOWN register. */ + +/* EVENTS_DOWN @Bit 0 : Downward crossing */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_Min (0x0UL) /*!< Min enumerator value of EVENTS_DOWN field. */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_Max (0x1UL) /*!< Max enumerator value of EVENTS_DOWN field. */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated */ + + +/* COMP_EVENTS_UP: Upward crossing */ + #define COMP_EVENTS_UP_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_UP register. */ + +/* EVENTS_UP @Bit 0 : Upward crossing */ + #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ + #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ + #define COMP_EVENTS_UP_EVENTS_UP_Min (0x0UL) /*!< Min enumerator value of EVENTS_UP field. */ + #define COMP_EVENTS_UP_EVENTS_UP_Max (0x1UL) /*!< Max enumerator value of EVENTS_UP field. */ + #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated */ + #define COMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated */ + + +/* COMP_EVENTS_CROSS: Downward or upward crossing */ + #define COMP_EVENTS_CROSS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CROSS register. */ + +/* EVENTS_CROSS @Bit 0 : Downward or upward crossing */ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field.*/ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_Min (0x0UL) /*!< Min enumerator value of EVENTS_CROSS field. */ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_Max (0x1UL) /*!< Max enumerator value of EVENTS_CROSS field. */ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated */ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated */ + + +/* COMP_PUBLISH_READY: Publish configuration for event READY */ + #define COMP_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define COMP_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << COMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_PUBLISH_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_PUBLISH_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_PUBLISH_READY_EN_Msk (0x1UL << COMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_PUBLISH_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_PUBLISH_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define COMP_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* COMP_PUBLISH_DOWN: Publish configuration for event DOWN */ + #define COMP_PUBLISH_DOWN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DOWN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DOWN will publish to */ + #define COMP_PUBLISH_DOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << COMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_PUBLISH_DOWN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_PUBLISH_DOWN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_PUBLISH_DOWN_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_PUBLISH_DOWN_EN_Msk (0x1UL << COMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_PUBLISH_DOWN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_PUBLISH_DOWN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_PUBLISH_DOWN_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define COMP_PUBLISH_DOWN_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* COMP_PUBLISH_UP: Publish configuration for event UP */ + #define COMP_PUBLISH_UP_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_UP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event UP will publish to */ + #define COMP_PUBLISH_UP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << COMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_PUBLISH_UP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_PUBLISH_UP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_PUBLISH_UP_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_PUBLISH_UP_EN_Msk (0x1UL << COMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_PUBLISH_UP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_PUBLISH_UP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_PUBLISH_UP_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define COMP_PUBLISH_UP_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* COMP_PUBLISH_CROSS: Publish configuration for event CROSS */ + #define COMP_PUBLISH_CROSS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CROSS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CROSS will publish to */ + #define COMP_PUBLISH_CROSS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << COMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_PUBLISH_CROSS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_PUBLISH_CROSS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_PUBLISH_CROSS_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_PUBLISH_CROSS_EN_Msk (0x1UL << COMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_PUBLISH_CROSS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_PUBLISH_CROSS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_PUBLISH_CROSS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define COMP_PUBLISH_CROSS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* COMP_SHORTS: Shortcuts between local events and tasks */ + #define COMP_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* READY_SAMPLE @Bit 0 : Shortcut between event READY and task SAMPLE */ + #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ + #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ + #define COMP_SHORTS_READY_SAMPLE_Min (0x0UL) /*!< Min enumerator value of READY_SAMPLE field. */ + #define COMP_SHORTS_READY_SAMPLE_Max (0x1UL) /*!< Max enumerator value of READY_SAMPLE field. */ + #define COMP_SHORTS_READY_SAMPLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define COMP_SHORTS_READY_SAMPLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* READY_STOP @Bit 1 : Shortcut between event READY and task STOP */ + #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ + #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ + #define COMP_SHORTS_READY_STOP_Min (0x0UL) /*!< Min enumerator value of READY_STOP field. */ + #define COMP_SHORTS_READY_STOP_Max (0x1UL) /*!< Max enumerator value of READY_STOP field. */ + #define COMP_SHORTS_READY_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define COMP_SHORTS_READY_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DOWN_STOP @Bit 2 : Shortcut between event DOWN and task STOP */ + #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ + #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ + #define COMP_SHORTS_DOWN_STOP_Min (0x0UL) /*!< Min enumerator value of DOWN_STOP field. */ + #define COMP_SHORTS_DOWN_STOP_Max (0x1UL) /*!< Max enumerator value of DOWN_STOP field. */ + #define COMP_SHORTS_DOWN_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define COMP_SHORTS_DOWN_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* UP_STOP @Bit 3 : Shortcut between event UP and task STOP */ + #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ + #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ + #define COMP_SHORTS_UP_STOP_Min (0x0UL) /*!< Min enumerator value of UP_STOP field. */ + #define COMP_SHORTS_UP_STOP_Max (0x1UL) /*!< Max enumerator value of UP_STOP field. */ + #define COMP_SHORTS_UP_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define COMP_SHORTS_UP_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* CROSS_STOP @Bit 4 : Shortcut between event CROSS and task STOP */ + #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ + #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ + #define COMP_SHORTS_CROSS_STOP_Min (0x0UL) /*!< Min enumerator value of CROSS_STOP field. */ + #define COMP_SHORTS_CROSS_STOP_Max (0x1UL) /*!< Max enumerator value of CROSS_STOP field. */ + #define COMP_SHORTS_CROSS_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define COMP_SHORTS_CROSS_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* COMP_INTEN: Enable or disable interrupt */ + #define COMP_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* READY @Bit 0 : Enable or disable interrupt for event READY */ + #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ + #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ + #define COMP_INTEN_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define COMP_INTEN_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define COMP_INTEN_READY_Disabled (0x0UL) /*!< Disable */ + #define COMP_INTEN_READY_Enabled (0x1UL) /*!< Enable */ + +/* DOWN @Bit 1 : Enable or disable interrupt for event DOWN */ + #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define COMP_INTEN_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define COMP_INTEN_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define COMP_INTEN_DOWN_Disabled (0x0UL) /*!< Disable */ + #define COMP_INTEN_DOWN_Enabled (0x1UL) /*!< Enable */ + +/* UP @Bit 2 : Enable or disable interrupt for event UP */ + #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ + #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ + #define COMP_INTEN_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define COMP_INTEN_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define COMP_INTEN_UP_Disabled (0x0UL) /*!< Disable */ + #define COMP_INTEN_UP_Enabled (0x1UL) /*!< Enable */ + +/* CROSS @Bit 3 : Enable or disable interrupt for event CROSS */ + #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define COMP_INTEN_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define COMP_INTEN_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define COMP_INTEN_CROSS_Disabled (0x0UL) /*!< Disable */ + #define COMP_INTEN_CROSS_Enabled (0x1UL) /*!< Enable */ + + +/* COMP_INTENSET: Enable interrupt */ + #define COMP_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* READY @Bit 0 : Write '1' to enable interrupt for event READY */ + #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ + #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ + #define COMP_INTENSET_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define COMP_INTENSET_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define COMP_INTENSET_READY_Set (0x1UL) /*!< Enable */ + #define COMP_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DOWN @Bit 1 : Write '1' to enable interrupt for event DOWN */ + #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define COMP_INTENSET_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define COMP_INTENSET_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define COMP_INTENSET_DOWN_Set (0x1UL) /*!< Enable */ + #define COMP_INTENSET_DOWN_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENSET_DOWN_Enabled (0x1UL) /*!< Read: Enabled */ + +/* UP @Bit 2 : Write '1' to enable interrupt for event UP */ + #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ + #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ + #define COMP_INTENSET_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define COMP_INTENSET_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define COMP_INTENSET_UP_Set (0x1UL) /*!< Enable */ + #define COMP_INTENSET_UP_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENSET_UP_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CROSS @Bit 3 : Write '1' to enable interrupt for event CROSS */ + #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define COMP_INTENSET_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define COMP_INTENSET_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define COMP_INTENSET_CROSS_Set (0x1UL) /*!< Enable */ + #define COMP_INTENSET_CROSS_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENSET_CROSS_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* COMP_INTENCLR: Disable interrupt */ + #define COMP_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* READY @Bit 0 : Write '1' to disable interrupt for event READY */ + #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ + #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ + #define COMP_INTENCLR_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define COMP_INTENCLR_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define COMP_INTENCLR_READY_Clear (0x1UL) /*!< Disable */ + #define COMP_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DOWN @Bit 1 : Write '1' to disable interrupt for event DOWN */ + #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define COMP_INTENCLR_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define COMP_INTENCLR_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define COMP_INTENCLR_DOWN_Clear (0x1UL) /*!< Disable */ + #define COMP_INTENCLR_DOWN_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENCLR_DOWN_Enabled (0x1UL) /*!< Read: Enabled */ + +/* UP @Bit 2 : Write '1' to disable interrupt for event UP */ + #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ + #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ + #define COMP_INTENCLR_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define COMP_INTENCLR_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define COMP_INTENCLR_UP_Clear (0x1UL) /*!< Disable */ + #define COMP_INTENCLR_UP_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENCLR_UP_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CROSS @Bit 3 : Write '1' to disable interrupt for event CROSS */ + #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define COMP_INTENCLR_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define COMP_INTENCLR_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define COMP_INTENCLR_CROSS_Clear (0x1UL) /*!< Disable */ + #define COMP_INTENCLR_CROSS_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENCLR_CROSS_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* COMP_INTPEND: Pending interrupts */ + #define COMP_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* READY @Bit 0 : Read pending status of interrupt for event READY */ + #define COMP_INTPEND_READY_Pos (0UL) /*!< Position of READY field. */ + #define COMP_INTPEND_READY_Msk (0x1UL << COMP_INTPEND_READY_Pos) /*!< Bit mask of READY field. */ + #define COMP_INTPEND_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define COMP_INTPEND_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define COMP_INTPEND_READY_NotPending (0x0UL) /*!< Read: Not pending */ + #define COMP_INTPEND_READY_Pending (0x1UL) /*!< Read: Pending */ + +/* DOWN @Bit 1 : Read pending status of interrupt for event DOWN */ + #define COMP_INTPEND_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define COMP_INTPEND_DOWN_Msk (0x1UL << COMP_INTPEND_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define COMP_INTPEND_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define COMP_INTPEND_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define COMP_INTPEND_DOWN_NotPending (0x0UL) /*!< Read: Not pending */ + #define COMP_INTPEND_DOWN_Pending (0x1UL) /*!< Read: Pending */ + +/* UP @Bit 2 : Read pending status of interrupt for event UP */ + #define COMP_INTPEND_UP_Pos (2UL) /*!< Position of UP field. */ + #define COMP_INTPEND_UP_Msk (0x1UL << COMP_INTPEND_UP_Pos) /*!< Bit mask of UP field. */ + #define COMP_INTPEND_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define COMP_INTPEND_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define COMP_INTPEND_UP_NotPending (0x0UL) /*!< Read: Not pending */ + #define COMP_INTPEND_UP_Pending (0x1UL) /*!< Read: Pending */ + +/* CROSS @Bit 3 : Read pending status of interrupt for event CROSS */ + #define COMP_INTPEND_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define COMP_INTPEND_CROSS_Msk (0x1UL << COMP_INTPEND_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define COMP_INTPEND_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define COMP_INTPEND_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define COMP_INTPEND_CROSS_NotPending (0x0UL) /*!< Read: Not pending */ + #define COMP_INTPEND_CROSS_Pending (0x1UL) /*!< Read: Pending */ + + +/* COMP_RESULT: Compare result */ + #define COMP_RESULT_ResetValue (0x00000000UL) /*!< Reset value of RESULT register. */ + +/* RESULT @Bit 0 : Result of last compare. Decision point SAMPLE task. */ + #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ + #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ + #define COMP_RESULT_RESULT_Min (0x0UL) /*!< Min enumerator value of RESULT field. */ + #define COMP_RESULT_RESULT_Max (0x1UL) /*!< Max enumerator value of RESULT field. */ + #define COMP_RESULT_RESULT_Below (0x0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ + #define COMP_RESULT_RESULT_Above (0x1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + + +/* COMP_ENABLE: COMP enable */ + #define COMP_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..1 : Enable or disable COMP */ + #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define COMP_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define COMP_ENABLE_ENABLE_Max (0x2UL) /*!< Max enumerator value of ENABLE field. */ + #define COMP_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define COMP_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable */ + + +/* COMP_PSEL: Pin select */ + #define COMP_PSEL_ResetValue (0x00000000UL) /*!< Reset value of PSEL register. */ + +/* PIN @Bits 0..4 : Analog pin select */ + #define COMP_PSEL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define COMP_PSEL_PIN_Msk (0x1FUL << COMP_PSEL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO Port selection */ + #define COMP_PSEL_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define COMP_PSEL_PORT_Msk (0xFUL << COMP_PSEL_PORT_Pos) /*!< Bit mask of PORT field. */ + + +/* COMP_REFSEL: Reference source select for single-ended mode */ + #define COMP_REFSEL_ResetValue (0x00000004UL) /*!< Reset value of REFSEL register. */ + +/* REFSEL @Bits 0..2 : Reference select */ + #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ + #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ + #define COMP_REFSEL_REFSEL_Min (0x0UL) /*!< Min enumerator value of REFSEL field. */ + #define COMP_REFSEL_REFSEL_Max (0x5UL) /*!< Max enumerator value of REFSEL field. */ + #define COMP_REFSEL_REFSEL_Int1V2 (0x0UL) /*!< VREF = internal 1.2 V reference */ + #define COMP_REFSEL_REFSEL_VDD (0x4UL) /*!< VREF = VDD */ + #define COMP_REFSEL_REFSEL_ARef (0x5UL) /*!< VREF = AREF */ + + +/* COMP_EXTREFSEL: External reference select */ + #define COMP_EXTREFSEL_ResetValue (0x00000000UL) /*!< Reset value of EXTREFSEL register. */ + +/* PIN @Bits 0..4 : External analog reference pin select */ + #define COMP_EXTREFSEL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define COMP_EXTREFSEL_PIN_Msk (0x1FUL << COMP_EXTREFSEL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO Port selection */ + #define COMP_EXTREFSEL_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define COMP_EXTREFSEL_PORT_Msk (0xFUL << COMP_EXTREFSEL_PORT_Pos) /*!< Bit mask of PORT field. */ + + +/* COMP_TH: Threshold configuration for hysteresis unit */ + #define COMP_TH_ResetValue (0x00002020UL) /*!< Reset value of TH register. */ + +/* THDOWN @Bits 0..5 : VDOWN = (THDOWN+1)/64*VREF */ + #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ + #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + #define COMP_TH_THDOWN_Min (0x00UL) /*!< Min value of THDOWN field. */ + #define COMP_TH_THDOWN_Max (0x3FUL) /*!< Max size of THDOWN field. */ + +/* THUP @Bits 8..13 : VUP = (THUP+1)/64*VREF */ + #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ + #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + #define COMP_TH_THUP_Min (0x00UL) /*!< Min value of THUP field. */ + #define COMP_TH_THUP_Max (0x3FUL) /*!< Max size of THUP field. */ + + +/* COMP_MODE: Mode configuration */ + #define COMP_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* SP @Bits 0..1 : Speed and power modes */ + #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ + #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ + #define COMP_MODE_SP_Min (0x0UL) /*!< Min enumerator value of SP field. */ + #define COMP_MODE_SP_Max (0x2UL) /*!< Max enumerator value of SP field. */ + #define COMP_MODE_SP_Low (0x0UL) /*!< Low-power mode */ + #define COMP_MODE_SP_Normal (0x1UL) /*!< Normal mode */ + #define COMP_MODE_SP_High (0x2UL) /*!< High-speed mode */ + +/* MAIN @Bit 8 : Main operation modes */ + #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ + #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ + #define COMP_MODE_MAIN_Min (0x0UL) /*!< Min enumerator value of MAIN field. */ + #define COMP_MODE_MAIN_Max (0x1UL) /*!< Max enumerator value of MAIN field. */ + #define COMP_MODE_MAIN_SE (0x0UL) /*!< Single-ended mode */ + #define COMP_MODE_MAIN_Diff (0x1UL) /*!< Differential mode */ + + +/* COMP_HYST: Comparator hysteresis enable */ + #define COMP_HYST_ResetValue (0x00000000UL) /*!< Reset value of HYST register. */ + +/* HYST @Bit 0 : Comparator hysteresis */ + #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ + #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ + #define COMP_HYST_HYST_Min (0x0UL) /*!< Min enumerator value of HYST field. */ + #define COMP_HYST_HYST_Max (0x1UL) /*!< Max enumerator value of HYST field. */ + #define COMP_HYST_HYST_NoHyst (0x0UL) /*!< Comparator hysteresis disabled */ + #define COMP_HYST_HYST_Hyst40mV (0x1UL) /*!< Comparator hysteresis enabled */ + + +/* COMP_ISOURCE: Current source select on analog input */ + #define COMP_ISOURCE_ResetValue (0x00000000UL) /*!< Reset value of ISOURCE register. */ + +/* ISOURCE @Bits 0..1 : Current source select on analog input */ + #define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */ + #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */ + #define COMP_ISOURCE_ISOURCE_Min (0x0UL) /*!< Min enumerator value of ISOURCE field. */ + #define COMP_ISOURCE_ISOURCE_Max (0x3UL) /*!< Max enumerator value of ISOURCE field. */ + #define COMP_ISOURCE_ISOURCE_Off (0x0UL) /*!< Current source disabled */ + #define COMP_ISOURCE_ISOURCE_Ien2uA5 (0x1UL) /*!< Current source enabled (+/- 2.5 uA) */ + #define COMP_ISOURCE_ISOURCE_Ien5uA (0x2UL) /*!< Current source enabled (+/- 5 uA) */ + #define COMP_ISOURCE_ISOURCE_Ien10uA (0x3UL) /*!< Current source enabled (+/- 10 uA) */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CPUC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct CPUC ======================================================= */ +/** + * @brief CPU control + */ + typedef struct { /*!< CPUC Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_FPUIOC; /*!< (@ 0x00000100) An invalid operation exception has occurred in the + FPU.*/ + __IOM uint32_t EVENTS_FPUDZC; /*!< (@ 0x00000104) A floating-point divide-by-zero exception has occurred + in the FPU.*/ + __IOM uint32_t EVENTS_FPUOFC; /*!< (@ 0x00000108) A floating-point overflow exception has occurred in the + FPU.*/ + __IOM uint32_t EVENTS_FPUUFC; /*!< (@ 0x0000010C) A floating-point underflow exception has occurred in + the FPU.*/ + __IOM uint32_t EVENTS_FPUIXC; /*!< (@ 0x00000110) A floating-point inexact exception has occurred in the + FPU.*/ + __IOM uint32_t EVENTS_FPUIDC; /*!< (@ 0x00000114) A floating-point input denormal exception has occurred + in the FPU.*/ + __IM uint32_t RESERVED1[122]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t LOCK; /*!< (@ 0x00000500) Register to lock the certain parts of the CPU from + being modified.*/ + __IM uint32_t CPUID; /*!< (@ 0x00000504) The identifier for the CPU in this subsystem. */ + } NRF_CPUC_Type; /*!< Size = 1288 (0x508) */ + +/* CPUC_EVENTS_FPUIOC: An invalid operation exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUIOC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIOC register. */ + +/* EVENTS_FPUIOC @Bit 0 : An invalid operation exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Pos (0UL) /*!< Position of EVENTS_FPUIOC field. */ + #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Msk (0x1UL << CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Pos) /*!< Bit mask of EVENTS_FPUIOC + field.*/ + #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIOC field. */ + #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIOC field. */ + #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Generated (0x1UL) /*!< Event generated */ + + +/* CPUC_EVENTS_FPUDZC: A floating-point divide-by-zero exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUDZC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUDZC register. */ + +/* EVENTS_FPUDZC @Bit 0 : A floating-point divide-by-zero exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Pos (0UL) /*!< Position of EVENTS_FPUDZC field. */ + #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Msk (0x1UL << CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Pos) /*!< Bit mask of EVENTS_FPUDZC + field.*/ + #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUDZC field. */ + #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUDZC field. */ + #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Generated (0x1UL) /*!< Event generated */ + + +/* CPUC_EVENTS_FPUOFC: A floating-point overflow exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUOFC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUOFC register. */ + +/* EVENTS_FPUOFC @Bit 0 : A floating-point overflow exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Pos (0UL) /*!< Position of EVENTS_FPUOFC field. */ + #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Msk (0x1UL << CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Pos) /*!< Bit mask of EVENTS_FPUOFC + field.*/ + #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUOFC field. */ + #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUOFC field. */ + #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Generated (0x1UL) /*!< Event generated */ + + +/* CPUC_EVENTS_FPUUFC: A floating-point underflow exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUUFC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUUFC register. */ + +/* EVENTS_FPUUFC @Bit 0 : A floating-point underflow exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Pos (0UL) /*!< Position of EVENTS_FPUUFC field. */ + #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Msk (0x1UL << CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Pos) /*!< Bit mask of EVENTS_FPUUFC + field.*/ + #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUUFC field. */ + #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUUFC field. */ + #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Generated (0x1UL) /*!< Event generated */ + + +/* CPUC_EVENTS_FPUIXC: A floating-point inexact exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUIXC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIXC register. */ + +/* EVENTS_FPUIXC @Bit 0 : A floating-point inexact exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Pos (0UL) /*!< Position of EVENTS_FPUIXC field. */ + #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Msk (0x1UL << CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Pos) /*!< Bit mask of EVENTS_FPUIXC + field.*/ + #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIXC field. */ + #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIXC field. */ + #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Generated (0x1UL) /*!< Event generated */ + + +/* CPUC_EVENTS_FPUIDC: A floating-point input denormal exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUIDC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIDC register. */ + +/* EVENTS_FPUIDC @Bit 0 : A floating-point input denormal exception has occurred in the FPU. */ + #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Pos (0UL) /*!< Position of EVENTS_FPUIDC field. */ + #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Msk (0x1UL << CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Pos) /*!< Bit mask of EVENTS_FPUIDC + field.*/ + #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIDC field. */ + #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIDC field. */ + #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Generated (0x1UL) /*!< Event generated */ + + +/* CPUC_INTEN: Enable or disable interrupt */ + #define CPUC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* FPUIOC @Bit 0 : Enable or disable interrupt for event FPUIOC */ + #define CPUC_INTEN_FPUIOC_Pos (0UL) /*!< Position of FPUIOC field. */ + #define CPUC_INTEN_FPUIOC_Msk (0x1UL << CPUC_INTEN_FPUIOC_Pos) /*!< Bit mask of FPUIOC field. */ + #define CPUC_INTEN_FPUIOC_Min (0x0UL) /*!< Min enumerator value of FPUIOC field. */ + #define CPUC_INTEN_FPUIOC_Max (0x1UL) /*!< Max enumerator value of FPUIOC field. */ + #define CPUC_INTEN_FPUIOC_Disabled (0x0UL) /*!< Disable */ + #define CPUC_INTEN_FPUIOC_Enabled (0x1UL) /*!< Enable */ + +/* FPUDZC @Bit 1 : Enable or disable interrupt for event FPUDZC */ + #define CPUC_INTEN_FPUDZC_Pos (1UL) /*!< Position of FPUDZC field. */ + #define CPUC_INTEN_FPUDZC_Msk (0x1UL << CPUC_INTEN_FPUDZC_Pos) /*!< Bit mask of FPUDZC field. */ + #define CPUC_INTEN_FPUDZC_Min (0x0UL) /*!< Min enumerator value of FPUDZC field. */ + #define CPUC_INTEN_FPUDZC_Max (0x1UL) /*!< Max enumerator value of FPUDZC field. */ + #define CPUC_INTEN_FPUDZC_Disabled (0x0UL) /*!< Disable */ + #define CPUC_INTEN_FPUDZC_Enabled (0x1UL) /*!< Enable */ + +/* FPUOFC @Bit 2 : Enable or disable interrupt for event FPUOFC */ + #define CPUC_INTEN_FPUOFC_Pos (2UL) /*!< Position of FPUOFC field. */ + #define CPUC_INTEN_FPUOFC_Msk (0x1UL << CPUC_INTEN_FPUOFC_Pos) /*!< Bit mask of FPUOFC field. */ + #define CPUC_INTEN_FPUOFC_Min (0x0UL) /*!< Min enumerator value of FPUOFC field. */ + #define CPUC_INTEN_FPUOFC_Max (0x1UL) /*!< Max enumerator value of FPUOFC field. */ + #define CPUC_INTEN_FPUOFC_Disabled (0x0UL) /*!< Disable */ + #define CPUC_INTEN_FPUOFC_Enabled (0x1UL) /*!< Enable */ + +/* FPUUFC @Bit 3 : Enable or disable interrupt for event FPUUFC */ + #define CPUC_INTEN_FPUUFC_Pos (3UL) /*!< Position of FPUUFC field. */ + #define CPUC_INTEN_FPUUFC_Msk (0x1UL << CPUC_INTEN_FPUUFC_Pos) /*!< Bit mask of FPUUFC field. */ + #define CPUC_INTEN_FPUUFC_Min (0x0UL) /*!< Min enumerator value of FPUUFC field. */ + #define CPUC_INTEN_FPUUFC_Max (0x1UL) /*!< Max enumerator value of FPUUFC field. */ + #define CPUC_INTEN_FPUUFC_Disabled (0x0UL) /*!< Disable */ + #define CPUC_INTEN_FPUUFC_Enabled (0x1UL) /*!< Enable */ + +/* FPUIXC @Bit 4 : Enable or disable interrupt for event FPUIXC */ + #define CPUC_INTEN_FPUIXC_Pos (4UL) /*!< Position of FPUIXC field. */ + #define CPUC_INTEN_FPUIXC_Msk (0x1UL << CPUC_INTEN_FPUIXC_Pos) /*!< Bit mask of FPUIXC field. */ + #define CPUC_INTEN_FPUIXC_Min (0x0UL) /*!< Min enumerator value of FPUIXC field. */ + #define CPUC_INTEN_FPUIXC_Max (0x1UL) /*!< Max enumerator value of FPUIXC field. */ + #define CPUC_INTEN_FPUIXC_Disabled (0x0UL) /*!< Disable */ + #define CPUC_INTEN_FPUIXC_Enabled (0x1UL) /*!< Enable */ + +/* FPUIDC @Bit 5 : Enable or disable interrupt for event FPUIDC */ + #define CPUC_INTEN_FPUIDC_Pos (5UL) /*!< Position of FPUIDC field. */ + #define CPUC_INTEN_FPUIDC_Msk (0x1UL << CPUC_INTEN_FPUIDC_Pos) /*!< Bit mask of FPUIDC field. */ + #define CPUC_INTEN_FPUIDC_Min (0x0UL) /*!< Min enumerator value of FPUIDC field. */ + #define CPUC_INTEN_FPUIDC_Max (0x1UL) /*!< Max enumerator value of FPUIDC field. */ + #define CPUC_INTEN_FPUIDC_Disabled (0x0UL) /*!< Disable */ + #define CPUC_INTEN_FPUIDC_Enabled (0x1UL) /*!< Enable */ + + +/* CPUC_INTENSET: Enable interrupt */ + #define CPUC_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* FPUIOC @Bit 0 : Write '1' to enable interrupt for event FPUIOC */ + #define CPUC_INTENSET_FPUIOC_Pos (0UL) /*!< Position of FPUIOC field. */ + #define CPUC_INTENSET_FPUIOC_Msk (0x1UL << CPUC_INTENSET_FPUIOC_Pos) /*!< Bit mask of FPUIOC field. */ + #define CPUC_INTENSET_FPUIOC_Min (0x0UL) /*!< Min enumerator value of FPUIOC field. */ + #define CPUC_INTENSET_FPUIOC_Max (0x1UL) /*!< Max enumerator value of FPUIOC field. */ + #define CPUC_INTENSET_FPUIOC_Set (0x1UL) /*!< Enable */ + #define CPUC_INTENSET_FPUIOC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENSET_FPUIOC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FPUDZC @Bit 1 : Write '1' to enable interrupt for event FPUDZC */ + #define CPUC_INTENSET_FPUDZC_Pos (1UL) /*!< Position of FPUDZC field. */ + #define CPUC_INTENSET_FPUDZC_Msk (0x1UL << CPUC_INTENSET_FPUDZC_Pos) /*!< Bit mask of FPUDZC field. */ + #define CPUC_INTENSET_FPUDZC_Min (0x0UL) /*!< Min enumerator value of FPUDZC field. */ + #define CPUC_INTENSET_FPUDZC_Max (0x1UL) /*!< Max enumerator value of FPUDZC field. */ + #define CPUC_INTENSET_FPUDZC_Set (0x1UL) /*!< Enable */ + #define CPUC_INTENSET_FPUDZC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENSET_FPUDZC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FPUOFC @Bit 2 : Write '1' to enable interrupt for event FPUOFC */ + #define CPUC_INTENSET_FPUOFC_Pos (2UL) /*!< Position of FPUOFC field. */ + #define CPUC_INTENSET_FPUOFC_Msk (0x1UL << CPUC_INTENSET_FPUOFC_Pos) /*!< Bit mask of FPUOFC field. */ + #define CPUC_INTENSET_FPUOFC_Min (0x0UL) /*!< Min enumerator value of FPUOFC field. */ + #define CPUC_INTENSET_FPUOFC_Max (0x1UL) /*!< Max enumerator value of FPUOFC field. */ + #define CPUC_INTENSET_FPUOFC_Set (0x1UL) /*!< Enable */ + #define CPUC_INTENSET_FPUOFC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENSET_FPUOFC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FPUUFC @Bit 3 : Write '1' to enable interrupt for event FPUUFC */ + #define CPUC_INTENSET_FPUUFC_Pos (3UL) /*!< Position of FPUUFC field. */ + #define CPUC_INTENSET_FPUUFC_Msk (0x1UL << CPUC_INTENSET_FPUUFC_Pos) /*!< Bit mask of FPUUFC field. */ + #define CPUC_INTENSET_FPUUFC_Min (0x0UL) /*!< Min enumerator value of FPUUFC field. */ + #define CPUC_INTENSET_FPUUFC_Max (0x1UL) /*!< Max enumerator value of FPUUFC field. */ + #define CPUC_INTENSET_FPUUFC_Set (0x1UL) /*!< Enable */ + #define CPUC_INTENSET_FPUUFC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENSET_FPUUFC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FPUIXC @Bit 4 : Write '1' to enable interrupt for event FPUIXC */ + #define CPUC_INTENSET_FPUIXC_Pos (4UL) /*!< Position of FPUIXC field. */ + #define CPUC_INTENSET_FPUIXC_Msk (0x1UL << CPUC_INTENSET_FPUIXC_Pos) /*!< Bit mask of FPUIXC field. */ + #define CPUC_INTENSET_FPUIXC_Min (0x0UL) /*!< Min enumerator value of FPUIXC field. */ + #define CPUC_INTENSET_FPUIXC_Max (0x1UL) /*!< Max enumerator value of FPUIXC field. */ + #define CPUC_INTENSET_FPUIXC_Set (0x1UL) /*!< Enable */ + #define CPUC_INTENSET_FPUIXC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENSET_FPUIXC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FPUIDC @Bit 5 : Write '1' to enable interrupt for event FPUIDC */ + #define CPUC_INTENSET_FPUIDC_Pos (5UL) /*!< Position of FPUIDC field. */ + #define CPUC_INTENSET_FPUIDC_Msk (0x1UL << CPUC_INTENSET_FPUIDC_Pos) /*!< Bit mask of FPUIDC field. */ + #define CPUC_INTENSET_FPUIDC_Min (0x0UL) /*!< Min enumerator value of FPUIDC field. */ + #define CPUC_INTENSET_FPUIDC_Max (0x1UL) /*!< Max enumerator value of FPUIDC field. */ + #define CPUC_INTENSET_FPUIDC_Set (0x1UL) /*!< Enable */ + #define CPUC_INTENSET_FPUIDC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENSET_FPUIDC_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CPUC_INTENCLR: Disable interrupt */ + #define CPUC_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* FPUIOC @Bit 0 : Write '1' to disable interrupt for event FPUIOC */ + #define CPUC_INTENCLR_FPUIOC_Pos (0UL) /*!< Position of FPUIOC field. */ + #define CPUC_INTENCLR_FPUIOC_Msk (0x1UL << CPUC_INTENCLR_FPUIOC_Pos) /*!< Bit mask of FPUIOC field. */ + #define CPUC_INTENCLR_FPUIOC_Min (0x0UL) /*!< Min enumerator value of FPUIOC field. */ + #define CPUC_INTENCLR_FPUIOC_Max (0x1UL) /*!< Max enumerator value of FPUIOC field. */ + #define CPUC_INTENCLR_FPUIOC_Clear (0x1UL) /*!< Disable */ + #define CPUC_INTENCLR_FPUIOC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENCLR_FPUIOC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FPUDZC @Bit 1 : Write '1' to disable interrupt for event FPUDZC */ + #define CPUC_INTENCLR_FPUDZC_Pos (1UL) /*!< Position of FPUDZC field. */ + #define CPUC_INTENCLR_FPUDZC_Msk (0x1UL << CPUC_INTENCLR_FPUDZC_Pos) /*!< Bit mask of FPUDZC field. */ + #define CPUC_INTENCLR_FPUDZC_Min (0x0UL) /*!< Min enumerator value of FPUDZC field. */ + #define CPUC_INTENCLR_FPUDZC_Max (0x1UL) /*!< Max enumerator value of FPUDZC field. */ + #define CPUC_INTENCLR_FPUDZC_Clear (0x1UL) /*!< Disable */ + #define CPUC_INTENCLR_FPUDZC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENCLR_FPUDZC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FPUOFC @Bit 2 : Write '1' to disable interrupt for event FPUOFC */ + #define CPUC_INTENCLR_FPUOFC_Pos (2UL) /*!< Position of FPUOFC field. */ + #define CPUC_INTENCLR_FPUOFC_Msk (0x1UL << CPUC_INTENCLR_FPUOFC_Pos) /*!< Bit mask of FPUOFC field. */ + #define CPUC_INTENCLR_FPUOFC_Min (0x0UL) /*!< Min enumerator value of FPUOFC field. */ + #define CPUC_INTENCLR_FPUOFC_Max (0x1UL) /*!< Max enumerator value of FPUOFC field. */ + #define CPUC_INTENCLR_FPUOFC_Clear (0x1UL) /*!< Disable */ + #define CPUC_INTENCLR_FPUOFC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENCLR_FPUOFC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FPUUFC @Bit 3 : Write '1' to disable interrupt for event FPUUFC */ + #define CPUC_INTENCLR_FPUUFC_Pos (3UL) /*!< Position of FPUUFC field. */ + #define CPUC_INTENCLR_FPUUFC_Msk (0x1UL << CPUC_INTENCLR_FPUUFC_Pos) /*!< Bit mask of FPUUFC field. */ + #define CPUC_INTENCLR_FPUUFC_Min (0x0UL) /*!< Min enumerator value of FPUUFC field. */ + #define CPUC_INTENCLR_FPUUFC_Max (0x1UL) /*!< Max enumerator value of FPUUFC field. */ + #define CPUC_INTENCLR_FPUUFC_Clear (0x1UL) /*!< Disable */ + #define CPUC_INTENCLR_FPUUFC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENCLR_FPUUFC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FPUIXC @Bit 4 : Write '1' to disable interrupt for event FPUIXC */ + #define CPUC_INTENCLR_FPUIXC_Pos (4UL) /*!< Position of FPUIXC field. */ + #define CPUC_INTENCLR_FPUIXC_Msk (0x1UL << CPUC_INTENCLR_FPUIXC_Pos) /*!< Bit mask of FPUIXC field. */ + #define CPUC_INTENCLR_FPUIXC_Min (0x0UL) /*!< Min enumerator value of FPUIXC field. */ + #define CPUC_INTENCLR_FPUIXC_Max (0x1UL) /*!< Max enumerator value of FPUIXC field. */ + #define CPUC_INTENCLR_FPUIXC_Clear (0x1UL) /*!< Disable */ + #define CPUC_INTENCLR_FPUIXC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENCLR_FPUIXC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FPUIDC @Bit 5 : Write '1' to disable interrupt for event FPUIDC */ + #define CPUC_INTENCLR_FPUIDC_Pos (5UL) /*!< Position of FPUIDC field. */ + #define CPUC_INTENCLR_FPUIDC_Msk (0x1UL << CPUC_INTENCLR_FPUIDC_Pos) /*!< Bit mask of FPUIDC field. */ + #define CPUC_INTENCLR_FPUIDC_Min (0x0UL) /*!< Min enumerator value of FPUIDC field. */ + #define CPUC_INTENCLR_FPUIDC_Max (0x1UL) /*!< Max enumerator value of FPUIDC field. */ + #define CPUC_INTENCLR_FPUIDC_Clear (0x1UL) /*!< Disable */ + #define CPUC_INTENCLR_FPUIDC_Disabled (0x0UL) /*!< Read: Disabled */ + #define CPUC_INTENCLR_FPUIDC_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CPUC_LOCK: Register to lock the certain parts of the CPU from being modified. */ + #define CPUC_LOCK_ResetValue (0x00000000UL) /*!< Reset value of LOCK register. */ + +/* LOCKVTORAIRCRS @Bit 0 : Locks both the Vector table Offset Register (VTOR) and Application Interrupt and Reset Control + Register (AIRCR) for secure mode. */ + + #define CPUC_LOCK_LOCKVTORAIRCRS_Pos (0UL) /*!< Position of LOCKVTORAIRCRS field. */ + #define CPUC_LOCK_LOCKVTORAIRCRS_Msk (0x1UL << CPUC_LOCK_LOCKVTORAIRCRS_Pos) /*!< Bit mask of LOCKVTORAIRCRS field. */ + #define CPUC_LOCK_LOCKVTORAIRCRS_Min (0x0UL) /*!< Min enumerator value of LOCKVTORAIRCRS field. */ + #define CPUC_LOCK_LOCKVTORAIRCRS_Max (0x1UL) /*!< Max enumerator value of LOCKVTORAIRCRS field. */ + #define CPUC_LOCK_LOCKVTORAIRCRS_NotLocked (0x0UL) /*!< Both VTOR and AIRCR can be changed. */ + #define CPUC_LOCK_LOCKVTORAIRCRS_Locked (0x1UL) /*!< Prevents changes to both VTOR and AIRCR. */ + +/* LOCKVTORNS @Bit 1 : Locks the Vector table Offset Register (VTOR) for non-secure mode. */ + #define CPUC_LOCK_LOCKVTORNS_Pos (1UL) /*!< Position of LOCKVTORNS field. */ + #define CPUC_LOCK_LOCKVTORNS_Msk (0x1UL << CPUC_LOCK_LOCKVTORNS_Pos) /*!< Bit mask of LOCKVTORNS field. */ + #define CPUC_LOCK_LOCKVTORNS_Min (0x0UL) /*!< Min enumerator value of LOCKVTORNS field. */ + #define CPUC_LOCK_LOCKVTORNS_Max (0x1UL) /*!< Max enumerator value of LOCKVTORNS field. */ + #define CPUC_LOCK_LOCKVTORNS_NotLocked (0x0UL) /*!< VTOR can be changed. */ + #define CPUC_LOCK_LOCKVTORNS_Locked (0x1UL) /*!< Prevents changes to VTOR. */ + +/* LOCKMPUS @Bit 2 : Locks the Memory Protection Unit (MPU) for secure mode. */ + #define CPUC_LOCK_LOCKMPUS_Pos (2UL) /*!< Position of LOCKMPUS field. */ + #define CPUC_LOCK_LOCKMPUS_Msk (0x1UL << CPUC_LOCK_LOCKMPUS_Pos) /*!< Bit mask of LOCKMPUS field. */ + #define CPUC_LOCK_LOCKMPUS_Min (0x0UL) /*!< Min enumerator value of LOCKMPUS field. */ + #define CPUC_LOCK_LOCKMPUS_Max (0x1UL) /*!< Max enumerator value of LOCKMPUS field. */ + #define CPUC_LOCK_LOCKMPUS_NotLocked (0x0UL) /*!< MPU registers can be changed. */ + #define CPUC_LOCK_LOCKMPUS_Locked (0x1UL) /*!< Prevents changes to MPU registers. */ + +/* LOCKMPUNS @Bit 3 : Locks the Memory Protection Unit (MPU) for non secure mode. */ + #define CPUC_LOCK_LOCKMPUNS_Pos (3UL) /*!< Position of LOCKMPUNS field. */ + #define CPUC_LOCK_LOCKMPUNS_Msk (0x1UL << CPUC_LOCK_LOCKMPUNS_Pos) /*!< Bit mask of LOCKMPUNS field. */ + #define CPUC_LOCK_LOCKMPUNS_Min (0x0UL) /*!< Min enumerator value of LOCKMPUNS field. */ + #define CPUC_LOCK_LOCKMPUNS_Max (0x1UL) /*!< Max enumerator value of LOCKMPUNS field. */ + #define CPUC_LOCK_LOCKMPUNS_NotLocked (0x0UL) /*!< MPU registers can be changed. */ + #define CPUC_LOCK_LOCKMPUNS_Locked (0x1UL) /*!< Prevents changes to MPU registers. */ + +/* LOCKSAU @Bit 4 : Locks the Security Attribution Unit (SAU) */ + #define CPUC_LOCK_LOCKSAU_Pos (4UL) /*!< Position of LOCKSAU field. */ + #define CPUC_LOCK_LOCKSAU_Msk (0x1UL << CPUC_LOCK_LOCKSAU_Pos) /*!< Bit mask of LOCKSAU field. */ + #define CPUC_LOCK_LOCKSAU_Min (0x0UL) /*!< Min enumerator value of LOCKSAU field. */ + #define CPUC_LOCK_LOCKSAU_Max (0x1UL) /*!< Max enumerator value of LOCKSAU field. */ + #define CPUC_LOCK_LOCKSAU_NotLocked (0x0UL) /*!< SAU registers can be changed. */ + #define CPUC_LOCK_LOCKSAU_Locked (0x1UL) /*!< Prevents changes to SAU registers. */ + + +/* CPUC_CPUID: The identifier for the CPU in this subsystem. */ + #define CPUC_CPUID_ResetValue (0x00000000UL) /*!< Reset value of CPUID register. */ + +/* CPUID @Bits 0..31 : The CPU identifier. */ + #define CPUC_CPUID_CPUID_Pos (0UL) /*!< Position of CPUID field. */ + #define CPUC_CPUID_CPUID_Msk (0xFFFFFFFFUL << CPUC_CPUID_CPUID_Pos) /*!< Bit mask of CPUID field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CRACEN ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ====================================================== Struct CRACEN ====================================================== */ +/** + * @brief CRACEN + */ + typedef struct { /*!< CRACEN Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_CRYPTOMASTER; /*!< (@ 0x00000100) Event indicating that interrupt triggered at + Cryptomaster*/ + __IOM uint32_t EVENTS_RNG; /*!< (@ 0x00000104) Event indicating that interrupt triggered at RNG */ + __IOM uint32_t EVENTS_PKEIKG; /*!< (@ 0x00000108) Event indicating that interrupt triggered at PKE or + IKG*/ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[60]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000400) Enable CRACEN peripheral modules. */ + __IOM uint32_t SEEDVALID; /*!< (@ 0x00000404) Indicates the SEED register is valid. Writing this + register has no effect.*/ + __IM uint32_t RESERVED3[2]; + __OM uint32_t SEED[12]; /*!< (@ 0x00000410) Seed word [n] for symmetric and asymmetric key + generation. This register is only writable from KMU.*/ + __IOM uint32_t SEEDLOCK; /*!< (@ 0x00000440) Indicates the access to the SEED register is locked. + Writing this register has no effect.*/ + __IOM uint32_t PROTECTEDRAMLOCK; /*!< (@ 0x00000444) Lock the access to the protected RAM. */ + } NRF_CRACEN_Type; /*!< Size = 1096 (0x448) */ + +/* CRACEN_EVENTS_CRYPTOMASTER: Event indicating that interrupt triggered at Cryptomaster */ + #define CRACEN_EVENTS_CRYPTOMASTER_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CRYPTOMASTER register. */ + +/* EVENTS_CRYPTOMASTER @Bit 0 : Event indicating that interrupt triggered at Cryptomaster */ + #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Pos (0UL) /*!< Position of EVENTS_CRYPTOMASTER field. */ + #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Msk (0x1UL << CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Pos) /*!< + Bit mask of EVENTS_CRYPTOMASTER field.*/ + #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Min (0x0UL) /*!< Min enumerator value of EVENTS_CRYPTOMASTER field. */ + #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Max (0x1UL) /*!< Max enumerator value of EVENTS_CRYPTOMASTER field. */ + #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_NotGenerated (0x0UL) /*!< Event not generated */ + #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Generated (0x1UL) /*!< Event generated */ + + +/* CRACEN_EVENTS_RNG: Event indicating that interrupt triggered at RNG */ + #define CRACEN_EVENTS_RNG_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RNG register. */ + +/* EVENTS_RNG @Bit 0 : Event indicating that interrupt triggered at RNG */ + #define CRACEN_EVENTS_RNG_EVENTS_RNG_Pos (0UL) /*!< Position of EVENTS_RNG field. */ + #define CRACEN_EVENTS_RNG_EVENTS_RNG_Msk (0x1UL << CRACEN_EVENTS_RNG_EVENTS_RNG_Pos) /*!< Bit mask of EVENTS_RNG field. */ + #define CRACEN_EVENTS_RNG_EVENTS_RNG_Min (0x0UL) /*!< Min enumerator value of EVENTS_RNG field. */ + #define CRACEN_EVENTS_RNG_EVENTS_RNG_Max (0x1UL) /*!< Max enumerator value of EVENTS_RNG field. */ + #define CRACEN_EVENTS_RNG_EVENTS_RNG_NotGenerated (0x0UL) /*!< Event not generated */ + #define CRACEN_EVENTS_RNG_EVENTS_RNG_Generated (0x1UL) /*!< Event generated */ + + +/* CRACEN_EVENTS_PKEIKG: Event indicating that interrupt triggered at PKE or IKG */ + #define CRACEN_EVENTS_PKEIKG_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PKEIKG register. */ + +/* EVENTS_PKEIKG @Bit 0 : Event indicating that interrupt triggered at PKE or IKG */ + #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Pos (0UL) /*!< Position of EVENTS_PKEIKG field. */ + #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Msk (0x1UL << CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Pos) /*!< Bit mask of + EVENTS_PKEIKG field.*/ + #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Min (0x0UL) /*!< Min enumerator value of EVENTS_PKEIKG field. */ + #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Max (0x1UL) /*!< Max enumerator value of EVENTS_PKEIKG field. */ + #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_NotGenerated (0x0UL) /*!< Event not generated */ + #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Generated (0x1UL) /*!< Event generated */ + + +/* CRACEN_INTEN: Enable or disable interrupt */ + #define CRACEN_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* CRYPTOMASTER @Bit 0 : Enable or disable interrupt for event CRYPTOMASTER */ + #define CRACEN_INTEN_CRYPTOMASTER_Pos (0UL) /*!< Position of CRYPTOMASTER field. */ + #define CRACEN_INTEN_CRYPTOMASTER_Msk (0x1UL << CRACEN_INTEN_CRYPTOMASTER_Pos) /*!< Bit mask of CRYPTOMASTER field. */ + #define CRACEN_INTEN_CRYPTOMASTER_Min (0x0UL) /*!< Min enumerator value of CRYPTOMASTER field. */ + #define CRACEN_INTEN_CRYPTOMASTER_Max (0x1UL) /*!< Max enumerator value of CRYPTOMASTER field. */ + #define CRACEN_INTEN_CRYPTOMASTER_Disabled (0x0UL) /*!< Disable */ + #define CRACEN_INTEN_CRYPTOMASTER_Enabled (0x1UL) /*!< Enable */ + +/* RNG @Bit 1 : Enable or disable interrupt for event RNG */ + #define CRACEN_INTEN_RNG_Pos (1UL) /*!< Position of RNG field. */ + #define CRACEN_INTEN_RNG_Msk (0x1UL << CRACEN_INTEN_RNG_Pos) /*!< Bit mask of RNG field. */ + #define CRACEN_INTEN_RNG_Min (0x0UL) /*!< Min enumerator value of RNG field. */ + #define CRACEN_INTEN_RNG_Max (0x1UL) /*!< Max enumerator value of RNG field. */ + #define CRACEN_INTEN_RNG_Disabled (0x0UL) /*!< Disable */ + #define CRACEN_INTEN_RNG_Enabled (0x1UL) /*!< Enable */ + +/* PKEIKG @Bit 2 : Enable or disable interrupt for event PKEIKG */ + #define CRACEN_INTEN_PKEIKG_Pos (2UL) /*!< Position of PKEIKG field. */ + #define CRACEN_INTEN_PKEIKG_Msk (0x1UL << CRACEN_INTEN_PKEIKG_Pos) /*!< Bit mask of PKEIKG field. */ + #define CRACEN_INTEN_PKEIKG_Min (0x0UL) /*!< Min enumerator value of PKEIKG field. */ + #define CRACEN_INTEN_PKEIKG_Max (0x1UL) /*!< Max enumerator value of PKEIKG field. */ + #define CRACEN_INTEN_PKEIKG_Disabled (0x0UL) /*!< Disable */ + #define CRACEN_INTEN_PKEIKG_Enabled (0x1UL) /*!< Enable */ + + +/* CRACEN_INTENSET: Enable interrupt */ + #define CRACEN_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* CRYPTOMASTER @Bit 0 : Write '1' to enable interrupt for event CRYPTOMASTER */ + #define CRACEN_INTENSET_CRYPTOMASTER_Pos (0UL) /*!< Position of CRYPTOMASTER field. */ + #define CRACEN_INTENSET_CRYPTOMASTER_Msk (0x1UL << CRACEN_INTENSET_CRYPTOMASTER_Pos) /*!< Bit mask of CRYPTOMASTER field. */ + #define CRACEN_INTENSET_CRYPTOMASTER_Min (0x0UL) /*!< Min enumerator value of CRYPTOMASTER field. */ + #define CRACEN_INTENSET_CRYPTOMASTER_Max (0x1UL) /*!< Max enumerator value of CRYPTOMASTER field. */ + #define CRACEN_INTENSET_CRYPTOMASTER_Set (0x1UL) /*!< Enable */ + #define CRACEN_INTENSET_CRYPTOMASTER_Disabled (0x0UL) /*!< Read: Disabled */ + #define CRACEN_INTENSET_CRYPTOMASTER_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RNG @Bit 1 : Write '1' to enable interrupt for event RNG */ + #define CRACEN_INTENSET_RNG_Pos (1UL) /*!< Position of RNG field. */ + #define CRACEN_INTENSET_RNG_Msk (0x1UL << CRACEN_INTENSET_RNG_Pos) /*!< Bit mask of RNG field. */ + #define CRACEN_INTENSET_RNG_Min (0x0UL) /*!< Min enumerator value of RNG field. */ + #define CRACEN_INTENSET_RNG_Max (0x1UL) /*!< Max enumerator value of RNG field. */ + #define CRACEN_INTENSET_RNG_Set (0x1UL) /*!< Enable */ + #define CRACEN_INTENSET_RNG_Disabled (0x0UL) /*!< Read: Disabled */ + #define CRACEN_INTENSET_RNG_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PKEIKG @Bit 2 : Write '1' to enable interrupt for event PKEIKG */ + #define CRACEN_INTENSET_PKEIKG_Pos (2UL) /*!< Position of PKEIKG field. */ + #define CRACEN_INTENSET_PKEIKG_Msk (0x1UL << CRACEN_INTENSET_PKEIKG_Pos) /*!< Bit mask of PKEIKG field. */ + #define CRACEN_INTENSET_PKEIKG_Min (0x0UL) /*!< Min enumerator value of PKEIKG field. */ + #define CRACEN_INTENSET_PKEIKG_Max (0x1UL) /*!< Max enumerator value of PKEIKG field. */ + #define CRACEN_INTENSET_PKEIKG_Set (0x1UL) /*!< Enable */ + #define CRACEN_INTENSET_PKEIKG_Disabled (0x0UL) /*!< Read: Disabled */ + #define CRACEN_INTENSET_PKEIKG_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CRACEN_INTENCLR: Disable interrupt */ + #define CRACEN_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* CRYPTOMASTER @Bit 0 : Write '1' to disable interrupt for event CRYPTOMASTER */ + #define CRACEN_INTENCLR_CRYPTOMASTER_Pos (0UL) /*!< Position of CRYPTOMASTER field. */ + #define CRACEN_INTENCLR_CRYPTOMASTER_Msk (0x1UL << CRACEN_INTENCLR_CRYPTOMASTER_Pos) /*!< Bit mask of CRYPTOMASTER field. */ + #define CRACEN_INTENCLR_CRYPTOMASTER_Min (0x0UL) /*!< Min enumerator value of CRYPTOMASTER field. */ + #define CRACEN_INTENCLR_CRYPTOMASTER_Max (0x1UL) /*!< Max enumerator value of CRYPTOMASTER field. */ + #define CRACEN_INTENCLR_CRYPTOMASTER_Clear (0x1UL) /*!< Disable */ + #define CRACEN_INTENCLR_CRYPTOMASTER_Disabled (0x0UL) /*!< Read: Disabled */ + #define CRACEN_INTENCLR_CRYPTOMASTER_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RNG @Bit 1 : Write '1' to disable interrupt for event RNG */ + #define CRACEN_INTENCLR_RNG_Pos (1UL) /*!< Position of RNG field. */ + #define CRACEN_INTENCLR_RNG_Msk (0x1UL << CRACEN_INTENCLR_RNG_Pos) /*!< Bit mask of RNG field. */ + #define CRACEN_INTENCLR_RNG_Min (0x0UL) /*!< Min enumerator value of RNG field. */ + #define CRACEN_INTENCLR_RNG_Max (0x1UL) /*!< Max enumerator value of RNG field. */ + #define CRACEN_INTENCLR_RNG_Clear (0x1UL) /*!< Disable */ + #define CRACEN_INTENCLR_RNG_Disabled (0x0UL) /*!< Read: Disabled */ + #define CRACEN_INTENCLR_RNG_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PKEIKG @Bit 2 : Write '1' to disable interrupt for event PKEIKG */ + #define CRACEN_INTENCLR_PKEIKG_Pos (2UL) /*!< Position of PKEIKG field. */ + #define CRACEN_INTENCLR_PKEIKG_Msk (0x1UL << CRACEN_INTENCLR_PKEIKG_Pos) /*!< Bit mask of PKEIKG field. */ + #define CRACEN_INTENCLR_PKEIKG_Min (0x0UL) /*!< Min enumerator value of PKEIKG field. */ + #define CRACEN_INTENCLR_PKEIKG_Max (0x1UL) /*!< Max enumerator value of PKEIKG field. */ + #define CRACEN_INTENCLR_PKEIKG_Clear (0x1UL) /*!< Disable */ + #define CRACEN_INTENCLR_PKEIKG_Disabled (0x0UL) /*!< Read: Disabled */ + #define CRACEN_INTENCLR_PKEIKG_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CRACEN_INTPEND: Pending interrupts */ + #define CRACEN_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* CRYPTOMASTER @Bit 0 : Read pending status of interrupt for event CRYPTOMASTER */ + #define CRACEN_INTPEND_CRYPTOMASTER_Pos (0UL) /*!< Position of CRYPTOMASTER field. */ + #define CRACEN_INTPEND_CRYPTOMASTER_Msk (0x1UL << CRACEN_INTPEND_CRYPTOMASTER_Pos) /*!< Bit mask of CRYPTOMASTER field. */ + #define CRACEN_INTPEND_CRYPTOMASTER_Min (0x0UL) /*!< Min enumerator value of CRYPTOMASTER field. */ + #define CRACEN_INTPEND_CRYPTOMASTER_Max (0x1UL) /*!< Max enumerator value of CRYPTOMASTER field. */ + #define CRACEN_INTPEND_CRYPTOMASTER_NotPending (0x0UL) /*!< Read: Not pending */ + #define CRACEN_INTPEND_CRYPTOMASTER_Pending (0x1UL) /*!< Read: Pending */ + +/* RNG @Bit 1 : Read pending status of interrupt for event RNG */ + #define CRACEN_INTPEND_RNG_Pos (1UL) /*!< Position of RNG field. */ + #define CRACEN_INTPEND_RNG_Msk (0x1UL << CRACEN_INTPEND_RNG_Pos) /*!< Bit mask of RNG field. */ + #define CRACEN_INTPEND_RNG_Min (0x0UL) /*!< Min enumerator value of RNG field. */ + #define CRACEN_INTPEND_RNG_Max (0x1UL) /*!< Max enumerator value of RNG field. */ + #define CRACEN_INTPEND_RNG_NotPending (0x0UL) /*!< Read: Not pending */ + #define CRACEN_INTPEND_RNG_Pending (0x1UL) /*!< Read: Pending */ + +/* PKEIKG @Bit 2 : Read pending status of interrupt for event PKEIKG */ + #define CRACEN_INTPEND_PKEIKG_Pos (2UL) /*!< Position of PKEIKG field. */ + #define CRACEN_INTPEND_PKEIKG_Msk (0x1UL << CRACEN_INTPEND_PKEIKG_Pos) /*!< Bit mask of PKEIKG field. */ + #define CRACEN_INTPEND_PKEIKG_Min (0x0UL) /*!< Min enumerator value of PKEIKG field. */ + #define CRACEN_INTPEND_PKEIKG_Max (0x1UL) /*!< Max enumerator value of PKEIKG field. */ + #define CRACEN_INTPEND_PKEIKG_NotPending (0x0UL) /*!< Read: Not pending */ + #define CRACEN_INTPEND_PKEIKG_Pending (0x1UL) /*!< Read: Pending */ + + +/* CRACEN_ENABLE: Enable CRACEN peripheral modules. */ + #define CRACEN_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* CRYPTOMASTER @Bit 0 : Enable cryptomaster */ + #define CRACEN_ENABLE_CRYPTOMASTER_Pos (0UL) /*!< Position of CRYPTOMASTER field. */ + #define CRACEN_ENABLE_CRYPTOMASTER_Msk (0x1UL << CRACEN_ENABLE_CRYPTOMASTER_Pos) /*!< Bit mask of CRYPTOMASTER field. */ + #define CRACEN_ENABLE_CRYPTOMASTER_Min (0x0UL) /*!< Min enumerator value of CRYPTOMASTER field. */ + #define CRACEN_ENABLE_CRYPTOMASTER_Max (0x1UL) /*!< Max enumerator value of CRYPTOMASTER field. */ + #define CRACEN_ENABLE_CRYPTOMASTER_Disabled (0x0UL) /*!< Cryptomaster disabled. */ + #define CRACEN_ENABLE_CRYPTOMASTER_Enabled (0x1UL) /*!< Cryptomaster enabled. */ + +/* RNG @Bit 1 : Enable RNG */ + #define CRACEN_ENABLE_RNG_Pos (1UL) /*!< Position of RNG field. */ + #define CRACEN_ENABLE_RNG_Msk (0x1UL << CRACEN_ENABLE_RNG_Pos) /*!< Bit mask of RNG field. */ + #define CRACEN_ENABLE_RNG_Min (0x0UL) /*!< Min enumerator value of RNG field. */ + #define CRACEN_ENABLE_RNG_Max (0x1UL) /*!< Max enumerator value of RNG field. */ + #define CRACEN_ENABLE_RNG_Disabled (0x0UL) /*!< RNG disabled. */ + #define CRACEN_ENABLE_RNG_Enabled (0x1UL) /*!< RNG enabled. */ + +/* PKEIKG @Bit 2 : Enable PKE and IKG */ + #define CRACEN_ENABLE_PKEIKG_Pos (2UL) /*!< Position of PKEIKG field. */ + #define CRACEN_ENABLE_PKEIKG_Msk (0x1UL << CRACEN_ENABLE_PKEIKG_Pos) /*!< Bit mask of PKEIKG field. */ + #define CRACEN_ENABLE_PKEIKG_Min (0x0UL) /*!< Min enumerator value of PKEIKG field. */ + #define CRACEN_ENABLE_PKEIKG_Max (0x1UL) /*!< Max enumerator value of PKEIKG field. */ + #define CRACEN_ENABLE_PKEIKG_Disabled (0x0UL) /*!< PKE and IKG disabled. */ + #define CRACEN_ENABLE_PKEIKG_Enabled (0x1UL) /*!< PKE and IKG enabled. */ + + +/* CRACEN_SEEDVALID: Indicates the SEED register is valid. Writing this register has no effect. */ + #define CRACEN_SEEDVALID_ResetValue (0x00000000UL) /*!< Reset value of SEEDVALID register. */ + +/* VALID @Bit 0 : Marks the SEED as valid */ + #define CRACEN_SEEDVALID_VALID_Pos (0UL) /*!< Position of VALID field. */ + #define CRACEN_SEEDVALID_VALID_Msk (0x1UL << CRACEN_SEEDVALID_VALID_Pos) /*!< Bit mask of VALID field. */ + #define CRACEN_SEEDVALID_VALID_Min (0x0UL) /*!< Min enumerator value of VALID field. */ + #define CRACEN_SEEDVALID_VALID_Max (0x1UL) /*!< Max enumerator value of VALID field. */ + #define CRACEN_SEEDVALID_VALID_Disabled (0x0UL) /*!< Valid disabled. */ + #define CRACEN_SEEDVALID_VALID_Enabled (0x1UL) /*!< Valid enabled. */ + + +/* CRACEN_SEED: Seed word [n] for symmetric and asymmetric key generation. This register is only writable from KMU. */ + #define CRACEN_SEED_MaxCount (12UL) /*!< Max size of SEED[12] array. */ + #define CRACEN_SEED_MaxIndex (11UL) /*!< Max index of SEED[12] array. */ + #define CRACEN_SEED_MinIndex (0UL) /*!< Min index of SEED[12] array. */ + #define CRACEN_SEED_ResetValue (0x00000000UL) /*!< Reset value of SEED[12] register. */ + +/* VAL @Bits 0..31 : Seed value */ + #define CRACEN_SEED_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define CRACEN_SEED_VAL_Msk (0xFFFFFFFFUL << CRACEN_SEED_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/* CRACEN_SEEDLOCK: Indicates the access to the SEED register is locked. Writing this register has no effect. */ + #define CRACEN_SEEDLOCK_ResetValue (0x00000000UL) /*!< Reset value of SEEDLOCK register. */ + +/* ENABLE @Bit 0 : Enable the lock */ + #define CRACEN_SEEDLOCK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define CRACEN_SEEDLOCK_ENABLE_Msk (0x1UL << CRACEN_SEEDLOCK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define CRACEN_SEEDLOCK_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define CRACEN_SEEDLOCK_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define CRACEN_SEEDLOCK_ENABLE_Disabled (0x0UL) /*!< Lock disabled. */ + #define CRACEN_SEEDLOCK_ENABLE_Enabled (0x1UL) /*!< Lock enabled. */ + + +/* CRACEN_PROTECTEDRAMLOCK: Lock the access to the protected RAM. */ + #define CRACEN_PROTECTEDRAMLOCK_ResetValue (0x00000000UL) /*!< Reset value of PROTECTEDRAMLOCK register. */ + +/* ENABLE @Bit 0 : Enable the lock */ + #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Msk (0x1UL << CRACEN_PROTECTEDRAMLOCK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Disabled (0x0UL) /*!< Lock disabled. */ + #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Enabled (0x1UL) /*!< Lock enabled. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CRACENCORE ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ============================================= Struct CRACENCORE_CRYPTMSTRDMA ============================================== */ +/** + * @brief CRYPTMSTRDMA [CRACENCORE_CRYPTMSTRDMA] (unspecified) + */ +typedef struct { + __IOM uint32_t FETCHADDRLSB; /*!< (@ 0x00000000) Fetch Address Least Significant Word */ + __IOM uint32_t FETCHADDRMSB; /*!< (@ 0x00000004) Fetch Address Most Significant Word */ + __IOM uint32_t FETCHLEN; /*!< (@ 0x00000008) Fetch DMA Length (only used in direct mode) */ + __IOM uint32_t FETCHTAG; /*!< (@ 0x0000000C) Fetch User Tag (only used in direct mode) */ + __IOM uint32_t PUSHADDRLSB; /*!< (@ 0x00000010) Push Address Least Significant Word */ + __IOM uint32_t PUSHADDRMSB; /*!< (@ 0x00000014) Push Address Most Significant Word */ + __IOM uint32_t PUSHLEN; /*!< (@ 0x00000018) Push Length (only used in direct mode) */ + __IOM uint32_t INTEN; /*!< (@ 0x0000001C) Interrupt Enable mask */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000020) Interrupt Set */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000024) Interrupt Clear */ + __IOM uint32_t INTSTATRAW; /*!< (@ 0x00000028) Interrupt Status Raw */ + __IOM uint32_t INTSTAT; /*!< (@ 0x0000002C) Interrupt Status */ + __IOM uint32_t INTSTATCLR; /*!< (@ 0x00000030) Interrupt Status Clear */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000034) Cryptomaster configuration */ + __IOM uint32_t START; /*!< (@ 0x00000038) Start */ + __IOM uint32_t STATUS; /*!< (@ 0x0000003C) Status */ +} NRF_CRACENCORE_CRYPTMSTRDMA_Type; /*!< Size = 64 (0x040) */ + +/* CRACENCORE_CRYPTMSTRDMA_FETCHADDRLSB: Fetch Address Least Significant Word */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRLSB_ResetValue (0x00000000UL) /*!< Reset value of FETCHADDRLSB register. */ + +/* FETCHADDRLSB @Bits 0..31 : Address */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRLSB_FETCHADDRLSB_Pos (0UL) /*!< Position of FETCHADDRLSB field. */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRLSB_FETCHADDRLSB_Msk (0xFFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_FETCHADDRLSB_FETCHADDRLSB_Pos) + /*!< Bit mask of FETCHADDRLSB field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_FETCHADDRMSB: Fetch Address Most Significant Word */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRMSB_ResetValue (0x00000000UL) /*!< Reset value of FETCHADDRMSB register. */ + +/* FETCHADDRMSB @Bits 0..31 : (unspecified) */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRMSB_FETCHADDRMSB_Pos (0UL) /*!< Position of FETCHADDRMSB field. */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRMSB_FETCHADDRMSB_Msk (0xFFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_FETCHADDRMSB_FETCHADDRMSB_Pos) + /*!< Bit mask of FETCHADDRMSB field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_FETCHLEN: Fetch DMA Length (only used in direct mode) */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_ResetValue (0x00000000UL) /*!< Reset value of FETCHLEN register. */ + +/* FETCHLEN @Bits 0..27 : Length of data block */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHLEN_Pos (0UL) /*!< Position of FETCHLEN field. */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHLEN_Msk (0xFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHLEN_Pos) /*!< Bit + mask of FETCHLEN field.*/ + +/* FETCHCSTADDR @Bit 28 : Constant address */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHCSTADDR_Pos (28UL) /*!< Position of FETCHCSTADDR field. */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHCSTADDR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHCSTADDR_Pos) /*!< + Bit mask of FETCHCSTADDR field.*/ + +/* FETCHREALIGN @Bit 29 : Realign length */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHREALIGN_Pos (29UL) /*!< Position of FETCHREALIGN field. */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHREALIGN_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHREALIGN_Pos) /*!< + Bit mask of FETCHREALIGN field.*/ + +/* FETCHZPADDING @Bit 30 : (unspecified) */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHZPADDING_Pos (30UL) /*!< Position of FETCHZPADDING field. */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHZPADDING_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHZPADDING_Pos) /*!< + Bit mask of FETCHZPADDING field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_FETCHTAG: Fetch User Tag (only used in direct mode) */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHTAG_ResetValue (0x00000000UL) /*!< Reset value of FETCHTAG register. */ + +/* FETCHTAG @Bits 0..31 : User tag */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHTAG_FETCHTAG_Pos (0UL) /*!< Position of FETCHTAG field. */ + #define CRACENCORE_CRYPTMSTRDMA_FETCHTAG_FETCHTAG_Msk (0xFFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_FETCHTAG_FETCHTAG_Pos) /*!< Bit + mask of FETCHTAG field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_PUSHADDRLSB: Push Address Least Significant Word */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRLSB_ResetValue (0x00000000UL) /*!< Reset value of PUSHADDRLSB register. */ + +/* PUSHADDRLSB @Bits 0..31 : Address */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRLSB_PUSHADDRLSB_Pos (0UL) /*!< Position of PUSHADDRLSB field. */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRLSB_PUSHADDRLSB_Msk (0xFFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_PUSHADDRLSB_PUSHADDRLSB_Pos) + /*!< Bit mask of PUSHADDRLSB field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_PUSHADDRMSB: Push Address Most Significant Word */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRMSB_ResetValue (0x00000000UL) /*!< Reset value of PUSHADDRMSB register. */ + +/* PUSHADDRMSB @Bits 0..31 : (unspecified) */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRMSB_PUSHADDRMSB_Pos (0UL) /*!< Position of PUSHADDRMSB field. */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRMSB_PUSHADDRMSB_Msk (0xFFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_PUSHADDRMSB_PUSHADDRMSB_Pos) + /*!< Bit mask of PUSHADDRMSB field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_PUSHLEN: Push Length (only used in direct mode) */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_ResetValue (0x00000000UL) /*!< Reset value of PUSHLEN register. */ + +/* PUSHLEN @Bits 0..27 : Length of data block */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHLEN_Pos (0UL) /*!< Position of PUSHLEN field. */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHLEN_Msk (0xFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHLEN_Pos) /*!< Bit mask + of PUSHLEN field.*/ + +/* PUSHCSTADDR @Bit 28 : Constant address */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHCSTADDR_Pos (28UL) /*!< Position of PUSHCSTADDR field. */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHCSTADDR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHCSTADDR_Pos) /*!< Bit + mask of PUSHCSTADDR field.*/ + +/* PUSHREALIGN @Bit 29 : Realign length */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHREALIGN_Pos (29UL) /*!< Position of PUSHREALIGN field. */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHREALIGN_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHREALIGN_Pos) /*!< Bit + mask of PUSHREALIGN field.*/ + +/* PUSHDISCARD @Bit 30 : Discard data */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHDISCARD_Pos (30UL) /*!< Position of PUSHDISCARD field. */ + #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHDISCARD_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHDISCARD_Pos) /*!< Bit + mask of PUSHDISCARD field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_INTEN: Interrupt Enable mask */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERBLOCKEND_Pos) /*!< + Bit mask of FETCHERBLOCKEND field.*/ + +/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERSTOPPED_Pos) /*!< Bit + mask of FETCHERSTOPPED field.*/ + +/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERERROR_Pos) /*!< Bit mask + of FETCHERERROR field.*/ + +/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERBLOCKEND_Pos) /*!< Bit + mask of PUSHERBLOCKEND field.*/ + +/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERSTOPPED_Pos) /*!< Bit + mask of PUSHERSTOPPED field.*/ + +/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERERROR_Pos) /*!< Bit mask + of PUSHERERROR field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_INTENSET: Interrupt Set */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERBLOCKEND_Pos) + /*!< Bit mask of FETCHERBLOCKEND field.*/ + +/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERSTOPPED_Pos) + /*!< Bit mask of FETCHERSTOPPED field.*/ + +/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERERROR_Pos) /*!< + Bit mask of FETCHERERROR field.*/ + +/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERBLOCKEND_Pos) + /*!< Bit mask of PUSHERBLOCKEND field.*/ + +/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERSTOPPED_Pos) /*!< + Bit mask of PUSHERSTOPPED field.*/ + +/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERERROR_Pos) /*!< Bit + mask of PUSHERERROR field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_INTENCLR: Interrupt Clear */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERBLOCKEND_Pos) + /*!< Bit mask of FETCHERBLOCKEND field.*/ + +/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERSTOPPED_Pos) + /*!< Bit mask of FETCHERSTOPPED field.*/ + +/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERERROR_Pos) /*!< + Bit mask of FETCHERERROR field.*/ + +/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERBLOCKEND_Pos) + /*!< Bit mask of PUSHERBLOCKEND field.*/ + +/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERSTOPPED_Pos) /*!< + Bit mask of PUSHERSTOPPED field.*/ + +/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERERROR_Pos) /*!< Bit + mask of PUSHERERROR field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_INTSTATRAW: Interrupt Status Raw */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_ResetValue (0x00000000UL) /*!< Reset value of INTSTATRAW register. */ + +/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERBLOCKEND_Pos) + /*!< Bit mask of FETCHERBLOCKEND field.*/ + +/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERSTOPPED_Pos) + /*!< Bit mask of FETCHERSTOPPED field.*/ + +/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERERROR_Pos) + /*!< Bit mask of FETCHERERROR field.*/ + +/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERBLOCKEND_Pos) + /*!< Bit mask of PUSHERBLOCKEND field.*/ + +/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERSTOPPED_Pos) + /*!< Bit mask of PUSHERSTOPPED field.*/ + +/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERERROR_Pos) /*!< + Bit mask of PUSHERERROR field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_INTSTAT: Interrupt Status */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_ResetValue (0x00000000UL) /*!< Reset value of INTSTAT register. */ + +/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERBLOCKEND_Pos) + /*!< Bit mask of FETCHERBLOCKEND field.*/ + +/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERSTOPPED_Pos) /*!< + Bit mask of FETCHERSTOPPED field.*/ + +/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERERROR_Pos) /*!< Bit + mask of FETCHERERROR field.*/ + +/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERBLOCKEND_Pos) /*!< + Bit mask of PUSHERBLOCKEND field.*/ + +/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERSTOPPED_Pos) /*!< + Bit mask of PUSHERSTOPPED field.*/ + +/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERERROR_Pos) /*!< Bit + mask of PUSHERERROR field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_INTSTATCLR: Interrupt Status Clear */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_ResetValue (0x00000000UL) /*!< Reset value of INTSTATCLR register. */ + +/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERBLOCKEND_Pos) + /*!< Bit mask of FETCHERBLOCKEND field.*/ + +/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERSTOPPED_Pos) + /*!< Bit mask of FETCHERSTOPPED field.*/ + +/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERERROR_Pos) + /*!< Bit mask of FETCHERERROR field.*/ + +/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERBLOCKEND_Pos) + /*!< Bit mask of PUSHERBLOCKEND field.*/ + +/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERSTOPPED_Pos) + /*!< Bit mask of PUSHERSTOPPED field.*/ + +/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field. */ + #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERERROR_Pos) /*!< + Bit mask of PUSHERERROR field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_CONFIG: Cryptomaster configuration */ + #define CRACENCORE_CRYPTMSTRDMA_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* FETCHCTRLINDIRECT @Bit 0 : Fetcher scatter/gather. */ + #define CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHCTRLINDIRECT_Pos (0UL) /*!< Position of FETCHCTRLINDIRECT field. */ + #define CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHCTRLINDIRECT_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHCTRLINDIRECT_Pos) + /*!< Bit mask of FETCHCTRLINDIRECT field.*/ + +/* PUSHCTRLINDIRECT @Bit 1 : Pusher scatter/gather. */ + #define CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHCTRLINDIRECT_Pos (1UL) /*!< Position of PUSHCTRLINDIRECT field. */ + #define CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHCTRLINDIRECT_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHCTRLINDIRECT_Pos) + /*!< Bit mask of PUSHCTRLINDIRECT field.*/ + +/* FETCHSTOP @Bit 2 : Stop fetcher. */ + #define CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHSTOP_Pos (2UL) /*!< Position of FETCHSTOP field. */ + #define CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHSTOP_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHSTOP_Pos) /*!< Bit mask of + FETCHSTOP field.*/ + +/* PUSHSTOP @Bit 3 : Stop pusher DMA. */ + #define CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHSTOP_Pos (3UL) /*!< Position of PUSHSTOP field. */ + #define CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHSTOP_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHSTOP_Pos) /*!< Bit mask of + PUSHSTOP field.*/ + +/* SOFTRST @Bit 4 : Soft reset the cryptomaster. */ + #define CRACENCORE_CRYPTMSTRDMA_CONFIG_SOFTRST_Pos (4UL) /*!< Position of SOFTRST field. */ + #define CRACENCORE_CRYPTMSTRDMA_CONFIG_SOFTRST_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_CONFIG_SOFTRST_Pos) /*!< Bit mask of + SOFTRST field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_START: Start */ + #define CRACENCORE_CRYPTMSTRDMA_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* STARTFETCH @Bit 0 : Writing a '1' starts the fetcher DMA. Writing a '0' has no effect. */ + #define CRACENCORE_CRYPTMSTRDMA_START_STARTFETCH_Pos (0UL) /*!< Position of STARTFETCH field. */ + #define CRACENCORE_CRYPTMSTRDMA_START_STARTFETCH_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_START_STARTFETCH_Pos) /*!< Bit mask of + STARTFETCH field.*/ + +/* STARTPUSH @Bit 1 : Writing a '1' starts the pusher DMA. Writing a '0' has no effect. */ + #define CRACENCORE_CRYPTMSTRDMA_START_STARTPUSH_Pos (1UL) /*!< Position of STARTPUSH field. */ + #define CRACENCORE_CRYPTMSTRDMA_START_STARTPUSH_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_START_STARTPUSH_Pos) /*!< Bit mask of + STARTPUSH field.*/ + + +/* CRACENCORE_CRYPTMSTRDMA_STATUS: Status */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* FETCHBUSY @Bit 0 : This bit is high as long as the fetcher DMA is busy. */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHBUSY_Pos (0UL) /*!< Position of FETCHBUSY field. */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHBUSY_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHBUSY_Pos) /*!< Bit mask of + FETCHBUSY field.*/ + +/* PUSHBUSY @Bit 1 : This bit is high as long as the pusher DMA is busy. */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHBUSY_Pos (1UL) /*!< Position of PUSHBUSY field. */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHBUSY_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHBUSY_Pos) /*!< Bit mask of + PUSHBUSY field.*/ + +/* FETCHNOTEMPTY @Bit 4 : Not empty flag for fetcher DMA input FIFO */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHNOTEMPTY_Pos (4UL) /*!< Position of FETCHNOTEMPTY field. */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHNOTEMPTY_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHNOTEMPTY_Pos) /*!< Bit + mask of FETCHNOTEMPTY field.*/ + +/* PUSHWAITINGFIFO @Bit 5 : Pusher DMA Waiting FIFO. This bit is high when the pusher is waiting for more data in output FIFO. */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHWAITINGFIFO_Pos (5UL) /*!< Position of PUSHWAITINGFIFO field. */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHWAITINGFIFO_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHWAITINGFIFO_Pos) /*!< + Bit mask of PUSHWAITINGFIFO field.*/ + +/* SOFTRSTBUSY @Bit 6 : This bit is high when the soft reset is on going */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_SOFTRSTBUSY_Pos (6UL) /*!< Position of SOFTRSTBUSY field. */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_SOFTRSTBUSY_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_STATUS_SOFTRSTBUSY_Pos) /*!< Bit mask + of SOFTRSTBUSY field.*/ + +/* PUSHNBDATA @Bits 16..31 : Amount of data in the pusher DMA output FIFO */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHNBDATA_Pos (16UL) /*!< Position of PUSHNBDATA field. */ + #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHNBDATA_Msk (0xFFFFUL << CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHNBDATA_Pos) /*!< Bit + mask of PUSHNBDATA field.*/ + + + +/* ============================================== Struct CRACENCORE_CRYPTMSTRHW ============================================== */ +/** + * @brief CRYPTMSTRHW [CRACENCORE_CRYPTMSTRHW] (unspecified) + */ +typedef struct { + __IOM uint32_t INCLIPSHWCFG; /*!< (@ 0x00000000) Incuded IPs Hardware configuration */ + __IOM uint32_t BA411EAESHWCFG1; /*!< (@ 0x00000004) Generic g_AesModesPoss value. */ + __IOM uint32_t BA411EAESHWCFG2; /*!< (@ 0x00000008) Generic g_CtrSize value. */ + __IOM uint32_t BA413HASHHWCFG; /*!< (@ 0x0000000C) Generic g_Hash value */ + __IOM uint32_t BA418SHA3HWCFG; /*!< (@ 0x00000010) Generic g_Sha3CtxtEn value. */ + __IOM uint32_t BA419SM4HWCFG; /*!< (@ 0x00000014) Generic g_SM4ModesPoss value. */ + __IOM uint32_t BA424ARIAHWCFG; /*!< (@ 0x00000018) Generic g_aria_modePoss value. */ +} NRF_CRACENCORE_CRYPTMSTRHW_Type; /*!< Size = 28 (0x01C) */ + +/* CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG: Incuded IPs Hardware configuration */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_ResetValue (0x00000671UL) /*!< Reset value of INCLIPSHWCFG register. */ + +/* BA411AESINCLUDED @Bit 0 : Generic g_IncludeAES value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA411AESINCLUDED_Pos (0UL) /*!< Position of BA411AESINCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA411AESINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA411AESINCLUDED_Pos) + /*!< Bit mask of BA411AESINCLUDED field.*/ + +/* BA415HPAESGCMINCLUDED @Bit 1 : Generic g_IncludeAESGCM value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA415HPAESGCMINCLUDED_Pos (1UL) /*!< Position of BA415HPAESGCMINCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA415HPAESGCMINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA415HPAESGCMINCLUDED_Pos) + /*!< Bit mask of BA415HPAESGCMINCLUDED field.*/ + +/* BA416HPAESXTSINCLUDED @Bit 2 : Generic g_IncludeAESXTS value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA416HPAESXTSINCLUDED_Pos (2UL) /*!< Position of BA416HPAESXTSINCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA416HPAESXTSINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA416HPAESXTSINCLUDED_Pos) + /*!< Bit mask of BA416HPAESXTSINCLUDED field.*/ + +/* BA412DESINCLUDED @Bit 3 : Generic g_IncludeDES value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA412DESINCLUDED_Pos (3UL) /*!< Position of BA412DESINCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA412DESINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA412DESINCLUDED_Pos) + /*!< Bit mask of BA412DESINCLUDED field.*/ + +/* BA413HASHINCLUDED @Bit 4 : Generic g_IncludeHASH value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA413HASHINCLUDED_Pos (4UL) /*!< Position of BA413HASHINCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA413HASHINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA413HASHINCLUDED_Pos) + /*!< Bit mask of BA413HASHINCLUDED field.*/ + +/* BA417CHACHAPOLYINCLUDED @Bit 5 : Generic g_IncludeChachaPoly value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA417CHACHAPOLYINCLUDED_Pos (5UL) /*!< Position of BA417CHACHAPOLYINCLUDED field.*/ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA417CHACHAPOLYINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA417CHACHAPOLYINCLUDED_Pos) + /*!< Bit mask of BA417CHACHAPOLYINCLUDED field.*/ + +/* BA418SHA3INCLUDED @Bit 6 : Generic g_IncludeSHA3 value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA418SHA3INCLUDED_Pos (6UL) /*!< Position of BA418SHA3INCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA418SHA3INCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA418SHA3INCLUDED_Pos) + /*!< Bit mask of BA418SHA3INCLUDED field.*/ + +/* BA421ZUCINCLUDED @Bit 7 : Generic g_IncludeZUC value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA421ZUCINCLUDED_Pos (7UL) /*!< Position of BA421ZUCINCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA421ZUCINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA421ZUCINCLUDED_Pos) + /*!< Bit mask of BA421ZUCINCLUDED field.*/ + +/* BA419SM4INCLUDED @Bit 8 : Generic g_IncludeSM4 value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA419SM4INCLUDED_Pos (8UL) /*!< Position of BA419SM4INCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA419SM4INCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA419SM4INCLUDED_Pos) + /*!< Bit mask of BA419SM4INCLUDED field.*/ + +/* BA414EPPKEINCLUDED @Bit 9 : Generic g_IncludePKE value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA414EPPKEINCLUDED_Pos (9UL) /*!< Position of BA414EPPKEINCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA414EPPKEINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA414EPPKEINCLUDED_Pos) + /*!< Bit mask of BA414EPPKEINCLUDED field.*/ + +/* BA431NDRNGINCLUDED @Bit 10 : Generic g_IncludeNDRNG value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA431NDRNGINCLUDED_Pos (10UL) /*!< Position of BA431NDRNGINCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA431NDRNGINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA431NDRNGINCLUDED_Pos) + /*!< Bit mask of BA431NDRNGINCLUDED field.*/ + +/* BA420HPCHACHAPOLYINCLUDED @Bit 11 : Generic g_IncludeHPChachaPoly value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA420HPCHACHAPOLYINCLUDED_Pos (11UL) /*!< Position of BA420HPCHACHAPOLYINCLUDED + field.*/ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA420HPCHACHAPOLYINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA420HPCHACHAPOLYINCLUDED_Pos) + /*!< Bit mask of BA420HPCHACHAPOLYINCLUDED field.*/ + +/* BA423SNOW3GINCLUDED @Bit 12 : Generic g_IncludeSnow3G value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA423SNOW3GINCLUDED_Pos (12UL) /*!< Position of BA423SNOW3GINCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA423SNOW3GINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA423SNOW3GINCLUDED_Pos) + /*!< Bit mask of BA423SNOW3GINCLUDED field.*/ + +/* BA422KASUMIINCLUDED @Bit 13 : Generic g_IncludeKasumi value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA422KASUMIINCLUDED_Pos (13UL) /*!< Position of BA422KASUMIINCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA422KASUMIINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA422KASUMIINCLUDED_Pos) + /*!< Bit mask of BA422KASUMIINCLUDED field.*/ + +/* BA422ARIAINCLUDED @Bit 14 : Generic g_IncludeAria value. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA422ARIAINCLUDED_Pos (14UL) /*!< Position of BA422ARIAINCLUDED field. */ + #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA422ARIAINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA422ARIAINCLUDED_Pos) + /*!< Bit mask of BA422ARIAINCLUDED field.*/ + + +/* CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1: Generic g_AesModesPoss value. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_ResetValue (0x1D020167UL) /*!< Reset value of BA411EAESHWCFG1 register. */ + +/* BA411EAESHWCFGMODE @Bits 0..8 : Generic g_AesModesPoss value. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMODE_Pos (0UL) /*!< Position of BA411EAESHWCFGMODE field. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMODE_Msk (0x1FFUL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMODE_Pos) + /*!< Bit mask of BA411EAESHWCFGMODE field.*/ + +/* BA411EAESHWCFGCS @Bit 16 : Generic g_CS value. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGCS_Pos (16UL) /*!< Position of BA411EAESHWCFGCS field. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGCS_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGCS_Pos) + /*!< Bit mask of BA411EAESHWCFGCS field.*/ + +/* BA411EAESHWCFGMASKING @Bit 17 : Generic g_UseMasking value. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMASKING_Pos (17UL) /*!< Position of BA411EAESHWCFGMASKING field.*/ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMASKING_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMASKING_Pos) + /*!< Bit mask of BA411EAESHWCFGMASKING field.*/ + +/* BA411EAESHWCFGKEYSIZE @Bits 24..26 : Generic g_Keysize value. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGKEYSIZE_Pos (24UL) /*!< Position of BA411EAESHWCFGKEYSIZE field.*/ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGKEYSIZE_Msk (0x7UL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGKEYSIZE_Pos) + /*!< Bit mask of BA411EAESHWCFGKEYSIZE field.*/ + +/* CONTEXTEN @Bit 27 : Generic g_CxSwitch value. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_CONTEXTEN_Pos (27UL) /*!< Position of CONTEXTEN field. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_CONTEXTEN_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_CONTEXTEN_Pos) + /*!< Bit mask of CONTEXTEN field.*/ + +/* GLITCHPROT @Bit 28 : Generic g_GlitchProtection value. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_GLITCHPROT_Pos (28UL) /*!< Position of GLITCHPROT field. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_GLITCHPROT_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_GLITCHPROT_Pos) + /*!< Bit mask of GLITCHPROT field.*/ + + +/* CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2: Generic g_CtrSize value. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_ResetValue (0x02000010UL) /*!< Reset value of BA411EAESHWCFG2 register. */ + +/* BA411EAESHWCFG2 @Bits 0..15 : Maximum size in bits for the counter in CTR and CCM modes (g_CtrSize value). */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_BA411EAESHWCFG2_Pos (0UL) /*!< Position of BA411EAESHWCFG2 field. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_BA411EAESHWCFG2_Msk (0xFFFFUL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_BA411EAESHWCFG2_Pos) + /*!< Bit mask of BA411EAESHWCFG2 field.*/ + +/* NBEXTAESKEYS @Bits 20..23 : Generic g_Ext_nb_AES_keys value. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_NBEXTAESKEYS_Pos (20UL) /*!< Position of NBEXTAESKEYS field. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_NBEXTAESKEYS_Msk (0xFUL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_NBEXTAESKEYS_Pos) + /*!< Bit mask of NBEXTAESKEYS field.*/ + +/* NBIKGAESKEYS @Bits 24..27 : Generic g_IKG_nb_AES_keys value. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_NBIKGAESKEYS_Pos (24UL) /*!< Position of NBIKGAESKEYS field. */ + #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_NBIKGAESKEYS_Msk (0xFUL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_NBIKGAESKEYS_Pos) + /*!< Bit mask of NBIKGAESKEYS field.*/ + + +/* CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG: Generic g_Hash value */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_ResetValue (0x0001003EUL) /*!< Reset value of BA413HASHHWCFG register. */ + +/* BA413HASHHWCFGMASK @Bits 0..6 : Generic g_HashMaskFunc value. */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGMASK_Pos (0UL) /*!< Position of BA413HASHHWCFGMASK field. */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGMASK_Msk (0x7FUL << CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGMASK_Pos) + /*!< Bit mask of BA413HASHHWCFGMASK field.*/ + +/* BA413HASHHWCFGPADDING @Bit 16 : Generic g_HashPadding value. */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGPADDING_Pos (16UL) /*!< Position of BA413HASHHWCFGPADDING field. */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGPADDING_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGPADDING_Pos) + /*!< Bit mask of BA413HASHHWCFGPADDING field.*/ + +/* BA413HASHHWCFGHMAC @Bit 17 : Generic g_HMAC_enabled value. */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGHMAC_Pos (17UL) /*!< Position of BA413HASHHWCFGHMAC field. */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGHMAC_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGHMAC_Pos) + /*!< Bit mask of BA413HASHHWCFGHMAC field.*/ + +/* BA413HASHHWCFGVERIFYDIGEST @Bit 18 : Generic g_HashVerifyDigest value. */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGVERIFYDIGEST_Pos (18UL) /*!< Position of + BA413HASHHWCFGVERIFYDIGEST field.*/ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGVERIFYDIGEST_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGVERIFYDIGEST_Pos) + /*!< Bit mask of BA413HASHHWCFGVERIFYDIGEST field.*/ + +/* NBEXTHASHKEYS @Bits 20..23 : Generic g_Ext_nb_Hash_keys value. */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_NBEXTHASHKEYS_Pos (20UL) /*!< Position of NBEXTHASHKEYS field. */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_NBEXTHASHKEYS_Msk (0xFUL << CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_NBEXTHASHKEYS_Pos) + /*!< Bit mask of NBEXTHASHKEYS field.*/ + +/* NBIKGHASHKEYS @Bits 24..27 : Generic g_IKG_nb_Hash_keys value. */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_NBIKGHASHKEYS_Pos (24UL) /*!< Position of NBIKGHASHKEYS field. */ + #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_NBIKGHASHKEYS_Msk (0xFUL << CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_NBIKGHASHKEYS_Pos) + /*!< Bit mask of NBIKGHASHKEYS field.*/ + + +/* CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG: Generic g_Sha3CtxtEn value. */ + #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_ResetValue (0x00000001UL) /*!< Reset value of BA418SHA3HWCFG register. */ + +/* BA418SHA3HWCFG @Bit 0 : Generic g_Sha3CtxtEn value. */ + #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_BA418SHA3HWCFG_Pos (0UL) /*!< Position of BA418SHA3HWCFG field. */ + #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_BA418SHA3HWCFG_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_BA418SHA3HWCFG_Pos) + /*!< Bit mask of BA418SHA3HWCFG field.*/ + +/* HMAC @Bit 17 : HMAC enabled. */ + #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_HMAC_Pos (17UL) /*!< Position of HMAC field. */ + #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_HMAC_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_HMAC_Pos) /*!< Bit mask + of HMAC field.*/ + +/* VERIFYDIGEST @Bit 18 : Support to digest verification. */ + #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_VERIFYDIGEST_Pos (18UL) /*!< Position of VERIFYDIGEST field. */ + #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_VERIFYDIGEST_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_VERIFYDIGEST_Pos) + /*!< Bit mask of VERIFYDIGEST field.*/ + +/* NBEXTHASHKEYS @Bits 20..23 : Number of SHA3 HW keys. */ + #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_NBEXTHASHKEYS_Pos (20UL) /*!< Position of NBEXTHASHKEYS field. */ + #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_NBEXTHASHKEYS_Msk (0xFUL << CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_NBEXTHASHKEYS_Pos) + /*!< Bit mask of NBEXTHASHKEYS field.*/ + +/* NBIKGHASHKEYS @Bits 24..27 : Number of SHA3 IKG keys. */ + #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_NBIKGHASHKEYS_Pos (24UL) /*!< Position of NBIKGHASHKEYS field. */ + #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_NBIKGHASHKEYS_Msk (0xFUL << CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_NBIKGHASHKEYS_Pos) + /*!< Bit mask of NBIKGHASHKEYS field.*/ + + +/* CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG: Generic g_SM4ModesPoss value. */ + #define CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_ResetValue (0x00000000UL) /*!< Reset value of BA419SM4HWCFG register. */ + +/* BA419SM4HWCFG @Bits 0..8 : Generic g_SM4ModesPoss value. */ + #define CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_BA419SM4HWCFG_Pos (0UL) /*!< Position of BA419SM4HWCFG field. */ + #define CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_BA419SM4HWCFG_Msk (0x1FFUL << CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_BA419SM4HWCFG_Pos) + /*!< Bit mask of BA419SM4HWCFG field.*/ + +/* USEMASKING @Bit 17 : Generic g_sm4UseMasking value. */ + #define CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_USEMASKING_Pos (17UL) /*!< Position of USEMASKING field. */ + #define CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_USEMASKING_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_USEMASKING_Pos) + /*!< Bit mask of USEMASKING field.*/ + + +/* CRACENCORE_CRYPTMSTRHW_BA424ARIAHWCFG: Generic g_aria_modePoss value. */ + #define CRACENCORE_CRYPTMSTRHW_BA424ARIAHWCFG_ResetValue (0x00000000UL) /*!< Reset value of BA424ARIAHWCFG register. */ + +/* BA424ARIAHWCFG @Bits 0..8 : Generic g_aria_modePoss value. */ + #define CRACENCORE_CRYPTMSTRHW_BA424ARIAHWCFG_BA424ARIAHWCFG_Pos (0UL) /*!< Position of BA424ARIAHWCFG field. */ + #define CRACENCORE_CRYPTMSTRHW_BA424ARIAHWCFG_BA424ARIAHWCFG_Msk (0x1FFUL << CRACENCORE_CRYPTMSTRHW_BA424ARIAHWCFG_BA424ARIAHWCFG_Pos) + /*!< Bit mask of BA424ARIAHWCFG field.*/ + + + +/* ============================================== Struct CRACENCORE_RNGCONTROL =============================================== */ +/** + * @brief RNGCONTROL [CRACENCORE_RNGCONTROL] (unspecified) + */ +typedef struct { + __IOM uint32_t CONTROL; /*!< (@ 0x00000000) Control register */ + __IOM uint32_t FIFOLEVEL; /*!< (@ 0x00000004) FIFO level register. */ + __IOM uint32_t FIFOTHRESHOLD; /*!< (@ 0x00000008) FIFO threshold register. */ + __IOM uint32_t FIFODEPTH; /*!< (@ 0x0000000C) FIFO depth register. */ + __IOM uint32_t KEY[4]; /*!< (@ 0x00000010) Key register. */ + __IOM uint32_t TESTDATA; /*!< (@ 0x00000020) Test data register. */ + __IOM uint32_t REPEATTHRESHOLD; /*!< (@ 0x00000024) Repetition test cut-off register. */ + __IOM uint32_t PROPTESTCUTOFF; /*!< (@ 0x00000028) Proportion test cut-off register. */ + __IOM uint32_t LFSRSEED; /*!< (@ 0x0000002C) LFSR seed register. */ + __IOM uint32_t STATUS; /*!< (@ 0x00000030) Status register. */ + __IOM uint32_t WARMUPPERIOD; /*!< (@ 0x00000034) Number of clock cycles in warm-up sequence. */ + __IOM uint32_t DISABLEOSC; /*!< (@ 0x00000038) DisableOsc register. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t SAMPLINGPERIOD; /*!< (@ 0x00000044) Number of clock cycles between sampling moments. */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t HWCONFIG; /*!< (@ 0x00000058) Hardware configuration register. */ + __IOM uint32_t COOLDOWNPERIOD; /*!< (@ 0x0000005C) Number of clock cycles in cool-down sequence. */ + __IOM uint32_t AUTOCORRTESTCUTOFF0; /*!< (@ 0x00000060) AutoCorrTestCutoff register 0 */ + __IOM uint32_t AUTOCORRTESTCUTOFF1; /*!< (@ 0x00000064) AutoCorrTestCutoff register 1 */ + __IOM uint32_t CORRTESTCUTOFF0; /*!< (@ 0x00000068) CorrTestCutoff register 0 */ + __IOM uint32_t CORRTESTCUTOFF1; /*!< (@ 0x0000006C) CorrTestCutoff register 1 */ + __IOM uint32_t AUTOCORRTESTFAILED; /*!< (@ 0x00000070) Auto-correlation test failing ring(s). */ + __IOM uint32_t CORRTESTFAILED; /*!< (@ 0x00000074) Correlation test failing ring. */ + __IM uint32_t RESERVED2; + __IOM uint32_t HWVERSION; /*!< (@ 0x0000007C) Fixed to 1 for this version. */ + __IM uint32_t FIFO[32]; /*!< (@ 0x00000080) FIFO data */ +} NRF_CRACENCORE_RNGCONTROL_Type; /*!< Size = 256 (0x100) */ + +/* CRACENCORE_RNGCONTROL_CONTROL: Control register */ + #define CRACENCORE_RNGCONTROL_CONTROL_ResetValue (0x00040000UL) /*!< Reset value of CONTROL register. */ + +/* ENABLE @Bit 0 : Start the NDRNG. Self-clearing bit. */ + #define CRACENCORE_RNGCONTROL_CONTROL_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_ENABLE_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_ENABLE_Pos) /*!< Bit mask of ENABLE + field.*/ + +/* LFSREN @Bit 1 : Select between the NDRNG with asynchronous free running oscillators (when 0) and the Pseudo-Random generator + with synchronous oscillators for simulation purpose (when 1). */ + + #define CRACENCORE_RNGCONTROL_CONTROL_LFSREN_Pos (1UL) /*!< Position of LFSREN field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_LFSREN_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_LFSREN_Pos) /*!< Bit mask of LFSREN + field.*/ + +/* TESTEN @Bit 2 : Select input for conditioning function and continuous tests: */ + #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_Pos (2UL) /*!< Position of TESTEN field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_TESTEN_Pos) /*!< Bit mask of TESTEN + field.*/ + #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_Min (0x0UL) /*!< Min enumerator value of TESTEN field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_Max (0x1UL) /*!< Max enumerator value of TESTEN field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_NORMAL (0x0UL) /*!< Noise source (normal mode). */ + #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_TEST (0x1UL) /*!< Test data register (test mode). */ + +/* CONDBYPASS @Bit 3 : Conditioning function bypass. */ + #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_Pos (3UL) /*!< Position of CONDBYPASS field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_Pos) /*!< Bit mask of + CONDBYPASS field.*/ + #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_Min (0x0UL) /*!< Min enumerator value of CONDBYPASS field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_Max (0x1UL) /*!< Max enumerator value of CONDBYPASS field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_NORMAL (0x0UL) /*!< the conditioning function is used (normal mode). */ + #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_BYPASS (0x1UL) /*!< the conditioning function is bypassed (to observe entropy + source directly).*/ + +/* INTENREP @Bit 4 : Enable interrupt if any of the health test fails. */ + #define CRACENCORE_RNGCONTROL_CONTROL_INTENREP_Pos (4UL) /*!< Position of INTENREP field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_INTENREP_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_INTENREP_Pos) /*!< Bit mask of + INTENREP field.*/ + +/* INTENFULL @Bit 7 : Enable interrupt if FIFO is full. */ + #define CRACENCORE_RNGCONTROL_CONTROL_INTENFULL_Pos (7UL) /*!< Position of INTENFULL field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_INTENFULL_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_INTENFULL_Pos) /*!< Bit mask of + INTENFULL field.*/ + +/* SOFTRST @Bit 8 : Datapath content flush and control FSM */ + #define CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_Pos (8UL) /*!< Position of SOFTRST field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_Pos) /*!< Bit mask of + SOFTRST field.*/ + +/* FORCEACTIVEROS @Bit 11 : Force oscillators to run when FIFO is full. */ + #define CRACENCORE_RNGCONTROL_CONTROL_FORCEACTIVEROS_Pos (11UL) /*!< Position of FORCEACTIVEROS field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_FORCEACTIVEROS_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_FORCEACTIVEROS_Pos) /*!< Bit + mask of FORCEACTIVEROS field.*/ + +/* IGNOREHEALTHTESTSFAILFORFSM @Bit 12 : Results of the health tests during start-up and online test do not affect the control + FSM state. */ + + #define CRACENCORE_RNGCONTROL_CONTROL_IGNOREHEALTHTESTSFAILFORFSM_Pos (12UL) /*!< Position of IGNOREHEALTHTESTSFAILFORFSM + field.*/ + #define CRACENCORE_RNGCONTROL_CONTROL_IGNOREHEALTHTESTSFAILFORFSM_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_IGNOREHEALTHTESTSFAILFORFSM_Pos) + /*!< Bit mask of IGNOREHEALTHTESTSFAILFORFSM field.*/ + +/* NB128BITBLOCKS @Bits 16..19 : Number of 128 bit blocks used in conditioning (AES-CBC-MAC) post-processing. */ + #define CRACENCORE_RNGCONTROL_CONTROL_NB128BITBLOCKS_Pos (16UL) /*!< Position of NB128BITBLOCKS field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_NB128BITBLOCKS_Msk (0xFUL << CRACENCORE_RNGCONTROL_CONTROL_NB128BITBLOCKS_Pos) /*!< Bit + mask of NB128BITBLOCKS field.*/ + +/* FIFOWRITESTARTUP @Bit 20 : Enable write of the samples in the FIFO during start-up. */ + #define CRACENCORE_RNGCONTROL_CONTROL_FIFOWRITESTARTUP_Pos (20UL) /*!< Position of FIFOWRITESTARTUP field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_FIFOWRITESTARTUP_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_FIFOWRITESTARTUP_Pos) /*!< + Bit mask of FIFOWRITESTARTUP field.*/ + +/* DISREPETTESTS @Bit 21 : All repetition tests (each share) are disabled via this single bit. */ + #define CRACENCORE_RNGCONTROL_CONTROL_DISREPETTESTS_Pos (21UL) /*!< Position of DISREPETTESTS field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_DISREPETTESTS_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_DISREPETTESTS_Pos) /*!< Bit + mask of DISREPETTESTS field.*/ + +/* DISPROPTESTS @Bit 22 : All proportion tests (each share) are disabled via this single bit. */ + #define CRACENCORE_RNGCONTROL_CONTROL_DISPROPTESTS_Pos (22UL) /*!< Position of DISPROPTESTS field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_DISPROPTESTS_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_DISPROPTESTS_Pos) /*!< Bit mask + of DISPROPTESTS field.*/ + +/* DISAUTOCORRTESTS @Bits 23..24 : Disable specific delay(s) check in auto-correlation test - same RO: */ + #define CRACENCORE_RNGCONTROL_CONTROL_DISAUTOCORRTESTS_Pos (23UL) /*!< Position of DISAUTOCORRTESTS field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_DISAUTOCORRTESTS_Msk (0x3UL << CRACENCORE_RNGCONTROL_CONTROL_DISAUTOCORRTESTS_Pos) /*!< + Bit mask of DISAUTOCORRTESTS field.*/ + +/* DISCORRTESTS @Bits 27..29 : Disable specific delay(s) check in correlation test - different ROs: */ + #define CRACENCORE_RNGCONTROL_CONTROL_DISCORRTESTS_Pos (27UL) /*!< Position of DISCORRTESTS field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_DISCORRTESTS_Msk (0x7UL << CRACENCORE_RNGCONTROL_CONTROL_DISCORRTESTS_Pos) /*!< Bit mask + of DISCORRTESTS field.*/ + +/* BLENDINGMETHOD @Bits 30..31 : Select blending method */ + #define CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_Pos (30UL) /*!< Position of BLENDINGMETHOD field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_Msk (0x3UL << CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_Pos) /*!< Bit + mask of BLENDINGMETHOD field.*/ + #define CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_Min (0x0UL) /*!< Min enumerator value of BLENDINGMETHOD field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_Max (0x3UL) /*!< Max enumerator value of BLENDINGMETHOD field. */ + #define CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_CONCATENATION (0x0UL) /*!< Concatenation */ + #define CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_XORLEVEL1 (0x1UL) /*!< XOR level 1 */ + #define CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_XORLEVEL2 (0x2UL) /*!< XOR level 2 */ + #define CRACENCORE_RNGCONTROL_CONTROL_BLENDINGMETHOD_VONNEUMANN (0x3UL) /*!< VON-NEUMANN debiasing */ + + +/* CRACENCORE_RNGCONTROL_FIFOLEVEL: FIFO level register. */ + #define CRACENCORE_RNGCONTROL_FIFOLEVEL_ResetValue (0x00000000UL) /*!< Reset value of FIFOLEVEL register. */ + +/* FIFOLEVEL @Bits 0..31 : Number of 32 bits words of random values available in the FIFO. */ + #define CRACENCORE_RNGCONTROL_FIFOLEVEL_FIFOLEVEL_Pos (0UL) /*!< Position of FIFOLEVEL field. */ + #define CRACENCORE_RNGCONTROL_FIFOLEVEL_FIFOLEVEL_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_FIFOLEVEL_FIFOLEVEL_Pos) /*!< Bit + mask of FIFOLEVEL field.*/ + + +/* CRACENCORE_RNGCONTROL_FIFOTHRESHOLD: FIFO threshold register. */ + #define CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_ResetValue (0x00000003UL) /*!< Reset value of FIFOTHRESHOLD register. */ + +/* FIFOTHRESHOLD @Bits 0..2 : FIFO level threshold below which the module leaves the idle state to refill the FIFO. Expressed in + number of 128bit blocks. */ + + #define CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_FIFOTHRESHOLD_Pos (0UL) /*!< Position of FIFOTHRESHOLD field. */ + #define CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_FIFOTHRESHOLD_Msk (0x7UL << CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_FIFOTHRESHOLD_Pos) + /*!< Bit mask of FIFOTHRESHOLD field.*/ + + +/* CRACENCORE_RNGCONTROL_FIFODEPTH: FIFO depth register. */ + #define CRACENCORE_RNGCONTROL_FIFODEPTH_ResetValue (0x00000010UL) /*!< Reset value of FIFODEPTH register. */ + +/* FIFODEPTH @Bits 0..31 : Maximum number of 32 bits words that can be stored in the FIFO. */ + #define CRACENCORE_RNGCONTROL_FIFODEPTH_FIFODEPTH_Pos (0UL) /*!< Position of FIFODEPTH field. */ + #define CRACENCORE_RNGCONTROL_FIFODEPTH_FIFODEPTH_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_FIFODEPTH_FIFODEPTH_Pos) /*!< Bit + mask of FIFODEPTH field.*/ + + +/* CRACENCORE_RNGCONTROL_KEY: Key register. */ + #define CRACENCORE_RNGCONTROL_KEY_MaxCount (4UL) /*!< Max size of KEY[4] array. */ + #define CRACENCORE_RNGCONTROL_KEY_MaxIndex (3UL) /*!< Max index of KEY[4] array. */ + #define CRACENCORE_RNGCONTROL_KEY_MinIndex (0UL) /*!< Min index of KEY[4] array. */ + #define CRACENCORE_RNGCONTROL_KEY_ResetValue (0x00000000UL) /*!< Reset value of KEY[4] register. */ + +/* KEY @Bits 0..31 : Key register. */ + #define CRACENCORE_RNGCONTROL_KEY_KEY_Pos (0UL) /*!< Position of KEY field. */ + #define CRACENCORE_RNGCONTROL_KEY_KEY_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_KEY_KEY_Pos) /*!< Bit mask of KEY field. */ + + +/* CRACENCORE_RNGCONTROL_TESTDATA: Test data register. */ + #define CRACENCORE_RNGCONTROL_TESTDATA_ResetValue (0x00000000UL) /*!< Reset value of TESTDATA register. */ + +/* TESTDATA @Bits 0..31 : Test data register. */ + #define CRACENCORE_RNGCONTROL_TESTDATA_TESTDATA_Pos (0UL) /*!< Position of TESTDATA field. */ + #define CRACENCORE_RNGCONTROL_TESTDATA_TESTDATA_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_TESTDATA_TESTDATA_Pos) /*!< Bit + mask of TESTDATA field.*/ + + +/* CRACENCORE_RNGCONTROL_REPEATTHRESHOLD: Repetition test cut-off register. */ + #define CRACENCORE_RNGCONTROL_REPEATTHRESHOLD_ResetValue (0x00000004UL) /*!< Reset value of REPEATTHRESHOLD register. */ + +/* REPEATTHRESHOLD @Bits 0..5 : Repetition Test cut-off value. */ + #define CRACENCORE_RNGCONTROL_REPEATTHRESHOLD_REPEATTHRESHOLD_Pos (0UL) /*!< Position of REPEATTHRESHOLD field. */ + #define CRACENCORE_RNGCONTROL_REPEATTHRESHOLD_REPEATTHRESHOLD_Msk (0x3FUL << CRACENCORE_RNGCONTROL_REPEATTHRESHOLD_REPEATTHRESHOLD_Pos) + /*!< Bit mask of REPEATTHRESHOLD field.*/ + + +/* CRACENCORE_RNGCONTROL_PROPTESTCUTOFF: Proportion test cut-off register. */ + #define CRACENCORE_RNGCONTROL_PROPTESTCUTOFF_ResetValue (0x0000000DUL) /*!< Reset value of PROPTESTCUTOFF register. */ + +/* PROPTESTCUTOFF @Bits 0..8 : Proportion test cut-off value. */ + #define CRACENCORE_RNGCONTROL_PROPTESTCUTOFF_PROPTESTCUTOFF_Pos (0UL) /*!< Position of PROPTESTCUTOFF field. */ + #define CRACENCORE_RNGCONTROL_PROPTESTCUTOFF_PROPTESTCUTOFF_Msk (0x1FFUL << CRACENCORE_RNGCONTROL_PROPTESTCUTOFF_PROPTESTCUTOFF_Pos) + /*!< Bit mask of PROPTESTCUTOFF field.*/ + + +/* CRACENCORE_RNGCONTROL_LFSRSEED: LFSR seed register. */ + #define CRACENCORE_RNGCONTROL_LFSRSEED_ResetValue (0x00FFFFFFUL) /*!< Reset value of LFSRSEED register. */ + +/* LFSRSEED @Bits 0..23 : LFSR initialization value. */ + #define CRACENCORE_RNGCONTROL_LFSRSEED_LFSRSEED_Pos (0UL) /*!< Position of LFSRSEED field. */ + #define CRACENCORE_RNGCONTROL_LFSRSEED_LFSRSEED_Msk (0xFFFFFFUL << CRACENCORE_RNGCONTROL_LFSRSEED_LFSRSEED_Pos) /*!< Bit mask + of LFSRSEED field.*/ + +/* LFSRSSELECTION @Bits 24..25 : Share index for which initialization value should be used. */ + #define CRACENCORE_RNGCONTROL_LFSRSEED_LFSRSSELECTION_Pos (24UL) /*!< Position of LFSRSSELECTION field. */ + #define CRACENCORE_RNGCONTROL_LFSRSEED_LFSRSSELECTION_Msk (0x3UL << CRACENCORE_RNGCONTROL_LFSRSEED_LFSRSSELECTION_Pos) /*!< + Bit mask of LFSRSSELECTION field.*/ + + +/* CRACENCORE_RNGCONTROL_STATUS: Status register. */ + #define CRACENCORE_RNGCONTROL_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* TESTDATABUSY @Bit 0 : High when data written to TestData register is being processed. */ + #define CRACENCORE_RNGCONTROL_STATUS_TESTDATABUSY_Pos (0UL) /*!< Position of TESTDATABUSY field. */ + #define CRACENCORE_RNGCONTROL_STATUS_TESTDATABUSY_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_TESTDATABUSY_Pos) /*!< Bit mask + of TESTDATABUSY field.*/ + +/* STATE @Bits 1..3 : State of the control FSM: */ + #define CRACENCORE_RNGCONTROL_STATUS_STATE_Pos (1UL) /*!< Position of STATE field. */ + #define CRACENCORE_RNGCONTROL_STATUS_STATE_Msk (0x7UL << CRACENCORE_RNGCONTROL_STATUS_STATE_Pos) /*!< Bit mask of STATE + field.*/ + #define CRACENCORE_RNGCONTROL_STATUS_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field. */ + #define CRACENCORE_RNGCONTROL_STATUS_STATE_Max (0x5UL) /*!< Max enumerator value of STATE field. */ + #define CRACENCORE_RNGCONTROL_STATUS_STATE_RESET (0x0UL) /*!< Reset */ + #define CRACENCORE_RNGCONTROL_STATUS_STATE_STARTUP (0x1UL) /*!< Startup */ + #define CRACENCORE_RNGCONTROL_STATUS_STATE_IDLERON (0x2UL) /*!< Idle / FIFO full */ + #define CRACENCORE_RNGCONTROL_STATUS_STATE_FILLFIFO (0x4UL) /*!< Fill FIFO */ + #define CRACENCORE_RNGCONTROL_STATUS_STATE_ERROR (0x5UL) /*!< Error */ + +/* REPFAIL @Bit 4 : NIST repetition test(s) failure. */ + #define CRACENCORE_RNGCONTROL_STATUS_REPFAIL_Pos (4UL) /*!< Position of REPFAIL field. */ + #define CRACENCORE_RNGCONTROL_STATUS_REPFAIL_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_REPFAIL_Pos) /*!< Bit mask of REPFAIL + field.*/ + +/* PROPFAIL @Bit 5 : NIST proportion test(s) failure. */ + #define CRACENCORE_RNGCONTROL_STATUS_PROPFAIL_Pos (5UL) /*!< Position of PROPFAIL field. */ + #define CRACENCORE_RNGCONTROL_STATUS_PROPFAIL_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_PROPFAIL_Pos) /*!< Bit mask of + PROPFAIL field.*/ + +/* ANYHEALTHTESTFAIL @Bit 6 : Any of the enabled health tests is failing. */ + #define CRACENCORE_RNGCONTROL_STATUS_ANYHEALTHTESTFAIL_Pos (6UL) /*!< Position of ANYHEALTHTESTFAIL field. */ + #define CRACENCORE_RNGCONTROL_STATUS_ANYHEALTHTESTFAIL_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_ANYHEALTHTESTFAIL_Pos) /*!< + Bit mask of ANYHEALTHTESTFAIL field.*/ + +/* FULLINT @Bit 7 : FIFO full status. */ + #define CRACENCORE_RNGCONTROL_STATUS_FULLINT_Pos (7UL) /*!< Position of FULLINT field. */ + #define CRACENCORE_RNGCONTROL_STATUS_FULLINT_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_FULLINT_Pos) /*!< Bit mask of FULLINT + field.*/ + +/* STARTUPFAIL @Bit 10 : Start-up test(s) failure. */ + #define CRACENCORE_RNGCONTROL_STATUS_STARTUPFAIL_Pos (10UL) /*!< Position of STARTUPFAIL field. */ + #define CRACENCORE_RNGCONTROL_STATUS_STARTUPFAIL_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_STARTUPFAIL_Pos) /*!< Bit mask of + STARTUPFAIL field.*/ + +/* REPTESTFAILPERSHARE @Bits 12..15 : NIST Repetition test failure per share. */ + #define CRACENCORE_RNGCONTROL_STATUS_REPTESTFAILPERSHARE_Pos (12UL) /*!< Position of REPTESTFAILPERSHARE field. */ + #define CRACENCORE_RNGCONTROL_STATUS_REPTESTFAILPERSHARE_Msk (0xFUL << CRACENCORE_RNGCONTROL_STATUS_REPTESTFAILPERSHARE_Pos) + /*!< Bit mask of REPTESTFAILPERSHARE field.*/ + +/* PROPTESTFAILPERSHARE @Bits 16..19 : NIST Proportion test failure per share. */ + #define CRACENCORE_RNGCONTROL_STATUS_PROPTESTFAILPERSHARE_Pos (16UL) /*!< Position of PROPTESTFAILPERSHARE field. */ + #define CRACENCORE_RNGCONTROL_STATUS_PROPTESTFAILPERSHARE_Msk (0xFUL << CRACENCORE_RNGCONTROL_STATUS_PROPTESTFAILPERSHARE_Pos) + /*!< Bit mask of PROPTESTFAILPERSHARE field.*/ + +/* CONDITIONINGISTOOSLOW @Bit 20 : Conditioning consumes data slower than they are provided to it. */ + #define CRACENCORE_RNGCONTROL_STATUS_CONDITIONINGISTOOSLOW_Pos (20UL) /*!< Position of CONDITIONINGISTOOSLOW field. */ + #define CRACENCORE_RNGCONTROL_STATUS_CONDITIONINGISTOOSLOW_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_CONDITIONINGISTOOSLOW_Pos) + /*!< Bit mask of CONDITIONINGISTOOSLOW field.*/ + + +/* CRACENCORE_RNGCONTROL_WARMUPPERIOD: Number of clock cycles in warm-up sequence. */ + #define CRACENCORE_RNGCONTROL_WARMUPPERIOD_ResetValue (0x00000200UL) /*!< Reset value of WARMUPPERIOD register. */ + +/* WARMUPPERIOD @Bits 0..11 : Number of clock cycles in warm-up sequence. */ + #define CRACENCORE_RNGCONTROL_WARMUPPERIOD_WARMUPPERIOD_Pos (0UL) /*!< Position of WARMUPPERIOD field. */ + #define CRACENCORE_RNGCONTROL_WARMUPPERIOD_WARMUPPERIOD_Msk (0xFFFUL << CRACENCORE_RNGCONTROL_WARMUPPERIOD_WARMUPPERIOD_Pos) + /*!< Bit mask of WARMUPPERIOD field.*/ + + +/* CRACENCORE_RNGCONTROL_DISABLEOSC: DisableOsc register. */ + #define CRACENCORE_RNGCONTROL_DISABLEOSC_ResetValue (0x00000000UL) /*!< Reset value of DISABLEOSC register. */ + +/* DISABLEOSC @Bits 0..31 : Disable oscillator rings. */ + #define CRACENCORE_RNGCONTROL_DISABLEOSC_DISABLEOSC_Pos (0UL) /*!< Position of DISABLEOSC field. */ + #define CRACENCORE_RNGCONTROL_DISABLEOSC_DISABLEOSC_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_DISABLEOSC_DISABLEOSC_Pos) /*!< + Bit mask of DISABLEOSC field.*/ + + +/* CRACENCORE_RNGCONTROL_SAMPLINGPERIOD: Number of clock cycles between sampling moments. */ + #define CRACENCORE_RNGCONTROL_SAMPLINGPERIOD_ResetValue (0x00000FFFUL) /*!< Reset value of SAMPLINGPERIOD register. */ + +/* SAMPLINGPERIOD @Bits 0..11 : Number of clock cycles between sampling moments. */ + #define CRACENCORE_RNGCONTROL_SAMPLINGPERIOD_SAMPLINGPERIOD_Pos (0UL) /*!< Position of SAMPLINGPERIOD field. */ + #define CRACENCORE_RNGCONTROL_SAMPLINGPERIOD_SAMPLINGPERIOD_Msk (0xFFFUL << CRACENCORE_RNGCONTROL_SAMPLINGPERIOD_SAMPLINGPERIOD_Pos) + /*!< Bit mask of SAMPLINGPERIOD field.*/ + + +/* CRACENCORE_RNGCONTROL_HWCONFIG: Hardware configuration register. */ + #define CRACENCORE_RNGCONTROL_HWCONFIG_ResetValue (0x0002410FUL) /*!< Reset value of HWCONFIG register. */ + +/* NBOFINV @Bits 0..7 : Generic g_NbOfInverters value. */ + #define CRACENCORE_RNGCONTROL_HWCONFIG_NBOFINV_Pos (0UL) /*!< Position of NBOFINV field. */ + #define CRACENCORE_RNGCONTROL_HWCONFIG_NBOFINV_Msk (0xFFUL << CRACENCORE_RNGCONTROL_HWCONFIG_NBOFINV_Pos) /*!< Bit mask of + NBOFINV field.*/ + +/* LOG2NBOFAUTOCORRTESTSPERSHARE @Bits 8..11 : Generic g_Log2NbOfAutoCorrTestsPerShare value. */ + #define CRACENCORE_RNGCONTROL_HWCONFIG_LOG2NBOFAUTOCORRTESTSPERSHARE_Pos (8UL) /*!< Position of LOG2NBOFAUTOCORRTESTSPERSHARE + field.*/ + #define CRACENCORE_RNGCONTROL_HWCONFIG_LOG2NBOFAUTOCORRTESTSPERSHARE_Msk (0xFUL << CRACENCORE_RNGCONTROL_HWCONFIG_LOG2NBOFAUTOCORRTESTSPERSHARE_Pos) + /*!< Bit mask of LOG2NBOFAUTOCORRTESTSPERSHARE + field.*/ + +/* LOG2FIFODEPTH @Bits 12..15 : Generic g_Log2FifoDepth value. */ + #define CRACENCORE_RNGCONTROL_HWCONFIG_LOG2FIFODEPTH_Pos (12UL) /*!< Position of LOG2FIFODEPTH field. */ + #define CRACENCORE_RNGCONTROL_HWCONFIG_LOG2FIFODEPTH_Msk (0xFUL << CRACENCORE_RNGCONTROL_HWCONFIG_LOG2FIFODEPTH_Pos) /*!< Bit + mask of LOG2FIFODEPTH field.*/ + +/* LOG2NBOFSHARES @Bits 16..17 : Generic g_Log2NbOfShares value. */ + #define CRACENCORE_RNGCONTROL_HWCONFIG_LOG2NBOFSHARES_Pos (16UL) /*!< Position of LOG2NBOFSHARES field. */ + #define CRACENCORE_RNGCONTROL_HWCONFIG_LOG2NBOFSHARES_Msk (0x3UL << CRACENCORE_RNGCONTROL_HWCONFIG_LOG2NBOFSHARES_Pos) /*!< + Bit mask of LOG2NBOFSHARES field.*/ + + +/* CRACENCORE_RNGCONTROL_COOLDOWNPERIOD: Number of clock cycles in cool-down sequence. */ + #define CRACENCORE_RNGCONTROL_COOLDOWNPERIOD_ResetValue (0x00000000UL) /*!< Reset value of COOLDOWNPERIOD register. */ + +/* COOLDOWNPERIOD @Bits 0..11 : Number of clock cycles in cool-down sequence. */ + #define CRACENCORE_RNGCONTROL_COOLDOWNPERIOD_COOLDOWNPERIOD_Pos (0UL) /*!< Position of COOLDOWNPERIOD field. */ + #define CRACENCORE_RNGCONTROL_COOLDOWNPERIOD_COOLDOWNPERIOD_Msk (0xFFFUL << CRACENCORE_RNGCONTROL_COOLDOWNPERIOD_COOLDOWNPERIOD_Pos) + /*!< Bit mask of COOLDOWNPERIOD field.*/ + + +/* CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0: AutoCorrTestCutoff register 0 */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_ResetValue (0x007F007FUL) /*!< Reset value of AUTOCORRTESTCUTOFF0 register.*/ + +/* DLYZEROCUTOFF @Bits 0..6 : Auto-correlation test cut-off value for delay of 0 samples. */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYZEROCUTOFF_Pos (0UL) /*!< Position of DLYZEROCUTOFF field. */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYZEROCUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYZEROCUTOFF_Pos) + /*!< Bit mask of DLYZEROCUTOFF field.*/ + +/* DLYONECUTOFF @Bits 16..22 : Auto-correlation test cut-off value for delay of +1 sample. */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYONECUTOFF_Pos (16UL) /*!< Position of DLYONECUTOFF field. */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYONECUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF0_DLYONECUTOFF_Pos) + /*!< Bit mask of DLYONECUTOFF field.*/ + + +/* CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1: AutoCorrTestCutoff register 1 */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_ResetValue (0x007F007FUL) /*!< Reset value of AUTOCORRTESTCUTOFF1 register.*/ + +/* DLYTWOCUTOFF @Bits 0..6 : Auto-correlation test cut-off value for delay of +2 samples. */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTWOCUTOFF_Pos (0UL) /*!< Position of DLYTWOCUTOFF field. */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTWOCUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTWOCUTOFF_Pos) + /*!< Bit mask of DLYTWOCUTOFF field.*/ + +/* DLYTHREECUTOFF @Bits 16..22 : Auto-correlation test cut-off value for delay of +3 samples. */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTHREECUTOFF_Pos (16UL) /*!< Position of DLYTHREECUTOFF field. */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTHREECUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTCUTOFF1_DLYTHREECUTOFF_Pos) + /*!< Bit mask of DLYTHREECUTOFF field.*/ + + +/* CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0: CorrTestCutoff register 0 */ + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_ResetValue (0x007F007FUL) /*!< Reset value of CORRTESTCUTOFF0 register. */ + +/* DLYZEROCUTOFF @Bits 0..6 : Correlation test cut-off value for delay of 0 samples. */ + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYZEROCUTOFF_Pos (0UL) /*!< Position of DLYZEROCUTOFF field. */ + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYZEROCUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYZEROCUTOFF_Pos) + /*!< Bit mask of DLYZEROCUTOFF field.*/ + +/* DLYONECUTOFF @Bits 16..22 : Correlation test cut-off value for delay of +/-1 sample. */ + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYONECUTOFF_Pos (16UL) /*!< Position of DLYONECUTOFF field. */ + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYONECUTOFF_Msk (0x7FUL << CRACENCORE_RNGCONTROL_CORRTESTCUTOFF0_DLYONECUTOFF_Pos) + /*!< Bit mask of DLYONECUTOFF field.*/ + + +/* CRACENCORE_RNGCONTROL_CORRTESTCUTOFF1: CorrTestCutoff register 1 */ + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF1_ResetValue (0x007F007FUL) /*!< Reset value of CORRTESTCUTOFF1 register. */ + +/* DLYTWOCUTOFF @Bits 0..15 : Correlation test cut-off value for delay of +/- 2 samples. */ + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF1_DLYTWOCUTOFF_Pos (0UL) /*!< Position of DLYTWOCUTOFF field. */ + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF1_DLYTWOCUTOFF_Msk (0xFFFFUL << CRACENCORE_RNGCONTROL_CORRTESTCUTOFF1_DLYTWOCUTOFF_Pos) + /*!< Bit mask of DLYTWOCUTOFF field.*/ + +/* DLYTHREECUTOFF @Bits 16..31 : Correlation test cut-off value for delay of +/- 3 samples. */ + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF1_DLYTHREECUTOFF_Pos (16UL) /*!< Position of DLYTHREECUTOFF field. */ + #define CRACENCORE_RNGCONTROL_CORRTESTCUTOFF1_DLYTHREECUTOFF_Msk (0xFFFFUL << CRACENCORE_RNGCONTROL_CORRTESTCUTOFF1_DLYTHREECUTOFF_Pos) + /*!< Bit mask of DLYTHREECUTOFF field.*/ + + +/* CRACENCORE_RNGCONTROL_AUTOCORRTESTFAILED: Auto-correlation test failing ring(s). */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTFAILED_ResetValue (0x00000000UL) /*!< Reset value of AUTOCORRTESTFAILED register. */ + +/* AUTOCORRTESTFAILED @Bits 0..31 : Auto-correlation test failing ring(s). */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTFAILED_AUTOCORRTESTFAILED_Pos (0UL) /*!< Position of AUTOCORRTESTFAILED field. */ + #define CRACENCORE_RNGCONTROL_AUTOCORRTESTFAILED_AUTOCORRTESTFAILED_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_AUTOCORRTESTFAILED_AUTOCORRTESTFAILED_Pos) + /*!< Bit mask of AUTOCORRTESTFAILED field.*/ + + +/* CRACENCORE_RNGCONTROL_CORRTESTFAILED: Correlation test failing ring. */ + #define CRACENCORE_RNGCONTROL_CORRTESTFAILED_ResetValue (0x00000000UL) /*!< Reset value of CORRTESTFAILED register. */ + +/* CORRTESTFAILED @Bits 0..31 : Correlation test failing ring. */ + #define CRACENCORE_RNGCONTROL_CORRTESTFAILED_CORRTESTFAILED_Pos (0UL) /*!< Position of CORRTESTFAILED field. */ + #define CRACENCORE_RNGCONTROL_CORRTESTFAILED_CORRTESTFAILED_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_CORRTESTFAILED_CORRTESTFAILED_Pos) + /*!< Bit mask of CORRTESTFAILED field.*/ + + +/* CRACENCORE_RNGCONTROL_HWVERSION: Fixed to 1 for this version. */ + #define CRACENCORE_RNGCONTROL_HWVERSION_ResetValue (0x00000001UL) /*!< Reset value of HWVERSION register. */ + +/* HWVERSION @Bits 0..31 : Fixed to 1 for this version. */ + #define CRACENCORE_RNGCONTROL_HWVERSION_HWVERSION_Pos (0UL) /*!< Position of HWVERSION field. */ + #define CRACENCORE_RNGCONTROL_HWVERSION_HWVERSION_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_HWVERSION_HWVERSION_Pos) /*!< Bit + mask of HWVERSION field.*/ + + +/* CRACENCORE_RNGCONTROL_FIFO: FIFO data */ + #define CRACENCORE_RNGCONTROL_FIFO_MaxCount (32UL) /*!< Max size of FIFO[32] array. */ + #define CRACENCORE_RNGCONTROL_FIFO_MaxIndex (31UL) /*!< Max index of FIFO[32] array. */ + #define CRACENCORE_RNGCONTROL_FIFO_MinIndex (0UL) /*!< Min index of FIFO[32] array. */ + #define CRACENCORE_RNGCONTROL_FIFO_ResetValue (0x00000000UL) /*!< Reset value of FIFO[32] register. */ + +/* DATA @Bits 0..31 : FIFO data */ + #define CRACENCORE_RNGCONTROL_FIFO_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define CRACENCORE_RNGCONTROL_FIFO_DATA_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_FIFO_DATA_Pos) /*!< Bit mask of DATA + field.*/ + + + +/* ================================================== Struct CRACENCORE_PK =================================================== */ +/** + * @brief PK [CRACENCORE_PK] (unspecified) + */ +typedef struct { + __IOM uint32_t POINTERS; /*!< (@ 0x00000000) Pointers register. */ + __IOM uint32_t COMMAND; /*!< (@ 0x00000004) Command register. */ + __IOM uint32_t CONTROL; /*!< (@ 0x00000008) Command register. */ + __IOM uint32_t STATUS; /*!< (@ 0x0000000C) Status register. */ + __IM uint32_t RESERVED; + __IOM uint32_t TIMER; /*!< (@ 0x00000014) Timer register. */ + __IOM uint32_t HWCONFIG; /*!< (@ 0x00000018) Hardware configuration register. */ + __IOM uint32_t OPSIZE; /*!< (@ 0x0000001C) Operand size register. */ + __IM uint32_t RESERVED1[8]; + __IOM uint32_t ECCERRORBITPOS; /*!< (@ 0x00000040) ECC Error bit position register. */ + __IOM uint32_t ECCCONTROLSTATUSREG; /*!< (@ 0x00000044) ECC Control and Status register. */ + __IM uint32_t RESERVED2[12]; + __IOM uint32_t MICROCODEFORMAT; /*!< (@ 0x00000078) Microcode Format register. */ + __IOM uint32_t HWVERSION; /*!< (@ 0x0000007C) Hardware Version register. */ +} NRF_CRACENCORE_PK_Type; /*!< Size = 128 (0x080) */ + +/* CRACENCORE_PK_POINTERS: Pointers register. */ + #define CRACENCORE_PK_POINTERS_ResetValue (0x00000000UL) /*!< Reset value of POINTERS register. */ + +/* OPPTRA @Bits 0..3 : When executing primitive arithmetic operations, this pointer defines where operand A is located in memory + (location 0x0 to 0xF). */ + + #define CRACENCORE_PK_POINTERS_OPPTRA_Pos (0UL) /*!< Position of OPPTRA field. */ + #define CRACENCORE_PK_POINTERS_OPPTRA_Msk (0xFUL << CRACENCORE_PK_POINTERS_OPPTRA_Pos) /*!< Bit mask of OPPTRA field. */ + +/* OPPTRB @Bits 8..11 : When executing primitive arithmetic operations, this pointer defines where operand B is located in + memory (location 0x0 to 0xF). */ + + #define CRACENCORE_PK_POINTERS_OPPTRB_Pos (8UL) /*!< Position of OPPTRB field. */ + #define CRACENCORE_PK_POINTERS_OPPTRB_Msk (0xFUL << CRACENCORE_PK_POINTERS_OPPTRB_Pos) /*!< Bit mask of OPPTRB field. */ + +/* OPPTRC @Bits 16..19 : When executing primitive arithmetic operations, this pointer defines the location (0x0 to 0xF) where + the result will be stored in memory. */ + + #define CRACENCORE_PK_POINTERS_OPPTRC_Pos (16UL) /*!< Position of OPPTRC field. */ + #define CRACENCORE_PK_POINTERS_OPPTRC_Msk (0xFUL << CRACENCORE_PK_POINTERS_OPPTRC_Pos) /*!< Bit mask of OPPTRC field. */ + +/* OPPTRN @Bits 24..27 : When executing primitive arithmetic operations, this pointer defines the location where the modulus is + located in memory (location 0x0 to 0xF). */ + + #define CRACENCORE_PK_POINTERS_OPPTRN_Pos (24UL) /*!< Position of OPPTRN field. */ + #define CRACENCORE_PK_POINTERS_OPPTRN_Msk (0xFUL << CRACENCORE_PK_POINTERS_OPPTRN_Pos) /*!< Bit mask of OPPTRN field. */ + + +/* CRACENCORE_PK_COMMAND: Command register. */ + #define CRACENCORE_PK_COMMAND_ResetValue (0x0000000FUL) /*!< Reset value of COMMAND register. */ + +/* OPEADDR @Bits 0..6 : This field defines the operation to be performed. */ + #define CRACENCORE_PK_COMMAND_OPEADDR_Pos (0UL) /*!< Position of OPEADDR field. */ + #define CRACENCORE_PK_COMMAND_OPEADDR_Msk (0x7FUL << CRACENCORE_PK_COMMAND_OPEADDR_Pos) /*!< Bit mask of OPEADDR field. */ + +/* FIELDF @Bit 7 : 0: Field is GF(p) 1: Field is GF(2**m) */ + #define CRACENCORE_PK_COMMAND_FIELDF_Pos (7UL) /*!< Position of FIELDF field. */ + #define CRACENCORE_PK_COMMAND_FIELDF_Msk (0x1UL << CRACENCORE_PK_COMMAND_FIELDF_Pos) /*!< Bit mask of FIELDF field. */ + +/* OPBYTESM1 @Bits 8..17 : This field defines the size (= number of bytes minus one) of the operands for the current operation. + */ + + #define CRACENCORE_PK_COMMAND_OPBYTESM1_Pos (8UL) /*!< Position of OPBYTESM1 field. */ + #define CRACENCORE_PK_COMMAND_OPBYTESM1_Msk (0x3FFUL << CRACENCORE_PK_COMMAND_OPBYTESM1_Pos) /*!< Bit mask of OPBYTESM1 + field.*/ + +/* RANDMOD @Bit 19 : Enable randomization of modulus (counter-measure). */ + #define CRACENCORE_PK_COMMAND_RANDMOD_Pos (19UL) /*!< Position of RANDMOD field. */ + #define CRACENCORE_PK_COMMAND_RANDMOD_Msk (0x1UL << CRACENCORE_PK_COMMAND_RANDMOD_Pos) /*!< Bit mask of RANDMOD field. */ + +/* SELCURVE @Bits 20..22 : Enable accelerator for specific curve modulus: */ + #define CRACENCORE_PK_COMMAND_SELCURVE_Pos (20UL) /*!< Position of SELCURVE field. */ + #define CRACENCORE_PK_COMMAND_SELCURVE_Msk (0x7UL << CRACENCORE_PK_COMMAND_SELCURVE_Pos) /*!< Bit mask of SELCURVE field. */ + #define CRACENCORE_PK_COMMAND_SELCURVE_Min (0x0UL) /*!< Min enumerator value of SELCURVE field. */ + #define CRACENCORE_PK_COMMAND_SELCURVE_Max (0x6UL) /*!< Max enumerator value of SELCURVE field. */ + #define CRACENCORE_PK_COMMAND_SELCURVE_NOACCEL (0x0UL) /*!< (unspecified) */ + #define CRACENCORE_PK_COMMAND_SELCURVE_P256 (0x1UL) /*!< (unspecified) */ + #define CRACENCORE_PK_COMMAND_SELCURVE_P384 (0x2UL) /*!< (unspecified) */ + #define CRACENCORE_PK_COMMAND_SELCURVE_P521 (0x3UL) /*!< (unspecified) */ + #define CRACENCORE_PK_COMMAND_SELCURVE_P192 (0x4UL) /*!< (unspecified) */ + #define CRACENCORE_PK_COMMAND_SELCURVE_CURVE25519 (0x5UL) /*!< (unspecified) */ + #define CRACENCORE_PK_COMMAND_SELCURVE_ED25519 (0x6UL) /*!< (unspecified) */ + +/* RANDKE @Bit 24 : Enable randomization of exponent/scalar (counter-measure). */ + #define CRACENCORE_PK_COMMAND_RANDKE_Pos (24UL) /*!< Position of RANDKE field. */ + #define CRACENCORE_PK_COMMAND_RANDKE_Msk (0x1UL << CRACENCORE_PK_COMMAND_RANDKE_Pos) /*!< Bit mask of RANDKE field. */ + +/* RANDPROJ @Bit 25 : Enable randomization of projective coordinates (counter-measure). */ + #define CRACENCORE_PK_COMMAND_RANDPROJ_Pos (25UL) /*!< Position of RANDPROJ field. */ + #define CRACENCORE_PK_COMMAND_RANDPROJ_Msk (0x1UL << CRACENCORE_PK_COMMAND_RANDPROJ_Pos) /*!< Bit mask of RANDPROJ field. */ + +/* EDWARDS @Bit 26 : Enable Edwards curve. */ + #define CRACENCORE_PK_COMMAND_EDWARDS_Pos (26UL) /*!< Position of EDWARDS field. */ + #define CRACENCORE_PK_COMMAND_EDWARDS_Msk (0x1UL << CRACENCORE_PK_COMMAND_EDWARDS_Pos) /*!< Bit mask of EDWARDS field. */ + +/* SWAPBYTES @Bit 28 : Swap the bytes on AHB interface: */ + #define CRACENCORE_PK_COMMAND_SWAPBYTES_Pos (28UL) /*!< Position of SWAPBYTES field. */ + #define CRACENCORE_PK_COMMAND_SWAPBYTES_Msk (0x1UL << CRACENCORE_PK_COMMAND_SWAPBYTES_Pos) /*!< Bit mask of SWAPBYTES field. */ + #define CRACENCORE_PK_COMMAND_SWAPBYTES_Min (0x0UL) /*!< Min enumerator value of SWAPBYTES field. */ + #define CRACENCORE_PK_COMMAND_SWAPBYTES_Max (0x1UL) /*!< Max enumerator value of SWAPBYTES field. */ + #define CRACENCORE_PK_COMMAND_SWAPBYTES_NATIVE (0x0UL) /*!< Native format (little endian). */ + #define CRACENCORE_PK_COMMAND_SWAPBYTES_SWAPPED (0x1UL) /*!< Byte swapped (big endian). */ + +/* FLAGA @Bit 29 : Flag A. */ + #define CRACENCORE_PK_COMMAND_FLAGA_Pos (29UL) /*!< Position of FLAGA field. */ + #define CRACENCORE_PK_COMMAND_FLAGA_Msk (0x1UL << CRACENCORE_PK_COMMAND_FLAGA_Pos) /*!< Bit mask of FLAGA field. */ + +/* FLAGB @Bit 30 : Flag B. */ + #define CRACENCORE_PK_COMMAND_FLAGB_Pos (30UL) /*!< Position of FLAGB field. */ + #define CRACENCORE_PK_COMMAND_FLAGB_Msk (0x1UL << CRACENCORE_PK_COMMAND_FLAGB_Pos) /*!< Bit mask of FLAGB field. */ + +/* CALCR2 @Bit 31 : This bit indicates if the IP has to calculate R**2 mod N for the next operation. */ + #define CRACENCORE_PK_COMMAND_CALCR2_Pos (31UL) /*!< Position of CALCR2 field. */ + #define CRACENCORE_PK_COMMAND_CALCR2_Msk (0x1UL << CRACENCORE_PK_COMMAND_CALCR2_Pos) /*!< Bit mask of CALCR2 field. */ + #define CRACENCORE_PK_COMMAND_CALCR2_Min (0x0UL) /*!< Min enumerator value of CALCR2 field. */ + #define CRACENCORE_PK_COMMAND_CALCR2_Max (0x1UL) /*!< Max enumerator value of CALCR2 field. */ + #define CRACENCORE_PK_COMMAND_CALCR2_NRECALCULATE (0x0UL) /*!< don't recalculate R² mod N */ + #define CRACENCORE_PK_COMMAND_CALCR2_RECALCULATE (0x1UL) /*!< re-calculate R² mod N */ + + +/* CRACENCORE_PK_CONTROL: Command register. */ + #define CRACENCORE_PK_CONTROL_ResetValue (0x00000000UL) /*!< Reset value of CONTROL register. */ + +/* START @Bit 0 : Writing a 1 starts the processing. */ + #define CRACENCORE_PK_CONTROL_START_Pos (0UL) /*!< Position of START field. */ + #define CRACENCORE_PK_CONTROL_START_Msk (0x1UL << CRACENCORE_PK_CONTROL_START_Pos) /*!< Bit mask of START field. */ + +/* CLEARIRQ @Bit 1 : Writing a 1 clears the IRQ output. */ + #define CRACENCORE_PK_CONTROL_CLEARIRQ_Pos (1UL) /*!< Position of CLEARIRQ field. */ + #define CRACENCORE_PK_CONTROL_CLEARIRQ_Msk (0x1UL << CRACENCORE_PK_CONTROL_CLEARIRQ_Pos) /*!< Bit mask of CLEARIRQ field. */ + + +/* CRACENCORE_PK_STATUS: Status register. */ + #define CRACENCORE_PK_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERRORFLAGS @Bits 4..15 : These bits indicate an error condition. */ + #define CRACENCORE_PK_STATUS_ERRORFLAGS_Pos (4UL) /*!< Position of ERRORFLAGS field. */ + #define CRACENCORE_PK_STATUS_ERRORFLAGS_Msk (0xFFFUL << CRACENCORE_PK_STATUS_ERRORFLAGS_Pos) /*!< Bit mask of ERRORFLAGS + field.*/ + +/* PKBUSY @Bit 16 : This bit reflects the BUSY output value. */ + #define CRACENCORE_PK_STATUS_PKBUSY_Pos (16UL) /*!< Position of PKBUSY field. */ + #define CRACENCORE_PK_STATUS_PKBUSY_Msk (0x1UL << CRACENCORE_PK_STATUS_PKBUSY_Pos) /*!< Bit mask of PKBUSY field. */ + +/* INTRPTSTATUS @Bit 17 : This bit reflects the IRQ output value. */ + #define CRACENCORE_PK_STATUS_INTRPTSTATUS_Pos (17UL) /*!< Position of INTRPTSTATUS field. */ + #define CRACENCORE_PK_STATUS_INTRPTSTATUS_Msk (0x1UL << CRACENCORE_PK_STATUS_INTRPTSTATUS_Pos) /*!< Bit mask of INTRPTSTATUS + field.*/ + +/* FAILPTR @Bits 24..28 : These bits indicate which data location generated the error flag. */ + #define CRACENCORE_PK_STATUS_FAILPTR_Pos (24UL) /*!< Position of FAILPTR field. */ + #define CRACENCORE_PK_STATUS_FAILPTR_Msk (0x1FUL << CRACENCORE_PK_STATUS_FAILPTR_Pos) /*!< Bit mask of FAILPTR field. */ + + +/* CRACENCORE_PK_TIMER: Timer register. */ + #define CRACENCORE_PK_TIMER_ResetValue (0x00000000UL) /*!< Reset value of TIMER register. */ + +/* TIMER @Bits 1..31 : Number of clock cycles (as the number of core cycles is always even, register bit 0 is tied to zero). */ + #define CRACENCORE_PK_TIMER_TIMER_Pos (1UL) /*!< Position of TIMER field. */ + #define CRACENCORE_PK_TIMER_TIMER_Msk (0x7FFFFFFFUL << CRACENCORE_PK_TIMER_TIMER_Pos) /*!< Bit mask of TIMER field. */ + + +/* CRACENCORE_PK_HWCONFIG: Hardware configuration register. */ + #define CRACENCORE_PK_HWCONFIG_ResetValue (0x01F30200UL) /*!< Reset value of HWCONFIG register. */ + +/* MAXOPSIZE @Bits 0..11 : Maximum operand size (number of bytes). */ + #define CRACENCORE_PK_HWCONFIG_MAXOPSIZE_Pos (0UL) /*!< Position of MAXOPSIZE field. */ + #define CRACENCORE_PK_HWCONFIG_MAXOPSIZE_Msk (0xFFFUL << CRACENCORE_PK_HWCONFIG_MAXOPSIZE_Pos) /*!< Bit mask of MAXOPSIZE + field.*/ + +/* NBMULT @Bits 12..15 : Number of multipliers: */ + #define CRACENCORE_PK_HWCONFIG_NBMULT_Pos (12UL) /*!< Position of NBMULT field. */ + #define CRACENCORE_PK_HWCONFIG_NBMULT_Msk (0xFUL << CRACENCORE_PK_HWCONFIG_NBMULT_Pos) /*!< Bit mask of NBMULT field. */ + #define CRACENCORE_PK_HWCONFIG_NBMULT_Min (0x0UL) /*!< Min enumerator value of NBMULT field. */ + #define CRACENCORE_PK_HWCONFIG_NBMULT_Max (0x8UL) /*!< Max enumerator value of NBMULT field. */ + #define CRACENCORE_PK_HWCONFIG_NBMULT_MULT1 (0x0UL) /*!< 1 multiplier */ + #define CRACENCORE_PK_HWCONFIG_NBMULT_MULT4 (0x1UL) /*!< 4 multipliers */ + #define CRACENCORE_PK_HWCONFIG_NBMULT_MULT16 (0x2UL) /*!< 16 multipliers */ + #define CRACENCORE_PK_HWCONFIG_NBMULT_MULT64 (0x4UL) /*!< 64 multipliers */ + #define CRACENCORE_PK_HWCONFIG_NBMULT_MULT256 (0x8UL) /*!< 256 multipliers */ + +/* PRIMEFIELD @Bit 16 : Support prime field. */ + #define CRACENCORE_PK_HWCONFIG_PRIMEFIELD_Pos (16UL) /*!< Position of PRIMEFIELD field. */ + #define CRACENCORE_PK_HWCONFIG_PRIMEFIELD_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_PRIMEFIELD_Pos) /*!< Bit mask of PRIMEFIELD + field.*/ + +/* BINARYFIELD @Bit 17 : Support binary field. */ + #define CRACENCORE_PK_HWCONFIG_BINARYFIELD_Pos (17UL) /*!< Position of BINARYFIELD field. */ + #define CRACENCORE_PK_HWCONFIG_BINARYFIELD_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_BINARYFIELD_Pos) /*!< Bit mask of BINARYFIELD + field.*/ + +/* DATAMEMECC @Bit 18 : Support data memory error correction. */ + #define CRACENCORE_PK_HWCONFIG_DATAMEMECC_Pos (18UL) /*!< Position of DATAMEMECC field. */ + #define CRACENCORE_PK_HWCONFIG_DATAMEMECC_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_DATAMEMECC_Pos) /*!< Bit mask of DATAMEMECC + field.*/ + +/* CODEMEMECC @Bit 19 : Support code memory error correction. */ + #define CRACENCORE_PK_HWCONFIG_CODEMEMECC_Pos (19UL) /*!< Position of CODEMEMECC field. */ + #define CRACENCORE_PK_HWCONFIG_CODEMEMECC_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_CODEMEMECC_Pos) /*!< Bit mask of CODEMEMECC + field.*/ + +/* P256 @Bit 20 : Support ECC P256 acceleration. */ + #define CRACENCORE_PK_HWCONFIG_P256_Pos (20UL) /*!< Position of P256 field. */ + #define CRACENCORE_PK_HWCONFIG_P256_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_P256_Pos) /*!< Bit mask of P256 field. */ + +/* P384 @Bit 21 : Support ECC P384 acceleration. */ + #define CRACENCORE_PK_HWCONFIG_P384_Pos (21UL) /*!< Position of P384 field. */ + #define CRACENCORE_PK_HWCONFIG_P384_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_P384_Pos) /*!< Bit mask of P384 field. */ + +/* P521 @Bit 22 : Support ECC P521 acceleration. */ + #define CRACENCORE_PK_HWCONFIG_P521_Pos (22UL) /*!< Position of P521 field. */ + #define CRACENCORE_PK_HWCONFIG_P521_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_P521_Pos) /*!< Bit mask of P521 field. */ + +/* P192 @Bit 23 : Support ECC P192 acceleration. */ + #define CRACENCORE_PK_HWCONFIG_P192_Pos (23UL) /*!< Position of P192 field. */ + #define CRACENCORE_PK_HWCONFIG_P192_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_P192_Pos) /*!< Bit mask of P192 field. */ + +/* X25519 @Bit 24 : Support Curve25519/Ed25519 acceleration. */ + #define CRACENCORE_PK_HWCONFIG_X25519_Pos (24UL) /*!< Position of X25519 field. */ + #define CRACENCORE_PK_HWCONFIG_X25519_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_X25519_Pos) /*!< Bit mask of X25519 field. */ + +/* AHBMASTER @Bit 25 : Memory access */ + #define CRACENCORE_PK_HWCONFIG_AHBMASTER_Pos (25UL) /*!< Position of AHBMASTER field. */ + #define CRACENCORE_PK_HWCONFIG_AHBMASTER_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_AHBMASTER_Pos) /*!< Bit mask of AHBMASTER + field.*/ + #define CRACENCORE_PK_HWCONFIG_AHBMASTER_Min (0x0UL) /*!< Min enumerator value of AHBMASTER field. */ + #define CRACENCORE_PK_HWCONFIG_AHBMASTER_Max (0x1UL) /*!< Max enumerator value of AHBMASTER field. */ + #define CRACENCORE_PK_HWCONFIG_AHBMASTER_SLAVE (0x0UL) /*!< Memory access through AHB Slave and internally in the PKE. */ + #define CRACENCORE_PK_HWCONFIG_AHBMASTER_MASTER (0x1UL) /*!< Memory access through AHB Master, outside the PKE. */ + +/* CODERAM @Bit 26 : Code memory */ + #define CRACENCORE_PK_HWCONFIG_CODERAM_Pos (26UL) /*!< Position of CODERAM field. */ + #define CRACENCORE_PK_HWCONFIG_CODERAM_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_CODERAM_Pos) /*!< Bit mask of CODERAM field. */ + #define CRACENCORE_PK_HWCONFIG_CODERAM_Min (0x0UL) /*!< Min enumerator value of CODERAM field. */ + #define CRACENCORE_PK_HWCONFIG_CODERAM_Max (0x1UL) /*!< Max enumerator value of CODERAM field. */ + #define CRACENCORE_PK_HWCONFIG_CODERAM_ROM (0x0UL) /*!< Code memory is a ROM. */ + #define CRACENCORE_PK_HWCONFIG_CODERAM_RAM (0x1UL) /*!< Code memory is a RAM. */ + +/* DISABLESMX @Bit 29 : State of DisableSMx input (high when SM2/SM9 operations are disabled). */ + #define CRACENCORE_PK_HWCONFIG_DISABLESMX_Pos (29UL) /*!< Position of DISABLESMX field. */ + #define CRACENCORE_PK_HWCONFIG_DISABLESMX_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_DISABLESMX_Pos) /*!< Bit mask of DISABLESMX + field.*/ + +/* DISABLECLRMEM @Bit 30 : State of DisableClrMem input (high when automatic clear of the RAM after reset is disabled). */ + #define CRACENCORE_PK_HWCONFIG_DISABLECLRMEM_Pos (30UL) /*!< Position of DISABLECLRMEM field. */ + #define CRACENCORE_PK_HWCONFIG_DISABLECLRMEM_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_DISABLECLRMEM_Pos) /*!< Bit mask of + DISABLECLRMEM field.*/ + +/* DISABLECM @Bit 31 : State of DisableCM input (high when counter-measures are disabled). */ + #define CRACENCORE_PK_HWCONFIG_DISABLECM_Pos (31UL) /*!< Position of DISABLECM field. */ + #define CRACENCORE_PK_HWCONFIG_DISABLECM_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_DISABLECM_Pos) /*!< Bit mask of DISABLECM + field.*/ + + +/* CRACENCORE_PK_OPSIZE: Operand size register. */ + #define CRACENCORE_PK_OPSIZE_ResetValue (0x00001000UL) /*!< Reset value of OPSIZE register. */ + +/* OPSIZE @Bits 0..12 : Operand size (number of bytes): This register is used when the memory is accessed via AHB Master */ + #define CRACENCORE_PK_OPSIZE_OPSIZE_Pos (0UL) /*!< Position of OPSIZE field. */ + #define CRACENCORE_PK_OPSIZE_OPSIZE_Msk (0x1FFFUL << CRACENCORE_PK_OPSIZE_OPSIZE_Pos) /*!< Bit mask of OPSIZE field. */ + #define CRACENCORE_PK_OPSIZE_OPSIZE_Min (0x0100UL) /*!< Min enumerator value of OPSIZE field. */ + #define CRACENCORE_PK_OPSIZE_OPSIZE_Max (0x1000UL) /*!< Max enumerator value of OPSIZE field. */ + #define CRACENCORE_PK_OPSIZE_OPSIZE_OPSIZE256 (0x0100UL) /*!< 256 bytes. */ + #define CRACENCORE_PK_OPSIZE_OPSIZE_OPSIZE521 (0x0209UL) /*!< 521 bytes. */ + #define CRACENCORE_PK_OPSIZE_OPSIZE_OPSIZE2048 (0x0800UL) /*!< 2048 bytes. */ + #define CRACENCORE_PK_OPSIZE_OPSIZE_OPSIZE4096 (0x1000UL) /*!< 4096 bytes. */ + + +/* CRACENCORE_PK_ECCERRORBITPOS: ECC Error bit position register. */ + #define CRACENCORE_PK_ECCERRORBITPOS_ResetValue (0x03FF03FFUL) /*!< Reset value of ECCERRORBITPOS register. */ + +/* ERRORBITPOS1 @Bits 0..9 : Position of error bit 1 */ + #define CRACENCORE_PK_ECCERRORBITPOS_ERRORBITPOS1_Pos (0UL) /*!< Position of ERRORBITPOS1 field. */ + #define CRACENCORE_PK_ECCERRORBITPOS_ERRORBITPOS1_Msk (0x3FFUL << CRACENCORE_PK_ECCERRORBITPOS_ERRORBITPOS1_Pos) /*!< Bit mask + of ERRORBITPOS1 field.*/ + +/* ERRORBITPOS2 @Bits 16..25 : Position of error bit 2 */ + #define CRACENCORE_PK_ECCERRORBITPOS_ERRORBITPOS2_Pos (16UL) /*!< Position of ERRORBITPOS2 field. */ + #define CRACENCORE_PK_ECCERRORBITPOS_ERRORBITPOS2_Msk (0x3FFUL << CRACENCORE_PK_ECCERRORBITPOS_ERRORBITPOS2_Pos) /*!< Bit mask + of ERRORBITPOS2 field.*/ + + +/* CRACENCORE_PK_ECCCONTROLSTATUSREG: ECC Control and Status register. */ + #define CRACENCORE_PK_ECCCONTROLSTATUSREG_ResetValue (0x00000000UL) /*!< Reset value of ECCCONTROLSTATUSREG register. */ + +/* DATAMEMCORRECTION @Bit 0 : Data Memory Correction flag, clear on write */ + #define CRACENCORE_PK_ECCCONTROLSTATUSREG_DATAMEMCORRECTION_Pos (0UL) /*!< Position of DATAMEMCORRECTION field. */ + #define CRACENCORE_PK_ECCCONTROLSTATUSREG_DATAMEMCORRECTION_Msk (0x1UL << CRACENCORE_PK_ECCCONTROLSTATUSREG_DATAMEMCORRECTION_Pos) + /*!< Bit mask of DATAMEMCORRECTION field.*/ + +/* DATAMEMFAILURE @Bit 1 : Data Memory Failure flag, clear on write */ + #define CRACENCORE_PK_ECCCONTROLSTATUSREG_DATAMEMFAILURE_Pos (1UL) /*!< Position of DATAMEMFAILURE field. */ + #define CRACENCORE_PK_ECCCONTROLSTATUSREG_DATAMEMFAILURE_Msk (0x1UL << CRACENCORE_PK_ECCCONTROLSTATUSREG_DATAMEMFAILURE_Pos) + /*!< Bit mask of DATAMEMFAILURE field.*/ + +/* CODEMEMCORRECTION @Bit 2 : Code Memory Correction flag, clear on write */ + #define CRACENCORE_PK_ECCCONTROLSTATUSREG_CODEMEMCORRECTION_Pos (2UL) /*!< Position of CODEMEMCORRECTION field. */ + #define CRACENCORE_PK_ECCCONTROLSTATUSREG_CODEMEMCORRECTION_Msk (0x1UL << CRACENCORE_PK_ECCCONTROLSTATUSREG_CODEMEMCORRECTION_Pos) + /*!< Bit mask of CODEMEMCORRECTION field.*/ + +/* CODEMEMFAILURE @Bit 3 : Code Memory Failure flag, clear on write */ + #define CRACENCORE_PK_ECCCONTROLSTATUSREG_CODEMEMFAILURE_Pos (3UL) /*!< Position of CODEMEMFAILURE field. */ + #define CRACENCORE_PK_ECCCONTROLSTATUSREG_CODEMEMFAILURE_Msk (0x1UL << CRACENCORE_PK_ECCCONTROLSTATUSREG_CODEMEMFAILURE_Pos) + /*!< Bit mask of CODEMEMFAILURE field.*/ + + +/* CRACENCORE_PK_MICROCODEFORMAT: Microcode Format register. */ + #define CRACENCORE_PK_MICROCODEFORMAT_ResetValue (0xD4B79DDAUL) /*!< Reset value of MICROCODEFORMAT register. */ + +/* MICROCODEFORMAT @Bits 0..31 : Microcode format number. */ + #define CRACENCORE_PK_MICROCODEFORMAT_MICROCODEFORMAT_Pos (0UL) /*!< Position of MICROCODEFORMAT field. */ + #define CRACENCORE_PK_MICROCODEFORMAT_MICROCODEFORMAT_Msk (0xFFFFFFFFUL << CRACENCORE_PK_MICROCODEFORMAT_MICROCODEFORMAT_Pos) + /*!< Bit mask of MICROCODEFORMAT field.*/ + + +/* CRACENCORE_PK_HWVERSION: Hardware Version register. */ + #define CRACENCORE_PK_HWVERSION_ResetValue (0x00010001UL) /*!< Reset value of HWVERSION register. */ + +/* MINOR @Bits 0..15 : Minor version number. */ + #define CRACENCORE_PK_HWVERSION_MINOR_Pos (0UL) /*!< Position of MINOR field. */ + #define CRACENCORE_PK_HWVERSION_MINOR_Msk (0xFFFFUL << CRACENCORE_PK_HWVERSION_MINOR_Pos) /*!< Bit mask of MINOR field. */ + +/* MAJOR @Bits 16..31 : Major version number. */ + #define CRACENCORE_PK_HWVERSION_MAJOR_Pos (16UL) /*!< Position of MAJOR field. */ + #define CRACENCORE_PK_HWVERSION_MAJOR_Msk (0xFFFFUL << CRACENCORE_PK_HWVERSION_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ + + + +/* ================================================== Struct CRACENCORE_IKG ================================================== */ +/** + * @brief IKG [CRACENCORE_IKG] (unspecified) + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Start register. */ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register. */ + __IOM uint32_t INITDATA; /*!< (@ 0x00000008) InitData register. */ + __IOM uint32_t NONCE; /*!< (@ 0x0000000C) Nonce register. */ + __IOM uint32_t PERSONALISATIONSTRING; /*!< (@ 0x00000010) Personalisation String register. */ + __IOM uint32_t RESEEDINTERVALLSB; /*!< (@ 0x00000014) Reseed Interval LSB register. */ + __IOM uint32_t RESEEDINTERVALMSB; /*!< (@ 0x00000018) Reseed Interval MSB register. */ + __IOM uint32_t PKECONTROL; /*!< (@ 0x0000001C) PKE Control register. */ + __IOM uint32_t PKECOMMAND; /*!< (@ 0x00000020) PKE Command register. */ + __IOM uint32_t PKESTATUS; /*!< (@ 0x00000024) PKE Status register. */ + __IOM uint32_t SOFTRST; /*!< (@ 0x00000028) SoftRst register. */ + __IOM uint32_t HWCONFIG; /*!< (@ 0x0000002C) HwConfig register. */ +} NRF_CRACENCORE_IKG_Type; /*!< Size = 48 (0x030) */ + +/* CRACENCORE_IKG_START: Start register. */ + #define CRACENCORE_IKG_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* START @Bit 0 : Start the Isolated Key Generation. */ + #define CRACENCORE_IKG_START_START_Pos (0UL) /*!< Position of START field. */ + #define CRACENCORE_IKG_START_START_Msk (0x1UL << CRACENCORE_IKG_START_START_Pos) /*!< Bit mask of START field. */ + + +/* CRACENCORE_IKG_STATUS: Status register. */ + #define CRACENCORE_IKG_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* SEEDERROR @Bit 0 : Seed Error during Isolated Key Generation. */ + #define CRACENCORE_IKG_STATUS_SEEDERROR_Pos (0UL) /*!< Position of SEEDERROR field. */ + #define CRACENCORE_IKG_STATUS_SEEDERROR_Msk (0x1UL << CRACENCORE_IKG_STATUS_SEEDERROR_Pos) /*!< Bit mask of SEEDERROR field. */ + +/* ENTROPYERROR @Bit 1 : Entropy Error during Isolated Key Generation. */ + #define CRACENCORE_IKG_STATUS_ENTROPYERROR_Pos (1UL) /*!< Position of ENTROPYERROR field. */ + #define CRACENCORE_IKG_STATUS_ENTROPYERROR_Msk (0x1UL << CRACENCORE_IKG_STATUS_ENTROPYERROR_Pos) /*!< Bit mask of ENTROPYERROR + field.*/ + +/* OKAY @Bit 2 : Isolated Key Generation is okay. */ + #define CRACENCORE_IKG_STATUS_OKAY_Pos (2UL) /*!< Position of OKAY field. */ + #define CRACENCORE_IKG_STATUS_OKAY_Msk (0x1UL << CRACENCORE_IKG_STATUS_OKAY_Pos) /*!< Bit mask of OKAY field. */ + +/* CTRDRBGBUSY @Bit 4 : CTR_DRBG health test is busy (only when g_hw_health_test = true). */ + #define CRACENCORE_IKG_STATUS_CTRDRBGBUSY_Pos (4UL) /*!< Position of CTRDRBGBUSY field. */ + #define CRACENCORE_IKG_STATUS_CTRDRBGBUSY_Msk (0x1UL << CRACENCORE_IKG_STATUS_CTRDRBGBUSY_Pos) /*!< Bit mask of CTRDRBGBUSY + field.*/ + +/* CATASTROPHICERROR @Bit 5 : Catastrophic error during CTR_DRBG health test (only when g_hw_health_test = true). */ + #define CRACENCORE_IKG_STATUS_CATASTROPHICERROR_Pos (5UL) /*!< Position of CATASTROPHICERROR field. */ + #define CRACENCORE_IKG_STATUS_CATASTROPHICERROR_Msk (0x1UL << CRACENCORE_IKG_STATUS_CATASTROPHICERROR_Pos) /*!< Bit mask of + CATASTROPHICERROR field.*/ + +/* SYMKEYSTORED @Bit 6 : Symmetric Keys are stored. */ + #define CRACENCORE_IKG_STATUS_SYMKEYSTORED_Pos (6UL) /*!< Position of SYMKEYSTORED field. */ + #define CRACENCORE_IKG_STATUS_SYMKEYSTORED_Msk (0x1UL << CRACENCORE_IKG_STATUS_SYMKEYSTORED_Pos) /*!< Bit mask of SYMKEYSTORED + field.*/ + +/* PRIVKEYSTORED @Bit 7 : Private Keys are stored. */ + #define CRACENCORE_IKG_STATUS_PRIVKEYSTORED_Pos (7UL) /*!< Position of PRIVKEYSTORED field. */ + #define CRACENCORE_IKG_STATUS_PRIVKEYSTORED_Msk (0x1UL << CRACENCORE_IKG_STATUS_PRIVKEYSTORED_Pos) /*!< Bit mask of + PRIVKEYSTORED field.*/ + + +/* CRACENCORE_IKG_INITDATA: InitData register. */ + #define CRACENCORE_IKG_INITDATA_ResetValue (0x00000000UL) /*!< Reset value of INITDATA register. */ + +/* INITDATA @Bit 0 : Writing a 1 initialise Nonce and Personalisation_String registers counters, i.e. start writing from the 32 + LSB. */ + + #define CRACENCORE_IKG_INITDATA_INITDATA_Pos (0UL) /*!< Position of INITDATA field. */ + #define CRACENCORE_IKG_INITDATA_INITDATA_Msk (0x1UL << CRACENCORE_IKG_INITDATA_INITDATA_Pos) /*!< Bit mask of INITDATA field.*/ + + +/* CRACENCORE_IKG_NONCE: Nonce register. */ + #define CRACENCORE_IKG_NONCE_ResetValue (0x00000000UL) /*!< Reset value of NONCE register. */ + +/* NONCE @Bits 0..31 : Nonce (write/read value 32-bit by 32-bit). */ + #define CRACENCORE_IKG_NONCE_NONCE_Pos (0UL) /*!< Position of NONCE field. */ + #define CRACENCORE_IKG_NONCE_NONCE_Msk (0xFFFFFFFFUL << CRACENCORE_IKG_NONCE_NONCE_Pos) /*!< Bit mask of NONCE field. */ + + +/* CRACENCORE_IKG_PERSONALISATIONSTRING: Personalisation String register. */ + #define CRACENCORE_IKG_PERSONALISATIONSTRING_ResetValue (0x00000000UL) /*!< Reset value of PERSONALISATIONSTRING register. */ + +/* PERSONALISATIONSTRING @Bits 0..31 : Personalisation String (write/read value 32-bit by 32-bit). */ + #define CRACENCORE_IKG_PERSONALISATIONSTRING_PERSONALISATIONSTRING_Pos (0UL) /*!< Position of PERSONALISATIONSTRING field. */ + #define CRACENCORE_IKG_PERSONALISATIONSTRING_PERSONALISATIONSTRING_Msk (0xFFFFFFFFUL << CRACENCORE_IKG_PERSONALISATIONSTRING_PERSONALISATIONSTRING_Pos) + /*!< Bit mask of PERSONALISATIONSTRING field.*/ + + +/* CRACENCORE_IKG_RESEEDINTERVALLSB: Reseed Interval LSB register. */ + #define CRACENCORE_IKG_RESEEDINTERVALLSB_ResetValue (0x80000000UL) /*!< Reset value of RESEEDINTERVALLSB register. */ + +/* RESEEDINTERVALLSB @Bits 0..31 : Reseed Interval LSB. */ + #define CRACENCORE_IKG_RESEEDINTERVALLSB_RESEEDINTERVALLSB_Pos (0UL) /*!< Position of RESEEDINTERVALLSB field. */ + #define CRACENCORE_IKG_RESEEDINTERVALLSB_RESEEDINTERVALLSB_Msk (0xFFFFFFFFUL << CRACENCORE_IKG_RESEEDINTERVALLSB_RESEEDINTERVALLSB_Pos) + /*!< Bit mask of RESEEDINTERVALLSB field.*/ + + +/* CRACENCORE_IKG_RESEEDINTERVALMSB: Reseed Interval MSB register. */ + #define CRACENCORE_IKG_RESEEDINTERVALMSB_ResetValue (0x00000000UL) /*!< Reset value of RESEEDINTERVALMSB register. */ + +/* RESEEDINTERVALMSB @Bits 0..15 : Reseed Interval MSB. */ + #define CRACENCORE_IKG_RESEEDINTERVALMSB_RESEEDINTERVALMSB_Pos (0UL) /*!< Position of RESEEDINTERVALMSB field. */ + #define CRACENCORE_IKG_RESEEDINTERVALMSB_RESEEDINTERVALMSB_Msk (0xFFFFUL << CRACENCORE_IKG_RESEEDINTERVALMSB_RESEEDINTERVALMSB_Pos) + /*!< Bit mask of RESEEDINTERVALMSB field.*/ + + +/* CRACENCORE_IKG_PKECONTROL: PKE Control register. */ + #define CRACENCORE_IKG_PKECONTROL_ResetValue (0x00000000UL) /*!< Reset value of PKECONTROL register. */ + +/* PKESTART @Bit 0 : Start the PKE operation or trigger for Secure mode exit. */ + #define CRACENCORE_IKG_PKECONTROL_PKESTART_Pos (0UL) /*!< Position of PKESTART field. */ + #define CRACENCORE_IKG_PKECONTROL_PKESTART_Msk (0x1UL << CRACENCORE_IKG_PKECONTROL_PKESTART_Pos) /*!< Bit mask of PKESTART + field.*/ + +/* CLEARIRQ @Bit 1 : Clear the IRQ output. */ + #define CRACENCORE_IKG_PKECONTROL_CLEARIRQ_Pos (1UL) /*!< Position of CLEARIRQ field. */ + #define CRACENCORE_IKG_PKECONTROL_CLEARIRQ_Msk (0x1UL << CRACENCORE_IKG_PKECONTROL_CLEARIRQ_Pos) /*!< Bit mask of CLEARIRQ + field.*/ + + +/* CRACENCORE_IKG_PKECOMMAND: PKE Command register. */ + #define CRACENCORE_IKG_PKECOMMAND_ResetValue (0x00000000UL) /*!< Reset value of PKECOMMAND register. */ + +/* SECUREMODE @Bit 0 : Secure mode. */ + #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_Pos (0UL) /*!< Position of SECUREMODE field. */ + #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_Msk (0x1UL << CRACENCORE_IKG_PKECOMMAND_SECUREMODE_Pos) /*!< Bit mask of + SECUREMODE field.*/ + #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_Min (0x0UL) /*!< Min enumerator value of SECUREMODE field. */ + #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_Max (0x1UL) /*!< Max enumerator value of SECUREMODE field. */ + #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_DEACTIVATED (0x0UL) /*!< (unspecified) */ + #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_ACTIVATED (0x1UL) /*!< (unspecified) */ + +/* SELECTEDKEY @Bits 4..7 : Select Generated Private Key for PKE operation. */ + #define CRACENCORE_IKG_PKECOMMAND_SELECTEDKEY_Pos (4UL) /*!< Position of SELECTEDKEY field. */ + #define CRACENCORE_IKG_PKECOMMAND_SELECTEDKEY_Msk (0xFUL << CRACENCORE_IKG_PKECOMMAND_SELECTEDKEY_Pos) /*!< Bit mask of + SELECTEDKEY field.*/ + +/* OPSEL @Bits 8..9 : Select PKE operation with Isolated Key */ + #define CRACENCORE_IKG_PKECOMMAND_OPSEL_Pos (8UL) /*!< Position of OPSEL field. */ + #define CRACENCORE_IKG_PKECOMMAND_OPSEL_Msk (0x3UL << CRACENCORE_IKG_PKECOMMAND_OPSEL_Pos) /*!< Bit mask of OPSEL field. */ + #define CRACENCORE_IKG_PKECOMMAND_OPSEL_Min (0x0UL) /*!< Min enumerator value of OPSEL field. */ + #define CRACENCORE_IKG_PKECOMMAND_OPSEL_Max (0x2UL) /*!< Max enumerator value of OPSEL field. */ + #define CRACENCORE_IKG_PKECOMMAND_OPSEL_PUBKEY (0x0UL) /*!< Public Key Generation */ + #define CRACENCORE_IKG_PKECOMMAND_OPSEL_ECDSA (0x1UL) /*!< ECDSA Signature */ + #define CRACENCORE_IKG_PKECOMMAND_OPSEL_PTMUL (0x2UL) /*!< Point Multiplication */ + + +/* CRACENCORE_IKG_PKESTATUS: PKE Status register. */ + #define CRACENCORE_IKG_PKESTATUS_ResetValue (0x00000000UL) /*!< Reset value of PKESTATUS register. */ + +/* ERROR @Bit 0 : Error because either Private Keys are not stored or the operation is not defined. */ + #define CRACENCORE_IKG_PKESTATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define CRACENCORE_IKG_PKESTATUS_ERROR_Msk (0x1UL << CRACENCORE_IKG_PKESTATUS_ERROR_Pos) /*!< Bit mask of ERROR field. */ + +/* STARTERROR @Bit 1 : Error because a new operation is started while the previous one is still busy. */ + #define CRACENCORE_IKG_PKESTATUS_STARTERROR_Pos (1UL) /*!< Position of STARTERROR field. */ + #define CRACENCORE_IKG_PKESTATUS_STARTERROR_Msk (0x1UL << CRACENCORE_IKG_PKESTATUS_STARTERROR_Pos) /*!< Bit mask of STARTERROR + field.*/ + +/* IKGPKBUSY @Bit 16 : Busy, set when the operation starts and cleared when the operation is finished. */ + #define CRACENCORE_IKG_PKESTATUS_IKGPKBUSY_Pos (16UL) /*!< Position of IKGPKBUSY field. */ + #define CRACENCORE_IKG_PKESTATUS_IKGPKBUSY_Msk (0x1UL << CRACENCORE_IKG_PKESTATUS_IKGPKBUSY_Pos) /*!< Bit mask of IKGPKBUSY + field.*/ + +/* IRQSTATUS @Bit 17 : IRQ, set when the operation is finished and cleared when the CPU writes the bit 1 of PKE_Control Register + or a new operation is started. */ + + #define CRACENCORE_IKG_PKESTATUS_IRQSTATUS_Pos (17UL) /*!< Position of IRQSTATUS field. */ + #define CRACENCORE_IKG_PKESTATUS_IRQSTATUS_Msk (0x1UL << CRACENCORE_IKG_PKESTATUS_IRQSTATUS_Pos) /*!< Bit mask of IRQSTATUS + field.*/ + +/* ERASEBUSY @Bit 18 : The PKE Data RAM is being erased. */ + #define CRACENCORE_IKG_PKESTATUS_ERASEBUSY_Pos (18UL) /*!< Position of ERASEBUSY field. */ + #define CRACENCORE_IKG_PKESTATUS_ERASEBUSY_Msk (0x1UL << CRACENCORE_IKG_PKESTATUS_ERASEBUSY_Pos) /*!< Bit mask of ERASEBUSY + field.*/ + + +/* CRACENCORE_IKG_SOFTRST: SoftRst register. */ + #define CRACENCORE_IKG_SOFTRST_ResetValue (0x00000000UL) /*!< Reset value of SOFTRST register. */ + +/* SOFTRST @Bit 0 : Software reset: */ + #define CRACENCORE_IKG_SOFTRST_SOFTRST_Pos (0UL) /*!< Position of SOFTRST field. */ + #define CRACENCORE_IKG_SOFTRST_SOFTRST_Msk (0x1UL << CRACENCORE_IKG_SOFTRST_SOFTRST_Pos) /*!< Bit mask of SOFTRST field. */ + #define CRACENCORE_IKG_SOFTRST_SOFTRST_Min (0x0UL) /*!< Min enumerator value of SOFTRST field. */ + #define CRACENCORE_IKG_SOFTRST_SOFTRST_Max (0x1UL) /*!< Max enumerator value of SOFTRST field. */ + #define CRACENCORE_IKG_SOFTRST_SOFTRST_NORMAL (0x0UL) /*!< Normal mode. */ + #define CRACENCORE_IKG_SOFTRST_SOFTRST_KEY (0x1UL) /*!< The Isolated Key Generation logic and the keys are reset. */ + + +/* CRACENCORE_IKG_HWCONFIG: HwConfig register. */ + #define CRACENCORE_IKG_HWCONFIG_ResetValue (0xCC4C8312UL) /*!< Reset value of HWCONFIG register. */ + +/* NBSYMKEYS @Bits 0..3 : Number of Symmetric Keys generated. */ + #define CRACENCORE_IKG_HWCONFIG_NBSYMKEYS_Pos (0UL) /*!< Position of NBSYMKEYS field. */ + #define CRACENCORE_IKG_HWCONFIG_NBSYMKEYS_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_NBSYMKEYS_Pos) /*!< Bit mask of NBSYMKEYS + field.*/ + +/* NBPRIVKEYS @Bits 4..7 : Number of Private Keys generated. */ + #define CRACENCORE_IKG_HWCONFIG_NBPRIVKEYS_Pos (4UL) /*!< Position of NBPRIVKEYS field. */ + #define CRACENCORE_IKG_HWCONFIG_NBPRIVKEYS_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_NBPRIVKEYS_Pos) /*!< Bit mask of NBPRIVKEYS + field.*/ + +/* IKGCM @Bit 8 : Countermeasures for IKG operations are implemented when 1. */ + #define CRACENCORE_IKG_HWCONFIG_IKGCM_Pos (8UL) /*!< Position of IKGCM field. */ + #define CRACENCORE_IKG_HWCONFIG_IKGCM_Msk (0x1UL << CRACENCORE_IKG_HWCONFIG_IKGCM_Pos) /*!< Bit mask of IKGCM field. */ + +/* HWHEALTHTEST @Bit 9 : CTR_DRBG health test is implemented when 1. */ + #define CRACENCORE_IKG_HWCONFIG_HWHEALTHTEST_Pos (9UL) /*!< Position of HWHEALTHTEST field. */ + #define CRACENCORE_IKG_HWCONFIG_HWHEALTHTEST_Msk (0x1UL << CRACENCORE_IKG_HWCONFIG_HWHEALTHTEST_Pos) /*!< Bit mask of + HWHEALTHTEST field.*/ + +/* CURVE @Bits 10..11 : ECC curve for IKG (input). */ + #define CRACENCORE_IKG_HWCONFIG_CURVE_Pos (10UL) /*!< Position of CURVE field. */ + #define CRACENCORE_IKG_HWCONFIG_CURVE_Msk (0x3UL << CRACENCORE_IKG_HWCONFIG_CURVE_Pos) /*!< Bit mask of CURVE field. */ + #define CRACENCORE_IKG_HWCONFIG_CURVE_Min (0x0UL) /*!< Min enumerator value of CURVE field. */ + #define CRACENCORE_IKG_HWCONFIG_CURVE_Max (0x2UL) /*!< Max enumerator value of CURVE field. */ + #define CRACENCORE_IKG_HWCONFIG_CURVE_P256 (0x0UL) /*!< P256. */ + #define CRACENCORE_IKG_HWCONFIG_CURVE_P384 (0x1UL) /*!< P384. */ + #define CRACENCORE_IKG_HWCONFIG_CURVE_P521 (0x2UL) /*!< P521. */ + +/* DF @Bit 12 : Derivation function is implemented in the CTR_DRBG when 1. */ + #define CRACENCORE_IKG_HWCONFIG_DF_Pos (12UL) /*!< Position of DF field. */ + #define CRACENCORE_IKG_HWCONFIG_DF_Msk (0x1UL << CRACENCORE_IKG_HWCONFIG_DF_Pos) /*!< Bit mask of DF field. */ + +/* KEYSIZE @Bits 13..15 : AES Key Size support for the AES Core embedded in the CTR_DRBG. */ + #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_Pos (13UL) /*!< Position of KEYSIZE field. */ + #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_Msk (0x7UL << CRACENCORE_IKG_HWCONFIG_KEYSIZE_Pos) /*!< Bit mask of KEYSIZE field. */ + #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_Min (0x1UL) /*!< Min enumerator value of KEYSIZE field. */ + #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_Max (0x4UL) /*!< Max enumerator value of KEYSIZE field. */ + #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_AES128 (0x1UL) /*!< supports AES128 */ + #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_AES192 (0x2UL) /*!< supports AES192 */ + #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_AES256 (0x4UL) /*!< supports AES256 */ + +/* ENTROPYINPUTLENGTH @Bits 16..19 : Value of g_entropy_input_length/32. */ + #define CRACENCORE_IKG_HWCONFIG_ENTROPYINPUTLENGTH_Pos (16UL) /*!< Position of ENTROPYINPUTLENGTH field. */ + #define CRACENCORE_IKG_HWCONFIG_ENTROPYINPUTLENGTH_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_ENTROPYINPUTLENGTH_Pos) /*!< Bit mask + of ENTROPYINPUTLENGTH field.*/ + +/* NONCELENGTH @Bits 20..23 : Value of g_nonce_length/32. */ + #define CRACENCORE_IKG_HWCONFIG_NONCELENGTH_Pos (20UL) /*!< Position of NONCELENGTH field. */ + #define CRACENCORE_IKG_HWCONFIG_NONCELENGTH_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_NONCELENGTH_Pos) /*!< Bit mask of + NONCELENGTH field.*/ + +/* PERSONALIZATIONSTRINGLENGTH @Bits 24..27 : Value of g_personalization_string_length/32. */ + #define CRACENCORE_IKG_HWCONFIG_PERSONALIZATIONSTRINGLENGTH_Pos (24UL) /*!< Position of PERSONALIZATIONSTRINGLENGTH field. */ + #define CRACENCORE_IKG_HWCONFIG_PERSONALIZATIONSTRINGLENGTH_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_PERSONALIZATIONSTRINGLENGTH_Pos) + /*!< Bit mask of PERSONALIZATIONSTRINGLENGTH field.*/ + +/* ADDITIONALINPUTLENGTH @Bits 28..31 : Value of g_additional_input_length/32. */ + #define CRACENCORE_IKG_HWCONFIG_ADDITIONALINPUTLENGTH_Pos (28UL) /*!< Position of ADDITIONALINPUTLENGTH field. */ + #define CRACENCORE_IKG_HWCONFIG_ADDITIONALINPUTLENGTH_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_ADDITIONALINPUTLENGTH_Pos) /*!< + Bit mask of ADDITIONALINPUTLENGTH field.*/ + + +/* ==================================================== Struct CRACENCORE ==================================================== */ +/** + * @brief CRACENCORE + */ + typedef struct { /*!< CRACENCORE Structure */ + __IOM NRF_CRACENCORE_CRYPTMSTRDMA_Type CRYPTMSTRDMA; /*!< (@ 0x00000000) (unspecified) */ + __IM uint32_t RESERVED[240]; + __IOM NRF_CRACENCORE_CRYPTMSTRHW_Type CRYPTMSTRHW; /*!< (@ 0x00000400) (unspecified) */ + __IM uint32_t RESERVED1[761]; + __IOM NRF_CRACENCORE_RNGCONTROL_Type RNGCONTROL; /*!< (@ 0x00001000) (unspecified) */ + __IM uint32_t RESERVED2[960]; + __IOM NRF_CRACENCORE_PK_Type PK; /*!< (@ 0x00002000) (unspecified) */ + __IM uint32_t RESERVED3[992]; + __IOM NRF_CRACENCORE_IKG_Type IKG; /*!< (@ 0x00003000) (unspecified) */ + } NRF_CRACENCORE_Type; /*!< Size = 12336 (0x3030) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CTRLAPPERI ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct CTRLAPPERI_MAILBOX ================================================ */ +/** + * @brief MAILBOX [CTRLAPPERI_MAILBOX] (unspecified) + */ +typedef struct { + __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ + __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) Status to indicate if data sent from the debugger to + the CPU has been read.*/ + __IM uint32_t RESERVED[30]; + __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ + __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) Status to indicate if data sent from the CPU to the + debugger has been read.*/ +} NRF_CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x088) */ + +/* CTRLAPPERI_MAILBOX_RXDATA: Data sent from the debugger to the CPU. */ + #define CTRLAPPERI_MAILBOX_RXDATA_ResetValue (0x00000000UL) /*!< Reset value of RXDATA register. */ + +/* RXDATA @Bits 0..31 : Data received from debugger. */ + #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */ + #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA + field.*/ + + +/* CTRLAPPERI_MAILBOX_RXSTATUS: Status to indicate if data sent from the debugger to the CPU has been read. */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_ResetValue (0x00000000UL) /*!< Reset value of RXSTATUS register. */ + +/* RXSTATUS @Bit 0 : Status of data in register RXDATA. */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS + field.*/ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Min (0x0UL) /*!< Min enumerator value of RXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Max (0x1UL) /*!< Max enumerator value of RXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0x0UL) /*!< No data is pending in register RXDATA. */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (0x1UL) /*!< Data is pending in register RXDATA. */ + + +/* CTRLAPPERI_MAILBOX_TXDATA: Data sent from the CPU to the debugger. */ + #define CTRLAPPERI_MAILBOX_TXDATA_ResetValue (0x00000000UL) /*!< Reset value of TXDATA register. */ + +/* TXDATA @Bits 0..31 : Data sent to debugger. */ + #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */ + #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA + field.*/ + + +/* CTRLAPPERI_MAILBOX_TXSTATUS: Status to indicate if data sent from the CPU to the debugger has been read. */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_ResetValue (0x00000000UL) /*!< Reset value of TXSTATUS register. */ + +/* TXSTATUS @Bit 0 : Status of data in register TXDATA. */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS + field.*/ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Min (0x0UL) /*!< Min enumerator value of TXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Max (0x1UL) /*!< Max enumerator value of TXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0x0UL) /*!< No data is pending in register TXDATA. */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (0x1UL) /*!< Data is pending in register TXDATA. */ + + + +/* ============================================= Struct CTRLAPPERI_ERASEPROTECT ============================================== */ +/** + * @brief ERASEPROTECT [CTRLAPPERI_ERASEPROTECT] (unspecified) + */ +typedef struct { + __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE register + from being written until next reset.*/ + __OM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register and + performs an ERASEALL operation.*/ +} NRF_CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x008) */ + +/* CTRLAPPERI_ERASEPROTECT_LOCK: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */ + #define CTRLAPPERI_ERASEPROTECT_LOCK_ResetValue (0x00000000UL) /*!< Reset value of LOCK register. */ + +/* LOCK @Bit 0 : Writing any value will lock the ERASEPROTECT.DISABLE register from being written until next reset. */ + #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ + #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Min (0x1UL) /*!< Min enumerator value of LOCK field. */ + #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (0x1UL) /*!< Register ERASEPROTECT.DISABLE is read-only. */ + + +/* CTRLAPPERI_ERASEPROTECT_DISABLE: This register disables the ERASEPROTECT register and performs an ERASEALL operation. */ + #define CTRLAPPERI_ERASEPROTECT_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of DISABLE register. */ + +/* KEY @Bits 0..31 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on + both the CPU and debugger sides. */ + + #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ + #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY + field.*/ + + +/* ==================================================== Struct CTRLAPPERI ==================================================== */ +/** + * @brief Control access port + */ + typedef struct { /*!< CTRLAPPERI Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000100) RXSTATUS is changed to DataPending. */ + __IOM uint32_t EVENTS_TXDONE; /*!< (@ 0x00000104) TXSTATUS is changed to NoDataPending. */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[60]; + __IOM NRF_CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) (unspecified) */ + __IM uint32_t RESERVED3[30]; + __IOM NRF_CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT; /*!< (@ 0x00000500) (unspecified) */ + __IM uint32_t RESERVED4[6]; + __OM uint32_t RESET; /*!< (@ 0x00000520) System reset request. */ + } NRF_CTRLAPPERI_Type; /*!< Size = 1316 (0x524) */ + +/* CTRLAPPERI_EVENTS_RXREADY: RXSTATUS is changed to DataPending. */ + #define CTRLAPPERI_EVENTS_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXREADY register. */ + +/* EVENTS_RXREADY @Bit 0 : RXSTATUS is changed to DataPending. */ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of + EVENTS_RXREADY field.*/ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXREADY field. */ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXREADY field. */ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0x0UL) /*!< Event not generated */ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Generated (0x1UL) /*!< Event generated */ + + +/* CTRLAPPERI_EVENTS_TXDONE: TXSTATUS is changed to NoDataPending. */ + #define CTRLAPPERI_EVENTS_TXDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXDONE register. */ + +/* EVENTS_TXDONE @Bit 0 : TXSTATUS is changed to NoDataPending. */ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Pos (0UL) /*!< Position of EVENTS_TXDONE field. */ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Msk (0x1UL << CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Pos) /*!< Bit mask of + EVENTS_TXDONE field.*/ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXDONE field. */ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXDONE field. */ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Generated (0x1UL) /*!< Event generated */ + + +/* CTRLAPPERI_INTEN: Enable or disable interrupt */ + #define CTRLAPPERI_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* RXREADY @Bit 0 : Enable or disable interrupt for event RXREADY */ + #define CTRLAPPERI_INTEN_RXREADY_Pos (0UL) /*!< Position of RXREADY field. */ + #define CTRLAPPERI_INTEN_RXREADY_Msk (0x1UL << CTRLAPPERI_INTEN_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define CTRLAPPERI_INTEN_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTEN_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTEN_RXREADY_Disabled (0x0UL) /*!< Disable */ + #define CTRLAPPERI_INTEN_RXREADY_Enabled (0x1UL) /*!< Enable */ + +/* TXDONE @Bit 1 : Enable or disable interrupt for event TXDONE */ + #define CTRLAPPERI_INTEN_TXDONE_Pos (1UL) /*!< Position of TXDONE field. */ + #define CTRLAPPERI_INTEN_TXDONE_Msk (0x1UL << CTRLAPPERI_INTEN_TXDONE_Pos) /*!< Bit mask of TXDONE field. */ + #define CTRLAPPERI_INTEN_TXDONE_Min (0x0UL) /*!< Min enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTEN_TXDONE_Max (0x1UL) /*!< Max enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTEN_TXDONE_Disabled (0x0UL) /*!< Disable */ + #define CTRLAPPERI_INTEN_TXDONE_Enabled (0x1UL) /*!< Enable */ + + +/* CTRLAPPERI_INTENSET: Enable interrupt */ + #define CTRLAPPERI_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* RXREADY @Bit 0 : Write '1' to enable interrupt for event RXREADY */ + #define CTRLAPPERI_INTENSET_RXREADY_Pos (0UL) /*!< Position of RXREADY field. */ + #define CTRLAPPERI_INTENSET_RXREADY_Msk (0x1UL << CTRLAPPERI_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define CTRLAPPERI_INTENSET_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTENSET_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTENSET_RXREADY_Set (0x1UL) /*!< Enable */ + #define CTRLAPPERI_INTENSET_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define CTRLAPPERI_INTENSET_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXDONE @Bit 1 : Write '1' to enable interrupt for event TXDONE */ + #define CTRLAPPERI_INTENSET_TXDONE_Pos (1UL) /*!< Position of TXDONE field. */ + #define CTRLAPPERI_INTENSET_TXDONE_Msk (0x1UL << CTRLAPPERI_INTENSET_TXDONE_Pos) /*!< Bit mask of TXDONE field. */ + #define CTRLAPPERI_INTENSET_TXDONE_Min (0x0UL) /*!< Min enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTENSET_TXDONE_Max (0x1UL) /*!< Max enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTENSET_TXDONE_Set (0x1UL) /*!< Enable */ + #define CTRLAPPERI_INTENSET_TXDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define CTRLAPPERI_INTENSET_TXDONE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CTRLAPPERI_INTENCLR: Disable interrupt */ + #define CTRLAPPERI_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* RXREADY @Bit 0 : Write '1' to disable interrupt for event RXREADY */ + #define CTRLAPPERI_INTENCLR_RXREADY_Pos (0UL) /*!< Position of RXREADY field. */ + #define CTRLAPPERI_INTENCLR_RXREADY_Msk (0x1UL << CTRLAPPERI_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define CTRLAPPERI_INTENCLR_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTENCLR_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTENCLR_RXREADY_Clear (0x1UL) /*!< Disable */ + #define CTRLAPPERI_INTENCLR_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define CTRLAPPERI_INTENCLR_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXDONE @Bit 1 : Write '1' to disable interrupt for event TXDONE */ + #define CTRLAPPERI_INTENCLR_TXDONE_Pos (1UL) /*!< Position of TXDONE field. */ + #define CTRLAPPERI_INTENCLR_TXDONE_Msk (0x1UL << CTRLAPPERI_INTENCLR_TXDONE_Pos) /*!< Bit mask of TXDONE field. */ + #define CTRLAPPERI_INTENCLR_TXDONE_Min (0x0UL) /*!< Min enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTENCLR_TXDONE_Max (0x1UL) /*!< Max enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTENCLR_TXDONE_Clear (0x1UL) /*!< Disable */ + #define CTRLAPPERI_INTENCLR_TXDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define CTRLAPPERI_INTENCLR_TXDONE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CTRLAPPERI_INTPEND: Pending interrupts */ + #define CTRLAPPERI_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* RXREADY @Bit 0 : Read pending status of interrupt for event RXREADY */ + #define CTRLAPPERI_INTPEND_RXREADY_Pos (0UL) /*!< Position of RXREADY field. */ + #define CTRLAPPERI_INTPEND_RXREADY_Msk (0x1UL << CTRLAPPERI_INTPEND_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define CTRLAPPERI_INTPEND_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTPEND_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTPEND_RXREADY_NotPending (0x0UL) /*!< Read: Not pending */ + #define CTRLAPPERI_INTPEND_RXREADY_Pending (0x1UL) /*!< Read: Pending */ + +/* TXDONE @Bit 1 : Read pending status of interrupt for event TXDONE */ + #define CTRLAPPERI_INTPEND_TXDONE_Pos (1UL) /*!< Position of TXDONE field. */ + #define CTRLAPPERI_INTPEND_TXDONE_Msk (0x1UL << CTRLAPPERI_INTPEND_TXDONE_Pos) /*!< Bit mask of TXDONE field. */ + #define CTRLAPPERI_INTPEND_TXDONE_Min (0x0UL) /*!< Min enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTPEND_TXDONE_Max (0x1UL) /*!< Max enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTPEND_TXDONE_NotPending (0x0UL) /*!< Read: Not pending */ + #define CTRLAPPERI_INTPEND_TXDONE_Pending (0x1UL) /*!< Read: Pending */ + + +/* CTRLAPPERI_RESET: System reset request. */ + #define CTRLAPPERI_RESET_ResetValue (0x00000000UL) /*!< Reset value of RESET register. */ + +/* RESET @Bits 0..2 : Reset request */ + #define CTRLAPPERI_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ + #define CTRLAPPERI_RESET_RESET_Msk (0x7UL << CTRLAPPERI_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ + #define CTRLAPPERI_RESET_RESET_Min (0x0UL) /*!< Min enumerator value of RESET field. */ + #define CTRLAPPERI_RESET_RESET_Max (0x4UL) /*!< Max enumerator value of RESET field. */ + #define CTRLAPPERI_RESET_RESET_NoReset (0x0UL) /*!< No reset is generated */ + #define CTRLAPPERI_RESET_RESET_SoftReset (0x1UL) /*!< Perform a device soft reset */ + #define CTRLAPPERI_RESET_RESET_HardReset (0x2UL) /*!< Perform a device hard reset */ + #define CTRLAPPERI_RESET_RESET_PinReset (0x4UL) /*!< Perform a device pin reset */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ DPPIC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================= Struct DPPIC_TASKS_CHG ================================================== */ +/** + * @brief TASKS_CHG [DPPIC_TASKS_CHG] Channel group tasks + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Enable channel group n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Disable channel group n */ +} NRF_DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x008) */ + #define DPPIC_TASKS_CHG_MaxCount (6UL) /*!< Size of TASKS_CHG[6] array. */ + #define DPPIC_TASKS_CHG_MaxIndex (5UL) /*!< Max index of TASKS_CHG[6] array. */ + #define DPPIC_TASKS_CHG_MinIndex (0UL) /*!< Min index of TASKS_CHG[6] array. */ + +/* DPPIC_TASKS_CHG_EN: Enable channel group n */ + #define DPPIC_TASKS_CHG_EN_ResetValue (0x00000000UL) /*!< Reset value of EN register. */ + +/* EN @Bit 0 : Enable channel group n */ + #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ + #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ + #define DPPIC_TASKS_CHG_EN_EN_Min (0x1UL) /*!< Min enumerator value of EN field. */ + #define DPPIC_TASKS_CHG_EN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define DPPIC_TASKS_CHG_EN_EN_Trigger (0x1UL) /*!< Trigger task */ + + +/* DPPIC_TASKS_CHG_DIS: Disable channel group n */ + #define DPPIC_TASKS_CHG_DIS_ResetValue (0x00000000UL) /*!< Reset value of DIS register. */ + +/* DIS @Bit 0 : Disable channel group n */ + #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ + #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ + #define DPPIC_TASKS_CHG_DIS_DIS_Min (0x1UL) /*!< Min enumerator value of DIS field. */ + #define DPPIC_TASKS_CHG_DIS_DIS_Max (0x1UL) /*!< Max enumerator value of DIS field. */ + #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (0x1UL) /*!< Trigger task */ + + + +/* =============================================== Struct DPPIC_SUBSCRIBE_CHG ================================================ */ +/** + * @brief SUBSCRIBE_CHG [DPPIC_SUBSCRIBE_CHG] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t EN; /*!< (@ 0x00000000) Subscribe configuration for task CHG[n].EN */ + __IOM uint32_t DIS; /*!< (@ 0x00000004) Subscribe configuration for task CHG[n].DIS */ +} NRF_DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x008) */ + #define DPPIC_SUBSCRIBE_CHG_MaxCount (6UL) /*!< Size of SUBSCRIBE_CHG[6] array. */ + #define DPPIC_SUBSCRIBE_CHG_MaxIndex (5UL) /*!< Max index of SUBSCRIBE_CHG[6] array. */ + #define DPPIC_SUBSCRIBE_CHG_MinIndex (0UL) /*!< Min index of SUBSCRIBE_CHG[6] array. */ + +/* DPPIC_SUBSCRIBE_CHG_EN: Subscribe configuration for task CHG[n].EN */ + #define DPPIC_SUBSCRIBE_CHG_EN_ResetValue (0x00000000UL) /*!< Reset value of EN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CHG[n].EN will subscribe to */ + #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* DPPIC_SUBSCRIBE_CHG_DIS: Subscribe configuration for task CHG[n].DIS */ + #define DPPIC_SUBSCRIBE_CHG_DIS_ResetValue (0x00000000UL) /*!< Reset value of DIS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CHG[n].DIS will subscribe to */ + #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* ====================================================== Struct DPPIC ======================================================= */ +/** + * @brief Distributed programmable peripheral interconnect controller + */ + typedef struct { /*!< DPPIC Structure */ + __OM NRF_DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[20]; + __IOM NRF_DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6]; /*!< (@ 0x00000080) Subscribe configuration for tasks */ + __IM uint32_t RESERVED1[276]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED2[189]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Channel group n Note: Writes to this register are + ignored if either SUBSCRIBE_CHG[n].EN or + SUBSCRIBE_CHG[n].DIS is enabled*/ + } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ + +/* DPPIC_CHEN: Channel enable register */ + #define DPPIC_CHEN_ResetValue (0x00000000UL) /*!< Reset value of CHEN register. */ + +/* CH0 @Bit 0 : Enable or disable channel 0 */ + #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define DPPIC_CHEN_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define DPPIC_CHEN_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define DPPIC_CHEN_CH0_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH0_Enabled (0x1UL) /*!< Enable channel */ + +/* CH1 @Bit 1 : Enable or disable channel 1 */ + #define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define DPPIC_CHEN_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define DPPIC_CHEN_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define DPPIC_CHEN_CH1_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH1_Enabled (0x1UL) /*!< Enable channel */ + +/* CH2 @Bit 2 : Enable or disable channel 2 */ + #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define DPPIC_CHEN_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define DPPIC_CHEN_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define DPPIC_CHEN_CH2_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH2_Enabled (0x1UL) /*!< Enable channel */ + +/* CH3 @Bit 3 : Enable or disable channel 3 */ + #define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define DPPIC_CHEN_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define DPPIC_CHEN_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define DPPIC_CHEN_CH3_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH3_Enabled (0x1UL) /*!< Enable channel */ + +/* CH4 @Bit 4 : Enable or disable channel 4 */ + #define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define DPPIC_CHEN_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define DPPIC_CHEN_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define DPPIC_CHEN_CH4_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH4_Enabled (0x1UL) /*!< Enable channel */ + +/* CH5 @Bit 5 : Enable or disable channel 5 */ + #define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define DPPIC_CHEN_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define DPPIC_CHEN_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define DPPIC_CHEN_CH5_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH5_Enabled (0x1UL) /*!< Enable channel */ + +/* CH6 @Bit 6 : Enable or disable channel 6 */ + #define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define DPPIC_CHEN_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define DPPIC_CHEN_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define DPPIC_CHEN_CH6_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH6_Enabled (0x1UL) /*!< Enable channel */ + +/* CH7 @Bit 7 : Enable or disable channel 7 */ + #define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define DPPIC_CHEN_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define DPPIC_CHEN_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define DPPIC_CHEN_CH7_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH7_Enabled (0x1UL) /*!< Enable channel */ + +/* CH8 @Bit 8 : Enable or disable channel 8 */ + #define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define DPPIC_CHEN_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define DPPIC_CHEN_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define DPPIC_CHEN_CH8_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH8_Enabled (0x1UL) /*!< Enable channel */ + +/* CH9 @Bit 9 : Enable or disable channel 9 */ + #define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define DPPIC_CHEN_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define DPPIC_CHEN_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define DPPIC_CHEN_CH9_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH9_Enabled (0x1UL) /*!< Enable channel */ + +/* CH10 @Bit 10 : Enable or disable channel 10 */ + #define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define DPPIC_CHEN_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define DPPIC_CHEN_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define DPPIC_CHEN_CH10_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH10_Enabled (0x1UL) /*!< Enable channel */ + +/* CH11 @Bit 11 : Enable or disable channel 11 */ + #define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define DPPIC_CHEN_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define DPPIC_CHEN_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define DPPIC_CHEN_CH11_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH11_Enabled (0x1UL) /*!< Enable channel */ + +/* CH12 @Bit 12 : Enable or disable channel 12 */ + #define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define DPPIC_CHEN_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define DPPIC_CHEN_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define DPPIC_CHEN_CH12_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH12_Enabled (0x1UL) /*!< Enable channel */ + +/* CH13 @Bit 13 : Enable or disable channel 13 */ + #define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define DPPIC_CHEN_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define DPPIC_CHEN_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define DPPIC_CHEN_CH13_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH13_Enabled (0x1UL) /*!< Enable channel */ + +/* CH14 @Bit 14 : Enable or disable channel 14 */ + #define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define DPPIC_CHEN_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define DPPIC_CHEN_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define DPPIC_CHEN_CH14_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH14_Enabled (0x1UL) /*!< Enable channel */ + +/* CH15 @Bit 15 : Enable or disable channel 15 */ + #define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define DPPIC_CHEN_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define DPPIC_CHEN_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define DPPIC_CHEN_CH15_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH15_Enabled (0x1UL) /*!< Enable channel */ + +/* CH16 @Bit 16 : Enable or disable channel 16 */ + #define DPPIC_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define DPPIC_CHEN_CH16_Msk (0x1UL << DPPIC_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define DPPIC_CHEN_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define DPPIC_CHEN_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define DPPIC_CHEN_CH16_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH16_Enabled (0x1UL) /*!< Enable channel */ + +/* CH17 @Bit 17 : Enable or disable channel 17 */ + #define DPPIC_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define DPPIC_CHEN_CH17_Msk (0x1UL << DPPIC_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define DPPIC_CHEN_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define DPPIC_CHEN_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define DPPIC_CHEN_CH17_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH17_Enabled (0x1UL) /*!< Enable channel */ + +/* CH18 @Bit 18 : Enable or disable channel 18 */ + #define DPPIC_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define DPPIC_CHEN_CH18_Msk (0x1UL << DPPIC_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define DPPIC_CHEN_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define DPPIC_CHEN_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define DPPIC_CHEN_CH18_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH18_Enabled (0x1UL) /*!< Enable channel */ + +/* CH19 @Bit 19 : Enable or disable channel 19 */ + #define DPPIC_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define DPPIC_CHEN_CH19_Msk (0x1UL << DPPIC_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define DPPIC_CHEN_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define DPPIC_CHEN_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define DPPIC_CHEN_CH19_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH19_Enabled (0x1UL) /*!< Enable channel */ + +/* CH20 @Bit 20 : Enable or disable channel 20 */ + #define DPPIC_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define DPPIC_CHEN_CH20_Msk (0x1UL << DPPIC_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define DPPIC_CHEN_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define DPPIC_CHEN_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define DPPIC_CHEN_CH20_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH20_Enabled (0x1UL) /*!< Enable channel */ + +/* CH21 @Bit 21 : Enable or disable channel 21 */ + #define DPPIC_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define DPPIC_CHEN_CH21_Msk (0x1UL << DPPIC_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define DPPIC_CHEN_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define DPPIC_CHEN_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define DPPIC_CHEN_CH21_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH21_Enabled (0x1UL) /*!< Enable channel */ + +/* CH22 @Bit 22 : Enable or disable channel 22 */ + #define DPPIC_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define DPPIC_CHEN_CH22_Msk (0x1UL << DPPIC_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define DPPIC_CHEN_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define DPPIC_CHEN_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define DPPIC_CHEN_CH22_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH22_Enabled (0x1UL) /*!< Enable channel */ + +/* CH23 @Bit 23 : Enable or disable channel 23 */ + #define DPPIC_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define DPPIC_CHEN_CH23_Msk (0x1UL << DPPIC_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define DPPIC_CHEN_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define DPPIC_CHEN_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define DPPIC_CHEN_CH23_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH23_Enabled (0x1UL) /*!< Enable channel */ + + +/* DPPIC_CHENSET: Channel enable set register */ + #define DPPIC_CHENSET_ResetValue (0x00000000UL) /*!< Reset value of CHENSET register. */ + +/* CH0 @Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define DPPIC_CHENSET_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define DPPIC_CHENSET_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define DPPIC_CHENSET_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH0_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH1 @Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define DPPIC_CHENSET_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define DPPIC_CHENSET_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define DPPIC_CHENSET_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH1_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH2 @Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define DPPIC_CHENSET_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define DPPIC_CHENSET_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define DPPIC_CHENSET_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH2_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH3 @Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define DPPIC_CHENSET_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define DPPIC_CHENSET_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define DPPIC_CHENSET_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH3_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH4 @Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define DPPIC_CHENSET_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define DPPIC_CHENSET_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define DPPIC_CHENSET_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH4_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH5 @Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define DPPIC_CHENSET_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define DPPIC_CHENSET_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define DPPIC_CHENSET_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH5_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH6 @Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define DPPIC_CHENSET_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define DPPIC_CHENSET_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define DPPIC_CHENSET_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH6_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH7 @Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define DPPIC_CHENSET_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define DPPIC_CHENSET_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define DPPIC_CHENSET_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH7_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH8 @Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define DPPIC_CHENSET_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define DPPIC_CHENSET_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define DPPIC_CHENSET_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH8_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH9 @Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define DPPIC_CHENSET_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define DPPIC_CHENSET_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define DPPIC_CHENSET_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH9_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH10 @Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define DPPIC_CHENSET_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define DPPIC_CHENSET_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define DPPIC_CHENSET_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH10_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH11 @Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define DPPIC_CHENSET_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define DPPIC_CHENSET_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define DPPIC_CHENSET_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH11_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH12 @Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define DPPIC_CHENSET_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define DPPIC_CHENSET_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define DPPIC_CHENSET_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH12_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH13 @Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define DPPIC_CHENSET_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define DPPIC_CHENSET_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define DPPIC_CHENSET_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH13_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH14 @Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define DPPIC_CHENSET_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define DPPIC_CHENSET_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define DPPIC_CHENSET_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH14_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH15 @Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define DPPIC_CHENSET_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define DPPIC_CHENSET_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define DPPIC_CHENSET_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH15_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH16 @Bit 16 : Channel 16 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define DPPIC_CHENSET_CH16_Msk (0x1UL << DPPIC_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define DPPIC_CHENSET_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define DPPIC_CHENSET_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define DPPIC_CHENSET_CH16_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH16_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH16_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH17 @Bit 17 : Channel 17 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define DPPIC_CHENSET_CH17_Msk (0x1UL << DPPIC_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define DPPIC_CHENSET_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define DPPIC_CHENSET_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define DPPIC_CHENSET_CH17_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH17_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH17_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH18 @Bit 18 : Channel 18 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define DPPIC_CHENSET_CH18_Msk (0x1UL << DPPIC_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define DPPIC_CHENSET_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define DPPIC_CHENSET_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define DPPIC_CHENSET_CH18_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH18_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH18_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH19 @Bit 19 : Channel 19 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define DPPIC_CHENSET_CH19_Msk (0x1UL << DPPIC_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define DPPIC_CHENSET_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define DPPIC_CHENSET_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define DPPIC_CHENSET_CH19_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH19_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH19_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH20 @Bit 20 : Channel 20 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define DPPIC_CHENSET_CH20_Msk (0x1UL << DPPIC_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define DPPIC_CHENSET_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define DPPIC_CHENSET_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define DPPIC_CHENSET_CH20_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH20_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH20_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH21 @Bit 21 : Channel 21 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define DPPIC_CHENSET_CH21_Msk (0x1UL << DPPIC_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define DPPIC_CHENSET_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define DPPIC_CHENSET_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define DPPIC_CHENSET_CH21_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH21_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH21_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH22 @Bit 22 : Channel 22 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define DPPIC_CHENSET_CH22_Msk (0x1UL << DPPIC_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define DPPIC_CHENSET_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define DPPIC_CHENSET_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define DPPIC_CHENSET_CH22_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH22_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH22_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH23 @Bit 23 : Channel 23 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define DPPIC_CHENSET_CH23_Msk (0x1UL << DPPIC_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define DPPIC_CHENSET_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define DPPIC_CHENSET_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define DPPIC_CHENSET_CH23_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH23_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH23_Set (0x1UL) /*!< Write: Enable channel */ + + +/* DPPIC_CHENCLR: Channel enable clear register */ + #define DPPIC_CHENCLR_ResetValue (0x00000000UL) /*!< Reset value of CHENCLR register. */ + +/* CH0 @Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define DPPIC_CHENCLR_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define DPPIC_CHENCLR_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define DPPIC_CHENCLR_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH0_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH1 @Bit 1 : Channel 1 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define DPPIC_CHENCLR_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define DPPIC_CHENCLR_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define DPPIC_CHENCLR_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH1_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH2 @Bit 2 : Channel 2 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define DPPIC_CHENCLR_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define DPPIC_CHENCLR_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define DPPIC_CHENCLR_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH2_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH3 @Bit 3 : Channel 3 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define DPPIC_CHENCLR_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define DPPIC_CHENCLR_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define DPPIC_CHENCLR_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH3_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH4 @Bit 4 : Channel 4 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define DPPIC_CHENCLR_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define DPPIC_CHENCLR_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define DPPIC_CHENCLR_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH4_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH5 @Bit 5 : Channel 5 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define DPPIC_CHENCLR_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define DPPIC_CHENCLR_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define DPPIC_CHENCLR_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH5_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH6 @Bit 6 : Channel 6 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define DPPIC_CHENCLR_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define DPPIC_CHENCLR_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define DPPIC_CHENCLR_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH6_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH7 @Bit 7 : Channel 7 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define DPPIC_CHENCLR_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define DPPIC_CHENCLR_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define DPPIC_CHENCLR_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH7_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH8 @Bit 8 : Channel 8 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define DPPIC_CHENCLR_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define DPPIC_CHENCLR_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define DPPIC_CHENCLR_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH8_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH9 @Bit 9 : Channel 9 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define DPPIC_CHENCLR_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define DPPIC_CHENCLR_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define DPPIC_CHENCLR_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH9_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH10 @Bit 10 : Channel 10 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define DPPIC_CHENCLR_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define DPPIC_CHENCLR_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define DPPIC_CHENCLR_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH10_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH11 @Bit 11 : Channel 11 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define DPPIC_CHENCLR_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define DPPIC_CHENCLR_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define DPPIC_CHENCLR_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH11_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH12 @Bit 12 : Channel 12 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define DPPIC_CHENCLR_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define DPPIC_CHENCLR_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define DPPIC_CHENCLR_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH12_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH13 @Bit 13 : Channel 13 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define DPPIC_CHENCLR_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define DPPIC_CHENCLR_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define DPPIC_CHENCLR_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH13_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH14 @Bit 14 : Channel 14 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define DPPIC_CHENCLR_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define DPPIC_CHENCLR_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define DPPIC_CHENCLR_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH14_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH15 @Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define DPPIC_CHENCLR_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define DPPIC_CHENCLR_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define DPPIC_CHENCLR_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH15_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH16 @Bit 16 : Channel 16 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define DPPIC_CHENCLR_CH16_Msk (0x1UL << DPPIC_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define DPPIC_CHENCLR_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define DPPIC_CHENCLR_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define DPPIC_CHENCLR_CH16_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH16_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH16_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH17 @Bit 17 : Channel 17 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define DPPIC_CHENCLR_CH17_Msk (0x1UL << DPPIC_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define DPPIC_CHENCLR_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define DPPIC_CHENCLR_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define DPPIC_CHENCLR_CH17_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH17_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH17_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH18 @Bit 18 : Channel 18 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define DPPIC_CHENCLR_CH18_Msk (0x1UL << DPPIC_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define DPPIC_CHENCLR_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define DPPIC_CHENCLR_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define DPPIC_CHENCLR_CH18_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH18_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH18_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH19 @Bit 19 : Channel 19 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define DPPIC_CHENCLR_CH19_Msk (0x1UL << DPPIC_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define DPPIC_CHENCLR_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define DPPIC_CHENCLR_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define DPPIC_CHENCLR_CH19_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH19_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH19_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH20 @Bit 20 : Channel 20 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define DPPIC_CHENCLR_CH20_Msk (0x1UL << DPPIC_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define DPPIC_CHENCLR_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define DPPIC_CHENCLR_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define DPPIC_CHENCLR_CH20_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH20_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH20_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH21 @Bit 21 : Channel 21 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define DPPIC_CHENCLR_CH21_Msk (0x1UL << DPPIC_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define DPPIC_CHENCLR_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define DPPIC_CHENCLR_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define DPPIC_CHENCLR_CH21_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH21_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH21_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH22 @Bit 22 : Channel 22 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define DPPIC_CHENCLR_CH22_Msk (0x1UL << DPPIC_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define DPPIC_CHENCLR_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define DPPIC_CHENCLR_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define DPPIC_CHENCLR_CH22_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH22_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH22_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH23 @Bit 23 : Channel 23 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define DPPIC_CHENCLR_CH23_Msk (0x1UL << DPPIC_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define DPPIC_CHENCLR_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define DPPIC_CHENCLR_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define DPPIC_CHENCLR_CH23_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH23_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH23_Clear (0x1UL) /*!< Write: Disable channel */ + + +/* DPPIC_CHG: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is + enabled */ + + #define DPPIC_CHG_MaxCount (6UL) /*!< Max size of CHG[6] array. */ + #define DPPIC_CHG_MaxIndex (5UL) /*!< Max index of CHG[6] array. */ + #define DPPIC_CHG_MinIndex (0UL) /*!< Min index of CHG[6] array. */ + #define DPPIC_CHG_ResetValue (0x00000000UL) /*!< Reset value of CHG[6] register. */ + +/* CH0 @Bit 0 : Include or exclude channel 0 */ + #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define DPPIC_CHG_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define DPPIC_CHG_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define DPPIC_CHG_CH0_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH0_Included (0x1UL) /*!< Include */ + +/* CH1 @Bit 1 : Include or exclude channel 1 */ + #define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define DPPIC_CHG_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define DPPIC_CHG_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define DPPIC_CHG_CH1_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH1_Included (0x1UL) /*!< Include */ + +/* CH2 @Bit 2 : Include or exclude channel 2 */ + #define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define DPPIC_CHG_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define DPPIC_CHG_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define DPPIC_CHG_CH2_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH2_Included (0x1UL) /*!< Include */ + +/* CH3 @Bit 3 : Include or exclude channel 3 */ + #define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define DPPIC_CHG_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define DPPIC_CHG_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define DPPIC_CHG_CH3_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH3_Included (0x1UL) /*!< Include */ + +/* CH4 @Bit 4 : Include or exclude channel 4 */ + #define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define DPPIC_CHG_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define DPPIC_CHG_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define DPPIC_CHG_CH4_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH4_Included (0x1UL) /*!< Include */ + +/* CH5 @Bit 5 : Include or exclude channel 5 */ + #define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define DPPIC_CHG_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define DPPIC_CHG_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define DPPIC_CHG_CH5_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH5_Included (0x1UL) /*!< Include */ + +/* CH6 @Bit 6 : Include or exclude channel 6 */ + #define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define DPPIC_CHG_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define DPPIC_CHG_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define DPPIC_CHG_CH6_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH6_Included (0x1UL) /*!< Include */ + +/* CH7 @Bit 7 : Include or exclude channel 7 */ + #define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define DPPIC_CHG_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define DPPIC_CHG_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define DPPIC_CHG_CH7_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH7_Included (0x1UL) /*!< Include */ + +/* CH8 @Bit 8 : Include or exclude channel 8 */ + #define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define DPPIC_CHG_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define DPPIC_CHG_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define DPPIC_CHG_CH8_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH8_Included (0x1UL) /*!< Include */ + +/* CH9 @Bit 9 : Include or exclude channel 9 */ + #define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define DPPIC_CHG_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define DPPIC_CHG_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define DPPIC_CHG_CH9_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH9_Included (0x1UL) /*!< Include */ + +/* CH10 @Bit 10 : Include or exclude channel 10 */ + #define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define DPPIC_CHG_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define DPPIC_CHG_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define DPPIC_CHG_CH10_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH10_Included (0x1UL) /*!< Include */ + +/* CH11 @Bit 11 : Include or exclude channel 11 */ + #define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define DPPIC_CHG_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define DPPIC_CHG_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define DPPIC_CHG_CH11_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH11_Included (0x1UL) /*!< Include */ + +/* CH12 @Bit 12 : Include or exclude channel 12 */ + #define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define DPPIC_CHG_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define DPPIC_CHG_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define DPPIC_CHG_CH12_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH12_Included (0x1UL) /*!< Include */ + +/* CH13 @Bit 13 : Include or exclude channel 13 */ + #define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define DPPIC_CHG_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define DPPIC_CHG_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define DPPIC_CHG_CH13_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH13_Included (0x1UL) /*!< Include */ + +/* CH14 @Bit 14 : Include or exclude channel 14 */ + #define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define DPPIC_CHG_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define DPPIC_CHG_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define DPPIC_CHG_CH14_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH14_Included (0x1UL) /*!< Include */ + +/* CH15 @Bit 15 : Include or exclude channel 15 */ + #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define DPPIC_CHG_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define DPPIC_CHG_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define DPPIC_CHG_CH15_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH15_Included (0x1UL) /*!< Include */ + +/* CH16 @Bit 16 : Include or exclude channel 16 */ + #define DPPIC_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define DPPIC_CHG_CH16_Msk (0x1UL << DPPIC_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define DPPIC_CHG_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define DPPIC_CHG_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define DPPIC_CHG_CH16_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH16_Included (0x1UL) /*!< Include */ + +/* CH17 @Bit 17 : Include or exclude channel 17 */ + #define DPPIC_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define DPPIC_CHG_CH17_Msk (0x1UL << DPPIC_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define DPPIC_CHG_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define DPPIC_CHG_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define DPPIC_CHG_CH17_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH17_Included (0x1UL) /*!< Include */ + +/* CH18 @Bit 18 : Include or exclude channel 18 */ + #define DPPIC_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define DPPIC_CHG_CH18_Msk (0x1UL << DPPIC_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define DPPIC_CHG_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define DPPIC_CHG_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define DPPIC_CHG_CH18_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH18_Included (0x1UL) /*!< Include */ + +/* CH19 @Bit 19 : Include or exclude channel 19 */ + #define DPPIC_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define DPPIC_CHG_CH19_Msk (0x1UL << DPPIC_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define DPPIC_CHG_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define DPPIC_CHG_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define DPPIC_CHG_CH19_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH19_Included (0x1UL) /*!< Include */ + +/* CH20 @Bit 20 : Include or exclude channel 20 */ + #define DPPIC_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define DPPIC_CHG_CH20_Msk (0x1UL << DPPIC_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define DPPIC_CHG_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define DPPIC_CHG_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define DPPIC_CHG_CH20_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH20_Included (0x1UL) /*!< Include */ + +/* CH21 @Bit 21 : Include or exclude channel 21 */ + #define DPPIC_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define DPPIC_CHG_CH21_Msk (0x1UL << DPPIC_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define DPPIC_CHG_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define DPPIC_CHG_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define DPPIC_CHG_CH21_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH21_Included (0x1UL) /*!< Include */ + +/* CH22 @Bit 22 : Include or exclude channel 22 */ + #define DPPIC_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define DPPIC_CHG_CH22_Msk (0x1UL << DPPIC_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define DPPIC_CHG_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define DPPIC_CHG_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define DPPIC_CHG_CH22_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH22_Included (0x1UL) /*!< Include */ + +/* CH23 @Bit 23 : Include or exclude channel 23 */ + #define DPPIC_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define DPPIC_CHG_CH23_Msk (0x1UL << DPPIC_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define DPPIC_CHG_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define DPPIC_CHG_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define DPPIC_CHG_CH23_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH23_Included (0x1UL) /*!< Include */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ===================================================== Struct ECB_KEY ====================================================== */ +/** + * @brief KEY [ECB_KEY] (unspecified) + */ +typedef struct { + __OM uint32_t VALUE[4]; /*!< (@ 0x00000000) 128-bit AES key */ +} NRF_ECB_KEY_Type; /*!< Size = 16 (0x010) */ + +/* ECB_KEY_VALUE: 128-bit AES key */ + #define ECB_KEY_VALUE_MaxCount (4UL) /*!< Max size of VALUE[4] array. */ + #define ECB_KEY_VALUE_MaxIndex (3UL) /*!< Max index of VALUE[4] array. */ + #define ECB_KEY_VALUE_MinIndex (0UL) /*!< Min index of VALUE[4] array. */ + #define ECB_KEY_VALUE_ResetValue (0x00000000UL) /*!< Reset value of VALUE[4] register. */ + +/* VALUE @Bits 0..31 : AES 128-bit key value, bits (32*(n+1))-1 : (32*n) */ + #define ECB_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define ECB_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << ECB_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + + +/* ====================================================== Struct ECB_IN ====================================================== */ +/** + * @brief IN [ECB_IN] IN EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Input pointer */ +} NRF_ECB_IN_Type; /*!< Size = 4 (0x004) */ + +/* ECB_IN_PTR: Input pointer */ + #define ECB_IN_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Points to a job list containing unencrypted ECB data structure */ + #define ECB_IN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define ECB_IN_PTR_PTR_Msk (0xFFFFFFFFUL << ECB_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + + +/* ===================================================== Struct ECB_OUT ====================================================== */ +/** + * @brief OUT [ECB_OUT] OUT EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Output pointer Points to a job list containing + encrypted ECB data structure*/ +} NRF_ECB_OUT_Type; /*!< Size = 4 (0x004) */ + +/* ECB_OUT_PTR: Output pointer Points to a job list containing encrypted ECB data structure */ + #define ECB_OUT_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Output pointer */ + #define ECB_OUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define ECB_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << ECB_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + + +/* ===================================================== Struct ECB_CSAA ===================================================== */ +/** + * @brief CSAA [ECB_CSAA] Channel sounding access address scoring algorithm + */ +typedef struct { + __IM uint32_t REFLECTOR; /*!< (@ 0x00000000) Selected Channel Sounding Access Address used in the CS + SYNC from Reflector to Initiator*/ + __IM uint32_t INITIATOR; /*!< (@ 0x00000004) Selected Channel Sounding Access Address used in the CS + SYNC from Initiator to Reflector*/ + __IOM uint32_t MODE; /*!< (@ 0x00000008) Operation modes */ +} NRF_ECB_CSAA_Type; /*!< Size = 12 (0x00C) */ + +/* ECB_CSAA_REFLECTOR: Selected Channel Sounding Access Address used in the CS SYNC from Reflector to Initiator */ + #define ECB_CSAA_REFLECTOR_ResetValue (0x00000000UL) /*!< Reset value of REFLECTOR register. */ + +/* PN @Bits 0..31 : (unspecified) */ + #define ECB_CSAA_REFLECTOR_PN_Pos (0UL) /*!< Position of PN field. */ + #define ECB_CSAA_REFLECTOR_PN_Msk (0xFFFFFFFFUL << ECB_CSAA_REFLECTOR_PN_Pos) /*!< Bit mask of PN field. */ + + +/* ECB_CSAA_INITIATOR: Selected Channel Sounding Access Address used in the CS SYNC from Initiator to Reflector */ + #define ECB_CSAA_INITIATOR_ResetValue (0x00000000UL) /*!< Reset value of INITIATOR register. */ + +/* PN @Bits 0..31 : (unspecified) */ + #define ECB_CSAA_INITIATOR_PN_Pos (0UL) /*!< Position of PN field. */ + #define ECB_CSAA_INITIATOR_PN_Msk (0xFFFFFFFFUL << ECB_CSAA_INITIATOR_PN_Pos) /*!< Bit mask of PN field. */ + + +/* ECB_CSAA_MODE: Operation modes */ + #define ECB_CSAA_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* BITREVERSE @Bit 0 : Reverse the endianness on bit level for the ECB output, INITIATOR, and REFLECTOR registers */ + #define ECB_CSAA_MODE_BITREVERSE_Pos (0UL) /*!< Position of BITREVERSE field. */ + #define ECB_CSAA_MODE_BITREVERSE_Msk (0x1UL << ECB_CSAA_MODE_BITREVERSE_Pos) /*!< Bit mask of BITREVERSE field. */ + #define ECB_CSAA_MODE_BITREVERSE_Min (0x0UL) /*!< Min enumerator value of BITREVERSE field. */ + #define ECB_CSAA_MODE_BITREVERSE_Max (0x1UL) /*!< Max enumerator value of BITREVERSE field. */ + #define ECB_CSAA_MODE_BITREVERSE_Default (0x0UL) /*!< Default endianness */ + #define ECB_CSAA_MODE_BITREVERSE_Reversed (0x1UL) /*!< Reversed endianness */ + + +/* ======================================================= Struct ECB ======================================================== */ +/** + * @brief AES ECB Mode Encryption + */ + typedef struct { /*!< ECB Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOP task or due + to an error*/ + __IM uint32_t RESERVED2[30]; + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000180) Publish configuration for event END */ + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000184) Publish configuration for event ERROR */ + __IM uint32_t RESERVED3[95]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IM uint32_t ERRORSTATUS; /*!< (@ 0x00000400) Error status */ + __IM uint32_t RESERVED5[67]; + __IOM NRF_ECB_KEY_Type KEY; /*!< (@ 0x00000510) (unspecified) */ + __IM uint32_t RESERVED6[4]; + __IOM NRF_ECB_IN_Type IN; /*!< (@ 0x00000530) IN EasyDMA channel */ + __IM uint32_t RESERVED7; + __IOM NRF_ECB_OUT_Type OUT; /*!< (@ 0x00000538) OUT EasyDMA channel */ + __IOM NRF_ECB_CSAA_Type CSAA; /*!< (@ 0x0000053C) Channel sounding access address scoring algorithm */ + } NRF_ECB_Type; /*!< Size = 1352 (0x548) */ + +/* ECB_TASKS_START: Start ECB block encrypt */ + #define ECB_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start ECB block encrypt */ + #define ECB_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define ECB_TASKS_START_TASKS_START_Msk (0x1UL << ECB_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define ECB_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define ECB_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define ECB_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* ECB_TASKS_STOP: Abort a possible executing ECB operation */ + #define ECB_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Abort a possible executing ECB operation */ + #define ECB_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define ECB_TASKS_STOP_TASKS_STOP_Msk (0x1UL << ECB_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define ECB_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define ECB_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define ECB_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* ECB_SUBSCRIBE_START: Subscribe configuration for task START */ + #define ECB_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define ECB_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define ECB_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define ECB_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define ECB_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define ECB_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define ECB_SUBSCRIBE_START_EN_Msk (0x1UL << ECB_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define ECB_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ECB_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ECB_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define ECB_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* ECB_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define ECB_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define ECB_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define ECB_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define ECB_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define ECB_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define ECB_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define ECB_SUBSCRIBE_STOP_EN_Msk (0x1UL << ECB_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define ECB_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ECB_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ECB_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define ECB_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* ECB_EVENTS_END: ECB block encrypt complete */ + #define ECB_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : ECB block encrypt complete */ + #define ECB_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define ECB_EVENTS_END_EVENTS_END_Msk (0x1UL << ECB_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define ECB_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define ECB_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define ECB_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define ECB_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* ECB_EVENTS_ERROR: ECB block encrypt aborted because of a STOP task or due to an error */ + #define ECB_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : ECB block encrypt aborted because of a STOP task or due to an error */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << ECB_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* ECB_PUBLISH_END: Publish configuration for event END */ + #define ECB_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define ECB_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define ECB_PUBLISH_END_CHIDX_Msk (0xFFUL << ECB_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define ECB_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define ECB_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define ECB_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define ECB_PUBLISH_END_EN_Msk (0x1UL << ECB_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define ECB_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ECB_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ECB_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define ECB_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* ECB_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define ECB_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define ECB_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define ECB_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define ECB_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define ECB_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define ECB_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define ECB_PUBLISH_ERROR_EN_Msk (0x1UL << ECB_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define ECB_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ECB_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ECB_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define ECB_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* ECB_INTENSET: Enable interrupt */ + #define ECB_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* END @Bit 0 : Write '1' to enable interrupt for event END */ + #define ECB_INTENSET_END_Pos (0UL) /*!< Position of END field. */ + #define ECB_INTENSET_END_Msk (0x1UL << ECB_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define ECB_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define ECB_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define ECB_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define ECB_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define ECB_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 1 : Write '1' to enable interrupt for event ERROR */ + #define ECB_INTENSET_ERROR_Pos (1UL) /*!< Position of ERROR field. */ + #define ECB_INTENSET_ERROR_Msk (0x1UL << ECB_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define ECB_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define ECB_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define ECB_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define ECB_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define ECB_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* ECB_INTENCLR: Disable interrupt */ + #define ECB_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* END @Bit 0 : Write '1' to disable interrupt for event END */ + #define ECB_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ + #define ECB_INTENCLR_END_Msk (0x1UL << ECB_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define ECB_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define ECB_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define ECB_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define ECB_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define ECB_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 1 : Write '1' to disable interrupt for event ERROR */ + #define ECB_INTENCLR_ERROR_Pos (1UL) /*!< Position of ERROR field. */ + #define ECB_INTENCLR_ERROR_Msk (0x1UL << ECB_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define ECB_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define ECB_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define ECB_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define ECB_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define ECB_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* ECB_ERRORSTATUS: Error status */ + #define ECB_ERRORSTATUS_ResetValue (0x00000000UL) /*!< Reset value of ERRORSTATUS register. */ + +/* ERRORSTATUS @Bits 0..2 : Error status when the ERROR event is generated */ + #define ECB_ERRORSTATUS_ERRORSTATUS_Pos (0UL) /*!< Position of ERRORSTATUS field. */ + #define ECB_ERRORSTATUS_ERRORSTATUS_Msk (0x7UL << ECB_ERRORSTATUS_ERRORSTATUS_Pos) /*!< Bit mask of ERRORSTATUS field. */ + #define ECB_ERRORSTATUS_ERRORSTATUS_Min (0x0UL) /*!< Min enumerator value of ERRORSTATUS field. */ + #define ECB_ERRORSTATUS_ERRORSTATUS_Max (0x4UL) /*!< Max enumerator value of ERRORSTATUS field. */ + #define ECB_ERRORSTATUS_ERRORSTATUS_NoError (0x0UL) /*!< No errors have occurred */ + #define ECB_ERRORSTATUS_ERRORSTATUS_PrematureInptrEnd (0x1UL) /*!< End of INPTR job list before data structure was read. */ + #define ECB_ERRORSTATUS_ERRORSTATUS_PrematureOutptrEnd (0x2UL) /*!< End of OUTPTR job list before data structure was read. */ + #define ECB_ERRORSTATUS_ERRORSTATUS_EncryptionTooSlow (0x3UL) /*!< Encryption aborted due to higher priority peripheral + requesting or using the AES module.*/ + #define ECB_ERRORSTATUS_ERRORSTATUS_Aborted (0x3UL) /*!< Encryption aborted due to higher priority peripheral requesting or + using the AES module.*/ + #define ECB_ERRORSTATUS_ERRORSTATUS_DmaError (0x4UL) /*!< Bus error during DMA access. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ EGU ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct EGU ======================================================== */ +/** + * @brief Event generator unit + */ + typedef struct { /*!< EGU Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Trigger n for triggering the corresponding TRIGGERED[n] + event*/ + __IM uint32_t RESERVED[16]; + __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Subscribe configuration for task TRIGGER[n] */ + __IM uint32_t RESERVED1[16]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Event number n generated by triggering the + corresponding TRIGGER[n] task*/ + __IM uint32_t RESERVED2[16]; + __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Publish configuration for event TRIGGERED[n] */ + __IM uint32_t RESERVED3[80]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + } NRF_EGU_Type; /*!< Size = 780 (0x30C) */ + +/* EGU_TASKS_TRIGGER: Trigger n for triggering the corresponding TRIGGERED[n] event */ + #define EGU_TASKS_TRIGGER_MaxCount (16UL) /*!< Max size of TASKS_TRIGGER[16] array. */ + #define EGU_TASKS_TRIGGER_MaxIndex (15UL) /*!< Max index of TASKS_TRIGGER[16] array. */ + #define EGU_TASKS_TRIGGER_MinIndex (0UL) /*!< Min index of TASKS_TRIGGER[16] array. */ + #define EGU_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[16] register. */ + +/* TASKS_TRIGGER @Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ + #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ + #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER + field.*/ + #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field. */ + #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field. */ + #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */ + + +/* EGU_SUBSCRIBE_TRIGGER: Subscribe configuration for task TRIGGER[n] */ + #define EGU_SUBSCRIBE_TRIGGER_MaxCount (16UL) /*!< Max size of SUBSCRIBE_TRIGGER[16] array. */ + #define EGU_SUBSCRIBE_TRIGGER_MaxIndex (15UL) /*!< Max index of SUBSCRIBE_TRIGGER[16] array. */ + #define EGU_SUBSCRIBE_TRIGGER_MinIndex (0UL) /*!< Min index of SUBSCRIBE_TRIGGER[16] array. */ + #define EGU_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[16] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task TRIGGER[n] will subscribe to */ + #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* EGU_EVENTS_TRIGGERED: Event number n generated by triggering the corresponding TRIGGER[n] task */ + #define EGU_EVENTS_TRIGGERED_MaxCount (16UL) /*!< Max size of EVENTS_TRIGGERED[16] array. */ + #define EGU_EVENTS_TRIGGERED_MaxIndex (15UL) /*!< Max index of EVENTS_TRIGGERED[16] array. */ + #define EGU_EVENTS_TRIGGERED_MinIndex (0UL) /*!< Min index of EVENTS_TRIGGERED[16] array. */ + #define EGU_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[16] register. */ + +/* EVENTS_TRIGGERED @Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of + EVENTS_TRIGGERED field.*/ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TRIGGERED field. */ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TRIGGERED field. */ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated */ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated */ + + +/* EGU_PUBLISH_TRIGGERED: Publish configuration for event TRIGGERED[n] */ + #define EGU_PUBLISH_TRIGGERED_MaxCount (16UL) /*!< Max size of PUBLISH_TRIGGERED[16] array. */ + #define EGU_PUBLISH_TRIGGERED_MaxIndex (15UL) /*!< Max index of PUBLISH_TRIGGERED[16] array. */ + #define EGU_PUBLISH_TRIGGERED_MinIndex (0UL) /*!< Min index of PUBLISH_TRIGGERED[16] array. */ + #define EGU_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[16] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TRIGGERED[n] will publish to */ + #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define EGU_PUBLISH_TRIGGERED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define EGU_PUBLISH_TRIGGERED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ + #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */ + #define EGU_PUBLISH_TRIGGERED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define EGU_PUBLISH_TRIGGERED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define EGU_PUBLISH_TRIGGERED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* EGU_INTEN: Enable or disable interrupt */ + #define EGU_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ + #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define EGU_INTEN_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define EGU_INTEN_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define EGU_INTEN_TRIGGERED0_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED0_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ + #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define EGU_INTEN_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define EGU_INTEN_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define EGU_INTEN_TRIGGERED1_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED1_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ + #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define EGU_INTEN_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define EGU_INTEN_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define EGU_INTEN_TRIGGERED2_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED2_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ + #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define EGU_INTEN_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define EGU_INTEN_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define EGU_INTEN_TRIGGERED3_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED3_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ + #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define EGU_INTEN_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define EGU_INTEN_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define EGU_INTEN_TRIGGERED4_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED4_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ + #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define EGU_INTEN_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define EGU_INTEN_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define EGU_INTEN_TRIGGERED5_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED5_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ + #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define EGU_INTEN_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define EGU_INTEN_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define EGU_INTEN_TRIGGERED6_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED6_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ + #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define EGU_INTEN_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define EGU_INTEN_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define EGU_INTEN_TRIGGERED7_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED7_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ + #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define EGU_INTEN_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define EGU_INTEN_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define EGU_INTEN_TRIGGERED8_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED8_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ + #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define EGU_INTEN_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define EGU_INTEN_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define EGU_INTEN_TRIGGERED9_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED9_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ + #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define EGU_INTEN_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define EGU_INTEN_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define EGU_INTEN_TRIGGERED10_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED10_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ + #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define EGU_INTEN_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define EGU_INTEN_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define EGU_INTEN_TRIGGERED11_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED11_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ + #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define EGU_INTEN_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define EGU_INTEN_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define EGU_INTEN_TRIGGERED12_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED12_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ + #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define EGU_INTEN_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define EGU_INTEN_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define EGU_INTEN_TRIGGERED13_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED13_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ + #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define EGU_INTEN_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define EGU_INTEN_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define EGU_INTEN_TRIGGERED14_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED14_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ + #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define EGU_INTEN_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define EGU_INTEN_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define EGU_INTEN_TRIGGERED15_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED15_Enabled (0x1UL) /*!< Enable */ + + +/* EGU_INTENSET: Enable interrupt */ + #define EGU_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ + #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define EGU_INTENSET_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define EGU_INTENSET_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define EGU_INTENSET_TRIGGERED0_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ + #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define EGU_INTENSET_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define EGU_INTENSET_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define EGU_INTENSET_TRIGGERED1_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ + #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define EGU_INTENSET_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define EGU_INTENSET_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define EGU_INTENSET_TRIGGERED2_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ + #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define EGU_INTENSET_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define EGU_INTENSET_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define EGU_INTENSET_TRIGGERED3_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ + #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define EGU_INTENSET_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define EGU_INTENSET_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define EGU_INTENSET_TRIGGERED4_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ + #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define EGU_INTENSET_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define EGU_INTENSET_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define EGU_INTENSET_TRIGGERED5_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ + #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define EGU_INTENSET_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define EGU_INTENSET_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define EGU_INTENSET_TRIGGERED6_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ + #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define EGU_INTENSET_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define EGU_INTENSET_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define EGU_INTENSET_TRIGGERED7_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ + #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define EGU_INTENSET_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define EGU_INTENSET_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define EGU_INTENSET_TRIGGERED8_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ + #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define EGU_INTENSET_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define EGU_INTENSET_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define EGU_INTENSET_TRIGGERED9_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ + #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define EGU_INTENSET_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define EGU_INTENSET_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define EGU_INTENSET_TRIGGERED10_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ + #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define EGU_INTENSET_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define EGU_INTENSET_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define EGU_INTENSET_TRIGGERED11_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ + #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define EGU_INTENSET_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define EGU_INTENSET_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define EGU_INTENSET_TRIGGERED12_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ + #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define EGU_INTENSET_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define EGU_INTENSET_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define EGU_INTENSET_TRIGGERED13_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ + #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define EGU_INTENSET_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define EGU_INTENSET_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define EGU_INTENSET_TRIGGERED14_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ + #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define EGU_INTENSET_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define EGU_INTENSET_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define EGU_INTENSET_TRIGGERED15_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* EGU_INTENCLR: Disable interrupt */ + #define EGU_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ + #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define EGU_INTENCLR_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define EGU_INTENCLR_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define EGU_INTENCLR_TRIGGERED0_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ + #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define EGU_INTENCLR_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define EGU_INTENCLR_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define EGU_INTENCLR_TRIGGERED1_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ + #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define EGU_INTENCLR_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define EGU_INTENCLR_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define EGU_INTENCLR_TRIGGERED2_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ + #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define EGU_INTENCLR_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define EGU_INTENCLR_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define EGU_INTENCLR_TRIGGERED3_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ + #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define EGU_INTENCLR_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define EGU_INTENCLR_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define EGU_INTENCLR_TRIGGERED4_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ + #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define EGU_INTENCLR_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define EGU_INTENCLR_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define EGU_INTENCLR_TRIGGERED5_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ + #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define EGU_INTENCLR_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define EGU_INTENCLR_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define EGU_INTENCLR_TRIGGERED6_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ + #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define EGU_INTENCLR_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define EGU_INTENCLR_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define EGU_INTENCLR_TRIGGERED7_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ + #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define EGU_INTENCLR_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define EGU_INTENCLR_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define EGU_INTENCLR_TRIGGERED8_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ + #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define EGU_INTENCLR_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define EGU_INTENCLR_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define EGU_INTENCLR_TRIGGERED9_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ + #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define EGU_INTENCLR_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define EGU_INTENCLR_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define EGU_INTENCLR_TRIGGERED10_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ + #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define EGU_INTENCLR_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define EGU_INTENCLR_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define EGU_INTENCLR_TRIGGERED11_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ + #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define EGU_INTENCLR_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define EGU_INTENCLR_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define EGU_INTENCLR_TRIGGERED12_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ + #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define EGU_INTENCLR_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define EGU_INTENCLR_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define EGU_INTENCLR_TRIGGERED13_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ + #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define EGU_INTENCLR_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define EGU_INTENCLR_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define EGU_INTENCLR_TRIGGERED14_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ + #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define EGU_INTENCLR_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define EGU_INTENCLR_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define EGU_INTENCLR_TRIGGERED15_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ ETM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct ETM ======================================================== */ +/** + * @brief Embedded Trace Macrocell + */ + typedef struct { /*!< ETM Structure */ + __IM uint32_t RESERVED; + __IOM uint32_t TRCPRGCTLR; /*!< (@ 0x00000004) Enables the trace unit. */ + __IOM uint32_t TRCPROCSELR; /*!< (@ 0x00000008) Controls which PE to trace. Might ignore writes when + the trace unit is enabled or not idle. Before writing + to this register, ensure that TRCSTATR.IDLE == 1 so + that the trace unit can synchronize with the chosen PE. + Implemented if TRCIDR3.NUMPROC is greater than zero.*/ + __IOM uint32_t TRCSTATR; /*!< (@ 0x0000000C) Idle status bit */ + __IOM uint32_t TRCCONFIGR; /*!< (@ 0x00000010) Controls the tracing options This register must always + be programmed as part of trace unit initialization. + Might ignore writes when the trace unit is enabled or + not idle.*/ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t TRCEVENTCTL0R; /*!< (@ 0x00000020) Controls the tracing of arbitrary events. If the + selected event occurs a trace element is generated in + the trace stream according to the settings in + TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN.*/ + __IOM uint32_t TRCEVENTCTL1R; /*!< (@ 0x00000024) Controls the behavior of the events that TRCEVENTCTL0R + selects. This register must always be programmed as + part of trace unit initialization. Might ignore writes + when the trace unit is enabled or not idle.*/ + __IM uint32_t RESERVED2; + __IOM uint32_t TRCSTALLCTLR; /*!< (@ 0x0000002C) Enables trace unit functionality that prevents trace + unit buffer overflows. Might ignore writes when the + trace unit is enabled or not idle. Must be programmed + if TRCIDR3.STALLCTL == 1.*/ + __IOM uint32_t TRCTSCTLR; /*!< (@ 0x00000030) Controls the insertion of global timestamps in the + trace streams. When the selected event is triggered, + the trace unit inserts a global timestamp into the + trace streams. Might ignore writes when the trace unit + is enabled or not idle. Must be programmed if + TRCCONFIGR.TS == 1.*/ + __IOM uint32_t TRCSYNCPR; /*!< (@ 0x00000034) Controls how often trace synchronization requests + occur. Might ignore writes when the trace unit is + enabled or not idle. If writes are permitted then the + register must be programmed.*/ + __IOM uint32_t TRCCCCTLR; /*!< (@ 0x00000038) Sets the threshold value for cycle counting. Might + ignore writes when the trace unit is enabled or not + idle. Must be programmed if TRCCONFIGR.CCI==1.*/ + __IOM uint32_t TRCBBCTLR; /*!< (@ 0x0000003C) Controls which regions in the memory map are enabled to + use branch broadcasting. Might ignore writes when the + trace unit is enabled or not idle. Must be programmed + if TRCCONFIGR.BB == 1.*/ + __IOM uint32_t TRCTRACEIDR; /*!< (@ 0x00000040) Sets the trace ID for instruction trace. If data trace + is enabled then it also sets the trace ID for data + trace, to (trace ID for instruction trace) + 1. This + register must always be programmed as part of trace + unit initialization. Might ignore writes when the trace + unit is enabled or not idle.*/ + __IOM uint32_t TRCQCTLR; /*!< (@ 0x00000044) Controls when Q elements are enabled. Might ignore + writes when the trace unit is enabled or not idle. This + register must be programmed if it is implemented and + TRCCONFIGR.QE is set to any value other than 0b00.*/ + __IM uint32_t RESERVED3[14]; + __IOM uint32_t TRCVICTLR; /*!< (@ 0x00000080) Controls instruction trace filtering. Might ignore + writes when the trace unit is enabled or not idle. Only + returns stable data when TRCSTATR.PMSTABLE == 1. Must + be programmed, particularly to set the value of the + SSSTATUS bit, which sets the state of the start/stop + logic.*/ + __IOM uint32_t TRCVIIECTLR; /*!< (@ 0x00000084) ViewInst exclude control. Might ignore writes when the + trace unit is enabled or not idle. This register must + be programmed when one or more address comparators are + implemented.*/ + __IOM uint32_t TRCVISSCTLR; /*!< (@ 0x00000088) Use this to set, or read, the single address + comparators that control the ViewInst start/stop logic. + The start/stop logic is active for an instruction which + causes a start and remains active up to and including + an instruction which causes a stop, and then the + start/stop logic becomes inactive. Might ignore writes + when the trace unit is enabled or not idle. If + implemented then this register must be programmed.*/ + __IOM uint32_t TRCVIPCSSCTLR; /*!< (@ 0x0000008C) Use this to set, or read, which PE comparator inputs + can control the ViewInst start/stop logic. Might ignore + writes when the trace unit is enabled or not idle. If + implemented then this register must be programmed.*/ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t TRCVDCTLR; /*!< (@ 0x000000A0) Controls data trace filtering. Might ignore writes when + the trace unit is enabled or not idle. This register + must be programmed when data tracing is enabled, that + is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == + 1.*/ + __IOM uint32_t TRCVDSACCTLR; /*!< (@ 0x000000A4) ViewData include / exclude control. Might ignore writes + when the trace unit is enabled or not idle. This + register must be programmed when one or more address + comparators are implemented.*/ + __IOM uint32_t TRCVDARCCTLR; /*!< (@ 0x000000A8) ViewData include / exclude control. Might ignore writes + when the trace unit is enabled or not idle. This + register must be programmed when one or more address + comparators are implemented.*/ + __IM uint32_t RESERVED5[21]; + __IOM uint32_t TRCSEQEVR[3]; /*!< (@ 0x00000100) Moves the sequencer state according to programmed + events. Might ignore writes when the trace unit is + enabled or not idle. When the sequencer is used, all + sequencer state transitions must be programmed with a + valid event.*/ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t TRCSEQRSTEVR; /*!< (@ 0x00000118) Moves the sequencer to state 0 when a programmed event + occurs. Might ignore writes when the trace unit is + enabled or not idle. When the sequencer is used, all + sequencer state transitions must be programmed with a + valid event.*/ + __IOM uint32_t TRCSEQSTR; /*!< (@ 0x0000011C) Use this to set, or read, the sequencer state. Might + ignore writes when the trace unit is enabled or not + idle. Only returns stable data when TRCSTATR.PMSTABLE + == 1. When the sequencer is used, all sequencer state + transitions must be programmed with a valid event.*/ + __IOM uint32_t TRCEXTINSELR; /*!< (@ 0x00000120) Use this to set, or read, which external inputs are + resources to the trace unit. Might ignore writes when + the trace unit is enabled or not idle. Only returns + stable data when TRCSTATR.PMSTABLE == 1. When the + sequencer is used, all sequencer state transitions must + be programmed with a valid event.*/ + __IM uint32_t RESERVED7[7]; + __IOM uint32_t TRCCNTRLDVR[4]; /*!< (@ 0x00000140) This sets or returns the reload count value for counter + n. Might ignore writes when the trace unit is enabled + or not idle.*/ + __IOM uint32_t TRCCNTCTLR[4]; /*!< (@ 0x00000150) Controls the operation of counter n. Might ignore + writes when the trace unit is enabled or not idle.*/ + __IOM uint32_t TRCCNTVR[4]; /*!< (@ 0x00000160) This sets or returns the value of counter n. The count + value is only stable when TRCSTATR.PMSTABLE == 1. If + software uses counter n then it must write to this + register to set the initial counter value. Might ignore + writes when the trace unit is enabled or not idle.*/ + __IM uint32_t RESERVED8[36]; + __IOM uint32_t TRCRSCTLR[32]; /*!< (@ 0x00000200) Controls the selection of the resources in the trace + unit. Might ignore writes when the trace unit is + enabled or not idle. If software selects a + non-implemented resource then CONSTRAINED UNPREDICTABLE + behavior of the resource selector occurs, so the + resource selector might fire unexpectedly or might not + fire. Reads of the TRCRSCTLRn might return UNKNOWN.*/ + __IOM uint32_t TRCSSCCR0; /*!< (@ 0x00000280) Controls the single-shot comparator. */ + __IM uint32_t RESERVED9[7]; + __IOM uint32_t TRCSSCSR0; /*!< (@ 0x000002A0) Indicates the status of the single-shot comparators. + TRCSSCSR0 is sensitive toinstruction addresses.*/ + __IM uint32_t RESERVED10[7]; + __IOM uint32_t TRCSSPCICR0; /*!< (@ 0x000002C0) Selects the processor comparator inputs for Single-shot + control.*/ + __IM uint32_t RESERVED11[19]; + __IOM uint32_t TRCPDCR; /*!< (@ 0x00000310) Controls the single-shot comparator. */ + __IOM uint32_t TRCPDSR; /*!< (@ 0x00000314) Indicates the power down status of the ETM. */ + __IM uint32_t RESERVED12[755]; + __IOM uint32_t TRCITATBIDR; /*!< (@ 0x00000EE4) Sets the state of output pins. */ + __IM uint32_t RESERVED13[3]; + __IOM uint32_t TRCITIATBINR; /*!< (@ 0x00000EF4) Reads the state of the input pins. */ + __IM uint32_t RESERVED14; + __IOM uint32_t TRCITIATBOUTR; /*!< (@ 0x00000EFC) Sets the state of the output pins. */ + __IOM uint32_t TRCITCTRL; /*!< (@ 0x00000F00) Enables topology detection or integration testing, by + putting ETM-M33 into integration mode.*/ + __IM uint32_t RESERVED15[39]; + __IOM uint32_t TRCCLAIMSET; /*!< (@ 0x00000FA0) Sets bits in the claim tag and determines the number of + claim tag bits implemented.*/ + __IOM uint32_t TRCCLAIMCLR; /*!< (@ 0x00000FA4) Clears bits in the claim tag and determines the current + value of the claim tag.*/ + __IM uint32_t RESERVED16[4]; + __IOM uint32_t TRCAUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the + system*/ + __IM uint32_t TRCDEVARCH; /*!< (@ 0x00000FBC) The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 + component*/ + __IM uint32_t RESERVED17[3]; + __IM uint32_t TRCDEVTYPE; /*!< (@ 0x00000FCC) Controls the single-shot comparator. */ + __IOM uint32_t TRCPIDR[8]; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ + __IOM uint32_t TRCCIDR[4]; /*!< (@ 0x00000FF0) Coresight component identification registers. */ + } NRF_ETM_Type; /*!< Size = 4096 (0x1000) */ + +/* ETM_TRCPRGCTLR: Enables the trace unit. */ + #define ETM_TRCPRGCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCPRGCTLR register. */ + +/* EN @Bit 0 : Trace unit enable bit */ + #define ETM_TRCPRGCTLR_EN_Pos (0UL) /*!< Position of EN field. */ + #define ETM_TRCPRGCTLR_EN_Msk (0x1UL << ETM_TRCPRGCTLR_EN_Pos) /*!< Bit mask of EN field. */ + #define ETM_TRCPRGCTLR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ETM_TRCPRGCTLR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ETM_TRCPRGCTLR_EN_Disabled (0x0UL) /*!< The trace unit is disabled. All trace resources are inactive and no + trace is generated.*/ + #define ETM_TRCPRGCTLR_EN_Enabled (0x1UL) /*!< The trace unit is enabled. */ + + +/* ETM_TRCPROCSELR: Controls which PE to trace. Might ignore writes when the trace unit is enabled or not idle. Before writing + to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE. + Implemented if TRCIDR3.NUMPROC is greater than zero. */ + + #define ETM_TRCPROCSELR_ResetValue (0x00000000UL) /*!< Reset value of TRCPROCSELR register. */ + +/* PROCSEL @Bits 0..4 : PE select bits that select the PE to trace. */ + #define ETM_TRCPROCSELR_PROCSEL_Pos (0UL) /*!< Position of PROCSEL field. */ + #define ETM_TRCPROCSELR_PROCSEL_Msk (0x1FUL << ETM_TRCPROCSELR_PROCSEL_Pos) /*!< Bit mask of PROCSEL field. */ + + +/* ETM_TRCSTATR: Idle status bit */ + #define ETM_TRCSTATR_ResetValue (0x00000000UL) /*!< Reset value of TRCSTATR register. */ + +/* IDLE @Bit 0 : Trace unit enable bit */ + #define ETM_TRCSTATR_IDLE_Pos (0UL) /*!< Position of IDLE field. */ + #define ETM_TRCSTATR_IDLE_Msk (0x1UL << ETM_TRCSTATR_IDLE_Pos) /*!< Bit mask of IDLE field. */ + #define ETM_TRCSTATR_IDLE_Min (0x0UL) /*!< Min enumerator value of IDLE field. */ + #define ETM_TRCSTATR_IDLE_Max (0x1UL) /*!< Max enumerator value of IDLE field. */ + #define ETM_TRCSTATR_IDLE_NotIdle (0x0UL) /*!< The trace unit is not idle. */ + #define ETM_TRCSTATR_IDLE_Idle (0x1UL) /*!< The trace unit is idle. */ + +/* PMSTABLE @Bit 1 : Programmers' model stable bit */ + #define ETM_TRCSTATR_PMSTABLE_Pos (1UL) /*!< Position of PMSTABLE field. */ + #define ETM_TRCSTATR_PMSTABLE_Msk (0x1UL << ETM_TRCSTATR_PMSTABLE_Pos) /*!< Bit mask of PMSTABLE field. */ + #define ETM_TRCSTATR_PMSTABLE_Min (0x0UL) /*!< Min enumerator value of PMSTABLE field. */ + #define ETM_TRCSTATR_PMSTABLE_Max (0x1UL) /*!< Max enumerator value of PMSTABLE field. */ + #define ETM_TRCSTATR_PMSTABLE_NotStable (0x0UL) /*!< The programmers' model is not stable. */ + #define ETM_TRCSTATR_PMSTABLE_Stable (0x1UL) /*!< The programmers' model is stable. */ + + +/* ETM_TRCCONFIGR: Controls the tracing options This register must always be programmed as part of trace unit initialization. + Might ignore writes when the trace unit is enabled or not idle. */ + + #define ETM_TRCCONFIGR_ResetValue (0x00000000UL) /*!< Reset value of TRCCONFIGR register. */ + +/* LOADASP0INST @Bit 1 : Instruction P0 load field. This field controls whether load instructions are traced as P0 instructions. + */ + + #define ETM_TRCCONFIGR_LOADASP0INST_Pos (1UL) /*!< Position of LOADASP0INST field. */ + #define ETM_TRCCONFIGR_LOADASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_LOADASP0INST_Pos) /*!< Bit mask of LOADASP0INST field. */ + #define ETM_TRCCONFIGR_LOADASP0INST_Min (0x0UL) /*!< Min enumerator value of LOADASP0INST field. */ + #define ETM_TRCCONFIGR_LOADASP0INST_Max (0x1UL) /*!< Max enumerator value of LOADASP0INST field. */ + #define ETM_TRCCONFIGR_LOADASP0INST_No (0x0UL) /*!< Do not trace load instructions as P0 instructions. */ + #define ETM_TRCCONFIGR_LOADASP0INST_Yes (0x1UL) /*!< Trace load instructions as P0 instructions. */ + +/* STOREASP0INST @Bit 2 : Instruction P0 field. This field controls whether store instructions are traced as P0 instructions. */ + #define ETM_TRCCONFIGR_STOREASP0INST_Pos (2UL) /*!< Position of STOREASP0INST field. */ + #define ETM_TRCCONFIGR_STOREASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_STOREASP0INST_Pos) /*!< Bit mask of STOREASP0INST field. */ + #define ETM_TRCCONFIGR_STOREASP0INST_Min (0x0UL) /*!< Min enumerator value of STOREASP0INST field. */ + #define ETM_TRCCONFIGR_STOREASP0INST_Max (0x1UL) /*!< Max enumerator value of STOREASP0INST field. */ + #define ETM_TRCCONFIGR_STOREASP0INST_No (0x0UL) /*!< Do not trace store instructions as P0 instructions. */ + #define ETM_TRCCONFIGR_STOREASP0INST_Yes (0x1UL) /*!< Trace store instructions as P0 instructions. */ + +/* BB @Bit 3 : Branch broadcast mode bit. */ + #define ETM_TRCCONFIGR_BB_Pos (3UL) /*!< Position of BB field. */ + #define ETM_TRCCONFIGR_BB_Msk (0x1UL << ETM_TRCCONFIGR_BB_Pos) /*!< Bit mask of BB field. */ + #define ETM_TRCCONFIGR_BB_Min (0x0UL) /*!< Min enumerator value of BB field. */ + #define ETM_TRCCONFIGR_BB_Max (0x1UL) /*!< Max enumerator value of BB field. */ + #define ETM_TRCCONFIGR_BB_Disabled (0x0UL) /*!< Branch broadcast mode is disabled. */ + #define ETM_TRCCONFIGR_BB_Enabled (0x1UL) /*!< Branch broadcast mode is enabled. */ + +/* CCI @Bit 4 : Cycle counting instruction trace bit. */ + #define ETM_TRCCONFIGR_CCI_Pos (4UL) /*!< Position of CCI field. */ + #define ETM_TRCCONFIGR_CCI_Msk (0x1UL << ETM_TRCCONFIGR_CCI_Pos) /*!< Bit mask of CCI field. */ + #define ETM_TRCCONFIGR_CCI_Min (0x0UL) /*!< Min enumerator value of CCI field. */ + #define ETM_TRCCONFIGR_CCI_Max (0x1UL) /*!< Max enumerator value of CCI field. */ + #define ETM_TRCCONFIGR_CCI_Disabled (0x0UL) /*!< Cycle counting in the instruction trace is disabled. */ + #define ETM_TRCCONFIGR_CCI_Enabled (0x1UL) /*!< Cycle counting in the instruction trace is enabled. */ + +/* CID @Bit 6 : Context ID tracing bit. */ + #define ETM_TRCCONFIGR_CID_Pos (6UL) /*!< Position of CID field. */ + #define ETM_TRCCONFIGR_CID_Msk (0x1UL << ETM_TRCCONFIGR_CID_Pos) /*!< Bit mask of CID field. */ + #define ETM_TRCCONFIGR_CID_Min (0x0UL) /*!< Min enumerator value of CID field. */ + #define ETM_TRCCONFIGR_CID_Max (0x1UL) /*!< Max enumerator value of CID field. */ + #define ETM_TRCCONFIGR_CID_Disabled (0x0UL) /*!< Context ID tracing is disabled. */ + #define ETM_TRCCONFIGR_CID_Enabled (0x1UL) /*!< Context ID tracing is enabled. */ + +/* VMID @Bit 7 : Virtual context identifier tracing bit. */ + #define ETM_TRCCONFIGR_VMID_Pos (7UL) /*!< Position of VMID field. */ + #define ETM_TRCCONFIGR_VMID_Msk (0x1UL << ETM_TRCCONFIGR_VMID_Pos) /*!< Bit mask of VMID field. */ + #define ETM_TRCCONFIGR_VMID_Min (0x0UL) /*!< Min enumerator value of VMID field. */ + #define ETM_TRCCONFIGR_VMID_Max (0x1UL) /*!< Max enumerator value of VMID field. */ + #define ETM_TRCCONFIGR_VMID_Disabled (0x0UL) /*!< Virtual context identifier tracing is disabled. */ + #define ETM_TRCCONFIGR_VMID_Enabled (0x1UL) /*!< Virtual context identifier tracing is enabled. */ + +/* COND @Bits 8..10 : Conditional instruction tracing bit. */ + #define ETM_TRCCONFIGR_COND_Pos (8UL) /*!< Position of COND field. */ + #define ETM_TRCCONFIGR_COND_Msk (0x7UL << ETM_TRCCONFIGR_COND_Pos) /*!< Bit mask of COND field. */ + #define ETM_TRCCONFIGR_COND_Min (0x0UL) /*!< Min enumerator value of COND field. */ + #define ETM_TRCCONFIGR_COND_Max (0x7UL) /*!< Max enumerator value of COND field. */ + #define ETM_TRCCONFIGR_COND_Disabled (0x0UL) /*!< Conditional instruction tracing is disabled. */ + #define ETM_TRCCONFIGR_COND_LoadOnly (0x1UL) /*!< Conditional load instructions are traced. */ + #define ETM_TRCCONFIGR_COND_StoreOnly (0x2UL) /*!< Conditional store instructions are traced. */ + #define ETM_TRCCONFIGR_COND_LoadAndStore (0x3UL) /*!< Conditional load and store instructions are traced. */ + #define ETM_TRCCONFIGR_COND_All (0x7UL) /*!< All conditional instructions are traced. */ + +/* TS @Bit 11 : Global timestamp tracing bit. */ + #define ETM_TRCCONFIGR_TS_Pos (11UL) /*!< Position of TS field. */ + #define ETM_TRCCONFIGR_TS_Msk (0x1UL << ETM_TRCCONFIGR_TS_Pos) /*!< Bit mask of TS field. */ + #define ETM_TRCCONFIGR_TS_Min (0x0UL) /*!< Min enumerator value of TS field. */ + #define ETM_TRCCONFIGR_TS_Max (0x1UL) /*!< Max enumerator value of TS field. */ + #define ETM_TRCCONFIGR_TS_Disabled (0x0UL) /*!< Global timestamp tracing is disabled. */ + #define ETM_TRCCONFIGR_TS_Enabled (0x1UL) /*!< Global timestamp tracing is enabled. */ + +/* RS @Bit 12 : Return stack enable bit. */ + #define ETM_TRCCONFIGR_RS_Pos (12UL) /*!< Position of RS field. */ + #define ETM_TRCCONFIGR_RS_Msk (0x1UL << ETM_TRCCONFIGR_RS_Pos) /*!< Bit mask of RS field. */ + #define ETM_TRCCONFIGR_RS_Min (0x0UL) /*!< Min enumerator value of RS field. */ + #define ETM_TRCCONFIGR_RS_Max (0x1UL) /*!< Max enumerator value of RS field. */ + #define ETM_TRCCONFIGR_RS_Disabled (0x0UL) /*!< Return stack is disabled. */ + #define ETM_TRCCONFIGR_RS_Enabled (0x1UL) /*!< Return stack is enabled. */ + +/* QE @Bits 13..14 : Q element enable field. */ + #define ETM_TRCCONFIGR_QE_Pos (13UL) /*!< Position of QE field. */ + #define ETM_TRCCONFIGR_QE_Msk (0x3UL << ETM_TRCCONFIGR_QE_Pos) /*!< Bit mask of QE field. */ + #define ETM_TRCCONFIGR_QE_Min (0x0UL) /*!< Min enumerator value of QE field. */ + #define ETM_TRCCONFIGR_QE_Max (0x3UL) /*!< Max enumerator value of QE field. */ + #define ETM_TRCCONFIGR_QE_Disabled (0x0UL) /*!< Q elements are disabled. */ + #define ETM_TRCCONFIGR_QE_OnlyWithoutInstCounts (0x1UL) /*!< Q elements with instruction counts are enabled. Q elements + without instruction counts are disabled.*/ + #define ETM_TRCCONFIGR_QE_Enabled (0x3UL) /*!< Q elements with and without instruction counts are enabled. */ + +/* VMIDOPT @Bit 15 : Control bit to select the Virtual context identifier value used by the trace unit, both for trace + generation and in the Virtual context identifier comparators. */ + + #define ETM_TRCCONFIGR_VMIDOPT_Pos (15UL) /*!< Position of VMIDOPT field. */ + #define ETM_TRCCONFIGR_VMIDOPT_Msk (0x1UL << ETM_TRCCONFIGR_VMIDOPT_Pos) /*!< Bit mask of VMIDOPT field. */ + #define ETM_TRCCONFIGR_VMIDOPT_Min (0x0UL) /*!< Min enumerator value of VMIDOPT field. */ + #define ETM_TRCCONFIGR_VMIDOPT_Max (0x1UL) /*!< Max enumerator value of VMIDOPT field. */ + #define ETM_TRCCONFIGR_VMIDOPT_VTTBR_EL2 (0x0UL) /*!< VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context + identifier larger than the VTTBR_EL2.VMID, the upper unused bits are + always zero. If the trace unit supports a Virtual context identifier + larger than 8 bits and if the VTCR_EL2.VS bit forces use of an 8-bit + Virtual context identifier, bits [15:8] of the trace unit Virtual + context identifier are always zero.*/ + #define ETM_TRCCONFIGR_VMIDOPT_CONTEXTIDR_EL2 (0x1UL) /*!< CONTEXTIDR_EL2 is used. */ + +/* DA @Bit 16 : Data address tracing bit. */ + #define ETM_TRCCONFIGR_DA_Pos (16UL) /*!< Position of DA field. */ + #define ETM_TRCCONFIGR_DA_Msk (0x1UL << ETM_TRCCONFIGR_DA_Pos) /*!< Bit mask of DA field. */ + #define ETM_TRCCONFIGR_DA_Min (0x0UL) /*!< Min enumerator value of DA field. */ + #define ETM_TRCCONFIGR_DA_Max (0x1UL) /*!< Max enumerator value of DA field. */ + #define ETM_TRCCONFIGR_DA_Disabled (0x0UL) /*!< Data address tracing is disabled. */ + #define ETM_TRCCONFIGR_DA_Enabled (0x1UL) /*!< Data address tracing is enabled. */ + +/* DV @Bit 17 : Data value tracing bit. */ + #define ETM_TRCCONFIGR_DV_Pos (17UL) /*!< Position of DV field. */ + #define ETM_TRCCONFIGR_DV_Msk (0x1UL << ETM_TRCCONFIGR_DV_Pos) /*!< Bit mask of DV field. */ + #define ETM_TRCCONFIGR_DV_Min (0x0UL) /*!< Min enumerator value of DV field. */ + #define ETM_TRCCONFIGR_DV_Max (0x1UL) /*!< Max enumerator value of DV field. */ + #define ETM_TRCCONFIGR_DV_Disabled (0x0UL) /*!< Data value tracing is disabled. */ + #define ETM_TRCCONFIGR_DV_Enabled (0x1UL) /*!< Data value tracing is enabled. */ + + +/* ETM_TRCEVENTCTL0R: Controls the tracing of arbitrary events. If the selected event occurs a trace element is generated in the + trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN. */ + + #define ETM_TRCEVENTCTL0R_ResetValue (0x00000000UL) /*!< Reset value of TRCEVENTCTL0R register. */ + +/* EVENT @Bits 0..7 : Select which event should generate trace elements. */ + #define ETM_TRCEVENTCTL0R_EVENT_Pos (0UL) /*!< Position of EVENT field. */ + #define ETM_TRCEVENTCTL0R_EVENT_Msk (0xFFUL << ETM_TRCEVENTCTL0R_EVENT_Pos) /*!< Bit mask of EVENT field. */ + #define ETM_TRCEVENTCTL0R_EVENT_Min (0x00UL) /*!< Min value of EVENT field. */ + #define ETM_TRCEVENTCTL0R_EVENT_Max (0xFFUL) /*!< Max size of EVENT field. */ + + +/* ETM_TRCEVENTCTL1R: Controls the behavior of the events that TRCEVENTCTL0R selects. This register must always be programmed as + part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. */ + + #define ETM_TRCEVENTCTL1R_ResetValue (0x00000000UL) /*!< Reset value of TRCEVENTCTL1R register. */ + +/* INSTEN0 @Bit 0 : Instruction event enable field. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Pos (0UL) /*!< Position of INSTEN0 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN0_Pos) /*!< Bit mask of INSTEN0 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Min (0x0UL) /*!< Min enumerator value of INSTEN0 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Max (0x1UL) /*!< Max enumerator value of INSTEN0 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 0, in the + instruction trace stream.*/ + +/* INSTEN1 @Bit 1 : Instruction event enable field. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Pos (1UL) /*!< Position of INSTEN1 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN1_Pos) /*!< Bit mask of INSTEN1 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Min (0x0UL) /*!< Min enumerator value of INSTEN1 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Max (0x1UL) /*!< Max enumerator value of INSTEN1 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 1, in the + instruction trace stream.*/ + +/* INSTEN2 @Bit 2 : Instruction event enable field. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Pos (2UL) /*!< Position of INSTEN2 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN2_Pos) /*!< Bit mask of INSTEN2 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Min (0x0UL) /*!< Min enumerator value of INSTEN2 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Max (0x1UL) /*!< Max enumerator value of INSTEN2 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 2, in the + instruction trace stream.*/ + +/* INSTEN3 @Bit 3 : Instruction event enable field. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Pos (3UL) /*!< Position of INSTEN3 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN3_Pos) /*!< Bit mask of INSTEN3 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Min (0x0UL) /*!< Min enumerator value of INSTEN3 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Max (0x1UL) /*!< Max enumerator value of INSTEN3 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 3, in the + instruction trace stream.*/ + +/* DATAEN @Bit 4 : Data event enable bit. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Pos (4UL) /*!< Position of DATAEN field. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Msk (0x1UL << ETM_TRCEVENTCTL1R_DATAEN_Pos) /*!< Bit mask of DATAEN field. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Min (0x0UL) /*!< Min enumerator value of DATAEN field. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Max (0x1UL) /*!< Max enumerator value of DATAEN field. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Disabled (0x0UL) /*!< The trace unit does not generate an Event element if event 0 occurs. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Enabled (0x1UL) /*!< The trace unit generates an Event element in the data trace stream if + event 0 occurs.*/ + +/* ATB @Bit 11 : AMBA Trace Bus (ATB) trigger enable bit. */ + #define ETM_TRCEVENTCTL1R_ATB_Pos (11UL) /*!< Position of ATB field. */ + #define ETM_TRCEVENTCTL1R_ATB_Msk (0x1UL << ETM_TRCEVENTCTL1R_ATB_Pos) /*!< Bit mask of ATB field. */ + #define ETM_TRCEVENTCTL1R_ATB_Min (0x0UL) /*!< Min enumerator value of ATB field. */ + #define ETM_TRCEVENTCTL1R_ATB_Max (0x1UL) /*!< Max enumerator value of ATB field. */ + #define ETM_TRCEVENTCTL1R_ATB_Disabled (0x0UL) /*!< ATB trigger is disabled. */ + #define ETM_TRCEVENTCTL1R_ATB_Enabled (0x1UL) /*!< ATB trigger is enabled. If a CoreSight ATB interface is implemented + then when event 0 occurs the trace unit generates an ATB event.*/ + +/* LPOVERRIDE @Bit 12 : Low-power state behavior override bit. Controls how a trace unit behaves in low-power state. */ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos (12UL) /*!< Position of LPOVERRIDE field. */ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Msk (0x1UL << ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos) /*!< Bit mask of LPOVERRIDE field. */ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Min (0x0UL) /*!< Min enumerator value of LPOVERRIDE field. */ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Max (0x1UL) /*!< Max enumerator value of LPOVERRIDE field. */ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Disabled (0x0UL) /*!< Trace unit low-power state behavior is not affected. That is, the + trace unit is enabled to enter low-power state.*/ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Enabled (0x1UL) /*!< Trace unit low-power state behavior is overridden. That is, entry to + a low-power state does not affect the trace unit resources or trace + generation.*/ + + +/* ETM_TRCSTALLCTLR: Enables trace unit functionality that prevents trace unit buffer overflows. Might ignore writes when the + trace unit is enabled or not idle. Must be programmed if TRCIDR3.STALLCTL == 1. */ + + #define ETM_TRCSTALLCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCSTALLCTLR register. */ + +/* LEVEL @Bits 0..3 : Threshold level field. If LEVEL is nonzero then a trace unit might suppress the generation of: Global + timestamps in the instruction trace stream and the data trace stream. Cycle counting in the instruction + trace stream, although the cumulative cycle count remains correct. */ + + #define ETM_TRCSTALLCTLR_LEVEL_Pos (0UL) /*!< Position of LEVEL field. */ + #define ETM_TRCSTALLCTLR_LEVEL_Msk (0xFUL << ETM_TRCSTALLCTLR_LEVEL_Pos) /*!< Bit mask of LEVEL field. */ + #define ETM_TRCSTALLCTLR_LEVEL_Min (0x0UL) /*!< Zero invasion. This setting has a greater risk of a FIFO overflow */ + #define ETM_TRCSTALLCTLR_LEVEL_Max (0xFUL) /*!< Maximum invasion occurs but there is less risk of a FIFO overflow. */ + +/* ISTALL @Bit 8 : Instruction stall bit. Controls if a trace unit can stall the PE when the instruction trace buffer space is + less than LEVEL. */ + + #define ETM_TRCSTALLCTLR_ISTALL_Pos (8UL) /*!< Position of ISTALL field. */ + #define ETM_TRCSTALLCTLR_ISTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_ISTALL_Pos) /*!< Bit mask of ISTALL field. */ + #define ETM_TRCSTALLCTLR_ISTALL_Min (0x0UL) /*!< Min enumerator value of ISTALL field. */ + #define ETM_TRCSTALLCTLR_ISTALL_Max (0x1UL) /*!< Max enumerator value of ISTALL field. */ + #define ETM_TRCSTALLCTLR_ISTALL_Disabled (0x0UL) /*!< The trace unit must not stall the PE. */ + #define ETM_TRCSTALLCTLR_ISTALL_Enabled (0x1UL) /*!< The trace unit can stall the PE. */ + +/* DSTALL @Bit 9 : Data stall bit. Controls if a trace unit can stall the PE when the data trace buffer space is less than + LEVEL. */ + + #define ETM_TRCSTALLCTLR_DSTALL_Pos (9UL) /*!< Position of DSTALL field. */ + #define ETM_TRCSTALLCTLR_DSTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_DSTALL_Pos) /*!< Bit mask of DSTALL field. */ + #define ETM_TRCSTALLCTLR_DSTALL_Min (0x0UL) /*!< Min enumerator value of DSTALL field. */ + #define ETM_TRCSTALLCTLR_DSTALL_Max (0x1UL) /*!< Max enumerator value of DSTALL field. */ + #define ETM_TRCSTALLCTLR_DSTALL_Disabled (0x0UL) /*!< The trace unit must not stall the PE. */ + #define ETM_TRCSTALLCTLR_DSTALL_Enabled (0x1UL) /*!< The trace unit can stall the PE. */ + +/* INSTPRIORITY @Bit 10 : Prioritize instruction trace bit. Controls if a trace unit can prioritize instruction trace when the + instruction trace buffer space is less than LEVEL. */ + + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Pos (10UL) /*!< Position of INSTPRIORITY field. */ + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Msk (0x1UL << ETM_TRCSTALLCTLR_INSTPRIORITY_Pos) /*!< Bit mask of INSTPRIORITY field. */ + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Min (0x0UL) /*!< Min enumerator value of INSTPRIORITY field. */ + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Max (0x1UL) /*!< Max enumerator value of INSTPRIORITY field. */ + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Disabled (0x0UL) /*!< The trace unit must not prioritize instruction trace. */ + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Enabled (0x1UL) /*!< The trace unit can prioritize instruction trace. A trace unit might + prioritize instruction trace by preventing output of data trace, or + other means which ensure that the instruction trace has a higher + priority than the data trace.*/ + +/* DATADISCARDLOAD @Bit 11 : Data discard field. Controls if a trace unit can discard data trace elements on a load when the + data trace buffer space is less than LEVEL. */ + + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos (11UL) /*!< Position of DATADISCARDLOAD field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos) /*!< Bit mask of DATADISCARDLOAD + field.*/ + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Min (0x0UL) /*!< Min enumerator value of DATADISCARDLOAD field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Max (0x1UL) /*!< Max enumerator value of DATADISCARDLOAD field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements. */ + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with + data loads.*/ + +/* DATADISCARDSTORE @Bit 12 : Data discard field. Controls if a trace unit can discard data trace elements on a store when the + data trace buffer space is less than LEVEL. */ + + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos (12UL) /*!< Position of DATADISCARDSTORE field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos) /*!< Bit mask of + DATADISCARDSTORE field.*/ + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Min (0x0UL) /*!< Min enumerator value of DATADISCARDSTORE field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Max (0x1UL) /*!< Max enumerator value of DATADISCARDSTORE field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements. */ + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with + data stores.*/ + +/* NOOVERFLOW @Bit 13 : Trace overflow prevention bit. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Pos (13UL) /*!< Position of NOOVERFLOW field. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Msk (0x1UL << ETM_TRCSTALLCTLR_NOOVERFLOW_Pos) /*!< Bit mask of NOOVERFLOW field. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Min (0x0UL) /*!< Min enumerator value of NOOVERFLOW field. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Max (0x1UL) /*!< Max enumerator value of NOOVERFLOW field. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Disabled (0x0UL) /*!< Trace overflow prevention is disabled. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Enabled (0x1UL) /*!< Trace overflow prevention is enabled. This might cause a significant + performance impact.*/ + + +/* ETM_TRCTSCTLR: Controls the insertion of global timestamps in the trace streams. When the selected event is triggered, the + trace unit inserts a global timestamp into the trace streams. Might ignore writes when the trace unit is + enabled or not idle. Must be programmed if TRCCONFIGR.TS == 1. */ + + #define ETM_TRCTSCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCTSCTLR register. */ + +/* EVENT @Bits 0..7 : Select which event should generate time stamps. */ + #define ETM_TRCTSCTLR_EVENT_Pos (0UL) /*!< Position of EVENT field. */ + #define ETM_TRCTSCTLR_EVENT_Msk (0xFFUL << ETM_TRCTSCTLR_EVENT_Pos) /*!< Bit mask of EVENT field. */ + #define ETM_TRCTSCTLR_EVENT_Min (0x00UL) /*!< Min value of EVENT field. */ + #define ETM_TRCTSCTLR_EVENT_Max (0xFFUL) /*!< Max size of EVENT field. */ + + +/* ETM_TRCSYNCPR: Controls how often trace synchronization requests occur. Might ignore writes when the trace unit is enabled or + not idle. If writes are permitted then the register must be programmed. */ + + #define ETM_TRCSYNCPR_ResetValue (0x00000000UL) /*!< Reset value of TRCSYNCPR register. */ + +/* PERIOD @Bits 0..4 : Controls how many bytes of trace, the sum of instruction and data, that a trace unit can generate before + a trace synchronization request occurs. The number of bytes is always a power of two, calculated by + 2^PERIOD */ + + #define ETM_TRCSYNCPR_PERIOD_Pos (0UL) /*!< Position of PERIOD field. */ + #define ETM_TRCSYNCPR_PERIOD_Msk (0x1FUL << ETM_TRCSYNCPR_PERIOD_Pos) /*!< Bit mask of PERIOD field. */ + #define ETM_TRCSYNCPR_PERIOD_Min (0x00UL) /*!< Min value of PERIOD field. */ + #define ETM_TRCSYNCPR_PERIOD_Max (0x1FUL) /*!< Max size of PERIOD field. */ + #define ETM_TRCSYNCPR_PERIOD_Disabled (0x00UL) /*!< Trace synchronization requests are disabled. This setting does not + disable other types of trace synchronization request.*/ + + +/* ETM_TRCCCCTLR: Sets the threshold value for cycle counting. Might ignore writes when the trace unit is enabled or not idle. + Must be programmed if TRCCONFIGR.CCI==1. */ + + #define ETM_TRCCCCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCCCCTLR register. */ + +/* THRESHOLD @Bits 0..11 : Sets the threshold value for instruction trace cycle counting. */ + #define ETM_TRCCCCTLR_THRESHOLD_Pos (0UL) /*!< Position of THRESHOLD field. */ + #define ETM_TRCCCCTLR_THRESHOLD_Msk (0xFFFUL << ETM_TRCCCCTLR_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ + #define ETM_TRCCCCTLR_THRESHOLD_Min (0x000UL) /*!< Min value of THRESHOLD field. */ + #define ETM_TRCCCCTLR_THRESHOLD_Max (0x7FFUL) /*!< Max size of THRESHOLD field. */ + + +/* ETM_TRCBBCTLR: Controls which regions in the memory map are enabled to use branch broadcasting. Might ignore writes when the + trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.BB == 1. */ + + #define ETM_TRCBBCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCBBCTLR register. */ + +/* RANGE0 @Bit 0 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[0] controls the selection of address range + comparator pair 0. */ + + #define ETM_TRCBBCTLR_RANGE0_Pos (0UL) /*!< Position of RANGE0 field. */ + #define ETM_TRCBBCTLR_RANGE0_Msk (0x1UL << ETM_TRCBBCTLR_RANGE0_Pos) /*!< Bit mask of RANGE0 field. */ + #define ETM_TRCBBCTLR_RANGE0_Min (0x0UL) /*!< Min enumerator value of RANGE0 field. */ + #define ETM_TRCBBCTLR_RANGE0_Max (0x1UL) /*!< Max enumerator value of RANGE0 field. */ + #define ETM_TRCBBCTLR_RANGE0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE0_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE1 @Bit 1 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[1] controls the selection of address range + comparator pair 1. */ + + #define ETM_TRCBBCTLR_RANGE1_Pos (1UL) /*!< Position of RANGE1 field. */ + #define ETM_TRCBBCTLR_RANGE1_Msk (0x1UL << ETM_TRCBBCTLR_RANGE1_Pos) /*!< Bit mask of RANGE1 field. */ + #define ETM_TRCBBCTLR_RANGE1_Min (0x0UL) /*!< Min enumerator value of RANGE1 field. */ + #define ETM_TRCBBCTLR_RANGE1_Max (0x1UL) /*!< Max enumerator value of RANGE1 field. */ + #define ETM_TRCBBCTLR_RANGE1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE1_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE2 @Bit 2 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[2] controls the selection of address range + comparator pair 2. */ + + #define ETM_TRCBBCTLR_RANGE2_Pos (2UL) /*!< Position of RANGE2 field. */ + #define ETM_TRCBBCTLR_RANGE2_Msk (0x1UL << ETM_TRCBBCTLR_RANGE2_Pos) /*!< Bit mask of RANGE2 field. */ + #define ETM_TRCBBCTLR_RANGE2_Min (0x0UL) /*!< Min enumerator value of RANGE2 field. */ + #define ETM_TRCBBCTLR_RANGE2_Max (0x1UL) /*!< Max enumerator value of RANGE2 field. */ + #define ETM_TRCBBCTLR_RANGE2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE2_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE3 @Bit 3 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[3] controls the selection of address range + comparator pair 3. */ + + #define ETM_TRCBBCTLR_RANGE3_Pos (3UL) /*!< Position of RANGE3 field. */ + #define ETM_TRCBBCTLR_RANGE3_Msk (0x1UL << ETM_TRCBBCTLR_RANGE3_Pos) /*!< Bit mask of RANGE3 field. */ + #define ETM_TRCBBCTLR_RANGE3_Min (0x0UL) /*!< Min enumerator value of RANGE3 field. */ + #define ETM_TRCBBCTLR_RANGE3_Max (0x1UL) /*!< Max enumerator value of RANGE3 field. */ + #define ETM_TRCBBCTLR_RANGE3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE3_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE4 @Bit 4 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[4] controls the selection of address range + comparator pair 4. */ + + #define ETM_TRCBBCTLR_RANGE4_Pos (4UL) /*!< Position of RANGE4 field. */ + #define ETM_TRCBBCTLR_RANGE4_Msk (0x1UL << ETM_TRCBBCTLR_RANGE4_Pos) /*!< Bit mask of RANGE4 field. */ + #define ETM_TRCBBCTLR_RANGE4_Min (0x0UL) /*!< Min enumerator value of RANGE4 field. */ + #define ETM_TRCBBCTLR_RANGE4_Max (0x1UL) /*!< Max enumerator value of RANGE4 field. */ + #define ETM_TRCBBCTLR_RANGE4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE4_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE5 @Bit 5 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[5] controls the selection of address range + comparator pair 5. */ + + #define ETM_TRCBBCTLR_RANGE5_Pos (5UL) /*!< Position of RANGE5 field. */ + #define ETM_TRCBBCTLR_RANGE5_Msk (0x1UL << ETM_TRCBBCTLR_RANGE5_Pos) /*!< Bit mask of RANGE5 field. */ + #define ETM_TRCBBCTLR_RANGE5_Min (0x0UL) /*!< Min enumerator value of RANGE5 field. */ + #define ETM_TRCBBCTLR_RANGE5_Max (0x1UL) /*!< Max enumerator value of RANGE5 field. */ + #define ETM_TRCBBCTLR_RANGE5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE5_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE6 @Bit 6 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[6] controls the selection of address range + comparator pair 6. */ + + #define ETM_TRCBBCTLR_RANGE6_Pos (6UL) /*!< Position of RANGE6 field. */ + #define ETM_TRCBBCTLR_RANGE6_Msk (0x1UL << ETM_TRCBBCTLR_RANGE6_Pos) /*!< Bit mask of RANGE6 field. */ + #define ETM_TRCBBCTLR_RANGE6_Min (0x0UL) /*!< Min enumerator value of RANGE6 field. */ + #define ETM_TRCBBCTLR_RANGE6_Max (0x1UL) /*!< Max enumerator value of RANGE6 field. */ + #define ETM_TRCBBCTLR_RANGE6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE6_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE7 @Bit 7 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[7] controls the selection of address range + comparator pair 7. */ + + #define ETM_TRCBBCTLR_RANGE7_Pos (7UL) /*!< Position of RANGE7 field. */ + #define ETM_TRCBBCTLR_RANGE7_Msk (0x1UL << ETM_TRCBBCTLR_RANGE7_Pos) /*!< Bit mask of RANGE7 field. */ + #define ETM_TRCBBCTLR_RANGE7_Min (0x0UL) /*!< Min enumerator value of RANGE7 field. */ + #define ETM_TRCBBCTLR_RANGE7_Max (0x1UL) /*!< Max enumerator value of RANGE7 field. */ + #define ETM_TRCBBCTLR_RANGE7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE7_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + + +/* ETM_TRCTRACEIDR: Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data + trace, to (trace ID for instruction trace) + 1. This register must always be programmed as part of trace + unit initialization. Might ignore writes when the trace unit is enabled or not idle. */ + + #define ETM_TRCTRACEIDR_ResetValue (0x00000000UL) /*!< Reset value of TRCTRACEIDR register. */ + +/* TRACEID @Bits 0..6 : Trace ID field. Sets the trace ID value for instruction trace. Bit[0] must be zero if data trace is + enabled. If data trace is enabled then a trace unit sets the trace ID for data trace, to TRACEID+1. */ + + #define ETM_TRCTRACEIDR_TRACEID_Pos (0UL) /*!< Position of TRACEID field. */ + #define ETM_TRCTRACEIDR_TRACEID_Msk (0x7FUL << ETM_TRCTRACEIDR_TRACEID_Pos) /*!< Bit mask of TRACEID field. */ + + +/* ETM_TRCQCTLR: Controls when Q elements are enabled. Might ignore writes when the trace unit is enabled or not idle. This + register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00. */ + + #define ETM_TRCQCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCQCTLR register. */ + +/* RANGE0 @Bit 0 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE0_Pos (0UL) /*!< Position of RANGE0 field. */ + #define ETM_TRCQCTLR_RANGE0_Msk (0x1UL << ETM_TRCQCTLR_RANGE0_Pos) /*!< Bit mask of RANGE0 field. */ + #define ETM_TRCQCTLR_RANGE0_Min (0x0UL) /*!< Min enumerator value of RANGE0 field. */ + #define ETM_TRCQCTLR_RANGE0_Max (0x1UL) /*!< Max enumerator value of RANGE0 field. */ + #define ETM_TRCQCTLR_RANGE0_Disabled (0x0UL) /*!< Address range comparator 0 is disabled. */ + #define ETM_TRCQCTLR_RANGE0_Enabled (0x1UL) /*!< Address range comparator 0 is selected for use. */ + +/* RANGE1 @Bit 1 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE1_Pos (1UL) /*!< Position of RANGE1 field. */ + #define ETM_TRCQCTLR_RANGE1_Msk (0x1UL << ETM_TRCQCTLR_RANGE1_Pos) /*!< Bit mask of RANGE1 field. */ + #define ETM_TRCQCTLR_RANGE1_Min (0x0UL) /*!< Min enumerator value of RANGE1 field. */ + #define ETM_TRCQCTLR_RANGE1_Max (0x1UL) /*!< Max enumerator value of RANGE1 field. */ + #define ETM_TRCQCTLR_RANGE1_Disabled (0x0UL) /*!< Address range comparator 1 is disabled. */ + #define ETM_TRCQCTLR_RANGE1_Enabled (0x1UL) /*!< Address range comparator 1 is selected for use. */ + +/* RANGE2 @Bit 2 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE2_Pos (2UL) /*!< Position of RANGE2 field. */ + #define ETM_TRCQCTLR_RANGE2_Msk (0x1UL << ETM_TRCQCTLR_RANGE2_Pos) /*!< Bit mask of RANGE2 field. */ + #define ETM_TRCQCTLR_RANGE2_Min (0x0UL) /*!< Min enumerator value of RANGE2 field. */ + #define ETM_TRCQCTLR_RANGE2_Max (0x1UL) /*!< Max enumerator value of RANGE2 field. */ + #define ETM_TRCQCTLR_RANGE2_Disabled (0x0UL) /*!< Address range comparator 2 is disabled. */ + #define ETM_TRCQCTLR_RANGE2_Enabled (0x1UL) /*!< Address range comparator 2 is selected for use. */ + +/* RANGE3 @Bit 3 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE3_Pos (3UL) /*!< Position of RANGE3 field. */ + #define ETM_TRCQCTLR_RANGE3_Msk (0x1UL << ETM_TRCQCTLR_RANGE3_Pos) /*!< Bit mask of RANGE3 field. */ + #define ETM_TRCQCTLR_RANGE3_Min (0x0UL) /*!< Min enumerator value of RANGE3 field. */ + #define ETM_TRCQCTLR_RANGE3_Max (0x1UL) /*!< Max enumerator value of RANGE3 field. */ + #define ETM_TRCQCTLR_RANGE3_Disabled (0x0UL) /*!< Address range comparator 3 is disabled. */ + #define ETM_TRCQCTLR_RANGE3_Enabled (0x1UL) /*!< Address range comparator 3 is selected for use. */ + +/* RANGE4 @Bit 4 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE4_Pos (4UL) /*!< Position of RANGE4 field. */ + #define ETM_TRCQCTLR_RANGE4_Msk (0x1UL << ETM_TRCQCTLR_RANGE4_Pos) /*!< Bit mask of RANGE4 field. */ + #define ETM_TRCQCTLR_RANGE4_Min (0x0UL) /*!< Min enumerator value of RANGE4 field. */ + #define ETM_TRCQCTLR_RANGE4_Max (0x1UL) /*!< Max enumerator value of RANGE4 field. */ + #define ETM_TRCQCTLR_RANGE4_Disabled (0x0UL) /*!< Address range comparator 4 is disabled. */ + #define ETM_TRCQCTLR_RANGE4_Enabled (0x1UL) /*!< Address range comparator 4 is selected for use. */ + +/* RANGE5 @Bit 5 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE5_Pos (5UL) /*!< Position of RANGE5 field. */ + #define ETM_TRCQCTLR_RANGE5_Msk (0x1UL << ETM_TRCQCTLR_RANGE5_Pos) /*!< Bit mask of RANGE5 field. */ + #define ETM_TRCQCTLR_RANGE5_Min (0x0UL) /*!< Min enumerator value of RANGE5 field. */ + #define ETM_TRCQCTLR_RANGE5_Max (0x1UL) /*!< Max enumerator value of RANGE5 field. */ + #define ETM_TRCQCTLR_RANGE5_Disabled (0x0UL) /*!< Address range comparator 5 is disabled. */ + #define ETM_TRCQCTLR_RANGE5_Enabled (0x1UL) /*!< Address range comparator 5 is selected for use. */ + +/* RANGE6 @Bit 6 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE6_Pos (6UL) /*!< Position of RANGE6 field. */ + #define ETM_TRCQCTLR_RANGE6_Msk (0x1UL << ETM_TRCQCTLR_RANGE6_Pos) /*!< Bit mask of RANGE6 field. */ + #define ETM_TRCQCTLR_RANGE6_Min (0x0UL) /*!< Min enumerator value of RANGE6 field. */ + #define ETM_TRCQCTLR_RANGE6_Max (0x1UL) /*!< Max enumerator value of RANGE6 field. */ + #define ETM_TRCQCTLR_RANGE6_Disabled (0x0UL) /*!< Address range comparator 6 is disabled. */ + #define ETM_TRCQCTLR_RANGE6_Enabled (0x1UL) /*!< Address range comparator 6 is selected for use. */ + +/* RANGE7 @Bit 7 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE7_Pos (7UL) /*!< Position of RANGE7 field. */ + #define ETM_TRCQCTLR_RANGE7_Msk (0x1UL << ETM_TRCQCTLR_RANGE7_Pos) /*!< Bit mask of RANGE7 field. */ + #define ETM_TRCQCTLR_RANGE7_Min (0x0UL) /*!< Min enumerator value of RANGE7 field. */ + #define ETM_TRCQCTLR_RANGE7_Max (0x1UL) /*!< Max enumerator value of RANGE7 field. */ + #define ETM_TRCQCTLR_RANGE7_Disabled (0x0UL) /*!< Address range comparator 7 is disabled. */ + #define ETM_TRCQCTLR_RANGE7_Enabled (0x1UL) /*!< Address range comparator 7 is selected for use. */ + +/* MODE @Bit 8 : Selects whether the address range comparators selected by the RANGE field indicate address ranges where the + trace unit is permitted to generate Q elements or address ranges where the trace unit is not permitted to + generate Q elements: */ + + #define ETM_TRCQCTLR_MODE_Pos (8UL) /*!< Position of MODE field. */ + #define ETM_TRCQCTLR_MODE_Msk (0x1UL << ETM_TRCQCTLR_MODE_Pos) /*!< Bit mask of MODE field. */ + #define ETM_TRCQCTLR_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define ETM_TRCQCTLR_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define ETM_TRCQCTLR_MODE_Exclude (0x0UL) /*!< Exclude mode. The address range comparators selected by the RANGE + field indicate address ranges where the trace unit cannot generate Q + elements. If no ranges are selected, Q elements are permitted across + the entire memory map.*/ + #define ETM_TRCQCTLR_MODE_Include (0x1UL) /*!< Include mode. The address range comparators selected by the RANGE + field indicate address ranges where the trace unit can generate Q + elements. If all the implemented bits in RANGE are set to 0 then Q + elements are disabled.*/ + + +/* ETM_TRCVICTLR: Controls instruction trace filtering. Might ignore writes when the trace unit is enabled or not idle. Only + returns stable data when TRCSTATR.PMSTABLE == 1. Must be programmed, particularly to set the value of the + SSSTATUS bit, which sets the state of the start/stop logic. */ + + #define ETM_TRCVICTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVICTLR register. */ + +/* EVENT_SEL @Bits 0..4 : Select which resource number should be filtered. */ + #define ETM_TRCVICTLR_EVENT_SEL_Pos (0UL) /*!< Position of EVENT_SEL field. */ + #define ETM_TRCVICTLR_EVENT_SEL_Msk (0x1FUL << ETM_TRCVICTLR_EVENT_SEL_Pos) /*!< Bit mask of EVENT_SEL field. */ + #define ETM_TRCVICTLR_EVENT_SEL_Min (0x00UL) /*!< Min enumerator value of EVENT_SEL field. */ + #define ETM_TRCVICTLR_EVENT_SEL_Max (0x01UL) /*!< Max enumerator value of EVENT_SEL field. */ + #define ETM_TRCVICTLR_EVENT_SEL_Disabled (0x00UL) /*!< This event is not filtered. */ + #define ETM_TRCVICTLR_EVENT_SEL_Enabled (0x01UL) /*!< This event is filtered. */ + +/* SSSTATUS @Bit 9 : When TRCIDR4.NUMACPAIRS > 0 or TRCIDR4.NUMPC > 0, this bit returns the status of the start/stop logic. */ + #define ETM_TRCVICTLR_SSSTATUS_Pos (9UL) /*!< Position of SSSTATUS field. */ + #define ETM_TRCVICTLR_SSSTATUS_Msk (0x1UL << ETM_TRCVICTLR_SSSTATUS_Pos) /*!< Bit mask of SSSTATUS field. */ + #define ETM_TRCVICTLR_SSSTATUS_Min (0x0UL) /*!< Min enumerator value of SSSTATUS field. */ + #define ETM_TRCVICTLR_SSSTATUS_Max (0x1UL) /*!< Max enumerator value of SSSTATUS field. */ + #define ETM_TRCVICTLR_SSSTATUS_Stopped (0x0UL) /*!< The start/stop logic is in the stopped state. */ + #define ETM_TRCVICTLR_SSSTATUS_Started (0x1UL) /*!< The start/stop logic is in the started state. */ + +/* TRCRESET @Bit 10 : Controls whether a trace unit must trace a Reset exception. */ + #define ETM_TRCVICTLR_TRCRESET_Pos (10UL) /*!< Position of TRCRESET field. */ + #define ETM_TRCVICTLR_TRCRESET_Msk (0x1UL << ETM_TRCVICTLR_TRCRESET_Pos) /*!< Bit mask of TRCRESET field. */ + #define ETM_TRCVICTLR_TRCRESET_Min (0x0UL) /*!< Min enumerator value of TRCRESET field. */ + #define ETM_TRCVICTLR_TRCRESET_Max (0x1UL) /*!< Max enumerator value of TRCRESET field. */ + #define ETM_TRCVICTLR_TRCRESET_Disabled (0x0UL) /*!< The trace unit does not trace a Reset exception unless it traces the + exception or instruction immediately prior to the Reset exception.*/ + #define ETM_TRCVICTLR_TRCRESET_Enabled (0x1UL) /*!< The trace unit always traces a Reset exception. */ + +/* TRCERR @Bit 11 : When TRCIDR3.TRCERR==1, this bit controls whether a trace unit must trace a System error exception. */ + #define ETM_TRCVICTLR_TRCERR_Pos (11UL) /*!< Position of TRCERR field. */ + #define ETM_TRCVICTLR_TRCERR_Msk (0x1UL << ETM_TRCVICTLR_TRCERR_Pos) /*!< Bit mask of TRCERR field. */ + #define ETM_TRCVICTLR_TRCERR_Min (0x0UL) /*!< Min enumerator value of TRCERR field. */ + #define ETM_TRCVICTLR_TRCERR_Max (0x1UL) /*!< Max enumerator value of TRCERR field. */ + #define ETM_TRCVICTLR_TRCERR_Disabled (0x0UL) /*!< The trace unit does not trace a System error exception unless it + traces the exception or instruction immediately prior to the System + error exception.*/ + #define ETM_TRCVICTLR_TRCERR_Enabled (0x1UL) /*!< The trace unit always traces a System error exception, regardless of + the value of ViewInst.*/ + +/* EXLEVEL0_S @Bit 16 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 0. */ + + #define ETM_TRCVICTLR_EXLEVEL0_S_Pos (16UL) /*!< Position of EXLEVEL0_S field. */ + #define ETM_TRCVICTLR_EXLEVEL0_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_S_Pos) /*!< Bit mask of EXLEVEL0_S field. */ + #define ETM_TRCVICTLR_EXLEVEL0_S_Min (0x0UL) /*!< Min enumerator value of EXLEVEL0_S field. */ + #define ETM_TRCVICTLR_EXLEVEL0_S_Max (0x1UL) /*!< Max enumerator value of EXLEVEL0_S field. */ + #define ETM_TRCVICTLR_EXLEVEL0_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, + for Exception level 0.*/ + #define ETM_TRCVICTLR_EXLEVEL0_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for + Exception level 0.*/ + +/* EXLEVEL1_S @Bit 17 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 1. */ + + #define ETM_TRCVICTLR_EXLEVEL1_S_Pos (17UL) /*!< Position of EXLEVEL1_S field. */ + #define ETM_TRCVICTLR_EXLEVEL1_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_S_Pos) /*!< Bit mask of EXLEVEL1_S field. */ + #define ETM_TRCVICTLR_EXLEVEL1_S_Min (0x0UL) /*!< Min enumerator value of EXLEVEL1_S field. */ + #define ETM_TRCVICTLR_EXLEVEL1_S_Max (0x1UL) /*!< Max enumerator value of EXLEVEL1_S field. */ + #define ETM_TRCVICTLR_EXLEVEL1_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, + for Exception level 1.*/ + #define ETM_TRCVICTLR_EXLEVEL1_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for + Exception level 1.*/ + +/* EXLEVEL2_S @Bit 18 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 2. */ + + #define ETM_TRCVICTLR_EXLEVEL2_S_Pos (18UL) /*!< Position of EXLEVEL2_S field. */ + #define ETM_TRCVICTLR_EXLEVEL2_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_S_Pos) /*!< Bit mask of EXLEVEL2_S field. */ + #define ETM_TRCVICTLR_EXLEVEL2_S_Min (0x0UL) /*!< Min enumerator value of EXLEVEL2_S field. */ + #define ETM_TRCVICTLR_EXLEVEL2_S_Max (0x1UL) /*!< Max enumerator value of EXLEVEL2_S field. */ + #define ETM_TRCVICTLR_EXLEVEL2_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, + for Exception level 2.*/ + #define ETM_TRCVICTLR_EXLEVEL2_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for + Exception level 2.*/ + +/* EXLEVEL3_S @Bit 19 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 3. */ + + #define ETM_TRCVICTLR_EXLEVEL3_S_Pos (19UL) /*!< Position of EXLEVEL3_S field. */ + #define ETM_TRCVICTLR_EXLEVEL3_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_S_Pos) /*!< Bit mask of EXLEVEL3_S field. */ + #define ETM_TRCVICTLR_EXLEVEL3_S_Min (0x0UL) /*!< Min enumerator value of EXLEVEL3_S field. */ + #define ETM_TRCVICTLR_EXLEVEL3_S_Max (0x1UL) /*!< Max enumerator value of EXLEVEL3_S field. */ + #define ETM_TRCVICTLR_EXLEVEL3_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, + for Exception level 3.*/ + #define ETM_TRCVICTLR_EXLEVEL3_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for + Exception level 3.*/ + +/* EXLEVEL0_NS @Bit 20 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 0. */ + + #define ETM_TRCVICTLR_EXLEVEL0_NS_Pos (20UL) /*!< Position of EXLEVEL0_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL0_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_NS_Pos) /*!< Bit mask of EXLEVEL0_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL0_NS_Min (0x0UL) /*!< Min enumerator value of EXLEVEL0_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL0_NS_Max (0x1UL) /*!< Max enumerator value of EXLEVEL0_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL0_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure + state, for Exception level 0.*/ + #define ETM_TRCVICTLR_EXLEVEL0_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for + Exception level 0.*/ + +/* EXLEVEL1_NS @Bit 21 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 1. */ + + #define ETM_TRCVICTLR_EXLEVEL1_NS_Pos (21UL) /*!< Position of EXLEVEL1_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL1_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_NS_Pos) /*!< Bit mask of EXLEVEL1_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL1_NS_Min (0x0UL) /*!< Min enumerator value of EXLEVEL1_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL1_NS_Max (0x1UL) /*!< Max enumerator value of EXLEVEL1_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL1_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure + state, for Exception level 1.*/ + #define ETM_TRCVICTLR_EXLEVEL1_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for + Exception level 1.*/ + +/* EXLEVEL2_NS @Bit 22 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 2. */ + + #define ETM_TRCVICTLR_EXLEVEL2_NS_Pos (22UL) /*!< Position of EXLEVEL2_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL2_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_NS_Pos) /*!< Bit mask of EXLEVEL2_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL2_NS_Min (0x0UL) /*!< Min enumerator value of EXLEVEL2_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL2_NS_Max (0x1UL) /*!< Max enumerator value of EXLEVEL2_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL2_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure + state, for Exception level 2.*/ + #define ETM_TRCVICTLR_EXLEVEL2_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for + Exception level 2.*/ + +/* EXLEVEL3_NS @Bit 23 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 3. */ + + #define ETM_TRCVICTLR_EXLEVEL3_NS_Pos (23UL) /*!< Position of EXLEVEL3_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL3_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_NS_Pos) /*!< Bit mask of EXLEVEL3_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL3_NS_Min (0x0UL) /*!< Min enumerator value of EXLEVEL3_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL3_NS_Max (0x1UL) /*!< Max enumerator value of EXLEVEL3_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL3_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure + state, for Exception level 3.*/ + #define ETM_TRCVICTLR_EXLEVEL3_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for + Exception level 3.*/ + + +/* ETM_TRCVIIECTLR: ViewInst exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must + be programmed when one or more address comparators are implemented. */ + + #define ETM_TRCVIIECTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVIIECTLR register. */ + +/* INCLUDE0 @Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE0_Pos (0UL) /*!< Position of INCLUDE0 field. */ + #define ETM_TRCVIIECTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field. */ + #define ETM_TRCVIIECTLR_INCLUDE0_Min (0x0UL) /*!< Min enumerator value of INCLUDE0 field. */ + #define ETM_TRCVIIECTLR_INCLUDE0_Max (0x1UL) /*!< Max enumerator value of INCLUDE0 field. */ + #define ETM_TRCVIIECTLR_INCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE0_Enabled (0x1UL) /*!< The address range that address range comparator pair 0 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE1 @Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE1_Pos (1UL) /*!< Position of INCLUDE1 field. */ + #define ETM_TRCVIIECTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field. */ + #define ETM_TRCVIIECTLR_INCLUDE1_Min (0x0UL) /*!< Min enumerator value of INCLUDE1 field. */ + #define ETM_TRCVIIECTLR_INCLUDE1_Max (0x1UL) /*!< Max enumerator value of INCLUDE1 field. */ + #define ETM_TRCVIIECTLR_INCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE1_Enabled (0x1UL) /*!< The address range that address range comparator pair 1 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE2 @Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE2_Pos (2UL) /*!< Position of INCLUDE2 field. */ + #define ETM_TRCVIIECTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field. */ + #define ETM_TRCVIIECTLR_INCLUDE2_Min (0x0UL) /*!< Min enumerator value of INCLUDE2 field. */ + #define ETM_TRCVIIECTLR_INCLUDE2_Max (0x1UL) /*!< Max enumerator value of INCLUDE2 field. */ + #define ETM_TRCVIIECTLR_INCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE2_Enabled (0x1UL) /*!< The address range that address range comparator pair 2 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE3 @Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE3_Pos (3UL) /*!< Position of INCLUDE3 field. */ + #define ETM_TRCVIIECTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field. */ + #define ETM_TRCVIIECTLR_INCLUDE3_Min (0x0UL) /*!< Min enumerator value of INCLUDE3 field. */ + #define ETM_TRCVIIECTLR_INCLUDE3_Max (0x1UL) /*!< Max enumerator value of INCLUDE3 field. */ + #define ETM_TRCVIIECTLR_INCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE3_Enabled (0x1UL) /*!< The address range that address range comparator pair 3 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE4 @Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE4_Pos (4UL) /*!< Position of INCLUDE4 field. */ + #define ETM_TRCVIIECTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field. */ + #define ETM_TRCVIIECTLR_INCLUDE4_Min (0x0UL) /*!< Min enumerator value of INCLUDE4 field. */ + #define ETM_TRCVIIECTLR_INCLUDE4_Max (0x1UL) /*!< Max enumerator value of INCLUDE4 field. */ + #define ETM_TRCVIIECTLR_INCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE4_Enabled (0x1UL) /*!< The address range that address range comparator pair 4 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE5 @Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE5_Pos (5UL) /*!< Position of INCLUDE5 field. */ + #define ETM_TRCVIIECTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field. */ + #define ETM_TRCVIIECTLR_INCLUDE5_Min (0x0UL) /*!< Min enumerator value of INCLUDE5 field. */ + #define ETM_TRCVIIECTLR_INCLUDE5_Max (0x1UL) /*!< Max enumerator value of INCLUDE5 field. */ + #define ETM_TRCVIIECTLR_INCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE5_Enabled (0x1UL) /*!< The address range that address range comparator pair 5 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE6 @Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE6_Pos (6UL) /*!< Position of INCLUDE6 field. */ + #define ETM_TRCVIIECTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field. */ + #define ETM_TRCVIIECTLR_INCLUDE6_Min (0x0UL) /*!< Min enumerator value of INCLUDE6 field. */ + #define ETM_TRCVIIECTLR_INCLUDE6_Max (0x1UL) /*!< Max enumerator value of INCLUDE6 field. */ + #define ETM_TRCVIIECTLR_INCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE6_Enabled (0x1UL) /*!< The address range that address range comparator pair 6 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE7 @Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE7_Pos (7UL) /*!< Position of INCLUDE7 field. */ + #define ETM_TRCVIIECTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field. */ + #define ETM_TRCVIIECTLR_INCLUDE7_Min (0x0UL) /*!< Min enumerator value of INCLUDE7 field. */ + #define ETM_TRCVIIECTLR_INCLUDE7_Max (0x1UL) /*!< Max enumerator value of INCLUDE7 field. */ + #define ETM_TRCVIIECTLR_INCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE7_Enabled (0x1UL) /*!< The address range that address range comparator pair 7 defines, is + selected for ViewInst include control.*/ + +/* EXCLUDE0 @Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE0_Pos (16UL) /*!< Position of EXCLUDE0 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE0_Min (0x0UL) /*!< Min enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE0_Max (0x1UL) /*!< Max enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE0_Enabled (0x1UL) /*!< The address range that address range comparator pair 0 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE1 @Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE1_Pos (17UL) /*!< Position of EXCLUDE1 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE1_Min (0x0UL) /*!< Min enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE1_Max (0x1UL) /*!< Max enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE1_Enabled (0x1UL) /*!< The address range that address range comparator pair 1 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE2 @Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE2_Pos (18UL) /*!< Position of EXCLUDE2 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE2_Min (0x0UL) /*!< Min enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE2_Max (0x1UL) /*!< Max enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE2_Enabled (0x1UL) /*!< The address range that address range comparator pair 2 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE3 @Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE3_Pos (19UL) /*!< Position of EXCLUDE3 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE3_Min (0x0UL) /*!< Min enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE3_Max (0x1UL) /*!< Max enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE3_Enabled (0x1UL) /*!< The address range that address range comparator pair 3 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE4 @Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE4_Pos (20UL) /*!< Position of EXCLUDE4 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE4_Min (0x0UL) /*!< Min enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE4_Max (0x1UL) /*!< Max enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE4_Enabled (0x1UL) /*!< The address range that address range comparator pair 4 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE5 @Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE5_Pos (21UL) /*!< Position of EXCLUDE5 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE5_Min (0x0UL) /*!< Min enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE5_Max (0x1UL) /*!< Max enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE5_Enabled (0x1UL) /*!< The address range that address range comparator pair 5 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE6 @Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE6_Pos (22UL) /*!< Position of EXCLUDE6 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE6_Min (0x0UL) /*!< Min enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE6_Max (0x1UL) /*!< Max enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE6_Enabled (0x1UL) /*!< The address range that address range comparator pair 6 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE7 @Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE7_Pos (23UL) /*!< Position of EXCLUDE7 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE7_Min (0x0UL) /*!< Min enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE7_Max (0x1UL) /*!< Max enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE7_Enabled (0x1UL) /*!< The address range that address range comparator pair 7 defines, is + selected for ViewInst exclude control.*/ + + +/* ETM_TRCVISSCTLR: Use this to set, or read, the single address comparators that control the ViewInst start/stop logic. The + start/stop logic is active for an instruction which causes a start and remains active up to and including + an instruction which causes a stop, and then the start/stop logic becomes inactive. Might ignore writes + when the trace unit is enabled or not idle. If implemented then this register must be programmed. */ + + #define ETM_TRCVISSCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVISSCTLR register. */ + +/* START0 @Bit 0 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START0_Pos (0UL) /*!< Position of START0 field. */ + #define ETM_TRCVISSCTLR_START0_Msk (0x1UL << ETM_TRCVISSCTLR_START0_Pos) /*!< Bit mask of START0 field. */ + #define ETM_TRCVISSCTLR_START0_Min (0x0UL) /*!< Min enumerator value of START0 field. */ + #define ETM_TRCVISSCTLR_START0_Max (0x1UL) /*!< Max enumerator value of START0 field. */ + #define ETM_TRCVISSCTLR_START0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START0_Enabled (0x1UL) /*!< The single address comparator 0, is selected as a start resource. */ + +/* START1 @Bit 1 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START1_Pos (1UL) /*!< Position of START1 field. */ + #define ETM_TRCVISSCTLR_START1_Msk (0x1UL << ETM_TRCVISSCTLR_START1_Pos) /*!< Bit mask of START1 field. */ + #define ETM_TRCVISSCTLR_START1_Min (0x0UL) /*!< Min enumerator value of START1 field. */ + #define ETM_TRCVISSCTLR_START1_Max (0x1UL) /*!< Max enumerator value of START1 field. */ + #define ETM_TRCVISSCTLR_START1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START1_Enabled (0x1UL) /*!< The single address comparator 1, is selected as a start resource. */ + +/* START2 @Bit 2 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START2_Pos (2UL) /*!< Position of START2 field. */ + #define ETM_TRCVISSCTLR_START2_Msk (0x1UL << ETM_TRCVISSCTLR_START2_Pos) /*!< Bit mask of START2 field. */ + #define ETM_TRCVISSCTLR_START2_Min (0x0UL) /*!< Min enumerator value of START2 field. */ + #define ETM_TRCVISSCTLR_START2_Max (0x1UL) /*!< Max enumerator value of START2 field. */ + #define ETM_TRCVISSCTLR_START2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START2_Enabled (0x1UL) /*!< The single address comparator 2, is selected as a start resource. */ + +/* START3 @Bit 3 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START3_Pos (3UL) /*!< Position of START3 field. */ + #define ETM_TRCVISSCTLR_START3_Msk (0x1UL << ETM_TRCVISSCTLR_START3_Pos) /*!< Bit mask of START3 field. */ + #define ETM_TRCVISSCTLR_START3_Min (0x0UL) /*!< Min enumerator value of START3 field. */ + #define ETM_TRCVISSCTLR_START3_Max (0x1UL) /*!< Max enumerator value of START3 field. */ + #define ETM_TRCVISSCTLR_START3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START3_Enabled (0x1UL) /*!< The single address comparator 3, is selected as a start resource. */ + +/* START4 @Bit 4 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START4_Pos (4UL) /*!< Position of START4 field. */ + #define ETM_TRCVISSCTLR_START4_Msk (0x1UL << ETM_TRCVISSCTLR_START4_Pos) /*!< Bit mask of START4 field. */ + #define ETM_TRCVISSCTLR_START4_Min (0x0UL) /*!< Min enumerator value of START4 field. */ + #define ETM_TRCVISSCTLR_START4_Max (0x1UL) /*!< Max enumerator value of START4 field. */ + #define ETM_TRCVISSCTLR_START4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START4_Enabled (0x1UL) /*!< The single address comparator 4, is selected as a start resource. */ + +/* START5 @Bit 5 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START5_Pos (5UL) /*!< Position of START5 field. */ + #define ETM_TRCVISSCTLR_START5_Msk (0x1UL << ETM_TRCVISSCTLR_START5_Pos) /*!< Bit mask of START5 field. */ + #define ETM_TRCVISSCTLR_START5_Min (0x0UL) /*!< Min enumerator value of START5 field. */ + #define ETM_TRCVISSCTLR_START5_Max (0x1UL) /*!< Max enumerator value of START5 field. */ + #define ETM_TRCVISSCTLR_START5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START5_Enabled (0x1UL) /*!< The single address comparator 5, is selected as a start resource. */ + +/* START6 @Bit 6 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START6_Pos (6UL) /*!< Position of START6 field. */ + #define ETM_TRCVISSCTLR_START6_Msk (0x1UL << ETM_TRCVISSCTLR_START6_Pos) /*!< Bit mask of START6 field. */ + #define ETM_TRCVISSCTLR_START6_Min (0x0UL) /*!< Min enumerator value of START6 field. */ + #define ETM_TRCVISSCTLR_START6_Max (0x1UL) /*!< Max enumerator value of START6 field. */ + #define ETM_TRCVISSCTLR_START6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START6_Enabled (0x1UL) /*!< The single address comparator 6, is selected as a start resource. */ + +/* START7 @Bit 7 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START7_Pos (7UL) /*!< Position of START7 field. */ + #define ETM_TRCVISSCTLR_START7_Msk (0x1UL << ETM_TRCVISSCTLR_START7_Pos) /*!< Bit mask of START7 field. */ + #define ETM_TRCVISSCTLR_START7_Min (0x0UL) /*!< Min enumerator value of START7 field. */ + #define ETM_TRCVISSCTLR_START7_Max (0x1UL) /*!< Max enumerator value of START7 field. */ + #define ETM_TRCVISSCTLR_START7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START7_Enabled (0x1UL) /*!< The single address comparator 7, is selected as a start resource. */ + +/* STOP0 @Bit 16 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP0_Pos (16UL) /*!< Position of STOP0 field. */ + #define ETM_TRCVISSCTLR_STOP0_Msk (0x1UL << ETM_TRCVISSCTLR_STOP0_Pos) /*!< Bit mask of STOP0 field. */ + #define ETM_TRCVISSCTLR_STOP0_Min (0x0UL) /*!< Min enumerator value of STOP0 field. */ + #define ETM_TRCVISSCTLR_STOP0_Max (0x1UL) /*!< Max enumerator value of STOP0 field. */ + #define ETM_TRCVISSCTLR_STOP0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP0_Enabled (0x1UL) /*!< The single address comparator 0, is selected as a stop resource. */ + +/* STOP1 @Bit 17 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP1_Pos (17UL) /*!< Position of STOP1 field. */ + #define ETM_TRCVISSCTLR_STOP1_Msk (0x1UL << ETM_TRCVISSCTLR_STOP1_Pos) /*!< Bit mask of STOP1 field. */ + #define ETM_TRCVISSCTLR_STOP1_Min (0x0UL) /*!< Min enumerator value of STOP1 field. */ + #define ETM_TRCVISSCTLR_STOP1_Max (0x1UL) /*!< Max enumerator value of STOP1 field. */ + #define ETM_TRCVISSCTLR_STOP1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP1_Enabled (0x1UL) /*!< The single address comparator 1, is selected as a stop resource. */ + +/* STOP2 @Bit 18 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP2_Pos (18UL) /*!< Position of STOP2 field. */ + #define ETM_TRCVISSCTLR_STOP2_Msk (0x1UL << ETM_TRCVISSCTLR_STOP2_Pos) /*!< Bit mask of STOP2 field. */ + #define ETM_TRCVISSCTLR_STOP2_Min (0x0UL) /*!< Min enumerator value of STOP2 field. */ + #define ETM_TRCVISSCTLR_STOP2_Max (0x1UL) /*!< Max enumerator value of STOP2 field. */ + #define ETM_TRCVISSCTLR_STOP2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP2_Enabled (0x1UL) /*!< The single address comparator 2, is selected as a stop resource. */ + +/* STOP3 @Bit 19 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP3_Pos (19UL) /*!< Position of STOP3 field. */ + #define ETM_TRCVISSCTLR_STOP3_Msk (0x1UL << ETM_TRCVISSCTLR_STOP3_Pos) /*!< Bit mask of STOP3 field. */ + #define ETM_TRCVISSCTLR_STOP3_Min (0x0UL) /*!< Min enumerator value of STOP3 field. */ + #define ETM_TRCVISSCTLR_STOP3_Max (0x1UL) /*!< Max enumerator value of STOP3 field. */ + #define ETM_TRCVISSCTLR_STOP3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP3_Enabled (0x1UL) /*!< The single address comparator 3, is selected as a stop resource. */ + +/* STOP4 @Bit 20 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP4_Pos (20UL) /*!< Position of STOP4 field. */ + #define ETM_TRCVISSCTLR_STOP4_Msk (0x1UL << ETM_TRCVISSCTLR_STOP4_Pos) /*!< Bit mask of STOP4 field. */ + #define ETM_TRCVISSCTLR_STOP4_Min (0x0UL) /*!< Min enumerator value of STOP4 field. */ + #define ETM_TRCVISSCTLR_STOP4_Max (0x1UL) /*!< Max enumerator value of STOP4 field. */ + #define ETM_TRCVISSCTLR_STOP4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP4_Enabled (0x1UL) /*!< The single address comparator 4, is selected as a stop resource. */ + +/* STOP5 @Bit 21 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP5_Pos (21UL) /*!< Position of STOP5 field. */ + #define ETM_TRCVISSCTLR_STOP5_Msk (0x1UL << ETM_TRCVISSCTLR_STOP5_Pos) /*!< Bit mask of STOP5 field. */ + #define ETM_TRCVISSCTLR_STOP5_Min (0x0UL) /*!< Min enumerator value of STOP5 field. */ + #define ETM_TRCVISSCTLR_STOP5_Max (0x1UL) /*!< Max enumerator value of STOP5 field. */ + #define ETM_TRCVISSCTLR_STOP5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP5_Enabled (0x1UL) /*!< The single address comparator 5, is selected as a stop resource. */ + +/* STOP6 @Bit 22 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP6_Pos (22UL) /*!< Position of STOP6 field. */ + #define ETM_TRCVISSCTLR_STOP6_Msk (0x1UL << ETM_TRCVISSCTLR_STOP6_Pos) /*!< Bit mask of STOP6 field. */ + #define ETM_TRCVISSCTLR_STOP6_Min (0x0UL) /*!< Min enumerator value of STOP6 field. */ + #define ETM_TRCVISSCTLR_STOP6_Max (0x1UL) /*!< Max enumerator value of STOP6 field. */ + #define ETM_TRCVISSCTLR_STOP6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP6_Enabled (0x1UL) /*!< The single address comparator 6, is selected as a stop resource. */ + +/* STOP7 @Bit 23 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP7_Pos (23UL) /*!< Position of STOP7 field. */ + #define ETM_TRCVISSCTLR_STOP7_Msk (0x1UL << ETM_TRCVISSCTLR_STOP7_Pos) /*!< Bit mask of STOP7 field. */ + #define ETM_TRCVISSCTLR_STOP7_Min (0x0UL) /*!< Min enumerator value of STOP7 field. */ + #define ETM_TRCVISSCTLR_STOP7_Max (0x1UL) /*!< Max enumerator value of STOP7 field. */ + #define ETM_TRCVISSCTLR_STOP7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP7_Enabled (0x1UL) /*!< The single address comparator 7, is selected as a stop resource. */ + + +/* ETM_TRCVIPCSSCTLR: Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic. Might + ignore writes when the trace unit is enabled or not idle. If implemented then this register must be + programmed. */ + + #define ETM_TRCVIPCSSCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVIPCSSCTLR register. */ + +/* START0 @Bit 0 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START0_Pos (0UL) /*!< Position of START0 field. */ + #define ETM_TRCVIPCSSCTLR_START0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START0_Pos) /*!< Bit mask of START0 field. */ + #define ETM_TRCVIPCSSCTLR_START0_Min (0x0UL) /*!< Min enumerator value of START0 field. */ + #define ETM_TRCVIPCSSCTLR_START0_Max (0x1UL) /*!< Max enumerator value of START0 field. */ + #define ETM_TRCVIPCSSCTLR_START0_Disabled (0x0UL) /*!< The single PE comparator input 0, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START0_Enabled (0x1UL) /*!< The single PE comparator input 0, is selected as a start resource. */ + +/* START1 @Bit 1 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START1_Pos (1UL) /*!< Position of START1 field. */ + #define ETM_TRCVIPCSSCTLR_START1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START1_Pos) /*!< Bit mask of START1 field. */ + #define ETM_TRCVIPCSSCTLR_START1_Min (0x0UL) /*!< Min enumerator value of START1 field. */ + #define ETM_TRCVIPCSSCTLR_START1_Max (0x1UL) /*!< Max enumerator value of START1 field. */ + #define ETM_TRCVIPCSSCTLR_START1_Disabled (0x0UL) /*!< The single PE comparator input 1, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START1_Enabled (0x1UL) /*!< The single PE comparator input 1, is selected as a start resource. */ + +/* START2 @Bit 2 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START2_Pos (2UL) /*!< Position of START2 field. */ + #define ETM_TRCVIPCSSCTLR_START2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START2_Pos) /*!< Bit mask of START2 field. */ + #define ETM_TRCVIPCSSCTLR_START2_Min (0x0UL) /*!< Min enumerator value of START2 field. */ + #define ETM_TRCVIPCSSCTLR_START2_Max (0x1UL) /*!< Max enumerator value of START2 field. */ + #define ETM_TRCVIPCSSCTLR_START2_Disabled (0x0UL) /*!< The single PE comparator input 2, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START2_Enabled (0x1UL) /*!< The single PE comparator input 2, is selected as a start resource. */ + +/* START3 @Bit 3 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START3_Pos (3UL) /*!< Position of START3 field. */ + #define ETM_TRCVIPCSSCTLR_START3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START3_Pos) /*!< Bit mask of START3 field. */ + #define ETM_TRCVIPCSSCTLR_START3_Min (0x0UL) /*!< Min enumerator value of START3 field. */ + #define ETM_TRCVIPCSSCTLR_START3_Max (0x1UL) /*!< Max enumerator value of START3 field. */ + #define ETM_TRCVIPCSSCTLR_START3_Disabled (0x0UL) /*!< The single PE comparator input 3, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START3_Enabled (0x1UL) /*!< The single PE comparator input 3, is selected as a start resource. */ + +/* START4 @Bit 4 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START4_Pos (4UL) /*!< Position of START4 field. */ + #define ETM_TRCVIPCSSCTLR_START4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START4_Pos) /*!< Bit mask of START4 field. */ + #define ETM_TRCVIPCSSCTLR_START4_Min (0x0UL) /*!< Min enumerator value of START4 field. */ + #define ETM_TRCVIPCSSCTLR_START4_Max (0x1UL) /*!< Max enumerator value of START4 field. */ + #define ETM_TRCVIPCSSCTLR_START4_Disabled (0x0UL) /*!< The single PE comparator input 4, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START4_Enabled (0x1UL) /*!< The single PE comparator input 4, is selected as a start resource. */ + +/* START5 @Bit 5 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START5_Pos (5UL) /*!< Position of START5 field. */ + #define ETM_TRCVIPCSSCTLR_START5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START5_Pos) /*!< Bit mask of START5 field. */ + #define ETM_TRCVIPCSSCTLR_START5_Min (0x0UL) /*!< Min enumerator value of START5 field. */ + #define ETM_TRCVIPCSSCTLR_START5_Max (0x1UL) /*!< Max enumerator value of START5 field. */ + #define ETM_TRCVIPCSSCTLR_START5_Disabled (0x0UL) /*!< The single PE comparator input 5, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START5_Enabled (0x1UL) /*!< The single PE comparator input 5, is selected as a start resource. */ + +/* START6 @Bit 6 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START6_Pos (6UL) /*!< Position of START6 field. */ + #define ETM_TRCVIPCSSCTLR_START6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START6_Pos) /*!< Bit mask of START6 field. */ + #define ETM_TRCVIPCSSCTLR_START6_Min (0x0UL) /*!< Min enumerator value of START6 field. */ + #define ETM_TRCVIPCSSCTLR_START6_Max (0x1UL) /*!< Max enumerator value of START6 field. */ + #define ETM_TRCVIPCSSCTLR_START6_Disabled (0x0UL) /*!< The single PE comparator input 6, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START6_Enabled (0x1UL) /*!< The single PE comparator input 6, is selected as a start resource. */ + +/* START7 @Bit 7 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START7_Pos (7UL) /*!< Position of START7 field. */ + #define ETM_TRCVIPCSSCTLR_START7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START7_Pos) /*!< Bit mask of START7 field. */ + #define ETM_TRCVIPCSSCTLR_START7_Min (0x0UL) /*!< Min enumerator value of START7 field. */ + #define ETM_TRCVIPCSSCTLR_START7_Max (0x1UL) /*!< Max enumerator value of START7 field. */ + #define ETM_TRCVIPCSSCTLR_START7_Disabled (0x0UL) /*!< The single PE comparator input 7, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START7_Enabled (0x1UL) /*!< The single PE comparator input 7, is selected as a start resource. */ + +/* STOP0 @Bit 16 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP0_Pos (16UL) /*!< Position of STOP0 field. */ + #define ETM_TRCVIPCSSCTLR_STOP0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP0_Pos) /*!< Bit mask of STOP0 field. */ + #define ETM_TRCVIPCSSCTLR_STOP0_Min (0x0UL) /*!< Min enumerator value of STOP0 field. */ + #define ETM_TRCVIPCSSCTLR_STOP0_Max (0x1UL) /*!< Max enumerator value of STOP0 field. */ + #define ETM_TRCVIPCSSCTLR_STOP0_Disabled (0x0UL) /*!< The single PE comparator input 0, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP0_Enabled (0x1UL) /*!< The single PE comparator input 0, is selected as a stop resource. */ + +/* STOP1 @Bit 17 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP1_Pos (17UL) /*!< Position of STOP1 field. */ + #define ETM_TRCVIPCSSCTLR_STOP1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP1_Pos) /*!< Bit mask of STOP1 field. */ + #define ETM_TRCVIPCSSCTLR_STOP1_Min (0x0UL) /*!< Min enumerator value of STOP1 field. */ + #define ETM_TRCVIPCSSCTLR_STOP1_Max (0x1UL) /*!< Max enumerator value of STOP1 field. */ + #define ETM_TRCVIPCSSCTLR_STOP1_Disabled (0x0UL) /*!< The single PE comparator input 1, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP1_Enabled (0x1UL) /*!< The single PE comparator input 1, is selected as a stop resource. */ + +/* STOP2 @Bit 18 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP2_Pos (18UL) /*!< Position of STOP2 field. */ + #define ETM_TRCVIPCSSCTLR_STOP2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP2_Pos) /*!< Bit mask of STOP2 field. */ + #define ETM_TRCVIPCSSCTLR_STOP2_Min (0x0UL) /*!< Min enumerator value of STOP2 field. */ + #define ETM_TRCVIPCSSCTLR_STOP2_Max (0x1UL) /*!< Max enumerator value of STOP2 field. */ + #define ETM_TRCVIPCSSCTLR_STOP2_Disabled (0x0UL) /*!< The single PE comparator input 2, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP2_Enabled (0x1UL) /*!< The single PE comparator input 2, is selected as a stop resource. */ + +/* STOP3 @Bit 19 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP3_Pos (19UL) /*!< Position of STOP3 field. */ + #define ETM_TRCVIPCSSCTLR_STOP3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP3_Pos) /*!< Bit mask of STOP3 field. */ + #define ETM_TRCVIPCSSCTLR_STOP3_Min (0x0UL) /*!< Min enumerator value of STOP3 field. */ + #define ETM_TRCVIPCSSCTLR_STOP3_Max (0x1UL) /*!< Max enumerator value of STOP3 field. */ + #define ETM_TRCVIPCSSCTLR_STOP3_Disabled (0x0UL) /*!< The single PE comparator input 3, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP3_Enabled (0x1UL) /*!< The single PE comparator input 3, is selected as a stop resource. */ + +/* STOP4 @Bit 20 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP4_Pos (20UL) /*!< Position of STOP4 field. */ + #define ETM_TRCVIPCSSCTLR_STOP4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP4_Pos) /*!< Bit mask of STOP4 field. */ + #define ETM_TRCVIPCSSCTLR_STOP4_Min (0x0UL) /*!< Min enumerator value of STOP4 field. */ + #define ETM_TRCVIPCSSCTLR_STOP4_Max (0x1UL) /*!< Max enumerator value of STOP4 field. */ + #define ETM_TRCVIPCSSCTLR_STOP4_Disabled (0x0UL) /*!< The single PE comparator input 4, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP4_Enabled (0x1UL) /*!< The single PE comparator input 4, is selected as a stop resource. */ + +/* STOP5 @Bit 21 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP5_Pos (21UL) /*!< Position of STOP5 field. */ + #define ETM_TRCVIPCSSCTLR_STOP5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP5_Pos) /*!< Bit mask of STOP5 field. */ + #define ETM_TRCVIPCSSCTLR_STOP5_Min (0x0UL) /*!< Min enumerator value of STOP5 field. */ + #define ETM_TRCVIPCSSCTLR_STOP5_Max (0x1UL) /*!< Max enumerator value of STOP5 field. */ + #define ETM_TRCVIPCSSCTLR_STOP5_Disabled (0x0UL) /*!< The single PE comparator input 5, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP5_Enabled (0x1UL) /*!< The single PE comparator input 5, is selected as a stop resource. */ + +/* STOP6 @Bit 22 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP6_Pos (22UL) /*!< Position of STOP6 field. */ + #define ETM_TRCVIPCSSCTLR_STOP6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP6_Pos) /*!< Bit mask of STOP6 field. */ + #define ETM_TRCVIPCSSCTLR_STOP6_Min (0x0UL) /*!< Min enumerator value of STOP6 field. */ + #define ETM_TRCVIPCSSCTLR_STOP6_Max (0x1UL) /*!< Max enumerator value of STOP6 field. */ + #define ETM_TRCVIPCSSCTLR_STOP6_Disabled (0x0UL) /*!< The single PE comparator input 6, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP6_Enabled (0x1UL) /*!< The single PE comparator input 6, is selected as a stop resource. */ + +/* STOP7 @Bit 23 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP7_Pos (23UL) /*!< Position of STOP7 field. */ + #define ETM_TRCVIPCSSCTLR_STOP7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP7_Pos) /*!< Bit mask of STOP7 field. */ + #define ETM_TRCVIPCSSCTLR_STOP7_Min (0x0UL) /*!< Min enumerator value of STOP7 field. */ + #define ETM_TRCVIPCSSCTLR_STOP7_Max (0x1UL) /*!< Max enumerator value of STOP7 field. */ + #define ETM_TRCVIPCSSCTLR_STOP7_Disabled (0x0UL) /*!< The single PE comparator input 7, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP7_Enabled (0x1UL) /*!< The single PE comparator input 7, is selected as a stop resource. */ + + +/* ETM_TRCVDCTLR: Controls data trace filtering. Might ignore writes when the trace unit is enabled or not idle. This register + must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == + 1. */ + + #define ETM_TRCVDCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVDCTLR register. */ + +/* EVENT0 @Bit 0 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT0_Pos (0UL) /*!< Position of EVENT0 field. */ + #define ETM_TRCVDCTLR_EVENT0_Msk (0x1UL << ETM_TRCVDCTLR_EVENT0_Pos) /*!< Bit mask of EVENT0 field. */ + #define ETM_TRCVDCTLR_EVENT0_Min (0x0UL) /*!< Min enumerator value of EVENT0 field. */ + #define ETM_TRCVDCTLR_EVENT0_Max (0x1UL) /*!< Max enumerator value of EVENT0 field. */ + #define ETM_TRCVDCTLR_EVENT0_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT0_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT1 @Bit 1 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT1_Pos (1UL) /*!< Position of EVENT1 field. */ + #define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field. */ + #define ETM_TRCVDCTLR_EVENT1_Min (0x0UL) /*!< Min enumerator value of EVENT1 field. */ + #define ETM_TRCVDCTLR_EVENT1_Max (0x1UL) /*!< Max enumerator value of EVENT1 field. */ + #define ETM_TRCVDCTLR_EVENT1_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT1_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT2 @Bit 2 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT2_Pos (2UL) /*!< Position of EVENT2 field. */ + #define ETM_TRCVDCTLR_EVENT2_Msk (0x1UL << ETM_TRCVDCTLR_EVENT2_Pos) /*!< Bit mask of EVENT2 field. */ + #define ETM_TRCVDCTLR_EVENT2_Min (0x0UL) /*!< Min enumerator value of EVENT2 field. */ + #define ETM_TRCVDCTLR_EVENT2_Max (0x1UL) /*!< Max enumerator value of EVENT2 field. */ + #define ETM_TRCVDCTLR_EVENT2_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT2_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT3 @Bit 3 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT3_Pos (3UL) /*!< Position of EVENT3 field. */ + #define ETM_TRCVDCTLR_EVENT3_Msk (0x1UL << ETM_TRCVDCTLR_EVENT3_Pos) /*!< Bit mask of EVENT3 field. */ + #define ETM_TRCVDCTLR_EVENT3_Min (0x0UL) /*!< Min enumerator value of EVENT3 field. */ + #define ETM_TRCVDCTLR_EVENT3_Max (0x1UL) /*!< Max enumerator value of EVENT3 field. */ + #define ETM_TRCVDCTLR_EVENT3_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT3_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT4 @Bit 4 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT4_Pos (4UL) /*!< Position of EVENT4 field. */ + #define ETM_TRCVDCTLR_EVENT4_Msk (0x1UL << ETM_TRCVDCTLR_EVENT4_Pos) /*!< Bit mask of EVENT4 field. */ + #define ETM_TRCVDCTLR_EVENT4_Min (0x0UL) /*!< Min enumerator value of EVENT4 field. */ + #define ETM_TRCVDCTLR_EVENT4_Max (0x1UL) /*!< Max enumerator value of EVENT4 field. */ + #define ETM_TRCVDCTLR_EVENT4_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT4_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT5 @Bit 5 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT5_Pos (5UL) /*!< Position of EVENT5 field. */ + #define ETM_TRCVDCTLR_EVENT5_Msk (0x1UL << ETM_TRCVDCTLR_EVENT5_Pos) /*!< Bit mask of EVENT5 field. */ + #define ETM_TRCVDCTLR_EVENT5_Min (0x0UL) /*!< Min enumerator value of EVENT5 field. */ + #define ETM_TRCVDCTLR_EVENT5_Max (0x1UL) /*!< Max enumerator value of EVENT5 field. */ + #define ETM_TRCVDCTLR_EVENT5_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT5_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT6 @Bit 6 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT6_Pos (6UL) /*!< Position of EVENT6 field. */ + #define ETM_TRCVDCTLR_EVENT6_Msk (0x1UL << ETM_TRCVDCTLR_EVENT6_Pos) /*!< Bit mask of EVENT6 field. */ + #define ETM_TRCVDCTLR_EVENT6_Min (0x0UL) /*!< Min enumerator value of EVENT6 field. */ + #define ETM_TRCVDCTLR_EVENT6_Max (0x1UL) /*!< Max enumerator value of EVENT6 field. */ + #define ETM_TRCVDCTLR_EVENT6_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT6_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT7 @Bit 7 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT7_Pos (7UL) /*!< Position of EVENT7 field. */ + #define ETM_TRCVDCTLR_EVENT7_Msk (0x1UL << ETM_TRCVDCTLR_EVENT7_Pos) /*!< Bit mask of EVENT7 field. */ + #define ETM_TRCVDCTLR_EVENT7_Min (0x0UL) /*!< Min enumerator value of EVENT7 field. */ + #define ETM_TRCVDCTLR_EVENT7_Max (0x1UL) /*!< Max enumerator value of EVENT7 field. */ + #define ETM_TRCVDCTLR_EVENT7_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT7_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* SPREL @Bits 8..9 : Controls whether a trace unit traces data for transfers that are relative to the Stack Pointer (SP). */ + #define ETM_TRCVDCTLR_SPREL_Pos (8UL) /*!< Position of SPREL field. */ + #define ETM_TRCVDCTLR_SPREL_Msk (0x3UL << ETM_TRCVDCTLR_SPREL_Pos) /*!< Bit mask of SPREL field. */ + #define ETM_TRCVDCTLR_SPREL_Min (0x0UL) /*!< Min enumerator value of SPREL field. */ + #define ETM_TRCVDCTLR_SPREL_Max (0x3UL) /*!< Max enumerator value of SPREL field. */ + #define ETM_TRCVDCTLR_SPREL_Enabled (0x0UL) /*!< The trace unit does not affect the tracing of SP-relative transfers. */ + #define ETM_TRCVDCTLR_SPREL_DataOnly (0x2UL) /*!< The trace unit does not trace the address portion of SP-relative + transfers. If data value tracing is enabled then the trace unit + generates a P1 data address element.*/ + #define ETM_TRCVDCTLR_SPREL_Disabled (0x3UL) /*!< The trace unit does not trace the address or value portions of + SP-relative transfers.*/ + +/* PCREL @Bit 10 : Controls whether a trace unit traces data for transfers that are relative to the Program Counter (PC). */ + #define ETM_TRCVDCTLR_PCREL_Pos (10UL) /*!< Position of PCREL field. */ + #define ETM_TRCVDCTLR_PCREL_Msk (0x1UL << ETM_TRCVDCTLR_PCREL_Pos) /*!< Bit mask of PCREL field. */ + #define ETM_TRCVDCTLR_PCREL_Min (0x0UL) /*!< Min enumerator value of PCREL field. */ + #define ETM_TRCVDCTLR_PCREL_Max (0x1UL) /*!< Max enumerator value of PCREL field. */ + #define ETM_TRCVDCTLR_PCREL_Enabled (0x0UL) /*!< The trace unit does not affect the tracing of PC-relative transfers. */ + #define ETM_TRCVDCTLR_PCREL_Disabled (0x1UL) /*!< The trace unit does not trace the address or value portions of + PC-relative transfers.*/ + +/* TBI @Bit 11 : Controls which information a trace unit populates in bits[63:56] of the data address. */ + #define ETM_TRCVDCTLR_TBI_Pos (11UL) /*!< Position of TBI field. */ + #define ETM_TRCVDCTLR_TBI_Msk (0x1UL << ETM_TRCVDCTLR_TBI_Pos) /*!< Bit mask of TBI field. */ + #define ETM_TRCVDCTLR_TBI_Min (0x0UL) /*!< Min enumerator value of TBI field. */ + #define ETM_TRCVDCTLR_TBI_Max (0x1UL) /*!< Max enumerator value of TBI field. */ + #define ETM_TRCVDCTLR_TBI_SignExtend (0x0UL) /*!< The trace unit assigns bits[63:56] to have the same value as bit[55] + of the data address, that is, it sign-extends the value.*/ + #define ETM_TRCVDCTLR_TBI_Copy (0x1UL) /*!< The trace unit assigns bits[63:56] to have the same value as + bits[63:56] of the data address.*/ + +/* TRCEXDATA @Bit 12 : Controls the tracing of data transfers for exceptions and exception returns on Armv6-M, Armv7-M, and + Armv8-M PEs. */ + + #define ETM_TRCVDCTLR_TRCEXDATA_Pos (12UL) /*!< Position of TRCEXDATA field. */ + #define ETM_TRCVDCTLR_TRCEXDATA_Msk (0x1UL << ETM_TRCVDCTLR_TRCEXDATA_Pos) /*!< Bit mask of TRCEXDATA field. */ + #define ETM_TRCVDCTLR_TRCEXDATA_Min (0x0UL) /*!< Min enumerator value of TRCEXDATA field. */ + #define ETM_TRCVDCTLR_TRCEXDATA_Max (0x1UL) /*!< Max enumerator value of TRCEXDATA field. */ + #define ETM_TRCVDCTLR_TRCEXDATA_Disabled (0x0UL) /*!< Exception and exception return data transfers are not traced. */ + #define ETM_TRCVDCTLR_TRCEXDATA_Enabled (0x1UL) /*!< Exception and exception return data transfers are traced if the other + aspects of ViewData indicate that the data transfers must be traced.*/ + + +/* ETM_TRCVDSACCTLR: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This + register must be programmed when one or more address comparators are implemented. */ + + #define ETM_TRCVDSACCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVDSACCTLR register. */ + +/* INCLUDE0 @Bit 0 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE0_Pos (0UL) /*!< Position of INCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE0_Min (0x0UL) /*!< Min enumerator value of INCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE0_Max (0x1UL) /*!< Max enumerator value of INCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE0_Enabled (0x1UL) /*!< The single address comparator 0, is selected for ViewData include + control.*/ + +/* INCLUDE1 @Bit 1 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE1_Pos (1UL) /*!< Position of INCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE1_Min (0x0UL) /*!< Min enumerator value of INCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE1_Max (0x1UL) /*!< Max enumerator value of INCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE1_Enabled (0x1UL) /*!< The single address comparator 1, is selected for ViewData include + control.*/ + +/* INCLUDE2 @Bit 2 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE2_Pos (2UL) /*!< Position of INCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE2_Min (0x0UL) /*!< Min enumerator value of INCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE2_Max (0x1UL) /*!< Max enumerator value of INCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE2_Enabled (0x1UL) /*!< The single address comparator 2, is selected for ViewData include + control.*/ + +/* INCLUDE3 @Bit 3 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE3_Pos (3UL) /*!< Position of INCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE3_Min (0x0UL) /*!< Min enumerator value of INCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE3_Max (0x1UL) /*!< Max enumerator value of INCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE3_Enabled (0x1UL) /*!< The single address comparator 3, is selected for ViewData include + control.*/ + +/* INCLUDE4 @Bit 4 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE4_Pos (4UL) /*!< Position of INCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE4_Min (0x0UL) /*!< Min enumerator value of INCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE4_Max (0x1UL) /*!< Max enumerator value of INCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE4_Enabled (0x1UL) /*!< The single address comparator 4, is selected for ViewData include + control.*/ + +/* INCLUDE5 @Bit 5 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE5_Pos (5UL) /*!< Position of INCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE5_Min (0x0UL) /*!< Min enumerator value of INCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE5_Max (0x1UL) /*!< Max enumerator value of INCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE5_Enabled (0x1UL) /*!< The single address comparator 5, is selected for ViewData include + control.*/ + +/* INCLUDE6 @Bit 6 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE6_Pos (6UL) /*!< Position of INCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE6_Min (0x0UL) /*!< Min enumerator value of INCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE6_Max (0x1UL) /*!< Max enumerator value of INCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE6_Enabled (0x1UL) /*!< The single address comparator 6, is selected for ViewData include + control.*/ + +/* INCLUDE7 @Bit 7 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE7_Pos (7UL) /*!< Position of INCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE7_Min (0x0UL) /*!< Min enumerator value of INCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE7_Max (0x1UL) /*!< Max enumerator value of INCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE7_Enabled (0x1UL) /*!< The single address comparator 7, is selected for ViewData include + control.*/ + +/* EXCLUDE0 @Bit 16 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Pos (16UL) /*!< Position of EXCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Min (0x0UL) /*!< Min enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Max (0x1UL) /*!< Max enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Enabled (0x1UL) /*!< The single address comparator 0, s selected for ViewData exclude + control.*/ + +/* EXCLUDE1 @Bit 17 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Pos (17UL) /*!< Position of EXCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Min (0x0UL) /*!< Min enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Max (0x1UL) /*!< Max enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Enabled (0x1UL) /*!< The single address comparator 1, s selected for ViewData exclude + control.*/ + +/* EXCLUDE2 @Bit 18 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Pos (18UL) /*!< Position of EXCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Min (0x0UL) /*!< Min enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Max (0x1UL) /*!< Max enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Enabled (0x1UL) /*!< The single address comparator 2, s selected for ViewData exclude + control.*/ + +/* EXCLUDE3 @Bit 19 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Pos (19UL) /*!< Position of EXCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Min (0x0UL) /*!< Min enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Max (0x1UL) /*!< Max enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Enabled (0x1UL) /*!< The single address comparator 3, s selected for ViewData exclude + control.*/ + +/* EXCLUDE4 @Bit 20 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Pos (20UL) /*!< Position of EXCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Min (0x0UL) /*!< Min enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Max (0x1UL) /*!< Max enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Enabled (0x1UL) /*!< The single address comparator 4, s selected for ViewData exclude + control.*/ + +/* EXCLUDE5 @Bit 21 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Pos (21UL) /*!< Position of EXCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Min (0x0UL) /*!< Min enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Max (0x1UL) /*!< Max enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Enabled (0x1UL) /*!< The single address comparator 5, s selected for ViewData exclude + control.*/ + +/* EXCLUDE6 @Bit 22 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Pos (22UL) /*!< Position of EXCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Min (0x0UL) /*!< Min enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Max (0x1UL) /*!< Max enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Enabled (0x1UL) /*!< The single address comparator 6, s selected for ViewData exclude + control.*/ + +/* EXCLUDE7 @Bit 23 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Pos (23UL) /*!< Position of EXCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Min (0x0UL) /*!< Min enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Max (0x1UL) /*!< Max enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Enabled (0x1UL) /*!< The single address comparator 7, s selected for ViewData exclude + control.*/ + + +/* ETM_TRCVDARCCTLR: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This + register must be programmed when one or more address comparators are implemented. */ + + #define ETM_TRCVDARCCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVDARCCTLR register. */ + +/* INCLUDE0 @Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE0_Pos (0UL) /*!< Position of INCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE0_Min (0x0UL) /*!< Min enumerator value of INCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE0_Max (0x1UL) /*!< Max enumerator value of INCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE0_Enabled (0x1UL) /*!< The address range that address range comparator 0 defines, is selected + for ViewData include control.*/ + +/* INCLUDE1 @Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE1_Pos (1UL) /*!< Position of INCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE1_Min (0x0UL) /*!< Min enumerator value of INCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE1_Max (0x1UL) /*!< Max enumerator value of INCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE1_Enabled (0x1UL) /*!< The address range that address range comparator 1 defines, is selected + for ViewData include control.*/ + +/* INCLUDE2 @Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE2_Pos (2UL) /*!< Position of INCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE2_Min (0x0UL) /*!< Min enumerator value of INCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE2_Max (0x1UL) /*!< Max enumerator value of INCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE2_Enabled (0x1UL) /*!< The address range that address range comparator 2 defines, is selected + for ViewData include control.*/ + +/* INCLUDE3 @Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE3_Pos (3UL) /*!< Position of INCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE3_Min (0x0UL) /*!< Min enumerator value of INCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE3_Max (0x1UL) /*!< Max enumerator value of INCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE3_Enabled (0x1UL) /*!< The address range that address range comparator 3 defines, is selected + for ViewData include control.*/ + +/* INCLUDE4 @Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE4_Pos (4UL) /*!< Position of INCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE4_Min (0x0UL) /*!< Min enumerator value of INCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE4_Max (0x1UL) /*!< Max enumerator value of INCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE4_Enabled (0x1UL) /*!< The address range that address range comparator 4 defines, is selected + for ViewData include control.*/ + +/* INCLUDE5 @Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE5_Pos (5UL) /*!< Position of INCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE5_Min (0x0UL) /*!< Min enumerator value of INCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE5_Max (0x1UL) /*!< Max enumerator value of INCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE5_Enabled (0x1UL) /*!< The address range that address range comparator 5 defines, is selected + for ViewData include control.*/ + +/* INCLUDE6 @Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE6_Pos (6UL) /*!< Position of INCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE6_Min (0x0UL) /*!< Min enumerator value of INCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE6_Max (0x1UL) /*!< Max enumerator value of INCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE6_Enabled (0x1UL) /*!< The address range that address range comparator 6 defines, is selected + for ViewData include control.*/ + +/* INCLUDE7 @Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE7_Pos (7UL) /*!< Position of INCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE7_Min (0x0UL) /*!< Min enumerator value of INCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE7_Max (0x1UL) /*!< Max enumerator value of INCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE7_Enabled (0x1UL) /*!< The address range that address range comparator 7 defines, is selected + for ViewData include control.*/ + +/* EXCLUDE0 @Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE0_Pos (16UL) /*!< Position of EXCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE0_Min (0x0UL) /*!< Min enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE0_Max (0x1UL) /*!< Max enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE0_Enabled (0x1UL) /*!< The address range that address range comparator 0 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE1 @Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE1_Pos (17UL) /*!< Position of EXCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE1_Min (0x0UL) /*!< Min enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE1_Max (0x1UL) /*!< Max enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE1_Enabled (0x1UL) /*!< The address range that address range comparator 1 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE2 @Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE2_Pos (18UL) /*!< Position of EXCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE2_Min (0x0UL) /*!< Min enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE2_Max (0x1UL) /*!< Max enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE2_Enabled (0x1UL) /*!< The address range that address range comparator 2 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE3 @Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE3_Pos (19UL) /*!< Position of EXCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE3_Min (0x0UL) /*!< Min enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE3_Max (0x1UL) /*!< Max enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE3_Enabled (0x1UL) /*!< The address range that address range comparator 3 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE4 @Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE4_Pos (20UL) /*!< Position of EXCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE4_Min (0x0UL) /*!< Min enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE4_Max (0x1UL) /*!< Max enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE4_Enabled (0x1UL) /*!< The address range that address range comparator 4 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE5 @Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE5_Pos (21UL) /*!< Position of EXCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE5_Min (0x0UL) /*!< Min enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE5_Max (0x1UL) /*!< Max enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE5_Enabled (0x1UL) /*!< The address range that address range comparator 5 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE6 @Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE6_Pos (22UL) /*!< Position of EXCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE6_Min (0x0UL) /*!< Min enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE6_Max (0x1UL) /*!< Max enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE6_Enabled (0x1UL) /*!< The address range that address range comparator 6 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE7 @Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE7_Pos (23UL) /*!< Position of EXCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE7_Min (0x0UL) /*!< Min enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE7_Max (0x1UL) /*!< Max enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE7_Enabled (0x1UL) /*!< The address range that address range comparator 7 defines, s selected + for ViewData exclude control.*/ + + +/* ETM_TRCSEQEVR: Moves the sequencer state according to programmed events. Might ignore writes when the trace unit is enabled + or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid + event. */ + + #define ETM_TRCSEQEVR_MaxCount (3UL) /*!< Max size of TRCSEQEVR[3] array. */ + #define ETM_TRCSEQEVR_MaxIndex (2UL) /*!< Max index of TRCSEQEVR[3] array. */ + #define ETM_TRCSEQEVR_MinIndex (0UL) /*!< Min index of TRCSEQEVR[3] array. */ + #define ETM_TRCSEQEVR_ResetValue (0x00000000UL) /*!< Reset value of TRCSEQEVR[3] register. */ + +/* F0 @Bit 0 : Forward field. */ + #define ETM_TRCSEQEVR_F0_Pos (0UL) /*!< Position of F0 field. */ + #define ETM_TRCSEQEVR_F0_Msk (0x1UL << ETM_TRCSEQEVR_F0_Pos) /*!< Bit mask of F0 field. */ + #define ETM_TRCSEQEVR_F0_Min (0x0UL) /*!< Min enumerator value of F0 field. */ + #define ETM_TRCSEQEVR_F0_Max (0x1UL) /*!< Max enumerator value of F0 field. */ + #define ETM_TRCSEQEVR_F0_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F0_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F1 @Bit 1 : Forward field. */ + #define ETM_TRCSEQEVR_F1_Pos (1UL) /*!< Position of F1 field. */ + #define ETM_TRCSEQEVR_F1_Msk (0x1UL << ETM_TRCSEQEVR_F1_Pos) /*!< Bit mask of F1 field. */ + #define ETM_TRCSEQEVR_F1_Min (0x0UL) /*!< Min enumerator value of F1 field. */ + #define ETM_TRCSEQEVR_F1_Max (0x1UL) /*!< Max enumerator value of F1 field. */ + #define ETM_TRCSEQEVR_F1_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F1_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F2 @Bit 2 : Forward field. */ + #define ETM_TRCSEQEVR_F2_Pos (2UL) /*!< Position of F2 field. */ + #define ETM_TRCSEQEVR_F2_Msk (0x1UL << ETM_TRCSEQEVR_F2_Pos) /*!< Bit mask of F2 field. */ + #define ETM_TRCSEQEVR_F2_Min (0x0UL) /*!< Min enumerator value of F2 field. */ + #define ETM_TRCSEQEVR_F2_Max (0x1UL) /*!< Max enumerator value of F2 field. */ + #define ETM_TRCSEQEVR_F2_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F2_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F3 @Bit 3 : Forward field. */ + #define ETM_TRCSEQEVR_F3_Pos (3UL) /*!< Position of F3 field. */ + #define ETM_TRCSEQEVR_F3_Msk (0x1UL << ETM_TRCSEQEVR_F3_Pos) /*!< Bit mask of F3 field. */ + #define ETM_TRCSEQEVR_F3_Min (0x0UL) /*!< Min enumerator value of F3 field. */ + #define ETM_TRCSEQEVR_F3_Max (0x1UL) /*!< Max enumerator value of F3 field. */ + #define ETM_TRCSEQEVR_F3_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F3_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F4 @Bit 4 : Forward field. */ + #define ETM_TRCSEQEVR_F4_Pos (4UL) /*!< Position of F4 field. */ + #define ETM_TRCSEQEVR_F4_Msk (0x1UL << ETM_TRCSEQEVR_F4_Pos) /*!< Bit mask of F4 field. */ + #define ETM_TRCSEQEVR_F4_Min (0x0UL) /*!< Min enumerator value of F4 field. */ + #define ETM_TRCSEQEVR_F4_Max (0x1UL) /*!< Max enumerator value of F4 field. */ + #define ETM_TRCSEQEVR_F4_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F4_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F5 @Bit 5 : Forward field. */ + #define ETM_TRCSEQEVR_F5_Pos (5UL) /*!< Position of F5 field. */ + #define ETM_TRCSEQEVR_F5_Msk (0x1UL << ETM_TRCSEQEVR_F5_Pos) /*!< Bit mask of F5 field. */ + #define ETM_TRCSEQEVR_F5_Min (0x0UL) /*!< Min enumerator value of F5 field. */ + #define ETM_TRCSEQEVR_F5_Max (0x1UL) /*!< Max enumerator value of F5 field. */ + #define ETM_TRCSEQEVR_F5_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F5_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F6 @Bit 6 : Forward field. */ + #define ETM_TRCSEQEVR_F6_Pos (6UL) /*!< Position of F6 field. */ + #define ETM_TRCSEQEVR_F6_Msk (0x1UL << ETM_TRCSEQEVR_F6_Pos) /*!< Bit mask of F6 field. */ + #define ETM_TRCSEQEVR_F6_Min (0x0UL) /*!< Min enumerator value of F6 field. */ + #define ETM_TRCSEQEVR_F6_Max (0x1UL) /*!< Max enumerator value of F6 field. */ + #define ETM_TRCSEQEVR_F6_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F6_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F7 @Bit 7 : Forward field. */ + #define ETM_TRCSEQEVR_F7_Pos (7UL) /*!< Position of F7 field. */ + #define ETM_TRCSEQEVR_F7_Msk (0x1UL << ETM_TRCSEQEVR_F7_Pos) /*!< Bit mask of F7 field. */ + #define ETM_TRCSEQEVR_F7_Min (0x0UL) /*!< Min enumerator value of F7 field. */ + #define ETM_TRCSEQEVR_F7_Max (0x1UL) /*!< Max enumerator value of F7 field. */ + #define ETM_TRCSEQEVR_F7_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F7_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* B0 @Bit 8 : Backward field. */ + #define ETM_TRCSEQEVR_B0_Pos (8UL) /*!< Position of B0 field. */ + #define ETM_TRCSEQEVR_B0_Msk (0x1UL << ETM_TRCSEQEVR_B0_Pos) /*!< Bit mask of B0 field. */ + #define ETM_TRCSEQEVR_B0_Min (0x0UL) /*!< Min enumerator value of B0 field. */ + #define ETM_TRCSEQEVR_B0_Max (0x1UL) /*!< Max enumerator value of B0 field. */ + #define ETM_TRCSEQEVR_B0_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B0_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B1 @Bit 9 : Backward field. */ + #define ETM_TRCSEQEVR_B1_Pos (9UL) /*!< Position of B1 field. */ + #define ETM_TRCSEQEVR_B1_Msk (0x1UL << ETM_TRCSEQEVR_B1_Pos) /*!< Bit mask of B1 field. */ + #define ETM_TRCSEQEVR_B1_Min (0x0UL) /*!< Min enumerator value of B1 field. */ + #define ETM_TRCSEQEVR_B1_Max (0x1UL) /*!< Max enumerator value of B1 field. */ + #define ETM_TRCSEQEVR_B1_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B1_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B2 @Bit 10 : Backward field. */ + #define ETM_TRCSEQEVR_B2_Pos (10UL) /*!< Position of B2 field. */ + #define ETM_TRCSEQEVR_B2_Msk (0x1UL << ETM_TRCSEQEVR_B2_Pos) /*!< Bit mask of B2 field. */ + #define ETM_TRCSEQEVR_B2_Min (0x0UL) /*!< Min enumerator value of B2 field. */ + #define ETM_TRCSEQEVR_B2_Max (0x1UL) /*!< Max enumerator value of B2 field. */ + #define ETM_TRCSEQEVR_B2_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B2_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B3 @Bit 11 : Backward field. */ + #define ETM_TRCSEQEVR_B3_Pos (11UL) /*!< Position of B3 field. */ + #define ETM_TRCSEQEVR_B3_Msk (0x1UL << ETM_TRCSEQEVR_B3_Pos) /*!< Bit mask of B3 field. */ + #define ETM_TRCSEQEVR_B3_Min (0x0UL) /*!< Min enumerator value of B3 field. */ + #define ETM_TRCSEQEVR_B3_Max (0x1UL) /*!< Max enumerator value of B3 field. */ + #define ETM_TRCSEQEVR_B3_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B3_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B4 @Bit 12 : Backward field. */ + #define ETM_TRCSEQEVR_B4_Pos (12UL) /*!< Position of B4 field. */ + #define ETM_TRCSEQEVR_B4_Msk (0x1UL << ETM_TRCSEQEVR_B4_Pos) /*!< Bit mask of B4 field. */ + #define ETM_TRCSEQEVR_B4_Min (0x0UL) /*!< Min enumerator value of B4 field. */ + #define ETM_TRCSEQEVR_B4_Max (0x1UL) /*!< Max enumerator value of B4 field. */ + #define ETM_TRCSEQEVR_B4_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B4_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B5 @Bit 13 : Backward field. */ + #define ETM_TRCSEQEVR_B5_Pos (13UL) /*!< Position of B5 field. */ + #define ETM_TRCSEQEVR_B5_Msk (0x1UL << ETM_TRCSEQEVR_B5_Pos) /*!< Bit mask of B5 field. */ + #define ETM_TRCSEQEVR_B5_Min (0x0UL) /*!< Min enumerator value of B5 field. */ + #define ETM_TRCSEQEVR_B5_Max (0x1UL) /*!< Max enumerator value of B5 field. */ + #define ETM_TRCSEQEVR_B5_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B5_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B6 @Bit 14 : Backward field. */ + #define ETM_TRCSEQEVR_B6_Pos (14UL) /*!< Position of B6 field. */ + #define ETM_TRCSEQEVR_B6_Msk (0x1UL << ETM_TRCSEQEVR_B6_Pos) /*!< Bit mask of B6 field. */ + #define ETM_TRCSEQEVR_B6_Min (0x0UL) /*!< Min enumerator value of B6 field. */ + #define ETM_TRCSEQEVR_B6_Max (0x1UL) /*!< Max enumerator value of B6 field. */ + #define ETM_TRCSEQEVR_B6_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B6_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B7 @Bit 15 : Backward field. */ + #define ETM_TRCSEQEVR_B7_Pos (15UL) /*!< Position of B7 field. */ + #define ETM_TRCSEQEVR_B7_Msk (0x1UL << ETM_TRCSEQEVR_B7_Pos) /*!< Bit mask of B7 field. */ + #define ETM_TRCSEQEVR_B7_Min (0x0UL) /*!< Min enumerator value of B7 field. */ + #define ETM_TRCSEQEVR_B7_Max (0x1UL) /*!< Max enumerator value of B7 field. */ + #define ETM_TRCSEQEVR_B7_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B7_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + + +/* ETM_TRCSEQRSTEVR: Moves the sequencer to state 0 when a programmed event occurs. Might ignore writes when the trace unit is + enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a + valid event. */ + + #define ETM_TRCSEQRSTEVR_ResetValue (0x00000000UL) /*!< Reset value of TRCSEQRSTEVR register. */ + +/* EVENT @Bits 0..7 : Select which event should reset the sequencer. */ + #define ETM_TRCSEQRSTEVR_EVENT_Pos (0UL) /*!< Position of EVENT field. */ + #define ETM_TRCSEQRSTEVR_EVENT_Msk (0xFFUL << ETM_TRCSEQRSTEVR_EVENT_Pos) /*!< Bit mask of EVENT field. */ + #define ETM_TRCSEQRSTEVR_EVENT_Min (0x00UL) /*!< Min value of EVENT field. */ + #define ETM_TRCSEQRSTEVR_EVENT_Max (0xFFUL) /*!< Max size of EVENT field. */ + + +/* ETM_TRCSEQSTR: Use this to set, or read, the sequencer state. Might ignore writes when the trace unit is enabled or not idle. + Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state + transitions must be programmed with a valid event. */ + + #define ETM_TRCSEQSTR_ResetValue (0x00000000UL) /*!< Reset value of TRCSEQSTR register. */ + +/* STATE @Bits 0..1 : Sets or returns the state of the sequencer. */ + #define ETM_TRCSEQSTR_STATE_Pos (0UL) /*!< Position of STATE field. */ + #define ETM_TRCSEQSTR_STATE_Msk (0x3UL << ETM_TRCSEQSTR_STATE_Pos) /*!< Bit mask of STATE field. */ + #define ETM_TRCSEQSTR_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field. */ + #define ETM_TRCSEQSTR_STATE_Max (0x3UL) /*!< Max enumerator value of STATE field. */ + #define ETM_TRCSEQSTR_STATE_State0 (0x0UL) /*!< The sequencer is in state 0. */ + #define ETM_TRCSEQSTR_STATE_State1 (0x1UL) /*!< The sequencer is in state 1. */ + #define ETM_TRCSEQSTR_STATE_State2 (0x2UL) /*!< The sequencer is in state 2. */ + #define ETM_TRCSEQSTR_STATE_State3 (0x3UL) /*!< The sequencer is in state 3. */ + + +/* ETM_TRCEXTINSELR: Use this to set, or read, which external inputs are resources to the trace unit. Might ignore writes when + the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the + sequencer is used, all sequencer state transitions must be programmed with a valid event. */ + + #define ETM_TRCEXTINSELR_ResetValue (0x00000000UL) /*!< Reset value of TRCEXTINSELR register. */ + +/* SEL0 @Bits 0..7 : Each field in this collection selects an external input as a resource for the trace unit. */ + #define ETM_TRCEXTINSELR_SEL0_Pos (0UL) /*!< Position of SEL0 field. */ + #define ETM_TRCEXTINSELR_SEL0_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL0_Pos) /*!< Bit mask of SEL0 field. */ + #define ETM_TRCEXTINSELR_SEL0_Min (0x00UL) /*!< Min value of SEL0 field. */ + #define ETM_TRCEXTINSELR_SEL0_Max (0xFFUL) /*!< Max size of SEL0 field. */ + +/* SEL1 @Bits 8..15 : Each field in this collection selects an external input as a resource for the trace unit. */ + #define ETM_TRCEXTINSELR_SEL1_Pos (8UL) /*!< Position of SEL1 field. */ + #define ETM_TRCEXTINSELR_SEL1_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL1_Pos) /*!< Bit mask of SEL1 field. */ + #define ETM_TRCEXTINSELR_SEL1_Min (0x00UL) /*!< Min value of SEL1 field. */ + #define ETM_TRCEXTINSELR_SEL1_Max (0xFFUL) /*!< Max size of SEL1 field. */ + +/* SEL2 @Bits 16..23 : Each field in this collection selects an external input as a resource for the trace unit. */ + #define ETM_TRCEXTINSELR_SEL2_Pos (16UL) /*!< Position of SEL2 field. */ + #define ETM_TRCEXTINSELR_SEL2_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL2_Pos) /*!< Bit mask of SEL2 field. */ + #define ETM_TRCEXTINSELR_SEL2_Min (0x00UL) /*!< Min value of SEL2 field. */ + #define ETM_TRCEXTINSELR_SEL2_Max (0xFFUL) /*!< Max size of SEL2 field. */ + +/* SEL3 @Bits 24..31 : Each field in this collection selects an external input as a resource for the trace unit. */ + #define ETM_TRCEXTINSELR_SEL3_Pos (24UL) /*!< Position of SEL3 field. */ + #define ETM_TRCEXTINSELR_SEL3_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL3_Pos) /*!< Bit mask of SEL3 field. */ + #define ETM_TRCEXTINSELR_SEL3_Min (0x00UL) /*!< Min value of SEL3 field. */ + #define ETM_TRCEXTINSELR_SEL3_Max (0xFFUL) /*!< Max size of SEL3 field. */ + + +/* ETM_TRCCNTRLDVR: This sets or returns the reload count value for counter n. Might ignore writes when the trace unit is + enabled or not idle. */ + + #define ETM_TRCCNTRLDVR_MaxCount (4UL) /*!< Max size of TRCCNTRLDVR[4] array. */ + #define ETM_TRCCNTRLDVR_MaxIndex (3UL) /*!< Max index of TRCCNTRLDVR[4] array. */ + #define ETM_TRCCNTRLDVR_MinIndex (0UL) /*!< Min index of TRCCNTRLDVR[4] array. */ + #define ETM_TRCCNTRLDVR_ResetValue (0x00000000UL) /*!< Reset value of TRCCNTRLDVR[4] register. */ + +/* VALUE @Bits 0..15 : Contains the reload value for counter n. When a reload event occurs for counter n then the trace unit + copies the VALUEn field into counter n. */ + + #define ETM_TRCCNTRLDVR_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define ETM_TRCCNTRLDVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTRLDVR_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define ETM_TRCCNTRLDVR_VALUE_Min (0x0000UL) /*!< Min value of VALUE field. */ + #define ETM_TRCCNTRLDVR_VALUE_Max (0xFFFFUL) /*!< Max size of VALUE field. */ + + +/* ETM_TRCCNTCTLR: Controls the operation of counter n. Might ignore writes when the trace unit is enabled or not idle. */ + #define ETM_TRCCNTCTLR_MaxCount (4UL) /*!< Max size of TRCCNTCTLR[4] array. */ + #define ETM_TRCCNTCTLR_MaxIndex (3UL) /*!< Max index of TRCCNTCTLR[4] array. */ + #define ETM_TRCCNTCTLR_MinIndex (0UL) /*!< Min index of TRCCNTCTLR[4] array. */ + #define ETM_TRCCNTCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCCNTCTLR[4] register. */ + +/* CNTEVENT @Bits 0..7 : Selects an event, that when it occurs causes counter n to decrement. */ + #define ETM_TRCCNTCTLR_CNTEVENT_Pos (0UL) /*!< Position of CNTEVENT field. */ + #define ETM_TRCCNTCTLR_CNTEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_CNTEVENT_Pos) /*!< Bit mask of CNTEVENT field. */ + #define ETM_TRCCNTCTLR_CNTEVENT_Min (0x00UL) /*!< Min value of CNTEVENT field. */ + #define ETM_TRCCNTCTLR_CNTEVENT_Max (0xFFUL) /*!< Max size of CNTEVENT field. */ + +/* RLDEVENT @Bits 8..15 : Selects an event, that when it occurs causes a reload event for counter n. */ + #define ETM_TRCCNTCTLR_RLDEVENT_Pos (8UL) /*!< Position of RLDEVENT field. */ + #define ETM_TRCCNTCTLR_RLDEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_RLDEVENT_Pos) /*!< Bit mask of RLDEVENT field. */ + #define ETM_TRCCNTCTLR_RLDEVENT_Min (0x00UL) /*!< Min value of RLDEVENT field. */ + #define ETM_TRCCNTCTLR_RLDEVENT_Max (0xFFUL) /*!< Max size of RLDEVENT field. */ + +/* RLDSELF @Bit 16 : Controls whether a reload event occurs for counter n, when counter n reaches zero. */ + #define ETM_TRCCNTCTLR_RLDSELF_Pos (16UL) /*!< Position of RLDSELF field. */ + #define ETM_TRCCNTCTLR_RLDSELF_Msk (0x1UL << ETM_TRCCNTCTLR_RLDSELF_Pos) /*!< Bit mask of RLDSELF field. */ + #define ETM_TRCCNTCTLR_RLDSELF_Min (0x0UL) /*!< Min enumerator value of RLDSELF field. */ + #define ETM_TRCCNTCTLR_RLDSELF_Max (0x1UL) /*!< Max enumerator value of RLDSELF field. */ + #define ETM_TRCCNTCTLR_RLDSELF_Disabled (0x0UL) /*!< The counter is in Normal mode. */ + #define ETM_TRCCNTCTLR_RLDSELF_Enabled (0x1UL) /*!< The counter is in Self-reload mode. */ + +/* CNTCHAIN @Bit 17 : For TRCCNTCTLR3 and TRCCNTCTLR1, this bit controls whether counter n decrements when a reload event occurs + for counter n-1. */ + + #define ETM_TRCCNTCTLR_CNTCHAIN_Pos (17UL) /*!< Position of CNTCHAIN field. */ + #define ETM_TRCCNTCTLR_CNTCHAIN_Msk (0x1UL << ETM_TRCCNTCTLR_CNTCHAIN_Pos) /*!< Bit mask of CNTCHAIN field. */ + #define ETM_TRCCNTCTLR_CNTCHAIN_Min (0x0UL) /*!< Min enumerator value of CNTCHAIN field. */ + #define ETM_TRCCNTCTLR_CNTCHAIN_Max (0x1UL) /*!< Max enumerator value of CNTCHAIN field. */ + #define ETM_TRCCNTCTLR_CNTCHAIN_Disabled (0x0UL) /*!< Counter n does not decrement when a reload event for counter n-1 + occurs.*/ + #define ETM_TRCCNTCTLR_CNTCHAIN_Enabled (0x1UL) /*!< Counter n decrements when a reload event for counter n-1 occurs. This + concatenates counter n and counter n-1, to provide a larger count + value.*/ + + +/* ETM_TRCCNTVR: This sets or returns the value of counter n. The count value is only stable when TRCSTATR.PMSTABLE == 1. If + software uses counter n then it must write to this register to set the initial counter value. Might ignore + writes when the trace unit is enabled or not idle. */ + + #define ETM_TRCCNTVR_MaxCount (4UL) /*!< Max size of TRCCNTVR[4] array. */ + #define ETM_TRCCNTVR_MaxIndex (3UL) /*!< Max index of TRCCNTVR[4] array. */ + #define ETM_TRCCNTVR_MinIndex (0UL) /*!< Min index of TRCCNTVR[4] array. */ + #define ETM_TRCCNTVR_ResetValue (0x00000000UL) /*!< Reset value of TRCCNTVR[4] register. */ + +/* VALUE @Bits 0..15 : Contains the count value of counter n. */ + #define ETM_TRCCNTVR_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define ETM_TRCCNTVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTVR_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define ETM_TRCCNTVR_VALUE_Min (0x0000UL) /*!< Min value of VALUE field. */ + #define ETM_TRCCNTVR_VALUE_Max (0xFFFFUL) /*!< Max size of VALUE field. */ + + +/* ETM_TRCRSCTLR: Controls the selection of the resources in the trace unit. Might ignore writes when the trace unit is enabled + or not idle. If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE behavior of the + resource selector occurs, so the resource selector might fire unexpectedly or might not fire. Reads of the + TRCRSCTLRn might return UNKNOWN. */ + + #define ETM_TRCRSCTLR_MaxCount (30UL) /*!< Max size of TRCRSCTLR[32] array. */ + #define ETM_TRCRSCTLR_MaxIndex (31UL) /*!< Max index of TRCRSCTLR[32] array. */ + #define ETM_TRCRSCTLR_MinIndex (2UL) /*!< Min index of TRCRSCTLR[32] array. */ + #define ETM_TRCRSCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCRSCTLR[32] register. */ + +/* EN @Bit 0 : Trace unit enable bit */ + #define ETM_TRCRSCTLR_EN_Pos (0UL) /*!< Position of EN field. */ + #define ETM_TRCRSCTLR_EN_Msk (0x1UL << ETM_TRCRSCTLR_EN_Pos) /*!< Bit mask of EN field. */ + #define ETM_TRCRSCTLR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ETM_TRCRSCTLR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ETM_TRCRSCTLR_EN_Disabled (0x0UL) /*!< The trace unit is disabled. All trace resources are inactive and no + trace is generated.*/ + #define ETM_TRCRSCTLR_EN_Enabled (0x1UL) /*!< The trace unit is enabled. */ + + +/* ETM_TRCSSCCR0: Controls the single-shot comparator. */ + #define ETM_TRCSSCCR0_ResetValue (0x00000000UL) /*!< Reset value of TRCSSCCR0 register. */ + +/* RST @Bit 24 : Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to + be detected */ + + #define ETM_TRCSSCCR0_RST_Pos (24UL) /*!< Position of RST field. */ + #define ETM_TRCSSCCR0_RST_Msk (0x1UL << ETM_TRCSSCCR0_RST_Pos) /*!< Bit mask of RST field. */ + #define ETM_TRCSSCCR0_RST_Min (0x0UL) /*!< Min enumerator value of RST field. */ + #define ETM_TRCSSCCR0_RST_Max (0x1UL) /*!< Max enumerator value of RST field. */ + #define ETM_TRCSSCCR0_RST_Disabled (0x0UL) /*!< Multiple matches can not be detected. */ + #define ETM_TRCSSCCR0_RST_Enabled (0x1UL) /*!< Multiple matches can occur. */ + + +/* ETM_TRCSSCSR0: Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses. */ + #define ETM_TRCSSCSR0_ResetValue (0x00000000UL) /*!< Reset value of TRCSSCSR0 register. */ + +/* INST @Bit 0 : Instruction address comparator support */ + #define ETM_TRCSSCSR0_INST_Pos (0UL) /*!< Position of INST field. */ + #define ETM_TRCSSCSR0_INST_Msk (0x1UL << ETM_TRCSSCSR0_INST_Pos) /*!< Bit mask of INST field. */ + #define ETM_TRCSSCSR0_INST_Min (0x0UL) /*!< Min enumerator value of INST field. */ + #define ETM_TRCSSCSR0_INST_Max (0x1UL) /*!< Max enumerator value of INST field. */ + #define ETM_TRCSSCSR0_INST_False (0x0UL) /*!< Single-shot instruction address comparisons not supported. */ + #define ETM_TRCSSCSR0_INST_True (0x1UL) /*!< Single-shot instruction address comparisons supported. */ + +/* DA @Bit 1 : Data address comparator support */ + #define ETM_TRCSSCSR0_DA_Pos (1UL) /*!< Position of DA field. */ + #define ETM_TRCSSCSR0_DA_Msk (0x1UL << ETM_TRCSSCSR0_DA_Pos) /*!< Bit mask of DA field. */ + #define ETM_TRCSSCSR0_DA_Min (0x0UL) /*!< Min enumerator value of DA field. */ + #define ETM_TRCSSCSR0_DA_Max (0x1UL) /*!< Max enumerator value of DA field. */ + #define ETM_TRCSSCSR0_DA_False (0x0UL) /*!< Data address comparisons not supported. */ + #define ETM_TRCSSCSR0_DA_True (0x1UL) /*!< Data address comparisons supported. */ + +/* DV @Bit 2 : Data value comparator support */ + #define ETM_TRCSSCSR0_DV_Pos (2UL) /*!< Position of DV field. */ + #define ETM_TRCSSCSR0_DV_Msk (0x1UL << ETM_TRCSSCSR0_DV_Pos) /*!< Bit mask of DV field. */ + #define ETM_TRCSSCSR0_DV_Min (0x0UL) /*!< Min enumerator value of DV field. */ + #define ETM_TRCSSCSR0_DV_Max (0x1UL) /*!< Max enumerator value of DV field. */ + #define ETM_TRCSSCSR0_DV_False (0x0UL) /*!< Data value comparisons not supported. */ + #define ETM_TRCSSCSR0_DV_True (0x1UL) /*!< Data value comparisons supported. */ + +/* PC @Bit 3 : Process counter value comparator support */ + #define ETM_TRCSSCSR0_PC_Pos (3UL) /*!< Position of PC field. */ + #define ETM_TRCSSCSR0_PC_Msk (0x1UL << ETM_TRCSSCSR0_PC_Pos) /*!< Bit mask of PC field. */ + #define ETM_TRCSSCSR0_PC_Min (0x0UL) /*!< Min enumerator value of PC field. */ + #define ETM_TRCSSCSR0_PC_Max (0x1UL) /*!< Max enumerator value of PC field. */ + #define ETM_TRCSSCSR0_PC_False (0x0UL) /*!< Process counter value comparisons not supported. */ + #define ETM_TRCSSCSR0_PC_True (0x1UL) /*!< Process counter value comparisons supported. */ + +/* STATUS @Bit 31 : Single-shot status. This indicates whether any of the selected comparators have matched. */ + #define ETM_TRCSSCSR0_STATUS_Pos (31UL) /*!< Position of STATUS field. */ + #define ETM_TRCSSCSR0_STATUS_Msk (0x1UL << ETM_TRCSSCSR0_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define ETM_TRCSSCSR0_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define ETM_TRCSSCSR0_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define ETM_TRCSSCSR0_STATUS_NoMatch (0x0UL) /*!< Match has not occurred. */ + #define ETM_TRCSSCSR0_STATUS_Match (0x1UL) /*!< Match has occurred at least once. */ + + +/* ETM_TRCSSPCICR0: Selects the processor comparator inputs for Single-shot control. */ + #define ETM_TRCSSPCICR0_ResetValue (0x00000000UL) /*!< Reset value of TRCSSPCICR0 register. */ + +/* PC0 @Bit 0 : Selects processor comparator 0 inputs for Single-shot control */ + #define ETM_TRCSSPCICR0_PC0_Pos (0UL) /*!< Position of PC0 field. */ + #define ETM_TRCSSPCICR0_PC0_Msk (0x1UL << ETM_TRCSSPCICR0_PC0_Pos) /*!< Bit mask of PC0 field. */ + #define ETM_TRCSSPCICR0_PC0_Min (0x0UL) /*!< Min enumerator value of PC0 field. */ + #define ETM_TRCSSPCICR0_PC0_Max (0x1UL) /*!< Max enumerator value of PC0 field. */ + #define ETM_TRCSSPCICR0_PC0_Disabled (0x0UL) /*!< Processor comparator 0 is not selected for Single-shot control. */ + #define ETM_TRCSSPCICR0_PC0_Enabled (0x1UL) /*!< Processor comparator 0 is selected for Single-shot control. */ + +/* PC1 @Bit 1 : Selects processor comparator 1 inputs for Single-shot control */ + #define ETM_TRCSSPCICR0_PC1_Pos (1UL) /*!< Position of PC1 field. */ + #define ETM_TRCSSPCICR0_PC1_Msk (0x1UL << ETM_TRCSSPCICR0_PC1_Pos) /*!< Bit mask of PC1 field. */ + #define ETM_TRCSSPCICR0_PC1_Min (0x0UL) /*!< Min enumerator value of PC1 field. */ + #define ETM_TRCSSPCICR0_PC1_Max (0x1UL) /*!< Max enumerator value of PC1 field. */ + #define ETM_TRCSSPCICR0_PC1_Disabled (0x0UL) /*!< Processor comparator 1 is not selected for Single-shot control. */ + #define ETM_TRCSSPCICR0_PC1_Enabled (0x1UL) /*!< Processor comparator 1 is selected for Single-shot control. */ + +/* PC2 @Bit 2 : Selects processor comparator 2 inputs for Single-shot control */ + #define ETM_TRCSSPCICR0_PC2_Pos (2UL) /*!< Position of PC2 field. */ + #define ETM_TRCSSPCICR0_PC2_Msk (0x1UL << ETM_TRCSSPCICR0_PC2_Pos) /*!< Bit mask of PC2 field. */ + #define ETM_TRCSSPCICR0_PC2_Min (0x0UL) /*!< Min enumerator value of PC2 field. */ + #define ETM_TRCSSPCICR0_PC2_Max (0x1UL) /*!< Max enumerator value of PC2 field. */ + #define ETM_TRCSSPCICR0_PC2_Disabled (0x0UL) /*!< Processor comparator 2 is not selected for Single-shot control. */ + #define ETM_TRCSSPCICR0_PC2_Enabled (0x1UL) /*!< Processor comparator 2 is selected for Single-shot control. */ + +/* PC3 @Bit 3 : Selects processor comparator 3 inputs for Single-shot control */ + #define ETM_TRCSSPCICR0_PC3_Pos (3UL) /*!< Position of PC3 field. */ + #define ETM_TRCSSPCICR0_PC3_Msk (0x1UL << ETM_TRCSSPCICR0_PC3_Pos) /*!< Bit mask of PC3 field. */ + #define ETM_TRCSSPCICR0_PC3_Min (0x0UL) /*!< Min enumerator value of PC3 field. */ + #define ETM_TRCSSPCICR0_PC3_Max (0x1UL) /*!< Max enumerator value of PC3 field. */ + #define ETM_TRCSSPCICR0_PC3_Disabled (0x0UL) /*!< Processor comparator 3 is not selected for Single-shot control. */ + #define ETM_TRCSSPCICR0_PC3_Enabled (0x1UL) /*!< Processor comparator 3 is selected for Single-shot control. */ + + +/* ETM_TRCPDCR: Controls the single-shot comparator. */ + #define ETM_TRCPDCR_ResetValue (0x00000000UL) /*!< Reset value of TRCPDCR register. */ + +/* PU @Bit 24 : Power up request, to request that power to ETM and access to the trace registers is maintained. */ + #define ETM_TRCPDCR_PU_Pos (24UL) /*!< Position of PU field. */ + #define ETM_TRCPDCR_PU_Msk (0x1UL << ETM_TRCPDCR_PU_Pos) /*!< Bit mask of PU field. */ + #define ETM_TRCPDCR_PU_Min (0x0UL) /*!< Min enumerator value of PU field. */ + #define ETM_TRCPDCR_PU_Max (0x1UL) /*!< Max enumerator value of PU field. */ + #define ETM_TRCPDCR_PU_Disabled (0x0UL) /*!< Power not requested. */ + #define ETM_TRCPDCR_PU_Enabled (0x1UL) /*!< Power requested. */ + + +/* ETM_TRCPDSR: Indicates the power down status of the ETM. */ + #define ETM_TRCPDSR_ResetValue (0x00000000UL) /*!< Reset value of TRCPDSR register. */ + +/* POWER @Bit 0 : Indicates ETM is powered up */ + #define ETM_TRCPDSR_POWER_Pos (0UL) /*!< Position of POWER field. */ + #define ETM_TRCPDSR_POWER_Msk (0x1UL << ETM_TRCPDSR_POWER_Pos) /*!< Bit mask of POWER field. */ + #define ETM_TRCPDSR_POWER_Min (0x0UL) /*!< Min enumerator value of POWER field. */ + #define ETM_TRCPDSR_POWER_Max (0x1UL) /*!< Max enumerator value of POWER field. */ + #define ETM_TRCPDSR_POWER_NotPoweredUp (0x0UL) /*!< ETM is not powered up. All registers are not accessible. */ + #define ETM_TRCPDSR_POWER_PoweredUp (0x1UL) /*!< ETM is powered up. All registers are accessible. */ + +/* STICKYPD @Bit 1 : Sticky power down state. This bit is set to 1 when power to the ETM registers is removed, to indicate that + programming state has been lost. It is cleared after a read of the TRCPDSR */ + + #define ETM_TRCPDSR_STICKYPD_Pos (1UL) /*!< Position of STICKYPD field. */ + #define ETM_TRCPDSR_STICKYPD_Msk (0x1UL << ETM_TRCPDSR_STICKYPD_Pos) /*!< Bit mask of STICKYPD field. */ + #define ETM_TRCPDSR_STICKYPD_Min (0x0UL) /*!< Min enumerator value of STICKYPD field. */ + #define ETM_TRCPDSR_STICKYPD_Max (0x1UL) /*!< Max enumerator value of STICKYPD field. */ + #define ETM_TRCPDSR_STICKYPD_NotPoweredDown (0x0UL) /*!< Trace register power has not been removed since the TRCPDSR was last + read.*/ + #define ETM_TRCPDSR_STICKYPD_PoweredDown (0x1UL) /*!< Trace register power has been removed since the TRCPDSR was last + read.*/ + + +/* ETM_TRCITATBIDR: Sets the state of output pins. */ + #define ETM_TRCITATBIDR_ResetValue (0x00000000UL) /*!< Reset value of TRCITATBIDR register. */ + +/* ID0 @Bit 0 : Drives the ATIDMI[0] output pin. */ + #define ETM_TRCITATBIDR_ID0_Pos (0UL) /*!< Position of ID0 field. */ + #define ETM_TRCITATBIDR_ID0_Msk (0x1UL << ETM_TRCITATBIDR_ID0_Pos) /*!< Bit mask of ID0 field. */ + +/* ID1 @Bit 1 : Drives the ATIDMI[1] output pin. */ + #define ETM_TRCITATBIDR_ID1_Pos (1UL) /*!< Position of ID1 field. */ + #define ETM_TRCITATBIDR_ID1_Msk (0x1UL << ETM_TRCITATBIDR_ID1_Pos) /*!< Bit mask of ID1 field. */ + +/* ID2 @Bit 2 : Drives the ATIDMI[2] output pin. */ + #define ETM_TRCITATBIDR_ID2_Pos (2UL) /*!< Position of ID2 field. */ + #define ETM_TRCITATBIDR_ID2_Msk (0x1UL << ETM_TRCITATBIDR_ID2_Pos) /*!< Bit mask of ID2 field. */ + +/* ID3 @Bit 3 : Drives the ATIDMI[3] output pin. */ + #define ETM_TRCITATBIDR_ID3_Pos (3UL) /*!< Position of ID3 field. */ + #define ETM_TRCITATBIDR_ID3_Msk (0x1UL << ETM_TRCITATBIDR_ID3_Pos) /*!< Bit mask of ID3 field. */ + +/* ID4 @Bit 4 : Drives the ATIDMI[4] output pin. */ + #define ETM_TRCITATBIDR_ID4_Pos (4UL) /*!< Position of ID4 field. */ + #define ETM_TRCITATBIDR_ID4_Msk (0x1UL << ETM_TRCITATBIDR_ID4_Pos) /*!< Bit mask of ID4 field. */ + +/* ID5 @Bit 5 : Drives the ATIDMI[5] output pin. */ + #define ETM_TRCITATBIDR_ID5_Pos (5UL) /*!< Position of ID5 field. */ + #define ETM_TRCITATBIDR_ID5_Msk (0x1UL << ETM_TRCITATBIDR_ID5_Pos) /*!< Bit mask of ID5 field. */ + +/* ID6 @Bit 6 : Drives the ATIDMI[6] output pin. */ + #define ETM_TRCITATBIDR_ID6_Pos (6UL) /*!< Position of ID6 field. */ + #define ETM_TRCITATBIDR_ID6_Msk (0x1UL << ETM_TRCITATBIDR_ID6_Pos) /*!< Bit mask of ID6 field. */ + + +/* ETM_TRCITIATBINR: Reads the state of the input pins. */ + #define ETM_TRCITIATBINR_ResetValue (0x00000000UL) /*!< Reset value of TRCITIATBINR register. */ + +/* ATVALID @Bit 0 : Returns the value of the ATVALIDMI input pin. */ + #define ETM_TRCITIATBINR_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ + #define ETM_TRCITIATBINR_ATVALID_Msk (0x1UL << ETM_TRCITIATBINR_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ + +/* AFREADY @Bit 1 : Returns the value of the AFREADYMI input pin. */ + #define ETM_TRCITIATBINR_AFREADY_Pos (1UL) /*!< Position of AFREADY field. */ + #define ETM_TRCITIATBINR_AFREADY_Msk (0x1UL << ETM_TRCITIATBINR_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ + + +/* ETM_TRCITIATBOUTR: Sets the state of the output pins. */ + #define ETM_TRCITIATBOUTR_ResetValue (0x00000000UL) /*!< Reset value of TRCITIATBOUTR register. */ + +/* ATVALID @Bit 0 : Drives the ATVALIDMI output pin. */ + #define ETM_TRCITIATBOUTR_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ + #define ETM_TRCITIATBOUTR_ATVALID_Msk (0x1UL << ETM_TRCITIATBOUTR_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ + +/* AFREADY @Bit 1 : Drives the AFREADYMI output pin. */ + #define ETM_TRCITIATBOUTR_AFREADY_Pos (1UL) /*!< Position of AFREADY field. */ + #define ETM_TRCITIATBOUTR_AFREADY_Msk (0x1UL << ETM_TRCITIATBOUTR_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ + + +/* ETM_TRCITCTRL: Enables topology detection or integration testing, by putting ETM-M33 into integration mode. */ + #define ETM_TRCITCTRL_ResetValue (0x00000000UL) /*!< Reset value of TRCITCTRL register. */ + +/* IME @Bit 0 : Integration mode enable */ + #define ETM_TRCITCTRL_IME_Pos (0UL) /*!< Position of IME field. */ + #define ETM_TRCITCTRL_IME_Msk (0x1UL << ETM_TRCITCTRL_IME_Pos) /*!< Bit mask of IME field. */ + #define ETM_TRCITCTRL_IME_Min (0x0UL) /*!< Min enumerator value of IME field. */ + #define ETM_TRCITCTRL_IME_Max (0x1UL) /*!< Max enumerator value of IME field. */ + #define ETM_TRCITCTRL_IME_Disabled (0x0UL) /*!< ETM is not in integration mode. */ + #define ETM_TRCITCTRL_IME_Enabled (0x1UL) /*!< ETM is in integration mode. */ + + +/* ETM_TRCCLAIMSET: Sets bits in the claim tag and determines the number of claim tag bits implemented. */ + #define ETM_TRCCLAIMSET_ResetValue (0x00000000UL) /*!< Reset value of TRCCLAIMSET register. */ + +/* SET0 @Bit 0 : Claim tag set register */ + #define ETM_TRCCLAIMSET_SET0_Pos (0UL) /*!< Position of SET0 field. */ + #define ETM_TRCCLAIMSET_SET0_Msk (0x1UL << ETM_TRCCLAIMSET_SET0_Pos) /*!< Bit mask of SET0 field. */ + #define ETM_TRCCLAIMSET_SET0_Min (0x0UL) /*!< Min enumerator value of SET0 field. */ + #define ETM_TRCCLAIMSET_SET0_Max (0x1UL) /*!< Max enumerator value of SET0 field. */ + #define ETM_TRCCLAIMSET_SET0_NotSet (0x0UL) /*!< Claim tag 0 is not set. */ + #define ETM_TRCCLAIMSET_SET0_Set (0x1UL) /*!< Claim tag 0 is set. */ + #define ETM_TRCCLAIMSET_SET0_Claim (0x1UL) /*!< Set claim tag 0. */ + +/* SET1 @Bit 1 : Claim tag set register */ + #define ETM_TRCCLAIMSET_SET1_Pos (1UL) /*!< Position of SET1 field. */ + #define ETM_TRCCLAIMSET_SET1_Msk (0x1UL << ETM_TRCCLAIMSET_SET1_Pos) /*!< Bit mask of SET1 field. */ + #define ETM_TRCCLAIMSET_SET1_Min (0x0UL) /*!< Min enumerator value of SET1 field. */ + #define ETM_TRCCLAIMSET_SET1_Max (0x1UL) /*!< Max enumerator value of SET1 field. */ + #define ETM_TRCCLAIMSET_SET1_NotSet (0x0UL) /*!< Claim tag 1 is not set. */ + #define ETM_TRCCLAIMSET_SET1_Set (0x1UL) /*!< Claim tag 1 is set. */ + #define ETM_TRCCLAIMSET_SET1_Claim (0x1UL) /*!< Set claim tag 1. */ + +/* SET2 @Bit 2 : Claim tag set register */ + #define ETM_TRCCLAIMSET_SET2_Pos (2UL) /*!< Position of SET2 field. */ + #define ETM_TRCCLAIMSET_SET2_Msk (0x1UL << ETM_TRCCLAIMSET_SET2_Pos) /*!< Bit mask of SET2 field. */ + #define ETM_TRCCLAIMSET_SET2_Min (0x0UL) /*!< Min enumerator value of SET2 field. */ + #define ETM_TRCCLAIMSET_SET2_Max (0x1UL) /*!< Max enumerator value of SET2 field. */ + #define ETM_TRCCLAIMSET_SET2_NotSet (0x0UL) /*!< Claim tag 2 is not set. */ + #define ETM_TRCCLAIMSET_SET2_Set (0x1UL) /*!< Claim tag 2 is set. */ + #define ETM_TRCCLAIMSET_SET2_Claim (0x1UL) /*!< Set claim tag 2. */ + +/* SET3 @Bit 3 : Claim tag set register */ + #define ETM_TRCCLAIMSET_SET3_Pos (3UL) /*!< Position of SET3 field. */ + #define ETM_TRCCLAIMSET_SET3_Msk (0x1UL << ETM_TRCCLAIMSET_SET3_Pos) /*!< Bit mask of SET3 field. */ + #define ETM_TRCCLAIMSET_SET3_Min (0x0UL) /*!< Min enumerator value of SET3 field. */ + #define ETM_TRCCLAIMSET_SET3_Max (0x1UL) /*!< Max enumerator value of SET3 field. */ + #define ETM_TRCCLAIMSET_SET3_NotSet (0x0UL) /*!< Claim tag 3 is not set. */ + #define ETM_TRCCLAIMSET_SET3_Set (0x1UL) /*!< Claim tag 3 is set. */ + #define ETM_TRCCLAIMSET_SET3_Claim (0x1UL) /*!< Set claim tag 3. */ + + +/* ETM_TRCCLAIMCLR: Clears bits in the claim tag and determines the current value of the claim tag. */ + #define ETM_TRCCLAIMCLR_ResetValue (0x00000000UL) /*!< Reset value of TRCCLAIMCLR register. */ + +/* CLR0 @Bit 0 : Claim tag clear register */ + #define ETM_TRCCLAIMCLR_CLR0_Pos (0UL) /*!< Position of CLR0 field. */ + #define ETM_TRCCLAIMCLR_CLR0_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR0_Pos) /*!< Bit mask of CLR0 field. */ + #define ETM_TRCCLAIMCLR_CLR0_Min (0x0UL) /*!< Min enumerator value of CLR0 field. */ + #define ETM_TRCCLAIMCLR_CLR0_Max (0x1UL) /*!< Max enumerator value of CLR0 field. */ + #define ETM_TRCCLAIMCLR_CLR0_NotSet (0x0UL) /*!< Claim tag 0 is not set. */ + #define ETM_TRCCLAIMCLR_CLR0_Set (0x1UL) /*!< Claim tag 0 is set. */ + #define ETM_TRCCLAIMCLR_CLR0_Clear (0x1UL) /*!< Clear claim tag 0. */ + +/* CLR1 @Bit 1 : Claim tag clear register */ + #define ETM_TRCCLAIMCLR_CLR1_Pos (1UL) /*!< Position of CLR1 field. */ + #define ETM_TRCCLAIMCLR_CLR1_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR1_Pos) /*!< Bit mask of CLR1 field. */ + #define ETM_TRCCLAIMCLR_CLR1_Min (0x0UL) /*!< Min enumerator value of CLR1 field. */ + #define ETM_TRCCLAIMCLR_CLR1_Max (0x1UL) /*!< Max enumerator value of CLR1 field. */ + #define ETM_TRCCLAIMCLR_CLR1_NotSet (0x0UL) /*!< Claim tag 1 is not set. */ + #define ETM_TRCCLAIMCLR_CLR1_Set (0x1UL) /*!< Claim tag 1 is set. */ + #define ETM_TRCCLAIMCLR_CLR1_Clear (0x1UL) /*!< Clear claim tag 1. */ + +/* CLR2 @Bit 2 : Claim tag clear register */ + #define ETM_TRCCLAIMCLR_CLR2_Pos (2UL) /*!< Position of CLR2 field. */ + #define ETM_TRCCLAIMCLR_CLR2_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR2_Pos) /*!< Bit mask of CLR2 field. */ + #define ETM_TRCCLAIMCLR_CLR2_Min (0x0UL) /*!< Min enumerator value of CLR2 field. */ + #define ETM_TRCCLAIMCLR_CLR2_Max (0x1UL) /*!< Max enumerator value of CLR2 field. */ + #define ETM_TRCCLAIMCLR_CLR2_NotSet (0x0UL) /*!< Claim tag 2 is not set. */ + #define ETM_TRCCLAIMCLR_CLR2_Set (0x1UL) /*!< Claim tag 2 is set. */ + #define ETM_TRCCLAIMCLR_CLR2_Clear (0x1UL) /*!< Clear claim tag 2. */ + +/* CLR3 @Bit 3 : Claim tag clear register */ + #define ETM_TRCCLAIMCLR_CLR3_Pos (3UL) /*!< Position of CLR3 field. */ + #define ETM_TRCCLAIMCLR_CLR3_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR3_Pos) /*!< Bit mask of CLR3 field. */ + #define ETM_TRCCLAIMCLR_CLR3_Min (0x0UL) /*!< Min enumerator value of CLR3 field. */ + #define ETM_TRCCLAIMCLR_CLR3_Max (0x1UL) /*!< Max enumerator value of CLR3 field. */ + #define ETM_TRCCLAIMCLR_CLR3_NotSet (0x0UL) /*!< Claim tag 3 is not set. */ + #define ETM_TRCCLAIMCLR_CLR3_Set (0x1UL) /*!< Claim tag 3 is set. */ + #define ETM_TRCCLAIMCLR_CLR3_Clear (0x1UL) /*!< Clear claim tag 3. */ + + +/* ETM_TRCAUTHSTATUS: Indicates the current level of tracing permitted by the system */ + #define ETM_TRCAUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of TRCAUTHSTATUS register. */ + +/* NSID @Bits 0..1 : Non-secure Invasive Debug */ + #define ETM_TRCAUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ + #define ETM_TRCAUTHSTATUS_NSID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ + #define ETM_TRCAUTHSTATUS_NSID_Min (0x0UL) /*!< Min enumerator value of NSID field. */ + #define ETM_TRCAUTHSTATUS_NSID_Max (0x1UL) /*!< Max enumerator value of NSID field. */ + #define ETM_TRCAUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ETM_TRCAUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */ + #define ETM_TRCAUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ + #define ETM_TRCAUTHSTATUS_NSNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ + #define ETM_TRCAUTHSTATUS_NSNID_Min (0x0UL) /*!< Min enumerator value of NSNID field. */ + #define ETM_TRCAUTHSTATUS_NSNID_Max (0x1UL) /*!< Max enumerator value of NSNID field. */ + #define ETM_TRCAUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ETM_TRCAUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SID @Bits 4..5 : Secure Invasive Debug */ + #define ETM_TRCAUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ + #define ETM_TRCAUTHSTATUS_SID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ + #define ETM_TRCAUTHSTATUS_SID_Min (0x0UL) /*!< Min enumerator value of SID field. */ + #define ETM_TRCAUTHSTATUS_SID_Max (0x1UL) /*!< Max enumerator value of SID field. */ + #define ETM_TRCAUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ETM_TRCAUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SNID @Bits 6..7 : Secure Non-Invasive Debug */ + #define ETM_TRCAUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ + #define ETM_TRCAUTHSTATUS_SNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ + #define ETM_TRCAUTHSTATUS_SNID_Min (0x0UL) /*!< Min enumerator value of SNID field. */ + #define ETM_TRCAUTHSTATUS_SNID_Max (0x1UL) /*!< Max enumerator value of SNID field. */ + #define ETM_TRCAUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ETM_TRCAUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */ + + +/* ETM_TRCDEVARCH: The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 component */ + #define ETM_TRCDEVARCH_ResetValue (0x00000000UL) /*!< Reset value of TRCDEVARCH register. */ + +/* ARCHID @Bits 0..15 : Architecture ID */ + #define ETM_TRCDEVARCH_ARCHID_Pos (0UL) /*!< Position of ARCHID field. */ + #define ETM_TRCDEVARCH_ARCHID_Msk (0xFFFFUL << ETM_TRCDEVARCH_ARCHID_Pos) /*!< Bit mask of ARCHID field. */ + #define ETM_TRCDEVARCH_ARCHID_Min (0x4A13UL) /*!< Min enumerator value of ARCHID field. */ + #define ETM_TRCDEVARCH_ARCHID_Max (0x4A13UL) /*!< Max enumerator value of ARCHID field. */ + #define ETM_TRCDEVARCH_ARCHID_ETMv42 (0x4A13UL) /*!< Component is an ETMv4 component */ + +/* REVISION @Bits 16..19 : Architecture revision */ + #define ETM_TRCDEVARCH_REVISION_Pos (16UL) /*!< Position of REVISION field. */ + #define ETM_TRCDEVARCH_REVISION_Msk (0xFUL << ETM_TRCDEVARCH_REVISION_Pos) /*!< Bit mask of REVISION field. */ + #define ETM_TRCDEVARCH_REVISION_Min (0x2UL) /*!< Min enumerator value of REVISION field. */ + #define ETM_TRCDEVARCH_REVISION_Max (0x2UL) /*!< Max enumerator value of REVISION field. */ + #define ETM_TRCDEVARCH_REVISION_v2 (0x2UL) /*!< Component is part of architecture 4.2 */ + +/* PRESENT @Bit 20 : This register is implemented */ + #define ETM_TRCDEVARCH_PRESENT_Pos (20UL) /*!< Position of PRESENT field. */ + #define ETM_TRCDEVARCH_PRESENT_Msk (0x1UL << ETM_TRCDEVARCH_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ + #define ETM_TRCDEVARCH_PRESENT_Min (0x0UL) /*!< Min enumerator value of PRESENT field. */ + #define ETM_TRCDEVARCH_PRESENT_Max (0x1UL) /*!< Max enumerator value of PRESENT field. */ + #define ETM_TRCDEVARCH_PRESENT_Absent (0x0UL) /*!< The register is not implemented. */ + #define ETM_TRCDEVARCH_PRESENT_Present (0x1UL) /*!< The register is implemented. */ + +/* ARCHITECT @Bits 21..31 : Defines the architect of the component */ + #define ETM_TRCDEVARCH_ARCHITECT_Pos (21UL) /*!< Position of ARCHITECT field. */ + #define ETM_TRCDEVARCH_ARCHITECT_Msk (0x7FFUL << ETM_TRCDEVARCH_ARCHITECT_Pos) /*!< Bit mask of ARCHITECT field. */ + #define ETM_TRCDEVARCH_ARCHITECT_Min (0x23BUL) /*!< Min enumerator value of ARCHITECT field. */ + #define ETM_TRCDEVARCH_ARCHITECT_Max (0x23BUL) /*!< Max enumerator value of ARCHITECT field. */ + #define ETM_TRCDEVARCH_ARCHITECT_Arm (0x23BUL) /*!< This peripheral was architected by Arm. */ + + +/* ETM_TRCDEVTYPE: Controls the single-shot comparator. */ + #define ETM_TRCDEVTYPE_ResetValue (0x00000000UL) /*!< Reset value of TRCDEVTYPE register. */ + +/* MAJOR @Bits 0..3 : The main type of the component */ + #define ETM_TRCDEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ + #define ETM_TRCDEVTYPE_MAJOR_Msk (0xFUL << ETM_TRCDEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ + #define ETM_TRCDEVTYPE_MAJOR_Min (0x3UL) /*!< Min enumerator value of MAJOR field. */ + #define ETM_TRCDEVTYPE_MAJOR_Max (0x3UL) /*!< Max enumerator value of MAJOR field. */ + #define ETM_TRCDEVTYPE_MAJOR_TraceSource (0x3UL) /*!< Peripheral is a trace source. */ + +/* SUB @Bits 4..7 : The sub-type of the component */ + #define ETM_TRCDEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ + #define ETM_TRCDEVTYPE_SUB_Msk (0xFUL << ETM_TRCDEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ + #define ETM_TRCDEVTYPE_SUB_Min (0x1UL) /*!< Min enumerator value of SUB field. */ + #define ETM_TRCDEVTYPE_SUB_Max (0x1UL) /*!< Max enumerator value of SUB field. */ + #define ETM_TRCDEVTYPE_SUB_ProcessorTrace (0x1UL) /*!< Peripheral is a processor trace source. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ==================================================== Struct FICR_INFO ===================================================== */ +/** + * @brief INFO [FICR_INFO] Device info + */ +typedef struct { + __IM uint32_t CONFIGID; /*!< (@ 0x00000000) Configuration identifier */ + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Device identifier */ + __IM uint32_t UUID[4]; /*!< (@ 0x0000000C) 128-bit Universally Unique IDentifier (UUID). */ + __IM uint32_t PART; /*!< (@ 0x0000001C) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000020) Part Variant, Hardware version and Production + configuration*/ + __IM uint32_t PACKAGE; /*!< (@ 0x00000024) Package option */ + __IM uint32_t RAM; /*!< (@ 0x00000028) RAM size (KB) */ + __IM uint32_t RRAM; /*!< (@ 0x0000002C) RRAM size (KB) */ +} NRF_FICR_INFO_Type; /*!< Size = 48 (0x030) */ + +/* FICR_INFO_CONFIGID: Configuration identifier */ + #define FICR_INFO_CONFIGID_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIGID register. */ + +/* HWID @Bits 0..15 : Identification number for the HW */ + #define FICR_INFO_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */ + #define FICR_INFO_CONFIGID_HWID_Msk (0xFFFFUL << FICR_INFO_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */ + + +/* FICR_INFO_DEVICEID: Device identifier */ + #define FICR_INFO_DEVICEID_MaxCount (2UL) /*!< Max size of DEVICEID[2] array. */ + #define FICR_INFO_DEVICEID_MaxIndex (1UL) /*!< Max index of DEVICEID[2] array. */ + #define FICR_INFO_DEVICEID_MinIndex (0UL) /*!< Min index of DEVICEID[2] array. */ + #define FICR_INFO_DEVICEID_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DEVICEID[2] register. */ + +/* DEVICEID @Bits 0..31 : 64 bit unique device identifier */ + #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ + #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + + +/* FICR_INFO_UUID: 128-bit Universally Unique IDentifier (UUID). */ + #define FICR_INFO_UUID_MaxCount (4UL) /*!< Max size of UUID[4] array. */ + #define FICR_INFO_UUID_MaxIndex (3UL) /*!< Max index of UUID[4] array. */ + #define FICR_INFO_UUID_MinIndex (0UL) /*!< Min index of UUID[4] array. */ + #define FICR_INFO_UUID_ResetValue (0xFFFFFFFFUL) /*!< Reset value of UUID[4] register. */ + +/* UUID @Bits 0..31 : Device UUID [n]. */ + #define FICR_INFO_UUID_UUID_Pos (0UL) /*!< Position of UUID field. */ + #define FICR_INFO_UUID_UUID_Msk (0xFFFFFFFFUL << FICR_INFO_UUID_UUID_Pos) /*!< Bit mask of UUID field. */ + + +/* FICR_INFO_PART: Part code */ + #define FICR_INFO_PART_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PART register. */ + +/* PART @Bits 0..31 : Part code */ + #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ + #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ + #define FICR_INFO_PART_PART_Min (0x054BC20AUL) /*!< Min enumerator value of PART field. */ + #define FICR_INFO_PART_PART_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PART field. */ + #define FICR_INFO_PART_PART_N54LM20A (0x054BC20AUL) /*!< nRF54LM20A */ + #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + +/* FICR_INFO_VARIANT: Part Variant, Hardware version and Production configuration */ + #define FICR_INFO_VARIANT_ResetValue (0xFFFFFFFFUL) /*!< Reset value of VARIANT register. */ + +/* VARIANT @Bits 0..31 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ + #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ + #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ + #define FICR_INFO_VARIANT_VARIANT_Min (0xFFFFFFFFUL) /*!< Min enumerator value of VARIANT field. */ + #define FICR_INFO_VARIANT_VARIANT_Max (0xFFFFFFFFUL) /*!< Max enumerator value of VARIANT field. */ + #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + +/* FICR_INFO_PACKAGE: Package option */ + #define FICR_INFO_PACKAGE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PACKAGE register. */ + +/* PACKAGE @Bits 0..31 : Package option */ + #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ + #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ + #define FICR_INFO_PACKAGE_PACKAGE_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PACKAGE field. */ + #define FICR_INFO_PACKAGE_PACKAGE_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PACKAGE field. */ + #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + +/* FICR_INFO_RAM: RAM size (KB) */ + #define FICR_INFO_RAM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RAM register. */ + +/* RAM @Bits 0..31 : RAM size (KB) */ + #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ + #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ + #define FICR_INFO_RAM_RAM_Min (0x00000200UL) /*!< Min enumerator value of RAM field. */ + #define FICR_INFO_RAM_RAM_Max (0xFFFFFFFFUL) /*!< Max enumerator value of RAM field. */ + #define FICR_INFO_RAM_RAM_K512 (0x00000200UL) /*!< 512 kByte RAM */ + #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + +/* FICR_INFO_RRAM: RRAM size (KB) */ + #define FICR_INFO_RRAM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RRAM register. */ + +/* RRAM @Bits 0..31 : RRAM size (KB) */ + #define FICR_INFO_RRAM_RRAM_Pos (0UL) /*!< Position of RRAM field. */ + #define FICR_INFO_RRAM_RRAM_Msk (0xFFFFFFFFUL << FICR_INFO_RRAM_RRAM_Pos) /*!< Bit mask of RRAM field. */ + #define FICR_INFO_RRAM_RRAM_Min (0x000007F4UL) /*!< Min enumerator value of RRAM field. */ + #define FICR_INFO_RRAM_RRAM_Max (0xFFFFFFFFUL) /*!< Max enumerator value of RRAM field. */ + #define FICR_INFO_RRAM_RRAM_K2036 (0x000007F4UL) /*!< 2036 KByte RRAM */ + #define FICR_INFO_RRAM_RRAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + + +/* =================================================== Struct FICR_TRIMCNF =================================================== */ +/** + * @brief TRIMCNF [FICR_TRIMCNF] (unspecified) + */ +typedef struct { + __IM uint32_t ADDR; /*!< (@ 0x00000000) Address of the register which will be written */ + __IM uint32_t DATA; /*!< (@ 0x00000004) Data to be written into the register */ +} NRF_FICR_TRIMCNF_Type; /*!< Size = 8 (0x008) */ + #define FICR_TRIMCNF_MaxCount (64UL) /*!< Size of TRIMCNF[64] array. */ + #define FICR_TRIMCNF_MaxIndex (63UL) /*!< Max index of TRIMCNF[64] array. */ + #define FICR_TRIMCNF_MinIndex (0UL) /*!< Min index of TRIMCNF[64] array. */ + +/* FICR_TRIMCNF_ADDR: Address of the register which will be written */ + #define FICR_TRIMCNF_ADDR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ADDR register. */ + +/* Address @Bits 0..31 : Address */ + #define FICR_TRIMCNF_ADDR_Address_Pos (0UL) /*!< Position of Address field. */ + #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field. */ + + +/* FICR_TRIMCNF_DATA: Data to be written into the register */ + #define FICR_TRIMCNF_DATA_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DATA register. */ + +/* Data @Bits 0..31 : Data */ + #define FICR_TRIMCNF_DATA_Data_Pos (0UL) /*!< Position of Data field. */ + #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field. */ + + + +/* ===================================================== Struct FICR_NFC ===================================================== */ +/** + * @brief NFC [FICR_NFC] (unspecified) + */ +typedef struct { + __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read these + values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and + NFCID1_LAST.*/ + __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read these + values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and + NFCID1_LAST.*/ + __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read these + values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and + NFCID1_LAST.*/ + __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read these + values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and + NFCID1_LAST.*/ +} NRF_FICR_NFC_Type; /*!< Size = 16 (0x010) */ + +/* FICR_NFC_TAGHEADER0: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST + and NFCID1_LAST. */ + + #define FICR_NFC_TAGHEADER0_ResetValue (0xFFFFFF5FUL) /*!< Reset value of TAGHEADER0 register. */ + +/* MFGID @Bits 0..7 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */ + #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */ + #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ + +/* UD1 @Bits 8..15 : Unique identifier byte 1 */ + #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */ + #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */ + +/* UD2 @Bits 16..23 : Unique identifier byte 2 */ + #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */ + #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */ + +/* UD3 @Bits 24..31 : Unique identifier byte 3 */ + #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ + #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */ + + +/* FICR_NFC_TAGHEADER1: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST + and NFCID1_LAST. */ + + #define FICR_NFC_TAGHEADER1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TAGHEADER1 register. */ + +/* UD4 @Bits 0..7 : Unique identifier byte 4 */ + #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */ + #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ + +/* UD5 @Bits 8..15 : Unique identifier byte 5 */ + #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */ + #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */ + +/* UD6 @Bits 16..23 : Unique identifier byte 6 */ + #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */ + #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */ + +/* UD7 @Bits 24..31 : Unique identifier byte 7 */ + #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ + #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */ + + +/* FICR_NFC_TAGHEADER2: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST + and NFCID1_LAST. */ + + #define FICR_NFC_TAGHEADER2_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TAGHEADER2 register. */ + +/* UD8 @Bits 0..7 : Unique identifier byte 8 */ + #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */ + #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ + +/* UD9 @Bits 8..15 : Unique identifier byte 9 */ + #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */ + #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */ + +/* UD10 @Bits 16..23 : Unique identifier byte 10 */ + #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */ + #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */ + +/* UD11 @Bits 24..31 : Unique identifier byte 11 */ + #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ + #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */ + + +/* FICR_NFC_TAGHEADER3: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST + and NFCID1_LAST. */ + + #define FICR_NFC_TAGHEADER3_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TAGHEADER3 register. */ + +/* UD12 @Bits 0..7 : Unique identifier byte 12 */ + #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */ + #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */ + +/* UD13 @Bits 8..15 : Unique identifier byte 13 */ + #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */ + #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */ + +/* UD14 @Bits 16..23 : Unique identifier byte 14 */ + #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */ + #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */ + +/* UD15 @Bits 24..31 : Unique identifier byte 15 */ + #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ + #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */ + + +/* ======================================================= Struct FICR ======================================================= */ +/** + * @brief Factory Information Configuration Registers + */ + typedef struct { /*!< FICR Structure */ + __IM uint32_t RESERVED[192]; + __IOM NRF_FICR_INFO_Type INFO; /*!< (@ 0x00000300) Device info */ + __IM uint32_t RESERVED1[20]; + __IM uint32_t ER[4]; /*!< (@ 0x00000380) Common encryption root key, word n */ + __IM uint32_t IR[4]; /*!< (@ 0x00000390) Common identity root key, word n */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000003A0) Device address type */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000003A4) Device address n */ + __IM uint32_t RESERVED2[21]; + __IOM NRF_FICR_TRIMCNF_Type TRIMCNF[64]; /*!< (@ 0x00000400) (unspecified) */ + __IOM NRF_FICR_NFC_Type NFC; /*!< (@ 0x00000600) (unspecified) */ + __IM uint32_t RESERVED3[4]; + __IM uint32_t XOSC32MTRIM; /*!< (@ 0x00000620) XOSC32M capacitor selection trim values */ + __IM uint32_t XOSC32KTRIM; /*!< (@ 0x00000624) XOSC32K capacitor selection trim values */ + } NRF_FICR_Type; /*!< Size = 1576 (0x628) */ + +/* FICR_ER: Common encryption root key, word n */ + #define FICR_ER_MaxCount (4UL) /*!< Max size of ER[4] array. */ + #define FICR_ER_MaxIndex (3UL) /*!< Max index of ER[4] array. */ + #define FICR_ER_MinIndex (0UL) /*!< Min index of ER[4] array. */ + #define FICR_ER_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ER[4] register. */ + +/* ER @Bits 0..31 : Encryption Root, word n */ + #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ + #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ + + +/* FICR_IR: Common identity root key, word n */ + #define FICR_IR_MaxCount (4UL) /*!< Max size of IR[4] array. */ + #define FICR_IR_MaxIndex (3UL) /*!< Max index of IR[4] array. */ + #define FICR_IR_MinIndex (0UL) /*!< Min index of IR[4] array. */ + #define FICR_IR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of IR[4] register. */ + +/* IR @Bits 0..31 : Identity Root, word n */ + #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ + #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ + + +/* FICR_DEVICEADDRTYPE: Device address type */ + #define FICR_DEVICEADDRTYPE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DEVICEADDRTYPE register. */ + +/* DEVICEADDRTYPE @Bit 0 : Device address type */ + #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ + #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of + DEVICEADDRTYPE field.*/ + #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Min (0x0UL) /*!< Min enumerator value of DEVICEADDRTYPE field. */ + #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Max (0x1UL) /*!< Max enumerator value of DEVICEADDRTYPE field. */ + #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0x0UL) /*!< Public address */ + #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (0x1UL) /*!< Random address */ + + +/* FICR_DEVICEADDR: Device address n */ + #define FICR_DEVICEADDR_MaxCount (2UL) /*!< Max size of DEVICEADDR[2] array. */ + #define FICR_DEVICEADDR_MaxIndex (1UL) /*!< Max index of DEVICEADDR[2] array. */ + #define FICR_DEVICEADDR_MinIndex (0UL) /*!< Min index of DEVICEADDR[2] array. */ + #define FICR_DEVICEADDR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DEVICEADDR[2] register. */ + +/* DEVICEADDR @Bits 0..31 : 48 bit device address */ + #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ + #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ + + +/* FICR_XOSC32MTRIM: XOSC32M capacitor selection trim values */ + #define FICR_XOSC32MTRIM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of XOSC32MTRIM register. */ + +/* SLOPE @Bits 0..8 : Slope trim factor on twos complement form */ + #define FICR_XOSC32MTRIM_SLOPE_Pos (0UL) /*!< Position of SLOPE field. */ + #define FICR_XOSC32MTRIM_SLOPE_Msk (0x1FFUL << FICR_XOSC32MTRIM_SLOPE_Pos) /*!< Bit mask of SLOPE field. */ + +/* OFFSET @Bits 16..25 : Offset trim factor on integer form */ + #define FICR_XOSC32MTRIM_OFFSET_Pos (16UL) /*!< Position of OFFSET field. */ + #define FICR_XOSC32MTRIM_OFFSET_Msk (0x3FFUL << FICR_XOSC32MTRIM_OFFSET_Pos) /*!< Bit mask of OFFSET field. */ + + +/* FICR_XOSC32KTRIM: XOSC32K capacitor selection trim values */ + #define FICR_XOSC32KTRIM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of XOSC32KTRIM register. */ + +/* SLOPE @Bits 0..8 : Slope trim factor on twos complement form */ + #define FICR_XOSC32KTRIM_SLOPE_Pos (0UL) /*!< Position of SLOPE field. */ + #define FICR_XOSC32KTRIM_SLOPE_Msk (0x1FFUL << FICR_XOSC32KTRIM_SLOPE_Pos) /*!< Bit mask of SLOPE field. */ + +/* OFFSET @Bits 16..25 : Offset trim factor on integer form */ + #define FICR_XOSC32KTRIM_OFFSET_Pos (16UL) /*!< Position of OFFSET field. */ + #define FICR_XOSC32KTRIM_OFFSET_Msk (0x3FFUL << FICR_XOSC32KTRIM_OFFSET_Pos) /*!< Bit mask of OFFSET field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ GLITCHDET ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ==================================================== Struct GLITCHDET ===================================================== */ +/** + * @brief Voltage glitch detectors + */ + typedef struct { /*!< GLITCHDET Structure */ + __IM uint32_t RESERVED[360]; + __IOM uint32_t CONFIG; /*!< (@ 0x000005A0) Configuration for glitch detector */ + } NRF_GLITCHDET_Type; /*!< Size = 1444 (0x5A4) */ + +/* GLITCHDET_CONFIG: Configuration for glitch detector */ + #define GLITCHDET_CONFIG_ResetValue (0x00000001UL) /*!< Reset value of CONFIG register. */ + +/* ENABLE @Bit 0 : Enable glitch detector */ + #define GLITCHDET_CONFIG_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define GLITCHDET_CONFIG_ENABLE_Msk (0x1UL << GLITCHDET_CONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define GLITCHDET_CONFIG_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define GLITCHDET_CONFIG_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define GLITCHDET_CONFIG_ENABLE_Disable (0x0UL) /*!< Disable glitch detector */ + #define GLITCHDET_CONFIG_ENABLE_Enable (0x1UL) /*!< Enable glitch detector */ + +/* MODE @Bit 4 : Glitch detector mode */ + #define GLITCHDET_CONFIG_MODE_Pos (4UL) /*!< Position of MODE field. */ + #define GLITCHDET_CONFIG_MODE_Msk (0x1UL << GLITCHDET_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ + #define GLITCHDET_CONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define GLITCHDET_CONFIG_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define GLITCHDET_CONFIG_MODE_HighPassFilter (0x0UL) /*!< High pass filter mode */ + #define GLITCHDET_CONFIG_MODE_CapDiv (0x1UL) /*!< Cap divider mode */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct GPIO ======================================================= */ +/** + * @brief GPIO Port + */ + typedef struct { /*!< GPIO Structure */ + __IOM uint32_t OUT; /*!< (@ 0x00000000) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000004) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x00000008) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x0000000C) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000010) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000014) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x00000018) DIR clear register */ + __IM uint32_t RESERVED; + __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that have met + the criteria set in the PIN_CNF[n].SENSE registers*/ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior and + LDETECT mode*/ + __IM uint32_t RESERVED1[22]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000080) Pin n configuration of GPIO pin */ + } NRF_GPIO_Type; /*!< Size = 256 (0x100) */ + +/* GPIO_OUT: Write GPIO port */ + #define GPIO_OUT_ResetValue (0x00000000UL) /*!< Reset value of OUT register. */ + +/* PIN0 @Bit 0 : Pin 0 */ + #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_OUT_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_OUT_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_OUT_PIN0_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN0_High (0x1UL) /*!< Pin driver is high */ + +/* PIN1 @Bit 1 : Pin 1 */ + #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_OUT_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_OUT_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_OUT_PIN1_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN1_High (0x1UL) /*!< Pin driver is high */ + +/* PIN2 @Bit 2 : Pin 2 */ + #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_OUT_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_OUT_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_OUT_PIN2_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN2_High (0x1UL) /*!< Pin driver is high */ + +/* PIN3 @Bit 3 : Pin 3 */ + #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_OUT_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_OUT_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_OUT_PIN3_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN3_High (0x1UL) /*!< Pin driver is high */ + +/* PIN4 @Bit 4 : Pin 4 */ + #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_OUT_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_OUT_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_OUT_PIN4_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN4_High (0x1UL) /*!< Pin driver is high */ + +/* PIN5 @Bit 5 : Pin 5 */ + #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_OUT_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_OUT_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_OUT_PIN5_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN5_High (0x1UL) /*!< Pin driver is high */ + +/* PIN6 @Bit 6 : Pin 6 */ + #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_OUT_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_OUT_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_OUT_PIN6_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN6_High (0x1UL) /*!< Pin driver is high */ + +/* PIN7 @Bit 7 : Pin 7 */ + #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_OUT_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_OUT_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_OUT_PIN7_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN7_High (0x1UL) /*!< Pin driver is high */ + +/* PIN8 @Bit 8 : Pin 8 */ + #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_OUT_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_OUT_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_OUT_PIN8_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN8_High (0x1UL) /*!< Pin driver is high */ + +/* PIN9 @Bit 9 : Pin 9 */ + #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_OUT_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_OUT_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_OUT_PIN9_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN9_High (0x1UL) /*!< Pin driver is high */ + +/* PIN10 @Bit 10 : Pin 10 */ + #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_OUT_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_OUT_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_OUT_PIN10_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN10_High (0x1UL) /*!< Pin driver is high */ + +/* PIN11 @Bit 11 : Pin 11 */ + #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_OUT_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_OUT_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_OUT_PIN11_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN11_High (0x1UL) /*!< Pin driver is high */ + +/* PIN12 @Bit 12 : Pin 12 */ + #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_OUT_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_OUT_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_OUT_PIN12_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN12_High (0x1UL) /*!< Pin driver is high */ + +/* PIN13 @Bit 13 : Pin 13 */ + #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_OUT_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_OUT_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_OUT_PIN13_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN13_High (0x1UL) /*!< Pin driver is high */ + +/* PIN14 @Bit 14 : Pin 14 */ + #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_OUT_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_OUT_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_OUT_PIN14_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN14_High (0x1UL) /*!< Pin driver is high */ + +/* PIN15 @Bit 15 : Pin 15 */ + #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_OUT_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_OUT_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_OUT_PIN15_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN15_High (0x1UL) /*!< Pin driver is high */ + +/* PIN16 @Bit 16 : Pin 16 */ + #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_OUT_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_OUT_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_OUT_PIN16_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN16_High (0x1UL) /*!< Pin driver is high */ + +/* PIN17 @Bit 17 : Pin 17 */ + #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_OUT_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_OUT_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_OUT_PIN17_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN17_High (0x1UL) /*!< Pin driver is high */ + +/* PIN18 @Bit 18 : Pin 18 */ + #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_OUT_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_OUT_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_OUT_PIN18_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN18_High (0x1UL) /*!< Pin driver is high */ + +/* PIN19 @Bit 19 : Pin 19 */ + #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_OUT_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_OUT_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_OUT_PIN19_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN19_High (0x1UL) /*!< Pin driver is high */ + +/* PIN20 @Bit 20 : Pin 20 */ + #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_OUT_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_OUT_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_OUT_PIN20_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN20_High (0x1UL) /*!< Pin driver is high */ + +/* PIN21 @Bit 21 : Pin 21 */ + #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_OUT_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_OUT_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_OUT_PIN21_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN21_High (0x1UL) /*!< Pin driver is high */ + +/* PIN22 @Bit 22 : Pin 22 */ + #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_OUT_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_OUT_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_OUT_PIN22_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN22_High (0x1UL) /*!< Pin driver is high */ + +/* PIN23 @Bit 23 : Pin 23 */ + #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_OUT_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_OUT_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_OUT_PIN23_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN23_High (0x1UL) /*!< Pin driver is high */ + +/* PIN24 @Bit 24 : Pin 24 */ + #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_OUT_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_OUT_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_OUT_PIN24_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN24_High (0x1UL) /*!< Pin driver is high */ + +/* PIN25 @Bit 25 : Pin 25 */ + #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_OUT_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_OUT_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_OUT_PIN25_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN25_High (0x1UL) /*!< Pin driver is high */ + +/* PIN26 @Bit 26 : Pin 26 */ + #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_OUT_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_OUT_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_OUT_PIN26_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN26_High (0x1UL) /*!< Pin driver is high */ + +/* PIN27 @Bit 27 : Pin 27 */ + #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_OUT_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_OUT_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_OUT_PIN27_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN27_High (0x1UL) /*!< Pin driver is high */ + +/* PIN28 @Bit 28 : Pin 28 */ + #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_OUT_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_OUT_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_OUT_PIN28_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN28_High (0x1UL) /*!< Pin driver is high */ + +/* PIN29 @Bit 29 : Pin 29 */ + #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_OUT_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_OUT_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_OUT_PIN29_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN29_High (0x1UL) /*!< Pin driver is high */ + +/* PIN30 @Bit 30 : Pin 30 */ + #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_OUT_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_OUT_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_OUT_PIN30_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN30_High (0x1UL) /*!< Pin driver is high */ + +/* PIN31 @Bit 31 : Pin 31 */ + #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_OUT_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_OUT_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_OUT_PIN31_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN31_High (0x1UL) /*!< Pin driver is high */ + + +/* GPIO_OUTSET: Set individual bits in GPIO port */ + #define GPIO_OUTSET_ResetValue (0x00000000UL) /*!< Reset value of OUTSET register. */ + +/* PIN0 @Bit 0 : Pin 0 */ + #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_OUTSET_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_OUTSET_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_OUTSET_PIN0_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN0_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN1 @Bit 1 : Pin 1 */ + #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_OUTSET_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_OUTSET_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_OUTSET_PIN1_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN1_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN2 @Bit 2 : Pin 2 */ + #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_OUTSET_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_OUTSET_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_OUTSET_PIN2_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN2_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN3 @Bit 3 : Pin 3 */ + #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_OUTSET_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_OUTSET_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_OUTSET_PIN3_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN3_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN4 @Bit 4 : Pin 4 */ + #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_OUTSET_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_OUTSET_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_OUTSET_PIN4_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN4_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN5 @Bit 5 : Pin 5 */ + #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_OUTSET_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_OUTSET_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_OUTSET_PIN5_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN5_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN6 @Bit 6 : Pin 6 */ + #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_OUTSET_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_OUTSET_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_OUTSET_PIN6_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN6_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN7 @Bit 7 : Pin 7 */ + #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_OUTSET_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_OUTSET_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_OUTSET_PIN7_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN7_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN8 @Bit 8 : Pin 8 */ + #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_OUTSET_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_OUTSET_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_OUTSET_PIN8_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN8_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN9 @Bit 9 : Pin 9 */ + #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_OUTSET_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_OUTSET_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_OUTSET_PIN9_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN9_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN10 @Bit 10 : Pin 10 */ + #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_OUTSET_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_OUTSET_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_OUTSET_PIN10_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN10_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN11 @Bit 11 : Pin 11 */ + #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_OUTSET_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_OUTSET_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_OUTSET_PIN11_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN11_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN12 @Bit 12 : Pin 12 */ + #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_OUTSET_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_OUTSET_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_OUTSET_PIN12_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN12_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN13 @Bit 13 : Pin 13 */ + #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_OUTSET_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_OUTSET_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_OUTSET_PIN13_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN13_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN14 @Bit 14 : Pin 14 */ + #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_OUTSET_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_OUTSET_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_OUTSET_PIN14_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN14_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN15 @Bit 15 : Pin 15 */ + #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_OUTSET_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_OUTSET_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_OUTSET_PIN15_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN15_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN16 @Bit 16 : Pin 16 */ + #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_OUTSET_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_OUTSET_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_OUTSET_PIN16_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN16_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN17 @Bit 17 : Pin 17 */ + #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_OUTSET_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_OUTSET_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_OUTSET_PIN17_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN17_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN18 @Bit 18 : Pin 18 */ + #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_OUTSET_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_OUTSET_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_OUTSET_PIN18_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN18_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN19 @Bit 19 : Pin 19 */ + #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_OUTSET_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_OUTSET_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_OUTSET_PIN19_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN19_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN20 @Bit 20 : Pin 20 */ + #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_OUTSET_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_OUTSET_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_OUTSET_PIN20_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN20_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN21 @Bit 21 : Pin 21 */ + #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_OUTSET_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_OUTSET_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_OUTSET_PIN21_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN21_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN22 @Bit 22 : Pin 22 */ + #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_OUTSET_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_OUTSET_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_OUTSET_PIN22_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN22_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN23 @Bit 23 : Pin 23 */ + #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_OUTSET_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_OUTSET_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_OUTSET_PIN23_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN23_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN24 @Bit 24 : Pin 24 */ + #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_OUTSET_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_OUTSET_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_OUTSET_PIN24_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN24_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN25 @Bit 25 : Pin 25 */ + #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_OUTSET_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_OUTSET_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_OUTSET_PIN25_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN25_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN26 @Bit 26 : Pin 26 */ + #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_OUTSET_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_OUTSET_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_OUTSET_PIN26_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN26_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN27 @Bit 27 : Pin 27 */ + #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_OUTSET_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_OUTSET_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_OUTSET_PIN27_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN27_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN28 @Bit 28 : Pin 28 */ + #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_OUTSET_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_OUTSET_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_OUTSET_PIN28_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN28_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN29 @Bit 29 : Pin 29 */ + #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_OUTSET_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_OUTSET_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_OUTSET_PIN29_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN29_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN30 @Bit 30 : Pin 30 */ + #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_OUTSET_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_OUTSET_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_OUTSET_PIN30_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN30_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN31 @Bit 31 : Pin 31 */ + #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_OUTSET_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_OUTSET_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_OUTSET_PIN31_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN31_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + + +/* GPIO_OUTCLR: Clear individual bits in GPIO port */ + #define GPIO_OUTCLR_ResetValue (0x00000000UL) /*!< Reset value of OUTCLR register. */ + +/* PIN0 @Bit 0 : Pin 0 */ + #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_OUTCLR_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_OUTCLR_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_OUTCLR_PIN0_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN0_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN1 @Bit 1 : Pin 1 */ + #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_OUTCLR_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_OUTCLR_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_OUTCLR_PIN1_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN1_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN2 @Bit 2 : Pin 2 */ + #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_OUTCLR_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_OUTCLR_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_OUTCLR_PIN2_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN2_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN3 @Bit 3 : Pin 3 */ + #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_OUTCLR_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_OUTCLR_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_OUTCLR_PIN3_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN3_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN4 @Bit 4 : Pin 4 */ + #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_OUTCLR_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_OUTCLR_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_OUTCLR_PIN4_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN4_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN5 @Bit 5 : Pin 5 */ + #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_OUTCLR_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_OUTCLR_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_OUTCLR_PIN5_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN5_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN6 @Bit 6 : Pin 6 */ + #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_OUTCLR_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_OUTCLR_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_OUTCLR_PIN6_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN6_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN7 @Bit 7 : Pin 7 */ + #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_OUTCLR_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_OUTCLR_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_OUTCLR_PIN7_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN7_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN8 @Bit 8 : Pin 8 */ + #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_OUTCLR_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_OUTCLR_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_OUTCLR_PIN8_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN8_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN9 @Bit 9 : Pin 9 */ + #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_OUTCLR_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_OUTCLR_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_OUTCLR_PIN9_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN9_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN10 @Bit 10 : Pin 10 */ + #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_OUTCLR_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_OUTCLR_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_OUTCLR_PIN10_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN10_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN11 @Bit 11 : Pin 11 */ + #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_OUTCLR_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_OUTCLR_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_OUTCLR_PIN11_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN11_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN12 @Bit 12 : Pin 12 */ + #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_OUTCLR_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_OUTCLR_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_OUTCLR_PIN12_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN12_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN13 @Bit 13 : Pin 13 */ + #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_OUTCLR_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_OUTCLR_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_OUTCLR_PIN13_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN13_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN14 @Bit 14 : Pin 14 */ + #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_OUTCLR_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_OUTCLR_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_OUTCLR_PIN14_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN14_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN15 @Bit 15 : Pin 15 */ + #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_OUTCLR_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_OUTCLR_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_OUTCLR_PIN15_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN15_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN16 @Bit 16 : Pin 16 */ + #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_OUTCLR_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_OUTCLR_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_OUTCLR_PIN16_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN16_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN17 @Bit 17 : Pin 17 */ + #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_OUTCLR_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_OUTCLR_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_OUTCLR_PIN17_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN17_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN18 @Bit 18 : Pin 18 */ + #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_OUTCLR_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_OUTCLR_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_OUTCLR_PIN18_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN18_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN19 @Bit 19 : Pin 19 */ + #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_OUTCLR_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_OUTCLR_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_OUTCLR_PIN19_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN19_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN20 @Bit 20 : Pin 20 */ + #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_OUTCLR_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_OUTCLR_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_OUTCLR_PIN20_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN20_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN21 @Bit 21 : Pin 21 */ + #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_OUTCLR_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_OUTCLR_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_OUTCLR_PIN21_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN21_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN22 @Bit 22 : Pin 22 */ + #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_OUTCLR_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_OUTCLR_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_OUTCLR_PIN22_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN22_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN23 @Bit 23 : Pin 23 */ + #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_OUTCLR_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_OUTCLR_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_OUTCLR_PIN23_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN23_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN24 @Bit 24 : Pin 24 */ + #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_OUTCLR_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_OUTCLR_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_OUTCLR_PIN24_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN24_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN25 @Bit 25 : Pin 25 */ + #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_OUTCLR_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_OUTCLR_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_OUTCLR_PIN25_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN25_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN26 @Bit 26 : Pin 26 */ + #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_OUTCLR_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_OUTCLR_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_OUTCLR_PIN26_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN26_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN27 @Bit 27 : Pin 27 */ + #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_OUTCLR_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_OUTCLR_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_OUTCLR_PIN27_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN27_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN28 @Bit 28 : Pin 28 */ + #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_OUTCLR_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_OUTCLR_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_OUTCLR_PIN28_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN28_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN29 @Bit 29 : Pin 29 */ + #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_OUTCLR_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_OUTCLR_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_OUTCLR_PIN29_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN29_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN30 @Bit 30 : Pin 30 */ + #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_OUTCLR_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_OUTCLR_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_OUTCLR_PIN30_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN30_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN31 @Bit 31 : Pin 31 */ + #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_OUTCLR_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_OUTCLR_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_OUTCLR_PIN31_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN31_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + + +/* GPIO_IN: Read GPIO port */ + #define GPIO_IN_ResetValue (0x00000000UL) /*!< Reset value of IN register. */ + +/* PIN0 @Bit 0 : Pin 0 */ + #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_IN_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_IN_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_IN_PIN0_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN0_High (0x1UL) /*!< Pin input is high */ + +/* PIN1 @Bit 1 : Pin 1 */ + #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_IN_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_IN_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_IN_PIN1_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN1_High (0x1UL) /*!< Pin input is high */ + +/* PIN2 @Bit 2 : Pin 2 */ + #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_IN_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_IN_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_IN_PIN2_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN2_High (0x1UL) /*!< Pin input is high */ + +/* PIN3 @Bit 3 : Pin 3 */ + #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_IN_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_IN_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_IN_PIN3_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN3_High (0x1UL) /*!< Pin input is high */ + +/* PIN4 @Bit 4 : Pin 4 */ + #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_IN_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_IN_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_IN_PIN4_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN4_High (0x1UL) /*!< Pin input is high */ + +/* PIN5 @Bit 5 : Pin 5 */ + #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_IN_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_IN_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_IN_PIN5_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN5_High (0x1UL) /*!< Pin input is high */ + +/* PIN6 @Bit 6 : Pin 6 */ + #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_IN_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_IN_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_IN_PIN6_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN6_High (0x1UL) /*!< Pin input is high */ + +/* PIN7 @Bit 7 : Pin 7 */ + #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_IN_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_IN_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_IN_PIN7_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN7_High (0x1UL) /*!< Pin input is high */ + +/* PIN8 @Bit 8 : Pin 8 */ + #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_IN_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_IN_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_IN_PIN8_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN8_High (0x1UL) /*!< Pin input is high */ + +/* PIN9 @Bit 9 : Pin 9 */ + #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_IN_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_IN_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_IN_PIN9_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN9_High (0x1UL) /*!< Pin input is high */ + +/* PIN10 @Bit 10 : Pin 10 */ + #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_IN_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_IN_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_IN_PIN10_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN10_High (0x1UL) /*!< Pin input is high */ + +/* PIN11 @Bit 11 : Pin 11 */ + #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_IN_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_IN_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_IN_PIN11_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN11_High (0x1UL) /*!< Pin input is high */ + +/* PIN12 @Bit 12 : Pin 12 */ + #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_IN_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_IN_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_IN_PIN12_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN12_High (0x1UL) /*!< Pin input is high */ + +/* PIN13 @Bit 13 : Pin 13 */ + #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_IN_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_IN_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_IN_PIN13_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN13_High (0x1UL) /*!< Pin input is high */ + +/* PIN14 @Bit 14 : Pin 14 */ + #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_IN_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_IN_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_IN_PIN14_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN14_High (0x1UL) /*!< Pin input is high */ + +/* PIN15 @Bit 15 : Pin 15 */ + #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_IN_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_IN_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_IN_PIN15_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN15_High (0x1UL) /*!< Pin input is high */ + +/* PIN16 @Bit 16 : Pin 16 */ + #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_IN_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_IN_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_IN_PIN16_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN16_High (0x1UL) /*!< Pin input is high */ + +/* PIN17 @Bit 17 : Pin 17 */ + #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_IN_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_IN_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_IN_PIN17_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN17_High (0x1UL) /*!< Pin input is high */ + +/* PIN18 @Bit 18 : Pin 18 */ + #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_IN_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_IN_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_IN_PIN18_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN18_High (0x1UL) /*!< Pin input is high */ + +/* PIN19 @Bit 19 : Pin 19 */ + #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_IN_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_IN_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_IN_PIN19_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN19_High (0x1UL) /*!< Pin input is high */ + +/* PIN20 @Bit 20 : Pin 20 */ + #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_IN_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_IN_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_IN_PIN20_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN20_High (0x1UL) /*!< Pin input is high */ + +/* PIN21 @Bit 21 : Pin 21 */ + #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_IN_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_IN_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_IN_PIN21_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN21_High (0x1UL) /*!< Pin input is high */ + +/* PIN22 @Bit 22 : Pin 22 */ + #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_IN_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_IN_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_IN_PIN22_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN22_High (0x1UL) /*!< Pin input is high */ + +/* PIN23 @Bit 23 : Pin 23 */ + #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_IN_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_IN_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_IN_PIN23_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN23_High (0x1UL) /*!< Pin input is high */ + +/* PIN24 @Bit 24 : Pin 24 */ + #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_IN_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_IN_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_IN_PIN24_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN24_High (0x1UL) /*!< Pin input is high */ + +/* PIN25 @Bit 25 : Pin 25 */ + #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_IN_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_IN_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_IN_PIN25_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN25_High (0x1UL) /*!< Pin input is high */ + +/* PIN26 @Bit 26 : Pin 26 */ + #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_IN_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_IN_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_IN_PIN26_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN26_High (0x1UL) /*!< Pin input is high */ + +/* PIN27 @Bit 27 : Pin 27 */ + #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_IN_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_IN_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_IN_PIN27_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN27_High (0x1UL) /*!< Pin input is high */ + +/* PIN28 @Bit 28 : Pin 28 */ + #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_IN_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_IN_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_IN_PIN28_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN28_High (0x1UL) /*!< Pin input is high */ + +/* PIN29 @Bit 29 : Pin 29 */ + #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_IN_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_IN_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_IN_PIN29_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN29_High (0x1UL) /*!< Pin input is high */ + +/* PIN30 @Bit 30 : Pin 30 */ + #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_IN_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_IN_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_IN_PIN30_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN30_High (0x1UL) /*!< Pin input is high */ + +/* PIN31 @Bit 31 : Pin 31 */ + #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_IN_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_IN_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_IN_PIN31_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN31_High (0x1UL) /*!< Pin input is high */ + + +/* GPIO_DIR: Direction of GPIO pins */ + #define GPIO_DIR_ResetValue (0x00000000UL) /*!< Reset value of DIR register. */ + +/* PIN0 @Bit 0 : Pin 0 */ + #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_DIR_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_DIR_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_DIR_PIN0_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN0_Output (0x1UL) /*!< Pin set as output */ + +/* PIN1 @Bit 1 : Pin 1 */ + #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_DIR_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_DIR_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_DIR_PIN1_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN1_Output (0x1UL) /*!< Pin set as output */ + +/* PIN2 @Bit 2 : Pin 2 */ + #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_DIR_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_DIR_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_DIR_PIN2_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN2_Output (0x1UL) /*!< Pin set as output */ + +/* PIN3 @Bit 3 : Pin 3 */ + #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_DIR_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_DIR_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_DIR_PIN3_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN3_Output (0x1UL) /*!< Pin set as output */ + +/* PIN4 @Bit 4 : Pin 4 */ + #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_DIR_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_DIR_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_DIR_PIN4_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN4_Output (0x1UL) /*!< Pin set as output */ + +/* PIN5 @Bit 5 : Pin 5 */ + #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_DIR_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_DIR_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_DIR_PIN5_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN5_Output (0x1UL) /*!< Pin set as output */ + +/* PIN6 @Bit 6 : Pin 6 */ + #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_DIR_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_DIR_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_DIR_PIN6_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN6_Output (0x1UL) /*!< Pin set as output */ + +/* PIN7 @Bit 7 : Pin 7 */ + #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_DIR_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_DIR_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_DIR_PIN7_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN7_Output (0x1UL) /*!< Pin set as output */ + +/* PIN8 @Bit 8 : Pin 8 */ + #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_DIR_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_DIR_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_DIR_PIN8_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN8_Output (0x1UL) /*!< Pin set as output */ + +/* PIN9 @Bit 9 : Pin 9 */ + #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_DIR_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_DIR_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_DIR_PIN9_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN9_Output (0x1UL) /*!< Pin set as output */ + +/* PIN10 @Bit 10 : Pin 10 */ + #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_DIR_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_DIR_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_DIR_PIN10_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN10_Output (0x1UL) /*!< Pin set as output */ + +/* PIN11 @Bit 11 : Pin 11 */ + #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_DIR_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_DIR_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_DIR_PIN11_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN11_Output (0x1UL) /*!< Pin set as output */ + +/* PIN12 @Bit 12 : Pin 12 */ + #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_DIR_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_DIR_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_DIR_PIN12_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN12_Output (0x1UL) /*!< Pin set as output */ + +/* PIN13 @Bit 13 : Pin 13 */ + #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_DIR_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_DIR_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_DIR_PIN13_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN13_Output (0x1UL) /*!< Pin set as output */ + +/* PIN14 @Bit 14 : Pin 14 */ + #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_DIR_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_DIR_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_DIR_PIN14_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN14_Output (0x1UL) /*!< Pin set as output */ + +/* PIN15 @Bit 15 : Pin 15 */ + #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_DIR_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_DIR_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_DIR_PIN15_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN15_Output (0x1UL) /*!< Pin set as output */ + +/* PIN16 @Bit 16 : Pin 16 */ + #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_DIR_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_DIR_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_DIR_PIN16_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN16_Output (0x1UL) /*!< Pin set as output */ + +/* PIN17 @Bit 17 : Pin 17 */ + #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_DIR_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_DIR_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_DIR_PIN17_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN17_Output (0x1UL) /*!< Pin set as output */ + +/* PIN18 @Bit 18 : Pin 18 */ + #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_DIR_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_DIR_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_DIR_PIN18_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN18_Output (0x1UL) /*!< Pin set as output */ + +/* PIN19 @Bit 19 : Pin 19 */ + #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_DIR_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_DIR_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_DIR_PIN19_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN19_Output (0x1UL) /*!< Pin set as output */ + +/* PIN20 @Bit 20 : Pin 20 */ + #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_DIR_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_DIR_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_DIR_PIN20_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN20_Output (0x1UL) /*!< Pin set as output */ + +/* PIN21 @Bit 21 : Pin 21 */ + #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_DIR_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_DIR_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_DIR_PIN21_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN21_Output (0x1UL) /*!< Pin set as output */ + +/* PIN22 @Bit 22 : Pin 22 */ + #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_DIR_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_DIR_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_DIR_PIN22_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN22_Output (0x1UL) /*!< Pin set as output */ + +/* PIN23 @Bit 23 : Pin 23 */ + #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_DIR_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_DIR_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_DIR_PIN23_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN23_Output (0x1UL) /*!< Pin set as output */ + +/* PIN24 @Bit 24 : Pin 24 */ + #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_DIR_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_DIR_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_DIR_PIN24_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN24_Output (0x1UL) /*!< Pin set as output */ + +/* PIN25 @Bit 25 : Pin 25 */ + #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_DIR_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_DIR_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_DIR_PIN25_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN25_Output (0x1UL) /*!< Pin set as output */ + +/* PIN26 @Bit 26 : Pin 26 */ + #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_DIR_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_DIR_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_DIR_PIN26_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN26_Output (0x1UL) /*!< Pin set as output */ + +/* PIN27 @Bit 27 : Pin 27 */ + #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_DIR_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_DIR_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_DIR_PIN27_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN27_Output (0x1UL) /*!< Pin set as output */ + +/* PIN28 @Bit 28 : Pin 28 */ + #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_DIR_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_DIR_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_DIR_PIN28_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN28_Output (0x1UL) /*!< Pin set as output */ + +/* PIN29 @Bit 29 : Pin 29 */ + #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_DIR_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_DIR_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_DIR_PIN29_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN29_Output (0x1UL) /*!< Pin set as output */ + +/* PIN30 @Bit 30 : Pin 30 */ + #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_DIR_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_DIR_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_DIR_PIN30_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN30_Output (0x1UL) /*!< Pin set as output */ + +/* PIN31 @Bit 31 : Pin 31 */ + #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_DIR_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_DIR_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_DIR_PIN31_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN31_Output (0x1UL) /*!< Pin set as output */ + + +/* GPIO_DIRSET: DIR set register */ + #define GPIO_DIRSET_ResetValue (0x00000000UL) /*!< Reset value of DIRSET register. */ + +/* PIN0 @Bit 0 : Set as output pin 0 */ + #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_DIRSET_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_DIRSET_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_DIRSET_PIN0_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN0_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN1 @Bit 1 : Set as output pin 1 */ + #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_DIRSET_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_DIRSET_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_DIRSET_PIN1_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN1_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN2 @Bit 2 : Set as output pin 2 */ + #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_DIRSET_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_DIRSET_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_DIRSET_PIN2_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN2_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN3 @Bit 3 : Set as output pin 3 */ + #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_DIRSET_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_DIRSET_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_DIRSET_PIN3_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN3_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN4 @Bit 4 : Set as output pin 4 */ + #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_DIRSET_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_DIRSET_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_DIRSET_PIN4_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN4_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN5 @Bit 5 : Set as output pin 5 */ + #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_DIRSET_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_DIRSET_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_DIRSET_PIN5_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN5_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN6 @Bit 6 : Set as output pin 6 */ + #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_DIRSET_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_DIRSET_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_DIRSET_PIN6_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN6_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN7 @Bit 7 : Set as output pin 7 */ + #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_DIRSET_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_DIRSET_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_DIRSET_PIN7_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN7_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN8 @Bit 8 : Set as output pin 8 */ + #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_DIRSET_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_DIRSET_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_DIRSET_PIN8_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN8_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN9 @Bit 9 : Set as output pin 9 */ + #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_DIRSET_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_DIRSET_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_DIRSET_PIN9_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN9_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN10 @Bit 10 : Set as output pin 10 */ + #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_DIRSET_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_DIRSET_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_DIRSET_PIN10_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN10_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN11 @Bit 11 : Set as output pin 11 */ + #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_DIRSET_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_DIRSET_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_DIRSET_PIN11_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN11_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN12 @Bit 12 : Set as output pin 12 */ + #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_DIRSET_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_DIRSET_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_DIRSET_PIN12_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN12_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN13 @Bit 13 : Set as output pin 13 */ + #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_DIRSET_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_DIRSET_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_DIRSET_PIN13_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN13_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN14 @Bit 14 : Set as output pin 14 */ + #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_DIRSET_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_DIRSET_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_DIRSET_PIN14_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN14_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN15 @Bit 15 : Set as output pin 15 */ + #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_DIRSET_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_DIRSET_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_DIRSET_PIN15_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN15_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN16 @Bit 16 : Set as output pin 16 */ + #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_DIRSET_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_DIRSET_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_DIRSET_PIN16_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN16_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN17 @Bit 17 : Set as output pin 17 */ + #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_DIRSET_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_DIRSET_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_DIRSET_PIN17_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN17_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN18 @Bit 18 : Set as output pin 18 */ + #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_DIRSET_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_DIRSET_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_DIRSET_PIN18_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN18_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN19 @Bit 19 : Set as output pin 19 */ + #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_DIRSET_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_DIRSET_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_DIRSET_PIN19_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN19_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN20 @Bit 20 : Set as output pin 20 */ + #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_DIRSET_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_DIRSET_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_DIRSET_PIN20_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN20_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN21 @Bit 21 : Set as output pin 21 */ + #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_DIRSET_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_DIRSET_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_DIRSET_PIN21_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN21_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN22 @Bit 22 : Set as output pin 22 */ + #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_DIRSET_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_DIRSET_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_DIRSET_PIN22_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN22_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN23 @Bit 23 : Set as output pin 23 */ + #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_DIRSET_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_DIRSET_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_DIRSET_PIN23_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN23_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN24 @Bit 24 : Set as output pin 24 */ + #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_DIRSET_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_DIRSET_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_DIRSET_PIN24_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN24_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN25 @Bit 25 : Set as output pin 25 */ + #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_DIRSET_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_DIRSET_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_DIRSET_PIN25_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN25_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN26 @Bit 26 : Set as output pin 26 */ + #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_DIRSET_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_DIRSET_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_DIRSET_PIN26_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN26_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN27 @Bit 27 : Set as output pin 27 */ + #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_DIRSET_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_DIRSET_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_DIRSET_PIN27_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN27_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN28 @Bit 28 : Set as output pin 28 */ + #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_DIRSET_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_DIRSET_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_DIRSET_PIN28_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN28_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN29 @Bit 29 : Set as output pin 29 */ + #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_DIRSET_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_DIRSET_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_DIRSET_PIN29_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN29_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN30 @Bit 30 : Set as output pin 30 */ + #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_DIRSET_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_DIRSET_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_DIRSET_PIN30_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN30_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN31 @Bit 31 : Set as output pin 31 */ + #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_DIRSET_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_DIRSET_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_DIRSET_PIN31_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN31_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + + +/* GPIO_DIRCLR: DIR clear register */ + #define GPIO_DIRCLR_ResetValue (0x00000000UL) /*!< Reset value of DIRCLR register. */ + +/* PIN0 @Bit 0 : Set as input pin 0 */ + #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_DIRCLR_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_DIRCLR_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_DIRCLR_PIN0_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN0_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN1 @Bit 1 : Set as input pin 1 */ + #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_DIRCLR_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_DIRCLR_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_DIRCLR_PIN1_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN1_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN2 @Bit 2 : Set as input pin 2 */ + #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_DIRCLR_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_DIRCLR_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_DIRCLR_PIN2_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN2_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN3 @Bit 3 : Set as input pin 3 */ + #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_DIRCLR_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_DIRCLR_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_DIRCLR_PIN3_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN3_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN4 @Bit 4 : Set as input pin 4 */ + #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_DIRCLR_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_DIRCLR_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_DIRCLR_PIN4_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN4_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN5 @Bit 5 : Set as input pin 5 */ + #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_DIRCLR_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_DIRCLR_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_DIRCLR_PIN5_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN5_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN6 @Bit 6 : Set as input pin 6 */ + #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_DIRCLR_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_DIRCLR_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_DIRCLR_PIN6_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN6_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN7 @Bit 7 : Set as input pin 7 */ + #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_DIRCLR_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_DIRCLR_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_DIRCLR_PIN7_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN7_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN8 @Bit 8 : Set as input pin 8 */ + #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_DIRCLR_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_DIRCLR_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_DIRCLR_PIN8_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN8_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN9 @Bit 9 : Set as input pin 9 */ + #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_DIRCLR_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_DIRCLR_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_DIRCLR_PIN9_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN9_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN10 @Bit 10 : Set as input pin 10 */ + #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_DIRCLR_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_DIRCLR_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_DIRCLR_PIN10_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN10_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN11 @Bit 11 : Set as input pin 11 */ + #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_DIRCLR_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_DIRCLR_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_DIRCLR_PIN11_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN11_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN12 @Bit 12 : Set as input pin 12 */ + #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_DIRCLR_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_DIRCLR_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_DIRCLR_PIN12_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN12_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN13 @Bit 13 : Set as input pin 13 */ + #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_DIRCLR_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_DIRCLR_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_DIRCLR_PIN13_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN13_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN14 @Bit 14 : Set as input pin 14 */ + #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_DIRCLR_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_DIRCLR_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_DIRCLR_PIN14_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN14_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN15 @Bit 15 : Set as input pin 15 */ + #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_DIRCLR_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_DIRCLR_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_DIRCLR_PIN15_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN15_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN16 @Bit 16 : Set as input pin 16 */ + #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_DIRCLR_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_DIRCLR_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_DIRCLR_PIN16_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN16_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN17 @Bit 17 : Set as input pin 17 */ + #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_DIRCLR_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_DIRCLR_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_DIRCLR_PIN17_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN17_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN18 @Bit 18 : Set as input pin 18 */ + #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_DIRCLR_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_DIRCLR_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_DIRCLR_PIN18_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN18_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN19 @Bit 19 : Set as input pin 19 */ + #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_DIRCLR_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_DIRCLR_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_DIRCLR_PIN19_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN19_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN20 @Bit 20 : Set as input pin 20 */ + #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_DIRCLR_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_DIRCLR_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_DIRCLR_PIN20_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN20_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN21 @Bit 21 : Set as input pin 21 */ + #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_DIRCLR_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_DIRCLR_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_DIRCLR_PIN21_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN21_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN22 @Bit 22 : Set as input pin 22 */ + #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_DIRCLR_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_DIRCLR_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_DIRCLR_PIN22_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN22_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN23 @Bit 23 : Set as input pin 23 */ + #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_DIRCLR_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_DIRCLR_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_DIRCLR_PIN23_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN23_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN24 @Bit 24 : Set as input pin 24 */ + #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_DIRCLR_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_DIRCLR_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_DIRCLR_PIN24_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN24_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN25 @Bit 25 : Set as input pin 25 */ + #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_DIRCLR_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_DIRCLR_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_DIRCLR_PIN25_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN25_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN26 @Bit 26 : Set as input pin 26 */ + #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_DIRCLR_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_DIRCLR_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_DIRCLR_PIN26_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN26_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN27 @Bit 27 : Set as input pin 27 */ + #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_DIRCLR_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_DIRCLR_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_DIRCLR_PIN27_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN27_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN28 @Bit 28 : Set as input pin 28 */ + #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_DIRCLR_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_DIRCLR_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_DIRCLR_PIN28_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN28_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN29 @Bit 29 : Set as input pin 29 */ + #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_DIRCLR_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_DIRCLR_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_DIRCLR_PIN29_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN29_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN30 @Bit 30 : Set as input pin 30 */ + #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_DIRCLR_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_DIRCLR_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_DIRCLR_PIN30_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN30_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN31 @Bit 31 : Set as input pin 31 */ + #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_DIRCLR_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_DIRCLR_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_DIRCLR_PIN31_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN31_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + + +/* GPIO_LATCH: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + #define GPIO_LATCH_ResetValue (0x00000000UL) /*!< Reset value of LATCH register. */ + +/* PIN0 @Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_LATCH_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_LATCH_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_LATCH_PIN0_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN0_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN1 @Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_LATCH_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_LATCH_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_LATCH_PIN1_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN1_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN2 @Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_LATCH_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_LATCH_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_LATCH_PIN2_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN2_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN3 @Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_LATCH_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_LATCH_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_LATCH_PIN3_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN3_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN4 @Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_LATCH_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_LATCH_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_LATCH_PIN4_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN4_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN5 @Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_LATCH_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_LATCH_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_LATCH_PIN5_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN5_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN6 @Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_LATCH_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_LATCH_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_LATCH_PIN6_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN6_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN7 @Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_LATCH_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_LATCH_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_LATCH_PIN7_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN7_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN8 @Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_LATCH_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_LATCH_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_LATCH_PIN8_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN8_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN9 @Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_LATCH_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_LATCH_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_LATCH_PIN9_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN9_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN10 @Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_LATCH_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_LATCH_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_LATCH_PIN10_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN10_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN11 @Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_LATCH_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_LATCH_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_LATCH_PIN11_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN11_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN12 @Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_LATCH_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_LATCH_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_LATCH_PIN12_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN12_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN13 @Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_LATCH_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_LATCH_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_LATCH_PIN13_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN13_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN14 @Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_LATCH_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_LATCH_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_LATCH_PIN14_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN14_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN15 @Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_LATCH_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_LATCH_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_LATCH_PIN15_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN15_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN16 @Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_LATCH_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_LATCH_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_LATCH_PIN16_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN16_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN17 @Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_LATCH_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_LATCH_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_LATCH_PIN17_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN17_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN18 @Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_LATCH_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_LATCH_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_LATCH_PIN18_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN18_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN19 @Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_LATCH_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_LATCH_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_LATCH_PIN19_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN19_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN20 @Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_LATCH_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_LATCH_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_LATCH_PIN20_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN20_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN21 @Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_LATCH_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_LATCH_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_LATCH_PIN21_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN21_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN22 @Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_LATCH_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_LATCH_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_LATCH_PIN22_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN22_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN23 @Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_LATCH_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_LATCH_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_LATCH_PIN23_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN23_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN24 @Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_LATCH_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_LATCH_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_LATCH_PIN24_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN24_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN25 @Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_LATCH_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_LATCH_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_LATCH_PIN25_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN25_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN26 @Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_LATCH_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_LATCH_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_LATCH_PIN26_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN26_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN27 @Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_LATCH_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_LATCH_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_LATCH_PIN27_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN27_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN28 @Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_LATCH_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_LATCH_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_LATCH_PIN28_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN28_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN29 @Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_LATCH_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_LATCH_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_LATCH_PIN29_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN29_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN30 @Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_LATCH_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_LATCH_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_LATCH_PIN30_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN30_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN31 @Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_LATCH_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_LATCH_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_LATCH_PIN31_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN31_Latched (0x1UL) /*!< Criteria has been met */ + + +/* GPIO_DETECTMODE: Select between default DETECT signal behavior and LDETECT mode */ + #define GPIO_DETECTMODE_ResetValue (0x00000000UL) /*!< Reset value of DETECTMODE register. */ + +/* DETECTMODE @Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ + #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ + #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ + #define GPIO_DETECTMODE_DETECTMODE_Min (0x0UL) /*!< Min enumerator value of DETECTMODE field. */ + #define GPIO_DETECTMODE_DETECTMODE_Max (0x1UL) /*!< Max enumerator value of DETECTMODE field. */ + #define GPIO_DETECTMODE_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals */ + #define GPIO_DETECTMODE_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior */ + + +/* GPIO_PIN_CNF: Pin n configuration of GPIO pin */ + #define GPIO_PIN_CNF_MaxCount (32UL) /*!< Max size of PIN_CNF[32] array. */ + #define GPIO_PIN_CNF_MaxIndex (31UL) /*!< Max index of PIN_CNF[32] array. */ + #define GPIO_PIN_CNF_MinIndex (0UL) /*!< Min index of PIN_CNF[32] array. */ + #define GPIO_PIN_CNF_ResetValue (0x00000002UL) /*!< Reset value of PIN_CNF[32] register. */ + +/* DIR @Bit 0 : Pin direction. Same physical register as DIR register */ + #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ + #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ + #define GPIO_PIN_CNF_DIR_Min (0x0UL) /*!< Min enumerator value of DIR field. */ + #define GPIO_PIN_CNF_DIR_Max (0x1UL) /*!< Max enumerator value of DIR field. */ + #define GPIO_PIN_CNF_DIR_Input (0x0UL) /*!< Configure pin as an input pin */ + #define GPIO_PIN_CNF_DIR_Output (0x1UL) /*!< Configure pin as an output pin */ + +/* INPUT @Bit 1 : Connect or disconnect input buffer */ + #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ + #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ + #define GPIO_PIN_CNF_INPUT_Min (0x0UL) /*!< Min enumerator value of INPUT field. */ + #define GPIO_PIN_CNF_INPUT_Max (0x1UL) /*!< Max enumerator value of INPUT field. */ + #define GPIO_PIN_CNF_INPUT_Connect (0x0UL) /*!< Connect input buffer */ + #define GPIO_PIN_CNF_INPUT_Disconnect (0x1UL) /*!< Disconnect input buffer */ + +/* PULL @Bits 2..3 : Pull configuration */ + #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ + #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ + #define GPIO_PIN_CNF_PULL_Min (0x0UL) /*!< Min enumerator value of PULL field. */ + #define GPIO_PIN_CNF_PULL_Max (0x3UL) /*!< Max enumerator value of PULL field. */ + #define GPIO_PIN_CNF_PULL_Disabled (0x0UL) /*!< No pull */ + #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull-down on pin */ + #define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull-up on pin */ + +/* DRIVE0 @Bits 8..9 : Drive configuration for '0' */ + #define GPIO_PIN_CNF_DRIVE0_Pos (8UL) /*!< Position of DRIVE0 field. */ + #define GPIO_PIN_CNF_DRIVE0_Msk (0x3UL << GPIO_PIN_CNF_DRIVE0_Pos) /*!< Bit mask of DRIVE0 field. */ + #define GPIO_PIN_CNF_DRIVE0_Min (0x0UL) /*!< Min enumerator value of DRIVE0 field. */ + #define GPIO_PIN_CNF_DRIVE0_Max (0x3UL) /*!< Max enumerator value of DRIVE0 field. */ + #define GPIO_PIN_CNF_DRIVE0_S0 (0x0UL) /*!< Standard '0' */ + #define GPIO_PIN_CNF_DRIVE0_H0 (0x1UL) /*!< High drive '0' */ + #define GPIO_PIN_CNF_DRIVE0_D0 (0x2UL) /*!< Disconnect '0'(normally used for wired-or connections) */ + #define GPIO_PIN_CNF_DRIVE0_E0 (0x3UL) /*!< Extra high drive '0' */ + +/* DRIVE1 @Bits 10..11 : Drive configuration for '1' */ + #define GPIO_PIN_CNF_DRIVE1_Pos (10UL) /*!< Position of DRIVE1 field. */ + #define GPIO_PIN_CNF_DRIVE1_Msk (0x3UL << GPIO_PIN_CNF_DRIVE1_Pos) /*!< Bit mask of DRIVE1 field. */ + #define GPIO_PIN_CNF_DRIVE1_Min (0x0UL) /*!< Min enumerator value of DRIVE1 field. */ + #define GPIO_PIN_CNF_DRIVE1_Max (0x3UL) /*!< Max enumerator value of DRIVE1 field. */ + #define GPIO_PIN_CNF_DRIVE1_S1 (0x0UL) /*!< Standard '1' */ + #define GPIO_PIN_CNF_DRIVE1_H1 (0x1UL) /*!< High drive '1' */ + #define GPIO_PIN_CNF_DRIVE1_D1 (0x2UL) /*!< Disconnect '1'(normally used for wired-or connections) */ + #define GPIO_PIN_CNF_DRIVE1_E1 (0x3UL) /*!< Extra high drive '1' */ + +/* SENSE @Bits 16..17 : Pin sensing mechanism */ + #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ + #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ + #define GPIO_PIN_CNF_SENSE_Min (0x0UL) /*!< Min enumerator value of SENSE field. */ + #define GPIO_PIN_CNF_SENSE_Max (0x3UL) /*!< Max enumerator value of SENSE field. */ + #define GPIO_PIN_CNF_SENSE_Disabled (0x0UL) /*!< Disabled */ + #define GPIO_PIN_CNF_SENSE_High (0x2UL) /*!< Sense for high level */ + #define GPIO_PIN_CNF_SENSE_Low (0x3UL) /*!< Sense for low level */ + +/* CTRLSEL @Bits 28..30 : Select which module has direct control over this pin */ + #define GPIO_PIN_CNF_CTRLSEL_Pos (28UL) /*!< Position of CTRLSEL field. */ + #define GPIO_PIN_CNF_CTRLSEL_Msk (0x7UL << GPIO_PIN_CNF_CTRLSEL_Pos) /*!< Bit mask of CTRLSEL field. */ + #define GPIO_PIN_CNF_CTRLSEL_Min (0x0UL) /*!< Min enumerator value of CTRLSEL field. */ + #define GPIO_PIN_CNF_CTRLSEL_Max (0x4UL) /*!< Max enumerator value of CTRLSEL field. */ + #define GPIO_PIN_CNF_CTRLSEL_GPIO (0x0UL) /*!< GPIO or peripherals with PSEL registers */ + #define GPIO_PIN_CNF_CTRLSEL_VPR (0x1UL) /*!< VPR processor */ + #define GPIO_PIN_CNF_CTRLSEL_GRTC (0x4UL) /*!< GRTC peripheral */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ GPIOHSPADCTRL ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ================================================== Struct GPIOHSPADCTRL =================================================== */ +/** + * @brief GPIO high-speed pad control + */ + typedef struct { /*!< GPIOHSPADCTRL Structure */ + __IM uint32_t RESERVED[12]; + __IOM uint32_t BIAS; /*!< (@ 0x00000030) Bias control */ + __IM uint32_t RESERVED1; + __IOM uint32_t CTRL; /*!< (@ 0x00000038) Input sampling and buffering control (used by the VPR + coprocessor for emulating a QSPI peripheral)*/ + } NRF_GPIOHSPADCTRL_Type; /*!< Size = 60 (0x03C) */ + +/* GPIOHSPADCTRL_BIAS: Bias control */ + #define GPIOHSPADCTRL_BIAS_ResetValue (0x00000000UL) /*!< Reset value of BIAS register. */ + +/* HSBIAS @Bits 0..1 : Slew setting for high-speed pad (Use highest/fastest value) */ + #define GPIOHSPADCTRL_BIAS_HSBIAS_Pos (0UL) /*!< Position of HSBIAS field. */ + #define GPIOHSPADCTRL_BIAS_HSBIAS_Msk (0x3UL << GPIOHSPADCTRL_BIAS_HSBIAS_Pos) /*!< Bit mask of HSBIAS field. */ + #define GPIOHSPADCTRL_BIAS_HSBIAS_Min (0x0UL) /*!< Min value of HSBIAS field. */ + #define GPIOHSPADCTRL_BIAS_HSBIAS_Max (0x3UL) /*!< Max size of HSBIAS field. */ + +/* REPLICABIAS @Bit 2 : Slew setting for replica clock (used by the VPR coprocessor for emulating a QSPI peripheral) */ + #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Pos (2UL) /*!< Position of REPLICABIAS field. */ + #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Msk (0x1UL << GPIOHSPADCTRL_BIAS_REPLICABIAS_Pos) /*!< Bit mask of REPLICABIAS field. */ + #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Min (0x0UL) /*!< Min value of REPLICABIAS field. */ + #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Max (0x1UL) /*!< Max size of REPLICABIAS field. */ + + +/* GPIOHSPADCTRL_CTRL: Input sampling and buffering control (used by the VPR coprocessor for emulating a QSPI peripheral) */ + #define GPIOHSPADCTRL_CTRL_ResetValue (0x00000000UL) /*!< Reset value of CTRL register. */ + +/* RXDELAY @Bits 0..2 : Delay selection */ + #define GPIOHSPADCTRL_CTRL_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */ + #define GPIOHSPADCTRL_CTRL_RXDELAY_Msk (0x7UL << GPIOHSPADCTRL_CTRL_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ + +/* SCKEN @Bit 3 : Enable SCK */ + #define GPIOHSPADCTRL_CTRL_SCKEN_Pos (3UL) /*!< Position of SCKEN field. */ + #define GPIOHSPADCTRL_CTRL_SCKEN_Msk (0x1UL << GPIOHSPADCTRL_CTRL_SCKEN_Pos) /*!< Bit mask of SCKEN field. */ + #define GPIOHSPADCTRL_CTRL_SCKEN_Min (0x0UL) /*!< Min enumerator value of SCKEN field. */ + #define GPIOHSPADCTRL_CTRL_SCKEN_Max (0x1UL) /*!< Max enumerator value of SCKEN field. */ + #define GPIOHSPADCTRL_CTRL_SCKEN_Disabled (0x0UL) /*!< Delay chain is reset and delayed sampling is disabled */ + #define GPIOHSPADCTRL_CTRL_SCKEN_Enabled (0x1UL) /*!< Delay chain and delayed sampling is active */ + +/* SCKPHASE @Bit 4 : SCK phase */ + #define GPIOHSPADCTRL_CTRL_SCKPHASE_Pos (4UL) /*!< Position of SCKPHASE field. */ + #define GPIOHSPADCTRL_CTRL_SCKPHASE_Msk (0x1UL << GPIOHSPADCTRL_CTRL_SCKPHASE_Pos) /*!< Bit mask of SCKPHASE field. */ + #define GPIOHSPADCTRL_CTRL_SCKPHASE_Min (0x0UL) /*!< Min enumerator value of SCKPHASE field. */ + #define GPIOHSPADCTRL_CTRL_SCKPHASE_Max (0x1UL) /*!< Max enumerator value of SCKPHASE field. */ + #define GPIOHSPADCTRL_CTRL_SCKPHASE_Inverted (0x0UL) /*!< Invert SCK phase */ + #define GPIOHSPADCTRL_CTRL_SCKPHASE_NonInverted (0x1UL) /*!< Non-inverted SCK phase */ + +/* CSNEN @Bit 5 : Enable CSN synchronization of sampling */ + #define GPIOHSPADCTRL_CTRL_CSNEN_Pos (5UL) /*!< Position of CSNEN field. */ + #define GPIOHSPADCTRL_CTRL_CSNEN_Msk (0x1UL << GPIOHSPADCTRL_CTRL_CSNEN_Pos) /*!< Bit mask of CSNEN field. */ + #define GPIOHSPADCTRL_CTRL_CSNEN_Min (0x0UL) /*!< Min enumerator value of CSNEN field. */ + #define GPIOHSPADCTRL_CTRL_CSNEN_Max (0x1UL) /*!< Max enumerator value of CSNEN field. */ + #define GPIOHSPADCTRL_CTRL_CSNEN_Enabled (0x0UL) /*!< Delay chain is reset on active edge of CSN */ + #define GPIOHSPADCTRL_CTRL_CSNEN_Disabled (0x1UL) /*!< Delay chain is not reset on active edge of CSN */ + +/* DATAENABLE @Bits 6..9 : Enable delayed sampling */ + #define GPIOHSPADCTRL_CTRL_DATAENABLE_Pos (6UL) /*!< Position of DATAENABLE field. */ + #define GPIOHSPADCTRL_CTRL_DATAENABLE_Msk (0xFUL << GPIOHSPADCTRL_CTRL_DATAENABLE_Pos) /*!< Bit mask of DATAENABLE field. */ + #define GPIOHSPADCTRL_CTRL_DATAENABLE_Min (0x0UL) /*!< Min enumerator value of DATAENABLE field. */ + #define GPIOHSPADCTRL_CTRL_DATAENABLE_Max (0xFUL) /*!< Max enumerator value of DATAENABLE field. */ + #define GPIOHSPADCTRL_CTRL_DATAENABLE_Disabled (0x0UL) /*!< Delayed sampling is disabled */ + #define GPIOHSPADCTRL_CTRL_DATAENABLE_Enabled (0xFUL) /*!< Delayed sampling is enabled */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ GPIOINTERNAL ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* =================================================== Struct GPIOINTERNAL =================================================== */ +/** + * @brief GPIO Internal + */ + typedef struct { /*!< GPIOINTERNAL Structure */ + __IM uint32_t RESERVED; + } NRF_GPIOINTERNAL_Type; /*!< Size = 4 (0x004) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct GPIOTE_EVENTS_PORT ================================================ */ +/** + * @brief EVENTS_PORT [GPIOTE_EVENTS_PORT] Peripheral events. + */ +typedef struct { + __IOM uint32_t NONSECURE; /*!< (@ 0x00000000) Non-secure port event */ + __IOM uint32_t SECURE; /*!< (@ 0x00000004) Secure port event */ +} NRF_GPIOTE_EVENTS_PORT_Type; /*!< Size = 8 (0x008) */ + #define GPIOTE_EVENTS_PORT_MaxCount (1UL) /*!< Size of EVENTS_PORT[1] array. */ + #define GPIOTE_EVENTS_PORT_MaxIndex (0UL) /*!< Max index of EVENTS_PORT[1] array. */ + #define GPIOTE_EVENTS_PORT_MinIndex (0UL) /*!< Min index of EVENTS_PORT[1] array. */ + +/* GPIOTE_EVENTS_PORT_NONSECURE: Non-secure port event */ + #define GPIOTE_EVENTS_PORT_NONSECURE_ResetValue (0x00000000UL) /*!< Reset value of NONSECURE register. */ + +/* NONSECURE @Bit 0 : Non-secure port event */ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Pos (0UL) /*!< Position of NONSECURE field. */ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Msk (0x1UL << GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Pos) /*!< Bit mask of + NONSECURE field.*/ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Min (0x0UL) /*!< Min enumerator value of NONSECURE field. */ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Max (0x1UL) /*!< Max enumerator value of NONSECURE field. */ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_NotGenerated (0x0UL) /*!< Event not generated */ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Generated (0x1UL) /*!< Event generated */ + + +/* GPIOTE_EVENTS_PORT_SECURE: Secure port event */ + #define GPIOTE_EVENTS_PORT_SECURE_ResetValue (0x00000000UL) /*!< Reset value of SECURE register. */ + +/* SECURE @Bit 0 : Secure port event */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Pos (0UL) /*!< Position of SECURE field. */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Msk (0x1UL << GPIOTE_EVENTS_PORT_SECURE_SECURE_Pos) /*!< Bit mask of SECURE field. */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field. */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Max (0x1UL) /*!< Max enumerator value of SECURE field. */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_NotGenerated (0x0UL) /*!< Event not generated */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Generated (0x1UL) /*!< Event generated */ + + + +/* =============================================== Struct GPIOTE_PUBLISH_PORT ================================================ */ +/** + * @brief PUBLISH_PORT [GPIOTE_PUBLISH_PORT] Publish configuration for events + */ +typedef struct { + __IOM uint32_t NONSECURE; /*!< (@ 0x00000000) Publish configuration for event PORT[n].NONSECURE */ + __IOM uint32_t SECURE; /*!< (@ 0x00000004) Publish configuration for event PORT[n].SECURE */ +} NRF_GPIOTE_PUBLISH_PORT_Type; /*!< Size = 8 (0x008) */ + #define GPIOTE_PUBLISH_PORT_MaxCount (1UL) /*!< Size of PUBLISH_PORT[1] array. */ + #define GPIOTE_PUBLISH_PORT_MaxIndex (0UL) /*!< Max index of PUBLISH_PORT[1] array. */ + #define GPIOTE_PUBLISH_PORT_MinIndex (0UL) /*!< Min index of PUBLISH_PORT[1] array. */ + +/* GPIOTE_PUBLISH_PORT_NONSECURE: Publish configuration for event PORT[n].NONSECURE */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_ResetValue (0x00000000UL) /*!< Reset value of NONSECURE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PORT[n].NONSECURE will publish to */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_NONSECURE_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* GPIOTE_PUBLISH_PORT_SECURE: Publish configuration for event PORT[n].SECURE */ + #define GPIOTE_PUBLISH_PORT_SECURE_ResetValue (0x00000000UL) /*!< Reset value of SECURE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PORT[n].SECURE will publish to */ + #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_SECURE_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* ====================================================== Struct GPIOTE ====================================================== */ +/** + * @brief GPIO Tasks and Events + */ + typedef struct { /*!< GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Task for writing to pin specified in CONFIG[n].PSEL. + Action on pin is configured in CONFIG[n].POLARITY.*/ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Task for writing to pin specified in CONFIG[n].PSEL. + Action on pin is to set it high.*/ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Task for writing to pin specified in CONFIG[n].PSEL. + Action on pin is to set it low.*/ + __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Subscribe configuration for task OUT[n] */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Subscribe configuration for task SET[n] */ + __IM uint32_t RESERVED3[4]; + __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Subscribe configuration for task CLR[n] */ + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Event from pin specified in CONFIG[n].PSEL */ + __IM uint32_t RESERVED4[8]; + __IOM NRF_GPIOTE_EVENTS_PORT_Type EVENTS_PORT[1]; /*!< (@ 0x00000140) Peripheral events. */ + __IM uint32_t RESERVED5[14]; + __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Publish configuration for event IN[n] */ + __IM uint32_t RESERVED6[8]; + __IOM NRF_GPIOTE_PUBLISH_PORT_Type PUBLISH_PORT[1]; /*!< (@ 0x000001C0) Publish configuration for events */ + __IM uint32_t RESERVED7[79]; + __IOM uint32_t INTENSET0; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR0; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED8[2]; + __IOM uint32_t INTENSET1; /*!< (@ 0x00000314) Enable interrupt */ + __IOM uint32_t INTENCLR1; /*!< (@ 0x00000318) Disable interrupt */ + __IM uint32_t RESERVED9[125]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Configuration for OUT[n], SET[n], and CLR[n] tasks and + IN[n] event*/ + } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + +/* GPIOTE_TASKS_OUT: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ + #define GPIOTE_TASKS_OUT_MaxCount (8UL) /*!< Max size of TASKS_OUT[8] array. */ + #define GPIOTE_TASKS_OUT_MaxIndex (7UL) /*!< Max index of TASKS_OUT[8] array. */ + #define GPIOTE_TASKS_OUT_MinIndex (0UL) /*!< Min index of TASKS_OUT[8] array. */ + #define GPIOTE_TASKS_OUT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_OUT[8] register. */ + +/* TASKS_OUT @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ + #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ + #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ + #define GPIOTE_TASKS_OUT_TASKS_OUT_Min (0x1UL) /*!< Min enumerator value of TASKS_OUT field. */ + #define GPIOTE_TASKS_OUT_TASKS_OUT_Max (0x1UL) /*!< Max enumerator value of TASKS_OUT field. */ + #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (0x1UL) /*!< Trigger task */ + + +/* GPIOTE_TASKS_SET: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ + #define GPIOTE_TASKS_SET_MaxCount (8UL) /*!< Max size of TASKS_SET[8] array. */ + #define GPIOTE_TASKS_SET_MaxIndex (7UL) /*!< Max index of TASKS_SET[8] array. */ + #define GPIOTE_TASKS_SET_MinIndex (0UL) /*!< Min index of TASKS_SET[8] array. */ + #define GPIOTE_TASKS_SET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SET[8] register. */ + +/* TASKS_SET @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ + #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ + #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ + #define GPIOTE_TASKS_SET_TASKS_SET_Min (0x1UL) /*!< Min enumerator value of TASKS_SET field. */ + #define GPIOTE_TASKS_SET_TASKS_SET_Max (0x1UL) /*!< Max enumerator value of TASKS_SET field. */ + #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (0x1UL) /*!< Trigger task */ + + +/* GPIOTE_TASKS_CLR: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ + #define GPIOTE_TASKS_CLR_MaxCount (8UL) /*!< Max size of TASKS_CLR[8] array. */ + #define GPIOTE_TASKS_CLR_MaxIndex (7UL) /*!< Max index of TASKS_CLR[8] array. */ + #define GPIOTE_TASKS_CLR_MinIndex (0UL) /*!< Min index of TASKS_CLR[8] array. */ + #define GPIOTE_TASKS_CLR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLR[8] register. */ + +/* TASKS_CLR @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ + #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ + #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ + #define GPIOTE_TASKS_CLR_TASKS_CLR_Min (0x1UL) /*!< Min enumerator value of TASKS_CLR field. */ + #define GPIOTE_TASKS_CLR_TASKS_CLR_Max (0x1UL) /*!< Max enumerator value of TASKS_CLR field. */ + #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (0x1UL) /*!< Trigger task */ + + +/* GPIOTE_SUBSCRIBE_OUT: Subscribe configuration for task OUT[n] */ + #define GPIOTE_SUBSCRIBE_OUT_MaxCount (8UL) /*!< Max size of SUBSCRIBE_OUT[8] array. */ + #define GPIOTE_SUBSCRIBE_OUT_MaxIndex (7UL) /*!< Max index of SUBSCRIBE_OUT[8] array. */ + #define GPIOTE_SUBSCRIBE_OUT_MinIndex (0UL) /*!< Min index of SUBSCRIBE_OUT[8] array. */ + #define GPIOTE_SUBSCRIBE_OUT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_OUT[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task OUT[n] will subscribe to */ + #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* GPIOTE_SUBSCRIBE_SET: Subscribe configuration for task SET[n] */ + #define GPIOTE_SUBSCRIBE_SET_MaxCount (8UL) /*!< Max size of SUBSCRIBE_SET[8] array. */ + #define GPIOTE_SUBSCRIBE_SET_MaxIndex (7UL) /*!< Max index of SUBSCRIBE_SET[8] array. */ + #define GPIOTE_SUBSCRIBE_SET_MinIndex (0UL) /*!< Min index of SUBSCRIBE_SET[8] array. */ + #define GPIOTE_SUBSCRIBE_SET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SET[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SET[n] will subscribe to */ + #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_SET_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_SET_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_SUBSCRIBE_SET_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_SET_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* GPIOTE_SUBSCRIBE_CLR: Subscribe configuration for task CLR[n] */ + #define GPIOTE_SUBSCRIBE_CLR_MaxCount (8UL) /*!< Max size of SUBSCRIBE_CLR[8] array. */ + #define GPIOTE_SUBSCRIBE_CLR_MaxIndex (7UL) /*!< Max index of SUBSCRIBE_CLR[8] array. */ + #define GPIOTE_SUBSCRIBE_CLR_MinIndex (0UL) /*!< Min index of SUBSCRIBE_CLR[8] array. */ + #define GPIOTE_SUBSCRIBE_CLR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLR[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CLR[n] will subscribe to */ + #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* GPIOTE_EVENTS_IN: Event from pin specified in CONFIG[n].PSEL */ + #define GPIOTE_EVENTS_IN_MaxCount (8UL) /*!< Max size of EVENTS_IN[8] array. */ + #define GPIOTE_EVENTS_IN_MaxIndex (7UL) /*!< Max index of EVENTS_IN[8] array. */ + #define GPIOTE_EVENTS_IN_MinIndex (0UL) /*!< Min index of EVENTS_IN[8] array. */ + #define GPIOTE_EVENTS_IN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_IN[8] register. */ + +/* EVENTS_IN @Bit 0 : Event from pin specified in CONFIG[n].PSEL */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_Min (0x0UL) /*!< Min enumerator value of EVENTS_IN field. */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_Max (0x1UL) /*!< Max enumerator value of EVENTS_IN field. */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0x0UL) /*!< Event not generated */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (0x1UL) /*!< Event generated */ + + +/* GPIOTE_PUBLISH_IN: Publish configuration for event IN[n] */ + #define GPIOTE_PUBLISH_IN_MaxCount (8UL) /*!< Max size of PUBLISH_IN[8] array. */ + #define GPIOTE_PUBLISH_IN_MaxIndex (7UL) /*!< Max index of PUBLISH_IN[8] array. */ + #define GPIOTE_PUBLISH_IN_MinIndex (0UL) /*!< Min index of PUBLISH_IN[8] array. */ + #define GPIOTE_PUBLISH_IN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_IN[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event IN[n] will publish to */ + #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GPIOTE_PUBLISH_IN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_PUBLISH_IN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_PUBLISH_IN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_PUBLISH_IN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_PUBLISH_IN_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define GPIOTE_PUBLISH_IN_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* GPIOTE_INTENSET0: Enable interrupt */ + #define GPIOTE_INTENSET0_ResetValue (0x00000000UL) /*!< Reset value of INTENSET0 register. */ + +/* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */ + #define GPIOTE_INTENSET0_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENSET0_IN0_Msk (0x1UL << GPIOTE_INTENSET0_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENSET0_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENSET0_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENSET0_IN0_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */ + #define GPIOTE_INTENSET0_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENSET0_IN1_Msk (0x1UL << GPIOTE_INTENSET0_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENSET0_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENSET0_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENSET0_IN1_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */ + #define GPIOTE_INTENSET0_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENSET0_IN2_Msk (0x1UL << GPIOTE_INTENSET0_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENSET0_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENSET0_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENSET0_IN2_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */ + #define GPIOTE_INTENSET0_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENSET0_IN3_Msk (0x1UL << GPIOTE_INTENSET0_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENSET0_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENSET0_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENSET0_IN3_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */ + #define GPIOTE_INTENSET0_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENSET0_IN4_Msk (0x1UL << GPIOTE_INTENSET0_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENSET0_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENSET0_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENSET0_IN4_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */ + #define GPIOTE_INTENSET0_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENSET0_IN5_Msk (0x1UL << GPIOTE_INTENSET0_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENSET0_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENSET0_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENSET0_IN5_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */ + #define GPIOTE_INTENSET0_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENSET0_IN6_Msk (0x1UL << GPIOTE_INTENSET0_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENSET0_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENSET0_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENSET0_IN6_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */ + #define GPIOTE_INTENSET0_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENSET0_IN7_Msk (0x1UL << GPIOTE_INTENSET0_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENSET0_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENSET0_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENSET0_IN7_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENSET0_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENSET0_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENSET0_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET0_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET0_PORT0SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENCLR0: Disable interrupt */ + #define GPIOTE_INTENCLR0_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR0 register. */ + +/* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */ + #define GPIOTE_INTENCLR0_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENCLR0_IN0_Msk (0x1UL << GPIOTE_INTENCLR0_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENCLR0_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR0_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR0_IN0_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */ + #define GPIOTE_INTENCLR0_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENCLR0_IN1_Msk (0x1UL << GPIOTE_INTENCLR0_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENCLR0_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR0_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR0_IN1_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */ + #define GPIOTE_INTENCLR0_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENCLR0_IN2_Msk (0x1UL << GPIOTE_INTENCLR0_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENCLR0_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR0_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR0_IN2_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */ + #define GPIOTE_INTENCLR0_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENCLR0_IN3_Msk (0x1UL << GPIOTE_INTENCLR0_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENCLR0_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR0_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR0_IN3_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */ + #define GPIOTE_INTENCLR0_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENCLR0_IN4_Msk (0x1UL << GPIOTE_INTENCLR0_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENCLR0_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR0_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR0_IN4_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */ + #define GPIOTE_INTENCLR0_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENCLR0_IN5_Msk (0x1UL << GPIOTE_INTENCLR0_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENCLR0_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR0_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR0_IN5_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */ + #define GPIOTE_INTENCLR0_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENCLR0_IN6_Msk (0x1UL << GPIOTE_INTENCLR0_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENCLR0_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR0_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR0_IN6_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */ + #define GPIOTE_INTENCLR0_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENCLR0_IN7_Msk (0x1UL << GPIOTE_INTENCLR0_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENCLR0_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR0_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR0_IN7_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENSET1: Enable interrupt */ + #define GPIOTE_INTENSET1_ResetValue (0x00000000UL) /*!< Reset value of INTENSET1 register. */ + +/* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */ + #define GPIOTE_INTENSET1_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENSET1_IN0_Msk (0x1UL << GPIOTE_INTENSET1_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENSET1_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENSET1_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENSET1_IN0_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */ + #define GPIOTE_INTENSET1_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENSET1_IN1_Msk (0x1UL << GPIOTE_INTENSET1_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENSET1_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENSET1_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENSET1_IN1_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */ + #define GPIOTE_INTENSET1_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENSET1_IN2_Msk (0x1UL << GPIOTE_INTENSET1_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENSET1_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENSET1_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENSET1_IN2_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */ + #define GPIOTE_INTENSET1_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENSET1_IN3_Msk (0x1UL << GPIOTE_INTENSET1_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENSET1_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENSET1_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENSET1_IN3_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */ + #define GPIOTE_INTENSET1_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENSET1_IN4_Msk (0x1UL << GPIOTE_INTENSET1_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENSET1_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENSET1_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENSET1_IN4_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */ + #define GPIOTE_INTENSET1_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENSET1_IN5_Msk (0x1UL << GPIOTE_INTENSET1_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENSET1_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENSET1_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENSET1_IN5_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */ + #define GPIOTE_INTENSET1_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENSET1_IN6_Msk (0x1UL << GPIOTE_INTENSET1_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENSET1_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENSET1_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENSET1_IN6_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */ + #define GPIOTE_INTENSET1_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENSET1_IN7_Msk (0x1UL << GPIOTE_INTENSET1_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENSET1_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENSET1_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENSET1_IN7_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENSET1_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENSET1_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENSET1_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET1_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET1_PORT0SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENCLR1: Disable interrupt */ + #define GPIOTE_INTENCLR1_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR1 register. */ + +/* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */ + #define GPIOTE_INTENCLR1_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENCLR1_IN0_Msk (0x1UL << GPIOTE_INTENCLR1_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENCLR1_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR1_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR1_IN0_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */ + #define GPIOTE_INTENCLR1_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENCLR1_IN1_Msk (0x1UL << GPIOTE_INTENCLR1_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENCLR1_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR1_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR1_IN1_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */ + #define GPIOTE_INTENCLR1_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENCLR1_IN2_Msk (0x1UL << GPIOTE_INTENCLR1_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENCLR1_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR1_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR1_IN2_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */ + #define GPIOTE_INTENCLR1_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENCLR1_IN3_Msk (0x1UL << GPIOTE_INTENCLR1_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENCLR1_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR1_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR1_IN3_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */ + #define GPIOTE_INTENCLR1_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENCLR1_IN4_Msk (0x1UL << GPIOTE_INTENCLR1_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENCLR1_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR1_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR1_IN4_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */ + #define GPIOTE_INTENCLR1_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENCLR1_IN5_Msk (0x1UL << GPIOTE_INTENCLR1_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENCLR1_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR1_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR1_IN5_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */ + #define GPIOTE_INTENCLR1_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENCLR1_IN6_Msk (0x1UL << GPIOTE_INTENCLR1_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENCLR1_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR1_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR1_IN6_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */ + #define GPIOTE_INTENCLR1_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENCLR1_IN7_Msk (0x1UL << GPIOTE_INTENCLR1_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENCLR1_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR1_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR1_IN7_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_CONFIG: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ + #define GPIOTE_CONFIG_MaxCount (8UL) /*!< Max size of CONFIG[8] array. */ + #define GPIOTE_CONFIG_MaxIndex (7UL) /*!< Max index of CONFIG[8] array. */ + #define GPIOTE_CONFIG_MinIndex (0UL) /*!< Min index of CONFIG[8] array. */ + #define GPIOTE_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG[8] register. */ + +/* MODE @Bits 0..1 : Mode */ + #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ + #define GPIOTE_CONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define GPIOTE_CONFIG_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field. */ + #define GPIOTE_CONFIG_MODE_Disabled (0x0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE + module.*/ + #define GPIOTE_CONFIG_MODE_Event (0x1UL) /*!< Event mode */ + #define GPIOTE_CONFIG_MODE_Task (0x3UL) /*!< Task mode */ + +/* PSEL @Bits 4..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ + #define GPIOTE_CONFIG_PSEL_Pos (4UL) /*!< Position of PSEL field. */ + #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + #define GPIOTE_CONFIG_PSEL_Min (0x00UL) /*!< Min value of PSEL field. */ + #define GPIOTE_CONFIG_PSEL_Max (0x1FUL) /*!< Max size of PSEL field. */ + +/* PORT @Bits 9..12 : Port number */ + #define GPIOTE_CONFIG_PORT_Pos (9UL) /*!< Position of PORT field. */ + #define GPIOTE_CONFIG_PORT_Msk (0xFUL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */ + #define GPIOTE_CONFIG_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define GPIOTE_CONFIG_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* POLARITY @Bits 16..17 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event + mode: Operation on input that shall trigger IN[n] event. */ + + #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ + #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ + #define GPIOTE_CONFIG_POLARITY_Min (0x0UL) /*!< Min enumerator value of POLARITY field. */ + #define GPIOTE_CONFIG_POLARITY_Max (0x3UL) /*!< Max enumerator value of POLARITY field. */ + #define GPIOTE_CONFIG_POLARITY_None (0x0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] + event generated on pin activity.*/ + #define GPIOTE_CONFIG_POLARITY_LoToHi (0x1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event + when rising edge on pin.*/ + #define GPIOTE_CONFIG_POLARITY_HiToLo (0x2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] + event when falling edge on pin.*/ + #define GPIOTE_CONFIG_POLARITY_Toggle (0x3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any + change on pin.*/ + +/* OUTINIT @Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: + No effect. */ + + #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ + #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ + #define GPIOTE_CONFIG_OUTINIT_Min (0x0UL) /*!< Min enumerator value of OUTINIT field. */ + #define GPIOTE_CONFIG_OUTINIT_Max (0x1UL) /*!< Max enumerator value of OUTINIT field. */ + #define GPIOTE_CONFIG_OUTINIT_Low (0x0UL) /*!< Task mode: Initial value of pin before task triggering is low */ + #define GPIOTE_CONFIG_OUTINIT_High (0x1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ GRTC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ===================================================== Struct GRTC_CC ====================================================== */ +/** + * @brief CC [GRTC_CC] (unspecified) + */ +typedef struct { + __IOM uint32_t CCL; /*!< (@ 0x00000000) The lower 32-bits of Capture/Compare register CC[n] */ + __IOM uint32_t CCH; /*!< (@ 0x00000004) The higher 32-bits of Capture/Compare register CC[n] */ + __OM uint32_t CCADD; /*!< (@ 0x00000008) Count to add to CC[n] when this register is written. */ + __IOM uint32_t CCEN; /*!< (@ 0x0000000C) Configure Capture/Compare register CC[n] */ +} NRF_GRTC_CC_Type; /*!< Size = 16 (0x010) */ + #define GRTC_CC_MaxCount (12UL) /*!< Size of CC[12] array. */ + #define GRTC_CC_MaxIndex (11UL) /*!< Max index of CC[12] array. */ + #define GRTC_CC_MinIndex (0UL) /*!< Min index of CC[12] array. */ + +/* GRTC_CC_CCL: The lower 32-bits of Capture/Compare register CC[n] */ + #define GRTC_CC_CCL_ResetValue (0x00000000UL) /*!< Reset value of CCL register. */ + +/* CCL @Bits 0..31 : Capture/Compare low value in 1 us */ + #define GRTC_CC_CCL_CCL_Pos (0UL) /*!< Position of CCL field. */ + #define GRTC_CC_CCL_CCL_Msk (0xFFFFFFFFUL << GRTC_CC_CCL_CCL_Pos) /*!< Bit mask of CCL field. */ + + +/* GRTC_CC_CCH: The higher 32-bits of Capture/Compare register CC[n] */ + #define GRTC_CC_CCH_ResetValue (0x00000000UL) /*!< Reset value of CCH register. */ + +/* CCH @Bits 0..19 : Capture/Compare high value in 1 us */ + #define GRTC_CC_CCH_CCH_Pos (0UL) /*!< Position of CCH field. */ + #define GRTC_CC_CCH_CCH_Msk (0xFFFFFUL << GRTC_CC_CCH_CCH_Pos) /*!< Bit mask of CCH field. */ + + +/* GRTC_CC_CCADD: Count to add to CC[n] when this register is written. */ + #define GRTC_CC_CCADD_ResetValue (0x00000000UL) /*!< Reset value of CCADD register. */ + +/* VALUE @Bits 0..30 : Count to add to CC[n] */ + #define GRTC_CC_CCADD_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define GRTC_CC_CCADD_VALUE_Msk (0x7FFFFFFFUL << GRTC_CC_CCADD_VALUE_Pos) /*!< Bit mask of VALUE field. */ + +/* REFERENCE @Bit 31 : Configure the Capture/Compare register */ + #define GRTC_CC_CCADD_REFERENCE_Pos (31UL) /*!< Position of REFERENCE field. */ + #define GRTC_CC_CCADD_REFERENCE_Msk (0x1UL << GRTC_CC_CCADD_REFERENCE_Pos) /*!< Bit mask of REFERENCE field. */ + #define GRTC_CC_CCADD_REFERENCE_Min (0x0UL) /*!< Min enumerator value of REFERENCE field. */ + #define GRTC_CC_CCADD_REFERENCE_Max (0x1UL) /*!< Max enumerator value of REFERENCE field. */ + #define GRTC_CC_CCADD_REFERENCE_SYSCOUNTER (0x0UL) /*!< Adds SYSCOUNTER value. */ + #define GRTC_CC_CCADD_REFERENCE_CC (0x1UL) /*!< Adds CC value. */ + + +/* GRTC_CC_CCEN: Configure Capture/Compare register CC[n] */ + #define GRTC_CC_CCEN_ResetValue (0x00000000UL) /*!< Reset value of CCEN register. */ + +/* ACTIVE @Bit 0 : Configure the Capture/Compare register */ + #define GRTC_CC_CCEN_ACTIVE_Pos (0UL) /*!< Position of ACTIVE field. */ + #define GRTC_CC_CCEN_ACTIVE_Msk (0x1UL << GRTC_CC_CCEN_ACTIVE_Pos) /*!< Bit mask of ACTIVE field. */ + #define GRTC_CC_CCEN_ACTIVE_Min (0x0UL) /*!< Min enumerator value of ACTIVE field. */ + #define GRTC_CC_CCEN_ACTIVE_Max (0x1UL) /*!< Max enumerator value of ACTIVE field. */ + #define GRTC_CC_CCEN_ACTIVE_Disable (0x0UL) /*!< Capture/Compare register CC[n] Disabled. */ + #define GRTC_CC_CCEN_ACTIVE_Enable (0x1UL) /*!< Capture/Compare register CC[n] enabled. */ + +/* PASTCC @Bit 1 : Status of event EVENTS_COMPARE[n] caused by the configured CC value is in past */ + #define GRTC_CC_CCEN_PASTCC_Pos (1UL) /*!< Position of PASTCC field. */ + #define GRTC_CC_CCEN_PASTCC_Msk (0x1UL << GRTC_CC_CCEN_PASTCC_Pos) /*!< Bit mask of PASTCC field. */ + #define GRTC_CC_CCEN_PASTCC_Min (0x0UL) /*!< Min enumerator value of PASTCC field. */ + #define GRTC_CC_CCEN_PASTCC_Max (0x1UL) /*!< Max enumerator value of PASTCC field. */ + #define GRTC_CC_CCEN_PASTCC_Inactive (0x0UL) /*!< Inactive */ + #define GRTC_CC_CCEN_PASTCC_Active (0x1UL) /*!< Active */ + + + +/* =================================================== Struct GRTC_STATUS ==================================================== */ +/** + * @brief STATUS [GRTC_STATUS] (unspecified) + */ +typedef struct { + __IOM uint32_t LFTIMER; /*!< (@ 0x00000000) Low frequency timer status. */ + __IOM uint32_t PWM; /*!< (@ 0x00000004) PWM status. */ + __IOM uint32_t CLKOUT; /*!< (@ 0x00000008) CLKOUT configuration status. */ +} NRF_GRTC_STATUS_Type; /*!< Size = 12 (0x00C) */ + +/* GRTC_STATUS_LFTIMER: Low frequency timer status. */ + #define GRTC_STATUS_LFTIMER_ResetValue (0x00000001UL) /*!< Reset value of LFTIMER register. */ + +/* READY @Bit 0 : Low frequency timer is ready or busy. */ + #define GRTC_STATUS_LFTIMER_READY_Pos (0UL) /*!< Position of READY field. */ + #define GRTC_STATUS_LFTIMER_READY_Msk (0x1UL << GRTC_STATUS_LFTIMER_READY_Pos) /*!< Bit mask of READY field. */ + #define GRTC_STATUS_LFTIMER_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define GRTC_STATUS_LFTIMER_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define GRTC_STATUS_LFTIMER_READY_Busy (0x0UL) /*!< Busy */ + #define GRTC_STATUS_LFTIMER_READY_Ready (0x1UL) /*!< Ready */ + + +/* GRTC_STATUS_PWM: PWM status. */ + #define GRTC_STATUS_PWM_ResetValue (0x00000001UL) /*!< Reset value of PWM register. */ + +/* READY @Bit 0 : PWM is ready or busy. */ + #define GRTC_STATUS_PWM_READY_Pos (0UL) /*!< Position of READY field. */ + #define GRTC_STATUS_PWM_READY_Msk (0x1UL << GRTC_STATUS_PWM_READY_Pos) /*!< Bit mask of READY field. */ + #define GRTC_STATUS_PWM_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define GRTC_STATUS_PWM_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define GRTC_STATUS_PWM_READY_Busy (0x0UL) /*!< Busy */ + #define GRTC_STATUS_PWM_READY_Ready (0x1UL) /*!< Ready */ + + +/* GRTC_STATUS_CLKOUT: CLKOUT configuration status. */ + #define GRTC_STATUS_CLKOUT_ResetValue (0x00000001UL) /*!< Reset value of CLKOUT register. */ + +/* READY @Bit 0 : CLKOUT is ready or busy. */ + #define GRTC_STATUS_CLKOUT_READY_Pos (0UL) /*!< Position of READY field. */ + #define GRTC_STATUS_CLKOUT_READY_Msk (0x1UL << GRTC_STATUS_CLKOUT_READY_Pos) /*!< Bit mask of READY field. */ + #define GRTC_STATUS_CLKOUT_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define GRTC_STATUS_CLKOUT_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define GRTC_STATUS_CLKOUT_READY_Busy (0x0UL) /*!< Busy */ + #define GRTC_STATUS_CLKOUT_READY_Ready (0x1UL) /*!< Ready */ + + + +/* ================================================= Struct GRTC_SYSCOUNTER ================================================== */ +/** + * @brief SYSCOUNTER [GRTC_SYSCOUNTER] (unspecified) + */ +typedef struct { + __IM uint32_t SYSCOUNTERL; /*!< (@ 0x00000000) The lower 32-bits of the SYSCOUNTER for index [n] */ + __IM uint32_t SYSCOUNTERH; /*!< (@ 0x00000004) The higher 20-bits of the SYSCOUNTER for index [n] */ + __IOM uint32_t ACTIVE; /*!< (@ 0x00000008) Request to keep the SYSCOUNTER in the active state and + prevent going to sleep for index [n]*/ + __IM uint32_t RESERVED; +} NRF_GRTC_SYSCOUNTER_Type; /*!< Size = 16 (0x010) */ + #define GRTC_SYSCOUNTER_MaxCount (4UL) /*!< Size of SYSCOUNTER[4] array. */ + #define GRTC_SYSCOUNTER_MaxIndex (3UL) /*!< Max index of SYSCOUNTER[4] array. */ + #define GRTC_SYSCOUNTER_MinIndex (0UL) /*!< Min index of SYSCOUNTER[4] array. */ + +/* GRTC_SYSCOUNTER_SYSCOUNTERL: The lower 32-bits of the SYSCOUNTER for index [n] */ + #define GRTC_SYSCOUNTER_SYSCOUNTERL_ResetValue (0x00000000UL) /*!< Reset value of SYSCOUNTERL register. */ + +/* VALUE @Bits 0..31 : The lower 32-bits of the SYSCOUNTER value. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Msk (0xFFFFFFFFUL << GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + + +/* GRTC_SYSCOUNTER_SYSCOUNTERH: The higher 20-bits of the SYSCOUNTER for index [n] */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_ResetValue (0x60000000UL) /*!< Reset value of SYSCOUNTERH register. */ + +/* VALUE @Bits 0..19 : The higher 20-bits of the SYSCOUNTER value. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Msk (0xFFFFFUL << GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + +/* LOADED @Bit 29 : SYSCOUNTER loaded status */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_LOADED_Pos (29UL) /*!< Position of LOADED field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_LOADED_Msk (0x1UL << GRTC_SYSCOUNTER_SYSCOUNTERH_LOADED_Pos) /*!< Bit mask of LOADED + field.*/ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_LOADED_Min (0x0UL) /*!< Min enumerator value of LOADED field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_LOADED_Max (0x1UL) /*!< Max enumerator value of LOADED field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_LOADED_NotLoaded (0x0UL) /*!< SYSCOUNTER is not loaded */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_LOADED_Loaded (0x1UL) /*!< SYSCOUNTER is loaded */ + +/* BUSY @Bit 30 : SYSCOUNTER busy status */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Pos (30UL) /*!< Position of BUSY field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Msk (0x1UL << GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Pos) /*!< Bit mask of BUSY field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Min (0x0UL) /*!< Min enumerator value of BUSY field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Max (0x1UL) /*!< Max enumerator value of BUSY field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Ready (0x0UL) /*!< SYSCOUNTER is ready for read */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Busy (0x1UL) /*!< SYSCOUNTER is busy, so not ready for read (value returned in the + VALUE field of this register is not valid)*/ + +/* OVERFLOW @Bit 31 : The SYSCOUNTERL overflow indication after reading it. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Pos (31UL) /*!< Position of OVERFLOW field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Msk (0x1UL << GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW + field.*/ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Min (0x0UL) /*!< Min enumerator value of OVERFLOW field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Max (0x1UL) /*!< Max enumerator value of OVERFLOW field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_NoOverflow (0x0UL) /*!< SYSCOUNTERL is not overflown */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Overflow (0x1UL) /*!< SYSCOUNTERL overflown */ + + +/* GRTC_SYSCOUNTER_ACTIVE: Request to keep the SYSCOUNTER in the active state and prevent going to sleep for index [n] */ + #define GRTC_SYSCOUNTER_ACTIVE_ResetValue (0x00000000UL) /*!< Reset value of ACTIVE register. */ + +/* ACTIVE @Bit 0 : Keep SYSCOUNTER in active state */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Pos (0UL) /*!< Position of ACTIVE field. */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Msk (0x1UL << GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Pos) /*!< Bit mask of ACTIVE field. */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Min (0x0UL) /*!< Min enumerator value of ACTIVE field. */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Max (0x1UL) /*!< Max enumerator value of ACTIVE field. */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + + +/* ======================================================= Struct GRTC ======================================================= */ +/** + * @brief Global Real-time counter + */ + typedef struct { /*!< GRTC Structure */ + __OM uint32_t TASKS_CAPTURE[12]; /*!< (@ 0x00000000) Capture the counter value to CC[n] register */ + __IM uint32_t RESERVED[12]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000060) Start the counter */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000064) Stop the counter */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000068) Clear the counter */ + __OM uint32_t TASKS_PWMSTART; /*!< (@ 0x0000006C) Start the PWM */ + __OM uint32_t TASKS_PWMSTOP; /*!< (@ 0x00000070) Stop the PWM */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t SUBSCRIBE_CAPTURE[12]; /*!< (@ 0x00000080) Subscribe configuration for task CAPTURE[n] */ + __IM uint32_t RESERVED2[20]; + __IOM uint32_t EVENTS_COMPARE[12]; /*!< (@ 0x00000100) Compare event on CC[n] match */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVENTS_RTCOMPARESYNC; /*!< (@ 0x00000164) The GRTC low frequency timer is synchronized with the + SYSCOUNTER*/ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x0000016C) Event on end of each PWM period */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_PWMREADY; /*!< (@ 0x00000174) Event on STATUS.PWM.READY status changed to ready */ + __IOM uint32_t EVENTS_CLKOUTREADY; /*!< (@ 0x00000178) Event on STATUS.CLKOUT.READY status changed to ready */ + __IM uint32_t RESERVED6; + __IOM uint32_t PUBLISH_COMPARE[12]; /*!< (@ 0x00000180) Publish configuration for event COMPARE[n] */ + __IM uint32_t RESERVED7[17]; + __IOM uint32_t PUBLISH_PWMREADY; /*!< (@ 0x000001F4) Publish configuration for event PWMREADY */ + __IOM uint32_t PUBLISH_CLKOUTREADY; /*!< (@ 0x000001F8) Publish configuration for event CLKOUTREADY */ + __IM uint32_t RESERVED8; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED9[63]; + __IOM uint32_t INTEN0; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET0; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR0; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND0; /*!< (@ 0x0000030C) Pending interrupts */ + __IOM uint32_t INTEN1; /*!< (@ 0x00000310) Enable or disable interrupt */ + __IOM uint32_t INTENSET1; /*!< (@ 0x00000314) Enable interrupt */ + __IOM uint32_t INTENCLR1; /*!< (@ 0x00000318) Disable interrupt */ + __IM uint32_t INTPEND1; /*!< (@ 0x0000031C) Pending interrupts */ + __IOM uint32_t INTEN2; /*!< (@ 0x00000320) Enable or disable interrupt */ + __IOM uint32_t INTENSET2; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t INTENCLR2; /*!< (@ 0x00000328) Disable interrupt */ + __IM uint32_t INTPEND2; /*!< (@ 0x0000032C) Pending interrupts */ + __IOM uint32_t INTEN3; /*!< (@ 0x00000330) Enable or disable interrupt */ + __IOM uint32_t INTENSET3; /*!< (@ 0x00000334) Enable interrupt */ + __IOM uint32_t INTENCLR3; /*!< (@ 0x00000338) Disable interrupt */ + __IM uint32_t INTPEND3; /*!< (@ 0x0000033C) Pending interrupts */ + __IM uint32_t RESERVED10[48]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000400) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000404) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000408) Disable event routing */ + __IM uint32_t RESERVED11[65]; + __IOM uint32_t MODE; /*!< (@ 0x00000510) Counter mode selection */ + __IM uint32_t RESERVED12[3]; + __IOM NRF_GRTC_CC_Type CC[12]; /*!< (@ 0x00000520) (unspecified) */ + __IM uint32_t RESERVED13[49]; + __IOM uint32_t TIMEOUT; /*!< (@ 0x000006A4) Timeout after all CPUs gone into sleep state to stop + the SYSCOUNTER*/ + __IOM uint32_t INTERVAL; /*!< (@ 0x000006A8) Count to add to CC[0] when the event EVENTS_COMPARE[0] + triggers.*/ + __IOM uint32_t WAKETIME; /*!< (@ 0x000006AC) GRTC wake up time. */ + __IOM NRF_GRTC_STATUS_Type STATUS; /*!< (@ 0x000006B0) (unspecified) */ + __IM uint32_t RESERVED14[21]; + __IOM uint32_t PWMCONFIG; /*!< (@ 0x00000710) PWM configuration. */ + __IOM uint32_t CLKOUT; /*!< (@ 0x00000714) Configuration of clock output */ + __IOM uint32_t CLKCFG; /*!< (@ 0x00000718) Clock Configuration */ + __IM uint32_t RESERVED15; + __IOM NRF_GRTC_SYSCOUNTER_Type SYSCOUNTER[4]; /*!< (@ 0x00000720) (unspecified) */ + } NRF_GRTC_Type; /*!< Size = 1888 (0x760) */ + +/* GRTC_TASKS_CAPTURE: Capture the counter value to CC[n] register */ + #define GRTC_TASKS_CAPTURE_MaxCount (12UL) /*!< Max size of TASKS_CAPTURE[12] array. */ + #define GRTC_TASKS_CAPTURE_MaxIndex (11UL) /*!< Max index of TASKS_CAPTURE[12] array. */ + #define GRTC_TASKS_CAPTURE_MinIndex (0UL) /*!< Min index of TASKS_CAPTURE[12] array. */ + #define GRTC_TASKS_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CAPTURE[12] register. */ + +/* TASKS_CAPTURE @Bit 0 : Capture the counter value to CC[n] register */ + #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ + #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE + field.*/ + #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Min (0x1UL) /*!< Min enumerator value of TASKS_CAPTURE field. */ + #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Max (0x1UL) /*!< Max enumerator value of TASKS_CAPTURE field. */ + #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task */ + + +/* GRTC_TASKS_START: Start the counter */ + #define GRTC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start the counter */ + #define GRTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define GRTC_TASKS_START_TASKS_START_Msk (0x1UL << GRTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define GRTC_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define GRTC_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define GRTC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* GRTC_TASKS_STOP: Stop the counter */ + #define GRTC_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop the counter */ + #define GRTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define GRTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << GRTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define GRTC_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define GRTC_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define GRTC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* GRTC_TASKS_CLEAR: Clear the counter */ + #define GRTC_TASKS_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLEAR register. */ + +/* TASKS_CLEAR @Bit 0 : Clear the counter */ + #define GRTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ + #define GRTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << GRTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ + #define GRTC_TASKS_CLEAR_TASKS_CLEAR_Min (0x1UL) /*!< Min enumerator value of TASKS_CLEAR field. */ + #define GRTC_TASKS_CLEAR_TASKS_CLEAR_Max (0x1UL) /*!< Max enumerator value of TASKS_CLEAR field. */ + #define GRTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */ + + +/* GRTC_TASKS_PWMSTART: Start the PWM */ + #define GRTC_TASKS_PWMSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PWMSTART register. */ + +/* TASKS_PWMSTART @Bit 0 : Start the PWM */ + #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Pos (0UL) /*!< Position of TASKS_PWMSTART field. */ + #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Msk (0x1UL << GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Pos) /*!< Bit mask of + TASKS_PWMSTART field.*/ + #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_PWMSTART field. */ + #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_PWMSTART field. */ + #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* GRTC_TASKS_PWMSTOP: Stop the PWM */ + #define GRTC_TASKS_PWMSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PWMSTOP register. */ + +/* TASKS_PWMSTOP @Bit 0 : Stop the PWM */ + #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Pos (0UL) /*!< Position of TASKS_PWMSTOP field. */ + #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Msk (0x1UL << GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Pos) /*!< Bit mask of TASKS_PWMSTOP + field.*/ + #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_PWMSTOP field. */ + #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_PWMSTOP field. */ + #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* GRTC_SUBSCRIBE_CAPTURE: Subscribe configuration for task CAPTURE[n] */ + #define GRTC_SUBSCRIBE_CAPTURE_MaxCount (12UL) /*!< Max size of SUBSCRIBE_CAPTURE[12] array. */ + #define GRTC_SUBSCRIBE_CAPTURE_MaxIndex (11UL) /*!< Max index of SUBSCRIBE_CAPTURE[12] array. */ + #define GRTC_SUBSCRIBE_CAPTURE_MinIndex (0UL) /*!< Min index of SUBSCRIBE_CAPTURE[12] array. */ + #define GRTC_SUBSCRIBE_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAPTURE[12] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CAPTURE[n] will subscribe to */ + #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << GRTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << GRTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* GRTC_EVENTS_COMPARE: Compare event on CC[n] match */ + #define GRTC_EVENTS_COMPARE_MaxCount (12UL) /*!< Max size of EVENTS_COMPARE[12] array. */ + #define GRTC_EVENTS_COMPARE_MaxIndex (11UL) /*!< Max index of EVENTS_COMPARE[12] array. */ + #define GRTC_EVENTS_COMPARE_MinIndex (0UL) /*!< Min index of EVENTS_COMPARE[12] array. */ + #define GRTC_EVENTS_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPARE[12] register. */ + +/* EVENTS_COMPARE @Bit 0 : Compare event on CC[n] match */ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of + EVENTS_COMPARE field.*/ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPARE field. */ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPARE field. */ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */ + + +/* GRTC_EVENTS_RTCOMPARESYNC: The GRTC low frequency timer is synchronized with the SYSCOUNTER */ + #define GRTC_EVENTS_RTCOMPARESYNC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RTCOMPARESYNC register. */ + +/* EVENTS_RTCOMPARESYNC @Bit 0 : The GRTC low frequency timer is synchronized with the SYSCOUNTER */ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Pos (0UL) /*!< Position of EVENTS_RTCOMPARESYNC field. */ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Msk (0x1UL << GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Pos) /*!< + Bit mask of EVENTS_RTCOMPARESYNC field.*/ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of EVENTS_RTCOMPARESYNC field. */ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of EVENTS_RTCOMPARESYNC field. */ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_NotGenerated (0x0UL) /*!< Event not generated */ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Generated (0x1UL) /*!< Event generated */ + + +/* GRTC_EVENTS_PWMPERIODEND: Event on end of each PWM period */ + #define GRTC_EVENTS_PWMPERIODEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PWMPERIODEND register. */ + +/* EVENTS_PWMPERIODEND @Bit 0 : Event on end of each PWM period */ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit + mask of EVENTS_PWMPERIODEND field.*/ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_PWMPERIODEND field. */ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_PWMPERIODEND field. */ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated */ + + +/* GRTC_EVENTS_PWMREADY: Event on STATUS.PWM.READY status changed to ready */ + #define GRTC_EVENTS_PWMREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PWMREADY register. */ + +/* EVENTS_PWMREADY @Bit 0 : Event on STATUS.PWM.READY status changed to ready */ + #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Pos (0UL) /*!< Position of EVENTS_PWMREADY field. */ + #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Msk (0x1UL << GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Pos) /*!< Bit mask of + EVENTS_PWMREADY field.*/ + #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_PWMREADY field. */ + #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_PWMREADY field. */ + #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_NotGenerated (0x0UL) /*!< Event not generated */ + #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Generated (0x1UL) /*!< Event generated */ + + +/* GRTC_EVENTS_CLKOUTREADY: Event on STATUS.CLKOUT.READY status changed to ready */ + #define GRTC_EVENTS_CLKOUTREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CLKOUTREADY register. */ + +/* EVENTS_CLKOUTREADY @Bit 0 : Event on STATUS.CLKOUT.READY status changed to ready */ + #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Pos (0UL) /*!< Position of EVENTS_CLKOUTREADY field. */ + #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Msk (0x1UL << GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Pos) /*!< Bit mask + of EVENTS_CLKOUTREADY field.*/ + #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_CLKOUTREADY field. */ + #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_CLKOUTREADY field. */ + #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_NotGenerated (0x0UL) /*!< Event not generated */ + #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Generated (0x1UL) /*!< Event generated */ + + +/* GRTC_PUBLISH_COMPARE: Publish configuration for event COMPARE[n] */ + #define GRTC_PUBLISH_COMPARE_MaxCount (12UL) /*!< Max size of PUBLISH_COMPARE[12] array. */ + #define GRTC_PUBLISH_COMPARE_MaxIndex (11UL) /*!< Max index of PUBLISH_COMPARE[12] array. */ + #define GRTC_PUBLISH_COMPARE_MinIndex (0UL) /*!< Min index of PUBLISH_COMPARE[12] array. */ + #define GRTC_PUBLISH_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPARE[12] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event COMPARE[n] will publish to */ + #define GRTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GRTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << GRTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GRTC_PUBLISH_COMPARE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GRTC_PUBLISH_COMPARE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GRTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ + #define GRTC_PUBLISH_COMPARE_EN_Msk (0x1UL << GRTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ + #define GRTC_PUBLISH_COMPARE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GRTC_PUBLISH_COMPARE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GRTC_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define GRTC_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* GRTC_PUBLISH_PWMREADY: Publish configuration for event PWMREADY */ + #define GRTC_PUBLISH_PWMREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PWMREADY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PWMREADY will publish to */ + #define GRTC_PUBLISH_PWMREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GRTC_PUBLISH_PWMREADY_CHIDX_Msk (0xFFUL << GRTC_PUBLISH_PWMREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GRTC_PUBLISH_PWMREADY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GRTC_PUBLISH_PWMREADY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GRTC_PUBLISH_PWMREADY_EN_Pos (31UL) /*!< Position of EN field. */ + #define GRTC_PUBLISH_PWMREADY_EN_Msk (0x1UL << GRTC_PUBLISH_PWMREADY_EN_Pos) /*!< Bit mask of EN field. */ + #define GRTC_PUBLISH_PWMREADY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GRTC_PUBLISH_PWMREADY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GRTC_PUBLISH_PWMREADY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define GRTC_PUBLISH_PWMREADY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* GRTC_PUBLISH_CLKOUTREADY: Publish configuration for event CLKOUTREADY */ + #define GRTC_PUBLISH_CLKOUTREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CLKOUTREADY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CLKOUTREADY will publish to */ + #define GRTC_PUBLISH_CLKOUTREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GRTC_PUBLISH_CLKOUTREADY_CHIDX_Msk (0xFFUL << GRTC_PUBLISH_CLKOUTREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GRTC_PUBLISH_CLKOUTREADY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GRTC_PUBLISH_CLKOUTREADY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GRTC_PUBLISH_CLKOUTREADY_EN_Pos (31UL) /*!< Position of EN field. */ + #define GRTC_PUBLISH_CLKOUTREADY_EN_Msk (0x1UL << GRTC_PUBLISH_CLKOUTREADY_EN_Pos) /*!< Bit mask of EN field. */ + #define GRTC_PUBLISH_CLKOUTREADY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GRTC_PUBLISH_CLKOUTREADY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GRTC_PUBLISH_CLKOUTREADY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define GRTC_PUBLISH_CLKOUTREADY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* GRTC_SHORTS: Shortcuts between local events and tasks */ + #define GRTC_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* RTCOMPARE_CLEAR @Bit 0 : Shortcut between event RTCOMPARE and task CLEAR */ + #define GRTC_SHORTS_RTCOMPARE_CLEAR_Pos (0UL) /*!< Position of RTCOMPARE_CLEAR field. */ + #define GRTC_SHORTS_RTCOMPARE_CLEAR_Msk (0x1UL << GRTC_SHORTS_RTCOMPARE_CLEAR_Pos) /*!< Bit mask of RTCOMPARE_CLEAR field. */ + #define GRTC_SHORTS_RTCOMPARE_CLEAR_Min (0x0UL) /*!< Min enumerator value of RTCOMPARE_CLEAR field. */ + #define GRTC_SHORTS_RTCOMPARE_CLEAR_Max (0x1UL) /*!< Max enumerator value of RTCOMPARE_CLEAR field. */ + #define GRTC_SHORTS_RTCOMPARE_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define GRTC_SHORTS_RTCOMPARE_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* GRTC_INTEN0: Enable or disable interrupt */ + #define GRTC_INTEN0_ResetValue (0x00000000UL) /*!< Reset value of INTEN0 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN0_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN0_COMPARE0_Msk (0x1UL << GRTC_INTEN0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN0_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN0_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN0_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN0_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN0_COMPARE1_Msk (0x1UL << GRTC_INTEN0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN0_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN0_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN0_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN0_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN0_COMPARE2_Msk (0x1UL << GRTC_INTEN0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN0_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN0_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN0_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN0_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN0_COMPARE3_Msk (0x1UL << GRTC_INTEN0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN0_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN0_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN0_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN0_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN0_COMPARE4_Msk (0x1UL << GRTC_INTEN0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN0_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN0_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN0_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN0_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN0_COMPARE5_Msk (0x1UL << GRTC_INTEN0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN0_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN0_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN0_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN0_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN0_COMPARE6_Msk (0x1UL << GRTC_INTEN0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN0_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN0_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN0_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN0_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN0_COMPARE7_Msk (0x1UL << GRTC_INTEN0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN0_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN0_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN0_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN0_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN0_COMPARE8_Msk (0x1UL << GRTC_INTEN0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN0_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN0_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN0_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN0_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN0_COMPARE9_Msk (0x1UL << GRTC_INTEN0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN0_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN0_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN0_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN0_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN0_COMPARE10_Msk (0x1UL << GRTC_INTEN0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN0_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN0_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN0_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN0_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN0_COMPARE11_Msk (0x1UL << GRTC_INTEN0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN0_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN0_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN0_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN0_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN0_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN0_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN0_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN0_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN0_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN0_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN0_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN0_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + +/* PWMREADY @Bit 29 : Enable or disable interrupt for event PWMREADY */ + #define GRTC_INTEN0_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTEN0_PWMREADY_Msk (0x1UL << GRTC_INTEN0_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTEN0_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTEN0_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTEN0_PWMREADY_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_PWMREADY_Enabled (0x1UL) /*!< Enable */ + +/* CLKOUTREADY @Bit 30 : Enable or disable interrupt for event CLKOUTREADY */ + #define GRTC_INTEN0_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTEN0_CLKOUTREADY_Msk (0x1UL << GRTC_INTEN0_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTEN0_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTEN0_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTEN0_CLKOUTREADY_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_CLKOUTREADY_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET0: Enable interrupt */ + #define GRTC_INTENSET0_ResetValue (0x00000000UL) /*!< Reset value of INTENSET0 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET0_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET0_COMPARE0_Msk (0x1UL << GRTC_INTENSET0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET0_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET0_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET0_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET0_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET0_COMPARE1_Msk (0x1UL << GRTC_INTENSET0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET0_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET0_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET0_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET0_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET0_COMPARE2_Msk (0x1UL << GRTC_INTENSET0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET0_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET0_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET0_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET0_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET0_COMPARE3_Msk (0x1UL << GRTC_INTENSET0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET0_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET0_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET0_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET0_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET0_COMPARE4_Msk (0x1UL << GRTC_INTENSET0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET0_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET0_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET0_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET0_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET0_COMPARE5_Msk (0x1UL << GRTC_INTENSET0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET0_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET0_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET0_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET0_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET0_COMPARE6_Msk (0x1UL << GRTC_INTENSET0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET0_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET0_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET0_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET0_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET0_COMPARE7_Msk (0x1UL << GRTC_INTENSET0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET0_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET0_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET0_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET0_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET0_COMPARE8_Msk (0x1UL << GRTC_INTENSET0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET0_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET0_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET0_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET0_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET0_COMPARE9_Msk (0x1UL << GRTC_INTENSET0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET0_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET0_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET0_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET0_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET0_COMPARE10_Msk (0x1UL << GRTC_INTENSET0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET0_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET0_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET0_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET0_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET0_COMPARE11_Msk (0x1UL << GRTC_INTENSET0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET0_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET0_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET0_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET0_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET0_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET0_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET0_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET0_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMREADY @Bit 29 : Write '1' to enable interrupt for event PWMREADY */ + #define GRTC_INTENSET0_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTENSET0_PWMREADY_Msk (0x1UL << GRTC_INTENSET0_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTENSET0_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTENSET0_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTENSET0_PWMREADY_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_PWMREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_PWMREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CLKOUTREADY @Bit 30 : Write '1' to enable interrupt for event CLKOUTREADY */ + #define GRTC_INTENSET0_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTENSET0_CLKOUTREADY_Msk (0x1UL << GRTC_INTENSET0_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTENSET0_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENSET0_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENSET0_CLKOUTREADY_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR0: Disable interrupt */ + #define GRTC_INTENCLR0_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR0 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR0_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR0_COMPARE0_Msk (0x1UL << GRTC_INTENCLR0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR0_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR0_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR0_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR0_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR0_COMPARE1_Msk (0x1UL << GRTC_INTENCLR0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR0_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR0_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR0_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR0_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR0_COMPARE2_Msk (0x1UL << GRTC_INTENCLR0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR0_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR0_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR0_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR0_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR0_COMPARE3_Msk (0x1UL << GRTC_INTENCLR0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR0_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR0_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR0_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR0_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR0_COMPARE4_Msk (0x1UL << GRTC_INTENCLR0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR0_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR0_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR0_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR0_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR0_COMPARE5_Msk (0x1UL << GRTC_INTENCLR0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR0_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR0_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR0_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR0_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR0_COMPARE6_Msk (0x1UL << GRTC_INTENCLR0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR0_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR0_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR0_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR0_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR0_COMPARE7_Msk (0x1UL << GRTC_INTENCLR0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR0_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR0_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR0_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR0_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR0_COMPARE8_Msk (0x1UL << GRTC_INTENCLR0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR0_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR0_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR0_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR0_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR0_COMPARE9_Msk (0x1UL << GRTC_INTENCLR0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR0_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR0_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR0_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR0_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR0_COMPARE10_Msk (0x1UL << GRTC_INTENCLR0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR0_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR0_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR0_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR0_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR0_COMPARE11_Msk (0x1UL << GRTC_INTENCLR0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR0_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR0_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR0_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR0_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR0_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR0_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR0_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR0_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMREADY @Bit 29 : Write '1' to disable interrupt for event PWMREADY */ + #define GRTC_INTENCLR0_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTENCLR0_PWMREADY_Msk (0x1UL << GRTC_INTENCLR0_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTENCLR0_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTENCLR0_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTENCLR0_PWMREADY_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_PWMREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_PWMREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CLKOUTREADY @Bit 30 : Write '1' to disable interrupt for event CLKOUTREADY */ + #define GRTC_INTENCLR0_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTENCLR0_CLKOUTREADY_Msk (0x1UL << GRTC_INTENCLR0_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTENCLR0_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENCLR0_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENCLR0_CLKOUTREADY_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND0: Pending interrupts */ + #define GRTC_INTPEND0_ResetValue (0x00000000UL) /*!< Reset value of INTPEND0 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND0_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND0_COMPARE0_Msk (0x1UL << GRTC_INTPEND0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND0_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND0_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND0_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND0_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND0_COMPARE1_Msk (0x1UL << GRTC_INTPEND0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND0_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND0_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND0_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND0_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND0_COMPARE2_Msk (0x1UL << GRTC_INTPEND0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND0_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND0_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND0_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND0_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND0_COMPARE3_Msk (0x1UL << GRTC_INTPEND0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND0_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND0_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND0_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND0_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND0_COMPARE4_Msk (0x1UL << GRTC_INTPEND0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND0_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND0_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND0_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND0_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND0_COMPARE5_Msk (0x1UL << GRTC_INTPEND0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND0_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND0_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND0_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND0_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND0_COMPARE6_Msk (0x1UL << GRTC_INTPEND0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND0_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND0_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND0_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND0_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND0_COMPARE7_Msk (0x1UL << GRTC_INTPEND0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND0_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND0_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND0_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND0_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND0_COMPARE8_Msk (0x1UL << GRTC_INTPEND0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND0_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND0_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND0_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND0_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND0_COMPARE9_Msk (0x1UL << GRTC_INTPEND0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND0_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND0_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND0_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND0_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND0_COMPARE10_Msk (0x1UL << GRTC_INTPEND0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND0_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND0_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND0_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND0_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND0_COMPARE11_Msk (0x1UL << GRTC_INTPEND0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND0_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND0_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND0_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND0_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND0_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND0_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND0_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND0_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND0_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND0_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND0_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND0_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMREADY @Bit 29 : Read pending status of interrupt for event PWMREADY */ + #define GRTC_INTPEND0_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTPEND0_PWMREADY_Msk (0x1UL << GRTC_INTPEND0_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTPEND0_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTPEND0_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTPEND0_PWMREADY_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_PWMREADY_Pending (0x1UL) /*!< Read: Pending */ + +/* CLKOUTREADY @Bit 30 : Read pending status of interrupt for event CLKOUTREADY */ + #define GRTC_INTPEND0_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTPEND0_CLKOUTREADY_Msk (0x1UL << GRTC_INTPEND0_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTPEND0_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTPEND0_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTPEND0_CLKOUTREADY_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_CLKOUTREADY_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN1: Enable or disable interrupt */ + #define GRTC_INTEN1_ResetValue (0x00000000UL) /*!< Reset value of INTEN1 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN1_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN1_COMPARE0_Msk (0x1UL << GRTC_INTEN1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN1_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN1_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN1_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN1_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN1_COMPARE1_Msk (0x1UL << GRTC_INTEN1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN1_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN1_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN1_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN1_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN1_COMPARE2_Msk (0x1UL << GRTC_INTEN1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN1_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN1_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN1_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN1_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN1_COMPARE3_Msk (0x1UL << GRTC_INTEN1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN1_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN1_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN1_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN1_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN1_COMPARE4_Msk (0x1UL << GRTC_INTEN1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN1_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN1_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN1_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN1_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN1_COMPARE5_Msk (0x1UL << GRTC_INTEN1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN1_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN1_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN1_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN1_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN1_COMPARE6_Msk (0x1UL << GRTC_INTEN1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN1_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN1_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN1_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN1_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN1_COMPARE7_Msk (0x1UL << GRTC_INTEN1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN1_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN1_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN1_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN1_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN1_COMPARE8_Msk (0x1UL << GRTC_INTEN1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN1_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN1_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN1_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN1_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN1_COMPARE9_Msk (0x1UL << GRTC_INTEN1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN1_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN1_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN1_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN1_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN1_COMPARE10_Msk (0x1UL << GRTC_INTEN1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN1_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN1_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN1_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN1_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN1_COMPARE11_Msk (0x1UL << GRTC_INTEN1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN1_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN1_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN1_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN1_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN1_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN1_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN1_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN1_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN1_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN1_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN1_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN1_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + +/* PWMREADY @Bit 29 : Enable or disable interrupt for event PWMREADY */ + #define GRTC_INTEN1_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTEN1_PWMREADY_Msk (0x1UL << GRTC_INTEN1_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTEN1_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTEN1_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTEN1_PWMREADY_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_PWMREADY_Enabled (0x1UL) /*!< Enable */ + +/* CLKOUTREADY @Bit 30 : Enable or disable interrupt for event CLKOUTREADY */ + #define GRTC_INTEN1_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTEN1_CLKOUTREADY_Msk (0x1UL << GRTC_INTEN1_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTEN1_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTEN1_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTEN1_CLKOUTREADY_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_CLKOUTREADY_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET1: Enable interrupt */ + #define GRTC_INTENSET1_ResetValue (0x00000000UL) /*!< Reset value of INTENSET1 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET1_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET1_COMPARE0_Msk (0x1UL << GRTC_INTENSET1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET1_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET1_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET1_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET1_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET1_COMPARE1_Msk (0x1UL << GRTC_INTENSET1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET1_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET1_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET1_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET1_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET1_COMPARE2_Msk (0x1UL << GRTC_INTENSET1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET1_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET1_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET1_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET1_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET1_COMPARE3_Msk (0x1UL << GRTC_INTENSET1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET1_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET1_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET1_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET1_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET1_COMPARE4_Msk (0x1UL << GRTC_INTENSET1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET1_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET1_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET1_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET1_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET1_COMPARE5_Msk (0x1UL << GRTC_INTENSET1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET1_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET1_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET1_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET1_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET1_COMPARE6_Msk (0x1UL << GRTC_INTENSET1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET1_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET1_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET1_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET1_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET1_COMPARE7_Msk (0x1UL << GRTC_INTENSET1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET1_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET1_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET1_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET1_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET1_COMPARE8_Msk (0x1UL << GRTC_INTENSET1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET1_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET1_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET1_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET1_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET1_COMPARE9_Msk (0x1UL << GRTC_INTENSET1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET1_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET1_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET1_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET1_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET1_COMPARE10_Msk (0x1UL << GRTC_INTENSET1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET1_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET1_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET1_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET1_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET1_COMPARE11_Msk (0x1UL << GRTC_INTENSET1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET1_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET1_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET1_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET1_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET1_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET1_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET1_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET1_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMREADY @Bit 29 : Write '1' to enable interrupt for event PWMREADY */ + #define GRTC_INTENSET1_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTENSET1_PWMREADY_Msk (0x1UL << GRTC_INTENSET1_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTENSET1_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTENSET1_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTENSET1_PWMREADY_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_PWMREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_PWMREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CLKOUTREADY @Bit 30 : Write '1' to enable interrupt for event CLKOUTREADY */ + #define GRTC_INTENSET1_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTENSET1_CLKOUTREADY_Msk (0x1UL << GRTC_INTENSET1_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTENSET1_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENSET1_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENSET1_CLKOUTREADY_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR1: Disable interrupt */ + #define GRTC_INTENCLR1_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR1 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR1_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR1_COMPARE0_Msk (0x1UL << GRTC_INTENCLR1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR1_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR1_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR1_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR1_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR1_COMPARE1_Msk (0x1UL << GRTC_INTENCLR1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR1_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR1_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR1_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR1_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR1_COMPARE2_Msk (0x1UL << GRTC_INTENCLR1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR1_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR1_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR1_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR1_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR1_COMPARE3_Msk (0x1UL << GRTC_INTENCLR1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR1_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR1_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR1_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR1_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR1_COMPARE4_Msk (0x1UL << GRTC_INTENCLR1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR1_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR1_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR1_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR1_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR1_COMPARE5_Msk (0x1UL << GRTC_INTENCLR1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR1_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR1_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR1_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR1_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR1_COMPARE6_Msk (0x1UL << GRTC_INTENCLR1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR1_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR1_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR1_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR1_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR1_COMPARE7_Msk (0x1UL << GRTC_INTENCLR1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR1_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR1_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR1_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR1_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR1_COMPARE8_Msk (0x1UL << GRTC_INTENCLR1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR1_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR1_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR1_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR1_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR1_COMPARE9_Msk (0x1UL << GRTC_INTENCLR1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR1_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR1_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR1_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR1_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR1_COMPARE10_Msk (0x1UL << GRTC_INTENCLR1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR1_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR1_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR1_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR1_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR1_COMPARE11_Msk (0x1UL << GRTC_INTENCLR1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR1_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR1_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR1_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR1_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR1_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR1_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR1_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR1_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMREADY @Bit 29 : Write '1' to disable interrupt for event PWMREADY */ + #define GRTC_INTENCLR1_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTENCLR1_PWMREADY_Msk (0x1UL << GRTC_INTENCLR1_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTENCLR1_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTENCLR1_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTENCLR1_PWMREADY_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_PWMREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_PWMREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CLKOUTREADY @Bit 30 : Write '1' to disable interrupt for event CLKOUTREADY */ + #define GRTC_INTENCLR1_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTENCLR1_CLKOUTREADY_Msk (0x1UL << GRTC_INTENCLR1_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTENCLR1_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENCLR1_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENCLR1_CLKOUTREADY_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND1: Pending interrupts */ + #define GRTC_INTPEND1_ResetValue (0x00000000UL) /*!< Reset value of INTPEND1 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND1_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND1_COMPARE0_Msk (0x1UL << GRTC_INTPEND1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND1_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND1_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND1_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND1_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND1_COMPARE1_Msk (0x1UL << GRTC_INTPEND1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND1_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND1_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND1_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND1_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND1_COMPARE2_Msk (0x1UL << GRTC_INTPEND1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND1_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND1_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND1_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND1_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND1_COMPARE3_Msk (0x1UL << GRTC_INTPEND1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND1_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND1_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND1_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND1_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND1_COMPARE4_Msk (0x1UL << GRTC_INTPEND1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND1_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND1_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND1_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND1_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND1_COMPARE5_Msk (0x1UL << GRTC_INTPEND1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND1_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND1_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND1_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND1_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND1_COMPARE6_Msk (0x1UL << GRTC_INTPEND1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND1_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND1_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND1_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND1_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND1_COMPARE7_Msk (0x1UL << GRTC_INTPEND1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND1_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND1_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND1_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND1_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND1_COMPARE8_Msk (0x1UL << GRTC_INTPEND1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND1_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND1_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND1_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND1_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND1_COMPARE9_Msk (0x1UL << GRTC_INTPEND1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND1_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND1_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND1_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND1_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND1_COMPARE10_Msk (0x1UL << GRTC_INTPEND1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND1_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND1_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND1_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND1_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND1_COMPARE11_Msk (0x1UL << GRTC_INTPEND1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND1_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND1_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND1_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND1_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND1_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND1_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND1_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND1_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND1_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND1_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND1_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND1_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMREADY @Bit 29 : Read pending status of interrupt for event PWMREADY */ + #define GRTC_INTPEND1_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTPEND1_PWMREADY_Msk (0x1UL << GRTC_INTPEND1_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTPEND1_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTPEND1_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTPEND1_PWMREADY_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_PWMREADY_Pending (0x1UL) /*!< Read: Pending */ + +/* CLKOUTREADY @Bit 30 : Read pending status of interrupt for event CLKOUTREADY */ + #define GRTC_INTPEND1_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTPEND1_CLKOUTREADY_Msk (0x1UL << GRTC_INTPEND1_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTPEND1_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTPEND1_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTPEND1_CLKOUTREADY_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_CLKOUTREADY_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN2: Enable or disable interrupt */ + #define GRTC_INTEN2_ResetValue (0x00000000UL) /*!< Reset value of INTEN2 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN2_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN2_COMPARE0_Msk (0x1UL << GRTC_INTEN2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN2_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN2_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN2_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN2_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN2_COMPARE1_Msk (0x1UL << GRTC_INTEN2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN2_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN2_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN2_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN2_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN2_COMPARE2_Msk (0x1UL << GRTC_INTEN2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN2_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN2_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN2_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN2_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN2_COMPARE3_Msk (0x1UL << GRTC_INTEN2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN2_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN2_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN2_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN2_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN2_COMPARE4_Msk (0x1UL << GRTC_INTEN2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN2_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN2_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN2_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN2_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN2_COMPARE5_Msk (0x1UL << GRTC_INTEN2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN2_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN2_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN2_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN2_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN2_COMPARE6_Msk (0x1UL << GRTC_INTEN2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN2_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN2_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN2_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN2_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN2_COMPARE7_Msk (0x1UL << GRTC_INTEN2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN2_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN2_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN2_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN2_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN2_COMPARE8_Msk (0x1UL << GRTC_INTEN2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN2_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN2_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN2_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN2_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN2_COMPARE9_Msk (0x1UL << GRTC_INTEN2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN2_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN2_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN2_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN2_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN2_COMPARE10_Msk (0x1UL << GRTC_INTEN2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN2_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN2_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN2_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN2_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN2_COMPARE11_Msk (0x1UL << GRTC_INTEN2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN2_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN2_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN2_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN2_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN2_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN2_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN2_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN2_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN2_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN2_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN2_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN2_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + +/* PWMREADY @Bit 29 : Enable or disable interrupt for event PWMREADY */ + #define GRTC_INTEN2_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTEN2_PWMREADY_Msk (0x1UL << GRTC_INTEN2_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTEN2_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTEN2_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTEN2_PWMREADY_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_PWMREADY_Enabled (0x1UL) /*!< Enable */ + +/* CLKOUTREADY @Bit 30 : Enable or disable interrupt for event CLKOUTREADY */ + #define GRTC_INTEN2_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTEN2_CLKOUTREADY_Msk (0x1UL << GRTC_INTEN2_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTEN2_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTEN2_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTEN2_CLKOUTREADY_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_CLKOUTREADY_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET2: Enable interrupt */ + #define GRTC_INTENSET2_ResetValue (0x00000000UL) /*!< Reset value of INTENSET2 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET2_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET2_COMPARE0_Msk (0x1UL << GRTC_INTENSET2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET2_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET2_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET2_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET2_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET2_COMPARE1_Msk (0x1UL << GRTC_INTENSET2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET2_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET2_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET2_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET2_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET2_COMPARE2_Msk (0x1UL << GRTC_INTENSET2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET2_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET2_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET2_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET2_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET2_COMPARE3_Msk (0x1UL << GRTC_INTENSET2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET2_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET2_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET2_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET2_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET2_COMPARE4_Msk (0x1UL << GRTC_INTENSET2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET2_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET2_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET2_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET2_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET2_COMPARE5_Msk (0x1UL << GRTC_INTENSET2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET2_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET2_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET2_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET2_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET2_COMPARE6_Msk (0x1UL << GRTC_INTENSET2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET2_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET2_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET2_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET2_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET2_COMPARE7_Msk (0x1UL << GRTC_INTENSET2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET2_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET2_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET2_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET2_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET2_COMPARE8_Msk (0x1UL << GRTC_INTENSET2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET2_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET2_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET2_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET2_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET2_COMPARE9_Msk (0x1UL << GRTC_INTENSET2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET2_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET2_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET2_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET2_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET2_COMPARE10_Msk (0x1UL << GRTC_INTENSET2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET2_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET2_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET2_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET2_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET2_COMPARE11_Msk (0x1UL << GRTC_INTENSET2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET2_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET2_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET2_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET2_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET2_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET2_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET2_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET2_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMREADY @Bit 29 : Write '1' to enable interrupt for event PWMREADY */ + #define GRTC_INTENSET2_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTENSET2_PWMREADY_Msk (0x1UL << GRTC_INTENSET2_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTENSET2_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTENSET2_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTENSET2_PWMREADY_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_PWMREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_PWMREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CLKOUTREADY @Bit 30 : Write '1' to enable interrupt for event CLKOUTREADY */ + #define GRTC_INTENSET2_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTENSET2_CLKOUTREADY_Msk (0x1UL << GRTC_INTENSET2_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTENSET2_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENSET2_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENSET2_CLKOUTREADY_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR2: Disable interrupt */ + #define GRTC_INTENCLR2_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR2 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR2_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR2_COMPARE0_Msk (0x1UL << GRTC_INTENCLR2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR2_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR2_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR2_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR2_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR2_COMPARE1_Msk (0x1UL << GRTC_INTENCLR2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR2_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR2_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR2_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR2_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR2_COMPARE2_Msk (0x1UL << GRTC_INTENCLR2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR2_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR2_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR2_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR2_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR2_COMPARE3_Msk (0x1UL << GRTC_INTENCLR2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR2_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR2_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR2_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR2_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR2_COMPARE4_Msk (0x1UL << GRTC_INTENCLR2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR2_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR2_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR2_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR2_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR2_COMPARE5_Msk (0x1UL << GRTC_INTENCLR2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR2_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR2_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR2_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR2_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR2_COMPARE6_Msk (0x1UL << GRTC_INTENCLR2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR2_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR2_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR2_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR2_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR2_COMPARE7_Msk (0x1UL << GRTC_INTENCLR2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR2_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR2_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR2_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR2_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR2_COMPARE8_Msk (0x1UL << GRTC_INTENCLR2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR2_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR2_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR2_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR2_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR2_COMPARE9_Msk (0x1UL << GRTC_INTENCLR2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR2_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR2_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR2_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR2_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR2_COMPARE10_Msk (0x1UL << GRTC_INTENCLR2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR2_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR2_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR2_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR2_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR2_COMPARE11_Msk (0x1UL << GRTC_INTENCLR2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR2_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR2_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR2_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR2_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR2_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR2_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR2_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR2_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMREADY @Bit 29 : Write '1' to disable interrupt for event PWMREADY */ + #define GRTC_INTENCLR2_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTENCLR2_PWMREADY_Msk (0x1UL << GRTC_INTENCLR2_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTENCLR2_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTENCLR2_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTENCLR2_PWMREADY_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_PWMREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_PWMREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CLKOUTREADY @Bit 30 : Write '1' to disable interrupt for event CLKOUTREADY */ + #define GRTC_INTENCLR2_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTENCLR2_CLKOUTREADY_Msk (0x1UL << GRTC_INTENCLR2_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTENCLR2_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENCLR2_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENCLR2_CLKOUTREADY_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND2: Pending interrupts */ + #define GRTC_INTPEND2_ResetValue (0x00000000UL) /*!< Reset value of INTPEND2 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND2_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND2_COMPARE0_Msk (0x1UL << GRTC_INTPEND2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND2_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND2_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND2_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND2_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND2_COMPARE1_Msk (0x1UL << GRTC_INTPEND2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND2_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND2_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND2_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND2_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND2_COMPARE2_Msk (0x1UL << GRTC_INTPEND2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND2_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND2_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND2_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND2_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND2_COMPARE3_Msk (0x1UL << GRTC_INTPEND2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND2_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND2_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND2_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND2_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND2_COMPARE4_Msk (0x1UL << GRTC_INTPEND2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND2_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND2_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND2_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND2_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND2_COMPARE5_Msk (0x1UL << GRTC_INTPEND2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND2_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND2_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND2_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND2_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND2_COMPARE6_Msk (0x1UL << GRTC_INTPEND2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND2_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND2_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND2_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND2_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND2_COMPARE7_Msk (0x1UL << GRTC_INTPEND2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND2_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND2_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND2_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND2_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND2_COMPARE8_Msk (0x1UL << GRTC_INTPEND2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND2_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND2_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND2_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND2_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND2_COMPARE9_Msk (0x1UL << GRTC_INTPEND2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND2_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND2_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND2_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND2_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND2_COMPARE10_Msk (0x1UL << GRTC_INTPEND2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND2_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND2_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND2_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND2_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND2_COMPARE11_Msk (0x1UL << GRTC_INTPEND2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND2_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND2_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND2_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND2_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND2_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND2_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND2_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND2_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND2_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND2_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND2_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND2_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMREADY @Bit 29 : Read pending status of interrupt for event PWMREADY */ + #define GRTC_INTPEND2_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTPEND2_PWMREADY_Msk (0x1UL << GRTC_INTPEND2_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTPEND2_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTPEND2_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTPEND2_PWMREADY_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_PWMREADY_Pending (0x1UL) /*!< Read: Pending */ + +/* CLKOUTREADY @Bit 30 : Read pending status of interrupt for event CLKOUTREADY */ + #define GRTC_INTPEND2_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTPEND2_CLKOUTREADY_Msk (0x1UL << GRTC_INTPEND2_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTPEND2_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTPEND2_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTPEND2_CLKOUTREADY_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_CLKOUTREADY_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN3: Enable or disable interrupt */ + #define GRTC_INTEN3_ResetValue (0x00000000UL) /*!< Reset value of INTEN3 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN3_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN3_COMPARE0_Msk (0x1UL << GRTC_INTEN3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN3_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN3_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN3_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN3_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN3_COMPARE1_Msk (0x1UL << GRTC_INTEN3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN3_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN3_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN3_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN3_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN3_COMPARE2_Msk (0x1UL << GRTC_INTEN3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN3_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN3_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN3_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN3_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN3_COMPARE3_Msk (0x1UL << GRTC_INTEN3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN3_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN3_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN3_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN3_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN3_COMPARE4_Msk (0x1UL << GRTC_INTEN3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN3_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN3_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN3_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN3_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN3_COMPARE5_Msk (0x1UL << GRTC_INTEN3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN3_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN3_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN3_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN3_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN3_COMPARE6_Msk (0x1UL << GRTC_INTEN3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN3_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN3_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN3_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN3_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN3_COMPARE7_Msk (0x1UL << GRTC_INTEN3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN3_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN3_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN3_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN3_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN3_COMPARE8_Msk (0x1UL << GRTC_INTEN3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN3_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN3_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN3_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN3_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN3_COMPARE9_Msk (0x1UL << GRTC_INTEN3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN3_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN3_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN3_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN3_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN3_COMPARE10_Msk (0x1UL << GRTC_INTEN3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN3_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN3_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN3_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN3_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN3_COMPARE11_Msk (0x1UL << GRTC_INTEN3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN3_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN3_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN3_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN3_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN3_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN3_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN3_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN3_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN3_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN3_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN3_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN3_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + +/* PWMREADY @Bit 29 : Enable or disable interrupt for event PWMREADY */ + #define GRTC_INTEN3_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTEN3_PWMREADY_Msk (0x1UL << GRTC_INTEN3_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTEN3_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTEN3_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTEN3_PWMREADY_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_PWMREADY_Enabled (0x1UL) /*!< Enable */ + +/* CLKOUTREADY @Bit 30 : Enable or disable interrupt for event CLKOUTREADY */ + #define GRTC_INTEN3_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTEN3_CLKOUTREADY_Msk (0x1UL << GRTC_INTEN3_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTEN3_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTEN3_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTEN3_CLKOUTREADY_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_CLKOUTREADY_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET3: Enable interrupt */ + #define GRTC_INTENSET3_ResetValue (0x00000000UL) /*!< Reset value of INTENSET3 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET3_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET3_COMPARE0_Msk (0x1UL << GRTC_INTENSET3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET3_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET3_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET3_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET3_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET3_COMPARE1_Msk (0x1UL << GRTC_INTENSET3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET3_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET3_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET3_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET3_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET3_COMPARE2_Msk (0x1UL << GRTC_INTENSET3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET3_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET3_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET3_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET3_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET3_COMPARE3_Msk (0x1UL << GRTC_INTENSET3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET3_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET3_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET3_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET3_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET3_COMPARE4_Msk (0x1UL << GRTC_INTENSET3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET3_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET3_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET3_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET3_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET3_COMPARE5_Msk (0x1UL << GRTC_INTENSET3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET3_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET3_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET3_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET3_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET3_COMPARE6_Msk (0x1UL << GRTC_INTENSET3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET3_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET3_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET3_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET3_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET3_COMPARE7_Msk (0x1UL << GRTC_INTENSET3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET3_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET3_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET3_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET3_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET3_COMPARE8_Msk (0x1UL << GRTC_INTENSET3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET3_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET3_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET3_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET3_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET3_COMPARE9_Msk (0x1UL << GRTC_INTENSET3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET3_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET3_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET3_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET3_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET3_COMPARE10_Msk (0x1UL << GRTC_INTENSET3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET3_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET3_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET3_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET3_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET3_COMPARE11_Msk (0x1UL << GRTC_INTENSET3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET3_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET3_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET3_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET3_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET3_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET3_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET3_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET3_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMREADY @Bit 29 : Write '1' to enable interrupt for event PWMREADY */ + #define GRTC_INTENSET3_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTENSET3_PWMREADY_Msk (0x1UL << GRTC_INTENSET3_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTENSET3_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTENSET3_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTENSET3_PWMREADY_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_PWMREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_PWMREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CLKOUTREADY @Bit 30 : Write '1' to enable interrupt for event CLKOUTREADY */ + #define GRTC_INTENSET3_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTENSET3_CLKOUTREADY_Msk (0x1UL << GRTC_INTENSET3_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTENSET3_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENSET3_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENSET3_CLKOUTREADY_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR3: Disable interrupt */ + #define GRTC_INTENCLR3_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR3 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR3_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR3_COMPARE0_Msk (0x1UL << GRTC_INTENCLR3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR3_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR3_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR3_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR3_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR3_COMPARE1_Msk (0x1UL << GRTC_INTENCLR3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR3_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR3_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR3_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR3_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR3_COMPARE2_Msk (0x1UL << GRTC_INTENCLR3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR3_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR3_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR3_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR3_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR3_COMPARE3_Msk (0x1UL << GRTC_INTENCLR3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR3_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR3_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR3_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR3_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR3_COMPARE4_Msk (0x1UL << GRTC_INTENCLR3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR3_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR3_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR3_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR3_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR3_COMPARE5_Msk (0x1UL << GRTC_INTENCLR3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR3_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR3_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR3_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR3_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR3_COMPARE6_Msk (0x1UL << GRTC_INTENCLR3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR3_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR3_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR3_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR3_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR3_COMPARE7_Msk (0x1UL << GRTC_INTENCLR3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR3_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR3_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR3_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR3_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR3_COMPARE8_Msk (0x1UL << GRTC_INTENCLR3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR3_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR3_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR3_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR3_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR3_COMPARE9_Msk (0x1UL << GRTC_INTENCLR3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR3_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR3_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR3_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR3_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR3_COMPARE10_Msk (0x1UL << GRTC_INTENCLR3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR3_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR3_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR3_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR3_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR3_COMPARE11_Msk (0x1UL << GRTC_INTENCLR3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR3_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR3_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR3_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR3_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR3_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR3_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR3_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR3_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMREADY @Bit 29 : Write '1' to disable interrupt for event PWMREADY */ + #define GRTC_INTENCLR3_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTENCLR3_PWMREADY_Msk (0x1UL << GRTC_INTENCLR3_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTENCLR3_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTENCLR3_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTENCLR3_PWMREADY_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_PWMREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_PWMREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CLKOUTREADY @Bit 30 : Write '1' to disable interrupt for event CLKOUTREADY */ + #define GRTC_INTENCLR3_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTENCLR3_CLKOUTREADY_Msk (0x1UL << GRTC_INTENCLR3_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTENCLR3_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENCLR3_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTENCLR3_CLKOUTREADY_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND3: Pending interrupts */ + #define GRTC_INTPEND3_ResetValue (0x00000000UL) /*!< Reset value of INTPEND3 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND3_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND3_COMPARE0_Msk (0x1UL << GRTC_INTPEND3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND3_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND3_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND3_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND3_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND3_COMPARE1_Msk (0x1UL << GRTC_INTPEND3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND3_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND3_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND3_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND3_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND3_COMPARE2_Msk (0x1UL << GRTC_INTPEND3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND3_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND3_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND3_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND3_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND3_COMPARE3_Msk (0x1UL << GRTC_INTPEND3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND3_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND3_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND3_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND3_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND3_COMPARE4_Msk (0x1UL << GRTC_INTPEND3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND3_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND3_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND3_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND3_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND3_COMPARE5_Msk (0x1UL << GRTC_INTPEND3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND3_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND3_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND3_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND3_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND3_COMPARE6_Msk (0x1UL << GRTC_INTPEND3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND3_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND3_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND3_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND3_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND3_COMPARE7_Msk (0x1UL << GRTC_INTPEND3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND3_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND3_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND3_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND3_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND3_COMPARE8_Msk (0x1UL << GRTC_INTPEND3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND3_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND3_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND3_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND3_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND3_COMPARE9_Msk (0x1UL << GRTC_INTPEND3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND3_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND3_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND3_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND3_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND3_COMPARE10_Msk (0x1UL << GRTC_INTPEND3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND3_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND3_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND3_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND3_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND3_COMPARE11_Msk (0x1UL << GRTC_INTPEND3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND3_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND3_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND3_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND3_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND3_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND3_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND3_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND3_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND3_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND3_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND3_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND3_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMREADY @Bit 29 : Read pending status of interrupt for event PWMREADY */ + #define GRTC_INTPEND3_PWMREADY_Pos (29UL) /*!< Position of PWMREADY field. */ + #define GRTC_INTPEND3_PWMREADY_Msk (0x1UL << GRTC_INTPEND3_PWMREADY_Pos) /*!< Bit mask of PWMREADY field. */ + #define GRTC_INTPEND3_PWMREADY_Min (0x0UL) /*!< Min enumerator value of PWMREADY field. */ + #define GRTC_INTPEND3_PWMREADY_Max (0x1UL) /*!< Max enumerator value of PWMREADY field. */ + #define GRTC_INTPEND3_PWMREADY_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_PWMREADY_Pending (0x1UL) /*!< Read: Pending */ + +/* CLKOUTREADY @Bit 30 : Read pending status of interrupt for event CLKOUTREADY */ + #define GRTC_INTPEND3_CLKOUTREADY_Pos (30UL) /*!< Position of CLKOUTREADY field. */ + #define GRTC_INTPEND3_CLKOUTREADY_Msk (0x1UL << GRTC_INTPEND3_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field. */ + #define GRTC_INTPEND3_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of CLKOUTREADY field. */ + #define GRTC_INTPEND3_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of CLKOUTREADY field. */ + #define GRTC_INTPEND3_CLKOUTREADY_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_CLKOUTREADY_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_EVTEN: Enable or disable event routing */ + #define GRTC_EVTEN_ResetValue (0x00000000UL) /*!< Reset value of EVTEN register. */ + +/* PWMPERIODEND @Bit 27 : Enable or disable event routing for event PWMPERIODEND */ + #define GRTC_EVTEN_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_EVTEN_PWMPERIODEND_Msk (0x1UL << GRTC_EVTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_EVTEN_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTEN_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTEN_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_EVTEN_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_EVTENSET: Enable event routing */ + #define GRTC_EVTENSET_ResetValue (0x00000000UL) /*!< Reset value of EVTENSET register. */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable event routing for event PWMPERIODEND */ + #define GRTC_EVTENSET_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_EVTENSET_PWMPERIODEND_Msk (0x1UL << GRTC_EVTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_EVTENSET_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTENSET_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_EVTENSET_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + #define GRTC_EVTENSET_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + + +/* GRTC_EVTENCLR: Disable event routing */ + #define GRTC_EVTENCLR_ResetValue (0x00000000UL) /*!< Reset value of EVTENCLR register. */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable event routing for event PWMPERIODEND */ + #define GRTC_EVTENCLR_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_EVTENCLR_PWMPERIODEND_Msk (0x1UL << GRTC_EVTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_EVTENCLR_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTENCLR_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_EVTENCLR_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + #define GRTC_EVTENCLR_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + + +/* GRTC_MODE: Counter mode selection */ + #define GRTC_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* AUTOEN @Bit 0 : Automatic enable to keep the SYSCOUNTER active. */ + #define GRTC_MODE_AUTOEN_Pos (0UL) /*!< Position of AUTOEN field. */ + #define GRTC_MODE_AUTOEN_Msk (0x1UL << GRTC_MODE_AUTOEN_Pos) /*!< Bit mask of AUTOEN field. */ + #define GRTC_MODE_AUTOEN_Min (0x0UL) /*!< Min enumerator value of AUTOEN field. */ + #define GRTC_MODE_AUTOEN_Max (0x1UL) /*!< Max enumerator value of AUTOEN field. */ + #define GRTC_MODE_AUTOEN_Default (0x0UL) /*!< Default configuration to keep the SYSCOUNTER active. */ + #define GRTC_MODE_AUTOEN_CpuActive (0x1UL) /*!< In addition to the above mode, any local CPU that is not sleeping keep + the SYSCOUNTER active.*/ + +/* SYSCOUNTEREN @Bit 1 : Enable the SYSCOUNTER */ + #define GRTC_MODE_SYSCOUNTEREN_Pos (1UL) /*!< Position of SYSCOUNTEREN field. */ + #define GRTC_MODE_SYSCOUNTEREN_Msk (0x1UL << GRTC_MODE_SYSCOUNTEREN_Pos) /*!< Bit mask of SYSCOUNTEREN field. */ + #define GRTC_MODE_SYSCOUNTEREN_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTEREN field. */ + #define GRTC_MODE_SYSCOUNTEREN_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTEREN field. */ + #define GRTC_MODE_SYSCOUNTEREN_Disabled (0x0UL) /*!< SYSCOUNTER disabled */ + #define GRTC_MODE_SYSCOUNTEREN_Enabled (0x1UL) /*!< SYSCOUNTER enabled */ + + +/* GRTC_TIMEOUT: Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER */ + #define GRTC_TIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of TIMEOUT register. */ + +/* VALUE @Bits 0..15 : Number of 32Ki cycles */ + #define GRTC_TIMEOUT_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define GRTC_TIMEOUT_VALUE_Msk (0xFFFFUL << GRTC_TIMEOUT_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* GRTC_INTERVAL: Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers. */ + #define GRTC_INTERVAL_ResetValue (0x00000000UL) /*!< Reset value of INTERVAL register. */ + +/* VALUE @Bits 0..15 : Count to add to CC[0] */ + #define GRTC_INTERVAL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define GRTC_INTERVAL_VALUE_Msk (0xFFFFUL << GRTC_INTERVAL_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* GRTC_WAKETIME: GRTC wake up time. */ + #define GRTC_WAKETIME_ResetValue (0x00000001UL) /*!< Reset value of WAKETIME register. */ + +/* VALUE @Bits 0..7 : Number of LFCLK clock cycles to wake up before the next scheduled EVENTS_COMPARE event */ + #define GRTC_WAKETIME_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define GRTC_WAKETIME_VALUE_Msk (0xFFUL << GRTC_WAKETIME_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* GRTC_PWMCONFIG: PWM configuration. */ + #define GRTC_PWMCONFIG_ResetValue (0x00000000UL) /*!< Reset value of PWMCONFIG register. */ + +/* COMPAREVALUE @Bits 0..7 : The PWM compare value */ + #define GRTC_PWMCONFIG_COMPAREVALUE_Pos (0UL) /*!< Position of COMPAREVALUE field. */ + #define GRTC_PWMCONFIG_COMPAREVALUE_Msk (0xFFUL << GRTC_PWMCONFIG_COMPAREVALUE_Pos) /*!< Bit mask of COMPAREVALUE field. */ + + +/* GRTC_CLKOUT: Configuration of clock output */ + #define GRTC_CLKOUT_ResetValue (0x00000000UL) /*!< Reset value of CLKOUT register. */ + +/* CLKOUT32K @Bit 0 : Enable 32Ki clock output on pin */ + #define GRTC_CLKOUT_CLKOUT32K_Pos (0UL) /*!< Position of CLKOUT32K field. */ + #define GRTC_CLKOUT_CLKOUT32K_Msk (0x1UL << GRTC_CLKOUT_CLKOUT32K_Pos) /*!< Bit mask of CLKOUT32K field. */ + #define GRTC_CLKOUT_CLKOUT32K_Min (0x0UL) /*!< Min enumerator value of CLKOUT32K field. */ + #define GRTC_CLKOUT_CLKOUT32K_Max (0x1UL) /*!< Max enumerator value of CLKOUT32K field. */ + #define GRTC_CLKOUT_CLKOUT32K_Disabled (0x0UL) /*!< Disabled */ + #define GRTC_CLKOUT_CLKOUT32K_Enabled (0x1UL) /*!< Enabled */ + +/* CLKOUTFAST @Bit 1 : Enable fast clock output on pin */ + #define GRTC_CLKOUT_CLKOUTFAST_Pos (1UL) /*!< Position of CLKOUTFAST field. */ + #define GRTC_CLKOUT_CLKOUTFAST_Msk (0x1UL << GRTC_CLKOUT_CLKOUTFAST_Pos) /*!< Bit mask of CLKOUTFAST field. */ + #define GRTC_CLKOUT_CLKOUTFAST_Min (0x0UL) /*!< Min enumerator value of CLKOUTFAST field. */ + #define GRTC_CLKOUT_CLKOUTFAST_Max (0x1UL) /*!< Max enumerator value of CLKOUTFAST field. */ + #define GRTC_CLKOUT_CLKOUTFAST_Disabled (0x0UL) /*!< Disabled */ + #define GRTC_CLKOUT_CLKOUTFAST_Enabled (0x1UL) /*!< Enabled */ + + +/* GRTC_CLKCFG: Clock Configuration */ + #define GRTC_CLKCFG_ResetValue (0x00010001UL) /*!< Reset value of CLKCFG register. */ + +/* CLKFASTDIV @Bits 0..7 : Fast clock divisor value of clock output */ + #define GRTC_CLKCFG_CLKFASTDIV_Pos (0UL) /*!< Position of CLKFASTDIV field. */ + #define GRTC_CLKCFG_CLKFASTDIV_Msk (0xFFUL << GRTC_CLKCFG_CLKFASTDIV_Pos) /*!< Bit mask of CLKFASTDIV field. */ + #define GRTC_CLKCFG_CLKFASTDIV_Min (0x01UL) /*!< Min value of CLKFASTDIV field. */ + #define GRTC_CLKCFG_CLKFASTDIV_Max (0xFFUL) /*!< Max size of CLKFASTDIV field. */ + +/* CLKSEL @Bits 16..17 : GRTC LFCLK clock source selection */ + #define GRTC_CLKCFG_CLKSEL_Pos (16UL) /*!< Position of CLKSEL field. */ + #define GRTC_CLKCFG_CLKSEL_Msk (0x3UL << GRTC_CLKCFG_CLKSEL_Pos) /*!< Bit mask of CLKSEL field. */ + #define GRTC_CLKCFG_CLKSEL_Min (0x0UL) /*!< Min enumerator value of CLKSEL field. */ + #define GRTC_CLKCFG_CLKSEL_Max (0x2UL) /*!< Max enumerator value of CLKSEL field. */ + #define GRTC_CLKCFG_CLKSEL_LFXO (0x0UL) /*!< GRTC LFCLK clock source is LFXO */ + #define GRTC_CLKCFG_CLKSEL_SystemLFCLK (0x1UL) /*!< GRTC LFCLK clock source is system LFCLK */ + #define GRTC_CLKCFG_CLKSEL_LFLPRC (0x2UL) /*!< GRTC LFCLK clock source is LFLPRC */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ KMU ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct KMU ======================================================== */ +/** + * @brief Key management unit + */ + typedef struct { /*!< KMU Structure */ + __OM uint32_t TASKS_PROVISION; /*!< (@ 0x00000000) Provision key slot */ + __OM uint32_t TASKS_PUSH; /*!< (@ 0x00000004) Push key slot */ + __OM uint32_t TASKS_REVOKE; /*!< (@ 0x00000008) Revoke key slot */ + __OM uint32_t TASKS_READMETADATA; /*!< (@ 0x0000000C) Read key slot metadata into METADATA register */ + __OM uint32_t TASKS_PUSHBLOCK; /*!< (@ 0x00000010) Block only the PUSH operation of a key slot, preventing + the key slot from being PUSHED until next reset. The + task is kept for backwards compatibility.*/ + __OM uint32_t TASKS_BLOCK; /*!< (@ 0x00000014) Block the PROVISION, PUSH, and REVOKE operations of a + key slot, preventing the key slot from being + PROVISIONED, PUSHED, or REVOKED until next reset*/ + __IM uint32_t RESERVED[58]; + __IOM uint32_t EVENTS_PROVISIONED; /*!< (@ 0x00000100) Key slot successfully provisioned */ + __IOM uint32_t EVENTS_PUSHED; /*!< (@ 0x00000104) Key slot successfully pushed */ + __IOM uint32_t EVENTS_REVOKED; /*!< (@ 0x00000108) Key slot has been revoked and can no longer be used */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000010C) Error generated during PROVISION, PUSH, READMETADATA or + REVOKE operations. Triggering the PROVISION, PUSH and + REVOKE tasks on a BLOCKED keyslot will also generate + this event.*/ + __IOM uint32_t EVENTS_METADATAREAD; /*!< (@ 0x00000110) Key slot metadata has been read into METADATA register*/ + __IOM uint32_t EVENTS_PUSHBLOCKED; /*!< (@ 0x00000114) The PUSHBLOCK operation was successful. The event is + kept for backwards compatibility.*/ + __IOM uint32_t EVENTS_BLOCKED; /*!< (@ 0x00000118) The BLOCK operation was successful */ + __IM uint32_t RESERVED1[185]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) KMU status register */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t KEYSLOT; /*!< (@ 0x00000500) Select key slot to operate on */ + __IOM uint32_t SRC; /*!< (@ 0x00000504) Source address for provisioning */ + __IOM uint32_t METADATA; /*!< (@ 0x00000508) Key slot metadata as read by TASKS_READMETADATA. */ + } NRF_KMU_Type; /*!< Size = 1292 (0x50C) */ + +/* KMU_TASKS_PROVISION: Provision key slot */ + #define KMU_TASKS_PROVISION_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PROVISION register. */ + +/* TASKS_PROVISION @Bit 0 : Provision key slot */ + #define KMU_TASKS_PROVISION_TASKS_PROVISION_Pos (0UL) /*!< Position of TASKS_PROVISION field. */ + #define KMU_TASKS_PROVISION_TASKS_PROVISION_Msk (0x1UL << KMU_TASKS_PROVISION_TASKS_PROVISION_Pos) /*!< Bit mask of + TASKS_PROVISION field.*/ + #define KMU_TASKS_PROVISION_TASKS_PROVISION_Min (0x1UL) /*!< Min enumerator value of TASKS_PROVISION field. */ + #define KMU_TASKS_PROVISION_TASKS_PROVISION_Max (0x1UL) /*!< Max enumerator value of TASKS_PROVISION field. */ + #define KMU_TASKS_PROVISION_TASKS_PROVISION_Trigger (0x1UL) /*!< Trigger task */ + + +/* KMU_TASKS_PUSH: Push key slot */ + #define KMU_TASKS_PUSH_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PUSH register. */ + +/* TASKS_PUSH @Bit 0 : Push key slot */ + #define KMU_TASKS_PUSH_TASKS_PUSH_Pos (0UL) /*!< Position of TASKS_PUSH field. */ + #define KMU_TASKS_PUSH_TASKS_PUSH_Msk (0x1UL << KMU_TASKS_PUSH_TASKS_PUSH_Pos) /*!< Bit mask of TASKS_PUSH field. */ + #define KMU_TASKS_PUSH_TASKS_PUSH_Min (0x1UL) /*!< Min enumerator value of TASKS_PUSH field. */ + #define KMU_TASKS_PUSH_TASKS_PUSH_Max (0x1UL) /*!< Max enumerator value of TASKS_PUSH field. */ + #define KMU_TASKS_PUSH_TASKS_PUSH_Trigger (0x1UL) /*!< Trigger task */ + + +/* KMU_TASKS_REVOKE: Revoke key slot */ + #define KMU_TASKS_REVOKE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_REVOKE register. */ + +/* TASKS_REVOKE @Bit 0 : Revoke key slot */ + #define KMU_TASKS_REVOKE_TASKS_REVOKE_Pos (0UL) /*!< Position of TASKS_REVOKE field. */ + #define KMU_TASKS_REVOKE_TASKS_REVOKE_Msk (0x1UL << KMU_TASKS_REVOKE_TASKS_REVOKE_Pos) /*!< Bit mask of TASKS_REVOKE field. */ + #define KMU_TASKS_REVOKE_TASKS_REVOKE_Min (0x1UL) /*!< Min enumerator value of TASKS_REVOKE field. */ + #define KMU_TASKS_REVOKE_TASKS_REVOKE_Max (0x1UL) /*!< Max enumerator value of TASKS_REVOKE field. */ + #define KMU_TASKS_REVOKE_TASKS_REVOKE_Trigger (0x1UL) /*!< Trigger task */ + + +/* KMU_TASKS_READMETADATA: Read key slot metadata into METADATA register */ + #define KMU_TASKS_READMETADATA_ResetValue (0x00000000UL) /*!< Reset value of TASKS_READMETADATA register. */ + +/* TASKS_READMETADATA @Bit 0 : Read key slot metadata into METADATA register */ + #define KMU_TASKS_READMETADATA_TASKS_READMETADATA_Pos (0UL) /*!< Position of TASKS_READMETADATA field. */ + #define KMU_TASKS_READMETADATA_TASKS_READMETADATA_Msk (0x1UL << KMU_TASKS_READMETADATA_TASKS_READMETADATA_Pos) /*!< Bit mask + of TASKS_READMETADATA field.*/ + #define KMU_TASKS_READMETADATA_TASKS_READMETADATA_Min (0x1UL) /*!< Min enumerator value of TASKS_READMETADATA field. */ + #define KMU_TASKS_READMETADATA_TASKS_READMETADATA_Max (0x1UL) /*!< Max enumerator value of TASKS_READMETADATA field. */ + #define KMU_TASKS_READMETADATA_TASKS_READMETADATA_Trigger (0x1UL) /*!< Trigger task */ + + +/* KMU_TASKS_PUSHBLOCK: Block only the PUSH operation of a key slot, preventing the key slot from being PUSHED until next reset. + The task is kept for backwards compatibility. */ + + #define KMU_TASKS_PUSHBLOCK_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PUSHBLOCK register. */ + +/* TASKS_PUSHBLOCK @Bit 0 : Block only the PUSH operation of a key slot, preventing the key slot from being PUSHED until next + reset. The task is kept for backwards compatibility. */ + + #define KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Pos (0UL) /*!< Position of TASKS_PUSHBLOCK field. */ + #define KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Msk (0x1UL << KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Pos) /*!< Bit mask of + TASKS_PUSHBLOCK field.*/ + #define KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Min (0x1UL) /*!< Min enumerator value of TASKS_PUSHBLOCK field. */ + #define KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Max (0x1UL) /*!< Max enumerator value of TASKS_PUSHBLOCK field. */ + #define KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Trigger (0x1UL) /*!< Trigger task */ + + +/* KMU_TASKS_BLOCK: Block the PROVISION, PUSH, and REVOKE operations of a key slot, preventing the key slot from being + PROVISIONED, PUSHED, or REVOKED until next reset */ + + #define KMU_TASKS_BLOCK_ResetValue (0x00000000UL) /*!< Reset value of TASKS_BLOCK register. */ + +/* TASKS_BLOCK @Bit 0 : Block the PROVISION, PUSH, and REVOKE operations of a key slot, preventing the key slot from being + PROVISIONED, PUSHED, or REVOKED until next reset */ + + #define KMU_TASKS_BLOCK_TASKS_BLOCK_Pos (0UL) /*!< Position of TASKS_BLOCK field. */ + #define KMU_TASKS_BLOCK_TASKS_BLOCK_Msk (0x1UL << KMU_TASKS_BLOCK_TASKS_BLOCK_Pos) /*!< Bit mask of TASKS_BLOCK field. */ + #define KMU_TASKS_BLOCK_TASKS_BLOCK_Min (0x1UL) /*!< Min enumerator value of TASKS_BLOCK field. */ + #define KMU_TASKS_BLOCK_TASKS_BLOCK_Max (0x1UL) /*!< Max enumerator value of TASKS_BLOCK field. */ + #define KMU_TASKS_BLOCK_TASKS_BLOCK_Trigger (0x1UL) /*!< Trigger task */ + + +/* KMU_EVENTS_PROVISIONED: Key slot successfully provisioned */ + #define KMU_EVENTS_PROVISIONED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PROVISIONED register. */ + +/* EVENTS_PROVISIONED @Bit 0 : Key slot successfully provisioned */ + #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Pos (0UL) /*!< Position of EVENTS_PROVISIONED field. */ + #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Msk (0x1UL << KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Pos) /*!< Bit mask + of EVENTS_PROVISIONED field.*/ + #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Min (0x0UL) /*!< Min enumerator value of EVENTS_PROVISIONED field. */ + #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Max (0x1UL) /*!< Max enumerator value of EVENTS_PROVISIONED field. */ + #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_NotGenerated (0x0UL) /*!< Event not generated */ + #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Generated (0x1UL) /*!< Event generated */ + + +/* KMU_EVENTS_PUSHED: Key slot successfully pushed */ + #define KMU_EVENTS_PUSHED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PUSHED register. */ + +/* EVENTS_PUSHED @Bit 0 : Key slot successfully pushed */ + #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_Pos (0UL) /*!< Position of EVENTS_PUSHED field. */ + #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_Msk (0x1UL << KMU_EVENTS_PUSHED_EVENTS_PUSHED_Pos) /*!< Bit mask of EVENTS_PUSHED + field.*/ + #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_Min (0x0UL) /*!< Min enumerator value of EVENTS_PUSHED field. */ + #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_Max (0x1UL) /*!< Max enumerator value of EVENTS_PUSHED field. */ + #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_NotGenerated (0x0UL) /*!< Event not generated */ + #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_Generated (0x1UL) /*!< Event generated */ + + +/* KMU_EVENTS_REVOKED: Key slot has been revoked and can no longer be used */ + #define KMU_EVENTS_REVOKED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_REVOKED register. */ + +/* EVENTS_REVOKED @Bit 0 : Key slot has been revoked and can no longer be used */ + #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_Pos (0UL) /*!< Position of EVENTS_REVOKED field. */ + #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_Msk (0x1UL << KMU_EVENTS_REVOKED_EVENTS_REVOKED_Pos) /*!< Bit mask of EVENTS_REVOKED + field.*/ + #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_Min (0x0UL) /*!< Min enumerator value of EVENTS_REVOKED field. */ + #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_Max (0x1UL) /*!< Max enumerator value of EVENTS_REVOKED field. */ + #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_NotGenerated (0x0UL) /*!< Event not generated */ + #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_Generated (0x1UL) /*!< Event generated */ + + +/* KMU_EVENTS_ERROR: Error generated during PROVISION, PUSH, READMETADATA or REVOKE operations. Triggering the PROVISION, PUSH + and REVOKE tasks on a BLOCKED keyslot will also generate this event. */ + + #define KMU_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : Error generated during PROVISION, PUSH, READMETADATA or REVOKE operations. Triggering the PROVISION, + PUSH and REVOKE tasks on a BLOCKED keyslot will also generate this event. */ + + #define KMU_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define KMU_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << KMU_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + #define KMU_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define KMU_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define KMU_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define KMU_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* KMU_EVENTS_METADATAREAD: Key slot metadata has been read into METADATA register */ + #define KMU_EVENTS_METADATAREAD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_METADATAREAD register. */ + +/* EVENTS_METADATAREAD @Bit 0 : Key slot metadata has been read into METADATA register */ + #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Pos (0UL) /*!< Position of EVENTS_METADATAREAD field. */ + #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Msk (0x1UL << KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Pos) /*!< Bit + mask of EVENTS_METADATAREAD field.*/ + #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Min (0x0UL) /*!< Min enumerator value of EVENTS_METADATAREAD field. */ + #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Max (0x1UL) /*!< Max enumerator value of EVENTS_METADATAREAD field. */ + #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_NotGenerated (0x0UL) /*!< Event not generated */ + #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Generated (0x1UL) /*!< Event generated */ + + +/* KMU_EVENTS_PUSHBLOCKED: The PUSHBLOCK operation was successful. The event is kept for backwards compatibility. */ + #define KMU_EVENTS_PUSHBLOCKED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PUSHBLOCKED register. */ + +/* EVENTS_PUSHBLOCKED @Bit 0 : The PUSHBLOCK operation was successful. The event is kept for backwards compatibility. */ + #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Pos (0UL) /*!< Position of EVENTS_PUSHBLOCKED field. */ + #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Msk (0x1UL << KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Pos) /*!< Bit mask + of EVENTS_PUSHBLOCKED field.*/ + #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Min (0x0UL) /*!< Min enumerator value of EVENTS_PUSHBLOCKED field. */ + #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Max (0x1UL) /*!< Max enumerator value of EVENTS_PUSHBLOCKED field. */ + #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_NotGenerated (0x0UL) /*!< Event not generated */ + #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Generated (0x1UL) /*!< Event generated */ + + +/* KMU_EVENTS_BLOCKED: The BLOCK operation was successful */ + #define KMU_EVENTS_BLOCKED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_BLOCKED register. */ + +/* EVENTS_BLOCKED @Bit 0 : The BLOCK operation was successful */ + #define KMU_EVENTS_BLOCKED_EVENTS_BLOCKED_Pos (0UL) /*!< Position of EVENTS_BLOCKED field. */ + #define KMU_EVENTS_BLOCKED_EVENTS_BLOCKED_Msk (0x1UL << KMU_EVENTS_BLOCKED_EVENTS_BLOCKED_Pos) /*!< Bit mask of EVENTS_BLOCKED + field.*/ + #define KMU_EVENTS_BLOCKED_EVENTS_BLOCKED_Min (0x0UL) /*!< Min enumerator value of EVENTS_BLOCKED field. */ + #define KMU_EVENTS_BLOCKED_EVENTS_BLOCKED_Max (0x1UL) /*!< Max enumerator value of EVENTS_BLOCKED field. */ + #define KMU_EVENTS_BLOCKED_EVENTS_BLOCKED_NotGenerated (0x0UL) /*!< Event not generated */ + #define KMU_EVENTS_BLOCKED_EVENTS_BLOCKED_Generated (0x1UL) /*!< Event generated */ + + +/* KMU_STATUS: KMU status register */ + #define KMU_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* STATUS @Bit 0 : KMU status */ + #define KMU_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define KMU_STATUS_STATUS_Msk (0x1UL << KMU_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define KMU_STATUS_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define KMU_STATUS_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define KMU_STATUS_STATUS_Ready (0x0UL) /*!< KMU is ready for new operation */ + #define KMU_STATUS_STATUS_Busy (0x1UL) /*!< KMU is busy, an operation is in progress */ + + +/* KMU_KEYSLOT: Select key slot to operate on */ + #define KMU_KEYSLOT_ResetValue (0x00000000UL) /*!< Reset value of KEYSLOT register. */ + +/* ID @Bits 0..7 : Select key slot ID to provision, push, read METADATA, revoke or block when the corresponding task is + triggered. */ + + #define KMU_KEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */ + #define KMU_KEYSLOT_ID_Msk (0xFFUL << KMU_KEYSLOT_ID_Pos) /*!< Bit mask of ID field. */ + #define KMU_KEYSLOT_ID_Min (0x00UL) /*!< Min value of ID field. */ + #define KMU_KEYSLOT_ID_Max (0xF9UL) /*!< Max size of ID field. */ + + +/* KMU_SRC: Source address for provisioning */ + #define KMU_SRC_ResetValue (0x00000000UL) /*!< Reset value of SRC register. */ + +/* SRC @Bits 0..31 : Source address for TASKS_PROVISION. */ + #define KMU_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */ + #define KMU_SRC_SRC_Msk (0xFFFFFFFFUL << KMU_SRC_SRC_Pos) /*!< Bit mask of SRC field. */ + + +/* KMU_METADATA: Key slot metadata as read by TASKS_READMETADATA. */ + #define KMU_METADATA_ResetValue (0x00000000UL) /*!< Reset value of METADATA register. */ + +/* METADATA @Bits 0..31 : Read metadata. */ + #define KMU_METADATA_METADATA_Pos (0UL) /*!< Position of METADATA field. */ + #define KMU_METADATA_METADATA_Msk (0xFFFFFFFFUL << KMU_METADATA_METADATA_Pos) /*!< Bit mask of METADATA field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ====================================================== Struct LPCOMP ====================================================== */ +/** + * @brief Low-power comparator + */ + typedef struct { /*!< LPCOMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value. This task requires that LPCOMP + has been started by the START task.*/ + __IM uint32_t RESERVED[29]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE */ + __IM uint32_t RESERVED1[29]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED2[28]; + __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ + __IOM uint32_t PUBLISH_DOWN; /*!< (@ 0x00000184) Publish configuration for event DOWN */ + __IOM uint32_t PUBLISH_UP; /*!< (@ 0x00000188) Publish configuration for event UP */ + __IOM uint32_t PUBLISH_CROSS; /*!< (@ 0x0000018C) Publish configuration for event CROSS */ + __IM uint32_t RESERVED3[28]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED5[60]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED6[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED7[4]; + __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ + __IM uint32_t RESERVED8[5]; + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ + } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53C) */ + +/* LPCOMP_TASKS_START: Start comparator */ + #define LPCOMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start comparator */ + #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define LPCOMP_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define LPCOMP_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define LPCOMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* LPCOMP_TASKS_STOP: Stop comparator */ + #define LPCOMP_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop comparator */ + #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define LPCOMP_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define LPCOMP_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* LPCOMP_TASKS_SAMPLE: Sample comparator value. This task requires that LPCOMP has been started by the START task. */ + #define LPCOMP_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register. */ + +/* TASKS_SAMPLE @Bit 0 : Sample comparator value. This task requires that LPCOMP has been started by the START task. */ + #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ + #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE + field.*/ + #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field. */ + #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field. */ + #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */ + + +/* LPCOMP_SUBSCRIBE_START: Subscribe configuration for task START */ + #define LPCOMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define LPCOMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_SUBSCRIBE_START_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define LPCOMP_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* LPCOMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define LPCOMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* LPCOMP_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */ + #define LPCOMP_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */ + #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* LPCOMP_EVENTS_READY: LPCOMP is ready and output is valid */ + #define LPCOMP_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register. */ + +/* EVENTS_READY @Bit 0 : LPCOMP is ready and output is valid */ + #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ + #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY + field.*/ + #define LPCOMP_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field. */ + #define LPCOMP_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field. */ + #define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */ + + +/* LPCOMP_EVENTS_DOWN: Downward crossing */ + #define LPCOMP_EVENTS_DOWN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DOWN register. */ + +/* EVENTS_DOWN @Bit 0 : Downward crossing */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Min (0x0UL) /*!< Min enumerator value of EVENTS_DOWN field. */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Max (0x1UL) /*!< Max enumerator value of EVENTS_DOWN field. */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated */ + + +/* LPCOMP_EVENTS_UP: Upward crossing */ + #define LPCOMP_EVENTS_UP_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_UP register. */ + +/* EVENTS_UP @Bit 0 : Upward crossing */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_Min (0x0UL) /*!< Min enumerator value of EVENTS_UP field. */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_Max (0x1UL) /*!< Max enumerator value of EVENTS_UP field. */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated */ + + +/* LPCOMP_EVENTS_CROSS: Downward or upward crossing */ + #define LPCOMP_EVENTS_CROSS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CROSS register. */ + +/* EVENTS_CROSS @Bit 0 : Downward or upward crossing */ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS + field.*/ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Min (0x0UL) /*!< Min enumerator value of EVENTS_CROSS field. */ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Max (0x1UL) /*!< Max enumerator value of EVENTS_CROSS field. */ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated */ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated */ + + +/* LPCOMP_PUBLISH_READY: Publish configuration for event READY */ + #define LPCOMP_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define LPCOMP_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_PUBLISH_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_PUBLISH_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_PUBLISH_READY_EN_Msk (0x1UL << LPCOMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_PUBLISH_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_PUBLISH_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define LPCOMP_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* LPCOMP_PUBLISH_DOWN: Publish configuration for event DOWN */ + #define LPCOMP_PUBLISH_DOWN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DOWN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DOWN will publish to */ + #define LPCOMP_PUBLISH_DOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_PUBLISH_DOWN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_PUBLISH_DOWN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_PUBLISH_DOWN_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_PUBLISH_DOWN_EN_Msk (0x1UL << LPCOMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_PUBLISH_DOWN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_PUBLISH_DOWN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_PUBLISH_DOWN_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define LPCOMP_PUBLISH_DOWN_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* LPCOMP_PUBLISH_UP: Publish configuration for event UP */ + #define LPCOMP_PUBLISH_UP_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_UP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event UP will publish to */ + #define LPCOMP_PUBLISH_UP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_PUBLISH_UP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_PUBLISH_UP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_PUBLISH_UP_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_PUBLISH_UP_EN_Msk (0x1UL << LPCOMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_PUBLISH_UP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_PUBLISH_UP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_PUBLISH_UP_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define LPCOMP_PUBLISH_UP_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* LPCOMP_PUBLISH_CROSS: Publish configuration for event CROSS */ + #define LPCOMP_PUBLISH_CROSS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CROSS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CROSS will publish to */ + #define LPCOMP_PUBLISH_CROSS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_PUBLISH_CROSS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_PUBLISH_CROSS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_PUBLISH_CROSS_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_PUBLISH_CROSS_EN_Msk (0x1UL << LPCOMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_PUBLISH_CROSS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_PUBLISH_CROSS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_PUBLISH_CROSS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define LPCOMP_PUBLISH_CROSS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* LPCOMP_SHORTS: Shortcuts between local events and tasks */ + #define LPCOMP_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* READY_SAMPLE @Bit 0 : Shortcut between event READY and task SAMPLE */ + #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ + #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ + #define LPCOMP_SHORTS_READY_SAMPLE_Min (0x0UL) /*!< Min enumerator value of READY_SAMPLE field. */ + #define LPCOMP_SHORTS_READY_SAMPLE_Max (0x1UL) /*!< Max enumerator value of READY_SAMPLE field. */ + #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* READY_STOP @Bit 1 : Shortcut between event READY and task STOP */ + #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ + #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ + #define LPCOMP_SHORTS_READY_STOP_Min (0x0UL) /*!< Min enumerator value of READY_STOP field. */ + #define LPCOMP_SHORTS_READY_STOP_Max (0x1UL) /*!< Max enumerator value of READY_STOP field. */ + #define LPCOMP_SHORTS_READY_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define LPCOMP_SHORTS_READY_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DOWN_STOP @Bit 2 : Shortcut between event DOWN and task STOP */ + #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ + #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ + #define LPCOMP_SHORTS_DOWN_STOP_Min (0x0UL) /*!< Min enumerator value of DOWN_STOP field. */ + #define LPCOMP_SHORTS_DOWN_STOP_Max (0x1UL) /*!< Max enumerator value of DOWN_STOP field. */ + #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define LPCOMP_SHORTS_DOWN_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* UP_STOP @Bit 3 : Shortcut between event UP and task STOP */ + #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ + #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ + #define LPCOMP_SHORTS_UP_STOP_Min (0x0UL) /*!< Min enumerator value of UP_STOP field. */ + #define LPCOMP_SHORTS_UP_STOP_Max (0x1UL) /*!< Max enumerator value of UP_STOP field. */ + #define LPCOMP_SHORTS_UP_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define LPCOMP_SHORTS_UP_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* CROSS_STOP @Bit 4 : Shortcut between event CROSS and task STOP */ + #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ + #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ + #define LPCOMP_SHORTS_CROSS_STOP_Min (0x0UL) /*!< Min enumerator value of CROSS_STOP field. */ + #define LPCOMP_SHORTS_CROSS_STOP_Max (0x1UL) /*!< Max enumerator value of CROSS_STOP field. */ + #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define LPCOMP_SHORTS_CROSS_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* LPCOMP_INTEN: Enable or disable interrupt */ + #define LPCOMP_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* READY @Bit 0 : Enable or disable interrupt for event READY */ + #define LPCOMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ + #define LPCOMP_INTEN_READY_Msk (0x1UL << LPCOMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ + #define LPCOMP_INTEN_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define LPCOMP_INTEN_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define LPCOMP_INTEN_READY_Disabled (0x0UL) /*!< Disable */ + #define LPCOMP_INTEN_READY_Enabled (0x1UL) /*!< Enable */ + +/* DOWN @Bit 1 : Enable or disable interrupt for event DOWN */ + #define LPCOMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define LPCOMP_INTEN_DOWN_Msk (0x1UL << LPCOMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define LPCOMP_INTEN_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define LPCOMP_INTEN_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define LPCOMP_INTEN_DOWN_Disabled (0x0UL) /*!< Disable */ + #define LPCOMP_INTEN_DOWN_Enabled (0x1UL) /*!< Enable */ + +/* UP @Bit 2 : Enable or disable interrupt for event UP */ + #define LPCOMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ + #define LPCOMP_INTEN_UP_Msk (0x1UL << LPCOMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ + #define LPCOMP_INTEN_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define LPCOMP_INTEN_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define LPCOMP_INTEN_UP_Disabled (0x0UL) /*!< Disable */ + #define LPCOMP_INTEN_UP_Enabled (0x1UL) /*!< Enable */ + +/* CROSS @Bit 3 : Enable or disable interrupt for event CROSS */ + #define LPCOMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define LPCOMP_INTEN_CROSS_Msk (0x1UL << LPCOMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define LPCOMP_INTEN_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define LPCOMP_INTEN_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define LPCOMP_INTEN_CROSS_Disabled (0x0UL) /*!< Disable */ + #define LPCOMP_INTEN_CROSS_Enabled (0x1UL) /*!< Enable */ + + +/* LPCOMP_INTENSET: Enable interrupt */ + #define LPCOMP_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* READY @Bit 0 : Write '1' to enable interrupt for event READY */ + #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ + #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ + #define LPCOMP_INTENSET_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define LPCOMP_INTENSET_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define LPCOMP_INTENSET_READY_Set (0x1UL) /*!< Enable */ + #define LPCOMP_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DOWN @Bit 1 : Write '1' to enable interrupt for event DOWN */ + #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define LPCOMP_INTENSET_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define LPCOMP_INTENSET_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define LPCOMP_INTENSET_DOWN_Set (0x1UL) /*!< Enable */ + #define LPCOMP_INTENSET_DOWN_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENSET_DOWN_Enabled (0x1UL) /*!< Read: Enabled */ + +/* UP @Bit 2 : Write '1' to enable interrupt for event UP */ + #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ + #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ + #define LPCOMP_INTENSET_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define LPCOMP_INTENSET_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define LPCOMP_INTENSET_UP_Set (0x1UL) /*!< Enable */ + #define LPCOMP_INTENSET_UP_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENSET_UP_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CROSS @Bit 3 : Write '1' to enable interrupt for event CROSS */ + #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define LPCOMP_INTENSET_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define LPCOMP_INTENSET_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define LPCOMP_INTENSET_CROSS_Set (0x1UL) /*!< Enable */ + #define LPCOMP_INTENSET_CROSS_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENSET_CROSS_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* LPCOMP_INTENCLR: Disable interrupt */ + #define LPCOMP_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* READY @Bit 0 : Write '1' to disable interrupt for event READY */ + #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ + #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ + #define LPCOMP_INTENCLR_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define LPCOMP_INTENCLR_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define LPCOMP_INTENCLR_READY_Clear (0x1UL) /*!< Disable */ + #define LPCOMP_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DOWN @Bit 1 : Write '1' to disable interrupt for event DOWN */ + #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define LPCOMP_INTENCLR_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define LPCOMP_INTENCLR_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define LPCOMP_INTENCLR_DOWN_Clear (0x1UL) /*!< Disable */ + #define LPCOMP_INTENCLR_DOWN_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENCLR_DOWN_Enabled (0x1UL) /*!< Read: Enabled */ + +/* UP @Bit 2 : Write '1' to disable interrupt for event UP */ + #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ + #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ + #define LPCOMP_INTENCLR_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define LPCOMP_INTENCLR_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define LPCOMP_INTENCLR_UP_Clear (0x1UL) /*!< Disable */ + #define LPCOMP_INTENCLR_UP_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENCLR_UP_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CROSS @Bit 3 : Write '1' to disable interrupt for event CROSS */ + #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define LPCOMP_INTENCLR_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define LPCOMP_INTENCLR_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define LPCOMP_INTENCLR_CROSS_Clear (0x1UL) /*!< Disable */ + #define LPCOMP_INTENCLR_CROSS_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENCLR_CROSS_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* LPCOMP_INTPEND: Pending interrupts */ + #define LPCOMP_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* READY @Bit 0 : Read pending status of interrupt for event READY */ + #define LPCOMP_INTPEND_READY_Pos (0UL) /*!< Position of READY field. */ + #define LPCOMP_INTPEND_READY_Msk (0x1UL << LPCOMP_INTPEND_READY_Pos) /*!< Bit mask of READY field. */ + #define LPCOMP_INTPEND_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define LPCOMP_INTPEND_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define LPCOMP_INTPEND_READY_NotPending (0x0UL) /*!< Read: Not pending */ + #define LPCOMP_INTPEND_READY_Pending (0x1UL) /*!< Read: Pending */ + +/* DOWN @Bit 1 : Read pending status of interrupt for event DOWN */ + #define LPCOMP_INTPEND_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define LPCOMP_INTPEND_DOWN_Msk (0x1UL << LPCOMP_INTPEND_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define LPCOMP_INTPEND_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define LPCOMP_INTPEND_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define LPCOMP_INTPEND_DOWN_NotPending (0x0UL) /*!< Read: Not pending */ + #define LPCOMP_INTPEND_DOWN_Pending (0x1UL) /*!< Read: Pending */ + +/* UP @Bit 2 : Read pending status of interrupt for event UP */ + #define LPCOMP_INTPEND_UP_Pos (2UL) /*!< Position of UP field. */ + #define LPCOMP_INTPEND_UP_Msk (0x1UL << LPCOMP_INTPEND_UP_Pos) /*!< Bit mask of UP field. */ + #define LPCOMP_INTPEND_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define LPCOMP_INTPEND_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define LPCOMP_INTPEND_UP_NotPending (0x0UL) /*!< Read: Not pending */ + #define LPCOMP_INTPEND_UP_Pending (0x1UL) /*!< Read: Pending */ + +/* CROSS @Bit 3 : Read pending status of interrupt for event CROSS */ + #define LPCOMP_INTPEND_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define LPCOMP_INTPEND_CROSS_Msk (0x1UL << LPCOMP_INTPEND_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define LPCOMP_INTPEND_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define LPCOMP_INTPEND_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define LPCOMP_INTPEND_CROSS_NotPending (0x0UL) /*!< Read: Not pending */ + #define LPCOMP_INTPEND_CROSS_Pending (0x1UL) /*!< Read: Pending */ + + +/* LPCOMP_RESULT: Compare result */ + #define LPCOMP_RESULT_ResetValue (0x00000000UL) /*!< Reset value of RESULT register. */ + +/* RESULT @Bit 0 : Result of last compare. Decision point SAMPLE task. */ + #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ + #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ + #define LPCOMP_RESULT_RESULT_Min (0x0UL) /*!< Min enumerator value of RESULT field. */ + #define LPCOMP_RESULT_RESULT_Max (0x1UL) /*!< Max enumerator value of RESULT field. */ + #define LPCOMP_RESULT_RESULT_Below (0x0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-) */ + #define LPCOMP_RESULT_RESULT_Above (0x1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-) */ + + +/* LPCOMP_ENABLE: Enable LPCOMP */ + #define LPCOMP_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..1 : Enable or disable LPCOMP */ + #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define LPCOMP_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define LPCOMP_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define LPCOMP_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define LPCOMP_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* LPCOMP_PSEL: Input pin select */ + #define LPCOMP_PSEL_ResetValue (0x00000000UL) /*!< Reset value of PSEL register. */ + +/* PIN @Bits 0..4 : Analog pin select */ + #define LPCOMP_PSEL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define LPCOMP_PSEL_PIN_Msk (0x1FUL << LPCOMP_PSEL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO Port selection */ + #define LPCOMP_PSEL_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define LPCOMP_PSEL_PORT_Msk (0xFUL << LPCOMP_PSEL_PORT_Pos) /*!< Bit mask of PORT field. */ + + +/* LPCOMP_REFSEL: Reference select */ + #define LPCOMP_REFSEL_ResetValue (0x00000004UL) /*!< Reset value of REFSEL register. */ + +/* REFSEL @Bits 0..3 : Reference select */ + #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ + #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ + #define LPCOMP_REFSEL_REFSEL_Min (0x0UL) /*!< Min enumerator value of REFSEL field. */ + #define LPCOMP_REFSEL_REFSEL_Max (0xFUL) /*!< Max enumerator value of REFSEL field. */ + #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0x0UL) /*!< VDD * 1/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (0x1UL) /*!< VDD * 2/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (0x2UL) /*!< VDD * 3/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (0x3UL) /*!< VDD * 4/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (0x4UL) /*!< VDD * 5/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (0x5UL) /*!< VDD * 6/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (0x6UL) /*!< VDD * 7/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_ARef (0x7UL) /*!< External analog reference selected */ + #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (0x8UL) /*!< VDD * 1/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (0x9UL) /*!< VDD * 3/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (0xAUL) /*!< VDD * 5/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (0xBUL) /*!< VDD * 7/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (0xCUL) /*!< VDD * 9/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (0xDUL) /*!< VDD * 11/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (0xEUL) /*!< VDD * 13/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (0xFUL) /*!< VDD * 15/16 selected as reference */ + + +/* LPCOMP_EXTREFSEL: External reference select */ + #define LPCOMP_EXTREFSEL_ResetValue (0x00000000UL) /*!< Reset value of EXTREFSEL register. */ + +/* PIN @Bits 0..4 : External analog reference pin select */ + #define LPCOMP_EXTREFSEL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define LPCOMP_EXTREFSEL_PIN_Msk (0x1FUL << LPCOMP_EXTREFSEL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO Port selection */ + #define LPCOMP_EXTREFSEL_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define LPCOMP_EXTREFSEL_PORT_Msk (0xFUL << LPCOMP_EXTREFSEL_PORT_Pos) /*!< Bit mask of PORT field. */ + + +/* LPCOMP_ANADETECT: Analog detect configuration */ + #define LPCOMP_ANADETECT_ResetValue (0x00000000UL) /*!< Reset value of ANADETECT register. */ + +/* ANADETECT @Bits 0..1 : Analog detect configuration */ + #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ + #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ + #define LPCOMP_ANADETECT_ANADETECT_Min (0x0UL) /*!< Min enumerator value of ANADETECT field. */ + #define LPCOMP_ANADETECT_ANADETECT_Max (0x2UL) /*!< Max enumerator value of ANADETECT field. */ + #define LPCOMP_ANADETECT_ANADETECT_Cross (0x0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward + crossing*/ + #define LPCOMP_ANADETECT_ANADETECT_Up (0x1UL) /*!< Generate ANADETECT on upward crossing only */ + #define LPCOMP_ANADETECT_ANADETECT_Down (0x2UL) /*!< Generate ANADETECT on downward crossing only */ + + +/* LPCOMP_HYST: Comparator hysteresis enable */ + #define LPCOMP_HYST_ResetValue (0x00000000UL) /*!< Reset value of HYST register. */ + +/* HYST @Bit 0 : Comparator hysteresis enable */ + #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ + #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ + #define LPCOMP_HYST_HYST_Min (0x0UL) /*!< Min enumerator value of HYST field. */ + #define LPCOMP_HYST_HYST_Max (0x1UL) /*!< Max enumerator value of HYST field. */ + #define LPCOMP_HYST_HYST_Disabled (0x0UL) /*!< Comparator hysteresis disabled */ + #define LPCOMP_HYST_HYST_Enabled (0x1UL) /*!< Comparator hysteresis enabled */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ MEMCONF ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct MEMCONF_POWER =================================================== */ +/** + * @brief POWER [MEMCONF_POWER] (unspecified) + */ +typedef struct { + __IOM uint32_t CONTROL; /*!< (@ 0x00000000) Control memory block power. */ + __IM uint32_t RESERVED; + __IOM uint32_t RET; /*!< (@ 0x00000008) RAM retention for RAM [n]. */ + __IM uint32_t RESERVED1; +} NRF_MEMCONF_POWER_Type; /*!< Size = 16 (0x010) */ + #define MEMCONF_POWER_MaxCount (2UL) /*!< Size of POWER[2] array. */ + #define MEMCONF_POWER_MaxIndex (1UL) /*!< Max index of POWER[2] array. */ + #define MEMCONF_POWER_MinIndex (0UL) /*!< Min index of POWER[2] array. */ + +/* MEMCONF_POWER_CONTROL: Control memory block power. */ + #define MEMCONF_POWER_CONTROL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONTROL register. */ + +/* MEM0 @Bit 0 : Keep the memory block MEM[0] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM0_Pos (0UL) /*!< Position of MEM0 field. */ + #define MEMCONF_POWER_CONTROL_MEM0_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM0_Pos) /*!< Bit mask of MEM0 field. */ + #define MEMCONF_POWER_CONTROL_MEM0_Min (0x0UL) /*!< Min enumerator value of MEM0 field. */ + #define MEMCONF_POWER_CONTROL_MEM0_Max (0x1UL) /*!< Max enumerator value of MEM0 field. */ + #define MEMCONF_POWER_CONTROL_MEM0_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM0_On (0x1UL) /*!< Power up */ + +/* MEM1 @Bit 1 : Keep the memory block MEM[1] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM1_Pos (1UL) /*!< Position of MEM1 field. */ + #define MEMCONF_POWER_CONTROL_MEM1_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM1_Pos) /*!< Bit mask of MEM1 field. */ + #define MEMCONF_POWER_CONTROL_MEM1_Min (0x0UL) /*!< Min enumerator value of MEM1 field. */ + #define MEMCONF_POWER_CONTROL_MEM1_Max (0x1UL) /*!< Max enumerator value of MEM1 field. */ + #define MEMCONF_POWER_CONTROL_MEM1_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM1_On (0x1UL) /*!< Power up */ + +/* MEM2 @Bit 2 : Keep the memory block MEM[2] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM2_Pos (2UL) /*!< Position of MEM2 field. */ + #define MEMCONF_POWER_CONTROL_MEM2_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM2_Pos) /*!< Bit mask of MEM2 field. */ + #define MEMCONF_POWER_CONTROL_MEM2_Min (0x0UL) /*!< Min enumerator value of MEM2 field. */ + #define MEMCONF_POWER_CONTROL_MEM2_Max (0x1UL) /*!< Max enumerator value of MEM2 field. */ + #define MEMCONF_POWER_CONTROL_MEM2_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM2_On (0x1UL) /*!< Power up */ + +/* MEM3 @Bit 3 : Keep the memory block MEM[3] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM3_Pos (3UL) /*!< Position of MEM3 field. */ + #define MEMCONF_POWER_CONTROL_MEM3_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM3_Pos) /*!< Bit mask of MEM3 field. */ + #define MEMCONF_POWER_CONTROL_MEM3_Min (0x0UL) /*!< Min enumerator value of MEM3 field. */ + #define MEMCONF_POWER_CONTROL_MEM3_Max (0x1UL) /*!< Max enumerator value of MEM3 field. */ + #define MEMCONF_POWER_CONTROL_MEM3_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM3_On (0x1UL) /*!< Power up */ + +/* MEM4 @Bit 4 : Keep the memory block MEM[4] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM4_Pos (4UL) /*!< Position of MEM4 field. */ + #define MEMCONF_POWER_CONTROL_MEM4_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM4_Pos) /*!< Bit mask of MEM4 field. */ + #define MEMCONF_POWER_CONTROL_MEM4_Min (0x0UL) /*!< Min enumerator value of MEM4 field. */ + #define MEMCONF_POWER_CONTROL_MEM4_Max (0x1UL) /*!< Max enumerator value of MEM4 field. */ + #define MEMCONF_POWER_CONTROL_MEM4_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM4_On (0x1UL) /*!< Power up */ + +/* MEM5 @Bit 5 : Keep the memory block MEM[5] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM5_Pos (5UL) /*!< Position of MEM5 field. */ + #define MEMCONF_POWER_CONTROL_MEM5_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM5_Pos) /*!< Bit mask of MEM5 field. */ + #define MEMCONF_POWER_CONTROL_MEM5_Min (0x0UL) /*!< Min enumerator value of MEM5 field. */ + #define MEMCONF_POWER_CONTROL_MEM5_Max (0x1UL) /*!< Max enumerator value of MEM5 field. */ + #define MEMCONF_POWER_CONTROL_MEM5_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM5_On (0x1UL) /*!< Power up */ + +/* MEM6 @Bit 6 : Keep the memory block MEM[6] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM6_Pos (6UL) /*!< Position of MEM6 field. */ + #define MEMCONF_POWER_CONTROL_MEM6_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM6_Pos) /*!< Bit mask of MEM6 field. */ + #define MEMCONF_POWER_CONTROL_MEM6_Min (0x0UL) /*!< Min enumerator value of MEM6 field. */ + #define MEMCONF_POWER_CONTROL_MEM6_Max (0x1UL) /*!< Max enumerator value of MEM6 field. */ + #define MEMCONF_POWER_CONTROL_MEM6_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM6_On (0x1UL) /*!< Power up */ + +/* MEM7 @Bit 7 : Keep the memory block MEM[7] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM7_Pos (7UL) /*!< Position of MEM7 field. */ + #define MEMCONF_POWER_CONTROL_MEM7_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM7_Pos) /*!< Bit mask of MEM7 field. */ + #define MEMCONF_POWER_CONTROL_MEM7_Min (0x0UL) /*!< Min enumerator value of MEM7 field. */ + #define MEMCONF_POWER_CONTROL_MEM7_Max (0x1UL) /*!< Max enumerator value of MEM7 field. */ + #define MEMCONF_POWER_CONTROL_MEM7_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM7_On (0x1UL) /*!< Power up */ + +/* MEM8 @Bit 8 : Keep the memory block MEM[8] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM8_Pos (8UL) /*!< Position of MEM8 field. */ + #define MEMCONF_POWER_CONTROL_MEM8_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM8_Pos) /*!< Bit mask of MEM8 field. */ + #define MEMCONF_POWER_CONTROL_MEM8_Min (0x0UL) /*!< Min enumerator value of MEM8 field. */ + #define MEMCONF_POWER_CONTROL_MEM8_Max (0x1UL) /*!< Max enumerator value of MEM8 field. */ + #define MEMCONF_POWER_CONTROL_MEM8_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM8_On (0x1UL) /*!< Power up */ + +/* MEM9 @Bit 9 : Keep the memory block MEM[9] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM9_Pos (9UL) /*!< Position of MEM9 field. */ + #define MEMCONF_POWER_CONTROL_MEM9_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM9_Pos) /*!< Bit mask of MEM9 field. */ + #define MEMCONF_POWER_CONTROL_MEM9_Min (0x0UL) /*!< Min enumerator value of MEM9 field. */ + #define MEMCONF_POWER_CONTROL_MEM9_Max (0x1UL) /*!< Max enumerator value of MEM9 field. */ + #define MEMCONF_POWER_CONTROL_MEM9_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM9_On (0x1UL) /*!< Power up */ + +/* MEM10 @Bit 10 : Keep the memory block MEM[10] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM10_Pos (10UL) /*!< Position of MEM10 field. */ + #define MEMCONF_POWER_CONTROL_MEM10_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM10_Pos) /*!< Bit mask of MEM10 field. */ + #define MEMCONF_POWER_CONTROL_MEM10_Min (0x0UL) /*!< Min enumerator value of MEM10 field. */ + #define MEMCONF_POWER_CONTROL_MEM10_Max (0x1UL) /*!< Max enumerator value of MEM10 field. */ + #define MEMCONF_POWER_CONTROL_MEM10_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM10_On (0x1UL) /*!< Power up */ + +/* MEM11 @Bit 11 : Keep the memory block MEM[11] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM11_Pos (11UL) /*!< Position of MEM11 field. */ + #define MEMCONF_POWER_CONTROL_MEM11_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM11_Pos) /*!< Bit mask of MEM11 field. */ + #define MEMCONF_POWER_CONTROL_MEM11_Min (0x0UL) /*!< Min enumerator value of MEM11 field. */ + #define MEMCONF_POWER_CONTROL_MEM11_Max (0x1UL) /*!< Max enumerator value of MEM11 field. */ + #define MEMCONF_POWER_CONTROL_MEM11_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM11_On (0x1UL) /*!< Power up */ + +/* MEM12 @Bit 12 : Keep the memory block MEM[12] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM12_Pos (12UL) /*!< Position of MEM12 field. */ + #define MEMCONF_POWER_CONTROL_MEM12_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM12_Pos) /*!< Bit mask of MEM12 field. */ + #define MEMCONF_POWER_CONTROL_MEM12_Min (0x0UL) /*!< Min enumerator value of MEM12 field. */ + #define MEMCONF_POWER_CONTROL_MEM12_Max (0x1UL) /*!< Max enumerator value of MEM12 field. */ + #define MEMCONF_POWER_CONTROL_MEM12_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM12_On (0x1UL) /*!< Power up */ + +/* MEM13 @Bit 13 : Keep the memory block MEM[13] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM13_Pos (13UL) /*!< Position of MEM13 field. */ + #define MEMCONF_POWER_CONTROL_MEM13_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM13_Pos) /*!< Bit mask of MEM13 field. */ + #define MEMCONF_POWER_CONTROL_MEM13_Min (0x0UL) /*!< Min enumerator value of MEM13 field. */ + #define MEMCONF_POWER_CONTROL_MEM13_Max (0x1UL) /*!< Max enumerator value of MEM13 field. */ + #define MEMCONF_POWER_CONTROL_MEM13_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM13_On (0x1UL) /*!< Power up */ + +/* MEM14 @Bit 14 : Keep the memory block MEM[14] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM14_Pos (14UL) /*!< Position of MEM14 field. */ + #define MEMCONF_POWER_CONTROL_MEM14_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM14_Pos) /*!< Bit mask of MEM14 field. */ + #define MEMCONF_POWER_CONTROL_MEM14_Min (0x0UL) /*!< Min enumerator value of MEM14 field. */ + #define MEMCONF_POWER_CONTROL_MEM14_Max (0x1UL) /*!< Max enumerator value of MEM14 field. */ + #define MEMCONF_POWER_CONTROL_MEM14_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM14_On (0x1UL) /*!< Power up */ + +/* MEM15 @Bit 15 : Keep the memory block MEM[15] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM15_Pos (15UL) /*!< Position of MEM15 field. */ + #define MEMCONF_POWER_CONTROL_MEM15_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM15_Pos) /*!< Bit mask of MEM15 field. */ + #define MEMCONF_POWER_CONTROL_MEM15_Min (0x0UL) /*!< Min enumerator value of MEM15 field. */ + #define MEMCONF_POWER_CONTROL_MEM15_Max (0x1UL) /*!< Max enumerator value of MEM15 field. */ + #define MEMCONF_POWER_CONTROL_MEM15_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM15_On (0x1UL) /*!< Power up */ + +/* MEM16 @Bit 16 : Keep the memory block MEM[16] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM16_Pos (16UL) /*!< Position of MEM16 field. */ + #define MEMCONF_POWER_CONTROL_MEM16_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM16_Pos) /*!< Bit mask of MEM16 field. */ + #define MEMCONF_POWER_CONTROL_MEM16_Min (0x0UL) /*!< Min enumerator value of MEM16 field. */ + #define MEMCONF_POWER_CONTROL_MEM16_Max (0x1UL) /*!< Max enumerator value of MEM16 field. */ + #define MEMCONF_POWER_CONTROL_MEM16_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM16_On (0x1UL) /*!< Power up */ + +/* MEM17 @Bit 17 : Keep the memory block MEM[17] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM17_Pos (17UL) /*!< Position of MEM17 field. */ + #define MEMCONF_POWER_CONTROL_MEM17_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM17_Pos) /*!< Bit mask of MEM17 field. */ + #define MEMCONF_POWER_CONTROL_MEM17_Min (0x0UL) /*!< Min enumerator value of MEM17 field. */ + #define MEMCONF_POWER_CONTROL_MEM17_Max (0x1UL) /*!< Max enumerator value of MEM17 field. */ + #define MEMCONF_POWER_CONTROL_MEM17_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM17_On (0x1UL) /*!< Power up */ + +/* MEM18 @Bit 18 : Keep the memory block MEM[18] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM18_Pos (18UL) /*!< Position of MEM18 field. */ + #define MEMCONF_POWER_CONTROL_MEM18_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM18_Pos) /*!< Bit mask of MEM18 field. */ + #define MEMCONF_POWER_CONTROL_MEM18_Min (0x0UL) /*!< Min enumerator value of MEM18 field. */ + #define MEMCONF_POWER_CONTROL_MEM18_Max (0x1UL) /*!< Max enumerator value of MEM18 field. */ + #define MEMCONF_POWER_CONTROL_MEM18_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM18_On (0x1UL) /*!< Power up */ + +/* MEM19 @Bit 19 : Keep the memory block MEM[19] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM19_Pos (19UL) /*!< Position of MEM19 field. */ + #define MEMCONF_POWER_CONTROL_MEM19_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM19_Pos) /*!< Bit mask of MEM19 field. */ + #define MEMCONF_POWER_CONTROL_MEM19_Min (0x0UL) /*!< Min enumerator value of MEM19 field. */ + #define MEMCONF_POWER_CONTROL_MEM19_Max (0x1UL) /*!< Max enumerator value of MEM19 field. */ + #define MEMCONF_POWER_CONTROL_MEM19_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM19_On (0x1UL) /*!< Power up */ + +/* MEM20 @Bit 20 : Keep the memory block MEM[20] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM20_Pos (20UL) /*!< Position of MEM20 field. */ + #define MEMCONF_POWER_CONTROL_MEM20_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM20_Pos) /*!< Bit mask of MEM20 field. */ + #define MEMCONF_POWER_CONTROL_MEM20_Min (0x0UL) /*!< Min enumerator value of MEM20 field. */ + #define MEMCONF_POWER_CONTROL_MEM20_Max (0x1UL) /*!< Max enumerator value of MEM20 field. */ + #define MEMCONF_POWER_CONTROL_MEM20_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM20_On (0x1UL) /*!< Power up */ + +/* MEM21 @Bit 21 : Keep the memory block MEM[21] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM21_Pos (21UL) /*!< Position of MEM21 field. */ + #define MEMCONF_POWER_CONTROL_MEM21_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM21_Pos) /*!< Bit mask of MEM21 field. */ + #define MEMCONF_POWER_CONTROL_MEM21_Min (0x0UL) /*!< Min enumerator value of MEM21 field. */ + #define MEMCONF_POWER_CONTROL_MEM21_Max (0x1UL) /*!< Max enumerator value of MEM21 field. */ + #define MEMCONF_POWER_CONTROL_MEM21_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM21_On (0x1UL) /*!< Power up */ + +/* MEM22 @Bit 22 : Keep the memory block MEM[22] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM22_Pos (22UL) /*!< Position of MEM22 field. */ + #define MEMCONF_POWER_CONTROL_MEM22_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM22_Pos) /*!< Bit mask of MEM22 field. */ + #define MEMCONF_POWER_CONTROL_MEM22_Min (0x0UL) /*!< Min enumerator value of MEM22 field. */ + #define MEMCONF_POWER_CONTROL_MEM22_Max (0x1UL) /*!< Max enumerator value of MEM22 field. */ + #define MEMCONF_POWER_CONTROL_MEM22_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM22_On (0x1UL) /*!< Power up */ + +/* MEM23 @Bit 23 : Keep the memory block MEM[23] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM23_Pos (23UL) /*!< Position of MEM23 field. */ + #define MEMCONF_POWER_CONTROL_MEM23_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM23_Pos) /*!< Bit mask of MEM23 field. */ + #define MEMCONF_POWER_CONTROL_MEM23_Min (0x0UL) /*!< Min enumerator value of MEM23 field. */ + #define MEMCONF_POWER_CONTROL_MEM23_Max (0x1UL) /*!< Max enumerator value of MEM23 field. */ + #define MEMCONF_POWER_CONTROL_MEM23_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM23_On (0x1UL) /*!< Power up */ + +/* MEM24 @Bit 24 : Keep the memory block MEM[24] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM24_Pos (24UL) /*!< Position of MEM24 field. */ + #define MEMCONF_POWER_CONTROL_MEM24_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM24_Pos) /*!< Bit mask of MEM24 field. */ + #define MEMCONF_POWER_CONTROL_MEM24_Min (0x0UL) /*!< Min enumerator value of MEM24 field. */ + #define MEMCONF_POWER_CONTROL_MEM24_Max (0x1UL) /*!< Max enumerator value of MEM24 field. */ + #define MEMCONF_POWER_CONTROL_MEM24_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM24_On (0x1UL) /*!< Power up */ + +/* MEM25 @Bit 25 : Keep the memory block MEM[25] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM25_Pos (25UL) /*!< Position of MEM25 field. */ + #define MEMCONF_POWER_CONTROL_MEM25_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM25_Pos) /*!< Bit mask of MEM25 field. */ + #define MEMCONF_POWER_CONTROL_MEM25_Min (0x0UL) /*!< Min enumerator value of MEM25 field. */ + #define MEMCONF_POWER_CONTROL_MEM25_Max (0x1UL) /*!< Max enumerator value of MEM25 field. */ + #define MEMCONF_POWER_CONTROL_MEM25_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM25_On (0x1UL) /*!< Power up */ + +/* MEM26 @Bit 26 : Keep the memory block MEM[26] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM26_Pos (26UL) /*!< Position of MEM26 field. */ + #define MEMCONF_POWER_CONTROL_MEM26_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM26_Pos) /*!< Bit mask of MEM26 field. */ + #define MEMCONF_POWER_CONTROL_MEM26_Min (0x0UL) /*!< Min enumerator value of MEM26 field. */ + #define MEMCONF_POWER_CONTROL_MEM26_Max (0x1UL) /*!< Max enumerator value of MEM26 field. */ + #define MEMCONF_POWER_CONTROL_MEM26_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM26_On (0x1UL) /*!< Power up */ + +/* MEM27 @Bit 27 : Keep the memory block MEM[27] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM27_Pos (27UL) /*!< Position of MEM27 field. */ + #define MEMCONF_POWER_CONTROL_MEM27_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM27_Pos) /*!< Bit mask of MEM27 field. */ + #define MEMCONF_POWER_CONTROL_MEM27_Min (0x0UL) /*!< Min enumerator value of MEM27 field. */ + #define MEMCONF_POWER_CONTROL_MEM27_Max (0x1UL) /*!< Max enumerator value of MEM27 field. */ + #define MEMCONF_POWER_CONTROL_MEM27_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM27_On (0x1UL) /*!< Power up */ + +/* MEM28 @Bit 28 : Keep the memory block MEM[28] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM28_Pos (28UL) /*!< Position of MEM28 field. */ + #define MEMCONF_POWER_CONTROL_MEM28_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM28_Pos) /*!< Bit mask of MEM28 field. */ + #define MEMCONF_POWER_CONTROL_MEM28_Min (0x0UL) /*!< Min enumerator value of MEM28 field. */ + #define MEMCONF_POWER_CONTROL_MEM28_Max (0x1UL) /*!< Max enumerator value of MEM28 field. */ + #define MEMCONF_POWER_CONTROL_MEM28_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM28_On (0x1UL) /*!< Power up */ + +/* MEM29 @Bit 29 : Keep the memory block MEM[29] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM29_Pos (29UL) /*!< Position of MEM29 field. */ + #define MEMCONF_POWER_CONTROL_MEM29_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM29_Pos) /*!< Bit mask of MEM29 field. */ + #define MEMCONF_POWER_CONTROL_MEM29_Min (0x0UL) /*!< Min enumerator value of MEM29 field. */ + #define MEMCONF_POWER_CONTROL_MEM29_Max (0x1UL) /*!< Max enumerator value of MEM29 field. */ + #define MEMCONF_POWER_CONTROL_MEM29_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM29_On (0x1UL) /*!< Power up */ + +/* MEM30 @Bit 30 : Keep the memory block MEM[30] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM30_Pos (30UL) /*!< Position of MEM30 field. */ + #define MEMCONF_POWER_CONTROL_MEM30_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM30_Pos) /*!< Bit mask of MEM30 field. */ + #define MEMCONF_POWER_CONTROL_MEM30_Min (0x0UL) /*!< Min enumerator value of MEM30 field. */ + #define MEMCONF_POWER_CONTROL_MEM30_Max (0x1UL) /*!< Max enumerator value of MEM30 field. */ + #define MEMCONF_POWER_CONTROL_MEM30_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM30_On (0x1UL) /*!< Power up */ + +/* MEM31 @Bit 31 : Keep the memory block MEM[31] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM31_Pos (31UL) /*!< Position of MEM31 field. */ + #define MEMCONF_POWER_CONTROL_MEM31_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM31_Pos) /*!< Bit mask of MEM31 field. */ + #define MEMCONF_POWER_CONTROL_MEM31_Min (0x0UL) /*!< Min enumerator value of MEM31 field. */ + #define MEMCONF_POWER_CONTROL_MEM31_Max (0x1UL) /*!< Max enumerator value of MEM31 field. */ + #define MEMCONF_POWER_CONTROL_MEM31_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM31_On (0x1UL) /*!< Power up */ + + +/* MEMCONF_POWER_RET: RAM retention for RAM [n]. */ + #define MEMCONF_POWER_RET_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RET register. */ + +/* MEM0 @Bit 0 : Keep the RAM block MEM[0] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM0_Pos (0UL) /*!< Position of MEM0 field. */ + #define MEMCONF_POWER_RET_MEM0_Msk (0x1UL << MEMCONF_POWER_RET_MEM0_Pos) /*!< Bit mask of MEM0 field. */ + #define MEMCONF_POWER_RET_MEM0_Min (0x0UL) /*!< Min enumerator value of MEM0 field. */ + #define MEMCONF_POWER_RET_MEM0_Max (0x1UL) /*!< Max enumerator value of MEM0 field. */ + #define MEMCONF_POWER_RET_MEM0_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM0_On (0x1UL) /*!< Retention on */ + +/* MEM1 @Bit 1 : Keep the RAM block MEM[1] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM1_Pos (1UL) /*!< Position of MEM1 field. */ + #define MEMCONF_POWER_RET_MEM1_Msk (0x1UL << MEMCONF_POWER_RET_MEM1_Pos) /*!< Bit mask of MEM1 field. */ + #define MEMCONF_POWER_RET_MEM1_Min (0x0UL) /*!< Min enumerator value of MEM1 field. */ + #define MEMCONF_POWER_RET_MEM1_Max (0x1UL) /*!< Max enumerator value of MEM1 field. */ + #define MEMCONF_POWER_RET_MEM1_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM1_On (0x1UL) /*!< Retention on */ + +/* MEM2 @Bit 2 : Keep the RAM block MEM[2] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM2_Pos (2UL) /*!< Position of MEM2 field. */ + #define MEMCONF_POWER_RET_MEM2_Msk (0x1UL << MEMCONF_POWER_RET_MEM2_Pos) /*!< Bit mask of MEM2 field. */ + #define MEMCONF_POWER_RET_MEM2_Min (0x0UL) /*!< Min enumerator value of MEM2 field. */ + #define MEMCONF_POWER_RET_MEM2_Max (0x1UL) /*!< Max enumerator value of MEM2 field. */ + #define MEMCONF_POWER_RET_MEM2_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM2_On (0x1UL) /*!< Retention on */ + +/* MEM3 @Bit 3 : Keep the RAM block MEM[3] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM3_Pos (3UL) /*!< Position of MEM3 field. */ + #define MEMCONF_POWER_RET_MEM3_Msk (0x1UL << MEMCONF_POWER_RET_MEM3_Pos) /*!< Bit mask of MEM3 field. */ + #define MEMCONF_POWER_RET_MEM3_Min (0x0UL) /*!< Min enumerator value of MEM3 field. */ + #define MEMCONF_POWER_RET_MEM3_Max (0x1UL) /*!< Max enumerator value of MEM3 field. */ + #define MEMCONF_POWER_RET_MEM3_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM3_On (0x1UL) /*!< Retention on */ + +/* MEM4 @Bit 4 : Keep the RAM block MEM[4] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM4_Pos (4UL) /*!< Position of MEM4 field. */ + #define MEMCONF_POWER_RET_MEM4_Msk (0x1UL << MEMCONF_POWER_RET_MEM4_Pos) /*!< Bit mask of MEM4 field. */ + #define MEMCONF_POWER_RET_MEM4_Min (0x0UL) /*!< Min enumerator value of MEM4 field. */ + #define MEMCONF_POWER_RET_MEM4_Max (0x1UL) /*!< Max enumerator value of MEM4 field. */ + #define MEMCONF_POWER_RET_MEM4_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM4_On (0x1UL) /*!< Retention on */ + +/* MEM5 @Bit 5 : Keep the RAM block MEM[5] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM5_Pos (5UL) /*!< Position of MEM5 field. */ + #define MEMCONF_POWER_RET_MEM5_Msk (0x1UL << MEMCONF_POWER_RET_MEM5_Pos) /*!< Bit mask of MEM5 field. */ + #define MEMCONF_POWER_RET_MEM5_Min (0x0UL) /*!< Min enumerator value of MEM5 field. */ + #define MEMCONF_POWER_RET_MEM5_Max (0x1UL) /*!< Max enumerator value of MEM5 field. */ + #define MEMCONF_POWER_RET_MEM5_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM5_On (0x1UL) /*!< Retention on */ + +/* MEM6 @Bit 6 : Keep the RAM block MEM[6] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM6_Pos (6UL) /*!< Position of MEM6 field. */ + #define MEMCONF_POWER_RET_MEM6_Msk (0x1UL << MEMCONF_POWER_RET_MEM6_Pos) /*!< Bit mask of MEM6 field. */ + #define MEMCONF_POWER_RET_MEM6_Min (0x0UL) /*!< Min enumerator value of MEM6 field. */ + #define MEMCONF_POWER_RET_MEM6_Max (0x1UL) /*!< Max enumerator value of MEM6 field. */ + #define MEMCONF_POWER_RET_MEM6_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM6_On (0x1UL) /*!< Retention on */ + +/* MEM7 @Bit 7 : Keep the RAM block MEM[7] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM7_Pos (7UL) /*!< Position of MEM7 field. */ + #define MEMCONF_POWER_RET_MEM7_Msk (0x1UL << MEMCONF_POWER_RET_MEM7_Pos) /*!< Bit mask of MEM7 field. */ + #define MEMCONF_POWER_RET_MEM7_Min (0x0UL) /*!< Min enumerator value of MEM7 field. */ + #define MEMCONF_POWER_RET_MEM7_Max (0x1UL) /*!< Max enumerator value of MEM7 field. */ + #define MEMCONF_POWER_RET_MEM7_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM7_On (0x1UL) /*!< Retention on */ + +/* MEM8 @Bit 8 : Keep the RAM block MEM[8] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM8_Pos (8UL) /*!< Position of MEM8 field. */ + #define MEMCONF_POWER_RET_MEM8_Msk (0x1UL << MEMCONF_POWER_RET_MEM8_Pos) /*!< Bit mask of MEM8 field. */ + #define MEMCONF_POWER_RET_MEM8_Min (0x0UL) /*!< Min enumerator value of MEM8 field. */ + #define MEMCONF_POWER_RET_MEM8_Max (0x1UL) /*!< Max enumerator value of MEM8 field. */ + #define MEMCONF_POWER_RET_MEM8_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM8_On (0x1UL) /*!< Retention on */ + +/* MEM9 @Bit 9 : Keep the RAM block MEM[9] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM9_Pos (9UL) /*!< Position of MEM9 field. */ + #define MEMCONF_POWER_RET_MEM9_Msk (0x1UL << MEMCONF_POWER_RET_MEM9_Pos) /*!< Bit mask of MEM9 field. */ + #define MEMCONF_POWER_RET_MEM9_Min (0x0UL) /*!< Min enumerator value of MEM9 field. */ + #define MEMCONF_POWER_RET_MEM9_Max (0x1UL) /*!< Max enumerator value of MEM9 field. */ + #define MEMCONF_POWER_RET_MEM9_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM9_On (0x1UL) /*!< Retention on */ + +/* MEM10 @Bit 10 : Keep the RAM block MEM[10] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM10_Pos (10UL) /*!< Position of MEM10 field. */ + #define MEMCONF_POWER_RET_MEM10_Msk (0x1UL << MEMCONF_POWER_RET_MEM10_Pos) /*!< Bit mask of MEM10 field. */ + #define MEMCONF_POWER_RET_MEM10_Min (0x0UL) /*!< Min enumerator value of MEM10 field. */ + #define MEMCONF_POWER_RET_MEM10_Max (0x1UL) /*!< Max enumerator value of MEM10 field. */ + #define MEMCONF_POWER_RET_MEM10_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM10_On (0x1UL) /*!< Retention on */ + +/* MEM11 @Bit 11 : Keep the RAM block MEM[11] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM11_Pos (11UL) /*!< Position of MEM11 field. */ + #define MEMCONF_POWER_RET_MEM11_Msk (0x1UL << MEMCONF_POWER_RET_MEM11_Pos) /*!< Bit mask of MEM11 field. */ + #define MEMCONF_POWER_RET_MEM11_Min (0x0UL) /*!< Min enumerator value of MEM11 field. */ + #define MEMCONF_POWER_RET_MEM11_Max (0x1UL) /*!< Max enumerator value of MEM11 field. */ + #define MEMCONF_POWER_RET_MEM11_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM11_On (0x1UL) /*!< Retention on */ + +/* MEM12 @Bit 12 : Keep the RAM block MEM[12] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM12_Pos (12UL) /*!< Position of MEM12 field. */ + #define MEMCONF_POWER_RET_MEM12_Msk (0x1UL << MEMCONF_POWER_RET_MEM12_Pos) /*!< Bit mask of MEM12 field. */ + #define MEMCONF_POWER_RET_MEM12_Min (0x0UL) /*!< Min enumerator value of MEM12 field. */ + #define MEMCONF_POWER_RET_MEM12_Max (0x1UL) /*!< Max enumerator value of MEM12 field. */ + #define MEMCONF_POWER_RET_MEM12_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM12_On (0x1UL) /*!< Retention on */ + +/* MEM13 @Bit 13 : Keep the RAM block MEM[13] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM13_Pos (13UL) /*!< Position of MEM13 field. */ + #define MEMCONF_POWER_RET_MEM13_Msk (0x1UL << MEMCONF_POWER_RET_MEM13_Pos) /*!< Bit mask of MEM13 field. */ + #define MEMCONF_POWER_RET_MEM13_Min (0x0UL) /*!< Min enumerator value of MEM13 field. */ + #define MEMCONF_POWER_RET_MEM13_Max (0x1UL) /*!< Max enumerator value of MEM13 field. */ + #define MEMCONF_POWER_RET_MEM13_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM13_On (0x1UL) /*!< Retention on */ + +/* MEM14 @Bit 14 : Keep the RAM block MEM[14] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM14_Pos (14UL) /*!< Position of MEM14 field. */ + #define MEMCONF_POWER_RET_MEM14_Msk (0x1UL << MEMCONF_POWER_RET_MEM14_Pos) /*!< Bit mask of MEM14 field. */ + #define MEMCONF_POWER_RET_MEM14_Min (0x0UL) /*!< Min enumerator value of MEM14 field. */ + #define MEMCONF_POWER_RET_MEM14_Max (0x1UL) /*!< Max enumerator value of MEM14 field. */ + #define MEMCONF_POWER_RET_MEM14_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM14_On (0x1UL) /*!< Retention on */ + +/* MEM15 @Bit 15 : Keep the RAM block MEM[15] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM15_Pos (15UL) /*!< Position of MEM15 field. */ + #define MEMCONF_POWER_RET_MEM15_Msk (0x1UL << MEMCONF_POWER_RET_MEM15_Pos) /*!< Bit mask of MEM15 field. */ + #define MEMCONF_POWER_RET_MEM15_Min (0x0UL) /*!< Min enumerator value of MEM15 field. */ + #define MEMCONF_POWER_RET_MEM15_Max (0x1UL) /*!< Max enumerator value of MEM15 field. */ + #define MEMCONF_POWER_RET_MEM15_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM15_On (0x1UL) /*!< Retention on */ + +/* MEM16 @Bit 16 : Keep the RAM block MEM[16] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM16_Pos (16UL) /*!< Position of MEM16 field. */ + #define MEMCONF_POWER_RET_MEM16_Msk (0x1UL << MEMCONF_POWER_RET_MEM16_Pos) /*!< Bit mask of MEM16 field. */ + #define MEMCONF_POWER_RET_MEM16_Min (0x0UL) /*!< Min enumerator value of MEM16 field. */ + #define MEMCONF_POWER_RET_MEM16_Max (0x1UL) /*!< Max enumerator value of MEM16 field. */ + #define MEMCONF_POWER_RET_MEM16_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM16_On (0x1UL) /*!< Retention on */ + +/* MEM17 @Bit 17 : Keep the RAM block MEM[17] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM17_Pos (17UL) /*!< Position of MEM17 field. */ + #define MEMCONF_POWER_RET_MEM17_Msk (0x1UL << MEMCONF_POWER_RET_MEM17_Pos) /*!< Bit mask of MEM17 field. */ + #define MEMCONF_POWER_RET_MEM17_Min (0x0UL) /*!< Min enumerator value of MEM17 field. */ + #define MEMCONF_POWER_RET_MEM17_Max (0x1UL) /*!< Max enumerator value of MEM17 field. */ + #define MEMCONF_POWER_RET_MEM17_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM17_On (0x1UL) /*!< Retention on */ + +/* MEM18 @Bit 18 : Keep the RAM block MEM[18] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM18_Pos (18UL) /*!< Position of MEM18 field. */ + #define MEMCONF_POWER_RET_MEM18_Msk (0x1UL << MEMCONF_POWER_RET_MEM18_Pos) /*!< Bit mask of MEM18 field. */ + #define MEMCONF_POWER_RET_MEM18_Min (0x0UL) /*!< Min enumerator value of MEM18 field. */ + #define MEMCONF_POWER_RET_MEM18_Max (0x1UL) /*!< Max enumerator value of MEM18 field. */ + #define MEMCONF_POWER_RET_MEM18_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM18_On (0x1UL) /*!< Retention on */ + +/* MEM19 @Bit 19 : Keep the RAM block MEM[19] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM19_Pos (19UL) /*!< Position of MEM19 field. */ + #define MEMCONF_POWER_RET_MEM19_Msk (0x1UL << MEMCONF_POWER_RET_MEM19_Pos) /*!< Bit mask of MEM19 field. */ + #define MEMCONF_POWER_RET_MEM19_Min (0x0UL) /*!< Min enumerator value of MEM19 field. */ + #define MEMCONF_POWER_RET_MEM19_Max (0x1UL) /*!< Max enumerator value of MEM19 field. */ + #define MEMCONF_POWER_RET_MEM19_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM19_On (0x1UL) /*!< Retention on */ + +/* MEM20 @Bit 20 : Keep the RAM block MEM[20] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM20_Pos (20UL) /*!< Position of MEM20 field. */ + #define MEMCONF_POWER_RET_MEM20_Msk (0x1UL << MEMCONF_POWER_RET_MEM20_Pos) /*!< Bit mask of MEM20 field. */ + #define MEMCONF_POWER_RET_MEM20_Min (0x0UL) /*!< Min enumerator value of MEM20 field. */ + #define MEMCONF_POWER_RET_MEM20_Max (0x1UL) /*!< Max enumerator value of MEM20 field. */ + #define MEMCONF_POWER_RET_MEM20_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM20_On (0x1UL) /*!< Retention on */ + +/* MEM21 @Bit 21 : Keep the RAM block MEM[21] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM21_Pos (21UL) /*!< Position of MEM21 field. */ + #define MEMCONF_POWER_RET_MEM21_Msk (0x1UL << MEMCONF_POWER_RET_MEM21_Pos) /*!< Bit mask of MEM21 field. */ + #define MEMCONF_POWER_RET_MEM21_Min (0x0UL) /*!< Min enumerator value of MEM21 field. */ + #define MEMCONF_POWER_RET_MEM21_Max (0x1UL) /*!< Max enumerator value of MEM21 field. */ + #define MEMCONF_POWER_RET_MEM21_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM21_On (0x1UL) /*!< Retention on */ + +/* MEM22 @Bit 22 : Keep the RAM block MEM[22] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM22_Pos (22UL) /*!< Position of MEM22 field. */ + #define MEMCONF_POWER_RET_MEM22_Msk (0x1UL << MEMCONF_POWER_RET_MEM22_Pos) /*!< Bit mask of MEM22 field. */ + #define MEMCONF_POWER_RET_MEM22_Min (0x0UL) /*!< Min enumerator value of MEM22 field. */ + #define MEMCONF_POWER_RET_MEM22_Max (0x1UL) /*!< Max enumerator value of MEM22 field. */ + #define MEMCONF_POWER_RET_MEM22_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM22_On (0x1UL) /*!< Retention on */ + +/* MEM23 @Bit 23 : Keep the RAM block MEM[23] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM23_Pos (23UL) /*!< Position of MEM23 field. */ + #define MEMCONF_POWER_RET_MEM23_Msk (0x1UL << MEMCONF_POWER_RET_MEM23_Pos) /*!< Bit mask of MEM23 field. */ + #define MEMCONF_POWER_RET_MEM23_Min (0x0UL) /*!< Min enumerator value of MEM23 field. */ + #define MEMCONF_POWER_RET_MEM23_Max (0x1UL) /*!< Max enumerator value of MEM23 field. */ + #define MEMCONF_POWER_RET_MEM23_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM23_On (0x1UL) /*!< Retention on */ + +/* MEM24 @Bit 24 : Keep the RAM block MEM[24] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM24_Pos (24UL) /*!< Position of MEM24 field. */ + #define MEMCONF_POWER_RET_MEM24_Msk (0x1UL << MEMCONF_POWER_RET_MEM24_Pos) /*!< Bit mask of MEM24 field. */ + #define MEMCONF_POWER_RET_MEM24_Min (0x0UL) /*!< Min enumerator value of MEM24 field. */ + #define MEMCONF_POWER_RET_MEM24_Max (0x1UL) /*!< Max enumerator value of MEM24 field. */ + #define MEMCONF_POWER_RET_MEM24_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM24_On (0x1UL) /*!< Retention on */ + +/* MEM25 @Bit 25 : Keep the RAM block MEM[25] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM25_Pos (25UL) /*!< Position of MEM25 field. */ + #define MEMCONF_POWER_RET_MEM25_Msk (0x1UL << MEMCONF_POWER_RET_MEM25_Pos) /*!< Bit mask of MEM25 field. */ + #define MEMCONF_POWER_RET_MEM25_Min (0x0UL) /*!< Min enumerator value of MEM25 field. */ + #define MEMCONF_POWER_RET_MEM25_Max (0x1UL) /*!< Max enumerator value of MEM25 field. */ + #define MEMCONF_POWER_RET_MEM25_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM25_On (0x1UL) /*!< Retention on */ + +/* MEM26 @Bit 26 : Keep the RAM block MEM[26] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM26_Pos (26UL) /*!< Position of MEM26 field. */ + #define MEMCONF_POWER_RET_MEM26_Msk (0x1UL << MEMCONF_POWER_RET_MEM26_Pos) /*!< Bit mask of MEM26 field. */ + #define MEMCONF_POWER_RET_MEM26_Min (0x0UL) /*!< Min enumerator value of MEM26 field. */ + #define MEMCONF_POWER_RET_MEM26_Max (0x1UL) /*!< Max enumerator value of MEM26 field. */ + #define MEMCONF_POWER_RET_MEM26_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM26_On (0x1UL) /*!< Retention on */ + +/* MEM27 @Bit 27 : Keep the RAM block MEM[27] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM27_Pos (27UL) /*!< Position of MEM27 field. */ + #define MEMCONF_POWER_RET_MEM27_Msk (0x1UL << MEMCONF_POWER_RET_MEM27_Pos) /*!< Bit mask of MEM27 field. */ + #define MEMCONF_POWER_RET_MEM27_Min (0x0UL) /*!< Min enumerator value of MEM27 field. */ + #define MEMCONF_POWER_RET_MEM27_Max (0x1UL) /*!< Max enumerator value of MEM27 field. */ + #define MEMCONF_POWER_RET_MEM27_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM27_On (0x1UL) /*!< Retention on */ + +/* MEM28 @Bit 28 : Keep the RAM block MEM[28] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM28_Pos (28UL) /*!< Position of MEM28 field. */ + #define MEMCONF_POWER_RET_MEM28_Msk (0x1UL << MEMCONF_POWER_RET_MEM28_Pos) /*!< Bit mask of MEM28 field. */ + #define MEMCONF_POWER_RET_MEM28_Min (0x0UL) /*!< Min enumerator value of MEM28 field. */ + #define MEMCONF_POWER_RET_MEM28_Max (0x1UL) /*!< Max enumerator value of MEM28 field. */ + #define MEMCONF_POWER_RET_MEM28_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM28_On (0x1UL) /*!< Retention on */ + +/* MEM29 @Bit 29 : Keep the RAM block MEM[29] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM29_Pos (29UL) /*!< Position of MEM29 field. */ + #define MEMCONF_POWER_RET_MEM29_Msk (0x1UL << MEMCONF_POWER_RET_MEM29_Pos) /*!< Bit mask of MEM29 field. */ + #define MEMCONF_POWER_RET_MEM29_Min (0x0UL) /*!< Min enumerator value of MEM29 field. */ + #define MEMCONF_POWER_RET_MEM29_Max (0x1UL) /*!< Max enumerator value of MEM29 field. */ + #define MEMCONF_POWER_RET_MEM29_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM29_On (0x1UL) /*!< Retention on */ + +/* MEM30 @Bit 30 : Keep the RAM block MEM[30] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM30_Pos (30UL) /*!< Position of MEM30 field. */ + #define MEMCONF_POWER_RET_MEM30_Msk (0x1UL << MEMCONF_POWER_RET_MEM30_Pos) /*!< Bit mask of MEM30 field. */ + #define MEMCONF_POWER_RET_MEM30_Min (0x0UL) /*!< Min enumerator value of MEM30 field. */ + #define MEMCONF_POWER_RET_MEM30_Max (0x1UL) /*!< Max enumerator value of MEM30 field. */ + #define MEMCONF_POWER_RET_MEM30_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM30_On (0x1UL) /*!< Retention on */ + +/* MEM31 @Bit 31 : Keep the RAM block MEM[31] retained when in System OFF mode. */ + #define MEMCONF_POWER_RET_MEM31_Pos (31UL) /*!< Position of MEM31 field. */ + #define MEMCONF_POWER_RET_MEM31_Msk (0x1UL << MEMCONF_POWER_RET_MEM31_Pos) /*!< Bit mask of MEM31 field. */ + #define MEMCONF_POWER_RET_MEM31_Min (0x0UL) /*!< Min enumerator value of MEM31 field. */ + #define MEMCONF_POWER_RET_MEM31_Max (0x1UL) /*!< Max enumerator value of MEM31 field. */ + #define MEMCONF_POWER_RET_MEM31_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM31_On (0x1UL) /*!< Retention on */ + + +/* ===================================================== Struct MEMCONF ====================================================== */ +/** + * @brief Memory configuration + */ + typedef struct { /*!< MEMCONF Structure */ + __IM uint32_t RESERVED[320]; + __IOM NRF_MEMCONF_POWER_Type POWER[2]; /*!< (@ 0x00000500) (unspecified) */ + } NRF_MEMCONF_Type; /*!< Size = 1312 (0x520) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ MPC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct MPC_MEMACCERR =================================================== */ +/** + * @brief MEMACCERR [MPC_MEMACCERR] Memory Access Error status registers + */ +typedef struct { + __IM uint32_t ADDRESS; /*!< (@ 0x00000000) Target Address of Memory Access Error. Register content + will not be changed as long as MEMACCERR event is + active.*/ + __IM uint32_t INFO; /*!< (@ 0x00000004) Access information for the transaction that triggered a + memory access error. Register content will not be + changed as long as MEMACCERR event is active.*/ +} NRF_MPC_MEMACCERR_Type; /*!< Size = 8 (0x008) */ + +/* MPC_MEMACCERR_ADDRESS: Target Address of Memory Access Error. Register content will not be changed as long as MEMACCERR event + is active. */ + + #define MPC_MEMACCERR_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* ADDRESS @Bits 0..31 : Target address for erroneous access */ + #define MPC_MEMACCERR_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define MPC_MEMACCERR_ADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << MPC_MEMACCERR_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.*/ + + +/* MPC_MEMACCERR_INFO: Access information for the transaction that triggered a memory access error. Register content will not be + changed as long as MEMACCERR event is active. */ + + #define MPC_MEMACCERR_INFO_ResetValue (0x00000000UL) /*!< Reset value of INFO register. */ + +/* READ @Bit 12 : Read bit of bus access */ + #define MPC_MEMACCERR_INFO_READ_Pos (12UL) /*!< Position of READ field. */ + #define MPC_MEMACCERR_INFO_READ_Msk (0x1UL << MPC_MEMACCERR_INFO_READ_Pos) /*!< Bit mask of READ field. */ + #define MPC_MEMACCERR_INFO_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define MPC_MEMACCERR_INFO_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define MPC_MEMACCERR_INFO_READ_Set (0x1UL) /*!< Read access bit was set */ + #define MPC_MEMACCERR_INFO_READ_NotSet (0x0UL) /*!< Read access bit was not set */ + +/* WRITE @Bit 13 : Write bit of bus access */ + #define MPC_MEMACCERR_INFO_WRITE_Pos (13UL) /*!< Position of WRITE field. */ + #define MPC_MEMACCERR_INFO_WRITE_Msk (0x1UL << MPC_MEMACCERR_INFO_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define MPC_MEMACCERR_INFO_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define MPC_MEMACCERR_INFO_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define MPC_MEMACCERR_INFO_WRITE_Set (0x1UL) /*!< Write access bit was set */ + #define MPC_MEMACCERR_INFO_WRITE_NotSet (0x0UL) /*!< Write access bit was not set */ + +/* EXECUTE @Bit 14 : Execute bit of bus access */ + #define MPC_MEMACCERR_INFO_EXECUTE_Pos (14UL) /*!< Position of EXECUTE field. */ + #define MPC_MEMACCERR_INFO_EXECUTE_Msk (0x1UL << MPC_MEMACCERR_INFO_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ + #define MPC_MEMACCERR_INFO_EXECUTE_Min (0x0UL) /*!< Min enumerator value of EXECUTE field. */ + #define MPC_MEMACCERR_INFO_EXECUTE_Max (0x1UL) /*!< Max enumerator value of EXECUTE field. */ + #define MPC_MEMACCERR_INFO_EXECUTE_Set (0x1UL) /*!< Execute access bit was set */ + #define MPC_MEMACCERR_INFO_EXECUTE_NotSet (0x0UL) /*!< Execute access bit was not set */ + +/* SECURE @Bit 15 : Secure bit of bus access */ + #define MPC_MEMACCERR_INFO_SECURE_Pos (15UL) /*!< Position of SECURE field. */ + #define MPC_MEMACCERR_INFO_SECURE_Msk (0x1UL << MPC_MEMACCERR_INFO_SECURE_Pos) /*!< Bit mask of SECURE field. */ + #define MPC_MEMACCERR_INFO_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field. */ + #define MPC_MEMACCERR_INFO_SECURE_Max (0x1UL) /*!< Max enumerator value of SECURE field. */ + #define MPC_MEMACCERR_INFO_SECURE_Set (0x1UL) /*!< Secure access bit was set */ + #define MPC_MEMACCERR_INFO_SECURE_NotSet (0x0UL) /*!< Secure access bit was not set */ + +/* ERRORSOURCE @Bit 16 : Source of memory access error */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_Pos (16UL) /*!< Position of ERRORSOURCE field. */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_Msk (0x1UL << MPC_MEMACCERR_INFO_ERRORSOURCE_Pos) /*!< Bit mask of ERRORSOURCE field. */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_Min (0x0UL) /*!< Min enumerator value of ERRORSOURCE field. */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_Max (0x1UL) /*!< Max enumerator value of ERRORSOURCE field. */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_MPC (0x1UL) /*!< Error was triggered by MPC module */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_Slave (0x0UL) /*!< Error was triggered by a Subordinate */ + + + +/* =================================================== Struct MPC_OVERRIDE =================================================== */ +/** + * @brief OVERRIDE [MPC_OVERRIDE] Special privilege tables + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Override region n Configuration register */ + __IOM uint32_t STARTADDR; /*!< (@ 0x00000004) Override region n Start Address */ + __IOM uint32_t ENDADDR; /*!< (@ 0x00000008) Override region n End Address */ + __IM uint32_t RESERVED; + __IOM uint32_t PERM; /*!< (@ 0x00000010) Permission settings for override region n */ + __IOM uint32_t PERMMASK; /*!< (@ 0x00000014) Masks permission setting fields from register + OVERRIDE.PERM*/ + __IM uint32_t RESERVED1[2]; +} NRF_MPC_OVERRIDE_Type; /*!< Size = 32 (0x020) */ + #define MPC_OVERRIDE_MaxCount (12UL) /*!< Size of OVERRIDE[12] array. */ + #define MPC_OVERRIDE_MaxIndex (11UL) /*!< Max index of OVERRIDE[12] array. */ + #define MPC_OVERRIDE_MinIndex (0UL) /*!< Min index of OVERRIDE[12] array. */ + +/* MPC_OVERRIDE_CONFIG: Override region n Configuration register */ + #define MPC_OVERRIDE_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* LOCK @Bit 8 : Lock Override region n */ + #define MPC_OVERRIDE_CONFIG_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define MPC_OVERRIDE_CONFIG_LOCK_Msk (0x1UL << MPC_OVERRIDE_CONFIG_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define MPC_OVERRIDE_CONFIG_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define MPC_OVERRIDE_CONFIG_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define MPC_OVERRIDE_CONFIG_LOCK_Unlocked (0x0UL) /*!< Override region n settings can be updated */ + #define MPC_OVERRIDE_CONFIG_LOCK_Locked (0x1UL) /*!< Override region n settings can not be updated until next reset */ + +/* ENABLE @Bit 9 : Enable Override region n */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Pos (9UL) /*!< Position of ENABLE field. */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Msk (0x1UL << MPC_OVERRIDE_CONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Disabled (0x0UL) /*!< Override region n is not used */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Enabled (0x1UL) /*!< Override region n is used */ + + +/* MPC_OVERRIDE_STARTADDR: Override region n Start Address */ + #define MPC_OVERRIDE_STARTADDR_ResetValue (0x00000000UL) /*!< Reset value of STARTADDR register. */ + +/* STARTADDR @Bits 0..31 : Start address for override region n */ + #define MPC_OVERRIDE_STARTADDR_STARTADDR_Pos (0UL) /*!< Position of STARTADDR field. */ + #define MPC_OVERRIDE_STARTADDR_STARTADDR_Msk (0xFFFFFFFFUL << MPC_OVERRIDE_STARTADDR_STARTADDR_Pos) /*!< Bit mask of STARTADDR + field.*/ + + +/* MPC_OVERRIDE_ENDADDR: Override region n End Address */ + #define MPC_OVERRIDE_ENDADDR_ResetValue (0x00000000UL) /*!< Reset value of ENDADDR register. */ + +/* ENDADDR @Bits 0..31 : End address for override region n */ + #define MPC_OVERRIDE_ENDADDR_ENDADDR_Pos (0UL) /*!< Position of ENDADDR field. */ + #define MPC_OVERRIDE_ENDADDR_ENDADDR_Msk (0xFFFFFFFFUL << MPC_OVERRIDE_ENDADDR_ENDADDR_Pos) /*!< Bit mask of ENDADDR field. */ + + +/* MPC_OVERRIDE_PERM: Permission settings for override region n */ + #define MPC_OVERRIDE_PERM_ResetValue (0x00000000UL) /*!< Reset value of PERM register. */ + +/* READ @Bit 0 : Read access */ + #define MPC_OVERRIDE_PERM_READ_Pos (0UL) /*!< Position of READ field. */ + #define MPC_OVERRIDE_PERM_READ_Msk (0x1UL << MPC_OVERRIDE_PERM_READ_Pos) /*!< Bit mask of READ field. */ + #define MPC_OVERRIDE_PERM_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define MPC_OVERRIDE_PERM_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define MPC_OVERRIDE_PERM_READ_NotAllowed (0x0UL) /*!< Read access to override region n is not allowed */ + #define MPC_OVERRIDE_PERM_READ_Allowed (0x1UL) /*!< Read access to override region n is allowed */ + +/* WRITE @Bit 1 : Write access */ + #define MPC_OVERRIDE_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ + #define MPC_OVERRIDE_PERM_WRITE_Msk (0x1UL << MPC_OVERRIDE_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define MPC_OVERRIDE_PERM_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define MPC_OVERRIDE_PERM_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define MPC_OVERRIDE_PERM_WRITE_NotAllowed (0x0UL) /*!< Write access to override region n is not allowed */ + #define MPC_OVERRIDE_PERM_WRITE_Allowed (0x1UL) /*!< Write access to override region n is allowed */ + +/* EXECUTE @Bit 2 : Software execute */ + #define MPC_OVERRIDE_PERM_EXECUTE_Pos (2UL) /*!< Position of EXECUTE field. */ + #define MPC_OVERRIDE_PERM_EXECUTE_Msk (0x1UL << MPC_OVERRIDE_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ + #define MPC_OVERRIDE_PERM_EXECUTE_Min (0x0UL) /*!< Min enumerator value of EXECUTE field. */ + #define MPC_OVERRIDE_PERM_EXECUTE_Max (0x1UL) /*!< Max enumerator value of EXECUTE field. */ + #define MPC_OVERRIDE_PERM_EXECUTE_NotAllowed (0x0UL) /*!< Software execution from override region n is not allowed */ + #define MPC_OVERRIDE_PERM_EXECUTE_Allowed (0x1UL) /*!< Software execution from override region n is allowed */ + +/* SECATTR @Bit 3 : Security mapping */ + #define MPC_OVERRIDE_PERM_SECATTR_Pos (3UL) /*!< Position of SECATTR field. */ + #define MPC_OVERRIDE_PERM_SECATTR_Msk (0x1UL << MPC_OVERRIDE_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define MPC_OVERRIDE_PERM_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define MPC_OVERRIDE_PERM_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define MPC_OVERRIDE_PERM_SECATTR_Secure (0x1UL) /*!< Override region n is mapped in secure memory address space */ + #define MPC_OVERRIDE_PERM_SECATTR_NonSecure (0x0UL) /*!< Override region n is mapped in non-secure memory address space */ + + +/* MPC_OVERRIDE_PERMMASK: Masks permission setting fields from register OVERRIDE.PERM */ + #define MPC_OVERRIDE_PERMMASK_ResetValue (0x00000000UL) /*!< Reset value of PERMMASK register. */ + +/* READ @Bit 0 : Read mask */ + #define MPC_OVERRIDE_PERMMASK_READ_Pos (0UL) /*!< Position of READ field. */ + #define MPC_OVERRIDE_PERMMASK_READ_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_READ_Pos) /*!< Bit mask of READ field. */ + #define MPC_OVERRIDE_PERMMASK_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define MPC_OVERRIDE_PERMMASK_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define MPC_OVERRIDE_PERMMASK_READ_Masked (0x0UL) /*!< Permission setting READ in OVERRIDE register will not be applied */ + #define MPC_OVERRIDE_PERMMASK_READ_UnMasked (0x1UL) /*!< Permission setting READ in OVERRIDE register will be applied */ + +/* WRITE @Bit 1 : Write mask */ + #define MPC_OVERRIDE_PERMMASK_WRITE_Pos (1UL) /*!< Position of WRITE field. */ + #define MPC_OVERRIDE_PERMMASK_WRITE_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define MPC_OVERRIDE_PERMMASK_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define MPC_OVERRIDE_PERMMASK_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define MPC_OVERRIDE_PERMMASK_WRITE_Masked (0x0UL) /*!< Permission setting WRITE in OVERRIDE register will not be applied */ + #define MPC_OVERRIDE_PERMMASK_WRITE_UnMasked (0x1UL) /*!< Permission setting WRITE in OVERRIDE register will be applied */ + +/* EXECUTE @Bit 2 : Execute mask */ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_Pos (2UL) /*!< Position of EXECUTE field. */ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_Min (0x0UL) /*!< Min enumerator value of EXECUTE field. */ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_Max (0x1UL) /*!< Max enumerator value of EXECUTE field. */ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_Masked (0x0UL) /*!< Permission setting EXECUTE in OVERRIDE register will not be applied*/ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_UnMasked (0x1UL) /*!< Permission setting EXECUTE in OVERRIDE register will be applied */ + +/* SECATTR @Bit 3 : Security mapping mask */ + #define MPC_OVERRIDE_PERMMASK_SECATTR_Pos (3UL) /*!< Position of SECATTR field. */ + #define MPC_OVERRIDE_PERMMASK_SECATTR_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define MPC_OVERRIDE_PERMMASK_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define MPC_OVERRIDE_PERMMASK_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define MPC_OVERRIDE_PERMMASK_SECATTR_Masked (0x0UL) /*!< Permission setting SECATTR in OVERRIDE register will not be applied*/ + #define MPC_OVERRIDE_PERMMASK_SECATTR_UnMasked (0x1UL) /*!< Permission setting SECATTR in OVERRIDE register will be applied */ + + +/* ======================================================= Struct MPC ======================================================== */ +/** + * @brief Memory Privilege Controller + */ + typedef struct { /*!< MPC Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_MEMACCERR; /*!< (@ 0x00000100) Memory Access Error event */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IOM NRF_MPC_MEMACCERR_Type MEMACCERR; /*!< (@ 0x00000400) Memory Access Error status registers */ + __IM uint32_t RESERVED3[254]; + __IOM NRF_MPC_OVERRIDE_Type OVERRIDE[12]; /*!< (@ 0x00000800) Special privilege tables */ + } NRF_MPC_Type; /*!< Size = 2432 (0x980) */ + +/* MPC_EVENTS_MEMACCERR: Memory Access Error event */ + #define MPC_EVENTS_MEMACCERR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_MEMACCERR register. */ + +/* EVENTS_MEMACCERR @Bit 0 : Memory Access Error event */ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Pos (0UL) /*!< Position of EVENTS_MEMACCERR field. */ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Msk (0x1UL << MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Pos) /*!< Bit mask of + EVENTS_MEMACCERR field.*/ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Min (0x0UL) /*!< Min enumerator value of EVENTS_MEMACCERR field. */ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Max (0x1UL) /*!< Max enumerator value of EVENTS_MEMACCERR field. */ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_NotGenerated (0x0UL) /*!< Event not generated */ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Generated (0x1UL) /*!< Event generated */ + + +/* MPC_INTEN: Enable or disable interrupt */ + #define MPC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* MEMACCERR @Bit 0 : Enable or disable interrupt for event MEMACCERR */ + #define MPC_INTEN_MEMACCERR_Pos (0UL) /*!< Position of MEMACCERR field. */ + #define MPC_INTEN_MEMACCERR_Msk (0x1UL << MPC_INTEN_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field. */ + #define MPC_INTEN_MEMACCERR_Min (0x0UL) /*!< Min enumerator value of MEMACCERR field. */ + #define MPC_INTEN_MEMACCERR_Max (0x1UL) /*!< Max enumerator value of MEMACCERR field. */ + #define MPC_INTEN_MEMACCERR_Disabled (0x0UL) /*!< Disable */ + #define MPC_INTEN_MEMACCERR_Enabled (0x1UL) /*!< Enable */ + + +/* MPC_INTENSET: Enable interrupt */ + #define MPC_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* MEMACCERR @Bit 0 : Write '1' to enable interrupt for event MEMACCERR */ + #define MPC_INTENSET_MEMACCERR_Pos (0UL) /*!< Position of MEMACCERR field. */ + #define MPC_INTENSET_MEMACCERR_Msk (0x1UL << MPC_INTENSET_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field. */ + #define MPC_INTENSET_MEMACCERR_Min (0x0UL) /*!< Min enumerator value of MEMACCERR field. */ + #define MPC_INTENSET_MEMACCERR_Max (0x1UL) /*!< Max enumerator value of MEMACCERR field. */ + #define MPC_INTENSET_MEMACCERR_Set (0x1UL) /*!< Enable */ + #define MPC_INTENSET_MEMACCERR_Disabled (0x0UL) /*!< Read: Disabled */ + #define MPC_INTENSET_MEMACCERR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* MPC_INTENCLR: Disable interrupt */ + #define MPC_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* MEMACCERR @Bit 0 : Write '1' to disable interrupt for event MEMACCERR */ + #define MPC_INTENCLR_MEMACCERR_Pos (0UL) /*!< Position of MEMACCERR field. */ + #define MPC_INTENCLR_MEMACCERR_Msk (0x1UL << MPC_INTENCLR_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field. */ + #define MPC_INTENCLR_MEMACCERR_Min (0x0UL) /*!< Min enumerator value of MEMACCERR field. */ + #define MPC_INTENCLR_MEMACCERR_Max (0x1UL) /*!< Max enumerator value of MEMACCERR field. */ + #define MPC_INTENCLR_MEMACCERR_Clear (0x1UL) /*!< Disable */ + #define MPC_INTENCLR_MEMACCERR_Disabled (0x0UL) /*!< Read: Disabled */ + #define MPC_INTENCLR_MEMACCERR_Enabled (0x1UL) /*!< Read: Enabled */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ NFCT ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================= Struct NFCT_FRAMESTATUS ================================================= */ +/** + * @brief FRAMESTATUS [NFCT_FRAMESTATUS] (unspecified) + */ +typedef struct { + __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ +} NRF_NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x004) */ + +/* NFCT_FRAMESTATUS_RX: Result of last incoming frame */ + #define NFCT_FRAMESTATUS_RX_ResetValue (0x00000000UL) /*!< Reset value of RX register. */ + +/* CRCERROR @Bit 0 : No valid end of frame (EoF) detected */ + #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */ + #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ + #define NFCT_FRAMESTATUS_RX_CRCERROR_Min (0x0UL) /*!< Min enumerator value of CRCERROR field. */ + #define NFCT_FRAMESTATUS_RX_CRCERROR_Max (0x1UL) /*!< Max enumerator value of CRCERROR field. */ + #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0x0UL) /*!< Valid CRC detected */ + #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (0x1UL) /*!< CRC received does not match local check */ + +/* PARITYSTATUS @Bit 2 : Parity status of received frame */ + #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */ + #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS + field.*/ + #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Min (0x0UL) /*!< Min enumerator value of PARITYSTATUS field. */ + #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Max (0x1UL) /*!< Max enumerator value of PARITYSTATUS field. */ + #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0x0UL) /*!< Frame received with parity OK */ + #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (0x1UL) /*!< Frame received with parity error */ + +/* OVERRUN @Bit 3 : Overrun detected */ + #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */ + #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ + #define NFCT_FRAMESTATUS_RX_OVERRUN_Min (0x0UL) /*!< Min enumerator value of OVERRUN field. */ + #define NFCT_FRAMESTATUS_RX_OVERRUN_Max (0x1UL) /*!< Max enumerator value of OVERRUN field. */ + #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0x0UL) /*!< No overrun detected */ + #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (0x1UL) /*!< Overrun error */ + + + +/* ===================================================== Struct NFCT_TXD ===================================================== */ +/** + * @brief TXD [NFCT_TXD] (unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ + __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ +} NRF_NFCT_TXD_Type; /*!< Size = 8 (0x008) */ + +/* NFCT_TXD_FRAMECONFIG: Configuration of outgoing frames */ + #define NFCT_TXD_FRAMECONFIG_ResetValue (0x00000017UL) /*!< Reset value of FRAMECONFIG register. */ + +/* PARITY @Bit 0 : Indicates if parity is added to the frame */ + #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ + #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ + #define NFCT_TXD_FRAMECONFIG_PARITY_Min (0x0UL) /*!< Min enumerator value of PARITY field. */ + #define NFCT_TXD_FRAMECONFIG_PARITY_Max (0x1UL) /*!< Max enumerator value of PARITY field. */ + #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0x0UL) /*!< Parity is not added to TX frames */ + #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (0x1UL) /*!< Parity is added to TX frames */ + +/* DISCARDMODE @Bit 1 : Discarding unused bits at start or end of a frame */ + #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */ + #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE + field.*/ + #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Min (0x0UL) /*!< Min enumerator value of DISCARDMODE field. */ + #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Max (0x1UL) /*!< Max enumerator value of DISCARDMODE field. */ + #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0x0UL) /*!< Unused bits are discarded at end of frame (EoF) */ + #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (0x1UL) /*!< Unused bits are discarded at start of frame (SoF) */ + +/* SOF @Bit 2 : Adding SoF or not in TX frames */ + #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ + #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ + #define NFCT_TXD_FRAMECONFIG_SOF_Min (0x0UL) /*!< Min enumerator value of SOF field. */ + #define NFCT_TXD_FRAMECONFIG_SOF_Max (0x1UL) /*!< Max enumerator value of SOF field. */ + #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0x0UL) /*!< SoF symbol not added */ + #define NFCT_TXD_FRAMECONFIG_SOF_SoF (0x1UL) /*!< SoF symbol added */ + +/* CRCMODETX @Bit 4 : CRC mode for outgoing frames */ + #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */ + #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */ + #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Min (0x0UL) /*!< Min enumerator value of CRCMODETX field. */ + #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Max (0x1UL) /*!< Max enumerator value of CRCMODETX field. */ + #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0x0UL) /*!< CRC is not added to the frame */ + #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (0x1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM + that is used in the frame*/ + + +/* NFCT_TXD_AMOUNT: Size of outgoing frame */ + #define NFCT_TXD_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* TXDATABITS @Bits 0..2 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding + parity bit). */ + + #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */ + #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */ + #define NFCT_TXD_AMOUNT_TXDATABITS_Min (0x0UL) /*!< Min value of TXDATABITS field. */ + #define NFCT_TXD_AMOUNT_TXDATABITS_Max (0x7UL) /*!< Max size of TXDATABITS field. */ + +/* TXDATABYTES @Bits 3..11 : Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. */ + #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */ + #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */ + #define NFCT_TXD_AMOUNT_TXDATABYTES_Min (0x000UL) /*!< Min value of TXDATABYTES field. */ + #define NFCT_TXD_AMOUNT_TXDATABYTES_Max (0x101UL) /*!< Max size of TXDATABYTES field. */ + + + +/* ===================================================== Struct NFCT_RXD ===================================================== */ +/** + * @brief RXD [NFCT_RXD] (unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ +} NRF_NFCT_RXD_Type; /*!< Size = 8 (0x008) */ + +/* NFCT_RXD_FRAMECONFIG: Configuration of incoming frames */ + #define NFCT_RXD_FRAMECONFIG_ResetValue (0x00000015UL) /*!< Reset value of FRAMECONFIG register. */ + +/* PARITY @Bit 0 : Indicates if parity expected in RX frame */ + #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ + #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ + #define NFCT_RXD_FRAMECONFIG_PARITY_Min (0x0UL) /*!< Min enumerator value of PARITY field. */ + #define NFCT_RXD_FRAMECONFIG_PARITY_Max (0x1UL) /*!< Max enumerator value of PARITY field. */ + #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0x0UL) /*!< Parity is not expected in RX frames */ + #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (0x1UL) /*!< Parity is expected in RX frames */ + +/* SOF @Bit 2 : SoF expected or not in RX frames */ + #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ + #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ + #define NFCT_RXD_FRAMECONFIG_SOF_Min (0x0UL) /*!< Min enumerator value of SOF field. */ + #define NFCT_RXD_FRAMECONFIG_SOF_Max (0x1UL) /*!< Max enumerator value of SOF field. */ + #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0x0UL) /*!< SoF symbol is not expected in RX frames */ + #define NFCT_RXD_FRAMECONFIG_SOF_SoF (0x1UL) /*!< SoF symbol is expected in RX frames */ + +/* CRCMODERX @Bit 4 : CRC mode for incoming frames */ + #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */ + #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */ + #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Min (0x0UL) /*!< Min enumerator value of CRCMODERX field. */ + #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Max (0x1UL) /*!< Max enumerator value of CRCMODERX field. */ + #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0x0UL) /*!< CRC is not expected in RX frames */ + #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (0x1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS + updated*/ + + +/* NFCT_RXD_AMOUNT: Size of last incoming frame */ + #define NFCT_RXD_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* RXDATABITS @Bits 0..2 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and + SoF/EoF framing). */ + + #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */ + #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */ + +/* RXDATABYTES @Bits 3..11 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF + framing) */ + + #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */ + #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */ + + + +/* =================================================== Struct NFCT_NFCID1 ==================================================== */ +/** + * @brief NFCID1 [NFCT_NFCID1] (unspecified) + */ +typedef struct { + __IOM uint32_t LAST; /*!< (@ 0x00000000) Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IOM uint32_t SECONDLAST; /*!< (@ 0x00000004) Second last NFCID1 part (7 or 10 bytes ID) */ + __IOM uint32_t THIRDLAST; /*!< (@ 0x00000008) Third last NFCID1 part (10 bytes ID) */ +} NRF_NFCT_NFCID1_Type; /*!< Size = 12 (0x00C) */ + +/* NFCT_NFCID1_LAST: Last NFCID1 part (4, 7 or 10 bytes ID) */ + #define NFCT_NFCID1_LAST_ResetValue (0x00006363UL) /*!< Reset value of LAST register. */ + +/* Z @Bits 0..7 : NFCID1 byte Z (very last byte sent) */ + #define NFCT_NFCID1_LAST_Z_Pos (0UL) /*!< Position of Z field. */ + #define NFCT_NFCID1_LAST_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_Z_Pos) /*!< Bit mask of Z field. */ + +/* Y @Bits 8..15 : NFCID1 byte Y */ + #define NFCT_NFCID1_LAST_Y_Pos (8UL) /*!< Position of Y field. */ + #define NFCT_NFCID1_LAST_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_Y_Pos) /*!< Bit mask of Y field. */ + +/* X @Bits 16..23 : NFCID1 byte X */ + #define NFCT_NFCID1_LAST_X_Pos (16UL) /*!< Position of X field. */ + #define NFCT_NFCID1_LAST_X_Msk (0xFFUL << NFCT_NFCID1_LAST_X_Pos) /*!< Bit mask of X field. */ + +/* W @Bits 24..31 : NFCID1 byte W */ + #define NFCT_NFCID1_LAST_W_Pos (24UL) /*!< Position of W field. */ + #define NFCT_NFCID1_LAST_W_Msk (0xFFUL << NFCT_NFCID1_LAST_W_Pos) /*!< Bit mask of W field. */ + + +/* NFCT_NFCID1_SECONDLAST: Second last NFCID1 part (7 or 10 bytes ID) */ + #define NFCT_NFCID1_SECONDLAST_ResetValue (0x00000000UL) /*!< Reset value of SECONDLAST register. */ + +/* V @Bits 0..7 : NFCID1 byte V */ + #define NFCT_NFCID1_SECONDLAST_V_Pos (0UL) /*!< Position of V field. */ + #define NFCT_NFCID1_SECONDLAST_V_Msk (0xFFUL << NFCT_NFCID1_SECONDLAST_V_Pos) /*!< Bit mask of V field. */ + +/* U @Bits 8..15 : NFCID1 byte U */ + #define NFCT_NFCID1_SECONDLAST_U_Pos (8UL) /*!< Position of U field. */ + #define NFCT_NFCID1_SECONDLAST_U_Msk (0xFFUL << NFCT_NFCID1_SECONDLAST_U_Pos) /*!< Bit mask of U field. */ + +/* T @Bits 16..23 : NFCID1 byte T */ + #define NFCT_NFCID1_SECONDLAST_T_Pos (16UL) /*!< Position of T field. */ + #define NFCT_NFCID1_SECONDLAST_T_Msk (0xFFUL << NFCT_NFCID1_SECONDLAST_T_Pos) /*!< Bit mask of T field. */ + + +/* NFCT_NFCID1_THIRDLAST: Third last NFCID1 part (10 bytes ID) */ + #define NFCT_NFCID1_THIRDLAST_ResetValue (0x00000000UL) /*!< Reset value of THIRDLAST register. */ + +/* S @Bits 0..7 : NFCID1 byte S */ + #define NFCT_NFCID1_THIRDLAST_S_Pos (0UL) /*!< Position of S field. */ + #define NFCT_NFCID1_THIRDLAST_S_Msk (0xFFUL << NFCT_NFCID1_THIRDLAST_S_Pos) /*!< Bit mask of S field. */ + +/* R @Bits 8..15 : NFCID1 byte R */ + #define NFCT_NFCID1_THIRDLAST_R_Pos (8UL) /*!< Position of R field. */ + #define NFCT_NFCID1_THIRDLAST_R_Msk (0xFFUL << NFCT_NFCID1_THIRDLAST_R_Pos) /*!< Bit mask of R field. */ + +/* Q @Bits 16..23 : NFCID1 byte Q */ + #define NFCT_NFCID1_THIRDLAST_Q_Pos (16UL) /*!< Position of Q field. */ + #define NFCT_NFCID1_THIRDLAST_Q_Msk (0xFFUL << NFCT_NFCID1_THIRDLAST_Q_Pos) /*!< Bit mask of Q field. */ + + +/* ======================================================= Struct NFCT ======================================================= */ +/** + * @brief NFC-A compatible radio NFC-A compatible radio + */ + typedef struct { /*!< NFCT Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing + frames, change state to activated*/ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ + __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to sense + mode*/ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change state + to transmit*/ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x00000010) Stops an issued transmission of a frame */ + __IM uint32_t RESERVED[2]; + __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ + __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ + __IM uint32_t RESERVED2[21]; + __IOM uint32_t SUBSCRIBE_ACTIVATE; /*!< (@ 0x00000080) Subscribe configuration for task ACTIVATE */ + __IOM uint32_t SUBSCRIBE_DISABLE; /*!< (@ 0x00000084) Subscribe configuration for task DISABLE */ + __IOM uint32_t SUBSCRIBE_SENSE; /*!< (@ 0x00000088) Subscribe configuration for task SENSE */ + __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x0000008C) Subscribe configuration for task STARTTX */ + __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x00000090) Subscribe configuration for task STOPTX */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t SUBSCRIBE_ENABLERXDATA; /*!< (@ 0x0000009C) Subscribe configuration for task ENABLERXDATA */ + __IM uint32_t RESERVED4; + __IOM uint32_t SUBSCRIBE_GOIDLE; /*!< (@ 0x000000A4) Subscribe configuration for task GOIDLE */ + __IOM uint32_t SUBSCRIBE_GOSLEEP; /*!< (@ 0x000000A8) Subscribe configuration for task GOSLEEP */ + __IM uint32_t RESERVED5[21]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send + frames*/ + __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ + __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ + __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted + frame*/ + __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air symbol of + a frame*/ + __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received frame */ + __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) and + transferred to RAM, and EasyDMA has ended accessing the + RX buffer*/ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register contains + details on the source of the error.*/ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX + register contains details on the source of the error.*/ + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) in Data + RAM full.*/ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA has + ended accessing the TX buffer*/ + __IM uint32_t RESERVED7; + __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ + __IM uint32_t RESERVED8[3]; + __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ + __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ + __IM uint32_t RESERVED9[11]; + __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ + __IOM uint32_t PUBLISH_FIELDDETECTED; /*!< (@ 0x00000184) Publish configuration for event FIELDDETECTED */ + __IOM uint32_t PUBLISH_FIELDLOST; /*!< (@ 0x00000188) Publish configuration for event FIELDLOST */ + __IOM uint32_t PUBLISH_TXFRAMESTART; /*!< (@ 0x0000018C) Publish configuration for event TXFRAMESTART */ + __IOM uint32_t PUBLISH_TXFRAMEEND; /*!< (@ 0x00000190) Publish configuration for event TXFRAMEEND */ + __IOM uint32_t PUBLISH_RXFRAMESTART; /*!< (@ 0x00000194) Publish configuration for event RXFRAMESTART */ + __IOM uint32_t PUBLISH_RXFRAMEEND; /*!< (@ 0x00000198) Publish configuration for event RXFRAMEEND */ + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x0000019C) Publish configuration for event ERROR */ + __IM uint32_t RESERVED10[2]; + __IOM uint32_t PUBLISH_RXERROR; /*!< (@ 0x000001A8) Publish configuration for event RXERROR */ + __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x000001AC) Publish configuration for event ENDRX */ + __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001B0) Publish configuration for event ENDTX */ + __IM uint32_t RESERVED11; + __IOM uint32_t PUBLISH_AUTOCOLRESSTARTED; /*!< (@ 0x000001B8) Publish configuration for event AUTOCOLRESSTARTED */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t PUBLISH_COLLISION; /*!< (@ 0x000001C8) Publish configuration for event COLLISION */ + __IOM uint32_t PUBLISH_SELECTED; /*!< (@ 0x000001CC) Publish configuration for event SELECTED */ + __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001D0) Publish configuration for event STARTED */ + __IM uint32_t RESERVED13[11]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED14[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED15[62]; + __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ + __IM uint32_t RESERVED16; + __IOM NRF_NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) (unspecified) */ + __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) Current operating state of NFC tag */ + __IM uint32_t RESERVED17[3]; + __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ + __IM uint32_t RESERVED18[6]; + __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ + __IM uint32_t RESERVED19[49]; + __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ + __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ + __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in Data + RAM*/ + __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD data + storage each*/ + __IOM NRF_NFCT_TXD_Type TXD; /*!< (@ 0x00000518) (unspecified) */ + __IOM NRF_NFCT_RXD_Type RXD; /*!< (@ 0x00000520) (unspecified) */ + __IM uint32_t RESERVED20; + __IOM uint32_t MODULATIONCTRL; /*!< (@ 0x0000052C) Enables the modulation output to a GPIO pin which can + be connected to a second external antenna.*/ + __IM uint32_t RESERVED21[2]; + __IOM uint32_t MODULATIONPSEL; /*!< (@ 0x00000538) Pin select for Modulation control */ + __IM uint32_t RESERVED22[5]; + __IOM uint32_t MODE; /*!< (@ 0x00000550) Configure EasyDMA mode */ + __IM uint32_t RESERVED23[15]; + __IOM NRF_NFCT_NFCID1_Type NFCID1; /*!< (@ 0x00000590) (unspecified) */ + __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. This + setting must be done before the NFCT peripheral is + activated.*/ + __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ + __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ + __IM uint32_t RESERVED24[75]; + __IOM uint32_t PADCONFIG; /*!< (@ 0x000006D4) NFC pad configuration */ + } NRF_NFCT_Type; /*!< Size = 1752 (0x6D8) */ + +/* NFCT_TASKS_ACTIVATE: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ + #define NFCT_TASKS_ACTIVATE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ACTIVATE register. */ + +/* TASKS_ACTIVATE @Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ + #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ + #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of + TASKS_ACTIVATE field.*/ + #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Min (0x1UL) /*!< Min enumerator value of TASKS_ACTIVATE field. */ + #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Max (0x1UL) /*!< Max enumerator value of TASKS_ACTIVATE field. */ + #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (0x1UL) /*!< Trigger task */ + + +/* NFCT_TASKS_DISABLE: Disable NFCT peripheral */ + #define NFCT_TASKS_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_DISABLE register. */ + +/* TASKS_DISABLE @Bit 0 : Disable NFCT peripheral */ + #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ + #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE + field.*/ + #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Min (0x1UL) /*!< Min enumerator value of TASKS_DISABLE field. */ + #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Max (0x1UL) /*!< Max enumerator value of TASKS_DISABLE field. */ + #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (0x1UL) /*!< Trigger task */ + + +/* NFCT_TASKS_SENSE: Enable NFC sense field mode, change state to sense mode */ + #define NFCT_TASKS_SENSE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SENSE register. */ + +/* TASKS_SENSE @Bit 0 : Enable NFC sense field mode, change state to sense mode */ + #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */ + #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */ + #define NFCT_TASKS_SENSE_TASKS_SENSE_Min (0x1UL) /*!< Min enumerator value of TASKS_SENSE field. */ + #define NFCT_TASKS_SENSE_TASKS_SENSE_Max (0x1UL) /*!< Max enumerator value of TASKS_SENSE field. */ + #define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (0x1UL) /*!< Trigger task */ + + +/* NFCT_TASKS_STARTTX: Start transmission of an outgoing frame, change state to transmit */ + #define NFCT_TASKS_STARTTX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STARTTX register. */ + +/* TASKS_STARTTX @Bit 0 : Start transmission of an outgoing frame, change state to transmit */ + #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ + #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX + field.*/ + #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Min (0x1UL) /*!< Min enumerator value of TASKS_STARTTX field. */ + #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Max (0x1UL) /*!< Max enumerator value of TASKS_STARTTX field. */ + #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */ + + +/* NFCT_TASKS_STOPTX: Stops an issued transmission of a frame */ + #define NFCT_TASKS_STOPTX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOPTX register. */ + +/* TASKS_STOPTX @Bit 0 : Stops an issued transmission of a frame */ + #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ + #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << NFCT_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field.*/ + #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Min (0x1UL) /*!< Min enumerator value of TASKS_STOPTX field. */ + #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Max (0x1UL) /*!< Max enumerator value of TASKS_STOPTX field. */ + #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Trigger (0x1UL) /*!< Trigger task */ + + +/* NFCT_TASKS_ENABLERXDATA: Initializes the EasyDMA for receive. */ + #define NFCT_TASKS_ENABLERXDATA_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ENABLERXDATA register. */ + +/* TASKS_ENABLERXDATA @Bit 0 : Initializes the EasyDMA for receive. */ + #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */ + #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask + of TASKS_ENABLERXDATA field.*/ + #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Min (0x1UL) /*!< Min enumerator value of TASKS_ENABLERXDATA field. */ + #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Max (0x1UL) /*!< Max enumerator value of TASKS_ENABLERXDATA field. */ + #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (0x1UL) /*!< Trigger task */ + + +/* NFCT_TASKS_GOIDLE: Force state machine to IDLE state */ + #define NFCT_TASKS_GOIDLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_GOIDLE register. */ + +/* TASKS_GOIDLE @Bit 0 : Force state machine to IDLE state */ + #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */ + #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field.*/ + #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Min (0x1UL) /*!< Min enumerator value of TASKS_GOIDLE field. */ + #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Max (0x1UL) /*!< Max enumerator value of TASKS_GOIDLE field. */ + #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (0x1UL) /*!< Trigger task */ + + +/* NFCT_TASKS_GOSLEEP: Force state machine to SLEEP_A state */ + #define NFCT_TASKS_GOSLEEP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_GOSLEEP register. */ + +/* TASKS_GOSLEEP @Bit 0 : Force state machine to SLEEP_A state */ + #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */ + #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP + field.*/ + #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Min (0x1UL) /*!< Min enumerator value of TASKS_GOSLEEP field. */ + #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Max (0x1UL) /*!< Max enumerator value of TASKS_GOSLEEP field. */ + #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (0x1UL) /*!< Trigger task */ + + +/* NFCT_SUBSCRIBE_ACTIVATE: Subscribe configuration for task ACTIVATE */ + #define NFCT_SUBSCRIBE_ACTIVATE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ACTIVATE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ACTIVATE will subscribe to */ + #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_SUBSCRIBE_ACTIVATE_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_SUBSCRIBE_ACTIVATE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ACTIVATE_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_SUBSCRIBE_ACTIVATE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_ACTIVATE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_ACTIVATE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define NFCT_SUBSCRIBE_ACTIVATE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* NFCT_SUBSCRIBE_DISABLE: Subscribe configuration for task DISABLE */ + #define NFCT_SUBSCRIBE_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_DISABLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLE will subscribe to */ + #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_SUBSCRIBE_DISABLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_SUBSCRIBE_DISABLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_DISABLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_DISABLE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define NFCT_SUBSCRIBE_DISABLE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* NFCT_SUBSCRIBE_SENSE: Subscribe configuration for task SENSE */ + #define NFCT_SUBSCRIBE_SENSE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SENSE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SENSE will subscribe to */ + #define NFCT_SUBSCRIBE_SENSE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_SUBSCRIBE_SENSE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_SENSE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_SUBSCRIBE_SENSE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_SUBSCRIBE_SENSE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_SUBSCRIBE_SENSE_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_SUBSCRIBE_SENSE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_SENSE_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_SUBSCRIBE_SENSE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_SENSE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_SENSE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define NFCT_SUBSCRIBE_SENSE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* NFCT_SUBSCRIBE_STARTTX: Subscribe configuration for task STARTTX */ + #define NFCT_SUBSCRIBE_STARTTX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STARTTX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STARTTX will subscribe to */ + #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << NFCT_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_SUBSCRIBE_STARTTX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_STARTTX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define NFCT_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* NFCT_SUBSCRIBE_STOPTX: Subscribe configuration for task STOPTX */ + #define NFCT_SUBSCRIBE_STOPTX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOPTX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOPTX will subscribe to */ + #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << NFCT_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_SUBSCRIBE_STOPTX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_STOPTX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_STOPTX_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define NFCT_SUBSCRIBE_STOPTX_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* NFCT_SUBSCRIBE_ENABLERXDATA: Subscribe configuration for task ENABLERXDATA */ + #define NFCT_SUBSCRIBE_ENABLERXDATA_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ENABLERXDATA register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ENABLERXDATA will subscribe to */ + #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* NFCT_SUBSCRIBE_GOIDLE: Subscribe configuration for task GOIDLE */ + #define NFCT_SUBSCRIBE_GOIDLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_GOIDLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task GOIDLE will subscribe to */ + #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_SUBSCRIBE_GOIDLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_SUBSCRIBE_GOIDLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOIDLE_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_SUBSCRIBE_GOIDLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_GOIDLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_GOIDLE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define NFCT_SUBSCRIBE_GOIDLE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* NFCT_SUBSCRIBE_GOSLEEP: Subscribe configuration for task GOSLEEP */ + #define NFCT_SUBSCRIBE_GOSLEEP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_GOSLEEP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task GOSLEEP will subscribe to */ + #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_SUBSCRIBE_GOSLEEP_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_SUBSCRIBE_GOSLEEP_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOSLEEP_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_SUBSCRIBE_GOSLEEP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_GOSLEEP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_SUBSCRIBE_GOSLEEP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define NFCT_SUBSCRIBE_GOSLEEP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* NFCT_EVENTS_READY: The NFCT peripheral is ready to receive and send frames */ + #define NFCT_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register. */ + +/* EVENTS_READY @Bit 0 : The NFCT peripheral is ready to receive and send frames */ + #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ + #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field.*/ + #define NFCT_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field. */ + #define NFCT_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field. */ + #define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_FIELDDETECTED: Remote NFC field detected */ + #define NFCT_EVENTS_FIELDDETECTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FIELDDETECTED register. */ + +/* EVENTS_FIELDDETECTED @Bit 0 : Remote NFC field detected */ + #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */ + #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< + Bit mask of EVENTS_FIELDDETECTED field.*/ + #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_FIELDDETECTED field. */ + #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_FIELDDETECTED field. */ + #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_FIELDLOST: Remote NFC field lost */ + #define NFCT_EVENTS_FIELDLOST_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FIELDLOST register. */ + +/* EVENTS_FIELDLOST @Bit 0 : Remote NFC field lost */ + #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */ + #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of + EVENTS_FIELDLOST field.*/ + #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Min (0x0UL) /*!< Min enumerator value of EVENTS_FIELDLOST field. */ + #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Max (0x1UL) /*!< Max enumerator value of EVENTS_FIELDLOST field. */ + #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_TXFRAMESTART: Marks the start of the first symbol of a transmitted frame */ + #define NFCT_EVENTS_TXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXFRAMESTART register. */ + +/* EVENTS_TXFRAMESTART @Bit 0 : Marks the start of the first symbol of a transmitted frame */ + #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */ + #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit + mask of EVENTS_TXFRAMESTART field.*/ + #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXFRAMESTART field. */ + #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXFRAMESTART field. */ + #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_TXFRAMEEND: Marks the end of the last transmitted on-air symbol of a frame */ + #define NFCT_EVENTS_TXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXFRAMEEND register. */ + +/* EVENTS_TXFRAMEEND @Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */ + #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */ + #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of + EVENTS_TXFRAMEEND field.*/ + #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXFRAMEEND field. */ + #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXFRAMEEND field. */ + #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_RXFRAMESTART: Marks the end of the first symbol of a received frame */ + #define NFCT_EVENTS_RXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXFRAMESTART register. */ + +/* EVENTS_RXFRAMESTART @Bit 0 : Marks the end of the first symbol of a received frame */ + #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */ + #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit + mask of EVENTS_RXFRAMESTART field.*/ + #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXFRAMESTART field. */ + #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXFRAMESTART field. */ + #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_RXFRAMEEND: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing + the RX buffer */ + + #define NFCT_EVENTS_RXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXFRAMEEND register. */ + +/* EVENTS_RXFRAMEEND @Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended + accessing the RX buffer */ + + #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */ + #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of + EVENTS_RXFRAMEEND field.*/ + #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXFRAMEEND field. */ + #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXFRAMEEND field. */ + #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_ERROR: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ + #define NFCT_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ + #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.*/ + #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_RXERROR: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ + #define NFCT_EVENTS_RXERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXERROR register. */ + +/* EVENTS_RXERROR @Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + */ + + #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */ + #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of + EVENTS_RXERROR field.*/ + #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXERROR field. */ + #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXERROR field. */ + #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_ENDRX: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ + #define NFCT_EVENTS_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ENDRX register. */ + +/* EVENTS_ENDRX @Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ + #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ + #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field.*/ + #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ENDRX field. */ + #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ENDRX field. */ + #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_ENDTX: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ + #define NFCT_EVENTS_ENDTX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ENDTX register. */ + +/* EVENTS_ENDTX @Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ + #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ + #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field.*/ + #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ENDTX field. */ + #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ENDTX field. */ + #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_AUTOCOLRESSTARTED: Auto collision resolution process has started */ + #define NFCT_EVENTS_AUTOCOLRESSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_AUTOCOLRESSTARTED register. */ + +/* EVENTS_AUTOCOLRESSTARTED @Bit 0 : Auto collision resolution process has started */ + #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */ + #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) + /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field.*/ + #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Min (0x0UL) /*!< Min enumerator value of + EVENTS_AUTOCOLRESSTARTED field.*/ + #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Max (0x1UL) /*!< Max enumerator value of + EVENTS_AUTOCOLRESSTARTED field.*/ + #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_COLLISION: NFC auto collision resolution error reported. */ + #define NFCT_EVENTS_COLLISION_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COLLISION register. */ + +/* EVENTS_COLLISION @Bit 0 : NFC auto collision resolution error reported. */ + #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */ + #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of + EVENTS_COLLISION field.*/ + #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Min (0x0UL) /*!< Min enumerator value of EVENTS_COLLISION field. */ + #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Max (0x1UL) /*!< Max enumerator value of EVENTS_COLLISION field. */ + #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_SELECTED: NFC auto collision resolution successfully completed */ + #define NFCT_EVENTS_SELECTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SELECTED register. */ + +/* EVENTS_SELECTED @Bit 0 : NFC auto collision resolution successfully completed */ + #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */ + #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of + EVENTS_SELECTED field.*/ + #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_SELECTED field. */ + #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_SELECTED field. */ + #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_EVENTS_STARTED: EasyDMA is ready to receive or send frames. */ + #define NFCT_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register. */ + +/* EVENTS_STARTED @Bit 0 : EasyDMA is ready to receive or send frames. */ + #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ + #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of + EVENTS_STARTED field.*/ + #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field. */ + #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field. */ + #define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ + + +/* NFCT_PUBLISH_READY: Publish configuration for event READY */ + #define NFCT_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define NFCT_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_READY_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_READY_EN_Msk (0x1UL << NFCT_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_FIELDDETECTED: Publish configuration for event FIELDDETECTED */ + #define NFCT_PUBLISH_FIELDDETECTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FIELDDETECTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event FIELDDETECTED will publish to */ + #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_FIELDDETECTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_FIELDDETECTED_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDDETECTED_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_FIELDDETECTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_FIELDDETECTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_FIELDDETECTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_FIELDDETECTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_FIELDLOST: Publish configuration for event FIELDLOST */ + #define NFCT_PUBLISH_FIELDLOST_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FIELDLOST register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event FIELDLOST will publish to */ + #define NFCT_PUBLISH_FIELDLOST_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_FIELDLOST_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDLOST_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_FIELDLOST_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_FIELDLOST_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_FIELDLOST_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_FIELDLOST_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDLOST_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_FIELDLOST_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_FIELDLOST_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_FIELDLOST_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_FIELDLOST_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_TXFRAMESTART: Publish configuration for event TXFRAMESTART */ + #define NFCT_PUBLISH_TXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXFRAMESTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TXFRAMESTART will publish to */ + #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_TXFRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_TXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMESTART_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_TXFRAMESTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_TXFRAMESTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_TXFRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_TXFRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_TXFRAMEEND: Publish configuration for event TXFRAMEEND */ + #define NFCT_PUBLISH_TXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXFRAMEEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TXFRAMEEND will publish to */ + #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_TXFRAMEEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_TXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMEEND_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_TXFRAMEEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_TXFRAMEEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_TXFRAMEEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_TXFRAMEEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_RXFRAMESTART: Publish configuration for event RXFRAMESTART */ + #define NFCT_PUBLISH_RXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXFRAMESTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXFRAMESTART will publish to */ + #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_RXFRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_RXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMESTART_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_RXFRAMESTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_RXFRAMESTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_RXFRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_RXFRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_RXFRAMEEND: Publish configuration for event RXFRAMEEND */ + #define NFCT_PUBLISH_RXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXFRAMEEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXFRAMEEND will publish to */ + #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_RXFRAMEEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_RXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMEEND_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_RXFRAMEEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_RXFRAMEEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_RXFRAMEEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_RXFRAMEEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define NFCT_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define NFCT_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_ERROR_EN_Msk (0x1UL << NFCT_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_RXERROR: Publish configuration for event RXERROR */ + #define NFCT_PUBLISH_RXERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXERROR will publish to */ + #define NFCT_PUBLISH_RXERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_RXERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_RXERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_RXERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_RXERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_RXERROR_EN_Msk (0x1UL << NFCT_PUBLISH_RXERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_RXERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_RXERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_RXERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_RXERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_ENDRX: Publish configuration for event ENDRX */ + #define NFCT_PUBLISH_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ENDRX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ENDRX will publish to */ + #define NFCT_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_ENDRX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_ENDRX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_ENDRX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_ENDRX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_ENDRX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_ENDTX: Publish configuration for event ENDTX */ + #define NFCT_PUBLISH_ENDTX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ENDTX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ENDTX will publish to */ + #define NFCT_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_ENDTX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_ENDTX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_ENDTX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_ENDTX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_ENDTX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_ENDTX_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_ENDTX_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_AUTOCOLRESSTARTED: Publish configuration for event AUTOCOLRESSTARTED */ + #define NFCT_PUBLISH_AUTOCOLRESSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_AUTOCOLRESSTARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event AUTOCOLRESSTARTED will publish to */ + #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Msk (0x1UL << NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_COLLISION: Publish configuration for event COLLISION */ + #define NFCT_PUBLISH_COLLISION_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COLLISION register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event COLLISION will publish to */ + #define NFCT_PUBLISH_COLLISION_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_COLLISION_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_COLLISION_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_COLLISION_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_COLLISION_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_COLLISION_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_COLLISION_EN_Msk (0x1UL << NFCT_PUBLISH_COLLISION_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_COLLISION_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_COLLISION_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_COLLISION_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_COLLISION_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_SELECTED: Publish configuration for event SELECTED */ + #define NFCT_PUBLISH_SELECTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SELECTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SELECTED will publish to */ + #define NFCT_PUBLISH_SELECTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_SELECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_SELECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_SELECTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_SELECTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_SELECTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_SELECTED_EN_Msk (0x1UL << NFCT_PUBLISH_SELECTED_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_SELECTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_SELECTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_SELECTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_SELECTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_PUBLISH_STARTED: Publish configuration for event STARTED */ + #define NFCT_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */ + #define NFCT_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define NFCT_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define NFCT_PUBLISH_STARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define NFCT_PUBLISH_STARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define NFCT_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define NFCT_PUBLISH_STARTED_EN_Msk (0x1UL << NFCT_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define NFCT_PUBLISH_STARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define NFCT_PUBLISH_STARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define NFCT_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define NFCT_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* NFCT_SHORTS: Shortcuts between local events and tasks */ + #define NFCT_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* FIELDDETECTED_ACTIVATE @Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */ + #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ + #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of + FIELDDETECTED_ACTIVATE field.*/ + #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Min (0x0UL) /*!< Min enumerator value of FIELDDETECTED_ACTIVATE field. */ + #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Max (0x1UL) /*!< Max enumerator value of FIELDDETECTED_ACTIVATE field. */ + #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0x0UL) /*!< Disable shortcut */ + #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* FIELDLOST_SENSE @Bit 1 : Shortcut between event FIELDLOST and task SENSE */ + #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ + #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ + #define NFCT_SHORTS_FIELDLOST_SENSE_Min (0x0UL) /*!< Min enumerator value of FIELDLOST_SENSE field. */ + #define NFCT_SHORTS_FIELDLOST_SENSE_Max (0x1UL) /*!< Max enumerator value of FIELDLOST_SENSE field. */ + #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0x0UL) /*!< Disable shortcut */ + #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* TXFRAMEEND_ENABLERXDATA @Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */ + #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */ + #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of + TXFRAMEEND_ENABLERXDATA field.*/ + #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Min (0x0UL) /*!< Min enumerator value of TXFRAMEEND_ENABLERXDATA field. */ + #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Max (0x1UL) /*!< Max enumerator value of TXFRAMEEND_ENABLERXDATA field. */ + #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0x0UL) /*!< Disable shortcut */ + #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* NFCT_INTEN: Enable or disable interrupt */ + #define NFCT_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* READY @Bit 0 : Enable or disable interrupt for event READY */ + #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ + #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ + #define NFCT_INTEN_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define NFCT_INTEN_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define NFCT_INTEN_READY_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_READY_Enabled (0x1UL) /*!< Enable */ + +/* FIELDDETECTED @Bit 1 : Enable or disable interrupt for event FIELDDETECTED */ + #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ + #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ + #define NFCT_INTEN_FIELDDETECTED_Min (0x0UL) /*!< Min enumerator value of FIELDDETECTED field. */ + #define NFCT_INTEN_FIELDDETECTED_Max (0x1UL) /*!< Max enumerator value of FIELDDETECTED field. */ + #define NFCT_INTEN_FIELDDETECTED_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_FIELDDETECTED_Enabled (0x1UL) /*!< Enable */ + +/* FIELDLOST @Bit 2 : Enable or disable interrupt for event FIELDLOST */ + #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ + #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ + #define NFCT_INTEN_FIELDLOST_Min (0x0UL) /*!< Min enumerator value of FIELDLOST field. */ + #define NFCT_INTEN_FIELDLOST_Max (0x1UL) /*!< Max enumerator value of FIELDLOST field. */ + #define NFCT_INTEN_FIELDLOST_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_FIELDLOST_Enabled (0x1UL) /*!< Enable */ + +/* TXFRAMESTART @Bit 3 : Enable or disable interrupt for event TXFRAMESTART */ + #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ + #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ + #define NFCT_INTEN_TXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of TXFRAMESTART field. */ + #define NFCT_INTEN_TXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of TXFRAMESTART field. */ + #define NFCT_INTEN_TXFRAMESTART_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_TXFRAMESTART_Enabled (0x1UL) /*!< Enable */ + +/* TXFRAMEEND @Bit 4 : Enable or disable interrupt for event TXFRAMEEND */ + #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ + #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ + #define NFCT_INTEN_TXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of TXFRAMEEND field. */ + #define NFCT_INTEN_TXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of TXFRAMEEND field. */ + #define NFCT_INTEN_TXFRAMEEND_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_TXFRAMEEND_Enabled (0x1UL) /*!< Enable */ + +/* RXFRAMESTART @Bit 5 : Enable or disable interrupt for event RXFRAMESTART */ + #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ + #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ + #define NFCT_INTEN_RXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of RXFRAMESTART field. */ + #define NFCT_INTEN_RXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of RXFRAMESTART field. */ + #define NFCT_INTEN_RXFRAMESTART_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_RXFRAMESTART_Enabled (0x1UL) /*!< Enable */ + +/* RXFRAMEEND @Bit 6 : Enable or disable interrupt for event RXFRAMEEND */ + #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ + #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ + #define NFCT_INTEN_RXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of RXFRAMEEND field. */ + #define NFCT_INTEN_RXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of RXFRAMEEND field. */ + #define NFCT_INTEN_RXFRAMEEND_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_RXFRAMEEND_Enabled (0x1UL) /*!< Enable */ + +/* ERROR @Bit 7 : Enable or disable interrupt for event ERROR */ + #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ + #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define NFCT_INTEN_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define NFCT_INTEN_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define NFCT_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ + +/* RXERROR @Bit 10 : Enable or disable interrupt for event RXERROR */ + #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ + #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ + #define NFCT_INTEN_RXERROR_Min (0x0UL) /*!< Min enumerator value of RXERROR field. */ + #define NFCT_INTEN_RXERROR_Max (0x1UL) /*!< Max enumerator value of RXERROR field. */ + #define NFCT_INTEN_RXERROR_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_RXERROR_Enabled (0x1UL) /*!< Enable */ + +/* ENDRX @Bit 11 : Enable or disable interrupt for event ENDRX */ + #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ + #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ + #define NFCT_INTEN_ENDRX_Min (0x0UL) /*!< Min enumerator value of ENDRX field. */ + #define NFCT_INTEN_ENDRX_Max (0x1UL) /*!< Max enumerator value of ENDRX field. */ + #define NFCT_INTEN_ENDRX_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_ENDRX_Enabled (0x1UL) /*!< Enable */ + +/* ENDTX @Bit 12 : Enable or disable interrupt for event ENDTX */ + #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ + #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ + #define NFCT_INTEN_ENDTX_Min (0x0UL) /*!< Min enumerator value of ENDTX field. */ + #define NFCT_INTEN_ENDTX_Max (0x1UL) /*!< Max enumerator value of ENDTX field. */ + #define NFCT_INTEN_ENDTX_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_ENDTX_Enabled (0x1UL) /*!< Enable */ + +/* AUTOCOLRESSTARTED @Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */ + #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ + #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED + field.*/ + #define NFCT_INTEN_AUTOCOLRESSTARTED_Min (0x0UL) /*!< Min enumerator value of AUTOCOLRESSTARTED field. */ + #define NFCT_INTEN_AUTOCOLRESSTARTED_Max (0x1UL) /*!< Max enumerator value of AUTOCOLRESSTARTED field. */ + #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Enable */ + +/* COLLISION @Bit 18 : Enable or disable interrupt for event COLLISION */ + #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ + #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ + #define NFCT_INTEN_COLLISION_Min (0x0UL) /*!< Min enumerator value of COLLISION field. */ + #define NFCT_INTEN_COLLISION_Max (0x1UL) /*!< Max enumerator value of COLLISION field. */ + #define NFCT_INTEN_COLLISION_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_COLLISION_Enabled (0x1UL) /*!< Enable */ + +/* SELECTED @Bit 19 : Enable or disable interrupt for event SELECTED */ + #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ + #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ + #define NFCT_INTEN_SELECTED_Min (0x0UL) /*!< Min enumerator value of SELECTED field. */ + #define NFCT_INTEN_SELECTED_Max (0x1UL) /*!< Max enumerator value of SELECTED field. */ + #define NFCT_INTEN_SELECTED_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_SELECTED_Enabled (0x1UL) /*!< Enable */ + +/* STARTED @Bit 20 : Enable or disable interrupt for event STARTED */ + #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ + #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define NFCT_INTEN_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define NFCT_INTEN_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define NFCT_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ + #define NFCT_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ + + +/* NFCT_INTENSET: Enable interrupt */ + #define NFCT_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* READY @Bit 0 : Write '1' to enable interrupt for event READY */ + #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ + #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ + #define NFCT_INTENSET_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define NFCT_INTENSET_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define NFCT_INTENSET_READY_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FIELDDETECTED @Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */ + #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ + #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ + #define NFCT_INTENSET_FIELDDETECTED_Min (0x0UL) /*!< Min enumerator value of FIELDDETECTED field. */ + #define NFCT_INTENSET_FIELDDETECTED_Max (0x1UL) /*!< Max enumerator value of FIELDDETECTED field. */ + #define NFCT_INTENSET_FIELDDETECTED_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_FIELDDETECTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_FIELDDETECTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FIELDLOST @Bit 2 : Write '1' to enable interrupt for event FIELDLOST */ + #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ + #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ + #define NFCT_INTENSET_FIELDLOST_Min (0x0UL) /*!< Min enumerator value of FIELDLOST field. */ + #define NFCT_INTENSET_FIELDLOST_Max (0x1UL) /*!< Max enumerator value of FIELDLOST field. */ + #define NFCT_INTENSET_FIELDLOST_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_FIELDLOST_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_FIELDLOST_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXFRAMESTART @Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */ + #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ + #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ + #define NFCT_INTENSET_TXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of TXFRAMESTART field. */ + #define NFCT_INTENSET_TXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of TXFRAMESTART field. */ + #define NFCT_INTENSET_TXFRAMESTART_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_TXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_TXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXFRAMEEND @Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */ + #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ + #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ + #define NFCT_INTENSET_TXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of TXFRAMEEND field. */ + #define NFCT_INTENSET_TXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of TXFRAMEEND field. */ + #define NFCT_INTENSET_TXFRAMEEND_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_TXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_TXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXFRAMESTART @Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */ + #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ + #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ + #define NFCT_INTENSET_RXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of RXFRAMESTART field. */ + #define NFCT_INTENSET_RXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of RXFRAMESTART field. */ + #define NFCT_INTENSET_RXFRAMESTART_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_RXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_RXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXFRAMEEND @Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */ + #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ + #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ + #define NFCT_INTENSET_RXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of RXFRAMEEND field. */ + #define NFCT_INTENSET_RXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of RXFRAMEEND field. */ + #define NFCT_INTENSET_RXFRAMEEND_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_RXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_RXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 7 : Write '1' to enable interrupt for event ERROR */ + #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ + #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define NFCT_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define NFCT_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define NFCT_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXERROR @Bit 10 : Write '1' to enable interrupt for event RXERROR */ + #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ + #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ + #define NFCT_INTENSET_RXERROR_Min (0x0UL) /*!< Min enumerator value of RXERROR field. */ + #define NFCT_INTENSET_RXERROR_Max (0x1UL) /*!< Max enumerator value of RXERROR field. */ + #define NFCT_INTENSET_RXERROR_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_RXERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_RXERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ENDRX @Bit 11 : Write '1' to enable interrupt for event ENDRX */ + #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ + #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ + #define NFCT_INTENSET_ENDRX_Min (0x0UL) /*!< Min enumerator value of ENDRX field. */ + #define NFCT_INTENSET_ENDRX_Max (0x1UL) /*!< Max enumerator value of ENDRX field. */ + #define NFCT_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ENDTX @Bit 12 : Write '1' to enable interrupt for event ENDTX */ + #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ + #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ + #define NFCT_INTENSET_ENDTX_Min (0x0UL) /*!< Min enumerator value of ENDTX field. */ + #define NFCT_INTENSET_ENDTX_Max (0x1UL) /*!< Max enumerator value of ENDTX field. */ + #define NFCT_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* AUTOCOLRESSTARTED @Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */ + #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ + #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED + field.*/ + #define NFCT_INTENSET_AUTOCOLRESSTARTED_Min (0x0UL) /*!< Min enumerator value of AUTOCOLRESSTARTED field. */ + #define NFCT_INTENSET_AUTOCOLRESSTARTED_Max (0x1UL) /*!< Max enumerator value of AUTOCOLRESSTARTED field. */ + #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COLLISION @Bit 18 : Write '1' to enable interrupt for event COLLISION */ + #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ + #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ + #define NFCT_INTENSET_COLLISION_Min (0x0UL) /*!< Min enumerator value of COLLISION field. */ + #define NFCT_INTENSET_COLLISION_Max (0x1UL) /*!< Max enumerator value of COLLISION field. */ + #define NFCT_INTENSET_COLLISION_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_COLLISION_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_COLLISION_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SELECTED @Bit 19 : Write '1' to enable interrupt for event SELECTED */ + #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ + #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ + #define NFCT_INTENSET_SELECTED_Min (0x0UL) /*!< Min enumerator value of SELECTED field. */ + #define NFCT_INTENSET_SELECTED_Max (0x1UL) /*!< Max enumerator value of SELECTED field. */ + #define NFCT_INTENSET_SELECTED_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_SELECTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_SELECTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STARTED @Bit 20 : Write '1' to enable interrupt for event STARTED */ + #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ + #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define NFCT_INTENSET_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define NFCT_INTENSET_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define NFCT_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ + #define NFCT_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* NFCT_INTENCLR: Disable interrupt */ + #define NFCT_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* READY @Bit 0 : Write '1' to disable interrupt for event READY */ + #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ + #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ + #define NFCT_INTENCLR_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define NFCT_INTENCLR_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define NFCT_INTENCLR_READY_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FIELDDETECTED @Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */ + #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ + #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ + #define NFCT_INTENCLR_FIELDDETECTED_Min (0x0UL) /*!< Min enumerator value of FIELDDETECTED field. */ + #define NFCT_INTENCLR_FIELDDETECTED_Max (0x1UL) /*!< Max enumerator value of FIELDDETECTED field. */ + #define NFCT_INTENCLR_FIELDDETECTED_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_FIELDDETECTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FIELDLOST @Bit 2 : Write '1' to disable interrupt for event FIELDLOST */ + #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ + #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ + #define NFCT_INTENCLR_FIELDLOST_Min (0x0UL) /*!< Min enumerator value of FIELDLOST field. */ + #define NFCT_INTENCLR_FIELDLOST_Max (0x1UL) /*!< Max enumerator value of FIELDLOST field. */ + #define NFCT_INTENCLR_FIELDLOST_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_FIELDLOST_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_FIELDLOST_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXFRAMESTART @Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */ + #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ + #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ + #define NFCT_INTENCLR_TXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of TXFRAMESTART field. */ + #define NFCT_INTENCLR_TXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of TXFRAMESTART field. */ + #define NFCT_INTENCLR_TXFRAMESTART_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_TXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXFRAMEEND @Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */ + #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ + #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ + #define NFCT_INTENCLR_TXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of TXFRAMEEND field. */ + #define NFCT_INTENCLR_TXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of TXFRAMEEND field. */ + #define NFCT_INTENCLR_TXFRAMEEND_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_TXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXFRAMESTART @Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */ + #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ + #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ + #define NFCT_INTENCLR_RXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of RXFRAMESTART field. */ + #define NFCT_INTENCLR_RXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of RXFRAMESTART field. */ + #define NFCT_INTENCLR_RXFRAMESTART_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_RXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXFRAMEEND @Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */ + #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ + #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ + #define NFCT_INTENCLR_RXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of RXFRAMEEND field. */ + #define NFCT_INTENCLR_RXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of RXFRAMEEND field. */ + #define NFCT_INTENCLR_RXFRAMEEND_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_RXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 7 : Write '1' to disable interrupt for event ERROR */ + #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ + #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define NFCT_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define NFCT_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define NFCT_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXERROR @Bit 10 : Write '1' to disable interrupt for event RXERROR */ + #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ + #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ + #define NFCT_INTENCLR_RXERROR_Min (0x0UL) /*!< Min enumerator value of RXERROR field. */ + #define NFCT_INTENCLR_RXERROR_Max (0x1UL) /*!< Max enumerator value of RXERROR field. */ + #define NFCT_INTENCLR_RXERROR_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_RXERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_RXERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ENDRX @Bit 11 : Write '1' to disable interrupt for event ENDRX */ + #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ + #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ + #define NFCT_INTENCLR_ENDRX_Min (0x0UL) /*!< Min enumerator value of ENDRX field. */ + #define NFCT_INTENCLR_ENDRX_Max (0x1UL) /*!< Max enumerator value of ENDRX field. */ + #define NFCT_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ENDTX @Bit 12 : Write '1' to disable interrupt for event ENDTX */ + #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ + #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ + #define NFCT_INTENCLR_ENDTX_Min (0x0UL) /*!< Min enumerator value of ENDTX field. */ + #define NFCT_INTENCLR_ENDTX_Max (0x1UL) /*!< Max enumerator value of ENDTX field. */ + #define NFCT_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* AUTOCOLRESSTARTED @Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */ + #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ + #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED + field.*/ + #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Min (0x0UL) /*!< Min enumerator value of AUTOCOLRESSTARTED field. */ + #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Max (0x1UL) /*!< Max enumerator value of AUTOCOLRESSTARTED field. */ + #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COLLISION @Bit 18 : Write '1' to disable interrupt for event COLLISION */ + #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ + #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ + #define NFCT_INTENCLR_COLLISION_Min (0x0UL) /*!< Min enumerator value of COLLISION field. */ + #define NFCT_INTENCLR_COLLISION_Max (0x1UL) /*!< Max enumerator value of COLLISION field. */ + #define NFCT_INTENCLR_COLLISION_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_COLLISION_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_COLLISION_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SELECTED @Bit 19 : Write '1' to disable interrupt for event SELECTED */ + #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ + #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ + #define NFCT_INTENCLR_SELECTED_Min (0x0UL) /*!< Min enumerator value of SELECTED field. */ + #define NFCT_INTENCLR_SELECTED_Max (0x1UL) /*!< Max enumerator value of SELECTED field. */ + #define NFCT_INTENCLR_SELECTED_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_SELECTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_SELECTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STARTED @Bit 20 : Write '1' to disable interrupt for event STARTED */ + #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ + #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define NFCT_INTENCLR_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define NFCT_INTENCLR_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define NFCT_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ + #define NFCT_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define NFCT_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* NFCT_ERRORSTATUS: NFC Error Status register */ + #define NFCT_ERRORSTATUS_ResetValue (0x00000000UL) /*!< Reset value of ERRORSTATUS register. */ + +/* FRAMEDELAYTIMEOUT @Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */ + #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */ + #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of + FRAMEDELAYTIMEOUT field.*/ + + +/* NFCT_NFCTAGSTATE: Current operating state of NFC tag */ + #define NFCT_NFCTAGSTATE_ResetValue (0x00000000UL) /*!< Reset value of NFCTAGSTATE register. */ + +/* NFCTAGSTATE @Bits 0..2 : NfcTag state */ + #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */ + #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */ + #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Min (0x0UL) /*!< Min enumerator value of NFCTAGSTATE field. */ + #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Max (0x6UL) /*!< Max enumerator value of NFCTAGSTATE field. */ + #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0x0UL) /*!< Disabled or sense */ + #define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (0x2UL) /*!< RampUp */ + #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (0x3UL) /*!< Idle */ + #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (0x4UL) /*!< Receive */ + #define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (0x5UL) /*!< FrameDelay */ + #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (0x6UL) /*!< Transmit */ + + +/* NFCT_SLEEPSTATE: Sleep state during automatic collision resolution */ + #define NFCT_SLEEPSTATE_ResetValue (0x00000000UL) /*!< Reset value of SLEEPSTATE register. */ + +/* SLEEPSTATE @Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to + SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. */ + + #define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */ + #define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field. */ + #define NFCT_SLEEPSTATE_SLEEPSTATE_Min (0x0UL) /*!< Min enumerator value of SLEEPSTATE field. */ + #define NFCT_SLEEPSTATE_SLEEPSTATE_Max (0x1UL) /*!< Max enumerator value of SLEEPSTATE field. */ + #define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0x0UL) /*!< State is IDLE. */ + #define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (0x1UL) /*!< State is SLEEP_A. */ + + +/* NFCT_FIELDPRESENT: Indicates the presence or not of a valid field */ + #define NFCT_FIELDPRESENT_ResetValue (0x00000000UL) /*!< Reset value of FIELDPRESENT register. */ + +/* FIELDPRESENT @Bit 0 : Indicates if a valid field is present. Available only in the activated state. */ + #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */ + #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field.*/ + #define NFCT_FIELDPRESENT_FIELDPRESENT_Min (0x0UL) /*!< Min enumerator value of FIELDPRESENT field. */ + #define NFCT_FIELDPRESENT_FIELDPRESENT_Max (0x1UL) /*!< Max enumerator value of FIELDPRESENT field. */ + #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0x0UL) /*!< No valid field detected */ + #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (0x1UL) /*!< Valid field detected */ + +/* LOCKDETECT @Bit 1 : Indicates if the low level has locked to the field */ + #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */ + #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */ + #define NFCT_FIELDPRESENT_LOCKDETECT_Min (0x0UL) /*!< Min enumerator value of LOCKDETECT field. */ + #define NFCT_FIELDPRESENT_LOCKDETECT_Max (0x1UL) /*!< Max enumerator value of LOCKDETECT field. */ + #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0x0UL) /*!< Not locked to field */ + #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (0x1UL) /*!< Locked to field */ + + +/* NFCT_FRAMEDELAYMIN: Minimum frame delay */ + #define NFCT_FRAMEDELAYMIN_ResetValue (0x00000480UL) /*!< Reset value of FRAMEDELAYMIN register. */ + +/* FRAMEDELAYMIN @Bits 0..15 : Minimum frame delay in number of 13.56 MHz clock cycles */ + #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */ + #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN + field.*/ + + +/* NFCT_FRAMEDELAYMAX: Maximum frame delay */ + #define NFCT_FRAMEDELAYMAX_ResetValue (0x00001000UL) /*!< Reset value of FRAMEDELAYMAX register. */ + +/* FRAMEDELAYMAX @Bits 0..19 : Maximum frame delay in number of 13.56 MHz clock cycles */ + #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ + #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of + FRAMEDELAYMAX field.*/ + + +/* NFCT_FRAMEDELAYMODE: Configuration register for the Frame Delay Timer */ + #define NFCT_FRAMEDELAYMODE_ResetValue (0x00000001UL) /*!< Reset value of FRAMEDELAYMODE register. */ + +/* FRAMEDELAYMODE @Bits 0..1 : Configuration register for the Frame Delay Timer */ + #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */ + #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of + FRAMEDELAYMODE field.*/ + #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Min (0x0UL) /*!< Min enumerator value of FRAMEDELAYMODE field. */ + #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Max (0x3UL) /*!< Max enumerator value of FRAMEDELAYMODE field. */ + #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0x0UL) /*!< Transmission is independent of frame timer and will start when + the STARTTX task is triggered. No timeout.*/ + #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (0x1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */ + #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (0x2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */ + #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (0x3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN + and FRAMEDELAYMAX*/ + + +/* NFCT_PACKETPTR: Packet pointer for TXD and RXD data storage in Data RAM */ + #define NFCT_PACKETPTR_ResetValue (0x00000000UL) /*!< Reset value of PACKETPTR register. */ + +/* PTR @Bits 0..31 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */ + #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* NFCT_MAXLEN: Size of the RAM buffer allocated to TXD and RXD data storage each */ + #define NFCT_MAXLEN_ResetValue (0x00000000UL) /*!< Reset value of MAXLEN register. */ + +/* MAXLEN @Bits 0..8 : Size of the RAM buffer allocated to TXD and RXD data storage each */ + #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ + #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + #define NFCT_MAXLEN_MAXLEN_Min (0x000UL) /*!< Min value of MAXLEN field. */ + #define NFCT_MAXLEN_MAXLEN_Max (0x101UL) /*!< Max size of MAXLEN field. */ + + +/* NFCT_MODULATIONCTRL: Enables the modulation output to a GPIO pin which can be connected to a second external antenna. */ + #define NFCT_MODULATIONCTRL_ResetValue (0x00000001UL) /*!< Reset value of MODULATIONCTRL register. */ + +/* MODULATIONCTRL @Bits 0..1 : Configuration of modulation control. */ + #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos (0UL) /*!< Position of MODULATIONCTRL field. */ + #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk (0x3UL << NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos) /*!< Bit mask of + MODULATIONCTRL field.*/ + #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Min (0x0UL) /*!< Min enumerator value of MODULATIONCTRL field. */ + #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Max (0x3UL) /*!< Max enumerator value of MODULATIONCTRL field. */ + #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Invalid (0x0UL) /*!< Invalid, defaults to same behaviour as for Internal */ + #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Internal (0x1UL) /*!< Use internal modulator only */ + #define NFCT_MODULATIONCTRL_MODULATIONCTRL_ModToGpio (0x2UL) /*!< Output digital modulation signal to a GPIO pin. */ + #define NFCT_MODULATIONCTRL_MODULATIONCTRL_InternalAndModToGpio (0x3UL) /*!< Use internal modulator and output digital + modulation signal to a GPIO pin.*/ + + +/* NFCT_MODULATIONPSEL: Pin select for Modulation control */ + #define NFCT_MODULATIONPSEL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MODULATIONPSEL register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define NFCT_MODULATIONPSEL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define NFCT_MODULATIONPSEL_PIN_Msk (0x1FUL << NFCT_MODULATIONPSEL_PIN_Pos) /*!< Bit mask of PIN field. */ + #define NFCT_MODULATIONPSEL_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define NFCT_MODULATIONPSEL_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..6 : Port number */ + #define NFCT_MODULATIONPSEL_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define NFCT_MODULATIONPSEL_PORT_Msk (0x3UL << NFCT_MODULATIONPSEL_PORT_Pos) /*!< Bit mask of PORT field. */ + #define NFCT_MODULATIONPSEL_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define NFCT_MODULATIONPSEL_PORT_Max (0x3UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define NFCT_MODULATIONPSEL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define NFCT_MODULATIONPSEL_CONNECT_Msk (0x1UL << NFCT_MODULATIONPSEL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define NFCT_MODULATIONPSEL_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define NFCT_MODULATIONPSEL_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define NFCT_MODULATIONPSEL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define NFCT_MODULATIONPSEL_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* NFCT_MODE: Configure EasyDMA mode */ + #define NFCT_MODE_ResetValue (0x00000001UL) /*!< Reset value of MODE register. */ + +/* LPOP @Bits 0..1 : Enable low-power operation, or use low-latency */ + #define NFCT_MODE_LPOP_Pos (0UL) /*!< Position of LPOP field. */ + #define NFCT_MODE_LPOP_Msk (0x3UL << NFCT_MODE_LPOP_Pos) /*!< Bit mask of LPOP field. */ + #define NFCT_MODE_LPOP_Min (0x0UL) /*!< Min enumerator value of LPOP field. */ + #define NFCT_MODE_LPOP_Max (0x3UL) /*!< Max enumerator value of LPOP field. */ + #define NFCT_MODE_LPOP_LowLat (0x0UL) /*!< Low-latency operation */ + #define NFCT_MODE_LPOP_LowPower (0x1UL) /*!< Low-power operation */ + #define NFCT_MODE_LPOP_FullLowPower (0x3UL) /*!< Full Low-power operation */ + + +/* NFCT_AUTOCOLRESCONFIG: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral + is activated. */ + + #define NFCT_AUTOCOLRESCONFIG_ResetValue (0x00000002UL) /*!< Reset value of AUTOCOLRESCONFIG register. */ + +/* MODE @Bit 0 : Enables/disables auto collision resolution */ + #define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ + #define NFCT_AUTOCOLRESCONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define NFCT_AUTOCOLRESCONFIG_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0x0UL) /*!< Auto collision resolution enabled */ + #define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (0x1UL) /*!< Auto collision resolution disabled */ + + +/* NFCT_SENSRES: NFC-A SENS_RES auto-response settings */ + #define NFCT_SENSRES_ResetValue (0x00000001UL) /*!< Reset value of SENSRES register. */ + +/* BITFRAMESDD @Bits 0..4 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital + Protocol Technical Specification */ + + #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */ + #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */ + #define NFCT_SENSRES_BITFRAMESDD_Min (0x00UL) /*!< Min enumerator value of BITFRAMESDD field. */ + #define NFCT_SENSRES_BITFRAMESDD_Max (0x10UL) /*!< Max enumerator value of BITFRAMESDD field. */ + #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0x00UL) /*!< SDD pattern 00000 */ + #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (0x01UL) /*!< SDD pattern 00001 */ + #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (0x02UL) /*!< SDD pattern 00010 */ + #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (0x04UL) /*!< SDD pattern 00100 */ + #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (0x08UL) /*!< SDD pattern 01000 */ + #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (0x10UL) /*!< SDD pattern 10000 */ + +/* RFU5 @Bit 5 : Reserved for future use. Shall be 0. */ + #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */ + #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */ + +/* NFCIDSIZE @Bits 6..7 : NFCID1 size. This value is used by the auto collision resolution engine. */ + #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */ + #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */ + #define NFCT_SENSRES_NFCIDSIZE_Min (0x0UL) /*!< Min enumerator value of NFCIDSIZE field. */ + #define NFCT_SENSRES_NFCIDSIZE_Max (0x2UL) /*!< Max enumerator value of NFCIDSIZE field. */ + #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0x0UL) /*!< NFCID1 size: single (4 bytes) */ + #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (0x1UL) /*!< NFCID1 size: double (7 bytes) */ + #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (0x2UL) /*!< NFCID1 size: triple (10 bytes) */ + +/* PLATFCONFIG @Bits 8..11 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, + NFC Digital Protocol Technical Specification */ + + #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */ + #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */ + +/* RFU74 @Bits 12..15 : Reserved for future use. Shall be 0. */ + #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */ + #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */ + + +/* NFCT_SELRES: NFC-A SEL_RES auto-response settings */ + #define NFCT_SELRES_ResetValue (0x00000000UL) /*!< Reset value of SELRES register. */ + +/* RFU10 @Bits 0..1 : Reserved for future use. Shall be 0. */ + #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */ + #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */ + +/* CASCADE @Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical + Specification (controlled by hardware, shall be 0) */ + + #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */ + #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */ + +/* RFU43 @Bits 3..4 : Reserved for future use. Shall be 0. */ + #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */ + #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */ + +/* PROTOCOL @Bits 5..6 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical + Specification */ + + #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */ + #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ + +/* RFU7 @Bit 7 : Reserved for future use. Shall be 0. */ + #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */ + #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */ + + +/* NFCT_PADCONFIG: NFC pad configuration */ + #define NFCT_PADCONFIG_ResetValue (0x00000001UL) /*!< Reset value of PADCONFIG register. */ + +/* ENABLE @Bit 0 : Enable NFC pads */ + #define NFCT_PADCONFIG_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define NFCT_PADCONFIG_ENABLE_Msk (0x1UL << NFCT_PADCONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define NFCT_PADCONFIG_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define NFCT_PADCONFIG_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define NFCT_PADCONFIG_ENABLE_Disabled (0x0UL) /*!< NFC pads are used as GPIO pins */ + #define NFCT_PADCONFIG_ENABLE_Enabled (0x1UL) /*!< The NFC pads are configured as NFC antenna pins */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ OSCILLATORS ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ============================================ Struct OSCILLATORS_XOSC32M_CONFIG ============================================ */ +/** + * @brief CONFIG [OSCILLATORS_XOSC32M_CONFIG] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IOM uint32_t INTCAP; /*!< (@ 0x00000008) Crystal load capacitor as seen by the crystal across + its terminals, including pin capacitance but excluding + PCB stray capacitance.*/ +} NRF_OSCILLATORS_XOSC32M_CONFIG_Type; /*!< Size = 12 (0x00C) */ + +/* OSCILLATORS_XOSC32M_CONFIG_INTCAP: Crystal load capacitor as seen by the crystal across its terminals, including pin + capacitance but excluding PCB stray capacitance. */ + + #define OSCILLATORS_XOSC32M_CONFIG_INTCAP_ResetValue (0x00000020UL) /*!< Reset value of INTCAP register. */ + +/* VAL @Bits 0..5 : Crystal load capacitor value */ + #define OSCILLATORS_XOSC32M_CONFIG_INTCAP_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define OSCILLATORS_XOSC32M_CONFIG_INTCAP_VAL_Msk (0x3FUL << OSCILLATORS_XOSC32M_CONFIG_INTCAP_VAL_Pos) /*!< Bit mask of VAL + field.*/ + + + +/* =============================================== Struct OSCILLATORS_XOSC32M ================================================ */ +/** + * @brief XOSC32M [OSCILLATORS_XOSC32M] 32 MHz oscillator control + */ +typedef struct { + __IM uint32_t RESERVED[5]; + __IOM NRF_OSCILLATORS_XOSC32M_CONFIG_Type CONFIG; /*!< (@ 0x00000014) (unspecified) */ +} NRF_OSCILLATORS_XOSC32M_Type; /*!< Size = 32 (0x020) */ + + +/* ================================================= Struct OSCILLATORS_PLL ================================================== */ +/** + * @brief PLL [OSCILLATORS_PLL] Oscillator control + */ +typedef struct { + __IOM uint32_t FREQ; /*!< (@ 0x00000000) Set speed of MCU power domain, including CPU */ + __IM uint32_t CURRENTFREQ; /*!< (@ 0x00000004) Current speed of MCU power domain, including CPU */ +} NRF_OSCILLATORS_PLL_Type; /*!< Size = 8 (0x008) */ + +/* OSCILLATORS_PLL_FREQ: Set speed of MCU power domain, including CPU */ + #define OSCILLATORS_PLL_FREQ_ResetValue (0x00000003UL) /*!< Reset value of FREQ register. */ + +/* FREQ @Bits 0..1 : Select CPU speed */ + #define OSCILLATORS_PLL_FREQ_FREQ_Pos (0UL) /*!< Position of FREQ field. */ + #define OSCILLATORS_PLL_FREQ_FREQ_Msk (0x3UL << OSCILLATORS_PLL_FREQ_FREQ_Pos) /*!< Bit mask of FREQ field. */ + #define OSCILLATORS_PLL_FREQ_FREQ_Min (0x1UL) /*!< Min enumerator value of FREQ field. */ + #define OSCILLATORS_PLL_FREQ_FREQ_Max (0x3UL) /*!< Max enumerator value of FREQ field. */ + #define OSCILLATORS_PLL_FREQ_FREQ_CK128M (0x1UL) /*!< 128 MHz */ + #define OSCILLATORS_PLL_FREQ_FREQ_CK64M (0x3UL) /*!< 64 MHz */ + + +/* OSCILLATORS_PLL_CURRENTFREQ: Current speed of MCU power domain, including CPU */ + #define OSCILLATORS_PLL_CURRENTFREQ_ResetValue (0x00000003UL) /*!< Reset value of CURRENTFREQ register. */ + +/* CURRENTFREQ @Bits 0..1 : Active CPU speed */ + #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_Pos (0UL) /*!< Position of CURRENTFREQ field. */ + #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_Msk (0x3UL << OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_Pos) /*!< Bit mask of + CURRENTFREQ field.*/ + #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_Min (0x1UL) /*!< Min enumerator value of CURRENTFREQ field. */ + #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_Max (0x3UL) /*!< Max enumerator value of CURRENTFREQ field. */ + #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_CK128M (0x1UL) /*!< 128 MHz */ + #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_CK64M (0x3UL) /*!< 64 MHz */ + + + +/* =============================================== Struct OSCILLATORS_XOSC32KI =============================================== */ +/** + * @brief XOSC32KI [OSCILLATORS_XOSC32KI] 32.768 kHz oscillator control + */ +typedef struct { + __IOM uint32_t BYPASS; /*!< (@ 0x00000000) Enable or disable bypass of LFCLK crystal oscillator + with external clock source*/ + __IOM uint32_t INTCAP; /*!< (@ 0x00000004) Programmable capacitance of XL1 and XL2 */ +} NRF_OSCILLATORS_XOSC32KI_Type; /*!< Size = 8 (0x008) */ + +/* OSCILLATORS_XOSC32KI_BYPASS: Enable or disable bypass of LFCLK crystal oscillator with external clock source */ + #define OSCILLATORS_XOSC32KI_BYPASS_ResetValue (0x00000000UL) /*!< Reset value of BYPASS register. */ + +/* BYPASS @Bit 0 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos (0UL) /*!< Position of BYPASS field. */ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Msk (0x1UL << OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos) /*!< Bit mask of BYPASS + field.*/ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Min (0x0UL) /*!< Min enumerator value of BYPASS field. */ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Max (0x1UL) /*!< Max enumerator value of BYPASS field. */ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Disabled (0x0UL) /*!< Disable (use crystal) */ + #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Enabled (0x1UL) /*!< Enable (use rail-to-rail external source) */ + + +/* OSCILLATORS_XOSC32KI_INTCAP: Programmable capacitance of XL1 and XL2 */ + #define OSCILLATORS_XOSC32KI_INTCAP_ResetValue (0x00000017UL) /*!< Reset value of INTCAP register. */ + +/* VAL @Bits 0..4 : Crystal load capacitor as seen by the crystal across its terminals, including pin capacitance but excluding + PCB stray capacitance. */ + + #define OSCILLATORS_XOSC32KI_INTCAP_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define OSCILLATORS_XOSC32KI_INTCAP_VAL_Msk (0x1FUL << OSCILLATORS_XOSC32KI_INTCAP_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/* =================================================== Struct OSCILLATORS ==================================================== */ +/** + * @brief Oscillator control + */ + typedef struct { /*!< OSCILLATORS Structure */ + __IM uint32_t RESERVED[448]; + __IOM NRF_OSCILLATORS_XOSC32M_Type XOSC32M; /*!< (@ 0x00000700) 32 MHz oscillator control */ + __IM uint32_t RESERVED1[56]; + __IOM NRF_OSCILLATORS_PLL_Type PLL; /*!< (@ 0x00000800) Oscillator control */ + __IM uint32_t RESERVED2[62]; + __IOM NRF_OSCILLATORS_XOSC32KI_Type XOSC32KI; /*!< (@ 0x00000900) 32.768 kHz oscillator control */ + } NRF_OSCILLATORS_Type; /*!< Size = 2312 (0x908) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct PDM_EVENTS_DMA ================================================== */ +/** + * @brief EVENTS_DMA [PDM_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM uint32_t BUSERROR; /*!< (@ 0x00000000) This event is generated if an error occurs during the + bus transfer.*/ +} NRF_PDM_EVENTS_DMA_Type; /*!< Size = 4 (0x004) */ + +/* PDM_EVENTS_DMA_BUSERROR: This event is generated if an error occurs during the bus transfer. */ + #define PDM_EVENTS_DMA_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */ + #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_Msk (0x1UL << PDM_EVENTS_DMA_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR field.*/ + #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct PDM_PUBLISH_DMA ================================================== */ +/** + * @brief PUBLISH_DMA [PDM_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM uint32_t BUSERROR; /*!< (@ 0x00000000) Publish configuration for event DMA.BUSERROR */ +} NRF_PDM_PUBLISH_DMA_Type; /*!< Size = 4 (0x004) */ + +/* PDM_PUBLISH_DMA_BUSERROR: Publish configuration for event DMA.BUSERROR */ + #define PDM_PUBLISH_DMA_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DMA.BUSERROR will publish to */ + #define PDM_PUBLISH_DMA_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PDM_PUBLISH_DMA_BUSERROR_CHIDX_Msk (0xFFUL << PDM_PUBLISH_DMA_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PDM_PUBLISH_DMA_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PDM_PUBLISH_DMA_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PDM_PUBLISH_DMA_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define PDM_PUBLISH_DMA_BUSERROR_EN_Msk (0x1UL << PDM_PUBLISH_DMA_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define PDM_PUBLISH_DMA_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PDM_PUBLISH_DMA_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PDM_PUBLISH_DMA_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PDM_PUBLISH_DMA_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ==================================================== Struct PDM_FILTER ==================================================== */ +/** + * @brief FILTER [PDM_FILTER] (unspecified) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Aditional PDM configurability */ + __IOM uint32_t HPPOLE; /*!< (@ 0x00000004) Settings for the high-pass filter */ + __IOM uint32_t HPDISABLE; /*!< (@ 0x00000008) High pass filter disable */ + __IOM uint32_t SOFTMUTE; /*!< (@ 0x0000000C) Soft mute function */ + __IOM uint32_t SOFTCYCLES; /*!< (@ 0x00000010) Soft mute settings */ + __IOM uint32_t SAMPLEDELAY; /*!< (@ 0x00000014) Input Data Sampling with Number of ckFilterL (double + frequency of PDM_CLK) Clock Cycle Delay. + Optionally,input sample point can be delayed + independently on left and right channels using + FILTER:CTRL[20:19] bits*/ +} NRF_PDM_FILTER_Type; /*!< Size = 24 (0x018) */ + +/* PDM_FILTER_CTRL: Aditional PDM configurability */ + #define PDM_FILTER_CTRL_ResetValue (0x4EE0D200UL) /*!< Reset value of CTRL register. */ + +/* OVERRIDERIGHTSOFTMUTE @Bit 6 : Override soft mute enable for right channel */ + #define PDM_FILTER_CTRL_OVERRIDERIGHTSOFTMUTE_Pos (6UL) /*!< Position of OVERRIDERIGHTSOFTMUTE field. */ + #define PDM_FILTER_CTRL_OVERRIDERIGHTSOFTMUTE_Msk (0x1UL << PDM_FILTER_CTRL_OVERRIDERIGHTSOFTMUTE_Pos) /*!< Bit mask of + OVERRIDERIGHTSOFTMUTE field.*/ + #define PDM_FILTER_CTRL_OVERRIDERIGHTSOFTMUTE_Min (0x0UL) /*!< Min enumerator value of OVERRIDERIGHTSOFTMUTE field. */ + #define PDM_FILTER_CTRL_OVERRIDERIGHTSOFTMUTE_Max (0x1UL) /*!< Max enumerator value of OVERRIDERIGHTSOFTMUTE field. */ + #define PDM_FILTER_CTRL_OVERRIDERIGHTSOFTMUTE_Disable (0x0UL) /*!< No action */ + #define PDM_FILTER_CTRL_OVERRIDERIGHTSOFTMUTE_Enable (0x1UL) /*!< override and disable soft mute */ + +/* OVERRIDELEFTSOFTMUTE @Bit 7 : Override soft mute enable for left channel */ + #define PDM_FILTER_CTRL_OVERRIDELEFTSOFTMUTE_Pos (7UL) /*!< Position of OVERRIDELEFTSOFTMUTE field. */ + #define PDM_FILTER_CTRL_OVERRIDELEFTSOFTMUTE_Msk (0x1UL << PDM_FILTER_CTRL_OVERRIDELEFTSOFTMUTE_Pos) /*!< Bit mask of + OVERRIDELEFTSOFTMUTE field.*/ + #define PDM_FILTER_CTRL_OVERRIDELEFTSOFTMUTE_Min (0x0UL) /*!< Min enumerator value of OVERRIDELEFTSOFTMUTE field. */ + #define PDM_FILTER_CTRL_OVERRIDELEFTSOFTMUTE_Max (0x1UL) /*!< Max enumerator value of OVERRIDELEFTSOFTMUTE field. */ + #define PDM_FILTER_CTRL_OVERRIDELEFTSOFTMUTE_Disable (0x0UL) /*!< No action */ + #define PDM_FILTER_CTRL_OVERRIDELEFTSOFTMUTE_Enable (0x1UL) /*!< override and disable soft mute */ + +/* GAINADD0P25 @Bit 8 : Add +0.25dB to the gain stage */ + #define PDM_FILTER_CTRL_GAINADD0P25_Pos (8UL) /*!< Position of GAINADD0P25 field. */ + #define PDM_FILTER_CTRL_GAINADD0P25_Msk (0x1UL << PDM_FILTER_CTRL_GAINADD0P25_Pos) /*!< Bit mask of GAINADD0P25 field. */ + #define PDM_FILTER_CTRL_GAINADD0P25_Min (0x0UL) /*!< Min enumerator value of GAINADD0P25 field. */ + #define PDM_FILTER_CTRL_GAINADD0P25_Max (0x1UL) /*!< Max enumerator value of GAINADD0P25 field. */ + #define PDM_FILTER_CTRL_GAINADD0P25_Disable (0x0UL) /*!< Nothing added */ + #define PDM_FILTER_CTRL_GAINADD0P25_Enable (0x1UL) /*!< +0.25dB added */ + +/* MINORSTEP025CUSTOM @Bit 9 : Compensates Gain with +0.25dB */ + #define PDM_FILTER_CTRL_MINORSTEP025CUSTOM_Pos (9UL) /*!< Position of MINORSTEP025CUSTOM field. */ + #define PDM_FILTER_CTRL_MINORSTEP025CUSTOM_Msk (0x1UL << PDM_FILTER_CTRL_MINORSTEP025CUSTOM_Pos) /*!< Bit mask of + MINORSTEP025CUSTOM field.*/ + #define PDM_FILTER_CTRL_MINORSTEP025CUSTOM_Min (0x0UL) /*!< Min enumerator value of MINORSTEP025CUSTOM field. */ + #define PDM_FILTER_CTRL_MINORSTEP025CUSTOM_Max (0x1UL) /*!< Max enumerator value of MINORSTEP025CUSTOM field. */ + #define PDM_FILTER_CTRL_MINORSTEP025CUSTOM_Disable (0x0UL) /*!< Nothing added */ + #define PDM_FILTER_CTRL_MINORSTEP025CUSTOM_Enable (0x1UL) /*!< +0.25dB added */ + +/* MINORSTEP050CUSTOM @Bits 10..13 : Compensates Gain with +0.5dB steps */ + #define PDM_FILTER_CTRL_MINORSTEP050CUSTOM_Pos (10UL) /*!< Position of MINORSTEP050CUSTOM field. */ + #define PDM_FILTER_CTRL_MINORSTEP050CUSTOM_Msk (0xFUL << PDM_FILTER_CTRL_MINORSTEP050CUSTOM_Pos) /*!< Bit mask of + MINORSTEP050CUSTOM field.*/ + #define PDM_FILTER_CTRL_MINORSTEP050CUSTOM_Min (0x0UL) /*!< Min value of MINORSTEP050CUSTOM field. */ + #define PDM_FILTER_CTRL_MINORSTEP050CUSTOM_Max (0xCUL) /*!< Max size of MINORSTEP050CUSTOM field. */ + +/* SOFTCYCLES @Bits 14..17 : Custom number of cycles for soft gain/mute function 32*(Multiplication+1) steps */ + #define PDM_FILTER_CTRL_SOFTCYCLES_Pos (14UL) /*!< Position of SOFTCYCLES field. */ + #define PDM_FILTER_CTRL_SOFTCYCLES_Msk (0xFUL << PDM_FILTER_CTRL_SOFTCYCLES_Pos) /*!< Bit mask of SOFTCYCLES field. */ + #define PDM_FILTER_CTRL_SOFTCYCLES_Min (0x0UL) /*!< Min value of SOFTCYCLES field. */ + #define PDM_FILTER_CTRL_SOFTCYCLES_Max (0xFUL) /*!< Max size of SOFTCYCLES field. */ + +/* DATASAMPLEDELAY @Bits 19..20 : Input data sampling point delay in PDM_CLK cycels */ + #define PDM_FILTER_CTRL_DATASAMPLEDELAY_Pos (19UL) /*!< Position of DATASAMPLEDELAY field. */ + #define PDM_FILTER_CTRL_DATASAMPLEDELAY_Msk (0x3UL << PDM_FILTER_CTRL_DATASAMPLEDELAY_Pos) /*!< Bit mask of DATASAMPLEDELAY + field.*/ + #define PDM_FILTER_CTRL_DATASAMPLEDELAY_Min (0x0UL) /*!< Min enumerator value of DATASAMPLEDELAY field. */ + #define PDM_FILTER_CTRL_DATASAMPLEDELAY_Max (0x3UL) /*!< Max enumerator value of DATASAMPLEDELAY field. */ + #define PDM_FILTER_CTRL_DATASAMPLEDELAY_NoDelay (0x0UL) /*!< No added delay */ + #define PDM_FILTER_CTRL_DATASAMPLEDELAY_DelayOnLeft (0x1UL) /*!< 1 clock cycle delay on left channel */ + #define PDM_FILTER_CTRL_DATASAMPLEDELAY_DelayOnRight (0x2UL) /*!< 1 clock cycle delay on right channel */ + #define PDM_FILTER_CTRL_DATASAMPLEDELAY_DelayOnBoth (0x3UL) /*!< 1 clock cycle delay on both channels */ + +/* CICFILTERMSBCUSTOM @Bits 21..24 : Defines MSB for CIC fliter when RATIO is set to 'Custom' */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Pos (21UL) /*!< Position of CICFILTERMSBCUSTOM field. */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Msk (0xFUL << PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Pos) /*!< Bit mask of + CICFILTERMSBCUSTOM field.*/ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Min (0x0UL) /*!< Min enumerator value of CICFILTERMSBCUSTOM field. */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Max (0xFUL) /*!< Max enumerator value of CICFILTERMSBCUSTOM field. */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range0 (0x0UL) /*!< OSR range low 4 OSR range high 32 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range1 (0x1UL) /*!< OSR range low 34 OSR range high 36 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range2 (0x2UL) /*!< OSR range low 38 OSR range high 42 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range3 (0x3UL) /*!< OSR range low 44 OSR range high 48 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range4 (0x4UL) /*!< OSR range low 50 OSR range high 54 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range5 (0x5UL) /*!< OSR range low 56 OSR range high 64 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range6 (0x6UL) /*!< OSR range low 66 OSR range high 72 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range7 (0x7UL) /*!< OSR range low 74 OSR range high 84 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range8 (0x8UL) /*!< OSR range low 86 OSR range high 96 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range9 (0x9UL) /*!< OSR range low 98 OSR range high 110 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range10 (0xAUL) /*!< OSR range low 112 OSR range high 128 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range11 (0xBUL) /*!< OSR range low 130 OSR range high 146 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range12 (0xCUL) /*!< OSR range low 148 OSR range high 168 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range13 (0xDUL) /*!< OSR range low 170 OSR range high 194 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range14 (0xEUL) /*!< OSR range low 196 OSR range high 222 */ + #define PDM_FILTER_CTRL_CICFILTERMSBCUSTOM_Range15 (0xFUL) /*!< OSR range low 224 OSR range high 256 */ + +/* DECRATIO @Bits 25..31 : Configures decimation ratio to any even number between 6 and 256 */ + #define PDM_FILTER_CTRL_DECRATIO_Pos (25UL) /*!< Position of DECRATIO field. */ + #define PDM_FILTER_CTRL_DECRATIO_Msk (0x7FUL << PDM_FILTER_CTRL_DECRATIO_Pos) /*!< Bit mask of DECRATIO field. */ + #define PDM_FILTER_CTRL_DECRATIO_Min (0x02UL) /*!< Min value of DECRATIO field. */ + #define PDM_FILTER_CTRL_DECRATIO_Max (0x7FUL) /*!< Max size of DECRATIO field. */ + + +/* PDM_FILTER_HPPOLE: Settings for the high-pass filter */ + #define PDM_FILTER_HPPOLE_ResetValue (0x00000005UL) /*!< Reset value of HPPOLE register. */ + +/* HPPOLE @Bits 0..3 : Settings for the high-pass filter -3dB gain pole, assuming filter source clock of 16KHz */ + #define PDM_FILTER_HPPOLE_HPPOLE_Pos (0UL) /*!< Position of HPPOLE field. */ + #define PDM_FILTER_HPPOLE_HPPOLE_Msk (0xFUL << PDM_FILTER_HPPOLE_HPPOLE_Pos) /*!< Bit mask of HPPOLE field. */ + #define PDM_FILTER_HPPOLE_HPPOLE_Min (0x1UL) /*!< Min enumerator value of HPPOLE field. */ + #define PDM_FILTER_HPPOLE_HPPOLE_Max (0xFUL) /*!< Max enumerator value of HPPOLE field. */ + #define PDM_FILTER_HPPOLE_HPPOLE_p0p16 (0xFUL) /*!< 0.16 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p0p32 (0xEUL) /*!< 0.32 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p0p64 (0xDUL) /*!< 0.64 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p1p25 (0xCUL) /*!< 1.25 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p2p5 (0xBUL) /*!< 2.5 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p5 (0xAUL) /*!< 5 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p10 (0x9UL) /*!< 10 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p20 (0x8UL) /*!< 20 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p40 (0x7UL) /*!< 40 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p79 (0x6UL) /*!< 79 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p157 (0x5UL) /*!< 157 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p310 (0x4UL) /*!< 310 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p603 (0x3UL) /*!< 603 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p1152 (0x2UL) /*!< 1152 Hz */ + #define PDM_FILTER_HPPOLE_HPPOLE_p2110 (0x1UL) /*!< 2110 Hz */ + + +/* PDM_FILTER_HPDISABLE: High pass filter disable */ + #define PDM_FILTER_HPDISABLE_ResetValue (0x00000001UL) /*!< Reset value of HPDISABLE register. */ + +/* DISABLE @Bit 0 : High pass filter disable */ + #define PDM_FILTER_HPDISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ + #define PDM_FILTER_HPDISABLE_DISABLE_Msk (0x1UL << PDM_FILTER_HPDISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ + #define PDM_FILTER_HPDISABLE_DISABLE_Min (0x0UL) /*!< Min enumerator value of DISABLE field. */ + #define PDM_FILTER_HPDISABLE_DISABLE_Max (0x1UL) /*!< Max enumerator value of DISABLE field. */ + #define PDM_FILTER_HPDISABLE_DISABLE_Enable (0x0UL) /*!< High pass filter enabled */ + #define PDM_FILTER_HPDISABLE_DISABLE_Disable (0x1UL) /*!< High pass filter disabled */ + + +/* PDM_FILTER_SOFTMUTE: Soft mute function */ + #define PDM_FILTER_SOFTMUTE_ResetValue (0x00000000UL) /*!< Reset value of SOFTMUTE register. */ + +/* ENABLE @Bit 0 : Soft mute function */ + #define PDM_FILTER_SOFTMUTE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define PDM_FILTER_SOFTMUTE_ENABLE_Msk (0x1UL << PDM_FILTER_SOFTMUTE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define PDM_FILTER_SOFTMUTE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define PDM_FILTER_SOFTMUTE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define PDM_FILTER_SOFTMUTE_ENABLE_Disabled (0x0UL) /*!< Disable soft mute function */ + #define PDM_FILTER_SOFTMUTE_ENABLE_Enabled (0x1UL) /*!< Enable soft mute function */ + + +/* PDM_FILTER_SOFTCYCLES: Soft mute settings */ + #define PDM_FILTER_SOFTCYCLES_ResetValue (0x00000002UL) /*!< Reset value of SOFTCYCLES register. */ + +/* DISABLE @Bits 0..2 : Soft mute settings: amount of cycles for transition */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_Msk (0x7UL << PDM_FILTER_SOFTCYCLES_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_Min (0x0UL) /*!< Min enumerator value of DISABLE field. */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_Max (0x7UL) /*!< Max enumerator value of DISABLE field. */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_s2 (0x0UL) /*!< 2 filter source clock cycles */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_s8 (0x1UL) /*!< 8 filter source clock cycles */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_s32 (0x2UL) /*!< 32 filter source clock cycles */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_s64 (0x3UL) /*!< 64 filter source clock cycles */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_s128 (0x4UL) /*!< 128 filter source clock cycles */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_s256 (0x5UL) /*!< 256 filter source clock cycles */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_s512 (0x6UL) /*!< 512 filter source clock cycles */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_Custom (0x7UL) /*!< The number of cycles can be set using FILTER.CTRL[17:14] bits */ + #define PDM_FILTER_SOFTCYCLES_DISABLE_custom (0x7UL) /*!< See the Custom enumerator */ + + +/* PDM_FILTER_SAMPLEDELAY: Input Data Sampling with Number of ckFilterL (double frequency of PDM_CLK) Clock Cycle Delay. + Optionally,input sample point can be delayed independently on left and right channels using + FILTER:CTRL[20:19] bits */ + + #define PDM_FILTER_SAMPLEDELAY_ResetValue (0x00000000UL) /*!< Reset value of SAMPLEDELAY register. */ + +/* DELAY @Bit 0 : Input Data Sampling with Number of ckFilterL (double frequency of PDM_CLK) Clock Cycle Delay */ + #define PDM_FILTER_SAMPLEDELAY_DELAY_Pos (0UL) /*!< Position of DELAY field. */ + #define PDM_FILTER_SAMPLEDELAY_DELAY_Msk (0x1UL << PDM_FILTER_SAMPLEDELAY_DELAY_Pos) /*!< Bit mask of DELAY field. */ + #define PDM_FILTER_SAMPLEDELAY_DELAY_Min (0x0UL) /*!< Min enumerator value of DELAY field. */ + #define PDM_FILTER_SAMPLEDELAY_DELAY_Max (0x1UL) /*!< Max enumerator value of DELAY field. */ + #define PDM_FILTER_SAMPLEDELAY_DELAY_NoDelay (0x0UL) /*!< No delay */ + #define PDM_FILTER_SAMPLEDELAY_DELAY_Delay1Ck (0x1UL) /*!< 1 Cycle */ + + + +/* ===================================================== Struct PDM_PSEL ===================================================== */ +/** + * @brief PSEL [PDM_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} NRF_PDM_PSEL_Type; /*!< Size = 8 (0x008) */ + +/* PDM_PSEL_CLK: Pin number configuration for PDM CLK signal */ + #define PDM_PSEL_CLK_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CLK register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + #define PDM_PSEL_CLK_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define PDM_PSEL_CLK_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define PDM_PSEL_CLK_PORT_Msk (0x7UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */ + #define PDM_PSEL_CLK_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define PDM_PSEL_CLK_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define PDM_PSEL_CLK_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define PDM_PSEL_CLK_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define PDM_PSEL_CLK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define PDM_PSEL_CLK_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* PDM_PSEL_DIN: Pin number configuration for PDM DIN signal */ + #define PDM_PSEL_DIN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DIN register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + #define PDM_PSEL_DIN_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define PDM_PSEL_DIN_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define PDM_PSEL_DIN_PORT_Msk (0x7UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */ + #define PDM_PSEL_DIN_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define PDM_PSEL_DIN_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define PDM_PSEL_DIN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define PDM_PSEL_DIN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define PDM_PSEL_DIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define PDM_PSEL_DIN_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ==================================================== Struct PDM_SAMPLE ==================================================== */ +/** + * @brief SAMPLE [PDM_SAMPLE] (unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes to allocate memory for in EasyDMA mode*/ +} NRF_PDM_SAMPLE_Type; /*!< Size = 8 (0x008) */ + +/* PDM_SAMPLE_PTR: RAM address pointer to write samples to with EasyDMA */ + #define PDM_SAMPLE_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* SAMPLEPTR @Bits 0..31 : Address to write PCM samples to over DMA */ + #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ + #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + + +/* PDM_SAMPLE_MAXCNT: Number of bytes to allocate memory for in EasyDMA mode */ + #define PDM_SAMPLE_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* BUFFSIZE @Bits 0..14 : Length of DMA RAM allocation in number of bytes */ + #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ + #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Min (0x0000UL) /*!< Min value of BUFFSIZE field. */ + #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Max (0x7FFFUL) /*!< Max size of BUFFSIZE field. */ + + + +/* ===================================================== Struct PDM_DMA ====================================================== */ +/** + * @brief DMA [PDM_DMA] (unspecified) + */ +typedef struct { + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_PDM_DMA_Type; /*!< Size = 8 (0x008) */ + +/* PDM_DMA_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define PDM_DMA_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << PDM_DMA_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of ENABLE + field.*/ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* PDM_DMA_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define PDM_DMA_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define PDM_DMA_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define PDM_DMA_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << PDM_DMA_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* ======================================================= Struct PDM ======================================================== */ +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface + */ + typedef struct { /*!< PDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified by + SAMPLE.MAXCNT (or the last sample after a STOP task has + been received) to Data RAM*/ + __IM uint32_t RESERVED2; + __IOM NRF_PDM_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x00000110) Peripheral events. */ + __IM uint32_t RESERVED3[27]; + __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ + __IM uint32_t RESERVED4; + __IOM NRF_PDM_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x00000190) Publish configuration for events */ + __IM uint32_t RESERVED5[91]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED6[124]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IM uint32_t RESERVED7; + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphone + signals*/ + __IM uint32_t RESERVED8[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the decimation ratio between PDM_CLK and output + sample rate. When RATIO is selected to be 'custom', the + decimation rate should be set using the FILTER.CTRL + field before setting the RATIO to 7 Change + PRESCALER.DIVISOR accordingly.*/ + __IOM NRF_PDM_FILTER_Type FILTER; /*!< (@ 0x00000524) (unspecified) */ + __IM uint32_t RESERVED9; + __IOM NRF_PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) (unspecified) */ + __IM uint32_t RESERVED10; + __IOM uint32_t CLKSELECT; /*!< (@ 0x0000054C) Master clock generator configuration */ + __IM uint32_t RESERVED11[4]; + __IOM NRF_PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) (unspecified) */ + __IM uint32_t RESERVED12[6]; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000580) The prescaler is used to set the PDM frequency */ + __IM uint32_t RESERVED13[95]; + __IOM NRF_PDM_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_PDM_Type; /*!< Size = 1800 (0x708) */ + +/* PDM_TASKS_START: Starts continuous PDM transfer */ + #define PDM_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Starts continuous PDM transfer */ + #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define PDM_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define PDM_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define PDM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* PDM_TASKS_STOP: Stops PDM transfer */ + #define PDM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stops PDM transfer */ + #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define PDM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define PDM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define PDM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* PDM_SUBSCRIBE_START: Subscribe configuration for task START */ + #define PDM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PDM_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PDM_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define PDM_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PDM_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PDM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PDM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PDM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define PDM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PDM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PDM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define PDM_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PDM_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PDM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PDM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PDM_EVENTS_STARTED: PDM transfer has started */ + #define PDM_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register. */ + +/* EVENTS_STARTED @Bit 0 : PDM transfer has started */ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED + field.*/ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field. */ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field. */ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ + + +/* PDM_EVENTS_STOPPED: PDM transfer has finished */ + #define PDM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : PDM transfer has finished */ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED + field.*/ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* PDM_EVENTS_END: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been + received) to Data RAM */ + + #define PDM_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has + been received) to Data RAM */ + + #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define PDM_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define PDM_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define PDM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* PDM_PUBLISH_STARTED: Publish configuration for event STARTED */ + #define PDM_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */ + #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PDM_PUBLISH_STARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PDM_PUBLISH_STARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define PDM_PUBLISH_STARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PDM_PUBLISH_STARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PDM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PDM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PDM_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define PDM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PDM_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PDM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define PDM_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PDM_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PDM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PDM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PDM_PUBLISH_END: Publish configuration for event END */ + #define PDM_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PDM_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PDM_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define PDM_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PDM_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PDM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PDM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PDM_INTEN: Enable or disable interrupt */ + #define PDM_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* STARTED @Bit 0 : Enable or disable interrupt for event STARTED */ + #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define PDM_INTEN_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define PDM_INTEN_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define PDM_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ + #define PDM_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ + +/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */ + #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PDM_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PDM_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PDM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define PDM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* END @Bit 2 : Enable or disable interrupt for event END */ + #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ + #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ + #define PDM_INTEN_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define PDM_INTEN_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define PDM_INTEN_END_Disabled (0x0UL) /*!< Disable */ + #define PDM_INTEN_END_Enabled (0x1UL) /*!< Enable */ + +/* DMABUSERROR @Bit 4 : Enable or disable interrupt for event DMABUSERROR */ + #define PDM_INTEN_DMABUSERROR_Pos (4UL) /*!< Position of DMABUSERROR field. */ + #define PDM_INTEN_DMABUSERROR_Msk (0x1UL << PDM_INTEN_DMABUSERROR_Pos) /*!< Bit mask of DMABUSERROR field. */ + #define PDM_INTEN_DMABUSERROR_Min (0x0UL) /*!< Min enumerator value of DMABUSERROR field. */ + #define PDM_INTEN_DMABUSERROR_Max (0x1UL) /*!< Max enumerator value of DMABUSERROR field. */ + #define PDM_INTEN_DMABUSERROR_Disabled (0x0UL) /*!< Disable */ + #define PDM_INTEN_DMABUSERROR_Enabled (0x1UL) /*!< Enable */ + + +/* PDM_INTENSET: Enable interrupt */ + #define PDM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */ + #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define PDM_INTENSET_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define PDM_INTENSET_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define PDM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ + #define PDM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PDM_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PDM_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PDM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define PDM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 2 : Write '1' to enable interrupt for event END */ + #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ + #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define PDM_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define PDM_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define PDM_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define PDM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMABUSERROR @Bit 4 : Write '1' to enable interrupt for event DMABUSERROR */ + #define PDM_INTENSET_DMABUSERROR_Pos (4UL) /*!< Position of DMABUSERROR field. */ + #define PDM_INTENSET_DMABUSERROR_Msk (0x1UL << PDM_INTENSET_DMABUSERROR_Pos) /*!< Bit mask of DMABUSERROR field. */ + #define PDM_INTENSET_DMABUSERROR_Min (0x0UL) /*!< Min enumerator value of DMABUSERROR field. */ + #define PDM_INTENSET_DMABUSERROR_Max (0x1UL) /*!< Max enumerator value of DMABUSERROR field. */ + #define PDM_INTENSET_DMABUSERROR_Set (0x1UL) /*!< Enable */ + #define PDM_INTENSET_DMABUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENSET_DMABUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* PDM_INTENCLR: Disable interrupt */ + #define PDM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */ + #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define PDM_INTENCLR_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define PDM_INTENCLR_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define PDM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ + #define PDM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PDM_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PDM_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PDM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define PDM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 2 : Write '1' to disable interrupt for event END */ + #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ + #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define PDM_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define PDM_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define PDM_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define PDM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMABUSERROR @Bit 4 : Write '1' to disable interrupt for event DMABUSERROR */ + #define PDM_INTENCLR_DMABUSERROR_Pos (4UL) /*!< Position of DMABUSERROR field. */ + #define PDM_INTENCLR_DMABUSERROR_Msk (0x1UL << PDM_INTENCLR_DMABUSERROR_Pos) /*!< Bit mask of DMABUSERROR field. */ + #define PDM_INTENCLR_DMABUSERROR_Min (0x0UL) /*!< Min enumerator value of DMABUSERROR field. */ + #define PDM_INTENCLR_DMABUSERROR_Max (0x1UL) /*!< Max enumerator value of DMABUSERROR field. */ + #define PDM_INTENCLR_DMABUSERROR_Clear (0x1UL) /*!< Disable */ + #define PDM_INTENCLR_DMABUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENCLR_DMABUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* PDM_INTPEND: Pending interrupts */ + #define PDM_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* STARTED @Bit 0 : Read pending status of interrupt for event STARTED */ + #define PDM_INTPEND_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define PDM_INTPEND_STARTED_Msk (0x1UL << PDM_INTPEND_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define PDM_INTPEND_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define PDM_INTPEND_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define PDM_INTPEND_STARTED_NotPending (0x0UL) /*!< Read: Not pending */ + #define PDM_INTPEND_STARTED_Pending (0x1UL) /*!< Read: Pending */ + +/* STOPPED @Bit 1 : Read pending status of interrupt for event STOPPED */ + #define PDM_INTPEND_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PDM_INTPEND_STOPPED_Msk (0x1UL << PDM_INTPEND_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PDM_INTPEND_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PDM_INTPEND_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PDM_INTPEND_STOPPED_NotPending (0x0UL) /*!< Read: Not pending */ + #define PDM_INTPEND_STOPPED_Pending (0x1UL) /*!< Read: Pending */ + +/* END @Bit 2 : Read pending status of interrupt for event END */ + #define PDM_INTPEND_END_Pos (2UL) /*!< Position of END field. */ + #define PDM_INTPEND_END_Msk (0x1UL << PDM_INTPEND_END_Pos) /*!< Bit mask of END field. */ + #define PDM_INTPEND_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define PDM_INTPEND_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define PDM_INTPEND_END_NotPending (0x0UL) /*!< Read: Not pending */ + #define PDM_INTPEND_END_Pending (0x1UL) /*!< Read: Pending */ + +/* DMABUSERROR @Bit 4 : Read pending status of interrupt for event DMABUSERROR */ + #define PDM_INTPEND_DMABUSERROR_Pos (4UL) /*!< Position of DMABUSERROR field. */ + #define PDM_INTPEND_DMABUSERROR_Msk (0x1UL << PDM_INTPEND_DMABUSERROR_Pos) /*!< Bit mask of DMABUSERROR field. */ + #define PDM_INTPEND_DMABUSERROR_Min (0x0UL) /*!< Min enumerator value of DMABUSERROR field. */ + #define PDM_INTPEND_DMABUSERROR_Max (0x1UL) /*!< Max enumerator value of DMABUSERROR field. */ + #define PDM_INTPEND_DMABUSERROR_NotPending (0x0UL) /*!< Read: Not pending */ + #define PDM_INTPEND_DMABUSERROR_Pending (0x1UL) /*!< Read: Pending */ + + +/* PDM_ENABLE: PDM module enable register */ + #define PDM_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable PDM module */ + #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define PDM_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define PDM_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define PDM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define PDM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* PDM_MODE: Defines the routing of the connected PDM microphone signals */ + #define PDM_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* OPERATION @Bit 0 : Mono or stereo operation */ + #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ + #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ + #define PDM_MODE_OPERATION_Min (0x0UL) /*!< Min enumerator value of OPERATION field. */ + #define PDM_MODE_OPERATION_Max (0x1UL) /*!< Max enumerator value of OPERATION field. */ + #define PDM_MODE_OPERATION_Stereo (0x0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM + word R=[31:16]; L=[15:0]*/ + #define PDM_MODE_OPERATION_Mono (0x1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM + word L1=[31:16]; L0=[15:0]*/ + +/* EDGE @Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled. */ + #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ + #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ + #define PDM_MODE_EDGE_Min (0x0UL) /*!< Min enumerator value of EDGE field. */ + #define PDM_MODE_EDGE_Max (0x1UL) /*!< Max enumerator value of EDGE field. */ + #define PDM_MODE_EDGE_LeftFalling (0x0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ + #define PDM_MODE_EDGE_LeftRising (0x1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + + +/* PDM_GAINL: Left output gain adjustment */ + #define PDM_GAINL_ResetValue (0x00000028UL) /*!< Reset value of GAINL register. */ + +/* GAINL @Bits 0..6 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust + 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ + + #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ + #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ + #define PDM_GAINL_GAINL_Min (0x00UL) /*!< Min enumerator value of GAINL field. */ + #define PDM_GAINL_GAINL_Max (0x50UL) /*!< Max enumerator value of GAINL field. */ + #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ + #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ + #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ + + +/* PDM_GAINR: Right output gain adjustment */ + #define PDM_GAINR_ResetValue (0x00000028UL) /*!< Reset value of GAINR register. */ + +/* GAINR @Bits 0..6 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + */ + + #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ + #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ + #define PDM_GAINR_GAINR_Min (0x00UL) /*!< Min enumerator value of GAINR field. */ + #define PDM_GAINR_GAINR_Max (0x50UL) /*!< Max enumerator value of GAINR field. */ + #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ + #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ + #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ + + +/* PDM_RATIO: Selects the decimation ratio between PDM_CLK and output sample rate. When RATIO is selected to be 'custom', the + decimation rate should be set using the FILTER.CTRL field before setting the RATIO to 7 Change PRESCALER.DIVISOR + accordingly. */ + + #define PDM_RATIO_ResetValue (0x00000002UL) /*!< Reset value of RATIO register. */ + +/* RATIO @Bits 0..2 : Selects the decimation ratio between PDM_CLK and output sample rate */ + #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ + #define PDM_RATIO_RATIO_Msk (0x7UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ + #define PDM_RATIO_RATIO_Min (0x0UL) /*!< Min enumerator value of RATIO field. */ + #define PDM_RATIO_RATIO_Max (0x7UL) /*!< Max enumerator value of RATIO field. */ + #define PDM_RATIO_RATIO_Ratio48 (0x0UL) /*!< Ratio of 48 */ + #define PDM_RATIO_RATIO_Ratio50 (0x1UL) /*!< Ratio of 50 */ + #define PDM_RATIO_RATIO_Ratio64 (0x2UL) /*!< Ratio of 64 */ + #define PDM_RATIO_RATIO_Ratio80 (0x3UL) /*!< Ratio of 80 */ + #define PDM_RATIO_RATIO_Ratio96 (0x4UL) /*!< Ratio of 96 */ + #define PDM_RATIO_RATIO_Ratio150 (0x5UL) /*!< Ratio of 150 */ + #define PDM_RATIO_RATIO_Ratio192 (0x6UL) /*!< Ratio of 192 */ + #define PDM_RATIO_RATIO_Custom (0x7UL) /*!< Custom. The decimation rate can be changed using the + FILTER.CTRL[31:25] bits*/ + + +/* PDM_CLKSELECT: Master clock generator configuration */ + #define PDM_CLKSELECT_ResetValue (0x00000000UL) /*!< Reset value of CLKSELECT register. */ + +/* SRC @Bit 0 : Master clock source selection */ + #define PDM_CLKSELECT_SRC_Pos (0UL) /*!< Position of SRC field. */ + #define PDM_CLKSELECT_SRC_Msk (0x1UL << PDM_CLKSELECT_SRC_Pos) /*!< Bit mask of SRC field. */ + #define PDM_CLKSELECT_SRC_Min (0x0UL) /*!< Min enumerator value of SRC field. */ + #define PDM_CLKSELECT_SRC_Max (0x1UL) /*!< Max enumerator value of SRC field. */ + #define PDM_CLKSELECT_SRC_PCLK32M (0x0UL) /*!< 32 MHz peripheral clock */ + #define PDM_CLKSELECT_SRC_ACLK (0x1UL) /*!< 24 MHz peripheral clock */ + + +/* PDM_PRESCALER: The prescaler is used to set the PDM frequency */ + #define PDM_PRESCALER_ResetValue (0x00000004UL) /*!< Reset value of PRESCALER register. */ + +/* DIVISOR @Bits 0..7 : Core clock to PDM divisor */ + #define PDM_PRESCALER_DIVISOR_Pos (0UL) /*!< Position of DIVISOR field. */ + #define PDM_PRESCALER_DIVISOR_Msk (0xFFUL << PDM_PRESCALER_DIVISOR_Pos) /*!< Bit mask of DIVISOR field. */ + #define PDM_PRESCALER_DIVISOR_Min (0x04UL) /*!< Min value of DIVISOR field. */ + #define PDM_PRESCALER_DIVISOR_Max (0x7EUL) /*!< Max size of DIVISOR field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ====================================================== Struct POWER ======================================================= */ +/** + * @brief Power control + */ + typedef struct { /*!< POWER Structure */ + __IM uint32_t RESERVED[12]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000030) Enable Constant Latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x00000034) Enable Low-power mode (variable latency) */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000B0) Subscribe configuration for task CONSTLAT */ + __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000B4) Subscribe configuration for task LOWPWR */ + __IM uint32_t RESERVED2[30]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000130) Power failure warning */ + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000134) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000138) CPU exited WFI/WFE sleep */ + __IM uint32_t RESERVED3[29]; + __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x000001B0) Publish configuration for event POFWARN */ + __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x000001B4) Publish configuration for event SLEEPENTER */ + __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x000001B8) Publish configuration for event SLEEPEXIT */ + __IM uint32_t RESERVED4[81]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[125]; + __IOM uint32_t GPREGRET[2]; /*!< (@ 0x00000500) General purpose retention register */ + __IM uint32_t RESERVED6[6]; + __IM uint32_t CONSTLATSTAT; /*!< (@ 0x00000520) Status of constant latency */ + } NRF_POWER_Type; /*!< Size = 1316 (0x524) */ + +/* POWER_TASKS_CONSTLAT: Enable Constant Latency mode */ + #define POWER_TASKS_CONSTLAT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CONSTLAT register. */ + +/* TASKS_CONSTLAT @Bit 0 : Enable Constant Latency mode */ + #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ + #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of + TASKS_CONSTLAT field.*/ + #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Min (0x1UL) /*!< Min enumerator value of TASKS_CONSTLAT field. */ + #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Max (0x1UL) /*!< Max enumerator value of TASKS_CONSTLAT field. */ + #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (0x1UL) /*!< Trigger task */ + + +/* POWER_TASKS_LOWPWR: Enable Low-power mode (variable latency) */ + #define POWER_TASKS_LOWPWR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_LOWPWR register. */ + +/* TASKS_LOWPWR @Bit 0 : Enable Low-power mode (variable latency) */ + #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ + #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR + field.*/ + #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Min (0x1UL) /*!< Min enumerator value of TASKS_LOWPWR field. */ + #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Max (0x1UL) /*!< Max enumerator value of TASKS_LOWPWR field. */ + #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (0x1UL) /*!< Trigger task */ + + +/* POWER_SUBSCRIBE_CONSTLAT: Subscribe configuration for task CONSTLAT */ + #define POWER_SUBSCRIBE_CONSTLAT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CONSTLAT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CONSTLAT will subscribe to */ + #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */ + #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */ + #define POWER_SUBSCRIBE_CONSTLAT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define POWER_SUBSCRIBE_CONSTLAT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* POWER_SUBSCRIBE_LOWPWR: Subscribe configuration for task LOWPWR */ + #define POWER_SUBSCRIBE_LOWPWR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_LOWPWR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task LOWPWR will subscribe to */ + #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */ + #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */ + #define POWER_SUBSCRIBE_LOWPWR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define POWER_SUBSCRIBE_LOWPWR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* POWER_EVENTS_POFWARN: Power failure warning */ + #define POWER_EVENTS_POFWARN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_POFWARN register. */ + +/* EVENTS_POFWARN @Bit 0 : Power failure warning */ + #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ + #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of + EVENTS_POFWARN field.*/ + #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Min (0x0UL) /*!< Min enumerator value of EVENTS_POFWARN field. */ + #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Max (0x1UL) /*!< Max enumerator value of EVENTS_POFWARN field. */ + #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0x0UL) /*!< Event not generated */ + #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (0x1UL) /*!< Event generated */ + + +/* POWER_EVENTS_SLEEPENTER: CPU entered WFI/WFE sleep */ + #define POWER_EVENTS_SLEEPENTER_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SLEEPENTER register. */ + +/* EVENTS_SLEEPENTER @Bit 0 : CPU entered WFI/WFE sleep */ + #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ + #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask + of EVENTS_SLEEPENTER field.*/ + #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Min (0x0UL) /*!< Min enumerator value of EVENTS_SLEEPENTER field. */ + #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Max (0x1UL) /*!< Max enumerator value of EVENTS_SLEEPENTER field. */ + #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0x0UL) /*!< Event not generated */ + #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (0x1UL) /*!< Event generated */ + + +/* POWER_EVENTS_SLEEPEXIT: CPU exited WFI/WFE sleep */ + #define POWER_EVENTS_SLEEPEXIT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SLEEPEXIT register. */ + +/* EVENTS_SLEEPEXIT @Bit 0 : CPU exited WFI/WFE sleep */ + #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ + #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of + EVENTS_SLEEPEXIT field.*/ + #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Min (0x0UL) /*!< Min enumerator value of EVENTS_SLEEPEXIT field. */ + #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Max (0x1UL) /*!< Max enumerator value of EVENTS_SLEEPEXIT field. */ + #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0x0UL) /*!< Event not generated */ + #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (0x1UL) /*!< Event generated */ + + +/* POWER_PUBLISH_POFWARN: Publish configuration for event POFWARN */ + #define POWER_PUBLISH_POFWARN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_POFWARN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event POFWARN will publish to */ + #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define POWER_PUBLISH_POFWARN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define POWER_PUBLISH_POFWARN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */ + #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */ + #define POWER_PUBLISH_POFWARN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define POWER_PUBLISH_POFWARN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define POWER_PUBLISH_POFWARN_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define POWER_PUBLISH_POFWARN_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* POWER_PUBLISH_SLEEPENTER: Publish configuration for event SLEEPENTER */ + #define POWER_PUBLISH_SLEEPENTER_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SLEEPENTER register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SLEEPENTER will publish to */ + #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define POWER_PUBLISH_SLEEPENTER_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define POWER_PUBLISH_SLEEPENTER_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */ + #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */ + #define POWER_PUBLISH_SLEEPENTER_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define POWER_PUBLISH_SLEEPENTER_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* POWER_PUBLISH_SLEEPEXIT: Publish configuration for event SLEEPEXIT */ + #define POWER_PUBLISH_SLEEPEXIT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SLEEPEXIT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SLEEPEXIT will publish to */ + #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */ + #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */ + #define POWER_PUBLISH_SLEEPEXIT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define POWER_PUBLISH_SLEEPEXIT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* POWER_INTEN: Enable or disable interrupt */ + #define POWER_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* POFWARN @Bit 12 : Enable or disable interrupt for event POFWARN */ + #define POWER_INTEN_POFWARN_Pos (12UL) /*!< Position of POFWARN field. */ + #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ + #define POWER_INTEN_POFWARN_Min (0x0UL) /*!< Min enumerator value of POFWARN field. */ + #define POWER_INTEN_POFWARN_Max (0x1UL) /*!< Max enumerator value of POFWARN field. */ + #define POWER_INTEN_POFWARN_Disabled (0x0UL) /*!< Disable */ + #define POWER_INTEN_POFWARN_Enabled (0x1UL) /*!< Enable */ + +/* SLEEPENTER @Bit 13 : Enable or disable interrupt for event SLEEPENTER */ + #define POWER_INTEN_SLEEPENTER_Pos (13UL) /*!< Position of SLEEPENTER field. */ + #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ + #define POWER_INTEN_SLEEPENTER_Min (0x0UL) /*!< Min enumerator value of SLEEPENTER field. */ + #define POWER_INTEN_SLEEPENTER_Max (0x1UL) /*!< Max enumerator value of SLEEPENTER field. */ + #define POWER_INTEN_SLEEPENTER_Disabled (0x0UL) /*!< Disable */ + #define POWER_INTEN_SLEEPENTER_Enabled (0x1UL) /*!< Enable */ + +/* SLEEPEXIT @Bit 14 : Enable or disable interrupt for event SLEEPEXIT */ + #define POWER_INTEN_SLEEPEXIT_Pos (14UL) /*!< Position of SLEEPEXIT field. */ + #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ + #define POWER_INTEN_SLEEPEXIT_Min (0x0UL) /*!< Min enumerator value of SLEEPEXIT field. */ + #define POWER_INTEN_SLEEPEXIT_Max (0x1UL) /*!< Max enumerator value of SLEEPEXIT field. */ + #define POWER_INTEN_SLEEPEXIT_Disabled (0x0UL) /*!< Disable */ + #define POWER_INTEN_SLEEPEXIT_Enabled (0x1UL) /*!< Enable */ + + +/* POWER_INTENSET: Enable interrupt */ + #define POWER_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* POFWARN @Bit 12 : Write '1' to enable interrupt for event POFWARN */ + #define POWER_INTENSET_POFWARN_Pos (12UL) /*!< Position of POFWARN field. */ + #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ + #define POWER_INTENSET_POFWARN_Min (0x0UL) /*!< Min enumerator value of POFWARN field. */ + #define POWER_INTENSET_POFWARN_Max (0x1UL) /*!< Max enumerator value of POFWARN field. */ + #define POWER_INTENSET_POFWARN_Set (0x1UL) /*!< Enable */ + #define POWER_INTENSET_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */ + #define POWER_INTENSET_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SLEEPENTER @Bit 13 : Write '1' to enable interrupt for event SLEEPENTER */ + #define POWER_INTENSET_SLEEPENTER_Pos (13UL) /*!< Position of SLEEPENTER field. */ + #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ + #define POWER_INTENSET_SLEEPENTER_Min (0x0UL) /*!< Min enumerator value of SLEEPENTER field. */ + #define POWER_INTENSET_SLEEPENTER_Max (0x1UL) /*!< Max enumerator value of SLEEPENTER field. */ + #define POWER_INTENSET_SLEEPENTER_Set (0x1UL) /*!< Enable */ + #define POWER_INTENSET_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */ + #define POWER_INTENSET_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SLEEPEXIT @Bit 14 : Write '1' to enable interrupt for event SLEEPEXIT */ + #define POWER_INTENSET_SLEEPEXIT_Pos (14UL) /*!< Position of SLEEPEXIT field. */ + #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ + #define POWER_INTENSET_SLEEPEXIT_Min (0x0UL) /*!< Min enumerator value of SLEEPEXIT field. */ + #define POWER_INTENSET_SLEEPEXIT_Max (0x1UL) /*!< Max enumerator value of SLEEPEXIT field. */ + #define POWER_INTENSET_SLEEPEXIT_Set (0x1UL) /*!< Enable */ + #define POWER_INTENSET_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */ + #define POWER_INTENSET_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* POWER_INTENCLR: Disable interrupt */ + #define POWER_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* POFWARN @Bit 12 : Write '1' to disable interrupt for event POFWARN */ + #define POWER_INTENCLR_POFWARN_Pos (12UL) /*!< Position of POFWARN field. */ + #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ + #define POWER_INTENCLR_POFWARN_Min (0x0UL) /*!< Min enumerator value of POFWARN field. */ + #define POWER_INTENCLR_POFWARN_Max (0x1UL) /*!< Max enumerator value of POFWARN field. */ + #define POWER_INTENCLR_POFWARN_Clear (0x1UL) /*!< Disable */ + #define POWER_INTENCLR_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */ + #define POWER_INTENCLR_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SLEEPENTER @Bit 13 : Write '1' to disable interrupt for event SLEEPENTER */ + #define POWER_INTENCLR_SLEEPENTER_Pos (13UL) /*!< Position of SLEEPENTER field. */ + #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ + #define POWER_INTENCLR_SLEEPENTER_Min (0x0UL) /*!< Min enumerator value of SLEEPENTER field. */ + #define POWER_INTENCLR_SLEEPENTER_Max (0x1UL) /*!< Max enumerator value of SLEEPENTER field. */ + #define POWER_INTENCLR_SLEEPENTER_Clear (0x1UL) /*!< Disable */ + #define POWER_INTENCLR_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */ + #define POWER_INTENCLR_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SLEEPEXIT @Bit 14 : Write '1' to disable interrupt for event SLEEPEXIT */ + #define POWER_INTENCLR_SLEEPEXIT_Pos (14UL) /*!< Position of SLEEPEXIT field. */ + #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ + #define POWER_INTENCLR_SLEEPEXIT_Min (0x0UL) /*!< Min enumerator value of SLEEPEXIT field. */ + #define POWER_INTENCLR_SLEEPEXIT_Max (0x1UL) /*!< Max enumerator value of SLEEPEXIT field. */ + #define POWER_INTENCLR_SLEEPEXIT_Clear (0x1UL) /*!< Disable */ + #define POWER_INTENCLR_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */ + #define POWER_INTENCLR_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* POWER_GPREGRET: General purpose retention register */ + #define POWER_GPREGRET_MaxCount (2UL) /*!< Max size of GPREGRET[2] array. */ + #define POWER_GPREGRET_MaxIndex (1UL) /*!< Max index of GPREGRET[2] array. */ + #define POWER_GPREGRET_MinIndex (0UL) /*!< Min index of GPREGRET[2] array. */ + #define POWER_GPREGRET_ResetValue (0x00000000UL) /*!< Reset value of GPREGRET[2] register. */ + +/* GPREGRET @Bits 0..7 : General purpose retention register */ + #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ + #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + + +/* POWER_CONSTLATSTAT: Status of constant latency */ + #define POWER_CONSTLATSTAT_ResetValue (0x00000000UL) /*!< Reset value of CONSTLATSTAT register. */ + +/* STATUS @Bit 0 : Status */ + #define POWER_CONSTLATSTAT_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define POWER_CONSTLATSTAT_STATUS_Msk (0x1UL << POWER_CONSTLATSTAT_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define POWER_CONSTLATSTAT_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define POWER_CONSTLATSTAT_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define POWER_CONSTLATSTAT_STATUS_Disable (0x0UL) /*!< Constant latency disabled */ + #define POWER_CONSTLATSTAT_STATUS_Enable (0x1UL) /*!< Constant latency enabled */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ PPIB ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct PPIB_OVERFLOW =================================================== */ +/** + * @brief OVERFLOW [PPIB_OVERFLOW] (unspecified) + */ +typedef struct { + __IOM uint32_t SEND; /*!< (@ 0x00000000) The task overflow for SEND tasks using SUBSCRIBE_SEND. + Write 0 to clear.*/ +} NRF_PPIB_OVERFLOW_Type; /*!< Size = 4 (0x004) */ + +/* PPIB_OVERFLOW_SEND: The task overflow for SEND tasks using SUBSCRIBE_SEND. Write 0 to clear. */ + #define PPIB_OVERFLOW_SEND_ResetValue (0x00000000UL) /*!< Reset value of SEND register. */ + +/* SEND0 @Bit 0 : The status for tasks overflow at SUBSCRIBE_SEND[0]. */ + #define PPIB_OVERFLOW_SEND_SEND0_Pos (0UL) /*!< Position of SEND0 field. */ + #define PPIB_OVERFLOW_SEND_SEND0_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND0_Pos) /*!< Bit mask of SEND0 field. */ + #define PPIB_OVERFLOW_SEND_SEND0_Min (0x0UL) /*!< Min enumerator value of SEND0 field. */ + #define PPIB_OVERFLOW_SEND_SEND0_Max (0x1UL) /*!< Max enumerator value of SEND0 field. */ + #define PPIB_OVERFLOW_SEND_SEND0_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND0_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND1 @Bit 1 : The status for tasks overflow at SUBSCRIBE_SEND[1]. */ + #define PPIB_OVERFLOW_SEND_SEND1_Pos (1UL) /*!< Position of SEND1 field. */ + #define PPIB_OVERFLOW_SEND_SEND1_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND1_Pos) /*!< Bit mask of SEND1 field. */ + #define PPIB_OVERFLOW_SEND_SEND1_Min (0x0UL) /*!< Min enumerator value of SEND1 field. */ + #define PPIB_OVERFLOW_SEND_SEND1_Max (0x1UL) /*!< Max enumerator value of SEND1 field. */ + #define PPIB_OVERFLOW_SEND_SEND1_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND1_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND2 @Bit 2 : The status for tasks overflow at SUBSCRIBE_SEND[2]. */ + #define PPIB_OVERFLOW_SEND_SEND2_Pos (2UL) /*!< Position of SEND2 field. */ + #define PPIB_OVERFLOW_SEND_SEND2_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND2_Pos) /*!< Bit mask of SEND2 field. */ + #define PPIB_OVERFLOW_SEND_SEND2_Min (0x0UL) /*!< Min enumerator value of SEND2 field. */ + #define PPIB_OVERFLOW_SEND_SEND2_Max (0x1UL) /*!< Max enumerator value of SEND2 field. */ + #define PPIB_OVERFLOW_SEND_SEND2_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND2_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND3 @Bit 3 : The status for tasks overflow at SUBSCRIBE_SEND[3]. */ + #define PPIB_OVERFLOW_SEND_SEND3_Pos (3UL) /*!< Position of SEND3 field. */ + #define PPIB_OVERFLOW_SEND_SEND3_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND3_Pos) /*!< Bit mask of SEND3 field. */ + #define PPIB_OVERFLOW_SEND_SEND3_Min (0x0UL) /*!< Min enumerator value of SEND3 field. */ + #define PPIB_OVERFLOW_SEND_SEND3_Max (0x1UL) /*!< Max enumerator value of SEND3 field. */ + #define PPIB_OVERFLOW_SEND_SEND3_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND3_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND4 @Bit 4 : The status for tasks overflow at SUBSCRIBE_SEND[4]. */ + #define PPIB_OVERFLOW_SEND_SEND4_Pos (4UL) /*!< Position of SEND4 field. */ + #define PPIB_OVERFLOW_SEND_SEND4_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND4_Pos) /*!< Bit mask of SEND4 field. */ + #define PPIB_OVERFLOW_SEND_SEND4_Min (0x0UL) /*!< Min enumerator value of SEND4 field. */ + #define PPIB_OVERFLOW_SEND_SEND4_Max (0x1UL) /*!< Max enumerator value of SEND4 field. */ + #define PPIB_OVERFLOW_SEND_SEND4_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND4_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND5 @Bit 5 : The status for tasks overflow at SUBSCRIBE_SEND[5]. */ + #define PPIB_OVERFLOW_SEND_SEND5_Pos (5UL) /*!< Position of SEND5 field. */ + #define PPIB_OVERFLOW_SEND_SEND5_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND5_Pos) /*!< Bit mask of SEND5 field. */ + #define PPIB_OVERFLOW_SEND_SEND5_Min (0x0UL) /*!< Min enumerator value of SEND5 field. */ + #define PPIB_OVERFLOW_SEND_SEND5_Max (0x1UL) /*!< Max enumerator value of SEND5 field. */ + #define PPIB_OVERFLOW_SEND_SEND5_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND5_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND6 @Bit 6 : The status for tasks overflow at SUBSCRIBE_SEND[6]. */ + #define PPIB_OVERFLOW_SEND_SEND6_Pos (6UL) /*!< Position of SEND6 field. */ + #define PPIB_OVERFLOW_SEND_SEND6_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND6_Pos) /*!< Bit mask of SEND6 field. */ + #define PPIB_OVERFLOW_SEND_SEND6_Min (0x0UL) /*!< Min enumerator value of SEND6 field. */ + #define PPIB_OVERFLOW_SEND_SEND6_Max (0x1UL) /*!< Max enumerator value of SEND6 field. */ + #define PPIB_OVERFLOW_SEND_SEND6_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND6_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND7 @Bit 7 : The status for tasks overflow at SUBSCRIBE_SEND[7]. */ + #define PPIB_OVERFLOW_SEND_SEND7_Pos (7UL) /*!< Position of SEND7 field. */ + #define PPIB_OVERFLOW_SEND_SEND7_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND7_Pos) /*!< Bit mask of SEND7 field. */ + #define PPIB_OVERFLOW_SEND_SEND7_Min (0x0UL) /*!< Min enumerator value of SEND7 field. */ + #define PPIB_OVERFLOW_SEND_SEND7_Max (0x1UL) /*!< Max enumerator value of SEND7 field. */ + #define PPIB_OVERFLOW_SEND_SEND7_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND7_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND8 @Bit 8 : The status for tasks overflow at SUBSCRIBE_SEND[8]. */ + #define PPIB_OVERFLOW_SEND_SEND8_Pos (8UL) /*!< Position of SEND8 field. */ + #define PPIB_OVERFLOW_SEND_SEND8_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND8_Pos) /*!< Bit mask of SEND8 field. */ + #define PPIB_OVERFLOW_SEND_SEND8_Min (0x0UL) /*!< Min enumerator value of SEND8 field. */ + #define PPIB_OVERFLOW_SEND_SEND8_Max (0x1UL) /*!< Max enumerator value of SEND8 field. */ + #define PPIB_OVERFLOW_SEND_SEND8_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND8_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND9 @Bit 9 : The status for tasks overflow at SUBSCRIBE_SEND[9]. */ + #define PPIB_OVERFLOW_SEND_SEND9_Pos (9UL) /*!< Position of SEND9 field. */ + #define PPIB_OVERFLOW_SEND_SEND9_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND9_Pos) /*!< Bit mask of SEND9 field. */ + #define PPIB_OVERFLOW_SEND_SEND9_Min (0x0UL) /*!< Min enumerator value of SEND9 field. */ + #define PPIB_OVERFLOW_SEND_SEND9_Max (0x1UL) /*!< Max enumerator value of SEND9 field. */ + #define PPIB_OVERFLOW_SEND_SEND9_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND9_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND10 @Bit 10 : The status for tasks overflow at SUBSCRIBE_SEND[10]. */ + #define PPIB_OVERFLOW_SEND_SEND10_Pos (10UL) /*!< Position of SEND10 field. */ + #define PPIB_OVERFLOW_SEND_SEND10_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND10_Pos) /*!< Bit mask of SEND10 field. */ + #define PPIB_OVERFLOW_SEND_SEND10_Min (0x0UL) /*!< Min enumerator value of SEND10 field. */ + #define PPIB_OVERFLOW_SEND_SEND10_Max (0x1UL) /*!< Max enumerator value of SEND10 field. */ + #define PPIB_OVERFLOW_SEND_SEND10_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND10_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND11 @Bit 11 : The status for tasks overflow at SUBSCRIBE_SEND[11]. */ + #define PPIB_OVERFLOW_SEND_SEND11_Pos (11UL) /*!< Position of SEND11 field. */ + #define PPIB_OVERFLOW_SEND_SEND11_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND11_Pos) /*!< Bit mask of SEND11 field. */ + #define PPIB_OVERFLOW_SEND_SEND11_Min (0x0UL) /*!< Min enumerator value of SEND11 field. */ + #define PPIB_OVERFLOW_SEND_SEND11_Max (0x1UL) /*!< Max enumerator value of SEND11 field. */ + #define PPIB_OVERFLOW_SEND_SEND11_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND11_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND12 @Bit 12 : The status for tasks overflow at SUBSCRIBE_SEND[12]. */ + #define PPIB_OVERFLOW_SEND_SEND12_Pos (12UL) /*!< Position of SEND12 field. */ + #define PPIB_OVERFLOW_SEND_SEND12_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND12_Pos) /*!< Bit mask of SEND12 field. */ + #define PPIB_OVERFLOW_SEND_SEND12_Min (0x0UL) /*!< Min enumerator value of SEND12 field. */ + #define PPIB_OVERFLOW_SEND_SEND12_Max (0x1UL) /*!< Max enumerator value of SEND12 field. */ + #define PPIB_OVERFLOW_SEND_SEND12_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND12_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND13 @Bit 13 : The status for tasks overflow at SUBSCRIBE_SEND[13]. */ + #define PPIB_OVERFLOW_SEND_SEND13_Pos (13UL) /*!< Position of SEND13 field. */ + #define PPIB_OVERFLOW_SEND_SEND13_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND13_Pos) /*!< Bit mask of SEND13 field. */ + #define PPIB_OVERFLOW_SEND_SEND13_Min (0x0UL) /*!< Min enumerator value of SEND13 field. */ + #define PPIB_OVERFLOW_SEND_SEND13_Max (0x1UL) /*!< Max enumerator value of SEND13 field. */ + #define PPIB_OVERFLOW_SEND_SEND13_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND13_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND14 @Bit 14 : The status for tasks overflow at SUBSCRIBE_SEND[14]. */ + #define PPIB_OVERFLOW_SEND_SEND14_Pos (14UL) /*!< Position of SEND14 field. */ + #define PPIB_OVERFLOW_SEND_SEND14_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND14_Pos) /*!< Bit mask of SEND14 field. */ + #define PPIB_OVERFLOW_SEND_SEND14_Min (0x0UL) /*!< Min enumerator value of SEND14 field. */ + #define PPIB_OVERFLOW_SEND_SEND14_Max (0x1UL) /*!< Max enumerator value of SEND14 field. */ + #define PPIB_OVERFLOW_SEND_SEND14_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND14_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND15 @Bit 15 : The status for tasks overflow at SUBSCRIBE_SEND[15]. */ + #define PPIB_OVERFLOW_SEND_SEND15_Pos (15UL) /*!< Position of SEND15 field. */ + #define PPIB_OVERFLOW_SEND_SEND15_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND15_Pos) /*!< Bit mask of SEND15 field. */ + #define PPIB_OVERFLOW_SEND_SEND15_Min (0x0UL) /*!< Min enumerator value of SEND15 field. */ + #define PPIB_OVERFLOW_SEND_SEND15_Max (0x1UL) /*!< Max enumerator value of SEND15 field. */ + #define PPIB_OVERFLOW_SEND_SEND15_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND15_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND16 @Bit 16 : The status for tasks overflow at SUBSCRIBE_SEND[16]. */ + #define PPIB_OVERFLOW_SEND_SEND16_Pos (16UL) /*!< Position of SEND16 field. */ + #define PPIB_OVERFLOW_SEND_SEND16_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND16_Pos) /*!< Bit mask of SEND16 field. */ + #define PPIB_OVERFLOW_SEND_SEND16_Min (0x0UL) /*!< Min enumerator value of SEND16 field. */ + #define PPIB_OVERFLOW_SEND_SEND16_Max (0x1UL) /*!< Max enumerator value of SEND16 field. */ + #define PPIB_OVERFLOW_SEND_SEND16_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND16_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND17 @Bit 17 : The status for tasks overflow at SUBSCRIBE_SEND[17]. */ + #define PPIB_OVERFLOW_SEND_SEND17_Pos (17UL) /*!< Position of SEND17 field. */ + #define PPIB_OVERFLOW_SEND_SEND17_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND17_Pos) /*!< Bit mask of SEND17 field. */ + #define PPIB_OVERFLOW_SEND_SEND17_Min (0x0UL) /*!< Min enumerator value of SEND17 field. */ + #define PPIB_OVERFLOW_SEND_SEND17_Max (0x1UL) /*!< Max enumerator value of SEND17 field. */ + #define PPIB_OVERFLOW_SEND_SEND17_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND17_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND18 @Bit 18 : The status for tasks overflow at SUBSCRIBE_SEND[18]. */ + #define PPIB_OVERFLOW_SEND_SEND18_Pos (18UL) /*!< Position of SEND18 field. */ + #define PPIB_OVERFLOW_SEND_SEND18_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND18_Pos) /*!< Bit mask of SEND18 field. */ + #define PPIB_OVERFLOW_SEND_SEND18_Min (0x0UL) /*!< Min enumerator value of SEND18 field. */ + #define PPIB_OVERFLOW_SEND_SEND18_Max (0x1UL) /*!< Max enumerator value of SEND18 field. */ + #define PPIB_OVERFLOW_SEND_SEND18_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND18_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND19 @Bit 19 : The status for tasks overflow at SUBSCRIBE_SEND[19]. */ + #define PPIB_OVERFLOW_SEND_SEND19_Pos (19UL) /*!< Position of SEND19 field. */ + #define PPIB_OVERFLOW_SEND_SEND19_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND19_Pos) /*!< Bit mask of SEND19 field. */ + #define PPIB_OVERFLOW_SEND_SEND19_Min (0x0UL) /*!< Min enumerator value of SEND19 field. */ + #define PPIB_OVERFLOW_SEND_SEND19_Max (0x1UL) /*!< Max enumerator value of SEND19 field. */ + #define PPIB_OVERFLOW_SEND_SEND19_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND19_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND20 @Bit 20 : The status for tasks overflow at SUBSCRIBE_SEND[20]. */ + #define PPIB_OVERFLOW_SEND_SEND20_Pos (20UL) /*!< Position of SEND20 field. */ + #define PPIB_OVERFLOW_SEND_SEND20_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND20_Pos) /*!< Bit mask of SEND20 field. */ + #define PPIB_OVERFLOW_SEND_SEND20_Min (0x0UL) /*!< Min enumerator value of SEND20 field. */ + #define PPIB_OVERFLOW_SEND_SEND20_Max (0x1UL) /*!< Max enumerator value of SEND20 field. */ + #define PPIB_OVERFLOW_SEND_SEND20_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND20_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND21 @Bit 21 : The status for tasks overflow at SUBSCRIBE_SEND[21]. */ + #define PPIB_OVERFLOW_SEND_SEND21_Pos (21UL) /*!< Position of SEND21 field. */ + #define PPIB_OVERFLOW_SEND_SEND21_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND21_Pos) /*!< Bit mask of SEND21 field. */ + #define PPIB_OVERFLOW_SEND_SEND21_Min (0x0UL) /*!< Min enumerator value of SEND21 field. */ + #define PPIB_OVERFLOW_SEND_SEND21_Max (0x1UL) /*!< Max enumerator value of SEND21 field. */ + #define PPIB_OVERFLOW_SEND_SEND21_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND21_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND22 @Bit 22 : The status for tasks overflow at SUBSCRIBE_SEND[22]. */ + #define PPIB_OVERFLOW_SEND_SEND22_Pos (22UL) /*!< Position of SEND22 field. */ + #define PPIB_OVERFLOW_SEND_SEND22_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND22_Pos) /*!< Bit mask of SEND22 field. */ + #define PPIB_OVERFLOW_SEND_SEND22_Min (0x0UL) /*!< Min enumerator value of SEND22 field. */ + #define PPIB_OVERFLOW_SEND_SEND22_Max (0x1UL) /*!< Max enumerator value of SEND22 field. */ + #define PPIB_OVERFLOW_SEND_SEND22_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND22_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND23 @Bit 23 : The status for tasks overflow at SUBSCRIBE_SEND[23]. */ + #define PPIB_OVERFLOW_SEND_SEND23_Pos (23UL) /*!< Position of SEND23 field. */ + #define PPIB_OVERFLOW_SEND_SEND23_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND23_Pos) /*!< Bit mask of SEND23 field. */ + #define PPIB_OVERFLOW_SEND_SEND23_Min (0x0UL) /*!< Min enumerator value of SEND23 field. */ + #define PPIB_OVERFLOW_SEND_SEND23_Max (0x1UL) /*!< Max enumerator value of SEND23 field. */ + #define PPIB_OVERFLOW_SEND_SEND23_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND23_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND24 @Bit 24 : The status for tasks overflow at SUBSCRIBE_SEND[24]. */ + #define PPIB_OVERFLOW_SEND_SEND24_Pos (24UL) /*!< Position of SEND24 field. */ + #define PPIB_OVERFLOW_SEND_SEND24_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND24_Pos) /*!< Bit mask of SEND24 field. */ + #define PPIB_OVERFLOW_SEND_SEND24_Min (0x0UL) /*!< Min enumerator value of SEND24 field. */ + #define PPIB_OVERFLOW_SEND_SEND24_Max (0x1UL) /*!< Max enumerator value of SEND24 field. */ + #define PPIB_OVERFLOW_SEND_SEND24_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND24_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND25 @Bit 25 : The status for tasks overflow at SUBSCRIBE_SEND[25]. */ + #define PPIB_OVERFLOW_SEND_SEND25_Pos (25UL) /*!< Position of SEND25 field. */ + #define PPIB_OVERFLOW_SEND_SEND25_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND25_Pos) /*!< Bit mask of SEND25 field. */ + #define PPIB_OVERFLOW_SEND_SEND25_Min (0x0UL) /*!< Min enumerator value of SEND25 field. */ + #define PPIB_OVERFLOW_SEND_SEND25_Max (0x1UL) /*!< Max enumerator value of SEND25 field. */ + #define PPIB_OVERFLOW_SEND_SEND25_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND25_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND26 @Bit 26 : The status for tasks overflow at SUBSCRIBE_SEND[26]. */ + #define PPIB_OVERFLOW_SEND_SEND26_Pos (26UL) /*!< Position of SEND26 field. */ + #define PPIB_OVERFLOW_SEND_SEND26_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND26_Pos) /*!< Bit mask of SEND26 field. */ + #define PPIB_OVERFLOW_SEND_SEND26_Min (0x0UL) /*!< Min enumerator value of SEND26 field. */ + #define PPIB_OVERFLOW_SEND_SEND26_Max (0x1UL) /*!< Max enumerator value of SEND26 field. */ + #define PPIB_OVERFLOW_SEND_SEND26_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND26_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND27 @Bit 27 : The status for tasks overflow at SUBSCRIBE_SEND[27]. */ + #define PPIB_OVERFLOW_SEND_SEND27_Pos (27UL) /*!< Position of SEND27 field. */ + #define PPIB_OVERFLOW_SEND_SEND27_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND27_Pos) /*!< Bit mask of SEND27 field. */ + #define PPIB_OVERFLOW_SEND_SEND27_Min (0x0UL) /*!< Min enumerator value of SEND27 field. */ + #define PPIB_OVERFLOW_SEND_SEND27_Max (0x1UL) /*!< Max enumerator value of SEND27 field. */ + #define PPIB_OVERFLOW_SEND_SEND27_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND27_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND28 @Bit 28 : The status for tasks overflow at SUBSCRIBE_SEND[28]. */ + #define PPIB_OVERFLOW_SEND_SEND28_Pos (28UL) /*!< Position of SEND28 field. */ + #define PPIB_OVERFLOW_SEND_SEND28_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND28_Pos) /*!< Bit mask of SEND28 field. */ + #define PPIB_OVERFLOW_SEND_SEND28_Min (0x0UL) /*!< Min enumerator value of SEND28 field. */ + #define PPIB_OVERFLOW_SEND_SEND28_Max (0x1UL) /*!< Max enumerator value of SEND28 field. */ + #define PPIB_OVERFLOW_SEND_SEND28_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND28_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND29 @Bit 29 : The status for tasks overflow at SUBSCRIBE_SEND[29]. */ + #define PPIB_OVERFLOW_SEND_SEND29_Pos (29UL) /*!< Position of SEND29 field. */ + #define PPIB_OVERFLOW_SEND_SEND29_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND29_Pos) /*!< Bit mask of SEND29 field. */ + #define PPIB_OVERFLOW_SEND_SEND29_Min (0x0UL) /*!< Min enumerator value of SEND29 field. */ + #define PPIB_OVERFLOW_SEND_SEND29_Max (0x1UL) /*!< Max enumerator value of SEND29 field. */ + #define PPIB_OVERFLOW_SEND_SEND29_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND29_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND30 @Bit 30 : The status for tasks overflow at SUBSCRIBE_SEND[30]. */ + #define PPIB_OVERFLOW_SEND_SEND30_Pos (30UL) /*!< Position of SEND30 field. */ + #define PPIB_OVERFLOW_SEND_SEND30_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND30_Pos) /*!< Bit mask of SEND30 field. */ + #define PPIB_OVERFLOW_SEND_SEND30_Min (0x0UL) /*!< Min enumerator value of SEND30 field. */ + #define PPIB_OVERFLOW_SEND_SEND30_Max (0x1UL) /*!< Max enumerator value of SEND30 field. */ + #define PPIB_OVERFLOW_SEND_SEND30_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND30_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND31 @Bit 31 : The status for tasks overflow at SUBSCRIBE_SEND[31]. */ + #define PPIB_OVERFLOW_SEND_SEND31_Pos (31UL) /*!< Position of SEND31 field. */ + #define PPIB_OVERFLOW_SEND_SEND31_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND31_Pos) /*!< Bit mask of SEND31 field. */ + #define PPIB_OVERFLOW_SEND_SEND31_Min (0x0UL) /*!< Min enumerator value of SEND31 field. */ + #define PPIB_OVERFLOW_SEND_SEND31_Max (0x1UL) /*!< Max enumerator value of SEND31 field. */ + #define PPIB_OVERFLOW_SEND_SEND31_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND31_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + + +/* ======================================================= Struct PPIB ======================================================= */ +/** + * @brief PPIB APB registers + */ + typedef struct { /*!< PPIB Structure */ + __OM uint32_t TASKS_SEND[32]; /*!< (@ 0x00000000) This task is unused, but the PPIB provides the + SUBSCRIBE task to connect SEND [n] task.*/ + __IOM uint32_t SUBSCRIBE_SEND[32]; /*!< (@ 0x00000080) Subscribe configuration for task SEND[n] */ + __IOM uint32_t EVENTS_RECEIVE[32]; /*!< (@ 0x00000100) This event is unused, but the PPIB provides the PUBLISH + event to connect RECEIVE [n] event.*/ + __IOM uint32_t PUBLISH_RECEIVE[32]; /*!< (@ 0x00000180) Publish configuration for event RECEIVE[n] */ + __IM uint32_t RESERVED[128]; + __IOM NRF_PPIB_OVERFLOW_Type OVERFLOW; /*!< (@ 0x00000400) (unspecified) */ + } NRF_PPIB_Type; /*!< Size = 1028 (0x404) */ + +/* PPIB_TASKS_SEND: This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. */ + #define PPIB_TASKS_SEND_MaxCount (32UL) /*!< Max size of TASKS_SEND[32] array. */ + #define PPIB_TASKS_SEND_MaxIndex (31UL) /*!< Max index of TASKS_SEND[32] array. */ + #define PPIB_TASKS_SEND_MinIndex (0UL) /*!< Min index of TASKS_SEND[32] array. */ + #define PPIB_TASKS_SEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SEND[32] register. */ + +/* TASKS_SEND @Bit 0 : This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. */ + #define PPIB_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */ + #define PPIB_TASKS_SEND_TASKS_SEND_Msk (0x1UL << PPIB_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */ + #define PPIB_TASKS_SEND_TASKS_SEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SEND field. */ + #define PPIB_TASKS_SEND_TASKS_SEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SEND field. */ + #define PPIB_TASKS_SEND_TASKS_SEND_Trigger (0x1UL) /*!< Trigger task */ + + +/* PPIB_SUBSCRIBE_SEND: Subscribe configuration for task SEND[n] */ + #define PPIB_SUBSCRIBE_SEND_MaxCount (32UL) /*!< Max size of SUBSCRIBE_SEND[32] array. */ + #define PPIB_SUBSCRIBE_SEND_MaxIndex (31UL) /*!< Max index of SUBSCRIBE_SEND[32] array. */ + #define PPIB_SUBSCRIBE_SEND_MinIndex (0UL) /*!< Min index of SUBSCRIBE_SEND[32] array. */ + #define PPIB_SUBSCRIBE_SEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SEND[32] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SEND[n] will subscribe to */ + #define PPIB_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PPIB_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << PPIB_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PPIB_SUBSCRIBE_SEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PPIB_SUBSCRIBE_SEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PPIB_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define PPIB_SUBSCRIBE_SEND_EN_Msk (0x1UL << PPIB_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */ + #define PPIB_SUBSCRIBE_SEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PPIB_SUBSCRIBE_SEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PPIB_SUBSCRIBE_SEND_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PPIB_SUBSCRIBE_SEND_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PPIB_EVENTS_RECEIVE: This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. */ + #define PPIB_EVENTS_RECEIVE_MaxCount (32UL) /*!< Max size of EVENTS_RECEIVE[32] array. */ + #define PPIB_EVENTS_RECEIVE_MaxIndex (31UL) /*!< Max index of EVENTS_RECEIVE[32] array. */ + #define PPIB_EVENTS_RECEIVE_MinIndex (0UL) /*!< Min index of EVENTS_RECEIVE[32] array. */ + #define PPIB_EVENTS_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RECEIVE[32] register. */ + +/* EVENTS_RECEIVE @Bit 0 : This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. */ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of + EVENTS_RECEIVE field.*/ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Min (0x0UL) /*!< Min enumerator value of EVENTS_RECEIVE field. */ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Max (0x1UL) /*!< Max enumerator value of EVENTS_RECEIVE field. */ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0x0UL) /*!< Event not generated */ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (0x1UL) /*!< Event generated */ + + +/* PPIB_PUBLISH_RECEIVE: Publish configuration for event RECEIVE[n] */ + #define PPIB_PUBLISH_RECEIVE_MaxCount (32UL) /*!< Max size of PUBLISH_RECEIVE[32] array. */ + #define PPIB_PUBLISH_RECEIVE_MaxIndex (31UL) /*!< Max index of PUBLISH_RECEIVE[32] array. */ + #define PPIB_PUBLISH_RECEIVE_MinIndex (0UL) /*!< Min index of PUBLISH_RECEIVE[32] array. */ + #define PPIB_PUBLISH_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RECEIVE[32] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RECEIVE[n] will publish to */ + #define PPIB_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PPIB_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << PPIB_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PPIB_PUBLISH_RECEIVE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PPIB_PUBLISH_RECEIVE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PPIB_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */ + #define PPIB_PUBLISH_RECEIVE_EN_Msk (0x1UL << PPIB_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */ + #define PPIB_PUBLISH_RECEIVE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PPIB_PUBLISH_RECEIVE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PPIB_PUBLISH_RECEIVE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PPIB_PUBLISH_RECEIVE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct PWM_TASKS_DMA_SEQ ================================================= */ +/** + * @brief SEQ [PWM_TASKS_DMA_SEQ] Peripheral tasks. + */ +typedef struct { + __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See + peripheral description for operation using easyDMA.*/ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ +} NRF_PWM_TASKS_DMA_SEQ_Type; /*!< Size = 8 (0x008) */ + #define PWM_TASKS_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_TASKS_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_TASKS_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_TASKS_DMA_SEQ_START: Starts operation using easyDMA to load the values. See peripheral description for operation using + easyDMA. */ + + #define PWM_TASKS_DMA_SEQ_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */ + #define PWM_TASKS_DMA_SEQ_START_START_Pos (0UL) /*!< Position of START field. */ + #define PWM_TASKS_DMA_SEQ_START_START_Msk (0x1UL << PWM_TASKS_DMA_SEQ_START_START_Pos) /*!< Bit mask of START field. */ + #define PWM_TASKS_DMA_SEQ_START_START_Min (0x1UL) /*!< Min enumerator value of START field. */ + #define PWM_TASKS_DMA_SEQ_START_START_Max (0x1UL) /*!< Max enumerator value of START field. */ + #define PWM_TASKS_DMA_SEQ_START_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* PWM_TASKS_DMA_SEQ_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define PWM_TASKS_DMA_SEQ_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Msk (0x1UL << PWM_TASKS_DMA_SEQ_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================== Struct PWM_TASKS_DMA =================================================== */ +/** + * @brief TASKS_DMA [PWM_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __OM NRF_PWM_TASKS_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Peripheral tasks. */ +} NRF_PWM_TASKS_DMA_Type; /*!< Size = 16 (0x010) */ + + +/* ============================================== Struct PWM_SUBSCRIBE_DMA_SEQ =============================================== */ +/** + * @brief SEQ [PWM_SUBSCRIBE_DMA_SEQ] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ +} NRF_PWM_SUBSCRIBE_DMA_SEQ_Type; /*!< Size = 8 (0x008) */ + #define PWM_SUBSCRIBE_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_SUBSCRIBE_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_SUBSCRIBE_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_SUBSCRIBE_DMA_SEQ_START: Subscribe configuration for task START */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Msk (0x1UL << PWM_SUBSCRIBE_DMA_SEQ_START_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PWM_SUBSCRIBE_DMA_SEQ_STOP: Subscribe configuration for task STOP */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ================================================ Struct PWM_SUBSCRIBE_DMA ================================================= */ +/** + * @brief SUBSCRIBE_DMA [PWM_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IOM NRF_PWM_SUBSCRIBE_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Subscribe configuration for tasks */ +} NRF_PWM_SUBSCRIBE_DMA_Type; /*!< Size = 16 (0x010) */ + + +/* ================================================ Struct PWM_EVENTS_DMA_SEQ ================================================ */ +/** + * @brief SEQ [PWM_EVENTS_DMA_SEQ] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_PWM_EVENTS_DMA_SEQ_Type; /*!< Size = 12 (0x00C) */ + #define PWM_EVENTS_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_EVENTS_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_EVENTS_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_EVENTS_DMA_SEQ_END: Generated after all MAXCNT bytes have been transferred */ + #define PWM_EVENTS_DMA_SEQ_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define PWM_EVENTS_DMA_SEQ_END_END_Pos (0UL) /*!< Position of END field. */ + #define PWM_EVENTS_DMA_SEQ_END_END_Msk (0x1UL << PWM_EVENTS_DMA_SEQ_END_END_Pos) /*!< Bit mask of END field. */ + #define PWM_EVENTS_DMA_SEQ_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define PWM_EVENTS_DMA_SEQ_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define PWM_EVENTS_DMA_SEQ_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_DMA_SEQ_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_DMA_SEQ_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define PWM_EVENTS_DMA_SEQ_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define PWM_EVENTS_DMA_SEQ_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define PWM_EVENTS_DMA_SEQ_READY_READY_Msk (0x1UL << PWM_EVENTS_DMA_SEQ_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define PWM_EVENTS_DMA_SEQ_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define PWM_EVENTS_DMA_SEQ_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define PWM_EVENTS_DMA_SEQ_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_DMA_SEQ_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_DMA_SEQ_BUSERROR: An error occured during the bus transfer. */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Msk (0x1UL << PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================== Struct PWM_EVENTS_DMA ================================================== */ +/** + * @brief EVENTS_DMA [PWM_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_PWM_EVENTS_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Peripheral events. */ +} NRF_PWM_EVENTS_DMA_Type; /*!< Size = 24 (0x018) */ + + +/* =============================================== Struct PWM_PUBLISH_DMA_SEQ ================================================ */ +/** + * @brief SEQ [PWM_PUBLISH_DMA_SEQ] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_PWM_PUBLISH_DMA_SEQ_Type; /*!< Size = 12 (0x00C) */ + #define PWM_PUBLISH_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_PUBLISH_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_PUBLISH_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_PUBLISH_DMA_SEQ_END: Publish configuration for event END */ + #define PWM_PUBLISH_DMA_SEQ_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Msk (0xFFUL << PWM_PUBLISH_DMA_SEQ_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Msk (0x1UL << PWM_PUBLISH_DMA_SEQ_END_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_DMA_SEQ_READY: Publish configuration for event READY */ + #define PWM_PUBLISH_DMA_SEQ_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Msk (0xFFUL << PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Msk (0x1UL << PWM_PUBLISH_DMA_SEQ_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_DMA_SEQ_BUSERROR: Publish configuration for event BUSERROR */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Msk (0xFFUL << PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Msk (0x1UL << PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================= Struct PWM_PUBLISH_DMA ================================================== */ +/** + * @brief PUBLISH_DMA [PWM_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_PWM_PUBLISH_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Publish configuration for events */ +} NRF_PWM_PUBLISH_DMA_Type; /*!< Size = 24 (0x018) */ + + +/* ===================================================== Struct PWM_SEQ ====================================================== */ +/** + * @brief SEQ [PWM_SEQ] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Number of additional PWM periods between samples loaded + into compare register*/ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Time added after the sequence */ + __IM uint32_t RESERVED1[4]; +} NRF_PWM_SEQ_Type; /*!< Size = 32 (0x020) */ + #define PWM_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_SEQ_REFRESH: Number of additional PWM periods between samples loaded into compare register */ + #define PWM_SEQ_REFRESH_ResetValue (0x00000001UL) /*!< Reset value of REFRESH register. */ + +/* CNT @Bits 0..23 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM + periods) */ + + #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ + #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ + #define PWM_SEQ_REFRESH_CNT_Min (0x000000UL) /*!< Min enumerator value of CNT field. */ + #define PWM_SEQ_REFRESH_CNT_Max (0x000000UL) /*!< Max enumerator value of CNT field. */ + #define PWM_SEQ_REFRESH_CNT_Continuous (0x000000UL) /*!< Update every PWM period */ + + +/* PWM_SEQ_ENDDELAY: Time added after the sequence */ + #define PWM_SEQ_ENDDELAY_ResetValue (0x00000000UL) /*!< Reset value of ENDDELAY register. */ + +/* CNT @Bits 0..23 : Time added after the sequence in PWM periods */ + #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ + #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + + + +/* ===================================================== Struct PWM_PSEL ===================================================== */ +/** + * @brief PSEL [PWM_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Output pin select for PWM channel n */ +} NRF_PWM_PSEL_Type; /*!< Size = 16 (0x010) */ + +/* PWM_PSEL_OUT: Output pin select for PWM channel n */ + #define PWM_PSEL_OUT_MaxCount (4UL) /*!< Max size of OUT[4] array. */ + #define PWM_PSEL_OUT_MaxIndex (3UL) /*!< Max index of OUT[4] array. */ + #define PWM_PSEL_OUT_MinIndex (0UL) /*!< Min index of OUT[4] array. */ + #define PWM_PSEL_OUT_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OUT[4] register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + #define PWM_PSEL_OUT_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define PWM_PSEL_OUT_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define PWM_PSEL_OUT_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define PWM_PSEL_OUT_PORT_Msk (0x7UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */ + #define PWM_PSEL_OUT_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define PWM_PSEL_OUT_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define PWM_PSEL_OUT_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define PWM_PSEL_OUT_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define PWM_PSEL_OUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define PWM_PSEL_OUT_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* =================================================== Struct PWM_DMA_SEQ ==================================================== */ +/** + * @brief SEQ [PWM_DMA_SEQ] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_PWM_DMA_SEQ_Type; /*!< Size = 36 (0x024) */ + #define PWM_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_DMA_SEQ_PTR: RAM buffer start address */ + #define PWM_DMA_SEQ_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define PWM_DMA_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define PWM_DMA_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_DMA_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* PWM_DMA_SEQ_MAXCNT: Maximum number of bytes in channel buffer */ + #define PWM_DMA_SEQ_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Msk (0x7FFFUL << PWM_DMA_SEQ_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* PWM_DMA_SEQ_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. */ + #define PWM_DMA_SEQ_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Msk (0x7FFFUL << PWM_DMA_SEQ_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* PWM_DMA_SEQ_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define PWM_DMA_SEQ_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* PWM_DMA_SEQ_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* PWM_DMA_SEQ_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define PWM_DMA_SEQ_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define PWM_DMA_SEQ_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define PWM_DMA_SEQ_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << PWM_DMA_SEQ_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ===================================================== Struct PWM_DMA ====================================================== */ +/** + * @brief DMA [PWM_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_PWM_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_PWM_DMA_Type; /*!< Size = 72 (0x048) */ + +/* ======================================================= Struct PWM ======================================================== */ +/** + * @brief Pulse width modulation unit + */ + typedef struct { /*!< PWM Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at the end + of current PWM period, and stops sequence playback*/ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000008) Steps by one value in the current sequence on all + enabled channels if DECODER.MODE=NextStep. Does not + cause PWM generation to start if not running.*/ + __IM uint32_t RESERVED1; + __OM NRF_PWM_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000010) Peripheral tasks. */ + __IM uint32_t RESERVED2[25]; + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000088) Subscribe configuration for task NEXTSTEP */ + __IM uint32_t RESERVED3; + __IOM NRF_PWM_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x00000090) Subscribe configuration for tasks */ + __IM uint32_t RESERVED4[25]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses are no + longer generated*/ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) First PWM period started on sequence n */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Emitted at end of every sequence n, when last value + from RAM has been applied to wave counter*/ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount of + times defined in LOOP.CNT*/ + __IOM uint32_t EVENTS_RAMUNDERFLOW; /*!< (@ 0x00000120) Emitted when retrieving from RAM does not complete in + time for the PWM module*/ + __IOM NRF_PWM_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x00000124) Peripheral events. */ + __IOM uint32_t EVENTS_COMPAREMATCH[4]; /*!< (@ 0x0000013C) This event is generated when the compare matches for + the compare channel [n].*/ + __IM uint32_t RESERVED5[14]; + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Publish configuration for event SEQSTARTED[n] */ + __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Publish configuration for event SEQEND[n] */ + __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ + __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ + __IOM uint32_t PUBLISH_RAMUNDERFLOW; /*!< (@ 0x000001A0) Publish configuration for event RAMUNDERFLOW */ + __IOM NRF_PWM_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001A4) Publish configuration for events */ + __IOM uint32_t PUBLISH_COMPAREMATCH[4]; /*!< (@ 0x000001BC) Publish configuration for event COMPAREMATCH[n] */ + __IM uint32_t RESERVED6[13]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED7[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED8[124]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ + __IOM uint32_t IDLEOUT; /*!< (@ 0x00000518) Configure the output value on the PWM channel during + idle*/ + __IM uint32_t RESERVED9; + __IOM NRF_PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) (unspecified) */ + __IOM NRF_PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) (unspecified) */ + __IM uint32_t RESERVED10[100]; + __IOM NRF_PWM_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_PWM_Type; /*!< Size = 1864 (0x748) */ + +/* PWM_TASKS_STOP: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ + #define PWM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + */ + + #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define PWM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define PWM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define PWM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* PWM_TASKS_NEXTSTEP: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not + cause PWM generation to start if not running. */ + + #define PWM_TASKS_NEXTSTEP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_NEXTSTEP register. */ + +/* TASKS_NEXTSTEP @Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not + cause PWM generation to start if not running. */ + + #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ + #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP + field.*/ + #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Min (0x1UL) /*!< Min enumerator value of TASKS_NEXTSTEP field. */ + #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Max (0x1UL) /*!< Max enumerator value of TASKS_NEXTSTEP field. */ + #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (0x1UL) /*!< Trigger task */ + + +/* PWM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define PWM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PWM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PWM_SUBSCRIBE_NEXTSTEP: Subscribe configuration for task NEXTSTEP */ + #define PWM_SUBSCRIBE_NEXTSTEP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_NEXTSTEP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task NEXTSTEP will subscribe to */ + #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PWM_EVENTS_STOPPED: Response to STOP task, emitted when PWM pulses are no longer generated */ + #define PWM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED + field.*/ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_SEQSTARTED: First PWM period started on sequence n */ + #define PWM_EVENTS_SEQSTARTED_MaxCount (2UL) /*!< Max size of EVENTS_SEQSTARTED[2] array. */ + #define PWM_EVENTS_SEQSTARTED_MaxIndex (1UL) /*!< Max index of EVENTS_SEQSTARTED[2] array. */ + #define PWM_EVENTS_SEQSTARTED_MinIndex (0UL) /*!< Min index of EVENTS_SEQSTARTED[2] array. */ + #define PWM_EVENTS_SEQSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SEQSTARTED[2] register. */ + +/* EVENTS_SEQSTARTED @Bit 0 : First PWM period started on sequence n */ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of + EVENTS_SEQSTARTED field.*/ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_SEQSTARTED field. */ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_SEQSTARTED field. */ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_SEQEND: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ + #define PWM_EVENTS_SEQEND_MaxCount (2UL) /*!< Max size of EVENTS_SEQEND[2] array. */ + #define PWM_EVENTS_SEQEND_MaxIndex (1UL) /*!< Max index of EVENTS_SEQEND[2] array. */ + #define PWM_EVENTS_SEQEND_MinIndex (0UL) /*!< Min index of EVENTS_SEQEND[2] array. */ + #define PWM_EVENTS_SEQEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SEQEND[2] register. */ + +/* EVENTS_SEQEND @Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND + field.*/ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_SEQEND field. */ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_SEQEND field. */ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_PWMPERIODEND: Emitted at the end of each PWM period */ + #define PWM_EVENTS_PWMPERIODEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PWMPERIODEND register. */ + +/* EVENTS_PWMPERIODEND @Bit 0 : Emitted at the end of each PWM period */ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit + mask of EVENTS_PWMPERIODEND field.*/ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_PWMPERIODEND field. */ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_PWMPERIODEND field. */ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_LOOPSDONE: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ + #define PWM_EVENTS_LOOPSDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LOOPSDONE register. */ + +/* EVENTS_LOOPSDONE @Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of + EVENTS_LOOPSDONE field.*/ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_LOOPSDONE field. */ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_LOOPSDONE field. */ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_RAMUNDERFLOW: Emitted when retrieving from RAM does not complete in time for the PWM module */ + #define PWM_EVENTS_RAMUNDERFLOW_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RAMUNDERFLOW register. */ + +/* EVENTS_RAMUNDERFLOW @Bit 0 : Emitted when retrieving from RAM does not complete in time for the PWM module */ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Pos (0UL) /*!< Position of EVENTS_RAMUNDERFLOW field. */ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Msk (0x1UL << PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Pos) /*!< Bit + mask of EVENTS_RAMUNDERFLOW field.*/ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of EVENTS_RAMUNDERFLOW field. */ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of EVENTS_RAMUNDERFLOW field. */ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_COMPAREMATCH: This event is generated when the compare matches for the compare channel [n]. */ + #define PWM_EVENTS_COMPAREMATCH_MaxCount (4UL) /*!< Max size of EVENTS_COMPAREMATCH[4] array. */ + #define PWM_EVENTS_COMPAREMATCH_MaxIndex (3UL) /*!< Max index of EVENTS_COMPAREMATCH[4] array. */ + #define PWM_EVENTS_COMPAREMATCH_MinIndex (0UL) /*!< Min index of EVENTS_COMPAREMATCH[4] array. */ + #define PWM_EVENTS_COMPAREMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPAREMATCH[4] register. */ + +/* EVENTS_COMPAREMATCH @Bit 0 : This event is generated when the compare matches for the compare channel [n]. */ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Pos (0UL) /*!< Position of EVENTS_COMPAREMATCH field. */ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Msk (0x1UL << PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Pos) /*!< Bit + mask of EVENTS_COMPAREMATCH field.*/ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPAREMATCH field. */ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPAREMATCH field. */ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define PWM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_SEQSTARTED: Publish configuration for event SEQSTARTED[n] */ + #define PWM_PUBLISH_SEQSTARTED_MaxCount (2UL) /*!< Max size of PUBLISH_SEQSTARTED[2] array. */ + #define PWM_PUBLISH_SEQSTARTED_MaxIndex (1UL) /*!< Max index of PUBLISH_SEQSTARTED[2] array. */ + #define PWM_PUBLISH_SEQSTARTED_MinIndex (0UL) /*!< Min index of PUBLISH_SEQSTARTED[2] array. */ + #define PWM_PUBLISH_SEQSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SEQSTARTED[2] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SEQSTARTED[n] will publish to */ + #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_SEQSTARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_SEQSTARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_SEQSTARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_SEQSTARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_SEQEND: Publish configuration for event SEQEND[n] */ + #define PWM_PUBLISH_SEQEND_MaxCount (2UL) /*!< Max size of PUBLISH_SEQEND[2] array. */ + #define PWM_PUBLISH_SEQEND_MaxIndex (1UL) /*!< Max index of PUBLISH_SEQEND[2] array. */ + #define PWM_PUBLISH_SEQEND_MinIndex (0UL) /*!< Min index of PUBLISH_SEQEND[2] array. */ + #define PWM_PUBLISH_SEQEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SEQEND[2] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SEQEND[n] will publish to */ + #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_SEQEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_SEQEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_SEQEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_SEQEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_SEQEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_SEQEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_PWMPERIODEND: Publish configuration for event PWMPERIODEND */ + #define PWM_PUBLISH_PWMPERIODEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PWMPERIODEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PWMPERIODEND will publish to */ + #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_LOOPSDONE: Publish configuration for event LOOPSDONE */ + #define PWM_PUBLISH_LOOPSDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LOOPSDONE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event LOOPSDONE will publish to */ + #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_LOOPSDONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_LOOPSDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_LOOPSDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_LOOPSDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_RAMUNDERFLOW: Publish configuration for event RAMUNDERFLOW */ + #define PWM_PUBLISH_RAMUNDERFLOW_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RAMUNDERFLOW register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RAMUNDERFLOW will publish to */ + #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Msk (0xFFUL << PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Msk (0x1UL << PWM_PUBLISH_RAMUNDERFLOW_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_COMPAREMATCH: Publish configuration for event COMPAREMATCH[n] */ + #define PWM_PUBLISH_COMPAREMATCH_MaxCount (4UL) /*!< Max size of PUBLISH_COMPAREMATCH[4] array. */ + #define PWM_PUBLISH_COMPAREMATCH_MaxIndex (3UL) /*!< Max index of PUBLISH_COMPAREMATCH[4] array. */ + #define PWM_PUBLISH_COMPAREMATCH_MinIndex (0UL) /*!< Min index of PUBLISH_COMPAREMATCH[4] array. */ + #define PWM_PUBLISH_COMPAREMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPAREMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event COMPAREMATCH[n] will publish to */ + #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Msk (0xFFUL << PWM_PUBLISH_COMPAREMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Msk (0x1UL << PWM_PUBLISH_COMPAREMATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_SHORTS: Shortcuts between local events and tasks */ + #define PWM_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* SEQEND0_STOP @Bit 0 : Shortcut between event SEQEND[n] and task STOP */ + #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ + #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ + #define PWM_SHORTS_SEQEND0_STOP_Min (0x0UL) /*!< Min enumerator value of SEQEND0_STOP field. */ + #define PWM_SHORTS_SEQEND0_STOP_Max (0x1UL) /*!< Max enumerator value of SEQEND0_STOP field. */ + #define PWM_SHORTS_SEQEND0_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_SEQEND0_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* SEQEND1_STOP @Bit 1 : Shortcut between event SEQEND[n] and task STOP */ + #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ + #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ + #define PWM_SHORTS_SEQEND1_STOP_Min (0x0UL) /*!< Min enumerator value of SEQEND1_STOP field. */ + #define PWM_SHORTS_SEQEND1_STOP_Max (0x1UL) /*!< Max enumerator value of SEQEND1_STOP field. */ + #define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LOOPSDONE_DMA_SEQ0_START @Bit 2 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos (2UL) /*!< Position of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos) /*!< Bit mask of + LOOPSDONE_DMA_SEQ0_START field.*/ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LOOPSDONE_DMA_SEQ1_START @Bit 3 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos (3UL) /*!< Position of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos) /*!< Bit mask of + LOOPSDONE_DMA_SEQ1_START field.*/ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LOOPSDONE_STOP @Bit 4 : Shortcut between event LOOPSDONE and task STOP */ + #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ + #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ + #define PWM_SHORTS_LOOPSDONE_STOP_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_STOP field. */ + #define PWM_SHORTS_LOOPSDONE_STOP_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_STOP field. */ + #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RAMUNDERFLOW_STOP @Bit 5 : Shortcut between event RAMUNDERFLOW and task STOP */ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Pos (5UL) /*!< Position of RAMUNDERFLOW_STOP field. */ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Msk (0x1UL << PWM_SHORTS_RAMUNDERFLOW_STOP_Pos) /*!< Bit mask of RAMUNDERFLOW_STOP + field.*/ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Min (0x0UL) /*!< Min enumerator value of RAMUNDERFLOW_STOP field. */ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Max (0x1UL) /*!< Max enumerator value of RAMUNDERFLOW_STOP field. */ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_SEQ0_BUSERROR_STOP @Bit 6 : Shortcut between event DMA.SEQ[n].BUSERROR and task STOP */ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Pos (6UL) /*!< Position of DMA_SEQ0_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Msk (0x1UL << PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Pos) /*!< Bit mask of + DMA_SEQ0_BUSERROR_STOP field.*/ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_SEQ0_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_SEQ0_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_SEQ1_BUSERROR_STOP @Bit 7 : Shortcut between event DMA.SEQ[n].BUSERROR and task STOP */ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Pos (7UL) /*!< Position of DMA_SEQ1_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Msk (0x1UL << PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Pos) /*!< Bit mask of + DMA_SEQ1_BUSERROR_STOP field.*/ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_SEQ1_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_SEQ1_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* PWM_INTEN: Enable or disable interrupt */ + #define PWM_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */ + #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PWM_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PWM_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PWM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* SEQSTARTED0 @Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ + #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ + #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ + #define PWM_INTEN_SEQSTARTED0_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED0 field. */ + #define PWM_INTEN_SEQSTARTED0_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED0 field. */ + #define PWM_INTEN_SEQSTARTED0_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_SEQSTARTED0_Enabled (0x1UL) /*!< Enable */ + +/* SEQSTARTED1 @Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ + #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ + #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ + #define PWM_INTEN_SEQSTARTED1_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED1 field. */ + #define PWM_INTEN_SEQSTARTED1_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED1 field. */ + #define PWM_INTEN_SEQSTARTED1_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_SEQSTARTED1_Enabled (0x1UL) /*!< Enable */ + +/* SEQEND0 @Bit 4 : Enable or disable interrupt for event SEQEND[0] */ + #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ + #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ + #define PWM_INTEN_SEQEND0_Min (0x0UL) /*!< Min enumerator value of SEQEND0 field. */ + #define PWM_INTEN_SEQEND0_Max (0x1UL) /*!< Max enumerator value of SEQEND0 field. */ + #define PWM_INTEN_SEQEND0_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_SEQEND0_Enabled (0x1UL) /*!< Enable */ + +/* SEQEND1 @Bit 5 : Enable or disable interrupt for event SEQEND[1] */ + #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ + #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ + #define PWM_INTEN_SEQEND1_Min (0x0UL) /*!< Min enumerator value of SEQEND1 field. */ + #define PWM_INTEN_SEQEND1_Max (0x1UL) /*!< Max enumerator value of SEQEND1 field. */ + #define PWM_INTEN_SEQEND1_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_SEQEND1_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ + #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ + #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define PWM_INTEN_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define PWM_INTEN_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define PWM_INTEN_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + +/* LOOPSDONE @Bit 7 : Enable or disable interrupt for event LOOPSDONE */ + #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ + #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ + #define PWM_INTEN_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE field. */ + #define PWM_INTEN_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE field. */ + #define PWM_INTEN_LOOPSDONE_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_LOOPSDONE_Enabled (0x1UL) /*!< Enable */ + +/* RAMUNDERFLOW @Bit 8 : Enable or disable interrupt for event RAMUNDERFLOW */ + #define PWM_INTEN_RAMUNDERFLOW_Pos (8UL) /*!< Position of RAMUNDERFLOW field. */ + #define PWM_INTEN_RAMUNDERFLOW_Msk (0x1UL << PWM_INTEN_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field. */ + #define PWM_INTEN_RAMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTEN_RAMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTEN_RAMUNDERFLOW_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_RAMUNDERFLOW_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ0END @Bit 9 : Enable or disable interrupt for event DMASEQ0END */ + #define PWM_INTEN_DMASEQ0END_Pos (9UL) /*!< Position of DMASEQ0END field. */ + #define PWM_INTEN_DMASEQ0END_Msk (0x1UL << PWM_INTEN_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field. */ + #define PWM_INTEN_DMASEQ0END_Min (0x0UL) /*!< Min enumerator value of DMASEQ0END field. */ + #define PWM_INTEN_DMASEQ0END_Max (0x1UL) /*!< Max enumerator value of DMASEQ0END field. */ + #define PWM_INTEN_DMASEQ0END_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ0END_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ0READY @Bit 10 : Enable or disable interrupt for event DMASEQ0READY */ + #define PWM_INTEN_DMASEQ0READY_Pos (10UL) /*!< Position of DMASEQ0READY field. */ + #define PWM_INTEN_DMASEQ0READY_Msk (0x1UL << PWM_INTEN_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field. */ + #define PWM_INTEN_DMASEQ0READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ0READY field. */ + #define PWM_INTEN_DMASEQ0READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ0READY field. */ + #define PWM_INTEN_DMASEQ0READY_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ0READY_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ0BUSERROR @Bit 11 : Enable or disable interrupt for event DMASEQ0BUSERROR */ + #define PWM_INTEN_DMASEQ0BUSERROR_Pos (11UL) /*!< Position of DMASEQ0BUSERROR field. */ + #define PWM_INTEN_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTEN_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field. */ + #define PWM_INTEN_DMASEQ0BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTEN_DMASEQ0BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTEN_DMASEQ0BUSERROR_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ0BUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ1END @Bit 12 : Enable or disable interrupt for event DMASEQ1END */ + #define PWM_INTEN_DMASEQ1END_Pos (12UL) /*!< Position of DMASEQ1END field. */ + #define PWM_INTEN_DMASEQ1END_Msk (0x1UL << PWM_INTEN_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field. */ + #define PWM_INTEN_DMASEQ1END_Min (0x0UL) /*!< Min enumerator value of DMASEQ1END field. */ + #define PWM_INTEN_DMASEQ1END_Max (0x1UL) /*!< Max enumerator value of DMASEQ1END field. */ + #define PWM_INTEN_DMASEQ1END_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ1END_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ1READY @Bit 13 : Enable or disable interrupt for event DMASEQ1READY */ + #define PWM_INTEN_DMASEQ1READY_Pos (13UL) /*!< Position of DMASEQ1READY field. */ + #define PWM_INTEN_DMASEQ1READY_Msk (0x1UL << PWM_INTEN_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field. */ + #define PWM_INTEN_DMASEQ1READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ1READY field. */ + #define PWM_INTEN_DMASEQ1READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ1READY field. */ + #define PWM_INTEN_DMASEQ1READY_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ1READY_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ1BUSERROR @Bit 14 : Enable or disable interrupt for event DMASEQ1BUSERROR */ + #define PWM_INTEN_DMASEQ1BUSERROR_Pos (14UL) /*!< Position of DMASEQ1BUSERROR field. */ + #define PWM_INTEN_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTEN_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field. */ + #define PWM_INTEN_DMASEQ1BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTEN_DMASEQ1BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTEN_DMASEQ1BUSERROR_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ1BUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* COMPAREMATCH0 @Bit 15 : Enable or disable interrupt for event COMPAREMATCH[0] */ + #define PWM_INTEN_COMPAREMATCH0_Pos (15UL) /*!< Position of COMPAREMATCH0 field. */ + #define PWM_INTEN_COMPAREMATCH0_Msk (0x1UL << PWM_INTEN_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field. */ + #define PWM_INTEN_COMPAREMATCH0_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTEN_COMPAREMATCH0_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTEN_COMPAREMATCH0_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_COMPAREMATCH0_Enabled (0x1UL) /*!< Enable */ + +/* COMPAREMATCH1 @Bit 16 : Enable or disable interrupt for event COMPAREMATCH[1] */ + #define PWM_INTEN_COMPAREMATCH1_Pos (16UL) /*!< Position of COMPAREMATCH1 field. */ + #define PWM_INTEN_COMPAREMATCH1_Msk (0x1UL << PWM_INTEN_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field. */ + #define PWM_INTEN_COMPAREMATCH1_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTEN_COMPAREMATCH1_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTEN_COMPAREMATCH1_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_COMPAREMATCH1_Enabled (0x1UL) /*!< Enable */ + +/* COMPAREMATCH2 @Bit 17 : Enable or disable interrupt for event COMPAREMATCH[2] */ + #define PWM_INTEN_COMPAREMATCH2_Pos (17UL) /*!< Position of COMPAREMATCH2 field. */ + #define PWM_INTEN_COMPAREMATCH2_Msk (0x1UL << PWM_INTEN_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field. */ + #define PWM_INTEN_COMPAREMATCH2_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTEN_COMPAREMATCH2_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTEN_COMPAREMATCH2_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_COMPAREMATCH2_Enabled (0x1UL) /*!< Enable */ + +/* COMPAREMATCH3 @Bit 18 : Enable or disable interrupt for event COMPAREMATCH[3] */ + #define PWM_INTEN_COMPAREMATCH3_Pos (18UL) /*!< Position of COMPAREMATCH3 field. */ + #define PWM_INTEN_COMPAREMATCH3_Msk (0x1UL << PWM_INTEN_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field. */ + #define PWM_INTEN_COMPAREMATCH3_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTEN_COMPAREMATCH3_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTEN_COMPAREMATCH3_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_COMPAREMATCH3_Enabled (0x1UL) /*!< Enable */ + + +/* PWM_INTENSET: Enable interrupt */ + #define PWM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PWM_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PWM_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PWM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQSTARTED0 @Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ + #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ + #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ + #define PWM_INTENSET_SEQSTARTED0_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED0 field. */ + #define PWM_INTENSET_SEQSTARTED0_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED0 field. */ + #define PWM_INTENSET_SEQSTARTED0_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQSTARTED1 @Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ + #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ + #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ + #define PWM_INTENSET_SEQSTARTED1_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED1 field. */ + #define PWM_INTENSET_SEQSTARTED1_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED1 field. */ + #define PWM_INTENSET_SEQSTARTED1_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQEND0 @Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ + #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ + #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ + #define PWM_INTENSET_SEQEND0_Min (0x0UL) /*!< Min enumerator value of SEQEND0 field. */ + #define PWM_INTENSET_SEQEND0_Max (0x1UL) /*!< Max enumerator value of SEQEND0 field. */ + #define PWM_INTENSET_SEQEND0_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQEND1 @Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ + #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ + #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ + #define PWM_INTENSET_SEQEND1_Min (0x0UL) /*!< Min enumerator value of SEQEND1 field. */ + #define PWM_INTENSET_SEQEND1_Max (0x1UL) /*!< Max enumerator value of SEQEND1 field. */ + #define PWM_INTENSET_SEQEND1_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ + #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define PWM_INTENSET_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define PWM_INTENSET_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define PWM_INTENSET_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LOOPSDONE @Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ + #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ + #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ + #define PWM_INTENSET_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE field. */ + #define PWM_INTENSET_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE field. */ + #define PWM_INTENSET_LOOPSDONE_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RAMUNDERFLOW @Bit 8 : Write '1' to enable interrupt for event RAMUNDERFLOW */ + #define PWM_INTENSET_RAMUNDERFLOW_Pos (8UL) /*!< Position of RAMUNDERFLOW field. */ + #define PWM_INTENSET_RAMUNDERFLOW_Msk (0x1UL << PWM_INTENSET_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field. */ + #define PWM_INTENSET_RAMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTENSET_RAMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTENSET_RAMUNDERFLOW_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_RAMUNDERFLOW_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_RAMUNDERFLOW_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0END @Bit 9 : Write '1' to enable interrupt for event DMASEQ0END */ + #define PWM_INTENSET_DMASEQ0END_Pos (9UL) /*!< Position of DMASEQ0END field. */ + #define PWM_INTENSET_DMASEQ0END_Msk (0x1UL << PWM_INTENSET_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field. */ + #define PWM_INTENSET_DMASEQ0END_Min (0x0UL) /*!< Min enumerator value of DMASEQ0END field. */ + #define PWM_INTENSET_DMASEQ0END_Max (0x1UL) /*!< Max enumerator value of DMASEQ0END field. */ + #define PWM_INTENSET_DMASEQ0END_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ0END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ0END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0READY @Bit 10 : Write '1' to enable interrupt for event DMASEQ0READY */ + #define PWM_INTENSET_DMASEQ0READY_Pos (10UL) /*!< Position of DMASEQ0READY field. */ + #define PWM_INTENSET_DMASEQ0READY_Msk (0x1UL << PWM_INTENSET_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field. */ + #define PWM_INTENSET_DMASEQ0READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ0READY field. */ + #define PWM_INTENSET_DMASEQ0READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ0READY field. */ + #define PWM_INTENSET_DMASEQ0READY_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ0READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ0READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0BUSERROR @Bit 11 : Write '1' to enable interrupt for event DMASEQ0BUSERROR */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Pos (11UL) /*!< Position of DMASEQ0BUSERROR field. */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTENSET_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field. */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1END @Bit 12 : Write '1' to enable interrupt for event DMASEQ1END */ + #define PWM_INTENSET_DMASEQ1END_Pos (12UL) /*!< Position of DMASEQ1END field. */ + #define PWM_INTENSET_DMASEQ1END_Msk (0x1UL << PWM_INTENSET_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field. */ + #define PWM_INTENSET_DMASEQ1END_Min (0x0UL) /*!< Min enumerator value of DMASEQ1END field. */ + #define PWM_INTENSET_DMASEQ1END_Max (0x1UL) /*!< Max enumerator value of DMASEQ1END field. */ + #define PWM_INTENSET_DMASEQ1END_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ1END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ1END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1READY @Bit 13 : Write '1' to enable interrupt for event DMASEQ1READY */ + #define PWM_INTENSET_DMASEQ1READY_Pos (13UL) /*!< Position of DMASEQ1READY field. */ + #define PWM_INTENSET_DMASEQ1READY_Msk (0x1UL << PWM_INTENSET_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field. */ + #define PWM_INTENSET_DMASEQ1READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ1READY field. */ + #define PWM_INTENSET_DMASEQ1READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ1READY field. */ + #define PWM_INTENSET_DMASEQ1READY_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ1READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ1READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1BUSERROR @Bit 14 : Write '1' to enable interrupt for event DMASEQ1BUSERROR */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Pos (14UL) /*!< Position of DMASEQ1BUSERROR field. */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTENSET_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field. */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH0 @Bit 15 : Write '1' to enable interrupt for event COMPAREMATCH[0] */ + #define PWM_INTENSET_COMPAREMATCH0_Pos (15UL) /*!< Position of COMPAREMATCH0 field. */ + #define PWM_INTENSET_COMPAREMATCH0_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field. */ + #define PWM_INTENSET_COMPAREMATCH0_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTENSET_COMPAREMATCH0_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTENSET_COMPAREMATCH0_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_COMPAREMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_COMPAREMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH1 @Bit 16 : Write '1' to enable interrupt for event COMPAREMATCH[1] */ + #define PWM_INTENSET_COMPAREMATCH1_Pos (16UL) /*!< Position of COMPAREMATCH1 field. */ + #define PWM_INTENSET_COMPAREMATCH1_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field. */ + #define PWM_INTENSET_COMPAREMATCH1_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTENSET_COMPAREMATCH1_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTENSET_COMPAREMATCH1_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_COMPAREMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_COMPAREMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH2 @Bit 17 : Write '1' to enable interrupt for event COMPAREMATCH[2] */ + #define PWM_INTENSET_COMPAREMATCH2_Pos (17UL) /*!< Position of COMPAREMATCH2 field. */ + #define PWM_INTENSET_COMPAREMATCH2_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field. */ + #define PWM_INTENSET_COMPAREMATCH2_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTENSET_COMPAREMATCH2_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTENSET_COMPAREMATCH2_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_COMPAREMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_COMPAREMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH3 @Bit 18 : Write '1' to enable interrupt for event COMPAREMATCH[3] */ + #define PWM_INTENSET_COMPAREMATCH3_Pos (18UL) /*!< Position of COMPAREMATCH3 field. */ + #define PWM_INTENSET_COMPAREMATCH3_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field. */ + #define PWM_INTENSET_COMPAREMATCH3_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTENSET_COMPAREMATCH3_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTENSET_COMPAREMATCH3_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_COMPAREMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_COMPAREMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* PWM_INTENCLR: Disable interrupt */ + #define PWM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PWM_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PWM_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PWM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQSTARTED0 @Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ + #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ + #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ + #define PWM_INTENCLR_SEQSTARTED0_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED0 field. */ + #define PWM_INTENCLR_SEQSTARTED0_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED0 field. */ + #define PWM_INTENCLR_SEQSTARTED0_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQSTARTED1 @Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ + #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ + #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ + #define PWM_INTENCLR_SEQSTARTED1_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED1 field. */ + #define PWM_INTENCLR_SEQSTARTED1_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED1 field. */ + #define PWM_INTENCLR_SEQSTARTED1_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQEND0 @Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ + #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ + #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ + #define PWM_INTENCLR_SEQEND0_Min (0x0UL) /*!< Min enumerator value of SEQEND0 field. */ + #define PWM_INTENCLR_SEQEND0_Max (0x1UL) /*!< Max enumerator value of SEQEND0 field. */ + #define PWM_INTENCLR_SEQEND0_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQEND1 @Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ + #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ + #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ + #define PWM_INTENCLR_SEQEND1_Min (0x0UL) /*!< Min enumerator value of SEQEND1 field. */ + #define PWM_INTENCLR_SEQEND1_Max (0x1UL) /*!< Max enumerator value of SEQEND1 field. */ + #define PWM_INTENCLR_SEQEND1_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ + #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define PWM_INTENCLR_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define PWM_INTENCLR_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define PWM_INTENCLR_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LOOPSDONE @Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ + #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ + #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ + #define PWM_INTENCLR_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE field. */ + #define PWM_INTENCLR_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE field. */ + #define PWM_INTENCLR_LOOPSDONE_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RAMUNDERFLOW @Bit 8 : Write '1' to disable interrupt for event RAMUNDERFLOW */ + #define PWM_INTENCLR_RAMUNDERFLOW_Pos (8UL) /*!< Position of RAMUNDERFLOW field. */ + #define PWM_INTENCLR_RAMUNDERFLOW_Msk (0x1UL << PWM_INTENCLR_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field. */ + #define PWM_INTENCLR_RAMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTENCLR_RAMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTENCLR_RAMUNDERFLOW_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_RAMUNDERFLOW_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_RAMUNDERFLOW_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0END @Bit 9 : Write '1' to disable interrupt for event DMASEQ0END */ + #define PWM_INTENCLR_DMASEQ0END_Pos (9UL) /*!< Position of DMASEQ0END field. */ + #define PWM_INTENCLR_DMASEQ0END_Msk (0x1UL << PWM_INTENCLR_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field. */ + #define PWM_INTENCLR_DMASEQ0END_Min (0x0UL) /*!< Min enumerator value of DMASEQ0END field. */ + #define PWM_INTENCLR_DMASEQ0END_Max (0x1UL) /*!< Max enumerator value of DMASEQ0END field. */ + #define PWM_INTENCLR_DMASEQ0END_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ0END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ0END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0READY @Bit 10 : Write '1' to disable interrupt for event DMASEQ0READY */ + #define PWM_INTENCLR_DMASEQ0READY_Pos (10UL) /*!< Position of DMASEQ0READY field. */ + #define PWM_INTENCLR_DMASEQ0READY_Msk (0x1UL << PWM_INTENCLR_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field. */ + #define PWM_INTENCLR_DMASEQ0READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ0READY field. */ + #define PWM_INTENCLR_DMASEQ0READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ0READY field. */ + #define PWM_INTENCLR_DMASEQ0READY_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ0READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ0READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0BUSERROR @Bit 11 : Write '1' to disable interrupt for event DMASEQ0BUSERROR */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Pos (11UL) /*!< Position of DMASEQ0BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTENCLR_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1END @Bit 12 : Write '1' to disable interrupt for event DMASEQ1END */ + #define PWM_INTENCLR_DMASEQ1END_Pos (12UL) /*!< Position of DMASEQ1END field. */ + #define PWM_INTENCLR_DMASEQ1END_Msk (0x1UL << PWM_INTENCLR_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field. */ + #define PWM_INTENCLR_DMASEQ1END_Min (0x0UL) /*!< Min enumerator value of DMASEQ1END field. */ + #define PWM_INTENCLR_DMASEQ1END_Max (0x1UL) /*!< Max enumerator value of DMASEQ1END field. */ + #define PWM_INTENCLR_DMASEQ1END_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ1END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ1END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1READY @Bit 13 : Write '1' to disable interrupt for event DMASEQ1READY */ + #define PWM_INTENCLR_DMASEQ1READY_Pos (13UL) /*!< Position of DMASEQ1READY field. */ + #define PWM_INTENCLR_DMASEQ1READY_Msk (0x1UL << PWM_INTENCLR_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field. */ + #define PWM_INTENCLR_DMASEQ1READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ1READY field. */ + #define PWM_INTENCLR_DMASEQ1READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ1READY field. */ + #define PWM_INTENCLR_DMASEQ1READY_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ1READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ1READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1BUSERROR @Bit 14 : Write '1' to disable interrupt for event DMASEQ1BUSERROR */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Pos (14UL) /*!< Position of DMASEQ1BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTENCLR_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH0 @Bit 15 : Write '1' to disable interrupt for event COMPAREMATCH[0] */ + #define PWM_INTENCLR_COMPAREMATCH0_Pos (15UL) /*!< Position of COMPAREMATCH0 field. */ + #define PWM_INTENCLR_COMPAREMATCH0_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field. */ + #define PWM_INTENCLR_COMPAREMATCH0_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTENCLR_COMPAREMATCH0_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTENCLR_COMPAREMATCH0_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_COMPAREMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_COMPAREMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH1 @Bit 16 : Write '1' to disable interrupt for event COMPAREMATCH[1] */ + #define PWM_INTENCLR_COMPAREMATCH1_Pos (16UL) /*!< Position of COMPAREMATCH1 field. */ + #define PWM_INTENCLR_COMPAREMATCH1_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field. */ + #define PWM_INTENCLR_COMPAREMATCH1_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTENCLR_COMPAREMATCH1_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTENCLR_COMPAREMATCH1_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_COMPAREMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_COMPAREMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH2 @Bit 17 : Write '1' to disable interrupt for event COMPAREMATCH[2] */ + #define PWM_INTENCLR_COMPAREMATCH2_Pos (17UL) /*!< Position of COMPAREMATCH2 field. */ + #define PWM_INTENCLR_COMPAREMATCH2_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field. */ + #define PWM_INTENCLR_COMPAREMATCH2_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTENCLR_COMPAREMATCH2_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTENCLR_COMPAREMATCH2_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_COMPAREMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_COMPAREMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH3 @Bit 18 : Write '1' to disable interrupt for event COMPAREMATCH[3] */ + #define PWM_INTENCLR_COMPAREMATCH3_Pos (18UL) /*!< Position of COMPAREMATCH3 field. */ + #define PWM_INTENCLR_COMPAREMATCH3_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field. */ + #define PWM_INTENCLR_COMPAREMATCH3_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTENCLR_COMPAREMATCH3_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTENCLR_COMPAREMATCH3_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_COMPAREMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_COMPAREMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* PWM_INTPEND: Pending interrupts */ + #define PWM_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* STOPPED @Bit 1 : Read pending status of interrupt for event STOPPED */ + #define PWM_INTPEND_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PWM_INTPEND_STOPPED_Msk (0x1UL << PWM_INTPEND_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PWM_INTPEND_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PWM_INTPEND_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PWM_INTPEND_STOPPED_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_STOPPED_Pending (0x1UL) /*!< Read: Pending */ + +/* SEQSTARTED0 @Bit 2 : Read pending status of interrupt for event SEQSTARTED[0] */ + #define PWM_INTPEND_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ + #define PWM_INTPEND_SEQSTARTED0_Msk (0x1UL << PWM_INTPEND_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ + #define PWM_INTPEND_SEQSTARTED0_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED0 field. */ + #define PWM_INTPEND_SEQSTARTED0_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED0 field. */ + #define PWM_INTPEND_SEQSTARTED0_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_SEQSTARTED0_Pending (0x1UL) /*!< Read: Pending */ + +/* SEQSTARTED1 @Bit 3 : Read pending status of interrupt for event SEQSTARTED[1] */ + #define PWM_INTPEND_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ + #define PWM_INTPEND_SEQSTARTED1_Msk (0x1UL << PWM_INTPEND_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ + #define PWM_INTPEND_SEQSTARTED1_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED1 field. */ + #define PWM_INTPEND_SEQSTARTED1_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED1 field. */ + #define PWM_INTPEND_SEQSTARTED1_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_SEQSTARTED1_Pending (0x1UL) /*!< Read: Pending */ + +/* SEQEND0 @Bit 4 : Read pending status of interrupt for event SEQEND[0] */ + #define PWM_INTPEND_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ + #define PWM_INTPEND_SEQEND0_Msk (0x1UL << PWM_INTPEND_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ + #define PWM_INTPEND_SEQEND0_Min (0x0UL) /*!< Min enumerator value of SEQEND0 field. */ + #define PWM_INTPEND_SEQEND0_Max (0x1UL) /*!< Max enumerator value of SEQEND0 field. */ + #define PWM_INTPEND_SEQEND0_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_SEQEND0_Pending (0x1UL) /*!< Read: Pending */ + +/* SEQEND1 @Bit 5 : Read pending status of interrupt for event SEQEND[1] */ + #define PWM_INTPEND_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ + #define PWM_INTPEND_SEQEND1_Msk (0x1UL << PWM_INTPEND_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ + #define PWM_INTPEND_SEQEND1_Min (0x0UL) /*!< Min enumerator value of SEQEND1 field. */ + #define PWM_INTPEND_SEQEND1_Max (0x1UL) /*!< Max enumerator value of SEQEND1 field. */ + #define PWM_INTPEND_SEQEND1_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_SEQEND1_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 6 : Read pending status of interrupt for event PWMPERIODEND */ + #define PWM_INTPEND_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ + #define PWM_INTPEND_PWMPERIODEND_Msk (0x1UL << PWM_INTPEND_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define PWM_INTPEND_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define PWM_INTPEND_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define PWM_INTPEND_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + +/* LOOPSDONE @Bit 7 : Read pending status of interrupt for event LOOPSDONE */ + #define PWM_INTPEND_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ + #define PWM_INTPEND_LOOPSDONE_Msk (0x1UL << PWM_INTPEND_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ + #define PWM_INTPEND_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE field. */ + #define PWM_INTPEND_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE field. */ + #define PWM_INTPEND_LOOPSDONE_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_LOOPSDONE_Pending (0x1UL) /*!< Read: Pending */ + +/* RAMUNDERFLOW @Bit 8 : Read pending status of interrupt for event RAMUNDERFLOW */ + #define PWM_INTPEND_RAMUNDERFLOW_Pos (8UL) /*!< Position of RAMUNDERFLOW field. */ + #define PWM_INTPEND_RAMUNDERFLOW_Msk (0x1UL << PWM_INTPEND_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field. */ + #define PWM_INTPEND_RAMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTPEND_RAMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTPEND_RAMUNDERFLOW_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_RAMUNDERFLOW_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ0END @Bit 9 : Read pending status of interrupt for event DMASEQ0END */ + #define PWM_INTPEND_DMASEQ0END_Pos (9UL) /*!< Position of DMASEQ0END field. */ + #define PWM_INTPEND_DMASEQ0END_Msk (0x1UL << PWM_INTPEND_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field. */ + #define PWM_INTPEND_DMASEQ0END_Min (0x0UL) /*!< Min enumerator value of DMASEQ0END field. */ + #define PWM_INTPEND_DMASEQ0END_Max (0x1UL) /*!< Max enumerator value of DMASEQ0END field. */ + #define PWM_INTPEND_DMASEQ0END_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ0END_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ0READY @Bit 10 : Read pending status of interrupt for event DMASEQ0READY */ + #define PWM_INTPEND_DMASEQ0READY_Pos (10UL) /*!< Position of DMASEQ0READY field. */ + #define PWM_INTPEND_DMASEQ0READY_Msk (0x1UL << PWM_INTPEND_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field. */ + #define PWM_INTPEND_DMASEQ0READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ0READY field. */ + #define PWM_INTPEND_DMASEQ0READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ0READY field. */ + #define PWM_INTPEND_DMASEQ0READY_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ0READY_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ0BUSERROR @Bit 11 : Read pending status of interrupt for event DMASEQ0BUSERROR */ + #define PWM_INTPEND_DMASEQ0BUSERROR_Pos (11UL) /*!< Position of DMASEQ0BUSERROR field. */ + #define PWM_INTPEND_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTPEND_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field. */ + #define PWM_INTPEND_DMASEQ0BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTPEND_DMASEQ0BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTPEND_DMASEQ0BUSERROR_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ0BUSERROR_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ1END @Bit 12 : Read pending status of interrupt for event DMASEQ1END */ + #define PWM_INTPEND_DMASEQ1END_Pos (12UL) /*!< Position of DMASEQ1END field. */ + #define PWM_INTPEND_DMASEQ1END_Msk (0x1UL << PWM_INTPEND_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field. */ + #define PWM_INTPEND_DMASEQ1END_Min (0x0UL) /*!< Min enumerator value of DMASEQ1END field. */ + #define PWM_INTPEND_DMASEQ1END_Max (0x1UL) /*!< Max enumerator value of DMASEQ1END field. */ + #define PWM_INTPEND_DMASEQ1END_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ1END_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ1READY @Bit 13 : Read pending status of interrupt for event DMASEQ1READY */ + #define PWM_INTPEND_DMASEQ1READY_Pos (13UL) /*!< Position of DMASEQ1READY field. */ + #define PWM_INTPEND_DMASEQ1READY_Msk (0x1UL << PWM_INTPEND_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field. */ + #define PWM_INTPEND_DMASEQ1READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ1READY field. */ + #define PWM_INTPEND_DMASEQ1READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ1READY field. */ + #define PWM_INTPEND_DMASEQ1READY_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ1READY_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ1BUSERROR @Bit 14 : Read pending status of interrupt for event DMASEQ1BUSERROR */ + #define PWM_INTPEND_DMASEQ1BUSERROR_Pos (14UL) /*!< Position of DMASEQ1BUSERROR field. */ + #define PWM_INTPEND_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTPEND_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field. */ + #define PWM_INTPEND_DMASEQ1BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTPEND_DMASEQ1BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTPEND_DMASEQ1BUSERROR_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ1BUSERROR_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPAREMATCH0 @Bit 15 : Read pending status of interrupt for event COMPAREMATCH[0] */ + #define PWM_INTPEND_COMPAREMATCH0_Pos (15UL) /*!< Position of COMPAREMATCH0 field. */ + #define PWM_INTPEND_COMPAREMATCH0_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field. */ + #define PWM_INTPEND_COMPAREMATCH0_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTPEND_COMPAREMATCH0_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTPEND_COMPAREMATCH0_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_COMPAREMATCH0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPAREMATCH1 @Bit 16 : Read pending status of interrupt for event COMPAREMATCH[1] */ + #define PWM_INTPEND_COMPAREMATCH1_Pos (16UL) /*!< Position of COMPAREMATCH1 field. */ + #define PWM_INTPEND_COMPAREMATCH1_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field. */ + #define PWM_INTPEND_COMPAREMATCH1_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTPEND_COMPAREMATCH1_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTPEND_COMPAREMATCH1_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_COMPAREMATCH1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPAREMATCH2 @Bit 17 : Read pending status of interrupt for event COMPAREMATCH[2] */ + #define PWM_INTPEND_COMPAREMATCH2_Pos (17UL) /*!< Position of COMPAREMATCH2 field. */ + #define PWM_INTPEND_COMPAREMATCH2_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field. */ + #define PWM_INTPEND_COMPAREMATCH2_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTPEND_COMPAREMATCH2_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTPEND_COMPAREMATCH2_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_COMPAREMATCH2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPAREMATCH3 @Bit 18 : Read pending status of interrupt for event COMPAREMATCH[3] */ + #define PWM_INTPEND_COMPAREMATCH3_Pos (18UL) /*!< Position of COMPAREMATCH3 field. */ + #define PWM_INTPEND_COMPAREMATCH3_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field. */ + #define PWM_INTPEND_COMPAREMATCH3_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTPEND_COMPAREMATCH3_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTPEND_COMPAREMATCH3_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_COMPAREMATCH3_Pending (0x1UL) /*!< Read: Pending */ + + +/* PWM_ENABLE: PWM module enable register */ + #define PWM_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable PWM module */ + #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define PWM_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define PWM_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define PWM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disabled */ + #define PWM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* PWM_MODE: Selects operating mode of the wave counter */ + #define PWM_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* UPDOWN @Bit 0 : Selects up mode or up-and-down mode for the counter */ + #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ + #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ + #define PWM_MODE_UPDOWN_Min (0x0UL) /*!< Min enumerator value of UPDOWN field. */ + #define PWM_MODE_UPDOWN_Max (0x1UL) /*!< Max enumerator value of UPDOWN field. */ + #define PWM_MODE_UPDOWN_Up (0x0UL) /*!< Up counter, edge-aligned PWM duty cycle */ + #define PWM_MODE_UPDOWN_UpAndDown (0x1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ + + +/* PWM_COUNTERTOP: Value up to which the pulse generator counter counts */ + #define PWM_COUNTERTOP_ResetValue (0x000003FFUL) /*!< Reset value of COUNTERTOP register. */ + +/* COUNTERTOP @Bits 0..14 : Value up to which the pulse generator counter counts. This register is ignored when + DECODER.MODE=WaveForm and only values from RAM are used. */ + + #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ + #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + #define PWM_COUNTERTOP_COUNTERTOP_Min (0x0003UL) /*!< Min value of COUNTERTOP field. */ + #define PWM_COUNTERTOP_COUNTERTOP_Max (0x7FFFUL) /*!< Max size of COUNTERTOP field. */ + + +/* PWM_PRESCALER: Configuration for PWM_CLK */ + #define PWM_PRESCALER_ResetValue (0x00000000UL) /*!< Reset value of PRESCALER register. */ + +/* PRESCALER @Bits 0..2 : Prescaler of PWM_CLK */ + #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ + #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + #define PWM_PRESCALER_PRESCALER_Min (0x0UL) /*!< Min enumerator value of PRESCALER field. */ + #define PWM_PRESCALER_PRESCALER_Max (0x7UL) /*!< Max enumerator value of PRESCALER field. */ + #define PWM_PRESCALER_PRESCALER_DIV_1 (0x0UL) /*!< Divide by 1 (16 MHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_2 (0x1UL) /*!< Divide by 2 (8 MHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_4 (0x2UL) /*!< Divide by 4 (4 MHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_8 (0x3UL) /*!< Divide by 8 (2 MHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_16 (0x4UL) /*!< Divide by 16 (1 MHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_32 (0x5UL) /*!< Divide by 32 (500 kHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_64 (0x6UL) /*!< Divide by 64 (250 kHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_128 (0x7UL) /*!< Divide by 128 (125 kHz) */ + + +/* PWM_DECODER: Configuration of the decoder */ + #define PWM_DECODER_ResetValue (0x00000000UL) /*!< Reset value of DECODER register. */ + +/* LOAD @Bits 0..1 : How a sequence is read from RAM and spread to the compare register */ + #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ + #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ + #define PWM_DECODER_LOAD_Min (0x0UL) /*!< Min enumerator value of LOAD field. */ + #define PWM_DECODER_LOAD_Max (0x3UL) /*!< Max enumerator value of LOAD field. */ + #define PWM_DECODER_LOAD_Common (0x0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ + #define PWM_DECODER_LOAD_Grouped (0x1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3*/ + #define PWM_DECODER_LOAD_Individual (0x2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ + #define PWM_DECODER_LOAD_WaveForm (0x3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* MODE @Bit 8 : Selects source for advancing the active sequence */ + #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ + #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ + #define PWM_DECODER_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define PWM_DECODER_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define PWM_DECODER_MODE_RefreshCount (0x0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare + registers*/ + #define PWM_DECODER_MODE_NextStep (0x1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare + registers*/ + + +/* PWM_LOOP: Number of playbacks of a loop */ + #define PWM_LOOP_ResetValue (0x00000000UL) /*!< Reset value of LOOP register. */ + +/* CNT @Bits 0..15 : Number of playbacks of pattern cycles */ + #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ + #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ + #define PWM_LOOP_CNT_Min (0x0000UL) /*!< Min enumerator value of CNT field. */ + #define PWM_LOOP_CNT_Max (0x0000UL) /*!< Max enumerator value of CNT field. */ + #define PWM_LOOP_CNT_Disabled (0x0000UL) /*!< Looping disabled (stop at the end of the sequence) */ + + +/* PWM_IDLEOUT: Configure the output value on the PWM channel during idle */ + #define PWM_IDLEOUT_ResetValue (0x00000000UL) /*!< Reset value of IDLEOUT register. */ + +/* VAL0 @Bit 0 : Idle output value for PWM channel [0] */ + #define PWM_IDLEOUT_VAL0_Pos (0UL) /*!< Position of VAL0 field. */ + #define PWM_IDLEOUT_VAL0_Msk (0x1UL << PWM_IDLEOUT_VAL0_Pos) /*!< Bit mask of VAL0 field. */ + +/* VAL1 @Bit 1 : Idle output value for PWM channel [1] */ + #define PWM_IDLEOUT_VAL1_Pos (1UL) /*!< Position of VAL1 field. */ + #define PWM_IDLEOUT_VAL1_Msk (0x1UL << PWM_IDLEOUT_VAL1_Pos) /*!< Bit mask of VAL1 field. */ + +/* VAL2 @Bit 2 : Idle output value for PWM channel [2] */ + #define PWM_IDLEOUT_VAL2_Pos (2UL) /*!< Position of VAL2 field. */ + #define PWM_IDLEOUT_VAL2_Msk (0x1UL << PWM_IDLEOUT_VAL2_Pos) /*!< Bit mask of VAL2 field. */ + +/* VAL3 @Bit 3 : Idle output value for PWM channel [3] */ + #define PWM_IDLEOUT_VAL3_Pos (3UL) /*!< Position of VAL3 field. */ + #define PWM_IDLEOUT_VAL3_Msk (0x1UL << PWM_IDLEOUT_VAL3_Pos) /*!< Bit mask of VAL3 field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ==================================================== Struct QDEC_PSEL ===================================================== */ +/** + * @brief PSEL [QDEC_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} NRF_QDEC_PSEL_Type; /*!< Size = 12 (0x00C) */ + +/* QDEC_PSEL_LED: Pin select for LED signal */ + #define QDEC_PSEL_LED_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LED register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + #define QDEC_PSEL_LED_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define QDEC_PSEL_LED_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define QDEC_PSEL_LED_PORT_Msk (0x7UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */ + #define QDEC_PSEL_LED_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define QDEC_PSEL_LED_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define QDEC_PSEL_LED_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define QDEC_PSEL_LED_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define QDEC_PSEL_LED_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define QDEC_PSEL_LED_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* QDEC_PSEL_A: Pin select for A signal */ + #define QDEC_PSEL_A_ResetValue (0xFFFFFFFFUL) /*!< Reset value of A register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + #define QDEC_PSEL_A_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define QDEC_PSEL_A_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define QDEC_PSEL_A_PORT_Msk (0x7UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */ + #define QDEC_PSEL_A_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define QDEC_PSEL_A_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define QDEC_PSEL_A_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define QDEC_PSEL_A_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define QDEC_PSEL_A_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define QDEC_PSEL_A_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* QDEC_PSEL_B: Pin select for B signal */ + #define QDEC_PSEL_B_ResetValue (0xFFFFFFFFUL) /*!< Reset value of B register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + #define QDEC_PSEL_B_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define QDEC_PSEL_B_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define QDEC_PSEL_B_PORT_Msk (0x7UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */ + #define QDEC_PSEL_B_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define QDEC_PSEL_B_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define QDEC_PSEL_B_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define QDEC_PSEL_B_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define QDEC_PSEL_B_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define QDEC_PSEL_B_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* ======================================================= Struct QDEC ======================================================= */ +/** + * @brief Quadrature Decoder + */ + typedef struct { /*!< QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[27]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_READCLRACC; /*!< (@ 0x00000088) Subscribe configuration for task READCLRACC */ + __IOM uint32_t SUBSCRIBE_RDCLRACC; /*!< (@ 0x0000008C) Subscribe configuration for task RDCLRACC */ + __IOM uint32_t SUBSCRIBE_RDCLRDBL; /*!< (@ 0x00000090) Subscribe configuration for task RDCLRDBL */ + __IM uint32_t RESERVED1[27]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register*/ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED2[27]; + __IOM uint32_t PUBLISH_SAMPLERDY; /*!< (@ 0x00000180) Publish configuration for event SAMPLERDY */ + __IOM uint32_t PUBLISH_REPORTRDY; /*!< (@ 0x00000184) Publish configuration for event REPORTRDY */ + __IOM uint32_t PUBLISH_ACCOF; /*!< (@ 0x00000188) Publish configuration for event ACCOF */ + __IOM uint32_t PUBLISH_DBLRDY; /*!< (@ 0x0000018C) Publish configuration for event DBLRDY */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000190) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED3[27]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED4[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY and + DBLRDY events can be generated*/ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the READCLRACC + or RDCLRACC task*/ + __IOM NRF_QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) (unspecified) */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED6[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected double + transitions*/ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC or + RDCLRDBL task*/ + } NRF_QDEC_Type; /*!< Size = 1356 (0x54C) */ + +/* QDEC_TASKS_START: Task starting the quadrature decoder */ + #define QDEC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Task starting the quadrature decoder */ + #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define QDEC_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define QDEC_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define QDEC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* QDEC_TASKS_STOP: Task stopping the quadrature decoder */ + #define QDEC_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Task stopping the quadrature decoder */ + #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define QDEC_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define QDEC_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* QDEC_TASKS_READCLRACC: Read and clear ACC and ACCDBL */ + #define QDEC_TASKS_READCLRACC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_READCLRACC register. */ + +/* TASKS_READCLRACC @Bit 0 : Read and clear ACC and ACCDBL */ + #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ + #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of + TASKS_READCLRACC field.*/ + #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Min (0x1UL) /*!< Min enumerator value of TASKS_READCLRACC field. */ + #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Max (0x1UL) /*!< Max enumerator value of TASKS_READCLRACC field. */ + #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (0x1UL) /*!< Trigger task */ + + +/* QDEC_TASKS_RDCLRACC: Read and clear ACC */ + #define QDEC_TASKS_RDCLRACC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RDCLRACC register. */ + +/* TASKS_RDCLRACC @Bit 0 : Read and clear ACC */ + #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ + #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of + TASKS_RDCLRACC field.*/ + #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Min (0x1UL) /*!< Min enumerator value of TASKS_RDCLRACC field. */ + #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Max (0x1UL) /*!< Max enumerator value of TASKS_RDCLRACC field. */ + #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (0x1UL) /*!< Trigger task */ + + +/* QDEC_TASKS_RDCLRDBL: Read and clear ACCDBL */ + #define QDEC_TASKS_RDCLRDBL_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RDCLRDBL register. */ + +/* TASKS_RDCLRDBL @Bit 0 : Read and clear ACCDBL */ + #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ + #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of + TASKS_RDCLRDBL field.*/ + #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Min (0x1UL) /*!< Min enumerator value of TASKS_RDCLRDBL field. */ + #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Max (0x1UL) /*!< Max enumerator value of TASKS_RDCLRDBL field. */ + #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (0x1UL) /*!< Trigger task */ + + +/* QDEC_SUBSCRIBE_START: Subscribe configuration for task START */ + #define QDEC_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define QDEC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_SUBSCRIBE_START_EN_Msk (0x1UL << QDEC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define QDEC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* QDEC_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define QDEC_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define QDEC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_SUBSCRIBE_STOP_EN_Msk (0x1UL << QDEC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define QDEC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* QDEC_SUBSCRIBE_READCLRACC: Subscribe configuration for task READCLRACC */ + #define QDEC_SUBSCRIBE_READCLRACC_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_READCLRACC register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task READCLRACC will subscribe to */ + #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_READCLRACC_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* QDEC_SUBSCRIBE_RDCLRACC: Subscribe configuration for task RDCLRACC */ + #define QDEC_SUBSCRIBE_RDCLRACC_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RDCLRACC register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RDCLRACC will subscribe to */ + #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRACC_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* QDEC_SUBSCRIBE_RDCLRDBL: Subscribe configuration for task RDCLRDBL */ + #define QDEC_SUBSCRIBE_RDCLRDBL_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RDCLRDBL register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RDCLRDBL will subscribe to */ + #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* QDEC_EVENTS_SAMPLERDY: Event being generated for every new sample value written to the SAMPLE register */ + #define QDEC_EVENTS_SAMPLERDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SAMPLERDY register. */ + +/* EVENTS_SAMPLERDY @Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of + EVENTS_SAMPLERDY field.*/ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_SAMPLERDY field. */ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_SAMPLERDY field. */ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (0x1UL) /*!< Event generated */ + + +/* QDEC_EVENTS_REPORTRDY: Non-null report ready */ + #define QDEC_EVENTS_REPORTRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_REPORTRDY register. */ + +/* EVENTS_REPORTRDY @Bit 0 : Non-null report ready */ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of + EVENTS_REPORTRDY field.*/ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_REPORTRDY field. */ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_REPORTRDY field. */ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (0x1UL) /*!< Event generated */ + + +/* QDEC_EVENTS_ACCOF: ACC or ACCDBL register overflow */ + #define QDEC_EVENTS_ACCOF_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ACCOF register. */ + +/* EVENTS_ACCOF @Bit 0 : ACC or ACCDBL register overflow */ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field.*/ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Min (0x0UL) /*!< Min enumerator value of EVENTS_ACCOF field. */ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Max (0x1UL) /*!< Max enumerator value of EVENTS_ACCOF field. */ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0x0UL) /*!< Event not generated */ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (0x1UL) /*!< Event generated */ + + +/* QDEC_EVENTS_DBLRDY: Double displacement(s) detected */ + #define QDEC_EVENTS_DBLRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DBLRDY register. */ + +/* EVENTS_DBLRDY @Bit 0 : Double displacement(s) detected */ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY + field.*/ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_DBLRDY field. */ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_DBLRDY field. */ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (0x1UL) /*!< Event generated */ + + +/* QDEC_EVENTS_STOPPED: QDEC has been stopped */ + #define QDEC_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : QDEC has been stopped */ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* QDEC_PUBLISH_SAMPLERDY: Publish configuration for event SAMPLERDY */ + #define QDEC_PUBLISH_SAMPLERDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SAMPLERDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SAMPLERDY will publish to */ + #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Msk (0x1UL << QDEC_PUBLISH_SAMPLERDY_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* QDEC_PUBLISH_REPORTRDY: Publish configuration for event REPORTRDY */ + #define QDEC_PUBLISH_REPORTRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_REPORTRDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event REPORTRDY will publish to */ + #define QDEC_PUBLISH_REPORTRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_PUBLISH_REPORTRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_REPORTRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_PUBLISH_REPORTRDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_PUBLISH_REPORTRDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_PUBLISH_REPORTRDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_PUBLISH_REPORTRDY_EN_Msk (0x1UL << QDEC_PUBLISH_REPORTRDY_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_PUBLISH_REPORTRDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_PUBLISH_REPORTRDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_PUBLISH_REPORTRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define QDEC_PUBLISH_REPORTRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* QDEC_PUBLISH_ACCOF: Publish configuration for event ACCOF */ + #define QDEC_PUBLISH_ACCOF_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ACCOF register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ACCOF will publish to */ + #define QDEC_PUBLISH_ACCOF_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_PUBLISH_ACCOF_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_ACCOF_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_PUBLISH_ACCOF_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_PUBLISH_ACCOF_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_PUBLISH_ACCOF_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_PUBLISH_ACCOF_EN_Msk (0x1UL << QDEC_PUBLISH_ACCOF_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_PUBLISH_ACCOF_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_PUBLISH_ACCOF_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_PUBLISH_ACCOF_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define QDEC_PUBLISH_ACCOF_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* QDEC_PUBLISH_DBLRDY: Publish configuration for event DBLRDY */ + #define QDEC_PUBLISH_DBLRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DBLRDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DBLRDY will publish to */ + #define QDEC_PUBLISH_DBLRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_PUBLISH_DBLRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_DBLRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_PUBLISH_DBLRDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_PUBLISH_DBLRDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_PUBLISH_DBLRDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_PUBLISH_DBLRDY_EN_Msk (0x1UL << QDEC_PUBLISH_DBLRDY_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_PUBLISH_DBLRDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_PUBLISH_DBLRDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_PUBLISH_DBLRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define QDEC_PUBLISH_DBLRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* QDEC_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define QDEC_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define QDEC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_PUBLISH_STOPPED_EN_Msk (0x1UL << QDEC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define QDEC_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* QDEC_SHORTS: Shortcuts between local events and tasks */ + #define QDEC_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* REPORTRDY_READCLRACC @Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of + REPORTRDY_READCLRACC field.*/ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Min (0x0UL) /*!< Min enumerator value of REPORTRDY_READCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Max (0x1UL) /*!< Max enumerator value of REPORTRDY_READCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut */ + +/* SAMPLERDY_STOP @Bit 1 : Shortcut between event SAMPLERDY and task STOP */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Min (0x0UL) /*!< Min enumerator value of SAMPLERDY_STOP field. */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Max (0x1UL) /*!< Max enumerator value of SAMPLERDY_STOP field. */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* REPORTRDY_RDCLRACC @Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC + field.*/ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Min (0x0UL) /*!< Min enumerator value of REPORTRDY_RDCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Max (0x1UL) /*!< Max enumerator value of REPORTRDY_RDCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (0x1UL) /*!< Enable shortcut */ + +/* REPORTRDY_STOP @Bit 3 : Shortcut between event REPORTRDY and task STOP */ + #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ + #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ + #define QDEC_SHORTS_REPORTRDY_STOP_Min (0x0UL) /*!< Min enumerator value of REPORTRDY_STOP field. */ + #define QDEC_SHORTS_REPORTRDY_STOP_Max (0x1UL) /*!< Max enumerator value of REPORTRDY_STOP field. */ + #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DBLRDY_RDCLRDBL @Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Min (0x0UL) /*!< Min enumerator value of DBLRDY_RDCLRDBL field. */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Max (0x1UL) /*!< Max enumerator value of DBLRDY_RDCLRDBL field. */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DBLRDY_STOP @Bit 5 : Shortcut between event DBLRDY and task STOP */ + #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ + #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ + #define QDEC_SHORTS_DBLRDY_STOP_Min (0x0UL) /*!< Min enumerator value of DBLRDY_STOP field. */ + #define QDEC_SHORTS_DBLRDY_STOP_Max (0x1UL) /*!< Max enumerator value of DBLRDY_STOP field. */ + #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_DBLRDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* SAMPLERDY_READCLRACC @Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of + SAMPLERDY_READCLRACC field.*/ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Min (0x0UL) /*!< Min enumerator value of SAMPLERDY_READCLRACC field. */ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Max (0x1UL) /*!< Max enumerator value of SAMPLERDY_READCLRACC field. */ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* QDEC_INTENSET: Enable interrupt */ + #define QDEC_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* SAMPLERDY @Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ + #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ + #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ + #define QDEC_INTENSET_SAMPLERDY_Min (0x0UL) /*!< Min enumerator value of SAMPLERDY field. */ + #define QDEC_INTENSET_SAMPLERDY_Max (0x1UL) /*!< Max enumerator value of SAMPLERDY field. */ + #define QDEC_INTENSET_SAMPLERDY_Set (0x1UL) /*!< Enable */ + #define QDEC_INTENSET_SAMPLERDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENSET_SAMPLERDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* REPORTRDY @Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ + #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ + #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ + #define QDEC_INTENSET_REPORTRDY_Min (0x0UL) /*!< Min enumerator value of REPORTRDY field. */ + #define QDEC_INTENSET_REPORTRDY_Max (0x1UL) /*!< Max enumerator value of REPORTRDY field. */ + #define QDEC_INTENSET_REPORTRDY_Set (0x1UL) /*!< Enable */ + #define QDEC_INTENSET_REPORTRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENSET_REPORTRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ACCOF @Bit 2 : Write '1' to enable interrupt for event ACCOF */ + #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ + #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ + #define QDEC_INTENSET_ACCOF_Min (0x0UL) /*!< Min enumerator value of ACCOF field. */ + #define QDEC_INTENSET_ACCOF_Max (0x1UL) /*!< Max enumerator value of ACCOF field. */ + #define QDEC_INTENSET_ACCOF_Set (0x1UL) /*!< Enable */ + #define QDEC_INTENSET_ACCOF_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENSET_ACCOF_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DBLRDY @Bit 3 : Write '1' to enable interrupt for event DBLRDY */ + #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ + #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ + #define QDEC_INTENSET_DBLRDY_Min (0x0UL) /*!< Min enumerator value of DBLRDY field. */ + #define QDEC_INTENSET_DBLRDY_Max (0x1UL) /*!< Max enumerator value of DBLRDY field. */ + #define QDEC_INTENSET_DBLRDY_Set (0x1UL) /*!< Enable */ + #define QDEC_INTENSET_DBLRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENSET_DBLRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 4 : Write '1' to enable interrupt for event STOPPED */ + #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ + #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define QDEC_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define QDEC_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define QDEC_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define QDEC_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* QDEC_INTENCLR: Disable interrupt */ + #define QDEC_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* SAMPLERDY @Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ + #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ + #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ + #define QDEC_INTENCLR_SAMPLERDY_Min (0x0UL) /*!< Min enumerator value of SAMPLERDY field. */ + #define QDEC_INTENCLR_SAMPLERDY_Max (0x1UL) /*!< Max enumerator value of SAMPLERDY field. */ + #define QDEC_INTENCLR_SAMPLERDY_Clear (0x1UL) /*!< Disable */ + #define QDEC_INTENCLR_SAMPLERDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENCLR_SAMPLERDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* REPORTRDY @Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ + #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ + #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ + #define QDEC_INTENCLR_REPORTRDY_Min (0x0UL) /*!< Min enumerator value of REPORTRDY field. */ + #define QDEC_INTENCLR_REPORTRDY_Max (0x1UL) /*!< Max enumerator value of REPORTRDY field. */ + #define QDEC_INTENCLR_REPORTRDY_Clear (0x1UL) /*!< Disable */ + #define QDEC_INTENCLR_REPORTRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENCLR_REPORTRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ACCOF @Bit 2 : Write '1' to disable interrupt for event ACCOF */ + #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ + #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ + #define QDEC_INTENCLR_ACCOF_Min (0x0UL) /*!< Min enumerator value of ACCOF field. */ + #define QDEC_INTENCLR_ACCOF_Max (0x1UL) /*!< Max enumerator value of ACCOF field. */ + #define QDEC_INTENCLR_ACCOF_Clear (0x1UL) /*!< Disable */ + #define QDEC_INTENCLR_ACCOF_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENCLR_ACCOF_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DBLRDY @Bit 3 : Write '1' to disable interrupt for event DBLRDY */ + #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ + #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ + #define QDEC_INTENCLR_DBLRDY_Min (0x0UL) /*!< Min enumerator value of DBLRDY field. */ + #define QDEC_INTENCLR_DBLRDY_Max (0x1UL) /*!< Max enumerator value of DBLRDY field. */ + #define QDEC_INTENCLR_DBLRDY_Clear (0x1UL) /*!< Disable */ + #define QDEC_INTENCLR_DBLRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENCLR_DBLRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 4 : Write '1' to disable interrupt for event STOPPED */ + #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ + #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define QDEC_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define QDEC_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define QDEC_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define QDEC_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* QDEC_ENABLE: Enable the quadrature decoder */ + #define QDEC_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable the quadrature decoder */ + #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define QDEC_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define QDEC_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define QDEC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define QDEC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* QDEC_LEDPOL: LED output pin polarity */ + #define QDEC_LEDPOL_ResetValue (0x00000000UL) /*!< Reset value of LEDPOL register. */ + +/* LEDPOL @Bit 0 : LED output pin polarity */ + #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ + #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ + #define QDEC_LEDPOL_LEDPOL_Min (0x0UL) /*!< Min enumerator value of LEDPOL field. */ + #define QDEC_LEDPOL_LEDPOL_Max (0x1UL) /*!< Max enumerator value of LEDPOL field. */ + #define QDEC_LEDPOL_LEDPOL_ActiveLow (0x0UL) /*!< Led active on output pin low */ + #define QDEC_LEDPOL_LEDPOL_ActiveHigh (0x1UL) /*!< Led active on output pin high */ + + +/* QDEC_SAMPLEPER: Sample period */ + #define QDEC_SAMPLEPER_ResetValue (0x00000000UL) /*!< Reset value of SAMPLEPER register. */ + +/* SAMPLEPER @Bits 0..3 : Sample period. The SAMPLE register will be updated for every new sample */ + #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ + #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ + #define QDEC_SAMPLEPER_SAMPLEPER_Min (0x0UL) /*!< Min enumerator value of SAMPLEPER field. */ + #define QDEC_SAMPLEPER_SAMPLEPER_Max (0xAUL) /*!< Max enumerator value of SAMPLEPER field. */ + #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x0UL) /*!< 128 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x1UL) /*!< 256 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x2UL) /*!< 512 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x3UL) /*!< 1024 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x4UL) /*!< 2048 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x5UL) /*!< 4096 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x6UL) /*!< 8192 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x7UL) /*!< 16384 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_32ms (0x8UL) /*!< 32768 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_65ms (0x9UL) /*!< 65536 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_131ms (0xAUL) /*!< 131072 us */ + + +/* QDEC_SAMPLE: Motion sample value */ + #define QDEC_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SAMPLE register. */ + +/* SAMPLE @Bits 0..31 : Last motion sample */ + #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ + #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + #define QDEC_SAMPLE_SAMPLE_Min (0xFFFFFFFFUL) /*!< Min value of SAMPLE field. */ + #define QDEC_SAMPLE_SAMPLE_Max (0x00000002UL) /*!< Max size of SAMPLE field. */ + + +/* QDEC_REPORTPER: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + #define QDEC_REPORTPER_ResetValue (0x00000000UL) /*!< Reset value of REPORTPER register. */ + +/* REPORTPER @Bits 0..3 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY + events can be generated. */ + + #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ + #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ + #define QDEC_REPORTPER_REPORTPER_Min (0x0UL) /*!< Min enumerator value of REPORTPER field. */ + #define QDEC_REPORTPER_REPORTPER_Max (0x8UL) /*!< Max enumerator value of REPORTPER field. */ + #define QDEC_REPORTPER_REPORTPER_10Smpl (0x0UL) /*!< 10 samples/report */ + #define QDEC_REPORTPER_REPORTPER_40Smpl (0x1UL) /*!< 40 samples/report */ + #define QDEC_REPORTPER_REPORTPER_80Smpl (0x2UL) /*!< 80 samples/report */ + #define QDEC_REPORTPER_REPORTPER_120Smpl (0x3UL) /*!< 120 samples/report */ + #define QDEC_REPORTPER_REPORTPER_160Smpl (0x4UL) /*!< 160 samples/report */ + #define QDEC_REPORTPER_REPORTPER_200Smpl (0x5UL) /*!< 200 samples/report */ + #define QDEC_REPORTPER_REPORTPER_240Smpl (0x6UL) /*!< 240 samples/report */ + #define QDEC_REPORTPER_REPORTPER_280Smpl (0x7UL) /*!< 280 samples/report */ + #define QDEC_REPORTPER_REPORTPER_1Smpl (0x8UL) /*!< 1 sample/report */ + + +/* QDEC_ACC: Register accumulating the valid transitions */ + #define QDEC_ACC_ResetValue (0x00000000UL) /*!< Reset value of ACC register. */ + +/* ACC @Bits 0..31 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */ + #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ + #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + #define QDEC_ACC_ACC_Min (0xFFFFFC00UL) /*!< Min value of ACC field. */ + #define QDEC_ACC_ACC_Max (0x000003FFUL) /*!< Max size of ACC field. */ + + +/* QDEC_ACCREAD: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + #define QDEC_ACCREAD_ResetValue (0x00000000UL) /*!< Reset value of ACCREAD register. */ + +/* ACCREAD @Bits 0..31 : Snapshot of the ACC register. */ + #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ + #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + #define QDEC_ACCREAD_ACCREAD_Min (0xFFFFFC00UL) /*!< Min value of ACCREAD field. */ + #define QDEC_ACCREAD_ACCREAD_Max (0x000003FFUL) /*!< Max size of ACCREAD field. */ + + +/* QDEC_DBFEN: Enable input debounce filters */ + #define QDEC_DBFEN_ResetValue (0x00000000UL) /*!< Reset value of DBFEN register. */ + +/* DBFEN @Bit 0 : Enable input debounce filters */ + #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ + #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ + #define QDEC_DBFEN_DBFEN_Min (0x0UL) /*!< Min enumerator value of DBFEN field. */ + #define QDEC_DBFEN_DBFEN_Max (0x1UL) /*!< Max enumerator value of DBFEN field. */ + #define QDEC_DBFEN_DBFEN_Disabled (0x0UL) /*!< Debounce input filters disabled */ + #define QDEC_DBFEN_DBFEN_Enabled (0x1UL) /*!< Debounce input filters enabled */ + + +/* QDEC_LEDPRE: Time period the LED is switched ON prior to sampling */ + #define QDEC_LEDPRE_ResetValue (0x00000010UL) /*!< Reset value of LEDPRE register. */ + +/* LEDPRE @Bits 0..8 : Period in us the LED is switched on prior to sampling */ + #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ + #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + #define QDEC_LEDPRE_LEDPRE_Min (0x001UL) /*!< Min value of LEDPRE field. */ + #define QDEC_LEDPRE_LEDPRE_Max (0x1FFUL) /*!< Max size of LEDPRE field. */ + + +/* QDEC_ACCDBL: Register accumulating the number of detected double transitions */ + #define QDEC_ACCDBL_ResetValue (0x00000000UL) /*!< Reset value of ACCDBL register. */ + +/* ACCDBL @Bits 0..3 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ + #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ + #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + #define QDEC_ACCDBL_ACCDBL_Min (0x0UL) /*!< Min value of ACCDBL field. */ + #define QDEC_ACCDBL_ACCDBL_Max (0xFUL) /*!< Max size of ACCDBL field. */ + + +/* QDEC_ACCDBLREAD: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + #define QDEC_ACCDBLREAD_ResetValue (0x00000000UL) /*!< Reset value of ACCDBLREAD register. */ + +/* ACCDBLREAD @Bits 0..3 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is + triggered. */ + + #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ + #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + #define QDEC_ACCDBLREAD_ACCDBLREAD_Min (0x0UL) /*!< Min value of ACCDBLREAD field. */ + #define QDEC_ACCDBLREAD_ACCDBLREAD_Max (0xFUL) /*!< Max size of ACCDBLREAD field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct RADIO_AUXDATA =================================================== */ +/** + * @brief AUXDATA [RADIO_AUXDATA] (unspecified) + */ +typedef struct { + __IOM uint32_t CNF[1]; /*!< (@ 0x00000000) AUXDATA configuration */ +} NRF_RADIO_AUXDATA_Type; /*!< Size = 4 (0x004) */ + +/* RADIO_AUXDATA_CNF: AUXDATA configuration */ + #define RADIO_AUXDATA_CNF_MaxCount (1UL) /*!< Max size of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_MaxIndex (0UL) /*!< Max index of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_MinIndex (0UL) /*!< Min index of CNF[1] array. */ + #define RADIO_AUXDATA_CNF_ResetValue (0x00000000UL) /*!< Reset value of CNF[1] register. */ + +/* ACQMODE @Bits 0..4 : Acquisition mode */ + #define RADIO_AUXDATA_CNF_ACQMODE_Pos (0UL) /*!< Position of ACQMODE field. */ + #define RADIO_AUXDATA_CNF_ACQMODE_Msk (0x1FUL << RADIO_AUXDATA_CNF_ACQMODE_Pos) /*!< Bit mask of ACQMODE field. */ + #define RADIO_AUXDATA_CNF_ACQMODE_Min (0x07UL) /*!< Min enumerator value of ACQMODE field. */ + #define RADIO_AUXDATA_CNF_ACQMODE_Max (0x07UL) /*!< Max enumerator value of ACQMODE field. */ + #define RADIO_AUXDATA_CNF_ACQMODE_Rtt (0x07UL) /*!< Baseband Channel Sounding RTT Data */ + + + +/* ================================================= Struct RADIO_AUXDATADMA ================================================= */ +/** + * @brief AUXDATADMA [RADIO_AUXDATADMA] (unspecified) + */ +typedef struct { + __IOM uint32_t ENABLE; /*!< (@ 0x00000000) Enable or disable data acquisition */ + __IOM uint32_t PTR; /*!< (@ 0x00000004) DMA pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of 32-bit words to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of 32-bit words transferred in the last + transaction*/ +} NRF_RADIO_AUXDATADMA_Type; /*!< Size = 16 (0x010) */ + #define RADIO_AUXDATADMA_MaxCount (1UL) /*!< Size of AUXDATADMA[1] array. */ + #define RADIO_AUXDATADMA_MaxIndex (0UL) /*!< Max index of AUXDATADMA[1] array. */ + #define RADIO_AUXDATADMA_MinIndex (0UL) /*!< Min index of AUXDATADMA[1] array. */ + +/* RADIO_AUXDATADMA_ENABLE: Enable or disable data acquisition */ + #define RADIO_AUXDATADMA_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable data acquisition */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Msk (0x1UL << RADIO_AUXDATADMA_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Disabled (0x0UL) /*!< Data acquisition is disabled */ + #define RADIO_AUXDATADMA_ENABLE_ENABLE_Enabled (0x1UL) /*!< Data acquisition is enabled */ + + +/* RADIO_AUXDATADMA_PTR: DMA pointer */ + #define RADIO_AUXDATADMA_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Data pointer */ + #define RADIO_AUXDATADMA_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define RADIO_AUXDATADMA_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_AUXDATADMA_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* RADIO_AUXDATADMA_MAXCNT: Maximum number of 32-bit words to transfer */ + #define RADIO_AUXDATADMA_MAXCNT_ResetValue (0x00000040UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..13 : Maximum number of 32-bit words to transfer */ + #define RADIO_AUXDATADMA_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define RADIO_AUXDATADMA_MAXCNT_MAXCNT_Msk (0x3FFFUL << RADIO_AUXDATADMA_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + + +/* RADIO_AUXDATADMA_AMOUNT: Number of 32-bit words transferred in the last transaction */ + #define RADIO_AUXDATADMA_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..13 : Number of 32-bit words transferred in the last transaction */ + #define RADIO_AUXDATADMA_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define RADIO_AUXDATADMA_AMOUNT_AMOUNT_Msk (0x3FFFUL << RADIO_AUXDATADMA_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + + +/* =================================================== Struct RADIO_RXGAIN =================================================== */ +/** + * @brief RXGAIN [RADIO_RXGAIN] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t CONFIG; /*!< (@ 0x00000004) Override configuration of receiver gain control loop */ +} NRF_RADIO_RXGAIN_Type; /*!< Size = 8 (0x008) */ + +/* RADIO_RXGAIN_CONFIG: Override configuration of receiver gain control loop */ + #define RADIO_RXGAIN_CONFIG_ResetValue (0x801230C3UL) /*!< Reset value of CONFIG register. */ + +/* AGCAAFOVERRIDE @Bits 17..20 : Override value for AAF */ + #define RADIO_RXGAIN_CONFIG_AGCAAFOVERRIDE_Pos (17UL) /*!< Position of AGCAAFOVERRIDE field. */ + #define RADIO_RXGAIN_CONFIG_AGCAAFOVERRIDE_Msk (0xFUL << RADIO_RXGAIN_CONFIG_AGCAAFOVERRIDE_Pos) /*!< Bit mask of + AGCAAFOVERRIDE field.*/ + +/* AGCMIXOVERRIDE @Bit 21 : Override value for MIX */ + #define RADIO_RXGAIN_CONFIG_AGCMIXOVERRIDE_Pos (21UL) /*!< Position of AGCMIXOVERRIDE field. */ + #define RADIO_RXGAIN_CONFIG_AGCMIXOVERRIDE_Msk (0x1UL << RADIO_RXGAIN_CONFIG_AGCMIXOVERRIDE_Pos) /*!< Bit mask of + AGCMIXOVERRIDE field.*/ + +/* AGCLNAOVERRIDE @Bits 22..23 : Override value for LNA */ + #define RADIO_RXGAIN_CONFIG_AGCLNAOVERRIDE_Pos (22UL) /*!< Position of AGCLNAOVERRIDE field. */ + #define RADIO_RXGAIN_CONFIG_AGCLNAOVERRIDE_Msk (0x3UL << RADIO_RXGAIN_CONFIG_AGCLNAOVERRIDE_Pos) /*!< Bit mask of + AGCLNAOVERRIDE field.*/ + +/* AGCOVERRIDEGAIN @Bit 28 : Enable AGC override */ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Pos (28UL) /*!< Position of AGCOVERRIDEGAIN field. */ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Msk (0x1UL << RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Pos) /*!< Bit mask of + AGCOVERRIDEGAIN field.*/ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Min (0x0UL) /*!< Min enumerator value of AGCOVERRIDEGAIN field. */ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Max (0x1UL) /*!< Max enumerator value of AGCOVERRIDEGAIN field. */ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_NoOverride (0x0UL) /*!< AGC takes control over all gains */ + #define RADIO_RXGAIN_CONFIG_AGCOVERRIDEGAIN_Override (0x1UL) /*!< Manual control of AAF, MIX, and LNA gain settings */ + + + +/* ==================================================== Struct RADIO_PSEL ==================================================== */ +/** + * @brief PSEL [RADIO_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t DFEGPIO[7]; /*!< (@ 0x00000000) Pin select for DFE pin n */ +} NRF_RADIO_PSEL_Type; /*!< Size = 28 (0x01C) */ + +/* RADIO_PSEL_DFEGPIO: Pin select for DFE pin n */ + #define RADIO_PSEL_DFEGPIO_MaxCount (7UL) /*!< Max size of DFEGPIO[7] array. */ + #define RADIO_PSEL_DFEGPIO_MaxIndex (6UL) /*!< Max index of DFEGPIO[7] array. */ + #define RADIO_PSEL_DFEGPIO_MinIndex (0UL) /*!< Min index of DFEGPIO[7] array. */ + #define RADIO_PSEL_DFEGPIO_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DFEGPIO[7] register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */ + #define RADIO_PSEL_DFEGPIO_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define RADIO_PSEL_DFEGPIO_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define RADIO_PSEL_DFEGPIO_PORT_Msk (0xFUL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field. */ + #define RADIO_PSEL_DFEGPIO_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define RADIO_PSEL_DFEGPIO_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================= Struct RADIO_DFEPACKET ================================================== */ +/** + * @brief DFEPACKET [RADIO_DFEPACKET] DFE packet EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the current transaction*/ +} NRF_RADIO_DFEPACKET_Type; /*!< Size = 16 (0x010) */ + +/* RADIO_DFEPACKET_PTR: Data pointer */ + #define RADIO_DFEPACKET_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Data pointer */ + #define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* RADIO_DFEPACKET_MAXCNT: Maximum number of bytes to transfer */ + #define RADIO_DFEPACKET_MAXCNT_ResetValue (0x00004000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes to transfer */ + #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0xFFFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + + +/* RADIO_DFEPACKET_AMOUNT: Number of bytes transferred in the last transaction */ + #define RADIO_DFEPACKET_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction */ + #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* RADIO_DFEPACKET_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define RADIO_DFEPACKET_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define RADIO_DFEPACKET_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define RADIO_DFEPACKET_CURRENTAMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of + AMOUNT field.*/ + + + +/* ================================================== Struct RADIO_CSTONES =================================================== */ +/** + * @brief CSTONES [RADIO_CSTONES] (unspecified) + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) Selects the mode(s) that are activated on the start + signal*/ + __IOM uint32_t NUMSAMPLES; /*!< (@ 0x00000004) Number of input samples at 2MHz sample rate */ + __IOM uint32_t NEXTFREQUENCY; /*!< (@ 0x00000008) The value of FREQUENCY that will be used in the next + step*/ + __IM uint32_t RESERVED[2]; + __IOM uint32_t FAEPEER; /*!< (@ 0x00000014) FAEPEER (Frequency Actuation Error) of peer if known. + Used during Mode 0 steps.*/ + __IOM uint32_t PHASESHIFT; /*!< (@ 0x00000018) Parameter used in TPM, provided by software */ + __IOM uint32_t NUMSAMPLESCOEFF; /*!< (@ 0x0000001C) Parameter used in TPM, provided by software */ + __IM uint32_t PCT16; /*!< (@ 0x00000020) Mean magnitude and mean phase converted to IQ */ + __IM uint32_t MAGPHASEMEAN; /*!< (@ 0x00000024) Mean magnitude and phase of the signal before it is + converted to PCT16*/ + __IM uint32_t IQRAWMEAN; /*!< (@ 0x00000028) Mean of IQ values */ + __IM uint32_t MAGSTD; /*!< (@ 0x0000002C) Magnitude standard deviation approximation */ + __IM uint32_t RESERVED1; + __IM uint32_t FFOEST; /*!< (@ 0x00000034) FFO estimate */ + __IOM uint32_t DOWNSAMPLE; /*!< (@ 0x00000038) Turn on/off down sample of input IQ-signals */ + __IM uint32_t RESERVED2[2]; + __IM uint32_t FREQOFFSET; /*!< (@ 0x00000044) Frequency offset estimate */ +} NRF_RADIO_CSTONES_Type; /*!< Size = 72 (0x048) */ + +/* RADIO_CSTONES_MODE: Selects the mode(s) that are activated on the start signal */ + #define RADIO_CSTONES_MODE_ResetValue (0x00000003UL) /*!< Reset value of MODE register. */ + +/* TPM @Bit 0 : Enable or disable TPM */ + #define RADIO_CSTONES_MODE_TPM_Pos (0UL) /*!< Position of TPM field. */ + #define RADIO_CSTONES_MODE_TPM_Msk (0x1UL << RADIO_CSTONES_MODE_TPM_Pos) /*!< Bit mask of TPM field. */ + #define RADIO_CSTONES_MODE_TPM_Min (0x0UL) /*!< Min enumerator value of TPM field. */ + #define RADIO_CSTONES_MODE_TPM_Max (0x1UL) /*!< Max enumerator value of TPM field. */ + #define RADIO_CSTONES_MODE_TPM_Disabled (0x0UL) /*!< TPM is disabled */ + #define RADIO_CSTONES_MODE_TPM_Enabled (0x1UL) /*!< TPM is enabled */ + +/* TFM @Bit 1 : Enable or disable TFM */ + #define RADIO_CSTONES_MODE_TFM_Pos (1UL) /*!< Position of TFM field. */ + #define RADIO_CSTONES_MODE_TFM_Msk (0x1UL << RADIO_CSTONES_MODE_TFM_Pos) /*!< Bit mask of TFM field. */ + #define RADIO_CSTONES_MODE_TFM_Min (0x0UL) /*!< Min enumerator value of TFM field. */ + #define RADIO_CSTONES_MODE_TFM_Max (0x1UL) /*!< Max enumerator value of TFM field. */ + #define RADIO_CSTONES_MODE_TFM_Disabled (0x0UL) /*!< TFM is disabled */ + #define RADIO_CSTONES_MODE_TFM_Enabled (0x1UL) /*!< TFM is enabled */ + + +/* RADIO_CSTONES_NUMSAMPLES: Number of input samples at 2MHz sample rate */ + #define RADIO_CSTONES_NUMSAMPLES_ResetValue (0x000000A0UL) /*!< Reset value of NUMSAMPLES register. */ + +/* NUMSAMPLES @Bits 0..7 : Maximum value supported is 160 */ + #define RADIO_CSTONES_NUMSAMPLES_NUMSAMPLES_Pos (0UL) /*!< Position of NUMSAMPLES field. */ + #define RADIO_CSTONES_NUMSAMPLES_NUMSAMPLES_Msk (0xFFUL << RADIO_CSTONES_NUMSAMPLES_NUMSAMPLES_Pos) /*!< Bit mask of + NUMSAMPLES field.*/ + + +/* RADIO_CSTONES_NEXTFREQUENCY: The value of FREQUENCY that will be used in the next step */ + #define RADIO_CSTONES_NEXTFREQUENCY_ResetValue (0x00000000UL) /*!< Reset value of NEXTFREQUENCY register. */ + +/* NEXTFREQUENCY @Bits 0..6 : Frequency = 2400 + FREQUENCY (MHz) */ + #define RADIO_CSTONES_NEXTFREQUENCY_NEXTFREQUENCY_Pos (0UL) /*!< Position of NEXTFREQUENCY field. */ + #define RADIO_CSTONES_NEXTFREQUENCY_NEXTFREQUENCY_Msk (0x7FUL << RADIO_CSTONES_NEXTFREQUENCY_NEXTFREQUENCY_Pos) /*!< Bit mask + of NEXTFREQUENCY field.*/ + + +/* RADIO_CSTONES_FAEPEER: FAEPEER (Frequency Actuation Error) of peer if known. Used during Mode 0 steps. */ + #define RADIO_CSTONES_FAEPEER_ResetValue (0x00000000UL) /*!< Reset value of FAEPEER register. */ + +/* FAEPEER @Bits 0..7 : Units 31.25 ppb. */ + #define RADIO_CSTONES_FAEPEER_FAEPEER_Pos (0UL) /*!< Position of FAEPEER field. */ + #define RADIO_CSTONES_FAEPEER_FAEPEER_Msk (0xFFUL << RADIO_CSTONES_FAEPEER_FAEPEER_Pos) /*!< Bit mask of FAEPEER field. */ + + +/* RADIO_CSTONES_PHASESHIFT: Parameter used in TPM, provided by software */ + #define RADIO_CSTONES_PHASESHIFT_ResetValue (0x00000000UL) /*!< Reset value of PHASESHIFT register. */ + +/* PHASESHIFT @Bits 0..15 : Phase shift used in TPM calculation */ + #define RADIO_CSTONES_PHASESHIFT_PHASESHIFT_Pos (0UL) /*!< Position of PHASESHIFT field. */ + #define RADIO_CSTONES_PHASESHIFT_PHASESHIFT_Msk (0xFFFFUL << RADIO_CSTONES_PHASESHIFT_PHASESHIFT_Pos) /*!< Bit mask of + PHASESHIFT field.*/ + + +/* RADIO_CSTONES_NUMSAMPLESCOEFF: Parameter used in TPM, provided by software */ + #define RADIO_CSTONES_NUMSAMPLESCOEFF_ResetValue (0x0000199AUL) /*!< Reset value of NUMSAMPLESCOEFF register. */ + +/* NUMSAMPLESCOEFF @Bits 0..15 : Coefficient 2**16/(numSamples/16) in Q1.15 format (Default numsamples value is 160) */ + #define RADIO_CSTONES_NUMSAMPLESCOEFF_NUMSAMPLESCOEFF_Pos (0UL) /*!< Position of NUMSAMPLESCOEFF field. */ + #define RADIO_CSTONES_NUMSAMPLESCOEFF_NUMSAMPLESCOEFF_Msk (0xFFFFUL << RADIO_CSTONES_NUMSAMPLESCOEFF_NUMSAMPLESCOEFF_Pos) /*!< + Bit mask of NUMSAMPLESCOEFF field.*/ + + +/* RADIO_CSTONES_PCT16: Mean magnitude and mean phase converted to IQ */ + #define RADIO_CSTONES_PCT16_ResetValue (0x00000000UL) /*!< Reset value of PCT16 register. */ + +/* PCT16I @Bits 0..15 : Inphase */ + #define RADIO_CSTONES_PCT16_PCT16I_Pos (0UL) /*!< Position of PCT16I field. */ + #define RADIO_CSTONES_PCT16_PCT16I_Msk (0xFFFFUL << RADIO_CSTONES_PCT16_PCT16I_Pos) /*!< Bit mask of PCT16I field. */ + +/* PCT16Q @Bits 16..31 : Quadrature */ + #define RADIO_CSTONES_PCT16_PCT16Q_Pos (16UL) /*!< Position of PCT16Q field. */ + #define RADIO_CSTONES_PCT16_PCT16Q_Msk (0xFFFFUL << RADIO_CSTONES_PCT16_PCT16Q_Pos) /*!< Bit mask of PCT16Q field. */ + + +/* RADIO_CSTONES_MAGPHASEMEAN: Mean magnitude and phase of the signal before it is converted to PCT16 */ + #define RADIO_CSTONES_MAGPHASEMEAN_ResetValue (0x00000000UL) /*!< Reset value of MAGPHASEMEAN register. */ + +/* PHASE @Bits 0..15 : Mean phase */ + #define RADIO_CSTONES_MAGPHASEMEAN_PHASE_Pos (0UL) /*!< Position of PHASE field. */ + #define RADIO_CSTONES_MAGPHASEMEAN_PHASE_Msk (0xFFFFUL << RADIO_CSTONES_MAGPHASEMEAN_PHASE_Pos) /*!< Bit mask of PHASE field.*/ + +/* MAG @Bits 16..31 : Mean magnitude */ + #define RADIO_CSTONES_MAGPHASEMEAN_MAG_Pos (16UL) /*!< Position of MAG field. */ + #define RADIO_CSTONES_MAGPHASEMEAN_MAG_Msk (0xFFFFUL << RADIO_CSTONES_MAGPHASEMEAN_MAG_Pos) /*!< Bit mask of MAG field. */ + + +/* RADIO_CSTONES_IQRAWMEAN: Mean of IQ values */ + #define RADIO_CSTONES_IQRAWMEAN_ResetValue (0x00000000UL) /*!< Reset value of IQRAWMEAN register. */ + +/* IQRAWMEANI @Bits 0..15 : Inphase */ + #define RADIO_CSTONES_IQRAWMEAN_IQRAWMEANI_Pos (0UL) /*!< Position of IQRAWMEANI field. */ + #define RADIO_CSTONES_IQRAWMEAN_IQRAWMEANI_Msk (0xFFFFUL << RADIO_CSTONES_IQRAWMEAN_IQRAWMEANI_Pos) /*!< Bit mask of + IQRAWMEANI field.*/ + +/* IQRAWMEANQ @Bits 16..31 : Quadrature */ + #define RADIO_CSTONES_IQRAWMEAN_IQRAWMEANQ_Pos (16UL) /*!< Position of IQRAWMEANQ field. */ + #define RADIO_CSTONES_IQRAWMEAN_IQRAWMEANQ_Msk (0xFFFFUL << RADIO_CSTONES_IQRAWMEAN_IQRAWMEANQ_Pos) /*!< Bit mask of + IQRAWMEANQ field.*/ + + +/* RADIO_CSTONES_MAGSTD: Magnitude standard deviation approximation */ + #define RADIO_CSTONES_MAGSTD_ResetValue (0x00000000UL) /*!< Reset value of MAGSTD register. */ + +/* MAGSTD @Bits 0..15 : Magnitude standard deviation approximation */ + #define RADIO_CSTONES_MAGSTD_MAGSTD_Pos (0UL) /*!< Position of MAGSTD field. */ + #define RADIO_CSTONES_MAGSTD_MAGSTD_Msk (0xFFFFUL << RADIO_CSTONES_MAGSTD_MAGSTD_Pos) /*!< Bit mask of MAGSTD field. */ + + +/* RADIO_CSTONES_FFOEST: FFO estimate */ + #define RADIO_CSTONES_FFOEST_ResetValue (0x00000000UL) /*!< Reset value of FFOEST register. */ + +/* FFOEST @Bits 0..11 : Units 62.5 ppb. Max range +/-100 ppm plus margin. */ + #define RADIO_CSTONES_FFOEST_FFOEST_Pos (0UL) /*!< Position of FFOEST field. */ + #define RADIO_CSTONES_FFOEST_FFOEST_Msk (0xFFFUL << RADIO_CSTONES_FFOEST_FFOEST_Pos) /*!< Bit mask of FFOEST field. */ + + +/* RADIO_CSTONES_DOWNSAMPLE: Turn on/off down sample of input IQ-signals */ + #define RADIO_CSTONES_DOWNSAMPLE_ResetValue (0x00000000UL) /*!< Reset value of DOWNSAMPLE register. */ + +/* ENABLEFILTER @Bit 0 : Turn on/off down sample of input IQ-signals */ + #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_Pos (0UL) /*!< Position of ENABLEFILTER field. */ + #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_Msk (0x1UL << RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_Pos) /*!< Bit mask of + ENABLEFILTER field.*/ + #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_Min (0x0UL) /*!< Min enumerator value of ENABLEFILTER field. */ + #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_Max (0x1UL) /*!< Max enumerator value of ENABLEFILTER field. */ + #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_OFF (0x0UL) /*!< Disable filter */ + #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_ON (0x1UL) /*!< Enable filter */ + +/* RATE @Bit 1 : Indicating if BLE1M or BLE2M is used */ + #define RADIO_CSTONES_DOWNSAMPLE_RATE_Pos (1UL) /*!< Position of RATE field. */ + #define RADIO_CSTONES_DOWNSAMPLE_RATE_Msk (0x1UL << RADIO_CSTONES_DOWNSAMPLE_RATE_Pos) /*!< Bit mask of RATE field. */ + #define RADIO_CSTONES_DOWNSAMPLE_RATE_Min (0x0UL) /*!< Min enumerator value of RATE field. */ + #define RADIO_CSTONES_DOWNSAMPLE_RATE_Max (0x1UL) /*!< Max enumerator value of RATE field. */ + #define RADIO_CSTONES_DOWNSAMPLE_RATE_BLE1M (0x0UL) /*!< Radio mode BLE1M is used */ + #define RADIO_CSTONES_DOWNSAMPLE_RATE_BLE2m (0x1UL) /*!< Radio mode BLE2M is used */ + #define RADIO_CSTONES_DOWNSAMPLE_RATE_BLE2M (0x1UL) /*!< Radio mode BLE2M is used */ + + +/* RADIO_CSTONES_FREQOFFSET: Frequency offset estimate */ + #define RADIO_CSTONES_FREQOFFSET_ResetValue (0x00000000UL) /*!< Reset value of FREQOFFSET register. */ + +/* FREQOFFSET @Bits 0..13 : (unspecified) */ + #define RADIO_CSTONES_FREQOFFSET_FREQOFFSET_Pos (0UL) /*!< Position of FREQOFFSET field. */ + #define RADIO_CSTONES_FREQOFFSET_FREQOFFSET_Msk (0x3FFFUL << RADIO_CSTONES_FREQOFFSET_FREQOFFSET_Pos) /*!< Bit mask of + FREQOFFSET field.*/ + + + +/* ==================================================== Struct RADIO_RTT ===================================================== */ +/** + * @brief RTT [RADIO_RTT] (unspecified) + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) RTT Config. */ + __IOM uint32_t SEGMENT01; /*!< (@ 0x00000004) RTT segments 0 and 1 */ + __IOM uint32_t SEGMENT23; /*!< (@ 0x00000008) RTT segments 2 and 3 */ + __IOM uint32_t SEGMENT45; /*!< (@ 0x0000000C) RTT segments 4 and 5 */ + __IOM uint32_t SEGMENT67; /*!< (@ 0x00000010) RTT segments 6 and 7 */ +} NRF_RADIO_RTT_Type; /*!< Size = 20 (0x014) */ + +/* RADIO_RTT_CONFIG: RTT Config. */ + #define RADIO_RTT_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* EN @Bit 0 : Enable RTT functionality. Only valid for BLE 1MBPS and 2MBPS mode */ + #define RADIO_RTT_CONFIG_EN_Pos (0UL) /*!< Position of EN field. */ + #define RADIO_RTT_CONFIG_EN_Msk (0x1UL << RADIO_RTT_CONFIG_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_RTT_CONFIG_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_RTT_CONFIG_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_RTT_CONFIG_EN_Disabled (0x0UL) /*!< Disable RTT Block */ + #define RADIO_RTT_CONFIG_EN_Enabled (0x1UL) /*!< Enable RTT Block */ + +/* ENFULLAA @Bit 1 : Enabling/Disable ping over the entire access address. */ + #define RADIO_RTT_CONFIG_ENFULLAA_Pos (1UL) /*!< Position of ENFULLAA field. */ + #define RADIO_RTT_CONFIG_ENFULLAA_Msk (0x1UL << RADIO_RTT_CONFIG_ENFULLAA_Pos) /*!< Bit mask of ENFULLAA field. */ + #define RADIO_RTT_CONFIG_ENFULLAA_Min (0x0UL) /*!< Min enumerator value of ENFULLAA field. */ + #define RADIO_RTT_CONFIG_ENFULLAA_Max (0x1UL) /*!< Max enumerator value of ENFULLAA field. */ + #define RADIO_RTT_CONFIG_ENFULLAA_Disabled (0x0UL) /*!< Disable ping over the entire access address, i.e., enable only over + the first 16-bit access address*/ + #define RADIO_RTT_CONFIG_ENFULLAA_Enabled (0x1UL) /*!< Enable ping over the entire access address */ + +/* ROLE @Bit 2 : Role as a Initiator or Reflector. */ + #define RADIO_RTT_CONFIG_ROLE_Pos (2UL) /*!< Position of ROLE field. */ + #define RADIO_RTT_CONFIG_ROLE_Msk (0x1UL << RADIO_RTT_CONFIG_ROLE_Pos) /*!< Bit mask of ROLE field. */ + #define RADIO_RTT_CONFIG_ROLE_Min (0x0UL) /*!< Min enumerator value of ROLE field. */ + #define RADIO_RTT_CONFIG_ROLE_Max (0x1UL) /*!< Max enumerator value of ROLE field. */ + #define RADIO_RTT_CONFIG_ROLE_Initiator (0x0UL) /*!< Initiator */ + #define RADIO_RTT_CONFIG_ROLE_Reflector (0x1UL) /*!< Reflector */ + +/* NUMSEGMENTS @Bits 3..6 : Number of 16bit payload segments available for ToA detection. Allowed values are 0, 2, 4, 6 and 8. */ + #define RADIO_RTT_CONFIG_NUMSEGMENTS_Pos (3UL) /*!< Position of NUMSEGMENTS field. */ + #define RADIO_RTT_CONFIG_NUMSEGMENTS_Msk (0xFUL << RADIO_RTT_CONFIG_NUMSEGMENTS_Pos) /*!< Bit mask of NUMSEGMENTS field. */ + +/* EFSDELAY @Bits 8..16 : Early Frame Sync Delay, i.e., number of cycles to wait for access address to anchor correctly. For + Ble_2Mbit, the EFSDELAY value is 64 (2us) and for Ble_1Mbit, it can be 256 (8us). */ + + #define RADIO_RTT_CONFIG_EFSDELAY_Pos (8UL) /*!< Position of EFSDELAY field. */ + #define RADIO_RTT_CONFIG_EFSDELAY_Msk (0x1FFUL << RADIO_RTT_CONFIG_EFSDELAY_Pos) /*!< Bit mask of EFSDELAY field. */ + + +/* RADIO_RTT_SEGMENT01: RTT segments 0 and 1 */ + #define RADIO_RTT_SEGMENT01_ResetValue (0x00000000UL) /*!< Reset value of SEGMENT01 register. */ + +/* DATA @Bits 0..31 : Data Bits 31 - 0 */ + #define RADIO_RTT_SEGMENT01_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define RADIO_RTT_SEGMENT01_DATA_Msk (0xFFFFFFFFUL << RADIO_RTT_SEGMENT01_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* RADIO_RTT_SEGMENT23: RTT segments 2 and 3 */ + #define RADIO_RTT_SEGMENT23_ResetValue (0x00000000UL) /*!< Reset value of SEGMENT23 register. */ + +/* DATA @Bits 0..31 : Data Bits 63 - 32 */ + #define RADIO_RTT_SEGMENT23_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define RADIO_RTT_SEGMENT23_DATA_Msk (0xFFFFFFFFUL << RADIO_RTT_SEGMENT23_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* RADIO_RTT_SEGMENT45: RTT segments 4 and 5 */ + #define RADIO_RTT_SEGMENT45_ResetValue (0x00000000UL) /*!< Reset value of SEGMENT45 register. */ + +/* DATA @Bits 0..31 : Data Bits 95 - 64 */ + #define RADIO_RTT_SEGMENT45_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define RADIO_RTT_SEGMENT45_DATA_Msk (0xFFFFFFFFUL << RADIO_RTT_SEGMENT45_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* RADIO_RTT_SEGMENT67: RTT segments 6 and 7 */ + #define RADIO_RTT_SEGMENT67_ResetValue (0x00000000UL) /*!< Reset value of SEGMENT67 register. */ + +/* DATA @Bits 0..31 : Data Bits 127 - 96 */ + #define RADIO_RTT_SEGMENT67_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define RADIO_RTT_SEGMENT67_DATA_Msk (0xFFFFFFFFUL << RADIO_RTT_SEGMENT67_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* ====================================================== Struct RADIO ======================================================= */ +/** + * @brief 2.4 GHz radio + */ + typedef struct { /*!< RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of the + receive signal strength*/ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x00000018) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x0000001C) Stop the bit counter */ + __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000020) Start the energy detect measurement used in IEEE + 802.15.4 mode*/ + __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000024) Stop the energy detect measurement */ + __OM uint32_t TASKS_CCASTART; /*!< (@ 0x00000028) Start the clear channel assessment used in IEEE + 802.15.4 mode*/ + __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x0000002C) Stop the clear channel assessment */ + __IM uint32_t RESERVED[2]; + __OM uint32_t TASKS_AUXDATADMASTART; /*!< (@ 0x00000038) Start DMA transaction of acquisition */ + __OM uint32_t TASKS_AUXDATADMASTOP; /*!< (@ 0x0000003C) Stop ongoing DMA transaction of acquisition */ + __IM uint32_t RESERVED1[11]; + __OM uint32_t TASKS_PLLEN; /*!< (@ 0x0000006C) Enable RADIO in PLL mode (standby for either TX or RX)*/ + __IM uint32_t RESERVED2[12]; + __OM uint32_t TASKS_CSTONESSTART; /*!< (@ 0x000000A0) Start tone processing for channel sounding */ + __OM uint32_t TASKS_SOFTRESET; /*!< (@ 0x000000A4) Reset all public registers, but with these exceptions: + DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH + registers. Only to be used in DISABLED state.*/ + __IM uint32_t RESERVED3[22]; + __IOM uint32_t SUBSCRIBE_TXEN; /*!< (@ 0x00000100) Subscribe configuration for task TXEN */ + __IOM uint32_t SUBSCRIBE_RXEN; /*!< (@ 0x00000104) Subscribe configuration for task RXEN */ + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000108) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x0000010C) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_DISABLE; /*!< (@ 0x00000110) Subscribe configuration for task DISABLE */ + __IOM uint32_t SUBSCRIBE_RSSISTART; /*!< (@ 0x00000114) Subscribe configuration for task RSSISTART */ + __IOM uint32_t SUBSCRIBE_BCSTART; /*!< (@ 0x00000118) Subscribe configuration for task BCSTART */ + __IOM uint32_t SUBSCRIBE_BCSTOP; /*!< (@ 0x0000011C) Subscribe configuration for task BCSTOP */ + __IOM uint32_t SUBSCRIBE_EDSTART; /*!< (@ 0x00000120) Subscribe configuration for task EDSTART */ + __IOM uint32_t SUBSCRIBE_EDSTOP; /*!< (@ 0x00000124) Subscribe configuration for task EDSTOP */ + __IOM uint32_t SUBSCRIBE_CCASTART; /*!< (@ 0x00000128) Subscribe configuration for task CCASTART */ + __IOM uint32_t SUBSCRIBE_CCASTOP; /*!< (@ 0x0000012C) Subscribe configuration for task CCASTOP */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t SUBSCRIBE_AUXDATADMASTART; /*!< (@ 0x00000138) Subscribe configuration for task AUXDATADMASTART */ + __IOM uint32_t SUBSCRIBE_AUXDATADMASTOP; /*!< (@ 0x0000013C) Subscribe configuration for task AUXDATADMASTOP */ + __IM uint32_t RESERVED5[11]; + __IOM uint32_t SUBSCRIBE_PLLEN; /*!< (@ 0x0000016C) Subscribe configuration for task PLLEN */ + __IM uint32_t RESERVED6[12]; + __IOM uint32_t SUBSCRIBE_CSTONESSTART; /*!< (@ 0x000001A0) Subscribe configuration for task CSTONESSTART */ + __IOM uint32_t SUBSCRIBE_SOFTRESET; /*!< (@ 0x000001A4) Subscribe configuration for task SOFTRESET */ + __IM uint32_t RESERVED7[22]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000200) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000204) RADIO has ramped up and is ready to be started TX path*/ + __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000208) RADIO has ramped up and is ready to be started RX path*/ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x0000020C) Address sent or received */ + __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000210) IEEE 802.15.4 length field received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000214) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000218) Memory access for packet data has been completed */ + __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000021C) The last bit is sent on air or last bit is received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000220) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000224) A device address match occurred on the last received + packet*/ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000228) No device address match occurred on the last received + packet*/ + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x0000022C) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000230) Packet received with CRC error */ + __IM uint32_t RESERVED8; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000238) Bit counter reached bit count value */ + __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000023C) Sampling of energy detection complete (a new ED sample + is ready for readout from the RADIO.EDSAMPLE register)*/ + __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000240) The sampling of energy detection has stopped */ + __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000244) Wireless medium in idle - clear to send */ + __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000248) Wireless medium busy - do not send */ + __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000024C) The CCA has stopped */ + __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000250) Ble_LR CI field received, receive mode is changed from + Ble_LR125Kbit to Ble_LR500Kbit*/ + __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x00000254) MAC header match found */ + __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000258) Initial sync detected */ + __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x0000025C) CTEInfo byte is received */ + __IM uint32_t RESERVED9[20]; + __IOM uint32_t EVENTS_PLLREADY; /*!< (@ 0x000002B0) PLL has settled and RADIO is ready to be enabled in + either TX or RX mode*/ + __IM uint32_t RESERVED10[2]; + __IOM uint32_t EVENTS_RXADDRESS; /*!< (@ 0x000002BC) Address received */ + __IOM uint32_t EVENTS_AUXDATADMAEND; /*!< (@ 0x000002C0) AUXDATA DMA end */ + __IM uint32_t RESERVED11; + __IOM uint32_t EVENTS_CSTONESEND; /*!< (@ 0x000002C8) The channel sounding tone processing is complete */ + __IM uint32_t RESERVED12[13]; + __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000300) Publish configuration for event READY */ + __IOM uint32_t PUBLISH_TXREADY; /*!< (@ 0x00000304) Publish configuration for event TXREADY */ + __IOM uint32_t PUBLISH_RXREADY; /*!< (@ 0x00000308) Publish configuration for event RXREADY */ + __IOM uint32_t PUBLISH_ADDRESS; /*!< (@ 0x0000030C) Publish configuration for event ADDRESS */ + __IOM uint32_t PUBLISH_FRAMESTART; /*!< (@ 0x00000310) Publish configuration for event FRAMESTART */ + __IOM uint32_t PUBLISH_PAYLOAD; /*!< (@ 0x00000314) Publish configuration for event PAYLOAD */ + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000318) Publish configuration for event END */ + __IOM uint32_t PUBLISH_PHYEND; /*!< (@ 0x0000031C) Publish configuration for event PHYEND */ + __IOM uint32_t PUBLISH_DISABLED; /*!< (@ 0x00000320) Publish configuration for event DISABLED */ + __IOM uint32_t PUBLISH_DEVMATCH; /*!< (@ 0x00000324) Publish configuration for event DEVMATCH */ + __IOM uint32_t PUBLISH_DEVMISS; /*!< (@ 0x00000328) Publish configuration for event DEVMISS */ + __IOM uint32_t PUBLISH_CRCOK; /*!< (@ 0x0000032C) Publish configuration for event CRCOK */ + __IOM uint32_t PUBLISH_CRCERROR; /*!< (@ 0x00000330) Publish configuration for event CRCERROR */ + __IM uint32_t RESERVED13; + __IOM uint32_t PUBLISH_BCMATCH; /*!< (@ 0x00000338) Publish configuration for event BCMATCH */ + __IOM uint32_t PUBLISH_EDEND; /*!< (@ 0x0000033C) Publish configuration for event EDEND */ + __IOM uint32_t PUBLISH_EDSTOPPED; /*!< (@ 0x00000340) Publish configuration for event EDSTOPPED */ + __IOM uint32_t PUBLISH_CCAIDLE; /*!< (@ 0x00000344) Publish configuration for event CCAIDLE */ + __IOM uint32_t PUBLISH_CCABUSY; /*!< (@ 0x00000348) Publish configuration for event CCABUSY */ + __IOM uint32_t PUBLISH_CCASTOPPED; /*!< (@ 0x0000034C) Publish configuration for event CCASTOPPED */ + __IOM uint32_t PUBLISH_RATEBOOST; /*!< (@ 0x00000350) Publish configuration for event RATEBOOST */ + __IOM uint32_t PUBLISH_MHRMATCH; /*!< (@ 0x00000354) Publish configuration for event MHRMATCH */ + __IOM uint32_t PUBLISH_SYNC; /*!< (@ 0x00000358) Publish configuration for event SYNC */ + __IOM uint32_t PUBLISH_CTEPRESENT; /*!< (@ 0x0000035C) Publish configuration for event CTEPRESENT */ + __IM uint32_t RESERVED14[20]; + __IOM uint32_t PUBLISH_PLLREADY; /*!< (@ 0x000003B0) Publish configuration for event PLLREADY */ + __IM uint32_t RESERVED15[2]; + __IOM uint32_t PUBLISH_RXADDRESS; /*!< (@ 0x000003BC) Publish configuration for event RXADDRESS */ + __IOM uint32_t PUBLISH_AUXDATADMAEND; /*!< (@ 0x000003C0) Publish configuration for event AUXDATADMAEND */ + __IM uint32_t RESERVED16; + __IOM uint32_t PUBLISH_CSTONESEND; /*!< (@ 0x000003C8) Publish configuration for event CSTONESEND */ + __IM uint32_t RESERVED17[13]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000400) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED18[33]; + __IOM uint32_t INTENSET00; /*!< (@ 0x00000488) Enable interrupt */ + __IOM uint32_t INTENSET01; /*!< (@ 0x0000048C) Enable interrupt */ + __IOM uint32_t INTENCLR00; /*!< (@ 0x00000490) Disable interrupt */ + __IOM uint32_t INTENCLR01; /*!< (@ 0x00000494) Disable interrupt */ + __IM uint32_t RESERVED19[4]; + __IOM uint32_t INTENSET10; /*!< (@ 0x000004A8) Enable interrupt */ + __IOM uint32_t INTENSET11; /*!< (@ 0x000004AC) Enable interrupt */ + __IOM uint32_t INTENCLR10; /*!< (@ 0x000004B0) Disable interrupt */ + __IOM uint32_t INTENCLR11; /*!< (@ 0x000004B4) Disable interrupt */ + __IM uint32_t RESERVED20[18]; + __IOM uint32_t MODE; /*!< (@ 0x00000500) Data rate and modulation */ + __IM uint32_t RESERVED21[5]; + __IOM uint32_t PHYENDTXDELAY; /*!< (@ 0x00000518) Configurable delay of PHYEND event for TX */ + __IM uint32_t RESERVED22; + __IM uint32_t STATE; /*!< (@ 0x00000520) Current radio state */ + __IM uint32_t RESERVED23[3]; + __IOM uint32_t EDCTRL; /*!< (@ 0x00000530) IEEE 802.15.4 energy detect control */ + __IM uint32_t EDSAMPLE; /*!< (@ 0x00000534) IEEE 802.15.4 energy detect level */ + __IOM uint32_t CCACTRL; /*!< (@ 0x00000538) IEEE 802.15.4 clear channel assessment control */ + __IM uint32_t RESERVED24; + __IOM uint32_t DATAWHITE; /*!< (@ 0x00000540) Data whitening configuration */ + __IM uint32_t RESERVED25; + __IOM NRF_RADIO_AUXDATA_Type AUXDATA; /*!< (@ 0x00000548) (unspecified) */ + __IM uint32_t RESERVED26; + __IOM NRF_RADIO_AUXDATADMA_Type AUXDATADMA[1]; /*!< (@ 0x00000550) (unspecified) */ + __IM uint32_t RESERVED27[105]; + __IOM uint32_t TIMING; /*!< (@ 0x00000704) Timing */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000708) Frequency */ + __IM uint32_t RESERVED28; + __IOM uint32_t TXPOWER; /*!< (@ 0x00000710) Output power */ + __IOM uint32_t TIFS; /*!< (@ 0x00000714) Interframe spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000718) RSSI sample */ + __IM uint32_t RESERVED29[45]; + __IOM NRF_RADIO_RXGAIN_Type RXGAIN; /*!< (@ 0x000007D0) (unspecified) */ + __IM uint32_t RESERVED30[11]; + __IOM uint32_t FREQFINETUNE; /*!< (@ 0x00000804) Fine tuning of the RF frequency */ + __IM uint32_t RESERVED31[64]; + __IOM uint32_t FECONFIG; /*!< (@ 0x00000908) Config register */ + __IM uint32_t RESERVED32[125]; + __IM uint32_t CFO_STAT; /*!< (@ 0x00000B00) Carrier freq. offset estimate */ + __IM uint32_t RESERVED33[15]; + __IOM uint32_t DBCCORR; /*!< (@ 0x00000B40) Correlator thresholds */ + __IM uint32_t RESERVED34[111]; + __IOM uint32_t DFEMODE; /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or + Angle-of-Departure (AOD)*/ + __IM uint32_t DFESTATUS; /*!< (@ 0x00000D04) DFE status information */ + __IM uint32_t RESERVED35[2]; + __IOM uint32_t DFECTRL1; /*!< (@ 0x00000D10) Various configuration for Direction finding */ + __IOM uint32_t DFECTRL2; /*!< (@ 0x00000D14) Start offset for Direction finding */ + __IM uint32_t RESERVED36[4]; + __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna */ + __OM uint32_t CLEARPATTERN; /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control */ + __IOM NRF_RADIO_PSEL_Type PSEL; /*!< (@ 0x00000D30) (unspecified) */ + __IM uint32_t RESERVED37; + __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000D50) DFE packet EasyDMA channel */ + __IM uint32_t RESERVED38[43]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000E0C) CRC status */ + __IM uint32_t RXMATCH; /*!< (@ 0x00000E10) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x00000E14) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000E18) Device address match index */ + __IM uint32_t PDUSTAT; /*!< (@ 0x00000E1C) Payload status */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000E20) Packet configuration register 0 */ + __IM uint32_t RESERVED39; + __IOM uint32_t PCNF1; /*!< (@ 0x00000E28) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x00000E2C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000E30) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000E34) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000E38) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x00000E3C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000E40) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000E44) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000E48) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x00000E4C) CRC initial value */ + __IOM uint32_t DAB[8]; /*!< (@ 0x00000E50) Device address base segment n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000E70) Device address prefix n */ + __IOM uint32_t DACNF; /*!< (@ 0x00000E90) Device address match configuration */ + __IOM uint32_t BCC; /*!< (@ 0x00000E94) Bit counter compare */ + __IM uint32_t RESERVED40[3]; + __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ + __IM uint32_t RESERVED41[3]; + __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000EB4) Search pattern configuration */ + __IOM uint32_t MHRMATCHMASK; /*!< (@ 0x00000EB8) Pattern mask */ + __IOM uint32_t SFD; /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter */ + __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000EC0) Configuration for CTE inline mode */ + __IM uint32_t RESERVED42[3]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000ED0) Packet pointer */ + __IM uint32_t RESERVED43[75]; + __IOM NRF_RADIO_CSTONES_Type CSTONES; /*!< (@ 0x00001000) (unspecified) */ + __IM uint32_t RESERVED44[2]; + __IOM NRF_RADIO_RTT_Type RTT; /*!< (@ 0x00001050) (unspecified) */ + } NRF_RADIO_Type; /*!< Size = 4196 (0x1064) */ + +/* RADIO_TASKS_TXEN: Enable RADIO in TX mode */ + #define RADIO_TASKS_TXEN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TXEN register. */ + +/* TASKS_TXEN @Bit 0 : Enable RADIO in TX mode */ + #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ + #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ + #define RADIO_TASKS_TXEN_TASKS_TXEN_Min (0x1UL) /*!< Min enumerator value of TASKS_TXEN field. */ + #define RADIO_TASKS_TXEN_TASKS_TXEN_Max (0x1UL) /*!< Max enumerator value of TASKS_TXEN field. */ + #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_RXEN: Enable RADIO in RX mode */ + #define RADIO_TASKS_RXEN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RXEN register. */ + +/* TASKS_RXEN @Bit 0 : Enable RADIO in RX mode */ + #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ + #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ + #define RADIO_TASKS_RXEN_TASKS_RXEN_Min (0x1UL) /*!< Min enumerator value of TASKS_RXEN field. */ + #define RADIO_TASKS_RXEN_TASKS_RXEN_Max (0x1UL) /*!< Max enumerator value of TASKS_RXEN field. */ + #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_START: Start RADIO */ + #define RADIO_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start RADIO */ + #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define RADIO_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define RADIO_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define RADIO_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_STOP: Stop RADIO */ + #define RADIO_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop RADIO */ + #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define RADIO_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define RADIO_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_DISABLE: Disable RADIO */ + #define RADIO_TASKS_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_DISABLE register. */ + +/* TASKS_DISABLE @Bit 0 : Disable RADIO */ + #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ + #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE + field.*/ + #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Min (0x1UL) /*!< Min enumerator value of TASKS_DISABLE field. */ + #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Max (0x1UL) /*!< Max enumerator value of TASKS_DISABLE field. */ + #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_RSSISTART: Start the RSSI and take one single sample of the receive signal strength */ + #define RADIO_TASKS_RSSISTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RSSISTART register. */ + +/* TASKS_RSSISTART @Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ + #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ + #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of + TASKS_RSSISTART field.*/ + #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Min (0x1UL) /*!< Min enumerator value of TASKS_RSSISTART field. */ + #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Max (0x1UL) /*!< Max enumerator value of TASKS_RSSISTART field. */ + #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_BCSTART: Start the bit counter */ + #define RADIO_TASKS_BCSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_BCSTART register. */ + +/* TASKS_BCSTART @Bit 0 : Start the bit counter */ + #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ + #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART + field.*/ + #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_BCSTART field. */ + #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_BCSTART field. */ + #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_BCSTOP: Stop the bit counter */ + #define RADIO_TASKS_BCSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_BCSTOP register. */ + +/* TASKS_BCSTOP @Bit 0 : Stop the bit counter */ + #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ + #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP + field.*/ + #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_BCSTOP field. */ + #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_BCSTOP field. */ + #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_EDSTART: Start the energy detect measurement used in IEEE 802.15.4 mode */ + #define RADIO_TASKS_EDSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_EDSTART register. */ + +/* TASKS_EDSTART @Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */ + #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ + #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART + field.*/ + #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_EDSTART field. */ + #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_EDSTART field. */ + #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_EDSTOP: Stop the energy detect measurement */ + #define RADIO_TASKS_EDSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_EDSTOP register. */ + +/* TASKS_EDSTOP @Bit 0 : Stop the energy detect measurement */ + #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ + #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP + field.*/ + #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_EDSTOP field. */ + #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_EDSTOP field. */ + #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_CCASTART: Start the clear channel assessment used in IEEE 802.15.4 mode */ + #define RADIO_TASKS_CCASTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CCASTART register. */ + +/* TASKS_CCASTART @Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */ + #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ + #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of + TASKS_CCASTART field.*/ + #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Min (0x1UL) /*!< Min enumerator value of TASKS_CCASTART field. */ + #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Max (0x1UL) /*!< Max enumerator value of TASKS_CCASTART field. */ + #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_CCASTOP: Stop the clear channel assessment */ + #define RADIO_TASKS_CCASTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CCASTOP register. */ + +/* TASKS_CCASTOP @Bit 0 : Stop the clear channel assessment */ + #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ + #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP + field.*/ + #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_CCASTOP field. */ + #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_CCASTOP field. */ + #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_AUXDATADMASTART: Start DMA transaction of acquisition */ + #define RADIO_TASKS_AUXDATADMASTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_AUXDATADMASTART register. */ + +/* TASKS_AUXDATADMASTART @Bit 0 : Start DMA transaction of acquisition */ + #define RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Pos (0UL) /*!< Position of TASKS_AUXDATADMASTART field. */ + #define RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Msk (0x1UL << RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Pos) + /*!< Bit mask of TASKS_AUXDATADMASTART field.*/ + #define RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Min (0x1UL) /*!< Min enumerator value of TASKS_AUXDATADMASTART + field.*/ + #define RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Max (0x1UL) /*!< Max enumerator value of TASKS_AUXDATADMASTART + field.*/ + #define RADIO_TASKS_AUXDATADMASTART_TASKS_AUXDATADMASTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_AUXDATADMASTOP: Stop ongoing DMA transaction of acquisition */ + #define RADIO_TASKS_AUXDATADMASTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_AUXDATADMASTOP register. */ + +/* TASKS_AUXDATADMASTOP @Bit 0 : Stop ongoing DMA transaction of acquisition */ + #define RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Pos (0UL) /*!< Position of TASKS_AUXDATADMASTOP field. */ + #define RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Msk (0x1UL << RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Pos) + /*!< Bit mask of TASKS_AUXDATADMASTOP field.*/ + #define RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_AUXDATADMASTOP field. */ + #define RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_AUXDATADMASTOP field. */ + #define RADIO_TASKS_AUXDATADMASTOP_TASKS_AUXDATADMASTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_PLLEN: Enable RADIO in PLL mode (standby for either TX or RX) */ + #define RADIO_TASKS_PLLEN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PLLEN register. */ + +/* TASKS_PLLEN @Bit 0 : Enable RADIO in PLL mode (standby for either TX or RX) */ + #define RADIO_TASKS_PLLEN_TASKS_PLLEN_Pos (0UL) /*!< Position of TASKS_PLLEN field. */ + #define RADIO_TASKS_PLLEN_TASKS_PLLEN_Msk (0x1UL << RADIO_TASKS_PLLEN_TASKS_PLLEN_Pos) /*!< Bit mask of TASKS_PLLEN field. */ + #define RADIO_TASKS_PLLEN_TASKS_PLLEN_Min (0x1UL) /*!< Min enumerator value of TASKS_PLLEN field. */ + #define RADIO_TASKS_PLLEN_TASKS_PLLEN_Max (0x1UL) /*!< Max enumerator value of TASKS_PLLEN field. */ + #define RADIO_TASKS_PLLEN_TASKS_PLLEN_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_CSTONESSTART: Start tone processing for channel sounding */ + #define RADIO_TASKS_CSTONESSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CSTONESSTART register. */ + +/* TASKS_CSTONESSTART @Bit 0 : Start tone processing for channel sounding */ + #define RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Pos (0UL) /*!< Position of TASKS_CSTONESSTART field. */ + #define RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Msk (0x1UL << RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Pos) /*!< Bit + mask of TASKS_CSTONESSTART field.*/ + #define RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_CSTONESSTART field. */ + #define RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_CSTONESSTART field. */ + #define RADIO_TASKS_CSTONESSTART_TASKS_CSTONESSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_SOFTRESET: Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH + registers. Only to be used in DISABLED state. */ + + #define RADIO_TASKS_SOFTRESET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SOFTRESET register. */ + +/* TASKS_SOFTRESET @Bit 0 : Reset all public registers, but with these exceptions: DMA registers and + EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. */ + + #define RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Pos (0UL) /*!< Position of TASKS_SOFTRESET field. */ + #define RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Msk (0x1UL << RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Pos) /*!< Bit mask of + TASKS_SOFTRESET field.*/ + #define RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Min (0x1UL) /*!< Min enumerator value of TASKS_SOFTRESET field. */ + #define RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Max (0x1UL) /*!< Max enumerator value of TASKS_SOFTRESET field. */ + #define RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_SUBSCRIBE_TXEN: Subscribe configuration for task TXEN */ + #define RADIO_SUBSCRIBE_TXEN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TXEN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task TXEN will subscribe to */ + #define RADIO_SUBSCRIBE_TXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_TXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_TXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_TXEN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_TXEN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_TXEN_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_TXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_TXEN_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_TXEN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_TXEN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_TXEN_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_TXEN_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_RXEN: Subscribe configuration for task RXEN */ + #define RADIO_SUBSCRIBE_RXEN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RXEN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RXEN will subscribe to */ + #define RADIO_SUBSCRIBE_RXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_RXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_RXEN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_RXEN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_RXEN_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_RXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RXEN_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_RXEN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_RXEN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_RXEN_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_RXEN_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_START: Subscribe configuration for task START */ + #define RADIO_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define RADIO_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_START_EN_Msk (0x1UL << RADIO_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define RADIO_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define RADIO_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_STOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_DISABLE: Subscribe configuration for task DISABLE */ + #define RADIO_SUBSCRIBE_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_DISABLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLE will subscribe to */ + #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << RADIO_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_RSSISTART: Subscribe configuration for task RSSISTART */ + #define RADIO_SUBSCRIBE_RSSISTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RSSISTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RSSISTART will subscribe to */ + #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_BCSTART: Subscribe configuration for task BCSTART */ + #define RADIO_SUBSCRIBE_BCSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_BCSTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task BCSTART will subscribe to */ + #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_BCSTOP: Subscribe configuration for task BCSTOP */ + #define RADIO_SUBSCRIBE_BCSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_BCSTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task BCSTOP will subscribe to */ + #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_EDSTART: Subscribe configuration for task EDSTART */ + #define RADIO_SUBSCRIBE_EDSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_EDSTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task EDSTART will subscribe to */ + #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_EDSTOP: Subscribe configuration for task EDSTOP */ + #define RADIO_SUBSCRIBE_EDSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_EDSTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task EDSTOP will subscribe to */ + #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_CCASTART: Subscribe configuration for task CCASTART */ + #define RADIO_SUBSCRIBE_CCASTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CCASTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CCASTART will subscribe to */ + #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_CCASTOP: Subscribe configuration for task CCASTOP */ + #define RADIO_SUBSCRIBE_CCASTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CCASTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CCASTOP will subscribe to */ + #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_AUXDATADMASTART: Subscribe configuration for task AUXDATADMASTART */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_AUXDATADMASTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task AUXDATADMASTART will subscribe to */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_AUXDATADMASTART_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_AUXDATADMASTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_AUXDATADMASTOP: Subscribe configuration for task AUXDATADMASTOP */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_AUXDATADMASTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task AUXDATADMASTOP will subscribe to */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_AUXDATADMASTOP_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_AUXDATADMASTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_PLLEN: Subscribe configuration for task PLLEN */ + #define RADIO_SUBSCRIBE_PLLEN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PLLEN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task PLLEN will subscribe to */ + #define RADIO_SUBSCRIBE_PLLEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_PLLEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_PLLEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_PLLEN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_PLLEN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_PLLEN_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_PLLEN_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_CSTONESSTART: Subscribe configuration for task CSTONESSTART */ + #define RADIO_SUBSCRIBE_CSTONESSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CSTONESSTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CSTONESSTART will subscribe to */ + #define RADIO_SUBSCRIBE_CSTONESSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CSTONESSTART_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define RADIO_SUBSCRIBE_CSTONESSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CSTONESSTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_CSTONESSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_SOFTRESET: Subscribe configuration for task SOFTRESET */ + #define RADIO_SUBSCRIBE_SOFTRESET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SOFTRESET register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SOFTRESET will subscribe to */ + #define RADIO_SUBSCRIBE_SOFTRESET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_SOFTRESET_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_SOFTRESET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_SOFTRESET_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_SOFTRESET_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_SOFTRESET_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_SOFTRESET_EN_Msk (0x1UL << RADIO_SUBSCRIBE_SOFTRESET_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_SOFTRESET_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_SOFTRESET_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_SOFTRESET_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_SOFTRESET_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_EVENTS_READY: RADIO has ramped up and is ready to be started */ + #define RADIO_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register. */ + +/* EVENTS_READY @Bit 0 : RADIO has ramped up and is ready to be started */ + #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ + #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY + field.*/ + #define RADIO_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field. */ + #define RADIO_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field. */ + #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_TXREADY: RADIO has ramped up and is ready to be started TX path */ + #define RADIO_EVENTS_TXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXREADY register. */ + +/* EVENTS_TXREADY @Bit 0 : RADIO has ramped up and is ready to be started TX path */ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of + EVENTS_TXREADY field.*/ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXREADY field. */ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXREADY field. */ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_RXREADY: RADIO has ramped up and is ready to be started RX path */ + #define RADIO_EVENTS_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXREADY register. */ + +/* EVENTS_RXREADY @Bit 0 : RADIO has ramped up and is ready to be started RX path */ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of + EVENTS_RXREADY field.*/ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXREADY field. */ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXREADY field. */ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_ADDRESS: Address sent or received */ + #define RADIO_EVENTS_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ADDRESS register. */ + +/* EVENTS_ADDRESS @Bit 0 : Address sent or received */ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of + EVENTS_ADDRESS field.*/ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Min (0x0UL) /*!< Min enumerator value of EVENTS_ADDRESS field. */ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Max (0x1UL) /*!< Max enumerator value of EVENTS_ADDRESS field. */ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_FRAMESTART: IEEE 802.15.4 length field received */ + #define RADIO_EVENTS_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FRAMESTART register. */ + +/* EVENTS_FRAMESTART @Bit 0 : IEEE 802.15.4 length field received */ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask + of EVENTS_FRAMESTART field.*/ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_FRAMESTART field. */ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_FRAMESTART field. */ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_PAYLOAD: Packet payload sent or received */ + #define RADIO_EVENTS_PAYLOAD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PAYLOAD register. */ + +/* EVENTS_PAYLOAD @Bit 0 : Packet payload sent or received */ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of + EVENTS_PAYLOAD field.*/ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of EVENTS_PAYLOAD field. */ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of EVENTS_PAYLOAD field. */ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_END: Memory access for packet data has been completed */ + #define RADIO_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : Memory access for packet data has been completed */ + #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define RADIO_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define RADIO_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_PHYEND: The last bit is sent on air or last bit is received */ + #define RADIO_EVENTS_PHYEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PHYEND register. */ + +/* EVENTS_PHYEND @Bit 0 : The last bit is sent on air or last bit is received */ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND + field.*/ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_PHYEND field. */ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_PHYEND field. */ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_DISABLED: RADIO has been disabled */ + #define RADIO_EVENTS_DISABLED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DISABLED register. */ + +/* EVENTS_DISABLED @Bit 0 : RADIO has been disabled */ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of + EVENTS_DISABLED field.*/ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Min (0x0UL) /*!< Min enumerator value of EVENTS_DISABLED field. */ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Max (0x1UL) /*!< Max enumerator value of EVENTS_DISABLED field. */ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_DEVMATCH: A device address match occurred on the last received packet */ + #define RADIO_EVENTS_DEVMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DEVMATCH register. */ + +/* EVENTS_DEVMATCH @Bit 0 : A device address match occurred on the last received packet */ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of + EVENTS_DEVMATCH field.*/ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_DEVMATCH field. */ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_DEVMATCH field. */ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_DEVMISS: No device address match occurred on the last received packet */ + #define RADIO_EVENTS_DEVMISS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DEVMISS register. */ + +/* EVENTS_DEVMISS @Bit 0 : No device address match occurred on the last received packet */ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of + EVENTS_DEVMISS field.*/ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Min (0x0UL) /*!< Min enumerator value of EVENTS_DEVMISS field. */ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Max (0x1UL) /*!< Max enumerator value of EVENTS_DEVMISS field. */ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CRCOK: Packet received with CRC ok */ + #define RADIO_EVENTS_CRCOK_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CRCOK register. */ + +/* EVENTS_CRCOK @Bit 0 : Packet received with CRC ok */ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK + field.*/ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Min (0x0UL) /*!< Min enumerator value of EVENTS_CRCOK field. */ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Max (0x1UL) /*!< Max enumerator value of EVENTS_CRCOK field. */ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CRCERROR: Packet received with CRC error */ + #define RADIO_EVENTS_CRCERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CRCERROR register. */ + +/* EVENTS_CRCERROR @Bit 0 : Packet received with CRC error */ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of + EVENTS_CRCERROR field.*/ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_CRCERROR field. */ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_CRCERROR field. */ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_BCMATCH: Bit counter reached bit count value */ + #define RADIO_EVENTS_BCMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_BCMATCH register. */ + +/* EVENTS_BCMATCH @Bit 0 : Bit counter reached bit count value */ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of + EVENTS_BCMATCH field.*/ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_BCMATCH field. */ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_BCMATCH field. */ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_EDEND: Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE + register) */ + + #define RADIO_EVENTS_EDEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_EDEND register. */ + +/* EVENTS_EDEND @Bit 0 : Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE + register) */ + + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND + field.*/ + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_EDEND field. */ + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_EDEND field. */ + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_EDSTOPPED: The sampling of energy detection has stopped */ + #define RADIO_EVENTS_EDSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_EDSTOPPED register. */ + +/* EVENTS_EDSTOPPED @Bit 0 : The sampling of energy detection has stopped */ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of + EVENTS_EDSTOPPED field.*/ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_EDSTOPPED field. */ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_EDSTOPPED field. */ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CCAIDLE: Wireless medium in idle - clear to send */ + #define RADIO_EVENTS_CCAIDLE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCAIDLE register. */ + +/* EVENTS_CCAIDLE @Bit 0 : Wireless medium in idle - clear to send */ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of + EVENTS_CCAIDLE field.*/ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCAIDLE field. */ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCAIDLE field. */ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CCABUSY: Wireless medium busy - do not send */ + #define RADIO_EVENTS_CCABUSY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCABUSY register. */ + +/* EVENTS_CCABUSY @Bit 0 : Wireless medium busy - do not send */ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of + EVENTS_CCABUSY field.*/ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCABUSY field. */ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCABUSY field. */ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CCASTOPPED: The CCA has stopped */ + #define RADIO_EVENTS_CCASTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCASTOPPED register. */ + +/* EVENTS_CCASTOPPED @Bit 0 : The CCA has stopped */ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask + of EVENTS_CCASTOPPED field.*/ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCASTOPPED field. */ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCASTOPPED field. */ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_RATEBOOST: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit */ + #define RADIO_EVENTS_RATEBOOST_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RATEBOOST register. */ + +/* EVENTS_RATEBOOST @Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit */ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of + EVENTS_RATEBOOST field.*/ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of EVENTS_RATEBOOST field. */ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of EVENTS_RATEBOOST field. */ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_MHRMATCH: MAC header match found */ + #define RADIO_EVENTS_MHRMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_MHRMATCH register. */ + +/* EVENTS_MHRMATCH @Bit 0 : MAC header match found */ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of + EVENTS_MHRMATCH field.*/ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_MHRMATCH field. */ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_MHRMATCH field. */ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_SYNC: Initial sync detected */ + #define RADIO_EVENTS_SYNC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SYNC register. */ + +/* EVENTS_SYNC @Bit 0 : Initial sync detected */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Min (0x0UL) /*!< Min enumerator value of EVENTS_SYNC field. */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Max (0x1UL) /*!< Max enumerator value of EVENTS_SYNC field. */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CTEPRESENT: CTEInfo byte is received */ + #define RADIO_EVENTS_CTEPRESENT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CTEPRESENT register. */ + +/* EVENTS_CTEPRESENT @Bit 0 : CTEInfo byte is received */ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask + of EVENTS_CTEPRESENT field.*/ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of EVENTS_CTEPRESENT field. */ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of EVENTS_CTEPRESENT field. */ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_PLLREADY: PLL has settled and RADIO is ready to be enabled in either TX or RX mode */ + #define RADIO_EVENTS_PLLREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PLLREADY register. */ + +/* EVENTS_PLLREADY @Bit 0 : PLL has settled and RADIO is ready to be enabled in either TX or RX mode */ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Pos (0UL) /*!< Position of EVENTS_PLLREADY field. */ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Msk (0x1UL << RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Pos) /*!< Bit mask of + EVENTS_PLLREADY field.*/ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_PLLREADY field. */ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_PLLREADY field. */ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_PLLREADY_EVENTS_PLLREADY_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_RXADDRESS: Address received */ + #define RADIO_EVENTS_RXADDRESS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXADDRESS register. */ + +/* EVENTS_RXADDRESS @Bit 0 : Address received */ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Pos (0UL) /*!< Position of EVENTS_RXADDRESS field. */ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Msk (0x1UL << RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Pos) /*!< Bit mask of + EVENTS_RXADDRESS field.*/ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXADDRESS field. */ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXADDRESS field. */ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_RXADDRESS_EVENTS_RXADDRESS_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_AUXDATADMAEND: AUXDATA DMA end */ + #define RADIO_EVENTS_AUXDATADMAEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_AUXDATADMAEND register. */ + +/* EVENTS_AUXDATADMAEND @Bit 0 : AUXDATA DMA end */ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Pos (0UL) /*!< Position of EVENTS_AUXDATADMAEND field. */ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Msk (0x1UL << RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Pos) + /*!< Bit mask of EVENTS_AUXDATADMAEND field.*/ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_AUXDATADMAEND field. */ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_AUXDATADMAEND field. */ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_AUXDATADMAEND_EVENTS_AUXDATADMAEND_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CSTONESEND: The channel sounding tone processing is complete */ + #define RADIO_EVENTS_CSTONESEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CSTONESEND register. */ + +/* EVENTS_CSTONESEND @Bit 0 : The channel sounding tone processing is complete */ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Pos (0UL) /*!< Position of EVENTS_CSTONESEND field. */ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Msk (0x1UL << RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Pos) /*!< Bit mask + of EVENTS_CSTONESEND field.*/ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_CSTONESEND field. */ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_CSTONESEND field. */ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CSTONESEND_EVENTS_CSTONESEND_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_PUBLISH_READY: Publish configuration for event READY */ + #define RADIO_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define RADIO_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_READY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_READY_EN_Msk (0x1UL << RADIO_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_TXREADY: Publish configuration for event TXREADY */ + #define RADIO_PUBLISH_TXREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXREADY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TXREADY will publish to */ + #define RADIO_PUBLISH_TXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_TXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_TXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_TXREADY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_TXREADY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_TXREADY_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_TXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_TXREADY_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_TXREADY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_TXREADY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_TXREADY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_TXREADY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_RXREADY: Publish configuration for event RXREADY */ + #define RADIO_PUBLISH_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXREADY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXREADY will publish to */ + #define RADIO_PUBLISH_RXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_RXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_RXREADY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_RXREADY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_RXREADY_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_RXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_RXREADY_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_RXREADY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_RXREADY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_RXREADY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_RXREADY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_ADDRESS: Publish configuration for event ADDRESS */ + #define RADIO_PUBLISH_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ADDRESS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ADDRESS will publish to */ + #define RADIO_PUBLISH_ADDRESS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_ADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_ADDRESS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_ADDRESS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_ADDRESS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_ADDRESS_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_ADDRESS_EN_Msk (0x1UL << RADIO_PUBLISH_ADDRESS_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_ADDRESS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_ADDRESS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_ADDRESS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_ADDRESS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_FRAMESTART: Publish configuration for event FRAMESTART */ + #define RADIO_PUBLISH_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FRAMESTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event FRAMESTART will publish to */ + #define RADIO_PUBLISH_FRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_FRAMESTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_FRAMESTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_FRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_FRAMESTART_EN_Msk (0x1UL << RADIO_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_FRAMESTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_FRAMESTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_FRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_FRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_PAYLOAD: Publish configuration for event PAYLOAD */ + #define RADIO_PUBLISH_PAYLOAD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PAYLOAD register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PAYLOAD will publish to */ + #define RADIO_PUBLISH_PAYLOAD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_PAYLOAD_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PAYLOAD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_PAYLOAD_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_PAYLOAD_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_PAYLOAD_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_PAYLOAD_EN_Msk (0x1UL << RADIO_PUBLISH_PAYLOAD_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_PAYLOAD_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_PAYLOAD_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_PAYLOAD_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_PAYLOAD_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_END: Publish configuration for event END */ + #define RADIO_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define RADIO_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_END_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_END_EN_Msk (0x1UL << RADIO_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_PHYEND: Publish configuration for event PHYEND */ + #define RADIO_PUBLISH_PHYEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PHYEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PHYEND will publish to */ + #define RADIO_PUBLISH_PHYEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_PHYEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PHYEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_PHYEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_PHYEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_PHYEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_PHYEND_EN_Msk (0x1UL << RADIO_PUBLISH_PHYEND_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_PHYEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_PHYEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_PHYEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_PHYEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_DISABLED: Publish configuration for event DISABLED */ + #define RADIO_PUBLISH_DISABLED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DISABLED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DISABLED will publish to */ + #define RADIO_PUBLISH_DISABLED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_DISABLED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DISABLED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_DISABLED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_DISABLED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_DISABLED_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_DISABLED_EN_Msk (0x1UL << RADIO_PUBLISH_DISABLED_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_DISABLED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_DISABLED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_DISABLED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_DISABLED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_DEVMATCH: Publish configuration for event DEVMATCH */ + #define RADIO_PUBLISH_DEVMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DEVMATCH register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DEVMATCH will publish to */ + #define RADIO_PUBLISH_DEVMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_DEVMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_DEVMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_DEVMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_DEVMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_DEVMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_DEVMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_DEVMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_DEVMATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_DEVMATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_DEVMISS: Publish configuration for event DEVMISS */ + #define RADIO_PUBLISH_DEVMISS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DEVMISS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DEVMISS will publish to */ + #define RADIO_PUBLISH_DEVMISS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_DEVMISS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMISS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_DEVMISS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_DEVMISS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_DEVMISS_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_DEVMISS_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMISS_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_DEVMISS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_DEVMISS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_DEVMISS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_DEVMISS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CRCOK: Publish configuration for event CRCOK */ + #define RADIO_PUBLISH_CRCOK_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CRCOK register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CRCOK will publish to */ + #define RADIO_PUBLISH_CRCOK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CRCOK_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCOK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CRCOK_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CRCOK_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CRCOK_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CRCOK_EN_Msk (0x1UL << RADIO_PUBLISH_CRCOK_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CRCOK_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CRCOK_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CRCOK_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CRCOK_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CRCERROR: Publish configuration for event CRCERROR */ + #define RADIO_PUBLISH_CRCERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CRCERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CRCERROR will publish to */ + #define RADIO_PUBLISH_CRCERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CRCERROR_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CRCERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CRCERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CRCERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CRCERROR_EN_Msk (0x1UL << RADIO_PUBLISH_CRCERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CRCERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CRCERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CRCERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CRCERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_BCMATCH: Publish configuration for event BCMATCH */ + #define RADIO_PUBLISH_BCMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_BCMATCH register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BCMATCH will publish to */ + #define RADIO_PUBLISH_BCMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_BCMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_BCMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_BCMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_BCMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_BCMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_BCMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_BCMATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_BCMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_BCMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_BCMATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_BCMATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_EDEND: Publish configuration for event EDEND */ + #define RADIO_PUBLISH_EDEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_EDEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event EDEND will publish to */ + #define RADIO_PUBLISH_EDEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_EDEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_EDEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_EDEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_EDEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_EDEND_EN_Msk (0x1UL << RADIO_PUBLISH_EDEND_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_EDEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_EDEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_EDEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_EDEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_EDSTOPPED: Publish configuration for event EDSTOPPED */ + #define RADIO_PUBLISH_EDSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_EDSTOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event EDSTOPPED will publish to */ + #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_EDSTOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CCAIDLE: Publish configuration for event CCAIDLE */ + #define RADIO_PUBLISH_CCAIDLE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCAIDLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CCAIDLE will publish to */ + #define RADIO_PUBLISH_CCAIDLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CCAIDLE_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCAIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CCAIDLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CCAIDLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CCAIDLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CCAIDLE_EN_Msk (0x1UL << RADIO_PUBLISH_CCAIDLE_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CCAIDLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CCAIDLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CCAIDLE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CCAIDLE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CCABUSY: Publish configuration for event CCABUSY */ + #define RADIO_PUBLISH_CCABUSY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCABUSY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CCABUSY will publish to */ + #define RADIO_PUBLISH_CCABUSY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CCABUSY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCABUSY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CCABUSY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CCABUSY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CCABUSY_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CCABUSY_EN_Msk (0x1UL << RADIO_PUBLISH_CCABUSY_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CCABUSY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CCABUSY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CCABUSY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CCABUSY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CCASTOPPED: Publish configuration for event CCASTOPPED */ + #define RADIO_PUBLISH_CCASTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCASTOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CCASTOPPED will publish to */ + #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_CCASTOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_RATEBOOST: Publish configuration for event RATEBOOST */ + #define RADIO_PUBLISH_RATEBOOST_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RATEBOOST register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RATEBOOST will publish to */ + #define RADIO_PUBLISH_RATEBOOST_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_RATEBOOST_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RATEBOOST_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_RATEBOOST_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_RATEBOOST_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_RATEBOOST_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_RATEBOOST_EN_Msk (0x1UL << RADIO_PUBLISH_RATEBOOST_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_RATEBOOST_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_RATEBOOST_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_RATEBOOST_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_RATEBOOST_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_MHRMATCH: Publish configuration for event MHRMATCH */ + #define RADIO_PUBLISH_MHRMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_MHRMATCH register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MHRMATCH will publish to */ + #define RADIO_PUBLISH_MHRMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_MHRMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_MHRMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_MHRMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_MHRMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_MHRMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_MHRMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_MHRMATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_MHRMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_MHRMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_MHRMATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_MHRMATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_SYNC: Publish configuration for event SYNC */ + #define RADIO_PUBLISH_SYNC_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SYNC register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SYNC will publish to */ + #define RADIO_PUBLISH_SYNC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_SYNC_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_SYNC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_SYNC_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_SYNC_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_SYNC_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_SYNC_EN_Msk (0x1UL << RADIO_PUBLISH_SYNC_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_SYNC_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_SYNC_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_SYNC_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_SYNC_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CTEPRESENT: Publish configuration for event CTEPRESENT */ + #define RADIO_PUBLISH_CTEPRESENT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CTEPRESENT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CTEPRESENT will publish to */ + #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Msk (0x1UL << RADIO_PUBLISH_CTEPRESENT_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_PLLREADY: Publish configuration for event PLLREADY */ + #define RADIO_PUBLISH_PLLREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PLLREADY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PLLREADY will publish to */ + #define RADIO_PUBLISH_PLLREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_PLLREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PLLREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_PLLREADY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_PLLREADY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_PLLREADY_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_PLLREADY_EN_Msk (0x1UL << RADIO_PUBLISH_PLLREADY_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_PLLREADY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_PLLREADY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_PLLREADY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_PLLREADY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_RXADDRESS: Publish configuration for event RXADDRESS */ + #define RADIO_PUBLISH_RXADDRESS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXADDRESS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXADDRESS will publish to */ + #define RADIO_PUBLISH_RXADDRESS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_RXADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXADDRESS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_RXADDRESS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_RXADDRESS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_RXADDRESS_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_RXADDRESS_EN_Msk (0x1UL << RADIO_PUBLISH_RXADDRESS_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_RXADDRESS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_RXADDRESS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_RXADDRESS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_RXADDRESS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_AUXDATADMAEND: Publish configuration for event AUXDATADMAEND */ + #define RADIO_PUBLISH_AUXDATADMAEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_AUXDATADMAEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event AUXDATADMAEND will publish to */ + #define RADIO_PUBLISH_AUXDATADMAEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_AUXDATADMAEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define RADIO_PUBLISH_AUXDATADMAEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Msk (0x1UL << RADIO_PUBLISH_AUXDATADMAEND_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_AUXDATADMAEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CSTONESEND: Publish configuration for event CSTONESEND */ + #define RADIO_PUBLISH_CSTONESEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CSTONESEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CSTONESEND will publish to */ + #define RADIO_PUBLISH_CSTONESEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CSTONESEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CSTONESEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CSTONESEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CSTONESEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CSTONESEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CSTONESEND_EN_Msk (0x1UL << RADIO_PUBLISH_CSTONESEND_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CSTONESEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CSTONESEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CSTONESEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CSTONESEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_SHORTS: Shortcuts between local events and tasks */ + #define RADIO_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* READY_START @Bit 0 : Shortcut between event READY and task START */ + #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ + #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ + #define RADIO_SHORTS_READY_START_Min (0x0UL) /*!< Min enumerator value of READY_START field. */ + #define RADIO_SHORTS_READY_START_Max (0x1UL) /*!< Max enumerator value of READY_START field. */ + #define RADIO_SHORTS_READY_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_READY_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DISABLED_TXEN @Bit 2 : Shortcut between event DISABLED and task TXEN */ + #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ + #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ + #define RADIO_SHORTS_DISABLED_TXEN_Min (0x0UL) /*!< Min enumerator value of DISABLED_TXEN field. */ + #define RADIO_SHORTS_DISABLED_TXEN_Max (0x1UL) /*!< Max enumerator value of DISABLED_TXEN field. */ + #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_DISABLED_TXEN_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DISABLED_RXEN @Bit 3 : Shortcut between event DISABLED and task RXEN */ + #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ + #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ + #define RADIO_SHORTS_DISABLED_RXEN_Min (0x0UL) /*!< Min enumerator value of DISABLED_RXEN field. */ + #define RADIO_SHORTS_DISABLED_RXEN_Max (0x1UL) /*!< Max enumerator value of DISABLED_RXEN field. */ + #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_DISABLED_RXEN_Enabled (0x1UL) /*!< Enable shortcut */ + +/* ADDRESS_RSSISTART @Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART + field.*/ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Min (0x0UL) /*!< Min enumerator value of ADDRESS_RSSISTART field. */ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Max (0x1UL) /*!< Max enumerator value of ADDRESS_RSSISTART field. */ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (0x1UL) /*!< Enable shortcut */ + +/* END_START @Bit 5 : Shortcut between event END and task START */ + #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ + #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ + #define RADIO_SHORTS_END_START_Min (0x0UL) /*!< Min enumerator value of END_START field. */ + #define RADIO_SHORTS_END_START_Max (0x1UL) /*!< Max enumerator value of END_START field. */ + #define RADIO_SHORTS_END_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_END_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* ADDRESS_BCSTART @Bit 6 : Shortcut between event ADDRESS and task BCSTART */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Min (0x0UL) /*!< Min enumerator value of ADDRESS_BCSTART field. */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Max (0x1UL) /*!< Max enumerator value of ADDRESS_BCSTART field. */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (0x1UL) /*!< Enable shortcut */ + +/* PHYEND_PLLEN @Bit 7 : Shortcut between event PHYEND and task PLLEN */ + #define RADIO_SHORTS_PHYEND_PLLEN_Pos (7UL) /*!< Position of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Msk (0x1UL << RADIO_SHORTS_PHYEND_PLLEN_Pos) /*!< Bit mask of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Min (0x0UL) /*!< Min enumerator value of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Max (0x1UL) /*!< Max enumerator value of PHYEND_PLLEN field. */ + #define RADIO_SHORTS_PHYEND_PLLEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PHYEND_PLLEN_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RXREADY_CCASTART @Bit 10 : Shortcut between event RXREADY and task CCASTART */ + #define RADIO_SHORTS_RXREADY_CCASTART_Pos (10UL) /*!< Position of RXREADY_CCASTART field. */ + #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART + field.*/ + #define RADIO_SHORTS_RXREADY_CCASTART_Min (0x0UL) /*!< Min enumerator value of RXREADY_CCASTART field. */ + #define RADIO_SHORTS_RXREADY_CCASTART_Max (0x1UL) /*!< Max enumerator value of RXREADY_CCASTART field. */ + #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (0x1UL) /*!< Enable shortcut */ + +/* CCAIDLE_TXEN @Bit 11 : Shortcut between event CCAIDLE and task TXEN */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (11UL) /*!< Position of CCAIDLE_TXEN field. */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Min (0x0UL) /*!< Min enumerator value of CCAIDLE_TXEN field. */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Max (0x1UL) /*!< Max enumerator value of CCAIDLE_TXEN field. */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (0x1UL) /*!< Enable shortcut */ + +/* CCABUSY_DISABLE @Bit 12 : Shortcut between event CCABUSY and task DISABLE */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (12UL) /*!< Position of CCABUSY_DISABLE field. */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Min (0x0UL) /*!< Min enumerator value of CCABUSY_DISABLE field. */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Max (0x1UL) /*!< Max enumerator value of CCABUSY_DISABLE field. */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* FRAMESTART_BCSTART @Bit 13 : Shortcut between event FRAMESTART and task BCSTART */ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (13UL) /*!< Position of FRAMESTART_BCSTART field. */ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART + field.*/ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART_BCSTART field. */ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART_BCSTART field. */ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (0x1UL) /*!< Enable shortcut */ + +/* READY_EDSTART @Bit 14 : Shortcut between event READY and task EDSTART */ + #define RADIO_SHORTS_READY_EDSTART_Pos (14UL) /*!< Position of READY_EDSTART field. */ + #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ + #define RADIO_SHORTS_READY_EDSTART_Min (0x0UL) /*!< Min enumerator value of READY_EDSTART field. */ + #define RADIO_SHORTS_READY_EDSTART_Max (0x1UL) /*!< Max enumerator value of READY_EDSTART field. */ + #define RADIO_SHORTS_READY_EDSTART_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_READY_EDSTART_Enabled (0x1UL) /*!< Enable shortcut */ + +/* EDEND_DISABLE @Bit 15 : Shortcut between event EDEND and task DISABLE */ + #define RADIO_SHORTS_EDEND_DISABLE_Pos (15UL) /*!< Position of EDEND_DISABLE field. */ + #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ + #define RADIO_SHORTS_EDEND_DISABLE_Min (0x0UL) /*!< Min enumerator value of EDEND_DISABLE field. */ + #define RADIO_SHORTS_EDEND_DISABLE_Max (0x1UL) /*!< Max enumerator value of EDEND_DISABLE field. */ + #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_EDEND_DISABLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* CCAIDLE_STOP @Bit 16 : Shortcut between event CCAIDLE and task STOP */ + #define RADIO_SHORTS_CCAIDLE_STOP_Pos (16UL) /*!< Position of CCAIDLE_STOP field. */ + #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ + #define RADIO_SHORTS_CCAIDLE_STOP_Min (0x0UL) /*!< Min enumerator value of CCAIDLE_STOP field. */ + #define RADIO_SHORTS_CCAIDLE_STOP_Max (0x1UL) /*!< Max enumerator value of CCAIDLE_STOP field. */ + #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* TXREADY_START @Bit 17 : Shortcut between event TXREADY and task START */ + #define RADIO_SHORTS_TXREADY_START_Pos (17UL) /*!< Position of TXREADY_START field. */ + #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ + #define RADIO_SHORTS_TXREADY_START_Min (0x0UL) /*!< Min enumerator value of TXREADY_START field. */ + #define RADIO_SHORTS_TXREADY_START_Max (0x1UL) /*!< Max enumerator value of TXREADY_START field. */ + #define RADIO_SHORTS_TXREADY_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_TXREADY_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RXREADY_START @Bit 18 : Shortcut between event RXREADY and task START */ + #define RADIO_SHORTS_RXREADY_START_Pos (18UL) /*!< Position of RXREADY_START field. */ + #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ + #define RADIO_SHORTS_RXREADY_START_Min (0x0UL) /*!< Min enumerator value of RXREADY_START field. */ + #define RADIO_SHORTS_RXREADY_START_Max (0x1UL) /*!< Max enumerator value of RXREADY_START field. */ + #define RADIO_SHORTS_RXREADY_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_RXREADY_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* PHYEND_DISABLE @Bit 19 : Shortcut between event PHYEND and task DISABLE */ + #define RADIO_SHORTS_PHYEND_DISABLE_Pos (19UL) /*!< Position of PHYEND_DISABLE field. */ + #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ + #define RADIO_SHORTS_PHYEND_DISABLE_Min (0x0UL) /*!< Min enumerator value of PHYEND_DISABLE field. */ + #define RADIO_SHORTS_PHYEND_DISABLE_Max (0x1UL) /*!< Max enumerator value of PHYEND_DISABLE field. */ + #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* PHYEND_START @Bit 20 : Shortcut between event PHYEND and task START */ + #define RADIO_SHORTS_PHYEND_START_Pos (20UL) /*!< Position of PHYEND_START field. */ + #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ + #define RADIO_SHORTS_PHYEND_START_Min (0x0UL) /*!< Min enumerator value of PHYEND_START field. */ + #define RADIO_SHORTS_PHYEND_START_Max (0x1UL) /*!< Max enumerator value of PHYEND_START field. */ + #define RADIO_SHORTS_PHYEND_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PHYEND_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* PLLREADY_TXEN @Bit 27 : Shortcut between event PLLREADY and task TXEN */ + #define RADIO_SHORTS_PLLREADY_TXEN_Pos (27UL) /*!< Position of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Msk (0x1UL << RADIO_SHORTS_PLLREADY_TXEN_Pos) /*!< Bit mask of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Min (0x0UL) /*!< Min enumerator value of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Max (0x1UL) /*!< Max enumerator value of PLLREADY_TXEN field. */ + #define RADIO_SHORTS_PLLREADY_TXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PLLREADY_TXEN_Enabled (0x1UL) /*!< Enable shortcut */ + +/* PLLREADY_RXEN @Bit 28 : Shortcut between event PLLREADY and task RXEN */ + #define RADIO_SHORTS_PLLREADY_RXEN_Pos (28UL) /*!< Position of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Msk (0x1UL << RADIO_SHORTS_PLLREADY_RXEN_Pos) /*!< Bit mask of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Min (0x0UL) /*!< Min enumerator value of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Max (0x1UL) /*!< Max enumerator value of PLLREADY_RXEN field. */ + #define RADIO_SHORTS_PLLREADY_RXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PLLREADY_RXEN_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* RADIO_INTENSET00: Enable interrupt */ + #define RADIO_INTENSET00_ResetValue (0x00000000UL) /*!< Reset value of INTENSET00 register. */ + +/* READY @Bit 0 : Write '1' to enable interrupt for event READY */ + #define RADIO_INTENSET00_READY_Pos (0UL) /*!< Position of READY field. */ + #define RADIO_INTENSET00_READY_Msk (0x1UL << RADIO_INTENSET00_READY_Pos) /*!< Bit mask of READY field. */ + #define RADIO_INTENSET00_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RADIO_INTENSET00_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RADIO_INTENSET00_READY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXREADY @Bit 1 : Write '1' to enable interrupt for event TXREADY */ + #define RADIO_INTENSET00_TXREADY_Pos (1UL) /*!< Position of TXREADY field. */ + #define RADIO_INTENSET00_TXREADY_Msk (0x1UL << RADIO_INTENSET00_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ + #define RADIO_INTENSET00_TXREADY_Min (0x0UL) /*!< Min enumerator value of TXREADY field. */ + #define RADIO_INTENSET00_TXREADY_Max (0x1UL) /*!< Max enumerator value of TXREADY field. */ + #define RADIO_INTENSET00_TXREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_TXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_TXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXREADY @Bit 2 : Write '1' to enable interrupt for event RXREADY */ + #define RADIO_INTENSET00_RXREADY_Pos (2UL) /*!< Position of RXREADY field. */ + #define RADIO_INTENSET00_RXREADY_Msk (0x1UL << RADIO_INTENSET00_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define RADIO_INTENSET00_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define RADIO_INTENSET00_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define RADIO_INTENSET00_RXREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ADDRESS @Bit 3 : Write '1' to enable interrupt for event ADDRESS */ + #define RADIO_INTENSET00_ADDRESS_Pos (3UL) /*!< Position of ADDRESS field. */ + #define RADIO_INTENSET00_ADDRESS_Msk (0x1UL << RADIO_INTENSET00_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + #define RADIO_INTENSET00_ADDRESS_Min (0x0UL) /*!< Min enumerator value of ADDRESS field. */ + #define RADIO_INTENSET00_ADDRESS_Max (0x1UL) /*!< Max enumerator value of ADDRESS field. */ + #define RADIO_INTENSET00_ADDRESS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_ADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_ADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMESTART @Bit 4 : Write '1' to enable interrupt for event FRAMESTART */ + #define RADIO_INTENSET00_FRAMESTART_Pos (4UL) /*!< Position of FRAMESTART field. */ + #define RADIO_INTENSET00_FRAMESTART_Msk (0x1UL << RADIO_INTENSET00_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ + #define RADIO_INTENSET00_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART field. */ + #define RADIO_INTENSET00_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART field. */ + #define RADIO_INTENSET00_FRAMESTART_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PAYLOAD @Bit 5 : Write '1' to enable interrupt for event PAYLOAD */ + #define RADIO_INTENSET00_PAYLOAD_Pos (5UL) /*!< Position of PAYLOAD field. */ + #define RADIO_INTENSET00_PAYLOAD_Msk (0x1UL << RADIO_INTENSET00_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ + #define RADIO_INTENSET00_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of PAYLOAD field. */ + #define RADIO_INTENSET00_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of PAYLOAD field. */ + #define RADIO_INTENSET00_PAYLOAD_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_PAYLOAD_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_PAYLOAD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 6 : Write '1' to enable interrupt for event END */ + #define RADIO_INTENSET00_END_Pos (6UL) /*!< Position of END field. */ + #define RADIO_INTENSET00_END_Msk (0x1UL << RADIO_INTENSET00_END_Pos) /*!< Bit mask of END field. */ + #define RADIO_INTENSET00_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define RADIO_INTENSET00_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define RADIO_INTENSET00_END_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PHYEND @Bit 7 : Write '1' to enable interrupt for event PHYEND */ + #define RADIO_INTENSET00_PHYEND_Pos (7UL) /*!< Position of PHYEND field. */ + #define RADIO_INTENSET00_PHYEND_Msk (0x1UL << RADIO_INTENSET00_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ + #define RADIO_INTENSET00_PHYEND_Min (0x0UL) /*!< Min enumerator value of PHYEND field. */ + #define RADIO_INTENSET00_PHYEND_Max (0x1UL) /*!< Max enumerator value of PHYEND field. */ + #define RADIO_INTENSET00_PHYEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_PHYEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_PHYEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DISABLED @Bit 8 : Write '1' to enable interrupt for event DISABLED */ + #define RADIO_INTENSET00_DISABLED_Pos (8UL) /*!< Position of DISABLED field. */ + #define RADIO_INTENSET00_DISABLED_Msk (0x1UL << RADIO_INTENSET00_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ + #define RADIO_INTENSET00_DISABLED_Min (0x0UL) /*!< Min enumerator value of DISABLED field. */ + #define RADIO_INTENSET00_DISABLED_Max (0x1UL) /*!< Max enumerator value of DISABLED field. */ + #define RADIO_INTENSET00_DISABLED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_DISABLED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_DISABLED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMATCH @Bit 9 : Write '1' to enable interrupt for event DEVMATCH */ + #define RADIO_INTENSET00_DEVMATCH_Pos (9UL) /*!< Position of DEVMATCH field. */ + #define RADIO_INTENSET00_DEVMATCH_Msk (0x1UL << RADIO_INTENSET00_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ + #define RADIO_INTENSET00_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of DEVMATCH field. */ + #define RADIO_INTENSET00_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of DEVMATCH field. */ + #define RADIO_INTENSET00_DEVMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_DEVMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMISS @Bit 10 : Write '1' to enable interrupt for event DEVMISS */ + #define RADIO_INTENSET00_DEVMISS_Pos (10UL) /*!< Position of DEVMISS field. */ + #define RADIO_INTENSET00_DEVMISS_Msk (0x1UL << RADIO_INTENSET00_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ + #define RADIO_INTENSET00_DEVMISS_Min (0x0UL) /*!< Min enumerator value of DEVMISS field. */ + #define RADIO_INTENSET00_DEVMISS_Max (0x1UL) /*!< Max enumerator value of DEVMISS field. */ + #define RADIO_INTENSET00_DEVMISS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_DEVMISS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_DEVMISS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCOK @Bit 11 : Write '1' to enable interrupt for event CRCOK */ + #define RADIO_INTENSET00_CRCOK_Pos (11UL) /*!< Position of CRCOK field. */ + #define RADIO_INTENSET00_CRCOK_Msk (0x1UL << RADIO_INTENSET00_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ + #define RADIO_INTENSET00_CRCOK_Min (0x0UL) /*!< Min enumerator value of CRCOK field. */ + #define RADIO_INTENSET00_CRCOK_Max (0x1UL) /*!< Max enumerator value of CRCOK field. */ + #define RADIO_INTENSET00_CRCOK_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CRCOK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CRCOK_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCERROR @Bit 12 : Write '1' to enable interrupt for event CRCERROR */ + #define RADIO_INTENSET00_CRCERROR_Pos (12UL) /*!< Position of CRCERROR field. */ + #define RADIO_INTENSET00_CRCERROR_Msk (0x1UL << RADIO_INTENSET00_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ + #define RADIO_INTENSET00_CRCERROR_Min (0x0UL) /*!< Min enumerator value of CRCERROR field. */ + #define RADIO_INTENSET00_CRCERROR_Max (0x1UL) /*!< Max enumerator value of CRCERROR field. */ + #define RADIO_INTENSET00_CRCERROR_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CRCERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* BCMATCH @Bit 14 : Write '1' to enable interrupt for event BCMATCH */ + #define RADIO_INTENSET00_BCMATCH_Pos (14UL) /*!< Position of BCMATCH field. */ + #define RADIO_INTENSET00_BCMATCH_Msk (0x1UL << RADIO_INTENSET00_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ + #define RADIO_INTENSET00_BCMATCH_Min (0x0UL) /*!< Min enumerator value of BCMATCH field. */ + #define RADIO_INTENSET00_BCMATCH_Max (0x1UL) /*!< Max enumerator value of BCMATCH field. */ + #define RADIO_INTENSET00_BCMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_BCMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_BCMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDEND @Bit 15 : Write '1' to enable interrupt for event EDEND */ + #define RADIO_INTENSET00_EDEND_Pos (15UL) /*!< Position of EDEND field. */ + #define RADIO_INTENSET00_EDEND_Msk (0x1UL << RADIO_INTENSET00_EDEND_Pos) /*!< Bit mask of EDEND field. */ + #define RADIO_INTENSET00_EDEND_Min (0x0UL) /*!< Min enumerator value of EDEND field. */ + #define RADIO_INTENSET00_EDEND_Max (0x1UL) /*!< Max enumerator value of EDEND field. */ + #define RADIO_INTENSET00_EDEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_EDEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_EDEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDSTOPPED @Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ + #define RADIO_INTENSET00_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ + #define RADIO_INTENSET00_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET00_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ + #define RADIO_INTENSET00_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EDSTOPPED field. */ + #define RADIO_INTENSET00_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EDSTOPPED field. */ + #define RADIO_INTENSET00_EDSTOPPED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCAIDLE @Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ + #define RADIO_INTENSET00_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ + #define RADIO_INTENSET00_CCAIDLE_Msk (0x1UL << RADIO_INTENSET00_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ + #define RADIO_INTENSET00_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of CCAIDLE field. */ + #define RADIO_INTENSET00_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of CCAIDLE field. */ + #define RADIO_INTENSET00_CCAIDLE_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CCAIDLE_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CCAIDLE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCABUSY @Bit 18 : Write '1' to enable interrupt for event CCABUSY */ + #define RADIO_INTENSET00_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ + #define RADIO_INTENSET00_CCABUSY_Msk (0x1UL << RADIO_INTENSET00_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ + #define RADIO_INTENSET00_CCABUSY_Min (0x0UL) /*!< Min enumerator value of CCABUSY field. */ + #define RADIO_INTENSET00_CCABUSY_Max (0x1UL) /*!< Max enumerator value of CCABUSY field. */ + #define RADIO_INTENSET00_CCABUSY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CCABUSY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CCABUSY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCASTOPPED @Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ + #define RADIO_INTENSET00_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ + #define RADIO_INTENSET00_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET00_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ + #define RADIO_INTENSET00_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of CCASTOPPED field. */ + #define RADIO_INTENSET00_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of CCASTOPPED field. */ + #define RADIO_INTENSET00_CCASTOPPED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RATEBOOST @Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ + #define RADIO_INTENSET00_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ + #define RADIO_INTENSET00_RATEBOOST_Msk (0x1UL << RADIO_INTENSET00_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ + #define RADIO_INTENSET00_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of RATEBOOST field. */ + #define RADIO_INTENSET00_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of RATEBOOST field. */ + #define RADIO_INTENSET00_RATEBOOST_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled */ + +/* MHRMATCH @Bit 21 : Write '1' to enable interrupt for event MHRMATCH */ + #define RADIO_INTENSET00_MHRMATCH_Pos (21UL) /*!< Position of MHRMATCH field. */ + #define RADIO_INTENSET00_MHRMATCH_Msk (0x1UL << RADIO_INTENSET00_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ + #define RADIO_INTENSET00_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of MHRMATCH field. */ + #define RADIO_INTENSET00_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of MHRMATCH field. */ + #define RADIO_INTENSET00_MHRMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_MHRMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYNC @Bit 22 : Write '1' to enable interrupt for event SYNC */ + #define RADIO_INTENSET00_SYNC_Pos (22UL) /*!< Position of SYNC field. */ + #define RADIO_INTENSET00_SYNC_Msk (0x1UL << RADIO_INTENSET00_SYNC_Pos) /*!< Bit mask of SYNC field. */ + #define RADIO_INTENSET00_SYNC_Min (0x0UL) /*!< Min enumerator value of SYNC field. */ + #define RADIO_INTENSET00_SYNC_Max (0x1UL) /*!< Max enumerator value of SYNC field. */ + #define RADIO_INTENSET00_SYNC_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_SYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_SYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CTEPRESENT @Bit 23 : Write '1' to enable interrupt for event CTEPRESENT */ + #define RADIO_INTENSET00_CTEPRESENT_Pos (23UL) /*!< Position of CTEPRESENT field. */ + #define RADIO_INTENSET00_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET00_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ + #define RADIO_INTENSET00_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of CTEPRESENT field. */ + #define RADIO_INTENSET00_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of CTEPRESENT field. */ + #define RADIO_INTENSET00_CTEPRESENT_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_INTENSET01: Enable interrupt */ + #define RADIO_INTENSET01_ResetValue (0x00000000UL) /*!< Reset value of INTENSET01 register. */ + +/* PLLREADY @Bit 12 : Write '1' to enable interrupt for event PLLREADY */ + #define RADIO_INTENSET01_PLLREADY_Pos (12UL) /*!< Position of PLLREADY field. */ + #define RADIO_INTENSET01_PLLREADY_Msk (0x1UL << RADIO_INTENSET01_PLLREADY_Pos) /*!< Bit mask of PLLREADY field. */ + #define RADIO_INTENSET01_PLLREADY_Min (0x0UL) /*!< Min enumerator value of PLLREADY field. */ + #define RADIO_INTENSET01_PLLREADY_Max (0x1UL) /*!< Max enumerator value of PLLREADY field. */ + #define RADIO_INTENSET01_PLLREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET01_PLLREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET01_PLLREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXADDRESS @Bit 15 : Write '1' to enable interrupt for event RXADDRESS */ + #define RADIO_INTENSET01_RXADDRESS_Pos (15UL) /*!< Position of RXADDRESS field. */ + #define RADIO_INTENSET01_RXADDRESS_Msk (0x1UL << RADIO_INTENSET01_RXADDRESS_Pos) /*!< Bit mask of RXADDRESS field. */ + #define RADIO_INTENSET01_RXADDRESS_Min (0x0UL) /*!< Min enumerator value of RXADDRESS field. */ + #define RADIO_INTENSET01_RXADDRESS_Max (0x1UL) /*!< Max enumerator value of RXADDRESS field. */ + #define RADIO_INTENSET01_RXADDRESS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET01_RXADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET01_RXADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* AUXDATADMAEND @Bit 16 : Write '1' to enable interrupt for event AUXDATADMAEND */ + #define RADIO_INTENSET01_AUXDATADMAEND_Pos (16UL) /*!< Position of AUXDATADMAEND field. */ + #define RADIO_INTENSET01_AUXDATADMAEND_Msk (0x1UL << RADIO_INTENSET01_AUXDATADMAEND_Pos) /*!< Bit mask of AUXDATADMAEND + field.*/ + #define RADIO_INTENSET01_AUXDATADMAEND_Min (0x0UL) /*!< Min enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENSET01_AUXDATADMAEND_Max (0x1UL) /*!< Max enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENSET01_AUXDATADMAEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET01_AUXDATADMAEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET01_AUXDATADMAEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CSTONESEND @Bit 18 : Write '1' to enable interrupt for event CSTONESEND */ + #define RADIO_INTENSET01_CSTONESEND_Pos (18UL) /*!< Position of CSTONESEND field. */ + #define RADIO_INTENSET01_CSTONESEND_Msk (0x1UL << RADIO_INTENSET01_CSTONESEND_Pos) /*!< Bit mask of CSTONESEND field. */ + #define RADIO_INTENSET01_CSTONESEND_Min (0x0UL) /*!< Min enumerator value of CSTONESEND field. */ + #define RADIO_INTENSET01_CSTONESEND_Max (0x1UL) /*!< Max enumerator value of CSTONESEND field. */ + #define RADIO_INTENSET01_CSTONESEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET01_CSTONESEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET01_CSTONESEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_INTENCLR00: Disable interrupt */ + #define RADIO_INTENCLR00_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR00 register. */ + +/* READY @Bit 0 : Write '1' to disable interrupt for event READY */ + #define RADIO_INTENCLR00_READY_Pos (0UL) /*!< Position of READY field. */ + #define RADIO_INTENCLR00_READY_Msk (0x1UL << RADIO_INTENCLR00_READY_Pos) /*!< Bit mask of READY field. */ + #define RADIO_INTENCLR00_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RADIO_INTENCLR00_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RADIO_INTENCLR00_READY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXREADY @Bit 1 : Write '1' to disable interrupt for event TXREADY */ + #define RADIO_INTENCLR00_TXREADY_Pos (1UL) /*!< Position of TXREADY field. */ + #define RADIO_INTENCLR00_TXREADY_Msk (0x1UL << RADIO_INTENCLR00_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ + #define RADIO_INTENCLR00_TXREADY_Min (0x0UL) /*!< Min enumerator value of TXREADY field. */ + #define RADIO_INTENCLR00_TXREADY_Max (0x1UL) /*!< Max enumerator value of TXREADY field. */ + #define RADIO_INTENCLR00_TXREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_TXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_TXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXREADY @Bit 2 : Write '1' to disable interrupt for event RXREADY */ + #define RADIO_INTENCLR00_RXREADY_Pos (2UL) /*!< Position of RXREADY field. */ + #define RADIO_INTENCLR00_RXREADY_Msk (0x1UL << RADIO_INTENCLR00_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define RADIO_INTENCLR00_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define RADIO_INTENCLR00_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define RADIO_INTENCLR00_RXREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ADDRESS @Bit 3 : Write '1' to disable interrupt for event ADDRESS */ + #define RADIO_INTENCLR00_ADDRESS_Pos (3UL) /*!< Position of ADDRESS field. */ + #define RADIO_INTENCLR00_ADDRESS_Msk (0x1UL << RADIO_INTENCLR00_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + #define RADIO_INTENCLR00_ADDRESS_Min (0x0UL) /*!< Min enumerator value of ADDRESS field. */ + #define RADIO_INTENCLR00_ADDRESS_Max (0x1UL) /*!< Max enumerator value of ADDRESS field. */ + #define RADIO_INTENCLR00_ADDRESS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_ADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_ADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMESTART @Bit 4 : Write '1' to disable interrupt for event FRAMESTART */ + #define RADIO_INTENCLR00_FRAMESTART_Pos (4UL) /*!< Position of FRAMESTART field. */ + #define RADIO_INTENCLR00_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR00_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ + #define RADIO_INTENCLR00_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART field. */ + #define RADIO_INTENCLR00_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART field. */ + #define RADIO_INTENCLR00_FRAMESTART_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PAYLOAD @Bit 5 : Write '1' to disable interrupt for event PAYLOAD */ + #define RADIO_INTENCLR00_PAYLOAD_Pos (5UL) /*!< Position of PAYLOAD field. */ + #define RADIO_INTENCLR00_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR00_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ + #define RADIO_INTENCLR00_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of PAYLOAD field. */ + #define RADIO_INTENCLR00_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of PAYLOAD field. */ + #define RADIO_INTENCLR00_PAYLOAD_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_PAYLOAD_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_PAYLOAD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 6 : Write '1' to disable interrupt for event END */ + #define RADIO_INTENCLR00_END_Pos (6UL) /*!< Position of END field. */ + #define RADIO_INTENCLR00_END_Msk (0x1UL << RADIO_INTENCLR00_END_Pos) /*!< Bit mask of END field. */ + #define RADIO_INTENCLR00_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define RADIO_INTENCLR00_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define RADIO_INTENCLR00_END_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PHYEND @Bit 7 : Write '1' to disable interrupt for event PHYEND */ + #define RADIO_INTENCLR00_PHYEND_Pos (7UL) /*!< Position of PHYEND field. */ + #define RADIO_INTENCLR00_PHYEND_Msk (0x1UL << RADIO_INTENCLR00_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ + #define RADIO_INTENCLR00_PHYEND_Min (0x0UL) /*!< Min enumerator value of PHYEND field. */ + #define RADIO_INTENCLR00_PHYEND_Max (0x1UL) /*!< Max enumerator value of PHYEND field. */ + #define RADIO_INTENCLR00_PHYEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_PHYEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_PHYEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DISABLED @Bit 8 : Write '1' to disable interrupt for event DISABLED */ + #define RADIO_INTENCLR00_DISABLED_Pos (8UL) /*!< Position of DISABLED field. */ + #define RADIO_INTENCLR00_DISABLED_Msk (0x1UL << RADIO_INTENCLR00_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ + #define RADIO_INTENCLR00_DISABLED_Min (0x0UL) /*!< Min enumerator value of DISABLED field. */ + #define RADIO_INTENCLR00_DISABLED_Max (0x1UL) /*!< Max enumerator value of DISABLED field. */ + #define RADIO_INTENCLR00_DISABLED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_DISABLED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_DISABLED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMATCH @Bit 9 : Write '1' to disable interrupt for event DEVMATCH */ + #define RADIO_INTENCLR00_DEVMATCH_Pos (9UL) /*!< Position of DEVMATCH field. */ + #define RADIO_INTENCLR00_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR00_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ + #define RADIO_INTENCLR00_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of DEVMATCH field. */ + #define RADIO_INTENCLR00_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of DEVMATCH field. */ + #define RADIO_INTENCLR00_DEVMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_DEVMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMISS @Bit 10 : Write '1' to disable interrupt for event DEVMISS */ + #define RADIO_INTENCLR00_DEVMISS_Pos (10UL) /*!< Position of DEVMISS field. */ + #define RADIO_INTENCLR00_DEVMISS_Msk (0x1UL << RADIO_INTENCLR00_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ + #define RADIO_INTENCLR00_DEVMISS_Min (0x0UL) /*!< Min enumerator value of DEVMISS field. */ + #define RADIO_INTENCLR00_DEVMISS_Max (0x1UL) /*!< Max enumerator value of DEVMISS field. */ + #define RADIO_INTENCLR00_DEVMISS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_DEVMISS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_DEVMISS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCOK @Bit 11 : Write '1' to disable interrupt for event CRCOK */ + #define RADIO_INTENCLR00_CRCOK_Pos (11UL) /*!< Position of CRCOK field. */ + #define RADIO_INTENCLR00_CRCOK_Msk (0x1UL << RADIO_INTENCLR00_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ + #define RADIO_INTENCLR00_CRCOK_Min (0x0UL) /*!< Min enumerator value of CRCOK field. */ + #define RADIO_INTENCLR00_CRCOK_Max (0x1UL) /*!< Max enumerator value of CRCOK field. */ + #define RADIO_INTENCLR00_CRCOK_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CRCOK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CRCOK_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCERROR @Bit 12 : Write '1' to disable interrupt for event CRCERROR */ + #define RADIO_INTENCLR00_CRCERROR_Pos (12UL) /*!< Position of CRCERROR field. */ + #define RADIO_INTENCLR00_CRCERROR_Msk (0x1UL << RADIO_INTENCLR00_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ + #define RADIO_INTENCLR00_CRCERROR_Min (0x0UL) /*!< Min enumerator value of CRCERROR field. */ + #define RADIO_INTENCLR00_CRCERROR_Max (0x1UL) /*!< Max enumerator value of CRCERROR field. */ + #define RADIO_INTENCLR00_CRCERROR_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CRCERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* BCMATCH @Bit 14 : Write '1' to disable interrupt for event BCMATCH */ + #define RADIO_INTENCLR00_BCMATCH_Pos (14UL) /*!< Position of BCMATCH field. */ + #define RADIO_INTENCLR00_BCMATCH_Msk (0x1UL << RADIO_INTENCLR00_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ + #define RADIO_INTENCLR00_BCMATCH_Min (0x0UL) /*!< Min enumerator value of BCMATCH field. */ + #define RADIO_INTENCLR00_BCMATCH_Max (0x1UL) /*!< Max enumerator value of BCMATCH field. */ + #define RADIO_INTENCLR00_BCMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_BCMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_BCMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDEND @Bit 15 : Write '1' to disable interrupt for event EDEND */ + #define RADIO_INTENCLR00_EDEND_Pos (15UL) /*!< Position of EDEND field. */ + #define RADIO_INTENCLR00_EDEND_Msk (0x1UL << RADIO_INTENCLR00_EDEND_Pos) /*!< Bit mask of EDEND field. */ + #define RADIO_INTENCLR00_EDEND_Min (0x0UL) /*!< Min enumerator value of EDEND field. */ + #define RADIO_INTENCLR00_EDEND_Max (0x1UL) /*!< Max enumerator value of EDEND field. */ + #define RADIO_INTENCLR00_EDEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_EDEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_EDEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDSTOPPED @Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ + #define RADIO_INTENCLR00_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ + #define RADIO_INTENCLR00_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR00_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ + #define RADIO_INTENCLR00_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EDSTOPPED field. */ + #define RADIO_INTENCLR00_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EDSTOPPED field. */ + #define RADIO_INTENCLR00_EDSTOPPED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCAIDLE @Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ + #define RADIO_INTENCLR00_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ + #define RADIO_INTENCLR00_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR00_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ + #define RADIO_INTENCLR00_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of CCAIDLE field. */ + #define RADIO_INTENCLR00_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of CCAIDLE field. */ + #define RADIO_INTENCLR00_CCAIDLE_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CCAIDLE_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CCAIDLE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCABUSY @Bit 18 : Write '1' to disable interrupt for event CCABUSY */ + #define RADIO_INTENCLR00_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ + #define RADIO_INTENCLR00_CCABUSY_Msk (0x1UL << RADIO_INTENCLR00_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ + #define RADIO_INTENCLR00_CCABUSY_Min (0x0UL) /*!< Min enumerator value of CCABUSY field. */ + #define RADIO_INTENCLR00_CCABUSY_Max (0x1UL) /*!< Max enumerator value of CCABUSY field. */ + #define RADIO_INTENCLR00_CCABUSY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CCABUSY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CCABUSY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCASTOPPED @Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ + #define RADIO_INTENCLR00_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ + #define RADIO_INTENCLR00_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR00_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ + #define RADIO_INTENCLR00_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of CCASTOPPED field. */ + #define RADIO_INTENCLR00_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of CCASTOPPED field. */ + #define RADIO_INTENCLR00_CCASTOPPED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RATEBOOST @Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ + #define RADIO_INTENCLR00_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ + #define RADIO_INTENCLR00_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR00_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ + #define RADIO_INTENCLR00_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of RATEBOOST field. */ + #define RADIO_INTENCLR00_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of RATEBOOST field. */ + #define RADIO_INTENCLR00_RATEBOOST_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled */ + +/* MHRMATCH @Bit 21 : Write '1' to disable interrupt for event MHRMATCH */ + #define RADIO_INTENCLR00_MHRMATCH_Pos (21UL) /*!< Position of MHRMATCH field. */ + #define RADIO_INTENCLR00_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR00_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ + #define RADIO_INTENCLR00_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of MHRMATCH field. */ + #define RADIO_INTENCLR00_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of MHRMATCH field. */ + #define RADIO_INTENCLR00_MHRMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_MHRMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYNC @Bit 22 : Write '1' to disable interrupt for event SYNC */ + #define RADIO_INTENCLR00_SYNC_Pos (22UL) /*!< Position of SYNC field. */ + #define RADIO_INTENCLR00_SYNC_Msk (0x1UL << RADIO_INTENCLR00_SYNC_Pos) /*!< Bit mask of SYNC field. */ + #define RADIO_INTENCLR00_SYNC_Min (0x0UL) /*!< Min enumerator value of SYNC field. */ + #define RADIO_INTENCLR00_SYNC_Max (0x1UL) /*!< Max enumerator value of SYNC field. */ + #define RADIO_INTENCLR00_SYNC_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_SYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_SYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CTEPRESENT @Bit 23 : Write '1' to disable interrupt for event CTEPRESENT */ + #define RADIO_INTENCLR00_CTEPRESENT_Pos (23UL) /*!< Position of CTEPRESENT field. */ + #define RADIO_INTENCLR00_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR00_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ + #define RADIO_INTENCLR00_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of CTEPRESENT field. */ + #define RADIO_INTENCLR00_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of CTEPRESENT field. */ + #define RADIO_INTENCLR00_CTEPRESENT_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_INTENCLR01: Disable interrupt */ + #define RADIO_INTENCLR01_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR01 register. */ + +/* PLLREADY @Bit 12 : Write '1' to disable interrupt for event PLLREADY */ + #define RADIO_INTENCLR01_PLLREADY_Pos (12UL) /*!< Position of PLLREADY field. */ + #define RADIO_INTENCLR01_PLLREADY_Msk (0x1UL << RADIO_INTENCLR01_PLLREADY_Pos) /*!< Bit mask of PLLREADY field. */ + #define RADIO_INTENCLR01_PLLREADY_Min (0x0UL) /*!< Min enumerator value of PLLREADY field. */ + #define RADIO_INTENCLR01_PLLREADY_Max (0x1UL) /*!< Max enumerator value of PLLREADY field. */ + #define RADIO_INTENCLR01_PLLREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR01_PLLREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR01_PLLREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXADDRESS @Bit 15 : Write '1' to disable interrupt for event RXADDRESS */ + #define RADIO_INTENCLR01_RXADDRESS_Pos (15UL) /*!< Position of RXADDRESS field. */ + #define RADIO_INTENCLR01_RXADDRESS_Msk (0x1UL << RADIO_INTENCLR01_RXADDRESS_Pos) /*!< Bit mask of RXADDRESS field. */ + #define RADIO_INTENCLR01_RXADDRESS_Min (0x0UL) /*!< Min enumerator value of RXADDRESS field. */ + #define RADIO_INTENCLR01_RXADDRESS_Max (0x1UL) /*!< Max enumerator value of RXADDRESS field. */ + #define RADIO_INTENCLR01_RXADDRESS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR01_RXADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR01_RXADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* AUXDATADMAEND @Bit 16 : Write '1' to disable interrupt for event AUXDATADMAEND */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Pos (16UL) /*!< Position of AUXDATADMAEND field. */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Msk (0x1UL << RADIO_INTENCLR01_AUXDATADMAEND_Pos) /*!< Bit mask of AUXDATADMAEND + field.*/ + #define RADIO_INTENCLR01_AUXDATADMAEND_Min (0x0UL) /*!< Min enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Max (0x1UL) /*!< Max enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR01_AUXDATADMAEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CSTONESEND @Bit 18 : Write '1' to disable interrupt for event CSTONESEND */ + #define RADIO_INTENCLR01_CSTONESEND_Pos (18UL) /*!< Position of CSTONESEND field. */ + #define RADIO_INTENCLR01_CSTONESEND_Msk (0x1UL << RADIO_INTENCLR01_CSTONESEND_Pos) /*!< Bit mask of CSTONESEND field. */ + #define RADIO_INTENCLR01_CSTONESEND_Min (0x0UL) /*!< Min enumerator value of CSTONESEND field. */ + #define RADIO_INTENCLR01_CSTONESEND_Max (0x1UL) /*!< Max enumerator value of CSTONESEND field. */ + #define RADIO_INTENCLR01_CSTONESEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR01_CSTONESEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR01_CSTONESEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_INTENSET10: Enable interrupt */ + #define RADIO_INTENSET10_ResetValue (0x00000000UL) /*!< Reset value of INTENSET10 register. */ + +/* READY @Bit 0 : Write '1' to enable interrupt for event READY */ + #define RADIO_INTENSET10_READY_Pos (0UL) /*!< Position of READY field. */ + #define RADIO_INTENSET10_READY_Msk (0x1UL << RADIO_INTENSET10_READY_Pos) /*!< Bit mask of READY field. */ + #define RADIO_INTENSET10_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RADIO_INTENSET10_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RADIO_INTENSET10_READY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXREADY @Bit 1 : Write '1' to enable interrupt for event TXREADY */ + #define RADIO_INTENSET10_TXREADY_Pos (1UL) /*!< Position of TXREADY field. */ + #define RADIO_INTENSET10_TXREADY_Msk (0x1UL << RADIO_INTENSET10_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ + #define RADIO_INTENSET10_TXREADY_Min (0x0UL) /*!< Min enumerator value of TXREADY field. */ + #define RADIO_INTENSET10_TXREADY_Max (0x1UL) /*!< Max enumerator value of TXREADY field. */ + #define RADIO_INTENSET10_TXREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_TXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_TXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXREADY @Bit 2 : Write '1' to enable interrupt for event RXREADY */ + #define RADIO_INTENSET10_RXREADY_Pos (2UL) /*!< Position of RXREADY field. */ + #define RADIO_INTENSET10_RXREADY_Msk (0x1UL << RADIO_INTENSET10_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define RADIO_INTENSET10_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define RADIO_INTENSET10_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define RADIO_INTENSET10_RXREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ADDRESS @Bit 3 : Write '1' to enable interrupt for event ADDRESS */ + #define RADIO_INTENSET10_ADDRESS_Pos (3UL) /*!< Position of ADDRESS field. */ + #define RADIO_INTENSET10_ADDRESS_Msk (0x1UL << RADIO_INTENSET10_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + #define RADIO_INTENSET10_ADDRESS_Min (0x0UL) /*!< Min enumerator value of ADDRESS field. */ + #define RADIO_INTENSET10_ADDRESS_Max (0x1UL) /*!< Max enumerator value of ADDRESS field. */ + #define RADIO_INTENSET10_ADDRESS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_ADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_ADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMESTART @Bit 4 : Write '1' to enable interrupt for event FRAMESTART */ + #define RADIO_INTENSET10_FRAMESTART_Pos (4UL) /*!< Position of FRAMESTART field. */ + #define RADIO_INTENSET10_FRAMESTART_Msk (0x1UL << RADIO_INTENSET10_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ + #define RADIO_INTENSET10_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART field. */ + #define RADIO_INTENSET10_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART field. */ + #define RADIO_INTENSET10_FRAMESTART_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PAYLOAD @Bit 5 : Write '1' to enable interrupt for event PAYLOAD */ + #define RADIO_INTENSET10_PAYLOAD_Pos (5UL) /*!< Position of PAYLOAD field. */ + #define RADIO_INTENSET10_PAYLOAD_Msk (0x1UL << RADIO_INTENSET10_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ + #define RADIO_INTENSET10_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of PAYLOAD field. */ + #define RADIO_INTENSET10_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of PAYLOAD field. */ + #define RADIO_INTENSET10_PAYLOAD_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_PAYLOAD_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_PAYLOAD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 6 : Write '1' to enable interrupt for event END */ + #define RADIO_INTENSET10_END_Pos (6UL) /*!< Position of END field. */ + #define RADIO_INTENSET10_END_Msk (0x1UL << RADIO_INTENSET10_END_Pos) /*!< Bit mask of END field. */ + #define RADIO_INTENSET10_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define RADIO_INTENSET10_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define RADIO_INTENSET10_END_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PHYEND @Bit 7 : Write '1' to enable interrupt for event PHYEND */ + #define RADIO_INTENSET10_PHYEND_Pos (7UL) /*!< Position of PHYEND field. */ + #define RADIO_INTENSET10_PHYEND_Msk (0x1UL << RADIO_INTENSET10_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ + #define RADIO_INTENSET10_PHYEND_Min (0x0UL) /*!< Min enumerator value of PHYEND field. */ + #define RADIO_INTENSET10_PHYEND_Max (0x1UL) /*!< Max enumerator value of PHYEND field. */ + #define RADIO_INTENSET10_PHYEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_PHYEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_PHYEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DISABLED @Bit 8 : Write '1' to enable interrupt for event DISABLED */ + #define RADIO_INTENSET10_DISABLED_Pos (8UL) /*!< Position of DISABLED field. */ + #define RADIO_INTENSET10_DISABLED_Msk (0x1UL << RADIO_INTENSET10_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ + #define RADIO_INTENSET10_DISABLED_Min (0x0UL) /*!< Min enumerator value of DISABLED field. */ + #define RADIO_INTENSET10_DISABLED_Max (0x1UL) /*!< Max enumerator value of DISABLED field. */ + #define RADIO_INTENSET10_DISABLED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_DISABLED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_DISABLED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMATCH @Bit 9 : Write '1' to enable interrupt for event DEVMATCH */ + #define RADIO_INTENSET10_DEVMATCH_Pos (9UL) /*!< Position of DEVMATCH field. */ + #define RADIO_INTENSET10_DEVMATCH_Msk (0x1UL << RADIO_INTENSET10_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ + #define RADIO_INTENSET10_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of DEVMATCH field. */ + #define RADIO_INTENSET10_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of DEVMATCH field. */ + #define RADIO_INTENSET10_DEVMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_DEVMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMISS @Bit 10 : Write '1' to enable interrupt for event DEVMISS */ + #define RADIO_INTENSET10_DEVMISS_Pos (10UL) /*!< Position of DEVMISS field. */ + #define RADIO_INTENSET10_DEVMISS_Msk (0x1UL << RADIO_INTENSET10_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ + #define RADIO_INTENSET10_DEVMISS_Min (0x0UL) /*!< Min enumerator value of DEVMISS field. */ + #define RADIO_INTENSET10_DEVMISS_Max (0x1UL) /*!< Max enumerator value of DEVMISS field. */ + #define RADIO_INTENSET10_DEVMISS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_DEVMISS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_DEVMISS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCOK @Bit 11 : Write '1' to enable interrupt for event CRCOK */ + #define RADIO_INTENSET10_CRCOK_Pos (11UL) /*!< Position of CRCOK field. */ + #define RADIO_INTENSET10_CRCOK_Msk (0x1UL << RADIO_INTENSET10_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ + #define RADIO_INTENSET10_CRCOK_Min (0x0UL) /*!< Min enumerator value of CRCOK field. */ + #define RADIO_INTENSET10_CRCOK_Max (0x1UL) /*!< Max enumerator value of CRCOK field. */ + #define RADIO_INTENSET10_CRCOK_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CRCOK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CRCOK_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCERROR @Bit 12 : Write '1' to enable interrupt for event CRCERROR */ + #define RADIO_INTENSET10_CRCERROR_Pos (12UL) /*!< Position of CRCERROR field. */ + #define RADIO_INTENSET10_CRCERROR_Msk (0x1UL << RADIO_INTENSET10_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ + #define RADIO_INTENSET10_CRCERROR_Min (0x0UL) /*!< Min enumerator value of CRCERROR field. */ + #define RADIO_INTENSET10_CRCERROR_Max (0x1UL) /*!< Max enumerator value of CRCERROR field. */ + #define RADIO_INTENSET10_CRCERROR_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CRCERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* BCMATCH @Bit 14 : Write '1' to enable interrupt for event BCMATCH */ + #define RADIO_INTENSET10_BCMATCH_Pos (14UL) /*!< Position of BCMATCH field. */ + #define RADIO_INTENSET10_BCMATCH_Msk (0x1UL << RADIO_INTENSET10_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ + #define RADIO_INTENSET10_BCMATCH_Min (0x0UL) /*!< Min enumerator value of BCMATCH field. */ + #define RADIO_INTENSET10_BCMATCH_Max (0x1UL) /*!< Max enumerator value of BCMATCH field. */ + #define RADIO_INTENSET10_BCMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_BCMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_BCMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDEND @Bit 15 : Write '1' to enable interrupt for event EDEND */ + #define RADIO_INTENSET10_EDEND_Pos (15UL) /*!< Position of EDEND field. */ + #define RADIO_INTENSET10_EDEND_Msk (0x1UL << RADIO_INTENSET10_EDEND_Pos) /*!< Bit mask of EDEND field. */ + #define RADIO_INTENSET10_EDEND_Min (0x0UL) /*!< Min enumerator value of EDEND field. */ + #define RADIO_INTENSET10_EDEND_Max (0x1UL) /*!< Max enumerator value of EDEND field. */ + #define RADIO_INTENSET10_EDEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_EDEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_EDEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDSTOPPED @Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ + #define RADIO_INTENSET10_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ + #define RADIO_INTENSET10_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET10_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ + #define RADIO_INTENSET10_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EDSTOPPED field. */ + #define RADIO_INTENSET10_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EDSTOPPED field. */ + #define RADIO_INTENSET10_EDSTOPPED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCAIDLE @Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ + #define RADIO_INTENSET10_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ + #define RADIO_INTENSET10_CCAIDLE_Msk (0x1UL << RADIO_INTENSET10_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ + #define RADIO_INTENSET10_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of CCAIDLE field. */ + #define RADIO_INTENSET10_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of CCAIDLE field. */ + #define RADIO_INTENSET10_CCAIDLE_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CCAIDLE_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CCAIDLE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCABUSY @Bit 18 : Write '1' to enable interrupt for event CCABUSY */ + #define RADIO_INTENSET10_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ + #define RADIO_INTENSET10_CCABUSY_Msk (0x1UL << RADIO_INTENSET10_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ + #define RADIO_INTENSET10_CCABUSY_Min (0x0UL) /*!< Min enumerator value of CCABUSY field. */ + #define RADIO_INTENSET10_CCABUSY_Max (0x1UL) /*!< Max enumerator value of CCABUSY field. */ + #define RADIO_INTENSET10_CCABUSY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CCABUSY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CCABUSY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCASTOPPED @Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ + #define RADIO_INTENSET10_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ + #define RADIO_INTENSET10_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET10_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ + #define RADIO_INTENSET10_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of CCASTOPPED field. */ + #define RADIO_INTENSET10_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of CCASTOPPED field. */ + #define RADIO_INTENSET10_CCASTOPPED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RATEBOOST @Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ + #define RADIO_INTENSET10_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ + #define RADIO_INTENSET10_RATEBOOST_Msk (0x1UL << RADIO_INTENSET10_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ + #define RADIO_INTENSET10_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of RATEBOOST field. */ + #define RADIO_INTENSET10_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of RATEBOOST field. */ + #define RADIO_INTENSET10_RATEBOOST_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled */ + +/* MHRMATCH @Bit 21 : Write '1' to enable interrupt for event MHRMATCH */ + #define RADIO_INTENSET10_MHRMATCH_Pos (21UL) /*!< Position of MHRMATCH field. */ + #define RADIO_INTENSET10_MHRMATCH_Msk (0x1UL << RADIO_INTENSET10_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ + #define RADIO_INTENSET10_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of MHRMATCH field. */ + #define RADIO_INTENSET10_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of MHRMATCH field. */ + #define RADIO_INTENSET10_MHRMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_MHRMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYNC @Bit 22 : Write '1' to enable interrupt for event SYNC */ + #define RADIO_INTENSET10_SYNC_Pos (22UL) /*!< Position of SYNC field. */ + #define RADIO_INTENSET10_SYNC_Msk (0x1UL << RADIO_INTENSET10_SYNC_Pos) /*!< Bit mask of SYNC field. */ + #define RADIO_INTENSET10_SYNC_Min (0x0UL) /*!< Min enumerator value of SYNC field. */ + #define RADIO_INTENSET10_SYNC_Max (0x1UL) /*!< Max enumerator value of SYNC field. */ + #define RADIO_INTENSET10_SYNC_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_SYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_SYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CTEPRESENT @Bit 23 : Write '1' to enable interrupt for event CTEPRESENT */ + #define RADIO_INTENSET10_CTEPRESENT_Pos (23UL) /*!< Position of CTEPRESENT field. */ + #define RADIO_INTENSET10_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET10_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ + #define RADIO_INTENSET10_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of CTEPRESENT field. */ + #define RADIO_INTENSET10_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of CTEPRESENT field. */ + #define RADIO_INTENSET10_CTEPRESENT_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_INTENSET11: Enable interrupt */ + #define RADIO_INTENSET11_ResetValue (0x00000000UL) /*!< Reset value of INTENSET11 register. */ + +/* PLLREADY @Bit 12 : Write '1' to enable interrupt for event PLLREADY */ + #define RADIO_INTENSET11_PLLREADY_Pos (12UL) /*!< Position of PLLREADY field. */ + #define RADIO_INTENSET11_PLLREADY_Msk (0x1UL << RADIO_INTENSET11_PLLREADY_Pos) /*!< Bit mask of PLLREADY field. */ + #define RADIO_INTENSET11_PLLREADY_Min (0x0UL) /*!< Min enumerator value of PLLREADY field. */ + #define RADIO_INTENSET11_PLLREADY_Max (0x1UL) /*!< Max enumerator value of PLLREADY field. */ + #define RADIO_INTENSET11_PLLREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET11_PLLREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET11_PLLREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXADDRESS @Bit 15 : Write '1' to enable interrupt for event RXADDRESS */ + #define RADIO_INTENSET11_RXADDRESS_Pos (15UL) /*!< Position of RXADDRESS field. */ + #define RADIO_INTENSET11_RXADDRESS_Msk (0x1UL << RADIO_INTENSET11_RXADDRESS_Pos) /*!< Bit mask of RXADDRESS field. */ + #define RADIO_INTENSET11_RXADDRESS_Min (0x0UL) /*!< Min enumerator value of RXADDRESS field. */ + #define RADIO_INTENSET11_RXADDRESS_Max (0x1UL) /*!< Max enumerator value of RXADDRESS field. */ + #define RADIO_INTENSET11_RXADDRESS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET11_RXADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET11_RXADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* AUXDATADMAEND @Bit 16 : Write '1' to enable interrupt for event AUXDATADMAEND */ + #define RADIO_INTENSET11_AUXDATADMAEND_Pos (16UL) /*!< Position of AUXDATADMAEND field. */ + #define RADIO_INTENSET11_AUXDATADMAEND_Msk (0x1UL << RADIO_INTENSET11_AUXDATADMAEND_Pos) /*!< Bit mask of AUXDATADMAEND + field.*/ + #define RADIO_INTENSET11_AUXDATADMAEND_Min (0x0UL) /*!< Min enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENSET11_AUXDATADMAEND_Max (0x1UL) /*!< Max enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENSET11_AUXDATADMAEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET11_AUXDATADMAEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET11_AUXDATADMAEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CSTONESEND @Bit 18 : Write '1' to enable interrupt for event CSTONESEND */ + #define RADIO_INTENSET11_CSTONESEND_Pos (18UL) /*!< Position of CSTONESEND field. */ + #define RADIO_INTENSET11_CSTONESEND_Msk (0x1UL << RADIO_INTENSET11_CSTONESEND_Pos) /*!< Bit mask of CSTONESEND field. */ + #define RADIO_INTENSET11_CSTONESEND_Min (0x0UL) /*!< Min enumerator value of CSTONESEND field. */ + #define RADIO_INTENSET11_CSTONESEND_Max (0x1UL) /*!< Max enumerator value of CSTONESEND field. */ + #define RADIO_INTENSET11_CSTONESEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET11_CSTONESEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET11_CSTONESEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_INTENCLR10: Disable interrupt */ + #define RADIO_INTENCLR10_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR10 register. */ + +/* READY @Bit 0 : Write '1' to disable interrupt for event READY */ + #define RADIO_INTENCLR10_READY_Pos (0UL) /*!< Position of READY field. */ + #define RADIO_INTENCLR10_READY_Msk (0x1UL << RADIO_INTENCLR10_READY_Pos) /*!< Bit mask of READY field. */ + #define RADIO_INTENCLR10_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RADIO_INTENCLR10_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RADIO_INTENCLR10_READY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXREADY @Bit 1 : Write '1' to disable interrupt for event TXREADY */ + #define RADIO_INTENCLR10_TXREADY_Pos (1UL) /*!< Position of TXREADY field. */ + #define RADIO_INTENCLR10_TXREADY_Msk (0x1UL << RADIO_INTENCLR10_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ + #define RADIO_INTENCLR10_TXREADY_Min (0x0UL) /*!< Min enumerator value of TXREADY field. */ + #define RADIO_INTENCLR10_TXREADY_Max (0x1UL) /*!< Max enumerator value of TXREADY field. */ + #define RADIO_INTENCLR10_TXREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_TXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_TXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXREADY @Bit 2 : Write '1' to disable interrupt for event RXREADY */ + #define RADIO_INTENCLR10_RXREADY_Pos (2UL) /*!< Position of RXREADY field. */ + #define RADIO_INTENCLR10_RXREADY_Msk (0x1UL << RADIO_INTENCLR10_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define RADIO_INTENCLR10_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define RADIO_INTENCLR10_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define RADIO_INTENCLR10_RXREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ADDRESS @Bit 3 : Write '1' to disable interrupt for event ADDRESS */ + #define RADIO_INTENCLR10_ADDRESS_Pos (3UL) /*!< Position of ADDRESS field. */ + #define RADIO_INTENCLR10_ADDRESS_Msk (0x1UL << RADIO_INTENCLR10_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + #define RADIO_INTENCLR10_ADDRESS_Min (0x0UL) /*!< Min enumerator value of ADDRESS field. */ + #define RADIO_INTENCLR10_ADDRESS_Max (0x1UL) /*!< Max enumerator value of ADDRESS field. */ + #define RADIO_INTENCLR10_ADDRESS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_ADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_ADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMESTART @Bit 4 : Write '1' to disable interrupt for event FRAMESTART */ + #define RADIO_INTENCLR10_FRAMESTART_Pos (4UL) /*!< Position of FRAMESTART field. */ + #define RADIO_INTENCLR10_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR10_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ + #define RADIO_INTENCLR10_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART field. */ + #define RADIO_INTENCLR10_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART field. */ + #define RADIO_INTENCLR10_FRAMESTART_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PAYLOAD @Bit 5 : Write '1' to disable interrupt for event PAYLOAD */ + #define RADIO_INTENCLR10_PAYLOAD_Pos (5UL) /*!< Position of PAYLOAD field. */ + #define RADIO_INTENCLR10_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR10_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ + #define RADIO_INTENCLR10_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of PAYLOAD field. */ + #define RADIO_INTENCLR10_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of PAYLOAD field. */ + #define RADIO_INTENCLR10_PAYLOAD_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_PAYLOAD_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_PAYLOAD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 6 : Write '1' to disable interrupt for event END */ + #define RADIO_INTENCLR10_END_Pos (6UL) /*!< Position of END field. */ + #define RADIO_INTENCLR10_END_Msk (0x1UL << RADIO_INTENCLR10_END_Pos) /*!< Bit mask of END field. */ + #define RADIO_INTENCLR10_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define RADIO_INTENCLR10_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define RADIO_INTENCLR10_END_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PHYEND @Bit 7 : Write '1' to disable interrupt for event PHYEND */ + #define RADIO_INTENCLR10_PHYEND_Pos (7UL) /*!< Position of PHYEND field. */ + #define RADIO_INTENCLR10_PHYEND_Msk (0x1UL << RADIO_INTENCLR10_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ + #define RADIO_INTENCLR10_PHYEND_Min (0x0UL) /*!< Min enumerator value of PHYEND field. */ + #define RADIO_INTENCLR10_PHYEND_Max (0x1UL) /*!< Max enumerator value of PHYEND field. */ + #define RADIO_INTENCLR10_PHYEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_PHYEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_PHYEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DISABLED @Bit 8 : Write '1' to disable interrupt for event DISABLED */ + #define RADIO_INTENCLR10_DISABLED_Pos (8UL) /*!< Position of DISABLED field. */ + #define RADIO_INTENCLR10_DISABLED_Msk (0x1UL << RADIO_INTENCLR10_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ + #define RADIO_INTENCLR10_DISABLED_Min (0x0UL) /*!< Min enumerator value of DISABLED field. */ + #define RADIO_INTENCLR10_DISABLED_Max (0x1UL) /*!< Max enumerator value of DISABLED field. */ + #define RADIO_INTENCLR10_DISABLED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_DISABLED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_DISABLED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMATCH @Bit 9 : Write '1' to disable interrupt for event DEVMATCH */ + #define RADIO_INTENCLR10_DEVMATCH_Pos (9UL) /*!< Position of DEVMATCH field. */ + #define RADIO_INTENCLR10_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR10_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ + #define RADIO_INTENCLR10_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of DEVMATCH field. */ + #define RADIO_INTENCLR10_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of DEVMATCH field. */ + #define RADIO_INTENCLR10_DEVMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_DEVMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMISS @Bit 10 : Write '1' to disable interrupt for event DEVMISS */ + #define RADIO_INTENCLR10_DEVMISS_Pos (10UL) /*!< Position of DEVMISS field. */ + #define RADIO_INTENCLR10_DEVMISS_Msk (0x1UL << RADIO_INTENCLR10_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ + #define RADIO_INTENCLR10_DEVMISS_Min (0x0UL) /*!< Min enumerator value of DEVMISS field. */ + #define RADIO_INTENCLR10_DEVMISS_Max (0x1UL) /*!< Max enumerator value of DEVMISS field. */ + #define RADIO_INTENCLR10_DEVMISS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_DEVMISS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_DEVMISS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCOK @Bit 11 : Write '1' to disable interrupt for event CRCOK */ + #define RADIO_INTENCLR10_CRCOK_Pos (11UL) /*!< Position of CRCOK field. */ + #define RADIO_INTENCLR10_CRCOK_Msk (0x1UL << RADIO_INTENCLR10_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ + #define RADIO_INTENCLR10_CRCOK_Min (0x0UL) /*!< Min enumerator value of CRCOK field. */ + #define RADIO_INTENCLR10_CRCOK_Max (0x1UL) /*!< Max enumerator value of CRCOK field. */ + #define RADIO_INTENCLR10_CRCOK_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CRCOK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CRCOK_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCERROR @Bit 12 : Write '1' to disable interrupt for event CRCERROR */ + #define RADIO_INTENCLR10_CRCERROR_Pos (12UL) /*!< Position of CRCERROR field. */ + #define RADIO_INTENCLR10_CRCERROR_Msk (0x1UL << RADIO_INTENCLR10_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ + #define RADIO_INTENCLR10_CRCERROR_Min (0x0UL) /*!< Min enumerator value of CRCERROR field. */ + #define RADIO_INTENCLR10_CRCERROR_Max (0x1UL) /*!< Max enumerator value of CRCERROR field. */ + #define RADIO_INTENCLR10_CRCERROR_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CRCERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* BCMATCH @Bit 14 : Write '1' to disable interrupt for event BCMATCH */ + #define RADIO_INTENCLR10_BCMATCH_Pos (14UL) /*!< Position of BCMATCH field. */ + #define RADIO_INTENCLR10_BCMATCH_Msk (0x1UL << RADIO_INTENCLR10_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ + #define RADIO_INTENCLR10_BCMATCH_Min (0x0UL) /*!< Min enumerator value of BCMATCH field. */ + #define RADIO_INTENCLR10_BCMATCH_Max (0x1UL) /*!< Max enumerator value of BCMATCH field. */ + #define RADIO_INTENCLR10_BCMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_BCMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_BCMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDEND @Bit 15 : Write '1' to disable interrupt for event EDEND */ + #define RADIO_INTENCLR10_EDEND_Pos (15UL) /*!< Position of EDEND field. */ + #define RADIO_INTENCLR10_EDEND_Msk (0x1UL << RADIO_INTENCLR10_EDEND_Pos) /*!< Bit mask of EDEND field. */ + #define RADIO_INTENCLR10_EDEND_Min (0x0UL) /*!< Min enumerator value of EDEND field. */ + #define RADIO_INTENCLR10_EDEND_Max (0x1UL) /*!< Max enumerator value of EDEND field. */ + #define RADIO_INTENCLR10_EDEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_EDEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_EDEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDSTOPPED @Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ + #define RADIO_INTENCLR10_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ + #define RADIO_INTENCLR10_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR10_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ + #define RADIO_INTENCLR10_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EDSTOPPED field. */ + #define RADIO_INTENCLR10_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EDSTOPPED field. */ + #define RADIO_INTENCLR10_EDSTOPPED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCAIDLE @Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ + #define RADIO_INTENCLR10_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ + #define RADIO_INTENCLR10_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR10_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ + #define RADIO_INTENCLR10_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of CCAIDLE field. */ + #define RADIO_INTENCLR10_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of CCAIDLE field. */ + #define RADIO_INTENCLR10_CCAIDLE_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CCAIDLE_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CCAIDLE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCABUSY @Bit 18 : Write '1' to disable interrupt for event CCABUSY */ + #define RADIO_INTENCLR10_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ + #define RADIO_INTENCLR10_CCABUSY_Msk (0x1UL << RADIO_INTENCLR10_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ + #define RADIO_INTENCLR10_CCABUSY_Min (0x0UL) /*!< Min enumerator value of CCABUSY field. */ + #define RADIO_INTENCLR10_CCABUSY_Max (0x1UL) /*!< Max enumerator value of CCABUSY field. */ + #define RADIO_INTENCLR10_CCABUSY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CCABUSY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CCABUSY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCASTOPPED @Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ + #define RADIO_INTENCLR10_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ + #define RADIO_INTENCLR10_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR10_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ + #define RADIO_INTENCLR10_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of CCASTOPPED field. */ + #define RADIO_INTENCLR10_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of CCASTOPPED field. */ + #define RADIO_INTENCLR10_CCASTOPPED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RATEBOOST @Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ + #define RADIO_INTENCLR10_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ + #define RADIO_INTENCLR10_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR10_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ + #define RADIO_INTENCLR10_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of RATEBOOST field. */ + #define RADIO_INTENCLR10_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of RATEBOOST field. */ + #define RADIO_INTENCLR10_RATEBOOST_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled */ + +/* MHRMATCH @Bit 21 : Write '1' to disable interrupt for event MHRMATCH */ + #define RADIO_INTENCLR10_MHRMATCH_Pos (21UL) /*!< Position of MHRMATCH field. */ + #define RADIO_INTENCLR10_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR10_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ + #define RADIO_INTENCLR10_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of MHRMATCH field. */ + #define RADIO_INTENCLR10_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of MHRMATCH field. */ + #define RADIO_INTENCLR10_MHRMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_MHRMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYNC @Bit 22 : Write '1' to disable interrupt for event SYNC */ + #define RADIO_INTENCLR10_SYNC_Pos (22UL) /*!< Position of SYNC field. */ + #define RADIO_INTENCLR10_SYNC_Msk (0x1UL << RADIO_INTENCLR10_SYNC_Pos) /*!< Bit mask of SYNC field. */ + #define RADIO_INTENCLR10_SYNC_Min (0x0UL) /*!< Min enumerator value of SYNC field. */ + #define RADIO_INTENCLR10_SYNC_Max (0x1UL) /*!< Max enumerator value of SYNC field. */ + #define RADIO_INTENCLR10_SYNC_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_SYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_SYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CTEPRESENT @Bit 23 : Write '1' to disable interrupt for event CTEPRESENT */ + #define RADIO_INTENCLR10_CTEPRESENT_Pos (23UL) /*!< Position of CTEPRESENT field. */ + #define RADIO_INTENCLR10_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR10_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ + #define RADIO_INTENCLR10_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of CTEPRESENT field. */ + #define RADIO_INTENCLR10_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of CTEPRESENT field. */ + #define RADIO_INTENCLR10_CTEPRESENT_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_INTENCLR11: Disable interrupt */ + #define RADIO_INTENCLR11_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR11 register. */ + +/* PLLREADY @Bit 12 : Write '1' to disable interrupt for event PLLREADY */ + #define RADIO_INTENCLR11_PLLREADY_Pos (12UL) /*!< Position of PLLREADY field. */ + #define RADIO_INTENCLR11_PLLREADY_Msk (0x1UL << RADIO_INTENCLR11_PLLREADY_Pos) /*!< Bit mask of PLLREADY field. */ + #define RADIO_INTENCLR11_PLLREADY_Min (0x0UL) /*!< Min enumerator value of PLLREADY field. */ + #define RADIO_INTENCLR11_PLLREADY_Max (0x1UL) /*!< Max enumerator value of PLLREADY field. */ + #define RADIO_INTENCLR11_PLLREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR11_PLLREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR11_PLLREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXADDRESS @Bit 15 : Write '1' to disable interrupt for event RXADDRESS */ + #define RADIO_INTENCLR11_RXADDRESS_Pos (15UL) /*!< Position of RXADDRESS field. */ + #define RADIO_INTENCLR11_RXADDRESS_Msk (0x1UL << RADIO_INTENCLR11_RXADDRESS_Pos) /*!< Bit mask of RXADDRESS field. */ + #define RADIO_INTENCLR11_RXADDRESS_Min (0x0UL) /*!< Min enumerator value of RXADDRESS field. */ + #define RADIO_INTENCLR11_RXADDRESS_Max (0x1UL) /*!< Max enumerator value of RXADDRESS field. */ + #define RADIO_INTENCLR11_RXADDRESS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR11_RXADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR11_RXADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* AUXDATADMAEND @Bit 16 : Write '1' to disable interrupt for event AUXDATADMAEND */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Pos (16UL) /*!< Position of AUXDATADMAEND field. */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Msk (0x1UL << RADIO_INTENCLR11_AUXDATADMAEND_Pos) /*!< Bit mask of AUXDATADMAEND + field.*/ + #define RADIO_INTENCLR11_AUXDATADMAEND_Min (0x0UL) /*!< Min enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Max (0x1UL) /*!< Max enumerator value of AUXDATADMAEND field. */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR11_AUXDATADMAEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CSTONESEND @Bit 18 : Write '1' to disable interrupt for event CSTONESEND */ + #define RADIO_INTENCLR11_CSTONESEND_Pos (18UL) /*!< Position of CSTONESEND field. */ + #define RADIO_INTENCLR11_CSTONESEND_Msk (0x1UL << RADIO_INTENCLR11_CSTONESEND_Pos) /*!< Bit mask of CSTONESEND field. */ + #define RADIO_INTENCLR11_CSTONESEND_Min (0x0UL) /*!< Min enumerator value of CSTONESEND field. */ + #define RADIO_INTENCLR11_CSTONESEND_Max (0x1UL) /*!< Max enumerator value of CSTONESEND field. */ + #define RADIO_INTENCLR11_CSTONESEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR11_CSTONESEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR11_CSTONESEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_MODE: Data rate and modulation */ + #define RADIO_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* MODE @Bits 0..3 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */ + #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define RADIO_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define RADIO_MODE_MODE_Max (0xFUL) /*!< Max enumerator value of MODE field. */ + #define RADIO_MODE_MODE_Nrf_1Mbit (0x0UL) /*!< 1 Mbps Nordic proprietary radio mode */ + #define RADIO_MODE_MODE_Nrf_2Mbit (0x1UL) /*!< 2 Mbps Nordic proprietary radio mode */ + #define RADIO_MODE_MODE_Ble_1Mbit (0x3UL) /*!< 1 Mbps BLE */ + #define RADIO_MODE_MODE_Ble_2Mbit (0x4UL) /*!< 2 Mbps BLE */ + #define RADIO_MODE_MODE_Ble_LR125Kbit (0x5UL) /*!< Long range 125 kbps TX, 125 kbps and 500 kbps RX */ + #define RADIO_MODE_MODE_Ble_LR500Kbit (0x6UL) /*!< Long range 500 kbps TX, 125 kbps and 500 kbps RX */ + #define RADIO_MODE_MODE_Nrf_4Mbit_0BT6 (0x9UL) /*!< 4 Mbps Nordic proprietary radio mode (BT=0.6/h=0.5) */ + #define RADIO_MODE_MODE_Nrf_4Mbit_0BT4 (0xAUL) /*!< 4 Mbps Nordic proprietary radio mode (BT=0.4/h=0.5) */ + #define RADIO_MODE_MODE_Ieee802154_250Kbit (0xFUL) /*!< IEEE 802.15.4-2006 250 kbps */ + + +/* RADIO_PHYENDTXDELAY: Configurable delay of PHYEND event for TX */ + #define RADIO_PHYENDTXDELAY_ResetValue (0x00000421UL) /*!< Reset value of PHYENDTXDELAY register. */ + +/* RATE4M @Bits 0..2 : For modes with 4 Mbps on-air bit rate, unit is 2 bit periods (Nrf_4Mbit0_5 and Nrf_4Mbit0_25 modes) */ + #define RADIO_PHYENDTXDELAY_RATE4M_Pos (0UL) /*!< Position of RATE4M field. */ + #define RADIO_PHYENDTXDELAY_RATE4M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE4M_Pos) /*!< Bit mask of RATE4M field. */ + +/* RATE2M @Bits 4..6 : For modes with 2 Mbps on-air bit rate, unit is 1 bit period (Nrf_2Mbit, Ble_2Mbit, and Ieee802154_250Kbit + modes) */ + + #define RADIO_PHYENDTXDELAY_RATE2M_Pos (4UL) /*!< Position of RATE2M field. */ + #define RADIO_PHYENDTXDELAY_RATE2M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE2M_Pos) /*!< Bit mask of RATE2M field. */ + +/* RATE1M @Bits 8..10 : For modes with 1 Mbps on-air bit rate, unit is 1/2 bit period (Nrf_1Mbit and Ble_1Mbit modes) Also used + for Coded phy (Ble_LR125Kbit and Ble_LR500Kbit modes) */ + + #define RADIO_PHYENDTXDELAY_RATE1M_Pos (8UL) /*!< Position of RATE1M field. */ + #define RADIO_PHYENDTXDELAY_RATE1M_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE1M_Pos) /*!< Bit mask of RATE1M field. */ + +/* RATE250K @Bits 12..14 : For modes with 250 kbps on-air bit rate, unit is 1/8 bit period (Nrf_250Kbit mode) */ + #define RADIO_PHYENDTXDELAY_RATE250K_Pos (12UL) /*!< Position of RATE250K field. */ + #define RADIO_PHYENDTXDELAY_RATE250K_Msk (0x7UL << RADIO_PHYENDTXDELAY_RATE250K_Pos) /*!< Bit mask of RATE250K field. */ + + +/* RADIO_STATE: Current radio state */ + #define RADIO_STATE_ResetValue (0x00000000UL) /*!< Reset value of STATE register. */ + +/* STATE @Bits 0..3 : Current radio state */ + #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ + #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ + #define RADIO_STATE_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field. */ + #define RADIO_STATE_STATE_Max (0xCUL) /*!< Max enumerator value of STATE field. */ + #define RADIO_STATE_STATE_Disabled (0x0UL) /*!< RADIO is in the DISABLED state */ + #define RADIO_STATE_STATE_RxRu (0x1UL) /*!< RADIO is in the RXRU state */ + #define RADIO_STATE_STATE_RxIdle (0x2UL) /*!< RADIO is in the RXIDLE state */ + #define RADIO_STATE_STATE_Rx (0x3UL) /*!< RADIO is in the RX state */ + #define RADIO_STATE_STATE_RxDisable (0x4UL) /*!< RADIO is in the RXDISABLE state */ + #define RADIO_STATE_STATE_Settle (0x5UL) /*!< RADIO is in the SETTLE state */ + #define RADIO_STATE_STATE_Pll (0x6UL) /*!< RADIO is in the PLL state */ + #define RADIO_STATE_STATE_TxRu (0x9UL) /*!< RADIO is in the TXRU state */ + #define RADIO_STATE_STATE_TxIdle (0xAUL) /*!< RADIO is in the TXIDLE state */ + #define RADIO_STATE_STATE_Tx (0xBUL) /*!< RADIO is in the TX state */ + #define RADIO_STATE_STATE_TxDisable (0xCUL) /*!< RADIO is in the TXDISABLE state */ + + +/* RADIO_EDCTRL: IEEE 802.15.4 energy detect control */ + #define RADIO_EDCTRL_ResetValue (0x20000000UL) /*!< Reset value of EDCTRL register. */ + +/* EDCNT @Bits 0..20 : IEEE 802.15.4 energy detect loop count */ + #define RADIO_EDCTRL_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */ + #define RADIO_EDCTRL_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCTRL_EDCNT_Pos) /*!< Bit mask of EDCNT field. */ + +/* EDPERIOD @Bits 24..29 : IEEE 802.15.4 energy detect period, 4us resolution, no averaging except the IEEE 802.15.4 ED range + 128us (32) */ + + #define RADIO_EDCTRL_EDPERIOD_Pos (24UL) /*!< Position of EDPERIOD field. */ + #define RADIO_EDCTRL_EDPERIOD_Msk (0x3FUL << RADIO_EDCTRL_EDPERIOD_Pos) /*!< Bit mask of EDPERIOD field. */ + #define RADIO_EDCTRL_EDPERIOD_Min (0x20UL) /*!< Min enumerator value of EDPERIOD field. */ + #define RADIO_EDCTRL_EDPERIOD_Max (0x20UL) /*!< Max enumerator value of EDPERIOD field. */ + #define RADIO_EDCTRL_EDPERIOD_Default (0x20UL) /*!< (unspecified) */ + + +/* RADIO_EDSAMPLE: IEEE 802.15.4 energy detect level */ + #define RADIO_EDSAMPLE_ResetValue (0x00000000UL) /*!< Reset value of EDSAMPLE register. */ + +/* EDLVL @Bits 0..7 : IEEE 802.15.4 energy detect level */ + #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */ + #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */ + #define RADIO_EDSAMPLE_EDLVL_Min (0x00UL) /*!< Min value of EDLVL field. */ + #define RADIO_EDSAMPLE_EDLVL_Max (0x7FUL) /*!< Max size of EDLVL field. */ + + +/* RADIO_CCACTRL: IEEE 802.15.4 clear channel assessment control */ + #define RADIO_CCACTRL_ResetValue (0x052D0000UL) /*!< Reset value of CCACTRL register. */ + +/* CCAMODE @Bits 0..2 : CCA mode of operation */ + #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */ + #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */ + #define RADIO_CCACTRL_CCAMODE_Min (0x0UL) /*!< Min enumerator value of CCAMODE field. */ + #define RADIO_CCACTRL_CCAMODE_Max (0x4UL) /*!< Max enumerator value of CCAMODE field. */ + #define RADIO_CCACTRL_CCAMODE_EdMode (0x0UL) /*!< Energy above threshold */ + #define RADIO_CCACTRL_CCAMODE_CarrierMode (0x1UL) /*!< Carrier seen */ + #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (0x2UL) /*!< Energy above threshold AND carrier seen */ + #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (0x3UL) /*!< Energy above threshold OR carrier seen */ + #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (0x4UL) /*!< Energy above threshold test mode that will abort when first ED + measurement over threshold is seen. No averaging.*/ + +/* CCAEDTHRES @Bits 8..15 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */ + #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */ + #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */ + +/* CCACORRTHRES @Bits 16..23 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and + CarrierOrEdMode. */ + + #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */ + #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */ + +/* CCACORRCNT @Bits 24..31 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect + is enabled. */ + + #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */ + #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */ + + +/* RADIO_DATAWHITE: Data whitening configuration */ + #define RADIO_DATAWHITE_ResetValue (0x00890040UL) /*!< Reset value of DATAWHITE register. */ + +/* IV @Bits 0..8 : Whitening initial value */ + #define RADIO_DATAWHITE_IV_Pos (0UL) /*!< Position of IV field. */ + #define RADIO_DATAWHITE_IV_Msk (0x1FFUL << RADIO_DATAWHITE_IV_Pos) /*!< Bit mask of IV field. */ + +/* POLY @Bits 16..25 : Whitening polynomial */ + #define RADIO_DATAWHITE_POLY_Pos (16UL) /*!< Position of POLY field. */ + #define RADIO_DATAWHITE_POLY_Msk (0x3FFUL << RADIO_DATAWHITE_POLY_Pos) /*!< Bit mask of POLY field. */ + + +/* RADIO_TIMING: Timing */ + #define RADIO_TIMING_ResetValue (0x00000001UL) /*!< Reset value of TIMING register. */ + +/* RU @Bit 0 : Ramp-up time */ + #define RADIO_TIMING_RU_Pos (0UL) /*!< Position of RU field. */ + #define RADIO_TIMING_RU_Msk (0x1UL << RADIO_TIMING_RU_Pos) /*!< Bit mask of RU field. */ + #define RADIO_TIMING_RU_Min (0x0UL) /*!< Min enumerator value of RU field. */ + #define RADIO_TIMING_RU_Max (0x1UL) /*!< Max enumerator value of RU field. */ + #define RADIO_TIMING_RU_Legacy (0x0UL) /*!< Legacy ramp-up time */ + #define RADIO_TIMING_RU_Fast (0x1UL) /*!< Fast ramp-up (default) */ + + +/* RADIO_FREQUENCY: Frequency */ + #define RADIO_FREQUENCY_ResetValue (0x00000002UL) /*!< Reset value of FREQUENCY register. */ + +/* FREQUENCY @Bits 0..6 : Radio channel frequency. Frequency = 2400 + FREQUENCY (MHz). */ + #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ + #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* MAP @Bit 8 : Channel map selection. 0: Channel map between 2400 MHZ to 2500 MHz, Frequency = 2400 + FREQUENCY (MHz). 1: + Channel map between 2360 MHZ to 2460 MHz, Frequency = 2360 + FREQUENCY (MHz). */ + + #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ + #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ + + +/* RADIO_TXPOWER: Output power */ + #define RADIO_TXPOWER_ResetValue (0x00000013UL) /*!< Reset value of TXPOWER register. */ + +/* TXPOWER @Bits 0..10 : RADIO output power */ + #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ + #define RADIO_TXPOWER_TXPOWER_Msk (0x7FFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ + #define RADIO_TXPOWER_TXPOWER_Min (0x000UL) /*!< Min enumerator value of TXPOWER field. */ + #define RADIO_TXPOWER_TXPOWER_Max (0x130UL) /*!< Max enumerator value of TXPOWER field. */ + #define RADIO_TXPOWER_TXPOWER_MaxdBm (0x03FUL) /*!< +8 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x03FUL) /*!< +8 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x039UL) /*!< +7 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x033UL) /*!< +6 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x02DUL) /*!< +5 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x028UL) /*!< +4 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x023UL) /*!< +3 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x01FUL) /*!< +2 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos1dBm (0x01BUL) /*!< +1 dBm */ + #define RADIO_TXPOWER_TXPOWER_0dBm (0x018UL) /*!< 0 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg1dBm (0x015UL) /*!< -1 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg2dBm (0x013UL) /*!< -2 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg3dBm (0x011UL) /*!< -3 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0x00FUL) /*!< -4 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg5dBm (0x00DUL) /*!< -5 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg6dBm (0x00BUL) /*!< -6 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg7dBm (0x00AUL) /*!< -7 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0x009UL) /*!< -8 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg9dBm (0x008UL) /*!< -9 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg10dBm (0x007UL) /*!< -10 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0x006UL) /*!< -12 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg14dBm (0x005UL) /*!< -14 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0x004UL) /*!< -16 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg18dBm (0x003UL) /*!< -18 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0x002UL) /*!< -20 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg22dBm (0x002UL) /*!< -22 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg28dBm (0x001UL) /*!< -28 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0x130UL) /*!< -40 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg46dBm (0x110UL) /*!< -46 dBm */ + #define RADIO_TXPOWER_TXPOWER_MindBm (0x000UL) /*!< Minimum output power */ + + +/* RADIO_TIFS: Interframe spacing in us */ + #define RADIO_TIFS_ResetValue (0x00000000UL) /*!< Reset value of TIFS register. */ + +/* TIFS @Bits 0..9 : Interframe spacing in us. Interframe space is the time interval between two consecutive packets. It is + defined as the time, in microseconds, from the end of the last bit of the previous packet to the start of + the first bit of the subsequent packet. */ + + #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ + #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + + +/* RADIO_RSSISAMPLE: RSSI sample */ + #define RADIO_RSSISAMPLE_ResetValue (0x0000007FUL) /*!< Reset value of RSSISAMPLE register. */ + +/* RSSISAMPLE @Bits 0..6 : RSSI sample result. The value of this register is read as a positive value while the actual received + signal strength is a negative value. Actual received signal strength is therefore as follows: + received signal strength = -A dBm. */ + + #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ + #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + + +/* RADIO_FREQFINETUNE: Fine tuning of the RF frequency */ + #define RADIO_FREQFINETUNE_ResetValue (0x00000000UL) /*!< Reset value of FREQFINETUNE register. */ + +/* FREQFINETUNE @Bits 0..12 : Twos-complement number for fine-tuning the frequency. The step size is 488.28125 Hz, giving a + range from -1 MHz to (one step short of) +1 MHz. */ + + #define RADIO_FREQFINETUNE_FREQFINETUNE_Pos (0UL) /*!< Position of FREQFINETUNE field. */ + #define RADIO_FREQFINETUNE_FREQFINETUNE_Msk (0x1FFFUL << RADIO_FREQFINETUNE_FREQFINETUNE_Pos) /*!< Bit mask of FREQFINETUNE + field.*/ + + +/* RADIO_FECONFIG: Config register */ + #define RADIO_FECONFIG_ResetValue (0x10800005UL) /*!< Reset value of FECONFIG register. */ + +/* SCALERMODE @Bit 20 : Mode for narrow scaling output. */ + #define RADIO_FECONFIG_SCALERMODE_Pos (20UL) /*!< Position of SCALERMODE field. */ + #define RADIO_FECONFIG_SCALERMODE_Msk (0x1UL << RADIO_FECONFIG_SCALERMODE_Pos) /*!< Bit mask of SCALERMODE field. */ + #define RADIO_FECONFIG_SCALERMODE_Min (0x0UL) /*!< Min enumerator value of SCALERMODE field. */ + #define RADIO_FECONFIG_SCALERMODE_Max (0x1UL) /*!< Max enumerator value of SCALERMODE field. */ + #define RADIO_FECONFIG_SCALERMODE_Disabled (0x0UL) /*!< Classic log based scaling mode. */ + #define RADIO_FECONFIG_SCALERMODE_Enabled (0x1UL) /*!< LUT based scaling mode. */ + + +/* RADIO_CFO_STAT: Carrier freq. offset estimate */ + #define RADIO_CFO_STAT_ResetValue (0x00000000UL) /*!< Reset value of CFO_STAT register. */ + +/* SYNCOK @Bit 12 : SYNC ok */ + #define RADIO_CFO_STAT_SYNCOK_Pos (12UL) /*!< Position of SYNCOK field. */ + #define RADIO_CFO_STAT_SYNCOK_Msk (0x1UL << RADIO_CFO_STAT_SYNCOK_Pos) /*!< Bit mask of SYNCOK field. */ + #define RADIO_CFO_STAT_SYNCOK_Min (0x0UL) /*!< Min enumerator value of SYNCOK field. */ + #define RADIO_CFO_STAT_SYNCOK_Max (0x1UL) /*!< Max enumerator value of SYNCOK field. */ + #define RADIO_CFO_STAT_SYNCOK_SyncNotOK (0x0UL) /*!< (unspecified) */ + #define RADIO_CFO_STAT_SYNCOK_SyncOk (0x1UL) /*!< (unspecified) */ + + +/* RADIO_DBCCORR: Correlator thresholds */ + #define RADIO_DBCCORR_ResetValue (0x1FFFFF90UL) /*!< Reset value of DBCCORR register. */ + +/* TH @Bits 0..7 : Correlation threshold */ + #define RADIO_DBCCORR_TH_Pos (0UL) /*!< Position of TH field. */ + #define RADIO_DBCCORR_TH_Msk (0xFFUL << RADIO_DBCCORR_TH_Pos) /*!< Bit mask of TH field. */ + + +/* RADIO_DFEMODE: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */ + #define RADIO_DFEMODE_ResetValue (0x00000000UL) /*!< Reset value of DFEMODE register. */ + +/* DFEOPMODE @Bits 0..1 : Direction finding operation mode */ + #define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */ + #define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */ + #define RADIO_DFEMODE_DFEOPMODE_Min (0x0UL) /*!< Min enumerator value of DFEOPMODE field. */ + #define RADIO_DFEMODE_DFEOPMODE_Max (0x3UL) /*!< Max enumerator value of DFEOPMODE field. */ + #define RADIO_DFEMODE_DFEOPMODE_Disabled (0x0UL) /*!< Direction finding mode disabled */ + #define RADIO_DFEMODE_DFEOPMODE_AoD (0x2UL) /*!< Direction finding mode set to AoD */ + #define RADIO_DFEMODE_DFEOPMODE_AoA (0x3UL) /*!< Direction finding mode set to AoA */ + + +/* RADIO_DFESTATUS: DFE status information */ + #define RADIO_DFESTATUS_ResetValue (0x00000000UL) /*!< Reset value of DFESTATUS register. */ + +/* SWITCHINGSTATE @Bits 0..2 : Internal state of switching state machine */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE + field.*/ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Min (0x0UL) /*!< Min enumerator value of SWITCHINGSTATE field. */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Max (0x5UL) /*!< Max enumerator value of SWITCHINGSTATE field. */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0x0UL) /*!< Switching state Idle */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (0x1UL) /*!< Switching state Offset */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (0x2UL) /*!< Switching state Guard */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (0x3UL) /*!< Switching state Ref */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (0x4UL) /*!< Switching state Switching */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (0x5UL) /*!< Switching state Ending */ + +/* SAMPLINGSTATE @Bit 4 : Internal state of sampling state machine */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Min (0x0UL) /*!< Min enumerator value of SAMPLINGSTATE field. */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Max (0x1UL) /*!< Max enumerator value of SAMPLINGSTATE field. */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0x0UL) /*!< Sampling state Idle */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (0x1UL) /*!< Sampling state Sampling */ + + +/* RADIO_DFECTRL1: Various configuration for Direction finding */ + #define RADIO_DFECTRL1_ResetValue (0x00023282UL) /*!< Reset value of DFECTRL1 register. */ + +/* NUMBEROF8US @Bits 0..5 : Length of the AoA/AoD procedure in number of 8 us units */ + #define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */ + #define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */ + +/* DFEINEXTENSION @Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */ + #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */ + #define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field.*/ + #define RADIO_DFECTRL1_DFEINEXTENSION_Min (0x0UL) /*!< Min enumerator value of DFEINEXTENSION field. */ + #define RADIO_DFECTRL1_DFEINEXTENSION_Max (0x1UL) /*!< Max enumerator value of DFEINEXTENSION field. */ + #define RADIO_DFECTRL1_DFEINEXTENSION_CRC (0x1UL) /*!< AoA/AoD procedure triggered at end of CRC */ + #define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0x0UL) /*!< Antenna switching/sampling is done in the packet payload */ + +/* TSWITCHSPACING @Bits 8..10 : Interval between every time the antenna is changed in the SWITCHING state */ + #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */ + #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field.*/ + #define RADIO_DFECTRL1_TSWITCHSPACING_Min (0x1UL) /*!< Min enumerator value of TSWITCHSPACING field. */ + #define RADIO_DFECTRL1_TSWITCHSPACING_Max (0x3UL) /*!< Max enumerator value of TSWITCHSPACING field. */ + #define RADIO_DFECTRL1_TSWITCHSPACING_4us (0x1UL) /*!< 4us */ + #define RADIO_DFECTRL1_TSWITCHSPACING_2us (0x2UL) /*!< 2us */ + #define RADIO_DFECTRL1_TSWITCHSPACING_1us (0x3UL) /*!< 1us */ + +/* TSAMPLESPACINGREF @Bits 12..14 : Interval between samples in the REFERENCE period */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of + TSAMPLESPACINGREF field.*/ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Min (0x1UL) /*!< Min enumerator value of TSAMPLESPACINGREF field. */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Max (0x6UL) /*!< Max enumerator value of TSAMPLESPACINGREF field. */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (0x1UL) /*!< 4us */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (0x2UL) /*!< 2us */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (0x3UL) /*!< 1us */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (0x4UL) /*!< 0.5us */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (0x5UL) /*!< 0.25us */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (0x6UL) /*!< 0.125us */ + +/* SAMPLETYPE @Bit 15 : Whether to sample I/Q or magnitude/phase */ + #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */ + #define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */ + #define RADIO_DFECTRL1_SAMPLETYPE_Min (0x0UL) /*!< Min enumerator value of SAMPLETYPE field. */ + #define RADIO_DFECTRL1_SAMPLETYPE_Max (0x1UL) /*!< Max enumerator value of SAMPLETYPE field. */ + #define RADIO_DFECTRL1_SAMPLETYPE_IQ (0x0UL) /*!< Complex samples in I and Q */ + #define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (0x1UL) /*!< Complex samples as magnitude and phase */ + +/* TSAMPLESPACING @Bits 16..18 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */ + #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */ + #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field.*/ + #define RADIO_DFECTRL1_TSAMPLESPACING_Min (0x1UL) /*!< Min enumerator value of TSAMPLESPACING field. */ + #define RADIO_DFECTRL1_TSAMPLESPACING_Max (0x6UL) /*!< Max enumerator value of TSAMPLESPACING field. */ + #define RADIO_DFECTRL1_TSAMPLESPACING_4us (0x1UL) /*!< 4us */ + #define RADIO_DFECTRL1_TSAMPLESPACING_2us (0x2UL) /*!< 2us */ + #define RADIO_DFECTRL1_TSAMPLESPACING_1us (0x3UL) /*!< 1us */ + #define RADIO_DFECTRL1_TSAMPLESPACING_500ns (0x4UL) /*!< 0.5us */ + #define RADIO_DFECTRL1_TSAMPLESPACING_250ns (0x5UL) /*!< 0.25us */ + #define RADIO_DFECTRL1_TSAMPLESPACING_125ns (0x6UL) /*!< 0.125us */ + +/* REPEATPATTERN @Bits 20..23 : Repeat every antenna pattern N times. */ + #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL) /*!< Position of REPEATPATTERN field. */ + #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field. */ + #define RADIO_DFECTRL1_REPEATPATTERN_Min (0x0UL) /*!< Min enumerator value of REPEATPATTERN field. */ + #define RADIO_DFECTRL1_REPEATPATTERN_Max (0x0UL) /*!< Max enumerator value of REPEATPATTERN field. */ + #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0x0UL) /*!< Do not repeat (1 time in total) */ + +/* AGCBACKOFFGAIN @Bits 24..27 : Gain will be lowered by the specified number of gain steps at the start of CTE */ + #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */ + #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field.*/ + + +/* RADIO_DFECTRL2: Start offset for Direction finding */ + #define RADIO_DFECTRL2_ResetValue (0x00000000UL) /*!< Reset value of DFECTRL2 register. */ + +/* TSWITCHOFFSET @Bits 0..12 : Signed value offset after the end of the CRC before starting switching in number of 16M cycles */ + #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */ + #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field.*/ + +/* TSAMPLEOFFSET @Bits 16..27 : Signed value offset before starting sampling in number of 16M cycles relative to the beginning + of the REFERENCE state - 12 us after switching start */ + + #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */ + #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */ + + +/* RADIO_SWITCHPATTERN: GPIO patterns to be used for each antenna */ + #define RADIO_SWITCHPATTERN_ResetValue (0x00000000UL) /*!< Reset value of SWITCHPATTERN register. */ + +/* SWITCHPATTERN @Bits 0..7 : Fill array of GPIO patterns for antenna control */ + #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */ + #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN + field.*/ + + +/* RADIO_CLEARPATTERN: Clear the GPIO pattern array for antenna control */ + #define RADIO_CLEARPATTERN_ResetValue (0x00000000UL) /*!< Reset value of CLEARPATTERN register. */ + +/* CLEARPATTERN @Bit 0 : Clear the GPIO pattern array for antenna control Behaves as a task register, but does not have PPI nor + IRQ */ + + #define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */ + #define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN + field.*/ + + +/* RADIO_CRCSTATUS: CRC status */ + #define RADIO_CRCSTATUS_ResetValue (0x00000000UL) /*!< Reset value of CRCSTATUS register. */ + +/* CRCSTATUS @Bit 0 : CRC status of packet received */ + #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ + #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ + #define RADIO_CRCSTATUS_CRCSTATUS_Min (0x0UL) /*!< Min enumerator value of CRCSTATUS field. */ + #define RADIO_CRCSTATUS_CRCSTATUS_Max (0x1UL) /*!< Max enumerator value of CRCSTATUS field. */ + #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0x0UL) /*!< Packet received with CRC error */ + #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (0x1UL) /*!< Packet received with CRC ok */ + + +/* RADIO_RXMATCH: Received address */ + #define RADIO_RXMATCH_ResetValue (0x00000000UL) /*!< Reset value of RXMATCH register. */ + +/* RXMATCH @Bits 0..2 : Received address */ + #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ + #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + + +/* RADIO_RXCRC: CRC field of previously received packet */ + #define RADIO_RXCRC_ResetValue (0x00000000UL) /*!< Reset value of RXCRC register. */ + +/* RXCRC @Bits 0..23 : CRC field of previously received packet */ + #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ + #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + + +/* RADIO_DAI: Device address match index */ + #define RADIO_DAI_ResetValue (0x00000000UL) /*!< Reset value of DAI register. */ + +/* DAI @Bits 0..2 : Device address match index */ + #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ + #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + + +/* RADIO_PDUSTAT: Payload status */ + #define RADIO_PDUSTAT_ResetValue (0x00000000UL) /*!< Reset value of PDUSTAT register. */ + +/* PDUSTAT @Bit 0 : Status on payload length vs. PCNF1.MAXLEN */ + #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */ + #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */ + #define RADIO_PDUSTAT_PDUSTAT_Min (0x0UL) /*!< Min enumerator value of PDUSTAT field. */ + #define RADIO_PDUSTAT_PDUSTAT_Max (0x1UL) /*!< Max enumerator value of PDUSTAT field. */ + #define RADIO_PDUSTAT_PDUSTAT_LessThan (0x0UL) /*!< Payload less than PCNF1.MAXLEN */ + #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (0x1UL) /*!< Payload greater than PCNF1.MAXLEN */ + +/* CISTAT @Bits 1..2 : Status on what rate packet is received with in Long Range */ + #define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */ + #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */ + #define RADIO_PDUSTAT_CISTAT_Min (0x0UL) /*!< Min enumerator value of CISTAT field. */ + #define RADIO_PDUSTAT_CISTAT_Max (0x1UL) /*!< Max enumerator value of CISTAT field. */ + #define RADIO_PDUSTAT_CISTAT_LR125kbit (0x0UL) /*!< Frame is received at 125 kbps */ + #define RADIO_PDUSTAT_CISTAT_LR500kbit (0x1UL) /*!< Frame is received at 500 kbps */ + + +/* RADIO_PCNF0: Packet configuration register 0 */ + #define RADIO_PCNF0_ResetValue (0x00000000UL) /*!< Reset value of PCNF0 register. */ + +/* LFLEN @Bits 0..3 : Length on air of LENGTH field in number of bits. */ + #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ + #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* S0LEN @Bit 8 : Length on air of S0 field in number of bytes. */ + #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ + #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* S1LEN @Bits 16..19 : Length on air of S1 field in number of bits. */ + #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ + #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* S1INCL @Bits 20..21 : Include or exclude S1 field in RAM */ + #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ + #define RADIO_PCNF0_S1INCL_Msk (0x3UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ + #define RADIO_PCNF0_S1INCL_Min (0x0UL) /*!< Min enumerator value of S1INCL field. */ + #define RADIO_PCNF0_S1INCL_Max (0x1UL) /*!< Max enumerator value of S1INCL field. */ + #define RADIO_PCNF0_S1INCL_Automatic (0x0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ + #define RADIO_PCNF0_S1INCL_Include (0x1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* CILEN @Bits 22..23 : Length of code indicator - long range */ + #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ + #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ + +/* PLEN @Bits 24..25 : Length of preamble on air. Decision point: TASKS_START task */ + #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ + #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ + #define RADIO_PCNF0_PLEN_Min (0x0UL) /*!< Min enumerator value of PLEN field. */ + #define RADIO_PCNF0_PLEN_Max (0x3UL) /*!< Max enumerator value of PLEN field. */ + #define RADIO_PCNF0_PLEN_8bit (0x0UL) /*!< 8-bit preamble */ + #define RADIO_PCNF0_PLEN_16bit (0x1UL) /*!< 16-bit preamble */ + #define RADIO_PCNF0_PLEN_32bitZero (0x2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ + #define RADIO_PCNF0_PLEN_LongRange (0x3UL) /*!< Preamble - used for BLE long range */ + +/* CRCINC @Bit 26 : Indicates if LENGTH field contains CRC or not */ + #define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */ + #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */ + #define RADIO_PCNF0_CRCINC_Min (0x0UL) /*!< Min enumerator value of CRCINC field. */ + #define RADIO_PCNF0_CRCINC_Max (0x1UL) /*!< Max enumerator value of CRCINC field. */ + #define RADIO_PCNF0_CRCINC_Exclude (0x0UL) /*!< LENGTH does not contain CRC */ + #define RADIO_PCNF0_CRCINC_Include (0x1UL) /*!< LENGTH includes CRC */ + +/* TERMLEN @Bits 29..30 : Length of TERM field in Long Range operation */ + #define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */ + #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */ + + +/* RADIO_PCNF1: Packet configuration register 1 */ + #define RADIO_PCNF1_ResetValue (0x00000000UL) /*!< Reset value of PCNF1 register. */ + +/* MAXLEN @Bits 0..7 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate + the payload to MAXLEN. */ + + #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ + #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + #define RADIO_PCNF1_MAXLEN_Min (0x00UL) /*!< Min value of MAXLEN field. */ + #define RADIO_PCNF1_MAXLEN_Max (0xFFUL) /*!< Max size of MAXLEN field. */ + +/* STATLEN @Bits 8..15 : Static length in number of bytes */ + #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ + #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + #define RADIO_PCNF1_STATLEN_Min (0x00UL) /*!< Min value of STATLEN field. */ + #define RADIO_PCNF1_STATLEN_Max (0xFFUL) /*!< Max size of STATLEN field. */ + +/* BALEN @Bits 16..18 : Base address length in number of bytes */ + #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ + #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + #define RADIO_PCNF1_BALEN_Min (0x1UL) /*!< Min value of BALEN field. */ + #define RADIO_PCNF1_BALEN_Max (0x1UL) /*!< Max size of BALEN field. */ + +/* ENDIAN @Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */ + #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ + #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ + #define RADIO_PCNF1_ENDIAN_Min (0x0UL) /*!< Min enumerator value of ENDIAN field. */ + #define RADIO_PCNF1_ENDIAN_Max (0x1UL) /*!< Max enumerator value of ENDIAN field. */ + #define RADIO_PCNF1_ENDIAN_Little (0x0UL) /*!< Least significant bit on air first */ + #define RADIO_PCNF1_ENDIAN_Big (0x1UL) /*!< Most significant bit on air first */ + +/* WHITEEN @Bit 25 : Enable or disable packet whitening */ + #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ + #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ + #define RADIO_PCNF1_WHITEEN_Min (0x0UL) /*!< Min enumerator value of WHITEEN field. */ + #define RADIO_PCNF1_WHITEEN_Max (0x1UL) /*!< Max enumerator value of WHITEEN field. */ + #define RADIO_PCNF1_WHITEEN_Disabled (0x0UL) /*!< Disable */ + #define RADIO_PCNF1_WHITEEN_Enabled (0x1UL) /*!< Enable */ + +/* WHITEOFFSET @Bit 26 : If whitening is enabled S0 can be configured to be excluded from whitening */ + #define RADIO_PCNF1_WHITEOFFSET_Pos (26UL) /*!< Position of WHITEOFFSET field. */ + #define RADIO_PCNF1_WHITEOFFSET_Msk (0x1UL << RADIO_PCNF1_WHITEOFFSET_Pos) /*!< Bit mask of WHITEOFFSET field. */ + #define RADIO_PCNF1_WHITEOFFSET_Min (0x0UL) /*!< Min enumerator value of WHITEOFFSET field. */ + #define RADIO_PCNF1_WHITEOFFSET_Max (0x1UL) /*!< Max enumerator value of WHITEOFFSET field. */ + #define RADIO_PCNF1_WHITEOFFSET_Include (0x0UL) /*!< S0 included in whitening */ + #define RADIO_PCNF1_WHITEOFFSET_Exclude (0x1UL) /*!< S0 excluded from whitening */ + + +/* RADIO_BASE0: Base address 0 */ + #define RADIO_BASE0_ResetValue (0x00000000UL) /*!< Reset value of BASE0 register. */ + +/* BASE0 @Bits 0..31 : Base address 0 */ + #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ + #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + + +/* RADIO_BASE1: Base address 1 */ + #define RADIO_BASE1_ResetValue (0x00000000UL) /*!< Reset value of BASE1 register. */ + +/* BASE1 @Bits 0..31 : Base address 1 */ + #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ + #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + + +/* RADIO_PREFIX0: Prefixes bytes for logical addresses 0-3 */ + #define RADIO_PREFIX0_ResetValue (0x00000000UL) /*!< Reset value of PREFIX0 register. */ + +/* AP0 @Bits 0..7 : Address prefix 0 */ + #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ + #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* AP1 @Bits 8..15 : Address prefix 1 */ + #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ + #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* AP2 @Bits 16..23 : Address prefix 2 */ + #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ + #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* AP3 @Bits 24..31 : Address prefix 3 */ + #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ + #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + + +/* RADIO_PREFIX1: Prefixes bytes for logical addresses 4-7 */ + #define RADIO_PREFIX1_ResetValue (0x00000000UL) /*!< Reset value of PREFIX1 register. */ + +/* AP4 @Bits 0..7 : Address prefix 4 */ + #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ + #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* AP5 @Bits 8..15 : Address prefix 5 */ + #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ + #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* AP6 @Bits 16..23 : Address prefix 6 */ + #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ + #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* AP7 @Bits 24..31 : Address prefix 7 */ + #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ + #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + + +/* RADIO_TXADDRESS: Transmit address select */ + #define RADIO_TXADDRESS_ResetValue (0x00000000UL) /*!< Reset value of TXADDRESS register. */ + +/* TXADDRESS @Bits 0..2 : Transmit address select */ + #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ + #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + + +/* RADIO_RXADDRESSES: Receive address select */ + #define RADIO_RXADDRESSES_ResetValue (0x00000000UL) /*!< Reset value of RXADDRESSES register. */ + +/* ADDR0 @Bit 0 : Enable or disable reception on logical address 0 */ + #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ + #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ + #define RADIO_RXADDRESSES_ADDR0_Min (0x0UL) /*!< Min enumerator value of ADDR0 field. */ + #define RADIO_RXADDRESSES_ADDR0_Max (0x1UL) /*!< Max enumerator value of ADDR0 field. */ + #define RADIO_RXADDRESSES_ADDR0_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR0_Enabled (0x1UL) /*!< Enable */ + +/* ADDR1 @Bit 1 : Enable or disable reception on logical address 1 */ + #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ + #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ + #define RADIO_RXADDRESSES_ADDR1_Min (0x0UL) /*!< Min enumerator value of ADDR1 field. */ + #define RADIO_RXADDRESSES_ADDR1_Max (0x1UL) /*!< Max enumerator value of ADDR1 field. */ + #define RADIO_RXADDRESSES_ADDR1_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR1_Enabled (0x1UL) /*!< Enable */ + +/* ADDR2 @Bit 2 : Enable or disable reception on logical address 2 */ + #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ + #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ + #define RADIO_RXADDRESSES_ADDR2_Min (0x0UL) /*!< Min enumerator value of ADDR2 field. */ + #define RADIO_RXADDRESSES_ADDR2_Max (0x1UL) /*!< Max enumerator value of ADDR2 field. */ + #define RADIO_RXADDRESSES_ADDR2_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR2_Enabled (0x1UL) /*!< Enable */ + +/* ADDR3 @Bit 3 : Enable or disable reception on logical address 3 */ + #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ + #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ + #define RADIO_RXADDRESSES_ADDR3_Min (0x0UL) /*!< Min enumerator value of ADDR3 field. */ + #define RADIO_RXADDRESSES_ADDR3_Max (0x1UL) /*!< Max enumerator value of ADDR3 field. */ + #define RADIO_RXADDRESSES_ADDR3_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR3_Enabled (0x1UL) /*!< Enable */ + +/* ADDR4 @Bit 4 : Enable or disable reception on logical address 4 */ + #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ + #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ + #define RADIO_RXADDRESSES_ADDR4_Min (0x0UL) /*!< Min enumerator value of ADDR4 field. */ + #define RADIO_RXADDRESSES_ADDR4_Max (0x1UL) /*!< Max enumerator value of ADDR4 field. */ + #define RADIO_RXADDRESSES_ADDR4_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR4_Enabled (0x1UL) /*!< Enable */ + +/* ADDR5 @Bit 5 : Enable or disable reception on logical address 5 */ + #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ + #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ + #define RADIO_RXADDRESSES_ADDR5_Min (0x0UL) /*!< Min enumerator value of ADDR5 field. */ + #define RADIO_RXADDRESSES_ADDR5_Max (0x1UL) /*!< Max enumerator value of ADDR5 field. */ + #define RADIO_RXADDRESSES_ADDR5_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR5_Enabled (0x1UL) /*!< Enable */ + +/* ADDR6 @Bit 6 : Enable or disable reception on logical address 6 */ + #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ + #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ + #define RADIO_RXADDRESSES_ADDR6_Min (0x0UL) /*!< Min enumerator value of ADDR6 field. */ + #define RADIO_RXADDRESSES_ADDR6_Max (0x1UL) /*!< Max enumerator value of ADDR6 field. */ + #define RADIO_RXADDRESSES_ADDR6_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR6_Enabled (0x1UL) /*!< Enable */ + +/* ADDR7 @Bit 7 : Enable or disable reception on logical address 7 */ + #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ + #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ + #define RADIO_RXADDRESSES_ADDR7_Min (0x0UL) /*!< Min enumerator value of ADDR7 field. */ + #define RADIO_RXADDRESSES_ADDR7_Max (0x1UL) /*!< Max enumerator value of ADDR7 field. */ + #define RADIO_RXADDRESSES_ADDR7_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR7_Enabled (0x1UL) /*!< Enable */ + + +/* RADIO_CRCCNF: CRC configuration */ + #define RADIO_CRCCNF_ResetValue (0x00000000UL) /*!< Reset value of CRCCNF register. */ + +/* LEN @Bits 0..1 : CRC length in number of bytes. */ + #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ + #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ + #define RADIO_CRCCNF_LEN_Min (0x0UL) /*!< Min enumerator value of LEN field. */ + #define RADIO_CRCCNF_LEN_Max (0x3UL) /*!< Max enumerator value of LEN field. */ + #define RADIO_CRCCNF_LEN_Disabled (0x0UL) /*!< CRC length is zero and CRC calculation is disabled */ + #define RADIO_CRCCNF_LEN_One (0x1UL) /*!< CRC length is one byte and CRC calculation is enabled */ + #define RADIO_CRCCNF_LEN_Two (0x2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ + #define RADIO_CRCCNF_LEN_Three (0x3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* SKIPADDR @Bits 8..10 : Control whether CRC calculation skips the address field. Other fields can also be skipped. */ + #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ + #define RADIO_CRCCNF_SKIPADDR_Msk (0x7UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ + #define RADIO_CRCCNF_SKIPADDR_Min (0x0UL) /*!< Min enumerator value of SKIPADDR field. */ + #define RADIO_CRCCNF_SKIPADDR_Max (0x4UL) /*!< Max enumerator value of SKIPADDR field. */ + #define RADIO_CRCCNF_SKIPADDR_Include (0x0UL) /*!< CRC calculation includes address field */ + #define RADIO_CRCCNF_SKIPADDR_Skip (0x1UL) /*!< CRC calculation starting at first byte after address field. */ + #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (0x2UL) /*!< CRC calculation starting at first byte after length field (as per + 802.15.4 standard).*/ + #define RADIO_CRCCNF_SKIPADDR_SkipS0 (0x3UL) /*!< CRC calculation starting at first byte after S0 field. */ + #define RADIO_CRCCNF_SKIPADDR_SkipS1 (0x4UL) /*!< CRC calculation starting at first byte after S1 field. */ + + +/* RADIO_CRCPOLY: CRC polynomial */ + #define RADIO_CRCPOLY_ResetValue (0x00000000UL) /*!< Reset value of CRCPOLY register. */ + +/* CRCPOLY @Bits 0..23 : CRC polynomial */ + #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ + #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + + +/* RADIO_CRCINIT: CRC initial value */ + #define RADIO_CRCINIT_ResetValue (0x00000000UL) /*!< Reset value of CRCINIT register. */ + +/* CRCINIT @Bits 0..23 : CRC initial value */ + #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ + #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + + +/* RADIO_DAB: Device address base segment n */ + #define RADIO_DAB_MaxCount (8UL) /*!< Max size of DAB[8] array. */ + #define RADIO_DAB_MaxIndex (7UL) /*!< Max index of DAB[8] array. */ + #define RADIO_DAB_MinIndex (0UL) /*!< Min index of DAB[8] array. */ + #define RADIO_DAB_ResetValue (0x00000000UL) /*!< Reset value of DAB[8] register. */ + +/* DAB @Bits 0..31 : Device address base segment n */ + #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ + #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + + +/* RADIO_DAP: Device address prefix n */ + #define RADIO_DAP_MaxCount (8UL) /*!< Max size of DAP[8] array. */ + #define RADIO_DAP_MaxIndex (7UL) /*!< Max index of DAP[8] array. */ + #define RADIO_DAP_MinIndex (0UL) /*!< Min index of DAP[8] array. */ + #define RADIO_DAP_ResetValue (0x00000000UL) /*!< Reset value of DAP[8] register. */ + +/* DAP @Bits 0..15 : Device address prefix n */ + #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ + #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + + +/* RADIO_DACNF: Device address match configuration */ + #define RADIO_DACNF_ResetValue (0x00000000UL) /*!< Reset value of DACNF register. */ + +/* ENA0 @Bit 0 : Enable or disable device address matching using device address 0 */ + #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ + #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ + #define RADIO_DACNF_ENA0_Min (0x0UL) /*!< Min enumerator value of ENA0 field. */ + #define RADIO_DACNF_ENA0_Max (0x1UL) /*!< Max enumerator value of ENA0 field. */ + #define RADIO_DACNF_ENA0_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA0_Enabled (0x1UL) /*!< Enabled */ + +/* ENA1 @Bit 1 : Enable or disable device address matching using device address 1 */ + #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ + #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ + #define RADIO_DACNF_ENA1_Min (0x0UL) /*!< Min enumerator value of ENA1 field. */ + #define RADIO_DACNF_ENA1_Max (0x1UL) /*!< Max enumerator value of ENA1 field. */ + #define RADIO_DACNF_ENA1_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA1_Enabled (0x1UL) /*!< Enabled */ + +/* ENA2 @Bit 2 : Enable or disable device address matching using device address 2 */ + #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ + #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ + #define RADIO_DACNF_ENA2_Min (0x0UL) /*!< Min enumerator value of ENA2 field. */ + #define RADIO_DACNF_ENA2_Max (0x1UL) /*!< Max enumerator value of ENA2 field. */ + #define RADIO_DACNF_ENA2_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA2_Enabled (0x1UL) /*!< Enabled */ + +/* ENA3 @Bit 3 : Enable or disable device address matching using device address 3 */ + #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ + #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ + #define RADIO_DACNF_ENA3_Min (0x0UL) /*!< Min enumerator value of ENA3 field. */ + #define RADIO_DACNF_ENA3_Max (0x1UL) /*!< Max enumerator value of ENA3 field. */ + #define RADIO_DACNF_ENA3_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA3_Enabled (0x1UL) /*!< Enabled */ + +/* ENA4 @Bit 4 : Enable or disable device address matching using device address 4 */ + #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ + #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ + #define RADIO_DACNF_ENA4_Min (0x0UL) /*!< Min enumerator value of ENA4 field. */ + #define RADIO_DACNF_ENA4_Max (0x1UL) /*!< Max enumerator value of ENA4 field. */ + #define RADIO_DACNF_ENA4_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA4_Enabled (0x1UL) /*!< Enabled */ + +/* ENA5 @Bit 5 : Enable or disable device address matching using device address 5 */ + #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ + #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ + #define RADIO_DACNF_ENA5_Min (0x0UL) /*!< Min enumerator value of ENA5 field. */ + #define RADIO_DACNF_ENA5_Max (0x1UL) /*!< Max enumerator value of ENA5 field. */ + #define RADIO_DACNF_ENA5_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA5_Enabled (0x1UL) /*!< Enabled */ + +/* ENA6 @Bit 6 : Enable or disable device address matching using device address 6 */ + #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ + #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ + #define RADIO_DACNF_ENA6_Min (0x0UL) /*!< Min enumerator value of ENA6 field. */ + #define RADIO_DACNF_ENA6_Max (0x1UL) /*!< Max enumerator value of ENA6 field. */ + #define RADIO_DACNF_ENA6_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA6_Enabled (0x1UL) /*!< Enabled */ + +/* ENA7 @Bit 7 : Enable or disable device address matching using device address 7 */ + #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ + #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ + #define RADIO_DACNF_ENA7_Min (0x0UL) /*!< Min enumerator value of ENA7 field. */ + #define RADIO_DACNF_ENA7_Max (0x1UL) /*!< Max enumerator value of ENA7 field. */ + #define RADIO_DACNF_ENA7_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA7_Enabled (0x1UL) /*!< Enabled */ + +/* TXADD0 @Bit 8 : TxAdd for device address 0 */ + #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ + #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* TXADD1 @Bit 9 : TxAdd for device address 1 */ + #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ + #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* TXADD2 @Bit 10 : TxAdd for device address 2 */ + #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ + #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* TXADD3 @Bit 11 : TxAdd for device address 3 */ + #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ + #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* TXADD4 @Bit 12 : TxAdd for device address 4 */ + #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ + #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* TXADD5 @Bit 13 : TxAdd for device address 5 */ + #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ + #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* TXADD6 @Bit 14 : TxAdd for device address 6 */ + #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ + #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* TXADD7 @Bit 15 : TxAdd for device address 7 */ + #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ + #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + + +/* RADIO_BCC: Bit counter compare */ + #define RADIO_BCC_ResetValue (0x00000000UL) /*!< Reset value of BCC register. */ + +/* BCC @Bits 0..31 : Bit counter compare */ + #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ + #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + + +/* RADIO_CTESTATUS: CTEInfo parsed from received packet */ + #define RADIO_CTESTATUS_ResetValue (0x00000000UL) /*!< Reset value of CTESTATUS register. */ + +/* CTETIME @Bits 0..4 : CTETime parsed from packet */ + #define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */ + #define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */ + +/* RFU @Bit 5 : RFU parsed from packet */ + #define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */ + #define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */ + +/* CTETYPE @Bits 6..7 : CTEType parsed from packet */ + #define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */ + #define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */ + + +/* RADIO_MHRMATCHCONF: Search pattern configuration */ + #define RADIO_MHRMATCHCONF_ResetValue (0x00000000UL) /*!< Reset value of MHRMATCHCONF register. */ + +/* MHRMATCHCONF @Bits 0..31 : Search pattern configuration */ + #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */ + #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of + MHRMATCHCONF field.*/ + + +/* RADIO_MHRMATCHMASK: Pattern mask */ + #define RADIO_MHRMATCHMASK_ResetValue (0x00000000UL) /*!< Reset value of MHRMATCHMASK register. */ + +/* MHRMATCHMASK @Bits 0..31 : Pattern mask */ + #define RADIO_MHRMATCHMASK_MHRMATCHMASK_Pos (0UL) /*!< Position of MHRMATCHMASK field. */ + #define RADIO_MHRMATCHMASK_MHRMATCHMASK_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMASK_MHRMATCHMASK_Pos) /*!< Bit mask of + MHRMATCHMASK field.*/ + + +/* RADIO_SFD: IEEE 802.15.4 start of frame delimiter */ + #define RADIO_SFD_ResetValue (0x000000A7UL) /*!< Reset value of SFD register. */ + +/* SFD @Bits 0..7 : IEEE 802.15.4 start of frame delimiter. Note: the least significant 4 bits of the SFD cannot all be zeros. */ + #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */ + #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */ + + +/* RADIO_CTEINLINECONF: Configuration for CTE inline mode */ + #define RADIO_CTEINLINECONF_ResetValue (0x00002800UL) /*!< Reset value of CTEINLINECONF register. */ + +/* CTEINLINECTRLEN @Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of + CTEINLINECTRLEN field.*/ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Min (0x0UL) /*!< Min enumerator value of CTEINLINECTRLEN field. */ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Max (0x1UL) /*!< Max enumerator value of CTEINLINECTRLEN field. */ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (0x1UL) /*!< Parsing of CTEInfo is enabled */ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0x0UL) /*!< Parsing of CTEInfo is disabled */ + +/* CTEINFOINS1 @Bit 3 : CTEInfo is S1 byte or not */ + #define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */ + #define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 + field.*/ + #define RADIO_CTEINLINECONF_CTEINFOINS1_Min (0x0UL) /*!< Min enumerator value of CTEINFOINS1 field. */ + #define RADIO_CTEINLINECONF_CTEINFOINS1_Max (0x1UL) /*!< Max enumerator value of CTEINFOINS1 field. */ + #define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (0x1UL) /*!< CTEInfo is in S1 byte (data PDU) */ + #define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0x0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */ + +/* CTEERRORHANDLING @Bit 4 : Sampling/switching if CRC is not OK */ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of + CTEERRORHANDLING field.*/ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Min (0x0UL) /*!< Min enumerator value of CTEERRORHANDLING field. */ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Max (0x1UL) /*!< Max enumerator value of CTEERRORHANDLING field. */ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (0x1UL) /*!< Sampling and antenna switching also when CRC is not OK */ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0x0UL) /*!< No sampling and antenna switching when CRC is not OK */ + +/* CTETIMEVALIDRANGE @Bits 6..7 : Max range of CTETime */ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of + CTETIMEVALIDRANGE field.*/ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Min (0x0UL) /*!< Min enumerator value of CTETIMEVALIDRANGE field. */ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Max (0x2UL) /*!< Max enumerator value of CTETIMEVALIDRANGE field. */ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0x0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger + han 20*/ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (0x1UL) /*!< 31 in 8us unit */ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (0x2UL) /*!< 63 in 8us unit */ + +/* CTEINLINERXMODE1US @Bits 10..12 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of + CTEINLINERXMODE1US field.*/ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Min (0x1UL) /*!< Min enumerator value of CTEINLINERXMODE1US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Max (0x6UL) /*!< Max enumerator value of CTEINLINERXMODE1US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (0x1UL) /*!< 4us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (0x2UL) /*!< 2us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (0x3UL) /*!< 1us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (0x4UL) /*!< 0.5us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (0x5UL) /*!< 0.25us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (0x6UL) /*!< 0.125us */ + +/* CTEINLINERXMODE2US @Bits 13..15 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of + CTEINLINERXMODE2US field.*/ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Min (0x1UL) /*!< Min enumerator value of CTEINLINERXMODE2US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Max (0x6UL) /*!< Max enumerator value of CTEINLINERXMODE2US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (0x1UL) /*!< 4us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (0x2UL) /*!< 2us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (0x3UL) /*!< 1us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (0x4UL) /*!< 0.5us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (0x5UL) /*!< 0.25us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (0x6UL) /*!< 0.125us */ + +/* S0CONF @Bits 16..23 : S0 bit pattern to match */ + #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */ + #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */ + +/* S0MASK @Bits 24..31 : S0 bit mask to set which bit to match */ + #define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */ + #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */ + + +/* RADIO_PACKETPTR: Packet pointer */ + #define RADIO_PACKETPTR_ResetValue (0x00000000UL) /*!< Reset value of PACKETPTR register. */ + +/* PTR @Bits 0..31 : Data pointer */ + #define RADIO_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define RADIO_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ REGULATORS ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =============================================== Struct REGULATORS_VREGMAIN ================================================ */ +/** + * @brief VREGMAIN [REGULATORS_VREGMAIN] Register interface for main voltage regulator. + */ +typedef struct { + __IOM uint32_t DCDCEN; /*!< (@ 0x00000000) Enable DC/DC converter */ + __IM uint32_t INDUCTORDET; /*!< (@ 0x00000004) VREGMAIN inductor detection */ +} NRF_REGULATORS_VREGMAIN_Type; /*!< Size = 8 (0x008) */ + +/* REGULATORS_VREGMAIN_DCDCEN: Enable DC/DC converter */ + #define REGULATORS_VREGMAIN_DCDCEN_ResetValue (0x00000000UL) /*!< Reset value of DCDCEN register. */ + +/* VAL @Bit 0 : Enable DC/DC buck converter */ + #define REGULATORS_VREGMAIN_DCDCEN_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define REGULATORS_VREGMAIN_DCDCEN_VAL_Msk (0x1UL << REGULATORS_VREGMAIN_DCDCEN_VAL_Pos) /*!< Bit mask of VAL field. */ + #define REGULATORS_VREGMAIN_DCDCEN_VAL_Min (0x0UL) /*!< Min enumerator value of VAL field. */ + #define REGULATORS_VREGMAIN_DCDCEN_VAL_Max (0x1UL) /*!< Max enumerator value of VAL field. */ + #define REGULATORS_VREGMAIN_DCDCEN_VAL_Disabled (0x0UL) /*!< Disable DC/DC buck converter */ + #define REGULATORS_VREGMAIN_DCDCEN_VAL_Enabled (0x1UL) /*!< Enable DC/DC converter */ + + +/* REGULATORS_VREGMAIN_INDUCTORDET: VREGMAIN inductor detection */ + #define REGULATORS_VREGMAIN_INDUCTORDET_ResetValue (0x00000000UL) /*!< Reset value of INDUCTORDET register. */ + +/* DETECTED @Bit 0 : (unspecified) */ + #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_Pos (0UL) /*!< Position of DETECTED field. */ + #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_Msk (0x1UL << REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_Pos) /*!< Bit mask of + DETECTED field.*/ + #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_Min (0x0UL) /*!< Min enumerator value of DETECTED field. */ + #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_Max (0x1UL) /*!< Max enumerator value of DETECTED field. */ + #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_InductorNotDetected (0x0UL) /*!< VREGMAIN inductor not detected */ + #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_InductorDetected (0x1UL) /*!< VREGMAIN inductor detected */ + + +/* ==================================================== Struct REGULATORS ==================================================== */ +/** + * @brief Voltage regulators + */ + typedef struct { /*!< REGULATORS Structure */ + __IM uint32_t RESERVED[320]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED1[11]; + __IOM uint32_t POFCON; /*!< (@ 0x00000530) Power-fail comparator configuration */ + __IM uint32_t POFSTAT; /*!< (@ 0x00000534) Power-fail comparator status register */ + __IM uint32_t RESERVED2[50]; + __IOM NRF_REGULATORS_VREGMAIN_Type VREGMAIN; /*!< (@ 0x00000600) Register interface for main voltage regulator. */ + } NRF_REGULATORS_Type; /*!< Size = 1544 (0x608) */ + +/* REGULATORS_SYSTEMOFF: System OFF register */ + #define REGULATORS_SYSTEMOFF_ResetValue (0x00000000UL) /*!< Reset value of SYSTEMOFF register. */ + +/* SYSTEMOFF @Bit 0 : Enable System OFF mode */ + #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ + #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ + #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Min (0x1UL) /*!< Min enumerator value of SYSTEMOFF field. */ + #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Max (0x1UL) /*!< Max enumerator value of SYSTEMOFF field. */ + #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enter (0x1UL) /*!< Enable System OFF mode */ + + +/* REGULATORS_POFCON: Power-fail comparator configuration */ + #define REGULATORS_POFCON_ResetValue (0x00000000UL) /*!< Reset value of POFCON register. */ + +/* POF @Bit 0 : Enable or disable power-fail comparator */ + #define REGULATORS_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ + #define REGULATORS_POFCON_POF_Msk (0x1UL << REGULATORS_POFCON_POF_Pos) /*!< Bit mask of POF field. */ + #define REGULATORS_POFCON_POF_Min (0x0UL) /*!< Min enumerator value of POF field. */ + #define REGULATORS_POFCON_POF_Max (0x1UL) /*!< Max enumerator value of POF field. */ + #define REGULATORS_POFCON_POF_Disabled (0x0UL) /*!< Disable */ + #define REGULATORS_POFCON_POF_Enabled (0x1UL) /*!< Enable */ + +/* THRESHOLD @Bits 1..4 : Power-fail comparator threshold setting */ + #define REGULATORS_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ + #define REGULATORS_POFCON_THRESHOLD_Msk (0xFUL << REGULATORS_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ + #define REGULATORS_POFCON_THRESHOLD_Min (0x0UL) /*!< Min enumerator value of THRESHOLD field. */ + #define REGULATORS_POFCON_THRESHOLD_Max (0xFUL) /*!< Max enumerator value of THRESHOLD field. */ + #define REGULATORS_POFCON_THRESHOLD_V17 (0x0UL) /*!< Set threshold to 1.7 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V18 (0x1UL) /*!< Set threshold to 1.8 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V19 (0x2UL) /*!< Set threshold to 1.9 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V20 (0x3UL) /*!< Set threshold to 2.0 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V21 (0x4UL) /*!< Set threshold to 2.1 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V22 (0x5UL) /*!< Set threshold to 2.2 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V23 (0x6UL) /*!< Set threshold to 2.3 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V24 (0x7UL) /*!< Set threshold to 2.4 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V25 (0x8UL) /*!< Set threshold to 2.5 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V26 (0x9UL) /*!< Set threshold to 2.6 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V27 (0xAUL) /*!< Set threshold to 2.7 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V28 (0xBUL) /*!< Set threshold to 2.8 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V29 (0xCUL) /*!< Set threshold to 2.9 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V30 (0xDUL) /*!< Set threshold to 3.0 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V31 (0xEUL) /*!< Set threshold to 3.1 V for VDD */ + #define REGULATORS_POFCON_THRESHOLD_V32 (0xFUL) /*!< Set threshold to 3.2 V for VDD */ + +/* EVENTDISABLE @Bit 7 : Disable the POFWARN power-fail warning event */ + #define REGULATORS_POFCON_EVENTDISABLE_Pos (7UL) /*!< Position of EVENTDISABLE field. */ + #define REGULATORS_POFCON_EVENTDISABLE_Msk (0x1UL << REGULATORS_POFCON_EVENTDISABLE_Pos) /*!< Bit mask of EVENTDISABLE field.*/ + #define REGULATORS_POFCON_EVENTDISABLE_Min (0x0UL) /*!< Min enumerator value of EVENTDISABLE field. */ + #define REGULATORS_POFCON_EVENTDISABLE_Max (0x1UL) /*!< Max enumerator value of EVENTDISABLE field. */ + #define REGULATORS_POFCON_EVENTDISABLE_Enabled (0x0UL) /*!< POFWARN event is generated */ + #define REGULATORS_POFCON_EVENTDISABLE_Disabled (0x1UL) /*!< POFWARN event is not generated */ + + +/* REGULATORS_POFSTAT: Power-fail comparator status register */ + #define REGULATORS_POFSTAT_ResetValue (0x00000000UL) /*!< Reset value of POFSTAT register. */ + +/* COMPARATOR @Bit 0 : Power-fail comparator status */ + #define REGULATORS_POFSTAT_COMPARATOR_Pos (0UL) /*!< Position of COMPARATOR field. */ + #define REGULATORS_POFSTAT_COMPARATOR_Msk (0x1UL << REGULATORS_POFSTAT_COMPARATOR_Pos) /*!< Bit mask of COMPARATOR field. */ + #define REGULATORS_POFSTAT_COMPARATOR_Min (0x0UL) /*!< Min enumerator value of COMPARATOR field. */ + #define REGULATORS_POFSTAT_COMPARATOR_Max (0x1UL) /*!< Max enumerator value of COMPARATOR field. */ + #define REGULATORS_POFSTAT_COMPARATOR_Above (0x0UL) /*!< Voltage detected above VPOF threshold */ + #define REGULATORS_POFSTAT_COMPARATOR_Below (0x1UL) /*!< Voltage detected below VPOF threshold */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ RESET ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ====================================================== Struct RESET ======================================================= */ +/** + * @brief Reset control + */ + typedef struct { /*!< RESET Structure */ + __IM uint32_t RESERVED[384]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000600) Reset reason */ + } NRF_RESET_Type; /*!< Size = 1540 (0x604) */ + +/* RESET_RESETREAS: Reset reason */ + #define RESET_RESETREAS_ResetValue (0x00000000UL) /*!< Reset value of RESETREAS register. */ + +/* RESETPIN @Bit 0 : Reset from pin reset detected */ + #define RESET_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ + #define RESET_RESETREAS_RESETPIN_Msk (0x1UL << RESET_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ + #define RESET_RESETREAS_RESETPIN_Min (0x0UL) /*!< Min enumerator value of RESETPIN field. */ + #define RESET_RESETREAS_RESETPIN_Max (0x1UL) /*!< Max enumerator value of RESETPIN field. */ + #define RESET_RESETREAS_RESETPIN_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_RESETPIN_Detected (0x1UL) /*!< Detected */ + +/* DOG0 @Bit 1 : Reset from watchdog timer 0 detected */ + #define RESET_RESETREAS_DOG0_Pos (1UL) /*!< Position of DOG0 field. */ + #define RESET_RESETREAS_DOG0_Msk (0x1UL << RESET_RESETREAS_DOG0_Pos) /*!< Bit mask of DOG0 field. */ + #define RESET_RESETREAS_DOG0_Min (0x0UL) /*!< Min enumerator value of DOG0 field. */ + #define RESET_RESETREAS_DOG0_Max (0x1UL) /*!< Max enumerator value of DOG0 field. */ + #define RESET_RESETREAS_DOG0_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_DOG0_Detected (0x1UL) /*!< Detected */ + +/* DOG1 @Bit 2 : Reset from watchdog timer 1 detected */ + #define RESET_RESETREAS_DOG1_Pos (2UL) /*!< Position of DOG1 field. */ + #define RESET_RESETREAS_DOG1_Msk (0x1UL << RESET_RESETREAS_DOG1_Pos) /*!< Bit mask of DOG1 field. */ + #define RESET_RESETREAS_DOG1_Min (0x0UL) /*!< Min enumerator value of DOG1 field. */ + #define RESET_RESETREAS_DOG1_Max (0x1UL) /*!< Max enumerator value of DOG1 field. */ + #define RESET_RESETREAS_DOG1_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_DOG1_Detected (0x1UL) /*!< Detected */ + +/* CTRLAPSOFT @Bit 3 : Soft reset from CTRL-AP detected */ + #define RESET_RESETREAS_CTRLAPSOFT_Pos (3UL) /*!< Position of CTRLAPSOFT field. */ + #define RESET_RESETREAS_CTRLAPSOFT_Msk (0x1UL << RESET_RESETREAS_CTRLAPSOFT_Pos) /*!< Bit mask of CTRLAPSOFT field. */ + #define RESET_RESETREAS_CTRLAPSOFT_Min (0x0UL) /*!< Min enumerator value of CTRLAPSOFT field. */ + #define RESET_RESETREAS_CTRLAPSOFT_Max (0x1UL) /*!< Max enumerator value of CTRLAPSOFT field. */ + #define RESET_RESETREAS_CTRLAPSOFT_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_CTRLAPSOFT_Detected (0x1UL) /*!< Detected */ + +/* CTRLAPHARD @Bit 4 : Reset due to CTRL-AP hard reset */ + #define RESET_RESETREAS_CTRLAPHARD_Pos (4UL) /*!< Position of CTRLAPHARD field. */ + #define RESET_RESETREAS_CTRLAPHARD_Msk (0x1UL << RESET_RESETREAS_CTRLAPHARD_Pos) /*!< Bit mask of CTRLAPHARD field. */ + #define RESET_RESETREAS_CTRLAPHARD_Min (0x0UL) /*!< Min enumerator value of CTRLAPHARD field. */ + #define RESET_RESETREAS_CTRLAPHARD_Max (0x1UL) /*!< Max enumerator value of CTRLAPHARD field. */ + #define RESET_RESETREAS_CTRLAPHARD_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_CTRLAPHARD_Detected (0x1UL) /*!< Detected */ + +/* CTRLAPPIN @Bit 5 : Reset due to CTRL-AP pin reset */ + #define RESET_RESETREAS_CTRLAPPIN_Pos (5UL) /*!< Position of CTRLAPPIN field. */ + #define RESET_RESETREAS_CTRLAPPIN_Msk (0x1UL << RESET_RESETREAS_CTRLAPPIN_Pos) /*!< Bit mask of CTRLAPPIN field. */ + #define RESET_RESETREAS_CTRLAPPIN_Min (0x0UL) /*!< Min enumerator value of CTRLAPPIN field. */ + #define RESET_RESETREAS_CTRLAPPIN_Max (0x1UL) /*!< Max enumerator value of CTRLAPPIN field. */ + #define RESET_RESETREAS_CTRLAPPIN_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_CTRLAPPIN_Detected (0x1UL) /*!< Detected */ + +/* SREQ @Bit 6 : Reset from soft reset detected */ + #define RESET_RESETREAS_SREQ_Pos (6UL) /*!< Position of SREQ field. */ + #define RESET_RESETREAS_SREQ_Msk (0x1UL << RESET_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ + #define RESET_RESETREAS_SREQ_Min (0x0UL) /*!< Min enumerator value of SREQ field. */ + #define RESET_RESETREAS_SREQ_Max (0x1UL) /*!< Max enumerator value of SREQ field. */ + #define RESET_RESETREAS_SREQ_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_SREQ_Detected (0x1UL) /*!< Detected */ + +/* LOCKUP @Bit 7 : Reset from CPU lockup detected */ + #define RESET_RESETREAS_LOCKUP_Pos (7UL) /*!< Position of LOCKUP field. */ + #define RESET_RESETREAS_LOCKUP_Msk (0x1UL << RESET_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ + #define RESET_RESETREAS_LOCKUP_Min (0x0UL) /*!< Min enumerator value of LOCKUP field. */ + #define RESET_RESETREAS_LOCKUP_Max (0x1UL) /*!< Max enumerator value of LOCKUP field. */ + #define RESET_RESETREAS_LOCKUP_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_LOCKUP_Detected (0x1UL) /*!< Detected */ + +/* OFF @Bit 8 : Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO */ + #define RESET_RESETREAS_OFF_Pos (8UL) /*!< Position of OFF field. */ + #define RESET_RESETREAS_OFF_Msk (0x1UL << RESET_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ + #define RESET_RESETREAS_OFF_Min (0x0UL) /*!< Min enumerator value of OFF field. */ + #define RESET_RESETREAS_OFF_Max (0x1UL) /*!< Max enumerator value of OFF field. */ + #define RESET_RESETREAS_OFF_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_OFF_Detected (0x1UL) /*!< Detected */ + +/* LPCOMP @Bit 9 : Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP */ + #define RESET_RESETREAS_LPCOMP_Pos (9UL) /*!< Position of LPCOMP field. */ + #define RESET_RESETREAS_LPCOMP_Msk (0x1UL << RESET_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ + #define RESET_RESETREAS_LPCOMP_Min (0x0UL) /*!< Min enumerator value of LPCOMP field. */ + #define RESET_RESETREAS_LPCOMP_Max (0x1UL) /*!< Max enumerator value of LPCOMP field. */ + #define RESET_RESETREAS_LPCOMP_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_LPCOMP_Detected (0x1UL) /*!< Detected */ + +/* DIF @Bit 10 : Reset triggered by Debug Interface */ + #define RESET_RESETREAS_DIF_Pos (10UL) /*!< Position of DIF field. */ + #define RESET_RESETREAS_DIF_Msk (0x1UL << RESET_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ + #define RESET_RESETREAS_DIF_Min (0x0UL) /*!< Min enumerator value of DIF field. */ + #define RESET_RESETREAS_DIF_Max (0x1UL) /*!< Max enumerator value of DIF field. */ + #define RESET_RESETREAS_DIF_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_DIF_Detected (0x1UL) /*!< Detected */ + +/* GRTC @Bit 11 : Reset due to wakeup from GRTC */ + #define RESET_RESETREAS_GRTC_Pos (11UL) /*!< Position of GRTC field. */ + #define RESET_RESETREAS_GRTC_Msk (0x1UL << RESET_RESETREAS_GRTC_Pos) /*!< Bit mask of GRTC field. */ + #define RESET_RESETREAS_GRTC_Min (0x0UL) /*!< Min enumerator value of GRTC field. */ + #define RESET_RESETREAS_GRTC_Max (0x1UL) /*!< Max enumerator value of GRTC field. */ + #define RESET_RESETREAS_GRTC_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_GRTC_Detected (0x1UL) /*!< Detected */ + +/* NFC @Bit 12 : Reset after wakeup from System OFF mode due to NFC field being detected */ + #define RESET_RESETREAS_NFC_Pos (12UL) /*!< Position of NFC field. */ + #define RESET_RESETREAS_NFC_Msk (0x1UL << RESET_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */ + #define RESET_RESETREAS_NFC_Min (0x0UL) /*!< Min enumerator value of NFC field. */ + #define RESET_RESETREAS_NFC_Max (0x1UL) /*!< Max enumerator value of NFC field. */ + #define RESET_RESETREAS_NFC_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_NFC_Detected (0x1UL) /*!< Detected */ + +/* SECTAMPER @Bit 13 : Reset due to illegal tampering of the device */ + #define RESET_RESETREAS_SECTAMPER_Pos (13UL) /*!< Position of SECTAMPER field. */ + #define RESET_RESETREAS_SECTAMPER_Msk (0x1UL << RESET_RESETREAS_SECTAMPER_Pos) /*!< Bit mask of SECTAMPER field. */ + #define RESET_RESETREAS_SECTAMPER_Min (0x0UL) /*!< Min enumerator value of SECTAMPER field. */ + #define RESET_RESETREAS_SECTAMPER_Max (0x1UL) /*!< Max enumerator value of SECTAMPER field. */ + #define RESET_RESETREAS_SECTAMPER_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_SECTAMPER_Detected (0x1UL) /*!< Detected */ + +/* VBUS @Bit 14 : Reset after wakeup from System OFF mode due to VBUS rising into valid range */ + #define RESET_RESETREAS_VBUS_Pos (14UL) /*!< Position of VBUS field. */ + #define RESET_RESETREAS_VBUS_Msk (0x1UL << RESET_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */ + #define RESET_RESETREAS_VBUS_Min (0x0UL) /*!< Min enumerator value of VBUS field. */ + #define RESET_RESETREAS_VBUS_Max (0x1UL) /*!< Max enumerator value of VBUS field. */ + #define RESET_RESETREAS_VBUS_NotDetected (0x0UL) /*!< Not detected */ + #define RESET_RESETREAS_VBUS_Detected (0x1UL) /*!< Detected */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ RRAMC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================= Struct RRAMC_BUFSTATUS ================================================== */ +/** + * @brief BUFSTATUS [RRAMC_BUFSTATUS] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IM uint32_t WRITEBUFEMPTY; /*!< (@ 0x00000008) Internal write-buffer is empty */ +} NRF_RRAMC_BUFSTATUS_Type; /*!< Size = 12 (0x00C) */ + +/* RRAMC_BUFSTATUS_WRITEBUFEMPTY: Internal write-buffer is empty */ + #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_ResetValue (0x00000000UL) /*!< Reset value of WRITEBUFEMPTY register. */ + +/* EMPTY @Bit 0 : (unspecified) */ + #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Pos (0UL) /*!< Position of EMPTY field. */ + #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Msk (0x1UL << RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Pos) /*!< Bit mask of EMPTY + field.*/ + #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Min (0x0UL) /*!< Min enumerator value of EMPTY field. */ + #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Max (0x1UL) /*!< Max enumerator value of EMPTY field. */ + #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_NotEmpty (0x0UL) /*!< The internal write-buffer has data that needs committing */ + #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Empty (0x1UL) /*!< The internal write-buffer is empty and has no content that + needs to be committed*/ + + + +/* ==================================================== Struct RRAMC_ECC ===================================================== */ +/** + * @brief ECC [RRAMC_ECC] (unspecified) + */ +typedef struct { + __IM uint32_t ERRORADDR; /*!< (@ 0x00000000) Address of the first ECC error that could not be + corrected*/ +} NRF_RRAMC_ECC_Type; /*!< Size = 4 (0x004) */ + +/* RRAMC_ECC_ERRORADDR: Address of the first ECC error that could not be corrected */ + #define RRAMC_ECC_ERRORADDR_ResetValue (0x00FFFFFFUL) /*!< Reset value of ERRORADDR register. */ + +/* ADDRESS @Bits 0..31 : ECC error address */ + #define RRAMC_ECC_ERRORADDR_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define RRAMC_ECC_ERRORADDR_ADDRESS_Msk (0xFFFFFFFFUL << RRAMC_ECC_ERRORADDR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + + +/* =================================================== Struct RRAMC_POWER ==================================================== */ +/** + * @brief POWER [RRAMC_POWER] (unspecified) + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Power configuration */ + __IM uint32_t RESERVED; + __IOM uint32_t LOWPOWERCONFIG; /*!< (@ 0x00000008) Low power mode configuration */ +} NRF_RRAMC_POWER_Type; /*!< Size = 12 (0x00C) */ + +/* RRAMC_POWER_CONFIG: Power configuration */ + #define RRAMC_POWER_CONFIG_ResetValue (0x00000100UL) /*!< Reset value of CONFIG register. */ + +/* ACCESSTIMEOUT @Bits 0..15 : Access timeout, in 31.25 ns units, used for going into standby power mode or remain active on + wake up */ + + #define RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Pos (0UL) /*!< Position of ACCESSTIMEOUT field. */ + #define RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Msk (0xFFFFUL << RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Pos) /*!< Bit mask of ACCESSTIMEOUT + field.*/ + +/* POF @Bit 16 : Power on failure warning handling configuration */ + #define RRAMC_POWER_CONFIG_POF_Pos (16UL) /*!< Position of POF field. */ + #define RRAMC_POWER_CONFIG_POF_Msk (0x1UL << RRAMC_POWER_CONFIG_POF_Pos) /*!< Bit mask of POF field. */ + #define RRAMC_POWER_CONFIG_POF_Min (0x0UL) /*!< Min enumerator value of POF field. */ + #define RRAMC_POWER_CONFIG_POF_Max (0x1UL) /*!< Max enumerator value of POF field. */ + #define RRAMC_POWER_CONFIG_POF_Wait (0x0UL) /*!< Wait until the current RRAM write finishes */ + #define RRAMC_POWER_CONFIG_POF_Abort (0x1UL) /*!< Abort the current RRAM write */ + + +/* RRAMC_POWER_LOWPOWERCONFIG: Low power mode configuration */ + #define RRAMC_POWER_LOWPOWERCONFIG_ResetValue (0x00000000UL) /*!< Reset value of LOWPOWERCONFIG register. */ + +/* MODE @Bits 0..1 : RRAM low power mode */ + #define RRAMC_POWER_LOWPOWERCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define RRAMC_POWER_LOWPOWERCONFIG_MODE_Msk (0x3UL << RRAMC_POWER_LOWPOWERCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ + #define RRAMC_POWER_LOWPOWERCONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define RRAMC_POWER_LOWPOWERCONFIG_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define RRAMC_POWER_LOWPOWERCONFIG_MODE_PowerOff (0x0UL) /*!< The RRAM is powered Off */ + #define RRAMC_POWER_LOWPOWERCONFIG_MODE_Standby (0x1UL) /*!< The RRAM automatically goes into standby mode while the RRAM is + not being accessed*/ + + + +/* =================================================== Struct RRAMC_ERASE ==================================================== */ +/** + * @brief ERASE [RRAMC_ERASE] (unspecified) + */ +typedef struct { + __IOM uint32_t ERASEALL; /*!< (@ 0x00000000) Erase RRAM, including UICR All information in SICR, + including keys, are also erased*/ +} NRF_RRAMC_ERASE_Type; /*!< Size = 4 (0x004) */ + +/* RRAMC_ERASE_ERASEALL: Erase RRAM, including UICR All information in SICR, including keys, are also erased */ + #define RRAMC_ERASE_ERASEALL_ResetValue (0x00000000UL) /*!< Reset value of ERASEALL register. */ + +/* ERASE @Bit 0 : Erase RRAM */ + #define RRAMC_ERASE_ERASEALL_ERASE_Pos (0UL) /*!< Position of ERASE field. */ + #define RRAMC_ERASE_ERASEALL_ERASE_Msk (0x1UL << RRAMC_ERASE_ERASEALL_ERASE_Pos) /*!< Bit mask of ERASE field. */ + #define RRAMC_ERASE_ERASEALL_ERASE_Min (0x0UL) /*!< Min enumerator value of ERASE field. */ + #define RRAMC_ERASE_ERASEALL_ERASE_Max (0x1UL) /*!< Max enumerator value of ERASE field. */ + #define RRAMC_ERASE_ERASEALL_ERASE_NoOperation (0x0UL) /*!< No operation */ + #define RRAMC_ERASE_ERASEALL_ERASE_Erase (0x1UL) /*!< Start erase of chip */ + + + +/* =================================================== Struct RRAMC_REGION =================================================== */ +/** + * @brief REGION [RRAMC_REGION] RRAMC can apply access privileges to regions of the RRAM. Some regions are dedicated for system + use and are not available for configuration - refer to the instantiation table for details. + + */ +typedef struct { + __IOM uint32_t ADDRESS; /*!< (@ 0x00000000) Region address */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000004) Region configuration */ +} NRF_RRAMC_REGION_Type; /*!< Size = 8 (0x008) */ + #define RRAMC_REGION_MaxCount (6UL) /*!< Size of REGION[6] array. */ + #define RRAMC_REGION_MaxIndex (5UL) /*!< Max index of REGION[6] array. */ + #define RRAMC_REGION_MinIndex (0UL) /*!< Min index of REGION[6] array. */ + +/* RRAMC_REGION_ADDRESS: Region address */ + #define RRAMC_REGION_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* STARTADDR @Bits 0..31 : Start address of the region [n] */ + #define RRAMC_REGION_ADDRESS_STARTADDR_Pos (0UL) /*!< Position of STARTADDR field. */ + #define RRAMC_REGION_ADDRESS_STARTADDR_Msk (0xFFFFFFFFUL << RRAMC_REGION_ADDRESS_STARTADDR_Pos) /*!< Bit mask of STARTADDR + field.*/ + + +/* RRAMC_REGION_CONFIG: Region configuration */ + #define RRAMC_REGION_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* READ @Bit 0 : Read access */ + #define RRAMC_REGION_CONFIG_READ_Pos (0UL) /*!< Position of READ field. */ + #define RRAMC_REGION_CONFIG_READ_Msk (0x1UL << RRAMC_REGION_CONFIG_READ_Pos) /*!< Bit mask of READ field. */ + #define RRAMC_REGION_CONFIG_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define RRAMC_REGION_CONFIG_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define RRAMC_REGION_CONFIG_READ_NotAllowed (0x0UL) /*!< Read access to override region [n] is not allowed */ + #define RRAMC_REGION_CONFIG_READ_Allowed (0x1UL) /*!< Read access to override region [n] is allowed */ + +/* WRITE @Bit 1 : Write access */ + #define RRAMC_REGION_CONFIG_WRITE_Pos (1UL) /*!< Position of WRITE field. */ + #define RRAMC_REGION_CONFIG_WRITE_Msk (0x1UL << RRAMC_REGION_CONFIG_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define RRAMC_REGION_CONFIG_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define RRAMC_REGION_CONFIG_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define RRAMC_REGION_CONFIG_WRITE_NotAllowed (0x0UL) /*!< Write access to override region [n] is not allowed */ + #define RRAMC_REGION_CONFIG_WRITE_Allowed (0x1UL) /*!< Write access to override region [n] is allowed */ + +/* EXECUTE @Bit 2 : Execute access */ + #define RRAMC_REGION_CONFIG_EXECUTE_Pos (2UL) /*!< Position of EXECUTE field. */ + #define RRAMC_REGION_CONFIG_EXECUTE_Msk (0x1UL << RRAMC_REGION_CONFIG_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ + #define RRAMC_REGION_CONFIG_EXECUTE_Min (0x0UL) /*!< Min enumerator value of EXECUTE field. */ + #define RRAMC_REGION_CONFIG_EXECUTE_Max (0x1UL) /*!< Max enumerator value of EXECUTE field. */ + #define RRAMC_REGION_CONFIG_EXECUTE_NotAllowed (0x0UL) /*!< Execute access to override region [n] is not allowed */ + #define RRAMC_REGION_CONFIG_EXECUTE_Allowed (0x1UL) /*!< Execute access to override region [n] is allowed */ + +/* SECURE @Bit 3 : Secure access */ + #define RRAMC_REGION_CONFIG_SECURE_Pos (3UL) /*!< Position of SECURE field. */ + #define RRAMC_REGION_CONFIG_SECURE_Msk (0x1UL << RRAMC_REGION_CONFIG_SECURE_Pos) /*!< Bit mask of SECURE field. */ + #define RRAMC_REGION_CONFIG_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field. */ + #define RRAMC_REGION_CONFIG_SECURE_Max (0x1UL) /*!< Max enumerator value of SECURE field. */ + #define RRAMC_REGION_CONFIG_SECURE_NonSecure (0x0UL) /*!< Both Secure and non-Secure access to override region [n] is allowed*/ + #define RRAMC_REGION_CONFIG_SECURE_Secure (0x1UL) /*!< Only secure access to override region [n] is allowed */ + +/* OWNER @Bits 4..7 : Owner ID */ + #define RRAMC_REGION_CONFIG_OWNER_Pos (4UL) /*!< Position of OWNER field. */ + #define RRAMC_REGION_CONFIG_OWNER_Msk (0xFUL << RRAMC_REGION_CONFIG_OWNER_Pos) /*!< Bit mask of OWNER field. */ + #define RRAMC_REGION_CONFIG_OWNER_Min (0x0UL) /*!< Min enumerator value of OWNER field. */ + #define RRAMC_REGION_CONFIG_OWNER_Max (0x0UL) /*!< Max enumerator value of OWNER field. */ + #define RRAMC_REGION_CONFIG_OWNER_NotEnforced (0x0UL) /*!< Owner ID protection is not enforced */ + +/* WRITEONCE @Bit 12 : Write-once */ + #define RRAMC_REGION_CONFIG_WRITEONCE_Pos (12UL) /*!< Position of WRITEONCE field. */ + #define RRAMC_REGION_CONFIG_WRITEONCE_Msk (0x1UL << RRAMC_REGION_CONFIG_WRITEONCE_Pos) /*!< Bit mask of WRITEONCE field. */ + #define RRAMC_REGION_CONFIG_WRITEONCE_Min (0x0UL) /*!< Min enumerator value of WRITEONCE field. */ + #define RRAMC_REGION_CONFIG_WRITEONCE_Max (0x1UL) /*!< Max enumerator value of WRITEONCE field. */ + #define RRAMC_REGION_CONFIG_WRITEONCE_Disabled (0x0UL) /*!< Write-once disabled */ + #define RRAMC_REGION_CONFIG_WRITEONCE_Enabled (0x1UL) /*!< Write-once enabled */ + +/* LOCK @Bit 13 : Enable lock */ + #define RRAMC_REGION_CONFIG_LOCK_Pos (13UL) /*!< Position of LOCK field. */ + #define RRAMC_REGION_CONFIG_LOCK_Msk (0x1UL << RRAMC_REGION_CONFIG_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define RRAMC_REGION_CONFIG_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define RRAMC_REGION_CONFIG_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define RRAMC_REGION_CONFIG_LOCK_Disabled (0x0UL) /*!< Lock disabled for region [n] */ + #define RRAMC_REGION_CONFIG_LOCK_Enabled (0x1UL) /*!< Lock enabled for region [n] */ + +/* SIZE @Bits 16..22 : Size in KBytes of region [n] */ + #define RRAMC_REGION_CONFIG_SIZE_Pos (16UL) /*!< Position of SIZE field. */ + #define RRAMC_REGION_CONFIG_SIZE_Msk (0x7FUL << RRAMC_REGION_CONFIG_SIZE_Pos) /*!< Bit mask of SIZE field. */ + + +/* ====================================================== Struct RRAMC ======================================================= */ +/** + * @brief RRAM controller GLITCH detector + */ + typedef struct { /*!< RRAMC Structure */ + __OM uint32_t TASKS_WAKEUP; /*!< (@ 0x00000000) Wakeup the RRAM from low power mode */ + __OM uint32_t TASKS_CLRWRITEBUF; /*!< (@ 0x00000004) Clear internal write-buffer */ + __OM uint32_t TASKS_COMMITWRITEBUF; /*!< (@ 0x00000008) Commits the data stored in internal write-buffer to + RRAM*/ + __IM uint32_t RESERVED[29]; + __IOM uint32_t SUBSCRIBE_WAKEUP; /*!< (@ 0x00000080) Subscribe configuration for task WAKEUP */ + __IOM uint32_t SUBSCRIBE_CLRWRITEBUF; /*!< (@ 0x00000084) Subscribe configuration for task CLRWRITEBUF */ + __IOM uint32_t SUBSCRIBE_COMMITWRITEBUF; /*!< (@ 0x00000088) Subscribe configuration for task COMMITWRITEBUF */ + __IM uint32_t RESERVED1[29]; + __IOM uint32_t EVENTS_WOKENUP; /*!< (@ 0x00000100) RRAMC is woken up from low power mode */ + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000104) RRAMC is ready */ + __IOM uint32_t EVENTS_READYNEXT; /*!< (@ 0x00000108) Ready to accept a new write operation */ + __IOM uint32_t EVENTS_ACCESSERROR; /*!< (@ 0x0000010C) RRAM access error */ + __IM uint32_t RESERVED2[28]; + __IOM uint32_t PUBLISH_WOKENUP; /*!< (@ 0x00000180) Publish configuration for event WOKENUP */ + __IM uint32_t RESERVED3[95]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED4[60]; + __IM uint32_t READY; /*!< (@ 0x00000400) RRAMC ready status */ + __IM uint32_t READYNEXT; /*!< (@ 0x00000404) Ready next flag */ + __IM uint32_t ACCESSERRORADDR; /*!< (@ 0x00000408) Address of the first access error */ + __IM uint32_t RESERVED5; + __IOM NRF_RRAMC_BUFSTATUS_Type BUFSTATUS; /*!< (@ 0x00000410) (unspecified) */ + __IM uint32_t RESERVED6; + __IOM NRF_RRAMC_ECC_Type ECC; /*!< (@ 0x00000420) (unspecified) */ + __IM uint32_t RESERVED7[55]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000500) Configuration register */ + __IM uint32_t RESERVED8[2]; + __IOM uint32_t READYNEXTTIMEOUT; /*!< (@ 0x0000050C) Configuration for ready next timeout counter, in units + of AXI clock frequency*/ + __IOM NRF_RRAMC_POWER_Type POWER; /*!< (@ 0x00000510) (unspecified) */ + __IM uint32_t RESERVED9[9]; + __IOM NRF_RRAMC_ERASE_Type ERASE; /*!< (@ 0x00000540) (unspecified) */ + __IM uint32_t RESERVED10[3]; + __IOM NRF_RRAMC_REGION_Type REGION[6]; /*!< (@ 0x00000550) RRAMC can apply access privileges to regions of the + RRAM. Some regions are dedicated for system use and are + not available for configuration - refer to the + instantiation table for details.*/ + } NRF_RRAMC_Type; /*!< Size = 1408 (0x580) */ + +/* RRAMC_TASKS_WAKEUP: Wakeup the RRAM from low power mode */ + #define RRAMC_TASKS_WAKEUP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_WAKEUP register. */ + +/* TASKS_WAKEUP @Bit 0 : Wakeup the RRAM from low power mode */ + #define RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Pos (0UL) /*!< Position of TASKS_WAKEUP field. */ + #define RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Msk (0x1UL << RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Pos) /*!< Bit mask of TASKS_WAKEUP + field.*/ + #define RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Min (0x1UL) /*!< Min enumerator value of TASKS_WAKEUP field. */ + #define RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Max (0x1UL) /*!< Max enumerator value of TASKS_WAKEUP field. */ + #define RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RRAMC_TASKS_CLRWRITEBUF: Clear internal write-buffer */ + #define RRAMC_TASKS_CLRWRITEBUF_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLRWRITEBUF register. */ + +/* TASKS_CLRWRITEBUF @Bit 0 : Clear internal write-buffer */ + #define RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Pos (0UL) /*!< Position of TASKS_CLRWRITEBUF field. */ + #define RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Msk (0x1UL << RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Pos) /*!< Bit mask + of TASKS_CLRWRITEBUF field.*/ + #define RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Min (0x1UL) /*!< Min enumerator value of TASKS_CLRWRITEBUF field. */ + #define RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Max (0x1UL) /*!< Max enumerator value of TASKS_CLRWRITEBUF field. */ + #define RRAMC_TASKS_CLRWRITEBUF_TASKS_CLRWRITEBUF_Trigger (0x1UL) /*!< Trigger task */ + + +/* RRAMC_TASKS_COMMITWRITEBUF: Commits the data stored in internal write-buffer to RRAM */ + #define RRAMC_TASKS_COMMITWRITEBUF_ResetValue (0x00000000UL) /*!< Reset value of TASKS_COMMITWRITEBUF register. */ + +/* TASKS_COMMITWRITEBUF @Bit 0 : Commits the data stored in internal write-buffer to RRAM */ + #define RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Pos (0UL) /*!< Position of TASKS_COMMITWRITEBUF field. */ + #define RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Msk (0x1UL << RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Pos) + /*!< Bit mask of TASKS_COMMITWRITEBUF field.*/ + #define RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Min (0x1UL) /*!< Min enumerator value of TASKS_COMMITWRITEBUF field. */ + #define RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Max (0x1UL) /*!< Max enumerator value of TASKS_COMMITWRITEBUF field. */ + #define RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Trigger (0x1UL) /*!< Trigger task */ + + +/* RRAMC_SUBSCRIBE_WAKEUP: Subscribe configuration for task WAKEUP */ + #define RRAMC_SUBSCRIBE_WAKEUP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_WAKEUP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task WAKEUP will subscribe to */ + #define RRAMC_SUBSCRIBE_WAKEUP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RRAMC_SUBSCRIBE_WAKEUP_CHIDX_Msk (0xFFUL << RRAMC_SUBSCRIBE_WAKEUP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RRAMC_SUBSCRIBE_WAKEUP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RRAMC_SUBSCRIBE_WAKEUP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RRAMC_SUBSCRIBE_WAKEUP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RRAMC_SUBSCRIBE_WAKEUP_EN_Msk (0x1UL << RRAMC_SUBSCRIBE_WAKEUP_EN_Pos) /*!< Bit mask of EN field. */ + #define RRAMC_SUBSCRIBE_WAKEUP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RRAMC_SUBSCRIBE_WAKEUP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RRAMC_SUBSCRIBE_WAKEUP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RRAMC_SUBSCRIBE_WAKEUP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RRAMC_SUBSCRIBE_CLRWRITEBUF: Subscribe configuration for task CLRWRITEBUF */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLRWRITEBUF register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CLRWRITEBUF will subscribe to */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_CHIDX_Msk (0xFFUL << RRAMC_SUBSCRIBE_CLRWRITEBUF_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Pos (31UL) /*!< Position of EN field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Msk (0x1UL << RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Pos) /*!< Bit mask of EN field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RRAMC_SUBSCRIBE_CLRWRITEBUF_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RRAMC_SUBSCRIBE_COMMITWRITEBUF: Subscribe configuration for task COMMITWRITEBUF */ + #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_COMMITWRITEBUF register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task COMMITWRITEBUF will subscribe to */ + #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_CHIDX_Msk (0xFFUL << RRAMC_SUBSCRIBE_COMMITWRITEBUF_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Pos (31UL) /*!< Position of EN field. */ + #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Msk (0x1UL << RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Pos) /*!< Bit mask of EN field. */ + #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RRAMC_EVENTS_WOKENUP: RRAMC is woken up from low power mode */ + #define RRAMC_EVENTS_WOKENUP_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_WOKENUP register. */ + +/* EVENTS_WOKENUP @Bit 0 : RRAMC is woken up from low power mode */ + #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Pos (0UL) /*!< Position of EVENTS_WOKENUP field. */ + #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Msk (0x1UL << RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Pos) /*!< Bit mask of + EVENTS_WOKENUP field.*/ + #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Min (0x0UL) /*!< Min enumerator value of EVENTS_WOKENUP field. */ + #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Max (0x1UL) /*!< Max enumerator value of EVENTS_WOKENUP field. */ + #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_NotGenerated (0x0UL) /*!< Event not generated */ + #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Generated (0x1UL) /*!< Event generated */ + + +/* RRAMC_EVENTS_READY: RRAMC is ready */ + #define RRAMC_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register. */ + +/* EVENTS_READY @Bit 0 : RRAMC is ready */ + #define RRAMC_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ + #define RRAMC_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RRAMC_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY + field.*/ + #define RRAMC_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field. */ + #define RRAMC_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field. */ + #define RRAMC_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define RRAMC_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */ + + +/* RRAMC_EVENTS_READYNEXT: Ready to accept a new write operation */ + #define RRAMC_EVENTS_READYNEXT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READYNEXT register. */ + +/* EVENTS_READYNEXT @Bit 0 : Ready to accept a new write operation */ + #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Pos (0UL) /*!< Position of EVENTS_READYNEXT field. */ + #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Msk (0x1UL << RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Pos) /*!< Bit mask of + EVENTS_READYNEXT field.*/ + #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Min (0x0UL) /*!< Min enumerator value of EVENTS_READYNEXT field. */ + #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Max (0x1UL) /*!< Max enumerator value of EVENTS_READYNEXT field. */ + #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_NotGenerated (0x0UL) /*!< Event not generated */ + #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Generated (0x1UL) /*!< Event generated */ + + +/* RRAMC_EVENTS_ACCESSERROR: RRAM access error */ + #define RRAMC_EVENTS_ACCESSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ACCESSERROR register. */ + +/* EVENTS_ACCESSERROR @Bit 0 : RRAM access error */ + #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Pos (0UL) /*!< Position of EVENTS_ACCESSERROR field. */ + #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Msk (0x1UL << RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Pos) /*!< Bit + mask of EVENTS_ACCESSERROR field.*/ + #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ACCESSERROR field. */ + #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ACCESSERROR field. */ + #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* RRAMC_PUBLISH_WOKENUP: Publish configuration for event WOKENUP */ + #define RRAMC_PUBLISH_WOKENUP_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_WOKENUP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event WOKENUP will publish to */ + #define RRAMC_PUBLISH_WOKENUP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RRAMC_PUBLISH_WOKENUP_CHIDX_Msk (0xFFUL << RRAMC_PUBLISH_WOKENUP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RRAMC_PUBLISH_WOKENUP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RRAMC_PUBLISH_WOKENUP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RRAMC_PUBLISH_WOKENUP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RRAMC_PUBLISH_WOKENUP_EN_Msk (0x1UL << RRAMC_PUBLISH_WOKENUP_EN_Pos) /*!< Bit mask of EN field. */ + #define RRAMC_PUBLISH_WOKENUP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RRAMC_PUBLISH_WOKENUP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RRAMC_PUBLISH_WOKENUP_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RRAMC_PUBLISH_WOKENUP_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RRAMC_INTEN: Enable or disable interrupt */ + #define RRAMC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* WOKENUP @Bit 0 : Enable or disable interrupt for event WOKENUP */ + #define RRAMC_INTEN_WOKENUP_Pos (0UL) /*!< Position of WOKENUP field. */ + #define RRAMC_INTEN_WOKENUP_Msk (0x1UL << RRAMC_INTEN_WOKENUP_Pos) /*!< Bit mask of WOKENUP field. */ + #define RRAMC_INTEN_WOKENUP_Min (0x0UL) /*!< Min enumerator value of WOKENUP field. */ + #define RRAMC_INTEN_WOKENUP_Max (0x1UL) /*!< Max enumerator value of WOKENUP field. */ + #define RRAMC_INTEN_WOKENUP_Disabled (0x0UL) /*!< Disable */ + #define RRAMC_INTEN_WOKENUP_Enabled (0x1UL) /*!< Enable */ + +/* READY @Bit 1 : Enable or disable interrupt for event READY */ + #define RRAMC_INTEN_READY_Pos (1UL) /*!< Position of READY field. */ + #define RRAMC_INTEN_READY_Msk (0x1UL << RRAMC_INTEN_READY_Pos) /*!< Bit mask of READY field. */ + #define RRAMC_INTEN_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RRAMC_INTEN_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RRAMC_INTEN_READY_Disabled (0x0UL) /*!< Disable */ + #define RRAMC_INTEN_READY_Enabled (0x1UL) /*!< Enable */ + +/* READYNEXT @Bit 2 : Enable or disable interrupt for event READYNEXT */ + #define RRAMC_INTEN_READYNEXT_Pos (2UL) /*!< Position of READYNEXT field. */ + #define RRAMC_INTEN_READYNEXT_Msk (0x1UL << RRAMC_INTEN_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ + #define RRAMC_INTEN_READYNEXT_Min (0x0UL) /*!< Min enumerator value of READYNEXT field. */ + #define RRAMC_INTEN_READYNEXT_Max (0x1UL) /*!< Max enumerator value of READYNEXT field. */ + #define RRAMC_INTEN_READYNEXT_Disabled (0x0UL) /*!< Disable */ + #define RRAMC_INTEN_READYNEXT_Enabled (0x1UL) /*!< Enable */ + +/* ACCESSERROR @Bit 3 : Enable or disable interrupt for event ACCESSERROR */ + #define RRAMC_INTEN_ACCESSERROR_Pos (3UL) /*!< Position of ACCESSERROR field. */ + #define RRAMC_INTEN_ACCESSERROR_Msk (0x1UL << RRAMC_INTEN_ACCESSERROR_Pos) /*!< Bit mask of ACCESSERROR field. */ + #define RRAMC_INTEN_ACCESSERROR_Min (0x0UL) /*!< Min enumerator value of ACCESSERROR field. */ + #define RRAMC_INTEN_ACCESSERROR_Max (0x1UL) /*!< Max enumerator value of ACCESSERROR field. */ + #define RRAMC_INTEN_ACCESSERROR_Disabled (0x0UL) /*!< Disable */ + #define RRAMC_INTEN_ACCESSERROR_Enabled (0x1UL) /*!< Enable */ + + +/* RRAMC_INTENSET: Enable interrupt */ + #define RRAMC_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* WOKENUP @Bit 0 : Write '1' to enable interrupt for event WOKENUP */ + #define RRAMC_INTENSET_WOKENUP_Pos (0UL) /*!< Position of WOKENUP field. */ + #define RRAMC_INTENSET_WOKENUP_Msk (0x1UL << RRAMC_INTENSET_WOKENUP_Pos) /*!< Bit mask of WOKENUP field. */ + #define RRAMC_INTENSET_WOKENUP_Min (0x0UL) /*!< Min enumerator value of WOKENUP field. */ + #define RRAMC_INTENSET_WOKENUP_Max (0x1UL) /*!< Max enumerator value of WOKENUP field. */ + #define RRAMC_INTENSET_WOKENUP_Set (0x1UL) /*!< Enable */ + #define RRAMC_INTENSET_WOKENUP_Disabled (0x0UL) /*!< Read: Disabled */ + #define RRAMC_INTENSET_WOKENUP_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY @Bit 1 : Write '1' to enable interrupt for event READY */ + #define RRAMC_INTENSET_READY_Pos (1UL) /*!< Position of READY field. */ + #define RRAMC_INTENSET_READY_Msk (0x1UL << RRAMC_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ + #define RRAMC_INTENSET_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RRAMC_INTENSET_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RRAMC_INTENSET_READY_Set (0x1UL) /*!< Enable */ + #define RRAMC_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RRAMC_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READYNEXT @Bit 2 : Write '1' to enable interrupt for event READYNEXT */ + #define RRAMC_INTENSET_READYNEXT_Pos (2UL) /*!< Position of READYNEXT field. */ + #define RRAMC_INTENSET_READYNEXT_Msk (0x1UL << RRAMC_INTENSET_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ + #define RRAMC_INTENSET_READYNEXT_Min (0x0UL) /*!< Min enumerator value of READYNEXT field. */ + #define RRAMC_INTENSET_READYNEXT_Max (0x1UL) /*!< Max enumerator value of READYNEXT field. */ + #define RRAMC_INTENSET_READYNEXT_Set (0x1UL) /*!< Enable */ + #define RRAMC_INTENSET_READYNEXT_Disabled (0x0UL) /*!< Read: Disabled */ + #define RRAMC_INTENSET_READYNEXT_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ACCESSERROR @Bit 3 : Write '1' to enable interrupt for event ACCESSERROR */ + #define RRAMC_INTENSET_ACCESSERROR_Pos (3UL) /*!< Position of ACCESSERROR field. */ + #define RRAMC_INTENSET_ACCESSERROR_Msk (0x1UL << RRAMC_INTENSET_ACCESSERROR_Pos) /*!< Bit mask of ACCESSERROR field. */ + #define RRAMC_INTENSET_ACCESSERROR_Min (0x0UL) /*!< Min enumerator value of ACCESSERROR field. */ + #define RRAMC_INTENSET_ACCESSERROR_Max (0x1UL) /*!< Max enumerator value of ACCESSERROR field. */ + #define RRAMC_INTENSET_ACCESSERROR_Set (0x1UL) /*!< Enable */ + #define RRAMC_INTENSET_ACCESSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define RRAMC_INTENSET_ACCESSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RRAMC_INTENCLR: Disable interrupt */ + #define RRAMC_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* WOKENUP @Bit 0 : Write '1' to disable interrupt for event WOKENUP */ + #define RRAMC_INTENCLR_WOKENUP_Pos (0UL) /*!< Position of WOKENUP field. */ + #define RRAMC_INTENCLR_WOKENUP_Msk (0x1UL << RRAMC_INTENCLR_WOKENUP_Pos) /*!< Bit mask of WOKENUP field. */ + #define RRAMC_INTENCLR_WOKENUP_Min (0x0UL) /*!< Min enumerator value of WOKENUP field. */ + #define RRAMC_INTENCLR_WOKENUP_Max (0x1UL) /*!< Max enumerator value of WOKENUP field. */ + #define RRAMC_INTENCLR_WOKENUP_Clear (0x1UL) /*!< Disable */ + #define RRAMC_INTENCLR_WOKENUP_Disabled (0x0UL) /*!< Read: Disabled */ + #define RRAMC_INTENCLR_WOKENUP_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY @Bit 1 : Write '1' to disable interrupt for event READY */ + #define RRAMC_INTENCLR_READY_Pos (1UL) /*!< Position of READY field. */ + #define RRAMC_INTENCLR_READY_Msk (0x1UL << RRAMC_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ + #define RRAMC_INTENCLR_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RRAMC_INTENCLR_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RRAMC_INTENCLR_READY_Clear (0x1UL) /*!< Disable */ + #define RRAMC_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RRAMC_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READYNEXT @Bit 2 : Write '1' to disable interrupt for event READYNEXT */ + #define RRAMC_INTENCLR_READYNEXT_Pos (2UL) /*!< Position of READYNEXT field. */ + #define RRAMC_INTENCLR_READYNEXT_Msk (0x1UL << RRAMC_INTENCLR_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ + #define RRAMC_INTENCLR_READYNEXT_Min (0x0UL) /*!< Min enumerator value of READYNEXT field. */ + #define RRAMC_INTENCLR_READYNEXT_Max (0x1UL) /*!< Max enumerator value of READYNEXT field. */ + #define RRAMC_INTENCLR_READYNEXT_Clear (0x1UL) /*!< Disable */ + #define RRAMC_INTENCLR_READYNEXT_Disabled (0x0UL) /*!< Read: Disabled */ + #define RRAMC_INTENCLR_READYNEXT_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ACCESSERROR @Bit 3 : Write '1' to disable interrupt for event ACCESSERROR */ + #define RRAMC_INTENCLR_ACCESSERROR_Pos (3UL) /*!< Position of ACCESSERROR field. */ + #define RRAMC_INTENCLR_ACCESSERROR_Msk (0x1UL << RRAMC_INTENCLR_ACCESSERROR_Pos) /*!< Bit mask of ACCESSERROR field. */ + #define RRAMC_INTENCLR_ACCESSERROR_Min (0x0UL) /*!< Min enumerator value of ACCESSERROR field. */ + #define RRAMC_INTENCLR_ACCESSERROR_Max (0x1UL) /*!< Max enumerator value of ACCESSERROR field. */ + #define RRAMC_INTENCLR_ACCESSERROR_Clear (0x1UL) /*!< Disable */ + #define RRAMC_INTENCLR_ACCESSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define RRAMC_INTENCLR_ACCESSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RRAMC_INTPEND: Pending interrupts */ + #define RRAMC_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* WOKENUP @Bit 0 : Read pending status of interrupt for event WOKENUP */ + #define RRAMC_INTPEND_WOKENUP_Pos (0UL) /*!< Position of WOKENUP field. */ + #define RRAMC_INTPEND_WOKENUP_Msk (0x1UL << RRAMC_INTPEND_WOKENUP_Pos) /*!< Bit mask of WOKENUP field. */ + #define RRAMC_INTPEND_WOKENUP_Min (0x0UL) /*!< Min enumerator value of WOKENUP field. */ + #define RRAMC_INTPEND_WOKENUP_Max (0x1UL) /*!< Max enumerator value of WOKENUP field. */ + #define RRAMC_INTPEND_WOKENUP_NotPending (0x0UL) /*!< Read: Not pending */ + #define RRAMC_INTPEND_WOKENUP_Pending (0x1UL) /*!< Read: Pending */ + +/* READY @Bit 1 : Read pending status of interrupt for event READY */ + #define RRAMC_INTPEND_READY_Pos (1UL) /*!< Position of READY field. */ + #define RRAMC_INTPEND_READY_Msk (0x1UL << RRAMC_INTPEND_READY_Pos) /*!< Bit mask of READY field. */ + #define RRAMC_INTPEND_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RRAMC_INTPEND_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RRAMC_INTPEND_READY_NotPending (0x0UL) /*!< Read: Not pending */ + #define RRAMC_INTPEND_READY_Pending (0x1UL) /*!< Read: Pending */ + +/* READYNEXT @Bit 2 : Read pending status of interrupt for event READYNEXT */ + #define RRAMC_INTPEND_READYNEXT_Pos (2UL) /*!< Position of READYNEXT field. */ + #define RRAMC_INTPEND_READYNEXT_Msk (0x1UL << RRAMC_INTPEND_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ + #define RRAMC_INTPEND_READYNEXT_Min (0x0UL) /*!< Min enumerator value of READYNEXT field. */ + #define RRAMC_INTPEND_READYNEXT_Max (0x1UL) /*!< Max enumerator value of READYNEXT field. */ + #define RRAMC_INTPEND_READYNEXT_NotPending (0x0UL) /*!< Read: Not pending */ + #define RRAMC_INTPEND_READYNEXT_Pending (0x1UL) /*!< Read: Pending */ + +/* ACCESSERROR @Bit 3 : Read pending status of interrupt for event ACCESSERROR */ + #define RRAMC_INTPEND_ACCESSERROR_Pos (3UL) /*!< Position of ACCESSERROR field. */ + #define RRAMC_INTPEND_ACCESSERROR_Msk (0x1UL << RRAMC_INTPEND_ACCESSERROR_Pos) /*!< Bit mask of ACCESSERROR field. */ + #define RRAMC_INTPEND_ACCESSERROR_Min (0x0UL) /*!< Min enumerator value of ACCESSERROR field. */ + #define RRAMC_INTPEND_ACCESSERROR_Max (0x1UL) /*!< Max enumerator value of ACCESSERROR field. */ + #define RRAMC_INTPEND_ACCESSERROR_NotPending (0x0UL) /*!< Read: Not pending */ + #define RRAMC_INTPEND_ACCESSERROR_Pending (0x1UL) /*!< Read: Pending */ + + +/* RRAMC_READY: RRAMC ready status */ + #define RRAMC_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : RRAMC is ready or busy */ + #define RRAMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define RRAMC_READY_READY_Msk (0x1UL << RRAMC_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define RRAMC_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RRAMC_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RRAMC_READY_READY_Busy (0x0UL) /*!< RRAMC is busy */ + #define RRAMC_READY_READY_Ready (0x1UL) /*!< The current RRAMC operation is completed and RRAMC is ready */ + + +/* RRAMC_READYNEXT: Ready next flag */ + #define RRAMC_READYNEXT_ResetValue (0x00000000UL) /*!< Reset value of READYNEXT register. */ + +/* READYNEXT @Bit 0 : RRAMC can accept a new write operation */ + #define RRAMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */ + #define RRAMC_READYNEXT_READYNEXT_Msk (0x1UL << RRAMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ + #define RRAMC_READYNEXT_READYNEXT_Min (0x0UL) /*!< Min enumerator value of READYNEXT field. */ + #define RRAMC_READYNEXT_READYNEXT_Max (0x1UL) /*!< Max enumerator value of READYNEXT field. */ + #define RRAMC_READYNEXT_READYNEXT_Busy (0x0UL) /*!< RRAMC cannot accept any write operation now */ + #define RRAMC_READYNEXT_READYNEXT_Ready (0x1UL) /*!< RRAMC is ready to accept a new write operation */ + + +/* RRAMC_ACCESSERRORADDR: Address of the first access error */ + #define RRAMC_ACCESSERRORADDR_ResetValue (0x00FFFFFFUL) /*!< Reset value of ACCESSERRORADDR register. */ + +/* ADDRESS @Bits 0..31 : Access error address */ + #define RRAMC_ACCESSERRORADDR_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define RRAMC_ACCESSERRORADDR_ADDRESS_Msk (0xFFFFFFFFUL << RRAMC_ACCESSERRORADDR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.*/ + + +/* RRAMC_CONFIG: Configuration register */ + #define RRAMC_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* WEN @Bit 0 : Write enable */ + #define RRAMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ + #define RRAMC_CONFIG_WEN_Msk (0x1UL << RRAMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ + #define RRAMC_CONFIG_WEN_Min (0x0UL) /*!< Min enumerator value of WEN field. */ + #define RRAMC_CONFIG_WEN_Max (0x1UL) /*!< Max enumerator value of WEN field. */ + #define RRAMC_CONFIG_WEN_Disabled (0x0UL) /*!< Write is disabled */ + #define RRAMC_CONFIG_WEN_Enabled (0x1UL) /*!< Write is enabled */ + +/* WRITEBUFSIZE @Bits 8..13 : write-buffer size in number of 128-bit words */ + #define RRAMC_CONFIG_WRITEBUFSIZE_Pos (8UL) /*!< Position of WRITEBUFSIZE field. */ + #define RRAMC_CONFIG_WRITEBUFSIZE_Msk (0x3FUL << RRAMC_CONFIG_WRITEBUFSIZE_Pos) /*!< Bit mask of WRITEBUFSIZE field. */ + #define RRAMC_CONFIG_WRITEBUFSIZE_Min (0x00UL) /*!< Min value of WRITEBUFSIZE field. */ + #define RRAMC_CONFIG_WRITEBUFSIZE_Max (0x20UL) /*!< Max size of WRITEBUFSIZE field. */ + #define RRAMC_CONFIG_WRITEBUFSIZE_Unbuffered (0x00UL) /*!< Disable buffering */ + + +/* RRAMC_READYNEXTTIMEOUT: Configuration for ready next timeout counter, in units of AXI clock frequency */ + #define RRAMC_READYNEXTTIMEOUT_ResetValue (0x00000080UL) /*!< Reset value of READYNEXTTIMEOUT register. */ + +/* VALUE @Bits 0..11 : Preload value for waiting for a next write */ + #define RRAMC_READYNEXTTIMEOUT_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define RRAMC_READYNEXTTIMEOUT_VALUE_Msk (0xFFFUL << RRAMC_READYNEXTTIMEOUT_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define RRAMC_READYNEXTTIMEOUT_VALUE_Min (0x000UL) /*!< Min value of VALUE field. */ + #define RRAMC_READYNEXTTIMEOUT_VALUE_Max (0xFFFUL) /*!< Max size of VALUE field. */ + +/* EN @Bit 31 : Enable ready next timeout */ + #define RRAMC_READYNEXTTIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */ + #define RRAMC_READYNEXTTIMEOUT_EN_Msk (0x1UL << RRAMC_READYNEXTTIMEOUT_EN_Pos) /*!< Bit mask of EN field. */ + #define RRAMC_READYNEXTTIMEOUT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RRAMC_READYNEXTTIMEOUT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RRAMC_READYNEXTTIMEOUT_EN_Disable (0x0UL) /*!< Disable ready next timeout */ + #define RRAMC_READYNEXTTIMEOUT_EN_Enable (0x1UL) /*!< Enable ready next timeout */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ SAADC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================= Struct SAADC_EVENTS_CH ================================================== */ +/** + * @brief EVENTS_CH [SAADC_EVENTS_CH] Peripheral events. + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Last results is above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Last results is below CH[n].LIMIT.LOW */ +} NRF_SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x008) */ + #define SAADC_EVENTS_CH_MaxCount (8UL) /*!< Size of EVENTS_CH[8] array. */ + #define SAADC_EVENTS_CH_MaxIndex (7UL) /*!< Max index of EVENTS_CH[8] array. */ + #define SAADC_EVENTS_CH_MinIndex (0UL) /*!< Min index of EVENTS_CH[8] array. */ + +/* SAADC_EVENTS_CH_LIMITH: Last results is above CH[n].LIMIT.HIGH */ + #define SAADC_EVENTS_CH_LIMITH_ResetValue (0x00000000UL) /*!< Reset value of LIMITH register. */ + +/* LIMITH @Bit 0 : Last results is above CH[n].LIMIT.HIGH */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_Min (0x0UL) /*!< Min enumerator value of LIMITH field. */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_Max (0x1UL) /*!< Max enumerator value of LIMITH field. */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_CH_LIMITL: Last results is below CH[n].LIMIT.LOW */ + #define SAADC_EVENTS_CH_LIMITL_ResetValue (0x00000000UL) /*!< Reset value of LIMITL register. */ + +/* LIMITL @Bit 0 : Last results is below CH[n].LIMIT.LOW */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_Min (0x0UL) /*!< Min enumerator value of LIMITL field. */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_Max (0x1UL) /*!< Max enumerator value of LIMITL field. */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct SAADC_PUBLISH_CH ================================================= */ +/** + * @brief PUBLISH_CH [SAADC_PUBLISH_CH] Publish configuration for events + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Publish configuration for event CH[n].LIMITH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Publish configuration for event CH[n].LIMITL */ +} NRF_SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x008) */ + #define SAADC_PUBLISH_CH_MaxCount (8UL) /*!< Size of PUBLISH_CH[8] array. */ + #define SAADC_PUBLISH_CH_MaxIndex (7UL) /*!< Max index of PUBLISH_CH[8] array. */ + #define SAADC_PUBLISH_CH_MinIndex (0UL) /*!< Min index of PUBLISH_CH[8] array. */ + +/* SAADC_PUBLISH_CH_LIMITH: Publish configuration for event CH[n].LIMITH */ + #define SAADC_PUBLISH_CH_LIMITH_ResetValue (0x00000000UL) /*!< Reset value of LIMITH register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CH[n].LIMITH will publish to */ + #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_CH_LIMITL: Publish configuration for event CH[n].LIMITL */ + #define SAADC_PUBLISH_CH_LIMITL_ResetValue (0x00000000UL) /*!< Reset value of LIMITL register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CH[n].LIMITL will publish to */ + #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ==================================================== Struct SAADC_TRIM ==================================================== */ +/** + * @brief TRIM [SAADC_TRIM] (unspecified) + */ +typedef struct { + __IOM uint32_t LINCALCOEFF[6]; /*!< (@ 0x00000000) Linearity calibration coefficient */ +} NRF_SAADC_TRIM_Type; /*!< Size = 24 (0x018) */ + +/* SAADC_TRIM_LINCALCOEFF: Linearity calibration coefficient */ + #define SAADC_TRIM_LINCALCOEFF_MaxCount (6UL) /*!< Max size of LINCALCOEFF[6] array. */ + #define SAADC_TRIM_LINCALCOEFF_MaxIndex (5UL) /*!< Max index of LINCALCOEFF[6] array. */ + #define SAADC_TRIM_LINCALCOEFF_MinIndex (0UL) /*!< Min index of LINCALCOEFF[6] array. */ + #define SAADC_TRIM_LINCALCOEFF_ResetValue (0x00000000UL) /*!< Reset value of LINCALCOEFF[6] register. */ + +/* VAL @Bits 0..15 : value */ + #define SAADC_TRIM_LINCALCOEFF_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define SAADC_TRIM_LINCALCOEFF_VAL_Msk (0xFFFFUL << SAADC_TRIM_LINCALCOEFF_VAL_Pos) /*!< Bit mask of VAL field. */ + #define SAADC_TRIM_LINCALCOEFF_VAL_Min (0x0000UL) /*!< Min value of VAL field. */ + #define SAADC_TRIM_LINCALCOEFF_VAL_Max (0xFFFFUL) /*!< Max size of VAL field. */ + + + +/* ===================================================== Struct SAADC_CH ===================================================== */ +/** + * @brief CH [SAADC_CH] (unspecified) + */ +typedef struct { + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Input positive pin selection for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Input negative pin selection for CH[n] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Input configuration for CH[n] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) High/low limits for event monitoring a channel */ +} NRF_SAADC_CH_Type; /*!< Size = 16 (0x010) */ + #define SAADC_CH_MaxCount (8UL) /*!< Size of CH[8] array. */ + #define SAADC_CH_MaxIndex (7UL) /*!< Max index of CH[8] array. */ + #define SAADC_CH_MinIndex (0UL) /*!< Min index of CH[8] array. */ + +/* SAADC_CH_PSELP: Input positive pin selection for CH[n] */ + #define SAADC_CH_PSELP_ResetValue (0x00000000UL) /*!< Reset value of PSELP register. */ + +/* PIN @Bits 0..4 : GPIO pin selection. */ + #define SAADC_CH_PSELP_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SAADC_CH_PSELP_PIN_Msk (0x1FUL << SAADC_CH_PSELP_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO port selection */ + #define SAADC_CH_PSELP_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define SAADC_CH_PSELP_PORT_Msk (0xFUL << SAADC_CH_PSELP_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* INTERNAL @Bits 12..13 : Internal input selection for analog positive input when CH[n].PSELP.CONNECT = Internal */ + #define SAADC_CH_PSELP_INTERNAL_Pos (12UL) /*!< Position of INTERNAL field. */ + #define SAADC_CH_PSELP_INTERNAL_Msk (0x3UL << SAADC_CH_PSELP_INTERNAL_Pos) /*!< Bit mask of INTERNAL field. */ + #define SAADC_CH_PSELP_INTERNAL_Min (0x0UL) /*!< Min enumerator value of INTERNAL field. */ + #define SAADC_CH_PSELP_INTERNAL_Max (0x2UL) /*!< Max enumerator value of INTERNAL field. */ + #define SAADC_CH_PSELP_INTERNAL_Avdd (0x0UL) /*!< Connected to the internal 0.9V analog supply rail */ + #define SAADC_CH_PSELP_INTERNAL_Dvdd (0x1UL) /*!< Connected to the internal 0.9V digital supply rail */ + #define SAADC_CH_PSELP_INTERNAL_Vdd (0x2UL) /*!< Connected to VDD */ + +/* CONNECT @Bits 30..31 : Connection */ + #define SAADC_CH_PSELP_CONNECT_Pos (30UL) /*!< Position of CONNECT field. */ + #define SAADC_CH_PSELP_CONNECT_Msk (0x3UL << SAADC_CH_PSELP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SAADC_CH_PSELP_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SAADC_CH_PSELP_CONNECT_Max (0x2UL) /*!< Max enumerator value of CONNECT field. */ + #define SAADC_CH_PSELP_CONNECT_NC (0x0UL) /*!< Not connected */ + #define SAADC_CH_PSELP_CONNECT_AnalogInput (0x1UL) /*!< Select analog input */ + #define SAADC_CH_PSELP_CONNECT_Internal (0x2UL) /*!< Selects internal inputs. */ + + +/* SAADC_CH_PSELN: Input negative pin selection for CH[n] */ + #define SAADC_CH_PSELN_ResetValue (0x00000000UL) /*!< Reset value of PSELN register. */ + +/* PIN @Bits 0..4 : GPIO pin selection. */ + #define SAADC_CH_PSELN_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SAADC_CH_PSELN_PIN_Msk (0x1FUL << SAADC_CH_PSELN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO Port selection */ + #define SAADC_CH_PSELN_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define SAADC_CH_PSELN_PORT_Msk (0xFUL << SAADC_CH_PSELN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* INTERNAL @Bits 12..13 : Internal input selection for analog negative input when CH[n].PSELN.CONNECT = Internal */ + #define SAADC_CH_PSELN_INTERNAL_Pos (12UL) /*!< Position of INTERNAL field. */ + #define SAADC_CH_PSELN_INTERNAL_Msk (0x3UL << SAADC_CH_PSELN_INTERNAL_Pos) /*!< Bit mask of INTERNAL field. */ + #define SAADC_CH_PSELN_INTERNAL_Min (0x0UL) /*!< Min enumerator value of INTERNAL field. */ + #define SAADC_CH_PSELN_INTERNAL_Max (0x2UL) /*!< Max enumerator value of INTERNAL field. */ + #define SAADC_CH_PSELN_INTERNAL_Avdd (0x0UL) /*!< Connected to the internal 0.9V analog supply rail */ + #define SAADC_CH_PSELN_INTERNAL_Dvdd (0x1UL) /*!< Connected to the internal 0.9V digital supply rail */ + #define SAADC_CH_PSELN_INTERNAL_Vdd (0x2UL) /*!< Connected to VDD */ + +/* CONNECT @Bits 30..31 : Connection */ + #define SAADC_CH_PSELN_CONNECT_Pos (30UL) /*!< Position of CONNECT field. */ + #define SAADC_CH_PSELN_CONNECT_Msk (0x3UL << SAADC_CH_PSELN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SAADC_CH_PSELN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SAADC_CH_PSELN_CONNECT_Max (0x2UL) /*!< Max enumerator value of CONNECT field. */ + #define SAADC_CH_PSELN_CONNECT_NC (0x0UL) /*!< Not connected */ + #define SAADC_CH_PSELN_CONNECT_AnalogInput (0x1UL) /*!< Select analog input */ + #define SAADC_CH_PSELN_CONNECT_Internal (0x2UL) /*!< Selects internal inputs. */ + + +/* SAADC_CH_CONFIG: Input configuration for CH[n] */ + #define SAADC_CH_CONFIG_ResetValue (0x00020000UL) /*!< Reset value of CONFIG register. */ + +/* CHOPPING @Bit 0 : Enable chopping */ + #define SAADC_CH_CONFIG_CHOPPING_Pos (0UL) /*!< Position of CHOPPING field. */ + #define SAADC_CH_CONFIG_CHOPPING_Msk (0x1UL << SAADC_CH_CONFIG_CHOPPING_Pos) /*!< Bit mask of CHOPPING field. */ + #define SAADC_CH_CONFIG_CHOPPING_Min (0x0UL) /*!< Min enumerator value of CHOPPING field. */ + #define SAADC_CH_CONFIG_CHOPPING_Max (0x1UL) /*!< Max enumerator value of CHOPPING field. */ + #define SAADC_CH_CONFIG_CHOPPING_Disabled (0x0UL) /*!< Chopping is disabled */ + #define SAADC_CH_CONFIG_CHOPPING_Enabled (0x1UL) /*!< Chopping is enabled */ + +/* GAIN @Bits 8..10 : Gain control */ + #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ + #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ + #define SAADC_CH_CONFIG_GAIN_Min (0x0UL) /*!< Min enumerator value of GAIN field. */ + #define SAADC_CH_CONFIG_GAIN_Max (0x7UL) /*!< Max enumerator value of GAIN field. */ + #define SAADC_CH_CONFIG_GAIN_Gain2 (0x0UL) /*!< 2 */ + #define SAADC_CH_CONFIG_GAIN_Gain1 (0x1UL) /*!< 1 */ + #define SAADC_CH_CONFIG_GAIN_Gain2_3 (0x2UL) /*!< 2/3 */ + #define SAADC_CH_CONFIG_GAIN_Gain2_4 (0x3UL) /*!< 2/4 */ + #define SAADC_CH_CONFIG_GAIN_Gain2_5 (0x4UL) /*!< 2/5 */ + #define SAADC_CH_CONFIG_GAIN_Gain2_6 (0x5UL) /*!< 2/6 */ + #define SAADC_CH_CONFIG_GAIN_Gain2_7 (0x6UL) /*!< 2/7 */ + #define SAADC_CH_CONFIG_GAIN_Gain2_8 (0x7UL) /*!< 2/8 */ + +/* REFSEL @Bit 12 : Reference control */ + #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ + #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ + #define SAADC_CH_CONFIG_REFSEL_Min (0x0UL) /*!< Min enumerator value of REFSEL field. */ + #define SAADC_CH_CONFIG_REFSEL_Max (0x1UL) /*!< Max enumerator value of REFSEL field. */ + #define SAADC_CH_CONFIG_REFSEL_Internal (0x0UL) /*!< Internal reference (0.9 V) */ + #define SAADC_CH_CONFIG_REFSEL_External (0x1UL) /*!< External reference given at PADC_EXT_REF_1V2 */ + +/* MODE @Bit 15 : Enable differential mode */ + #define SAADC_CH_CONFIG_MODE_Pos (15UL) /*!< Position of MODE field. */ + #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ + #define SAADC_CH_CONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define SAADC_CH_CONFIG_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define SAADC_CH_CONFIG_MODE_SE (0x0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to + GND*/ + #define SAADC_CH_CONFIG_MODE_Diff (0x1UL) /*!< Differential */ + +/* TACQ @Bits 16..24 : Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquistion time is + ((TACQ+1) x 125 ns) */ + + #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ + #define SAADC_CH_CONFIG_TACQ_Msk (0x1FFUL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ + #define SAADC_CH_CONFIG_TACQ_Min (0x001UL) /*!< Min value of TACQ field. */ + #define SAADC_CH_CONFIG_TACQ_Max (0x13FUL) /*!< Max size of TACQ field. */ + +/* TCONV @Bits 28..30 : Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns) */ + #define SAADC_CH_CONFIG_TCONV_Pos (28UL) /*!< Position of TCONV field. */ + #define SAADC_CH_CONFIG_TCONV_Msk (0x7UL << SAADC_CH_CONFIG_TCONV_Pos) /*!< Bit mask of TCONV field. */ + #define SAADC_CH_CONFIG_TCONV_Min (0x1UL) /*!< Min value of TCONV field. */ + #define SAADC_CH_CONFIG_TCONV_Max (0x7UL) /*!< Max size of TCONV field. */ + + +/* SAADC_CH_LIMIT: High/low limits for event monitoring a channel */ + #define SAADC_CH_LIMIT_ResetValue (0x7FFF8000UL) /*!< Reset value of LIMIT register. */ + +/* LOW @Bits 0..15 : Low level limit */ + #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ + #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* HIGH @Bits 16..31 : High level limit */ + #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ + #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + + + +/* =================================================== Struct SAADC_RESULT =================================================== */ +/** + * @brief RESULT [SAADC_RESULT] RESULT EasyDMA channel + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of buffer bytes to transfer. Note that + one sample is two bytes.*/ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of buffer bytes transferred since last START, + updated after the END or STOPPED events*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of buffer bytes transferred since last START, + continuously updated*/ +} NRF_SAADC_RESULT_Type; /*!< Size = 20 (0x014) */ + +/* SAADC_RESULT_PTR: Data pointer */ + #define SAADC_RESULT_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Data pointer */ + #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* SAADC_RESULT_MAXCNT: Maximum number of buffer bytes to transfer. Note that one sample is two bytes. */ + #define SAADC_RESULT_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of buffer bytes to transfer. Note that one sample is two bytes. */ + #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + + +/* SAADC_RESULT_AMOUNT: Number of buffer bytes transferred since last START, updated after the END or STOPPED events */ + #define SAADC_RESULT_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of buffer bytes transferred since last START, updated after the END or STOPPED events. */ + #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* SAADC_RESULT_CURRENTAMOUNT: Number of buffer bytes transferred since last START, continuously updated */ + #define SAADC_RESULT_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of buffer bytes transferred since last START, continuously updated. */ + #define SAADC_RESULT_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SAADC_RESULT_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + + +/* ====================================================== Struct SAADC ======================================================= */ +/** + * @brief Analog to Digital Converter + */ + typedef struct { /*!< SAADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels + are sampled. This task requires that SAADC has started, + i.e. EVENTS_STARTED was set and EVENTS_STOPPED was + not.*/ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[28]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ + __IM uint32_t RESERVED1[28]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC DMA has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending on the + mode, multiple conversions might be needed for a result + to be transferred to RAM.*/ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC DMA has stopped */ + __IOM NRF_SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ + __IM uint32_t RESERVED2[10]; + __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ + __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ + __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ + __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ + __IOM NRF_SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ + __IM uint32_t RESERVED3[10]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED6[15]; + __IOM NRF_SAADC_TRIM_Type TRIM; /*!< (@ 0x00000440) (unspecified) */ + __IM uint32_t RESERVED7[42]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ + __IM uint32_t RESERVED8[3]; + __IOM NRF_SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) (unspecified) */ + __IM uint32_t RESERVED9[22]; + __IOM uint32_t BURST; /*!< (@ 0x000005E8) Enable burst mode */ + __IM uint32_t RESERVED10; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should not be + combined with SCAN unless burst is enabled. The + RESOLUTION is applied before averaging, thus for high + OVERSAMPLE a higher RESOLUTION should be used.*/ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Configures the sampling rate for either task-triggered + or continuous operation using a local timer*/ + __IM uint32_t RESERVED11[11]; + __IOM NRF_SAADC_RESULT_Type RESULT; /*!< (@ 0x00000628) RESULT EasyDMA channel */ + __IM uint32_t RESERVED12[6]; + __IOM uint32_t NOISESHAPE; /*!< (@ 0x00000654) SAADC provides two operational noise shaping modes (one + that prioritizes higher bandwith, while the other + prioritizes higher accuracy) that allow trade-offs + between ADC resolution, power consumption, and signal + bandwidth.*/ + } NRF_SAADC_Type; /*!< Size = 1624 (0x658) */ + +/* SAADC_TASKS_START: Start the ADC and prepare the result buffer in RAM */ + #define SAADC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start the ADC and prepare the result buffer in RAM */ + #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define SAADC_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define SAADC_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define SAADC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* SAADC_TASKS_SAMPLE: Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has + started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. */ + + #define SAADC_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register. */ + +/* TASKS_SAMPLE @Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has + started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. */ + + #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ + #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE + field.*/ + #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field. */ + #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field. */ + #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */ + + +/* SAADC_TASKS_STOP: Stop the ADC and terminate any on-going conversion */ + #define SAADC_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop the ADC and terminate any on-going conversion */ + #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define SAADC_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define SAADC_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* SAADC_TASKS_CALIBRATEOFFSET: Starts offset auto-calibration */ + #define SAADC_TASKS_CALIBRATEOFFSET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CALIBRATEOFFSET register. */ + +/* TASKS_CALIBRATEOFFSET @Bit 0 : Starts offset auto-calibration */ + #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ + #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) + /*!< Bit mask of TASKS_CALIBRATEOFFSET field.*/ + #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Min (0x1UL) /*!< Min enumerator value of TASKS_CALIBRATEOFFSET + field.*/ + #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Max (0x1UL) /*!< Max enumerator value of TASKS_CALIBRATEOFFSET + field.*/ + #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (0x1UL) /*!< Trigger task */ + + +/* SAADC_SUBSCRIBE_START: Subscribe configuration for task START */ + #define SAADC_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SAADC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SAADC_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */ + #define SAADC_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */ + #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SAADC_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define SAADC_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SAADC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SAADC_SUBSCRIBE_CALIBRATEOFFSET: Subscribe configuration for task CALIBRATEOFFSET */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CALIBRATEOFFSET register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CALIBRATEOFFSET will subscribe to */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SAADC_EVENTS_STARTED: The ADC DMA has started */ + #define SAADC_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register. */ + +/* EVENTS_STARTED @Bit 0 : The ADC DMA has started */ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of + EVENTS_STARTED field.*/ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field. */ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field. */ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_END: The ADC has filled up the Result buffer */ + #define SAADC_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : The ADC has filled up the Result buffer */ + #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define SAADC_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define SAADC_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_DONE: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a + result to be transferred to RAM. */ + + #define SAADC_EVENTS_DONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DONE register. */ + +/* EVENTS_DONE @Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a + result to be transferred to RAM. */ + + #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ + #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ + #define SAADC_EVENTS_DONE_EVENTS_DONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_DONE field. */ + #define SAADC_EVENTS_DONE_EVENTS_DONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_DONE field. */ + #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_RESULTDONE: A result is ready to get transferred to RAM. */ + #define SAADC_EVENTS_RESULTDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RESULTDONE register. */ + +/* EVENTS_RESULTDONE @Bit 0 : A result is ready to get transferred to RAM. */ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask + of EVENTS_RESULTDONE field.*/ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_RESULTDONE field. */ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_RESULTDONE field. */ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_CALIBRATEDONE: Calibration is complete */ + #define SAADC_EVENTS_CALIBRATEDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CALIBRATEDONE register. */ + +/* EVENTS_CALIBRATEDONE @Bit 0 : Calibration is complete */ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) + /*!< Bit mask of EVENTS_CALIBRATEDONE field.*/ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CALIBRATEDONE field. */ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CALIBRATEDONE field. */ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_STOPPED: The ADC DMA has stopped */ + #define SAADC_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : The ADC DMA has stopped */ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_PUBLISH_STARTED: Publish configuration for event STARTED */ + #define SAADC_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */ + #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_STARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_STARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_STARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_STARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_END: Publish configuration for event END */ + #define SAADC_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_DONE: Publish configuration for event DONE */ + #define SAADC_PUBLISH_DONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DONE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DONE will publish to */ + #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_DONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_DONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_DONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_DONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_DONE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_DONE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_RESULTDONE: Publish configuration for event RESULTDONE */ + #define SAADC_PUBLISH_RESULTDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RESULTDONE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RESULTDONE will publish to */ + #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_RESULTDONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_RESULTDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_RESULTDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_RESULTDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_CALIBRATEDONE: Publish configuration for event CALIBRATEDONE */ + #define SAADC_PUBLISH_CALIBRATEDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CALIBRATEDONE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CALIBRATEDONE will publish to */ + #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define SAADC_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_SHORTS: Shortcuts between local events and tasks */ + #define SAADC_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* DONE_SAMPLE @Bit 0 : Shortcut between event DONE and task SAMPLE */ + #define SAADC_SHORTS_DONE_SAMPLE_Pos (0UL) /*!< Position of DONE_SAMPLE field. */ + #define SAADC_SHORTS_DONE_SAMPLE_Msk (0x1UL << SAADC_SHORTS_DONE_SAMPLE_Pos) /*!< Bit mask of DONE_SAMPLE field. */ + #define SAADC_SHORTS_DONE_SAMPLE_Min (0x0UL) /*!< Min enumerator value of DONE_SAMPLE field. */ + #define SAADC_SHORTS_DONE_SAMPLE_Max (0x1UL) /*!< Max enumerator value of DONE_SAMPLE field. */ + #define SAADC_SHORTS_DONE_SAMPLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define SAADC_SHORTS_DONE_SAMPLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* END_START @Bit 1 : Shortcut between event END and task START */ + #define SAADC_SHORTS_END_START_Pos (1UL) /*!< Position of END_START field. */ + #define SAADC_SHORTS_END_START_Msk (0x1UL << SAADC_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ + #define SAADC_SHORTS_END_START_Min (0x0UL) /*!< Min enumerator value of END_START field. */ + #define SAADC_SHORTS_END_START_Max (0x1UL) /*!< Max enumerator value of END_START field. */ + #define SAADC_SHORTS_END_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define SAADC_SHORTS_END_START_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* SAADC_INTEN: Enable or disable interrupt */ + #define SAADC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* STARTED @Bit 0 : Enable or disable interrupt for event STARTED */ + #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define SAADC_INTEN_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define SAADC_INTEN_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define SAADC_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ + +/* END @Bit 1 : Enable or disable interrupt for event END */ + #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ + #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ + #define SAADC_INTEN_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SAADC_INTEN_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SAADC_INTEN_END_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_END_Enabled (0x1UL) /*!< Enable */ + +/* DONE @Bit 2 : Enable or disable interrupt for event DONE */ + #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ + #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ + #define SAADC_INTEN_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define SAADC_INTEN_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define SAADC_INTEN_DONE_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_DONE_Enabled (0x1UL) /*!< Enable */ + +/* RESULTDONE @Bit 3 : Enable or disable interrupt for event RESULTDONE */ + #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ + #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ + #define SAADC_INTEN_RESULTDONE_Min (0x0UL) /*!< Min enumerator value of RESULTDONE field. */ + #define SAADC_INTEN_RESULTDONE_Max (0x1UL) /*!< Max enumerator value of RESULTDONE field. */ + #define SAADC_INTEN_RESULTDONE_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_RESULTDONE_Enabled (0x1UL) /*!< Enable */ + +/* CALIBRATEDONE @Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ + #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ + #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ + #define SAADC_INTEN_CALIBRATEDONE_Min (0x0UL) /*!< Min enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTEN_CALIBRATEDONE_Max (0x1UL) /*!< Max enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTEN_CALIBRATEDONE_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CALIBRATEDONE_Enabled (0x1UL) /*!< Enable */ + +/* STOPPED @Bit 5 : Enable or disable interrupt for event STOPPED */ + #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ + #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define SAADC_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define SAADC_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define SAADC_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* CH0LIMITH @Bit 6 : Enable or disable interrupt for event CH0LIMITH */ + #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ + #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ + #define SAADC_INTEN_CH0LIMITH_Min (0x0UL) /*!< Min enumerator value of CH0LIMITH field. */ + #define SAADC_INTEN_CH0LIMITH_Max (0x1UL) /*!< Max enumerator value of CH0LIMITH field. */ + #define SAADC_INTEN_CH0LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH0LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH0LIMITL @Bit 7 : Enable or disable interrupt for event CH0LIMITL */ + #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ + #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ + #define SAADC_INTEN_CH0LIMITL_Min (0x0UL) /*!< Min enumerator value of CH0LIMITL field. */ + #define SAADC_INTEN_CH0LIMITL_Max (0x1UL) /*!< Max enumerator value of CH0LIMITL field. */ + #define SAADC_INTEN_CH0LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH0LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH1LIMITH @Bit 8 : Enable or disable interrupt for event CH1LIMITH */ + #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ + #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ + #define SAADC_INTEN_CH1LIMITH_Min (0x0UL) /*!< Min enumerator value of CH1LIMITH field. */ + #define SAADC_INTEN_CH1LIMITH_Max (0x1UL) /*!< Max enumerator value of CH1LIMITH field. */ + #define SAADC_INTEN_CH1LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH1LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH1LIMITL @Bit 9 : Enable or disable interrupt for event CH1LIMITL */ + #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ + #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ + #define SAADC_INTEN_CH1LIMITL_Min (0x0UL) /*!< Min enumerator value of CH1LIMITL field. */ + #define SAADC_INTEN_CH1LIMITL_Max (0x1UL) /*!< Max enumerator value of CH1LIMITL field. */ + #define SAADC_INTEN_CH1LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH1LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH2LIMITH @Bit 10 : Enable or disable interrupt for event CH2LIMITH */ + #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ + #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ + #define SAADC_INTEN_CH2LIMITH_Min (0x0UL) /*!< Min enumerator value of CH2LIMITH field. */ + #define SAADC_INTEN_CH2LIMITH_Max (0x1UL) /*!< Max enumerator value of CH2LIMITH field. */ + #define SAADC_INTEN_CH2LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH2LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH2LIMITL @Bit 11 : Enable or disable interrupt for event CH2LIMITL */ + #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ + #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ + #define SAADC_INTEN_CH2LIMITL_Min (0x0UL) /*!< Min enumerator value of CH2LIMITL field. */ + #define SAADC_INTEN_CH2LIMITL_Max (0x1UL) /*!< Max enumerator value of CH2LIMITL field. */ + #define SAADC_INTEN_CH2LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH2LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH3LIMITH @Bit 12 : Enable or disable interrupt for event CH3LIMITH */ + #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ + #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ + #define SAADC_INTEN_CH3LIMITH_Min (0x0UL) /*!< Min enumerator value of CH3LIMITH field. */ + #define SAADC_INTEN_CH3LIMITH_Max (0x1UL) /*!< Max enumerator value of CH3LIMITH field. */ + #define SAADC_INTEN_CH3LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH3LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH3LIMITL @Bit 13 : Enable or disable interrupt for event CH3LIMITL */ + #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ + #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ + #define SAADC_INTEN_CH3LIMITL_Min (0x0UL) /*!< Min enumerator value of CH3LIMITL field. */ + #define SAADC_INTEN_CH3LIMITL_Max (0x1UL) /*!< Max enumerator value of CH3LIMITL field. */ + #define SAADC_INTEN_CH3LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH3LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH4LIMITH @Bit 14 : Enable or disable interrupt for event CH4LIMITH */ + #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ + #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ + #define SAADC_INTEN_CH4LIMITH_Min (0x0UL) /*!< Min enumerator value of CH4LIMITH field. */ + #define SAADC_INTEN_CH4LIMITH_Max (0x1UL) /*!< Max enumerator value of CH4LIMITH field. */ + #define SAADC_INTEN_CH4LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH4LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH4LIMITL @Bit 15 : Enable or disable interrupt for event CH4LIMITL */ + #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ + #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ + #define SAADC_INTEN_CH4LIMITL_Min (0x0UL) /*!< Min enumerator value of CH4LIMITL field. */ + #define SAADC_INTEN_CH4LIMITL_Max (0x1UL) /*!< Max enumerator value of CH4LIMITL field. */ + #define SAADC_INTEN_CH4LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH4LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH5LIMITH @Bit 16 : Enable or disable interrupt for event CH5LIMITH */ + #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ + #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ + #define SAADC_INTEN_CH5LIMITH_Min (0x0UL) /*!< Min enumerator value of CH5LIMITH field. */ + #define SAADC_INTEN_CH5LIMITH_Max (0x1UL) /*!< Max enumerator value of CH5LIMITH field. */ + #define SAADC_INTEN_CH5LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH5LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH5LIMITL @Bit 17 : Enable or disable interrupt for event CH5LIMITL */ + #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ + #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ + #define SAADC_INTEN_CH5LIMITL_Min (0x0UL) /*!< Min enumerator value of CH5LIMITL field. */ + #define SAADC_INTEN_CH5LIMITL_Max (0x1UL) /*!< Max enumerator value of CH5LIMITL field. */ + #define SAADC_INTEN_CH5LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH5LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH6LIMITH @Bit 18 : Enable or disable interrupt for event CH6LIMITH */ + #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ + #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ + #define SAADC_INTEN_CH6LIMITH_Min (0x0UL) /*!< Min enumerator value of CH6LIMITH field. */ + #define SAADC_INTEN_CH6LIMITH_Max (0x1UL) /*!< Max enumerator value of CH6LIMITH field. */ + #define SAADC_INTEN_CH6LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH6LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH6LIMITL @Bit 19 : Enable or disable interrupt for event CH6LIMITL */ + #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ + #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ + #define SAADC_INTEN_CH6LIMITL_Min (0x0UL) /*!< Min enumerator value of CH6LIMITL field. */ + #define SAADC_INTEN_CH6LIMITL_Max (0x1UL) /*!< Max enumerator value of CH6LIMITL field. */ + #define SAADC_INTEN_CH6LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH6LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH7LIMITH @Bit 20 : Enable or disable interrupt for event CH7LIMITH */ + #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ + #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ + #define SAADC_INTEN_CH7LIMITH_Min (0x0UL) /*!< Min enumerator value of CH7LIMITH field. */ + #define SAADC_INTEN_CH7LIMITH_Max (0x1UL) /*!< Max enumerator value of CH7LIMITH field. */ + #define SAADC_INTEN_CH7LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH7LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH7LIMITL @Bit 21 : Enable or disable interrupt for event CH7LIMITL */ + #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ + #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ + #define SAADC_INTEN_CH7LIMITL_Min (0x0UL) /*!< Min enumerator value of CH7LIMITL field. */ + #define SAADC_INTEN_CH7LIMITL_Max (0x1UL) /*!< Max enumerator value of CH7LIMITL field. */ + #define SAADC_INTEN_CH7LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH7LIMITL_Enabled (0x1UL) /*!< Enable */ + + +/* SAADC_INTENSET: Enable interrupt */ + #define SAADC_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */ + #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define SAADC_INTENSET_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define SAADC_INTENSET_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define SAADC_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 1 : Write '1' to enable interrupt for event END */ + #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ + #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define SAADC_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SAADC_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SAADC_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DONE @Bit 2 : Write '1' to enable interrupt for event DONE */ + #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ + #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ + #define SAADC_INTENSET_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define SAADC_INTENSET_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define SAADC_INTENSET_DONE_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_DONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_DONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RESULTDONE @Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ + #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ + #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ + #define SAADC_INTENSET_RESULTDONE_Min (0x0UL) /*!< Min enumerator value of RESULTDONE field. */ + #define SAADC_INTENSET_RESULTDONE_Max (0x1UL) /*!< Max enumerator value of RESULTDONE field. */ + #define SAADC_INTENSET_RESULTDONE_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CALIBRATEDONE @Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ + #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ + #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ + #define SAADC_INTENSET_CALIBRATEDONE_Min (0x0UL) /*!< Min enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTENSET_CALIBRATEDONE_Max (0x1UL) /*!< Max enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTENSET_CALIBRATEDONE_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 5 : Write '1' to enable interrupt for event STOPPED */ + #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ + #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define SAADC_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define SAADC_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define SAADC_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH0LIMITH @Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ + #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ + #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ + #define SAADC_INTENSET_CH0LIMITH_Min (0x0UL) /*!< Min enumerator value of CH0LIMITH field. */ + #define SAADC_INTENSET_CH0LIMITH_Max (0x1UL) /*!< Max enumerator value of CH0LIMITH field. */ + #define SAADC_INTENSET_CH0LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH0LIMITL @Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ + #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ + #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ + #define SAADC_INTENSET_CH0LIMITL_Min (0x0UL) /*!< Min enumerator value of CH0LIMITL field. */ + #define SAADC_INTENSET_CH0LIMITL_Max (0x1UL) /*!< Max enumerator value of CH0LIMITL field. */ + #define SAADC_INTENSET_CH0LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH1LIMITH @Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ + #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ + #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ + #define SAADC_INTENSET_CH1LIMITH_Min (0x0UL) /*!< Min enumerator value of CH1LIMITH field. */ + #define SAADC_INTENSET_CH1LIMITH_Max (0x1UL) /*!< Max enumerator value of CH1LIMITH field. */ + #define SAADC_INTENSET_CH1LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH1LIMITL @Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ + #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ + #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ + #define SAADC_INTENSET_CH1LIMITL_Min (0x0UL) /*!< Min enumerator value of CH1LIMITL field. */ + #define SAADC_INTENSET_CH1LIMITL_Max (0x1UL) /*!< Max enumerator value of CH1LIMITL field. */ + #define SAADC_INTENSET_CH1LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH2LIMITH @Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ + #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ + #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ + #define SAADC_INTENSET_CH2LIMITH_Min (0x0UL) /*!< Min enumerator value of CH2LIMITH field. */ + #define SAADC_INTENSET_CH2LIMITH_Max (0x1UL) /*!< Max enumerator value of CH2LIMITH field. */ + #define SAADC_INTENSET_CH2LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH2LIMITL @Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ + #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ + #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ + #define SAADC_INTENSET_CH2LIMITL_Min (0x0UL) /*!< Min enumerator value of CH2LIMITL field. */ + #define SAADC_INTENSET_CH2LIMITL_Max (0x1UL) /*!< Max enumerator value of CH2LIMITL field. */ + #define SAADC_INTENSET_CH2LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH3LIMITH @Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ + #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ + #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ + #define SAADC_INTENSET_CH3LIMITH_Min (0x0UL) /*!< Min enumerator value of CH3LIMITH field. */ + #define SAADC_INTENSET_CH3LIMITH_Max (0x1UL) /*!< Max enumerator value of CH3LIMITH field. */ + #define SAADC_INTENSET_CH3LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH3LIMITL @Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ + #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ + #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ + #define SAADC_INTENSET_CH3LIMITL_Min (0x0UL) /*!< Min enumerator value of CH3LIMITL field. */ + #define SAADC_INTENSET_CH3LIMITL_Max (0x1UL) /*!< Max enumerator value of CH3LIMITL field. */ + #define SAADC_INTENSET_CH3LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH4LIMITH @Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ + #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ + #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ + #define SAADC_INTENSET_CH4LIMITH_Min (0x0UL) /*!< Min enumerator value of CH4LIMITH field. */ + #define SAADC_INTENSET_CH4LIMITH_Max (0x1UL) /*!< Max enumerator value of CH4LIMITH field. */ + #define SAADC_INTENSET_CH4LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH4LIMITL @Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ + #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ + #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ + #define SAADC_INTENSET_CH4LIMITL_Min (0x0UL) /*!< Min enumerator value of CH4LIMITL field. */ + #define SAADC_INTENSET_CH4LIMITL_Max (0x1UL) /*!< Max enumerator value of CH4LIMITL field. */ + #define SAADC_INTENSET_CH4LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH5LIMITH @Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ + #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ + #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ + #define SAADC_INTENSET_CH5LIMITH_Min (0x0UL) /*!< Min enumerator value of CH5LIMITH field. */ + #define SAADC_INTENSET_CH5LIMITH_Max (0x1UL) /*!< Max enumerator value of CH5LIMITH field. */ + #define SAADC_INTENSET_CH5LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH5LIMITL @Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ + #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ + #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ + #define SAADC_INTENSET_CH5LIMITL_Min (0x0UL) /*!< Min enumerator value of CH5LIMITL field. */ + #define SAADC_INTENSET_CH5LIMITL_Max (0x1UL) /*!< Max enumerator value of CH5LIMITL field. */ + #define SAADC_INTENSET_CH5LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH6LIMITH @Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ + #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ + #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ + #define SAADC_INTENSET_CH6LIMITH_Min (0x0UL) /*!< Min enumerator value of CH6LIMITH field. */ + #define SAADC_INTENSET_CH6LIMITH_Max (0x1UL) /*!< Max enumerator value of CH6LIMITH field. */ + #define SAADC_INTENSET_CH6LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH6LIMITL @Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ + #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ + #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ + #define SAADC_INTENSET_CH6LIMITL_Min (0x0UL) /*!< Min enumerator value of CH6LIMITL field. */ + #define SAADC_INTENSET_CH6LIMITL_Max (0x1UL) /*!< Max enumerator value of CH6LIMITL field. */ + #define SAADC_INTENSET_CH6LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH7LIMITH @Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ + #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ + #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ + #define SAADC_INTENSET_CH7LIMITH_Min (0x0UL) /*!< Min enumerator value of CH7LIMITH field. */ + #define SAADC_INTENSET_CH7LIMITH_Max (0x1UL) /*!< Max enumerator value of CH7LIMITH field. */ + #define SAADC_INTENSET_CH7LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH7LIMITL @Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ + #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ + #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ + #define SAADC_INTENSET_CH7LIMITL_Min (0x0UL) /*!< Min enumerator value of CH7LIMITL field. */ + #define SAADC_INTENSET_CH7LIMITL_Max (0x1UL) /*!< Max enumerator value of CH7LIMITL field. */ + #define SAADC_INTENSET_CH7LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SAADC_INTENCLR: Disable interrupt */ + #define SAADC_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */ + #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define SAADC_INTENCLR_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define SAADC_INTENCLR_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define SAADC_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 1 : Write '1' to disable interrupt for event END */ + #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ + #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define SAADC_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SAADC_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SAADC_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DONE @Bit 2 : Write '1' to disable interrupt for event DONE */ + #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ + #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ + #define SAADC_INTENCLR_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define SAADC_INTENCLR_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define SAADC_INTENCLR_DONE_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_DONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_DONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RESULTDONE @Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ + #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ + #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ + #define SAADC_INTENCLR_RESULTDONE_Min (0x0UL) /*!< Min enumerator value of RESULTDONE field. */ + #define SAADC_INTENCLR_RESULTDONE_Max (0x1UL) /*!< Max enumerator value of RESULTDONE field. */ + #define SAADC_INTENCLR_RESULTDONE_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CALIBRATEDONE @Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ + #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ + #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ + #define SAADC_INTENCLR_CALIBRATEDONE_Min (0x0UL) /*!< Min enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTENCLR_CALIBRATEDONE_Max (0x1UL) /*!< Max enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTENCLR_CALIBRATEDONE_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 5 : Write '1' to disable interrupt for event STOPPED */ + #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ + #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define SAADC_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define SAADC_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define SAADC_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH0LIMITH @Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ + #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ + #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ + #define SAADC_INTENCLR_CH0LIMITH_Min (0x0UL) /*!< Min enumerator value of CH0LIMITH field. */ + #define SAADC_INTENCLR_CH0LIMITH_Max (0x1UL) /*!< Max enumerator value of CH0LIMITH field. */ + #define SAADC_INTENCLR_CH0LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH0LIMITL @Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ + #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ + #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ + #define SAADC_INTENCLR_CH0LIMITL_Min (0x0UL) /*!< Min enumerator value of CH0LIMITL field. */ + #define SAADC_INTENCLR_CH0LIMITL_Max (0x1UL) /*!< Max enumerator value of CH0LIMITL field. */ + #define SAADC_INTENCLR_CH0LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH1LIMITH @Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ + #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ + #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ + #define SAADC_INTENCLR_CH1LIMITH_Min (0x0UL) /*!< Min enumerator value of CH1LIMITH field. */ + #define SAADC_INTENCLR_CH1LIMITH_Max (0x1UL) /*!< Max enumerator value of CH1LIMITH field. */ + #define SAADC_INTENCLR_CH1LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH1LIMITL @Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ + #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ + #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ + #define SAADC_INTENCLR_CH1LIMITL_Min (0x0UL) /*!< Min enumerator value of CH1LIMITL field. */ + #define SAADC_INTENCLR_CH1LIMITL_Max (0x1UL) /*!< Max enumerator value of CH1LIMITL field. */ + #define SAADC_INTENCLR_CH1LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH2LIMITH @Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ + #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ + #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ + #define SAADC_INTENCLR_CH2LIMITH_Min (0x0UL) /*!< Min enumerator value of CH2LIMITH field. */ + #define SAADC_INTENCLR_CH2LIMITH_Max (0x1UL) /*!< Max enumerator value of CH2LIMITH field. */ + #define SAADC_INTENCLR_CH2LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH2LIMITL @Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ + #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ + #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ + #define SAADC_INTENCLR_CH2LIMITL_Min (0x0UL) /*!< Min enumerator value of CH2LIMITL field. */ + #define SAADC_INTENCLR_CH2LIMITL_Max (0x1UL) /*!< Max enumerator value of CH2LIMITL field. */ + #define SAADC_INTENCLR_CH2LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH3LIMITH @Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ + #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ + #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ + #define SAADC_INTENCLR_CH3LIMITH_Min (0x0UL) /*!< Min enumerator value of CH3LIMITH field. */ + #define SAADC_INTENCLR_CH3LIMITH_Max (0x1UL) /*!< Max enumerator value of CH3LIMITH field. */ + #define SAADC_INTENCLR_CH3LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH3LIMITL @Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ + #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ + #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ + #define SAADC_INTENCLR_CH3LIMITL_Min (0x0UL) /*!< Min enumerator value of CH3LIMITL field. */ + #define SAADC_INTENCLR_CH3LIMITL_Max (0x1UL) /*!< Max enumerator value of CH3LIMITL field. */ + #define SAADC_INTENCLR_CH3LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH4LIMITH @Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ + #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ + #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ + #define SAADC_INTENCLR_CH4LIMITH_Min (0x0UL) /*!< Min enumerator value of CH4LIMITH field. */ + #define SAADC_INTENCLR_CH4LIMITH_Max (0x1UL) /*!< Max enumerator value of CH4LIMITH field. */ + #define SAADC_INTENCLR_CH4LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH4LIMITL @Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ + #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ + #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ + #define SAADC_INTENCLR_CH4LIMITL_Min (0x0UL) /*!< Min enumerator value of CH4LIMITL field. */ + #define SAADC_INTENCLR_CH4LIMITL_Max (0x1UL) /*!< Max enumerator value of CH4LIMITL field. */ + #define SAADC_INTENCLR_CH4LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH5LIMITH @Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ + #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ + #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ + #define SAADC_INTENCLR_CH5LIMITH_Min (0x0UL) /*!< Min enumerator value of CH5LIMITH field. */ + #define SAADC_INTENCLR_CH5LIMITH_Max (0x1UL) /*!< Max enumerator value of CH5LIMITH field. */ + #define SAADC_INTENCLR_CH5LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH5LIMITL @Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ + #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ + #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ + #define SAADC_INTENCLR_CH5LIMITL_Min (0x0UL) /*!< Min enumerator value of CH5LIMITL field. */ + #define SAADC_INTENCLR_CH5LIMITL_Max (0x1UL) /*!< Max enumerator value of CH5LIMITL field. */ + #define SAADC_INTENCLR_CH5LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH6LIMITH @Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ + #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ + #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ + #define SAADC_INTENCLR_CH6LIMITH_Min (0x0UL) /*!< Min enumerator value of CH6LIMITH field. */ + #define SAADC_INTENCLR_CH6LIMITH_Max (0x1UL) /*!< Max enumerator value of CH6LIMITH field. */ + #define SAADC_INTENCLR_CH6LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH6LIMITL @Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ + #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ + #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ + #define SAADC_INTENCLR_CH6LIMITL_Min (0x0UL) /*!< Min enumerator value of CH6LIMITL field. */ + #define SAADC_INTENCLR_CH6LIMITL_Max (0x1UL) /*!< Max enumerator value of CH6LIMITL field. */ + #define SAADC_INTENCLR_CH6LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH7LIMITH @Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ + #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ + #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ + #define SAADC_INTENCLR_CH7LIMITH_Min (0x0UL) /*!< Min enumerator value of CH7LIMITH field. */ + #define SAADC_INTENCLR_CH7LIMITH_Max (0x1UL) /*!< Max enumerator value of CH7LIMITH field. */ + #define SAADC_INTENCLR_CH7LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH7LIMITL @Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ + #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ + #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ + #define SAADC_INTENCLR_CH7LIMITL_Min (0x0UL) /*!< Min enumerator value of CH7LIMITL field. */ + #define SAADC_INTENCLR_CH7LIMITL_Max (0x1UL) /*!< Max enumerator value of CH7LIMITL field. */ + #define SAADC_INTENCLR_CH7LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SAADC_STATUS: Status */ + #define SAADC_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* STATUS @Bit 0 : Status */ + #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define SAADC_STATUS_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define SAADC_STATUS_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define SAADC_STATUS_STATUS_Ready (0x0UL) /*!< ADC is ready. No on-going conversion. */ + #define SAADC_STATUS_STATUS_Busy (0x1UL) /*!< ADC is busy. Conversion is in progress. */ + + +/* SAADC_ENABLE: Enable or disable ADC */ + #define SAADC_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable ADC */ + #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define SAADC_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SAADC_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SAADC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable ADC */ + #define SAADC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable ADC */ + + +/* SAADC_BURST: Enable burst mode */ + #define SAADC_BURST_ResetValue (0x00000000UL) /*!< Reset value of BURST register. */ + +/* BURST @Bit 0 : Enable burst mode */ + #define SAADC_BURST_BURST_Pos (0UL) /*!< Position of BURST field. */ + #define SAADC_BURST_BURST_Msk (0x1UL << SAADC_BURST_BURST_Pos) /*!< Bit mask of BURST field. */ + #define SAADC_BURST_BURST_Min (0x0UL) /*!< Min enumerator value of BURST field. */ + #define SAADC_BURST_BURST_Max (0x1UL) /*!< Max enumerator value of BURST field. */ + #define SAADC_BURST_BURST_Disabled (0x0UL) /*!< Burst mode is disabled (normal operation) */ + #define SAADC_BURST_BURST_Enabled (0x1UL) /*!< Burst mode is enabled. SAADC triggers new samples until RESULTDONE + event for every enabled channel*/ + + +/* SAADC_RESOLUTION: Resolution configuration */ + #define SAADC_RESOLUTION_ResetValue (0x00000001UL) /*!< Reset value of RESOLUTION register. */ + +/* VAL @Bits 0..2 : Set the resolution */ + #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ + #define SAADC_RESOLUTION_VAL_Min (0x0UL) /*!< Min enumerator value of VAL field. */ + #define SAADC_RESOLUTION_VAL_Max (0x3UL) /*!< Max enumerator value of VAL field. */ + #define SAADC_RESOLUTION_VAL_8bit (0x0UL) /*!< 8 bit */ + #define SAADC_RESOLUTION_VAL_10bit (0x1UL) /*!< 10 bit */ + #define SAADC_RESOLUTION_VAL_12bit (0x2UL) /*!< 12 bit */ + #define SAADC_RESOLUTION_VAL_14bit (0x3UL) /*!< 14 bit */ + + +/* SAADC_OVERSAMPLE: Oversampling configuration. OVERSAMPLE should not be combined with SCAN unless burst is enabled. The + RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + + #define SAADC_OVERSAMPLE_ResetValue (0x00000000UL) /*!< Reset value of OVERSAMPLE register. */ + +/* OVERSAMPLE @Bits 0..3 : Oversample control */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Min (0x0UL) /*!< Min enumerator value of OVERSAMPLE field. */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Max (0x8UL) /*!< Max enumerator value of OVERSAMPLE field. */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0x0UL) /*!< Bypass oversampling */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (0x1UL) /*!< Oversample 2x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (0x2UL) /*!< Oversample 4x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (0x3UL) /*!< Oversample 8x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (0x4UL) /*!< Oversample 16x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (0x5UL) /*!< Oversample 32x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (0x6UL) /*!< Oversample 64x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (0x7UL) /*!< Oversample 128x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (0x8UL) /*!< Oversample 256x */ + + +/* SAADC_SAMPLERATE: Configures the sampling rate for either task-triggered or continuous operation using a local timer */ + #define SAADC_SAMPLERATE_ResetValue (0x00000000UL) /*!< Reset value of SAMPLERATE register. */ + +/* CC @Bits 0..10 : Capture and compare value. Sample rate is 16 MHz/CC */ + #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ + #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + #define SAADC_SAMPLERATE_CC_Min (0x008UL) /*!< Min value of CC field. */ + #define SAADC_SAMPLERATE_CC_Max (0x7FFUL) /*!< Max size of CC field. */ + +/* MODE @Bit 12 : Select mode for sample rate control */ + #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ + #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define SAADC_SAMPLERATE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define SAADC_SAMPLERATE_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define SAADC_SAMPLERATE_MODE_Task (0x0UL) /*!< Rate is controlled from SAMPLE task */ + #define SAADC_SAMPLERATE_MODE_Timers (0x1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + + +/* SAADC_NOISESHAPE: SAADC provides two operational noise shaping modes (one that prioritizes higher bandwith, while the other + prioritizes higher accuracy) that allow trade-offs between ADC resolution, power consumption, and signal + bandwidth. */ + + #define SAADC_NOISESHAPE_ResetValue (0x00000000UL) /*!< Reset value of NOISESHAPE register. */ + +/* NOISESHAPE @Bits 0..1 : Noise shaping configuration */ + #define SAADC_NOISESHAPE_NOISESHAPE_Pos (0UL) /*!< Position of NOISESHAPE field. */ + #define SAADC_NOISESHAPE_NOISESHAPE_Msk (0x3UL << SAADC_NOISESHAPE_NOISESHAPE_Pos) /*!< Bit mask of NOISESHAPE field. */ + #define SAADC_NOISESHAPE_NOISESHAPE_Min (0x0UL) /*!< Min enumerator value of NOISESHAPE field. */ + #define SAADC_NOISESHAPE_NOISESHAPE_Max (0x3UL) /*!< Max enumerator value of NOISESHAPE field. */ + #define SAADC_NOISESHAPE_NOISESHAPE_Disable (0x0UL) /*!< Disable noiseshaping. Configurable oversampling. */ + #define SAADC_NOISESHAPE_NOISESHAPE_NS1 (0x1UL) /*!< Noiseshaping and decimating. Larger passband. Decimation ratio 8, 125 + kS/s, with resulting bandwidth around 45 kHz. Takes precedence over + the OVERSAMPLING register.*/ + #define SAADC_NOISESHAPE_NOISESHAPE_NS2 (0x2UL) /*!< Noiseshaping and decimating. Smaller passband. Decimation ratio 32, + 31.25 kS/s, with resulting bandwidth around 7 kHz. Takes precedence + over the OVERSAMPLING register.*/ + #define SAADC_NOISESHAPE_NOISESHAPE_NS3 (0x3UL) /*!< Noise shaping with oversampling set by the OVERSAMPLE register */ + #define SAADC_NOISESHAPE_NOISESHAPE_Audio (0x1UL) /*!< Use enumerator NS1 for future compatibility. */ + #define SAADC_NOISESHAPE_NOISESHAPE_Accuracy (0x2UL) /*!< Use enumerator NS2 for future compatibility. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ SICR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct SICR ======================================================= */ +/** + * @brief Factory Information Configuration Registers + */ + typedef struct { /*!< SICR Structure */ + __IM uint32_t RESERVED; + } NRF_SICR_Type; /*!< Size = 4 (0x004) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ SPIM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct SPIM_TASKS_DMA_RX ================================================= */ +/** + * @brief RX [SPIM_TASKS_DMA_RX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Enables the MATCH[n] event by setting the ENABLE[n] bit + in the CONFIG register.*/ + __OM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Disables the MATCH[n] event by clearing the ENABLE[n] + bit in the CONFIG register.*/ +} NRF_SPIM_TASKS_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* SPIM_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask + of ENABLEMATCH field.*/ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIM_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit + mask of DISABLEMATCH field.*/ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================== Struct SPIM_TASKS_DMA ================================================== */ +/** + * @brief TASKS_DMA [SPIM_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __OM NRF_SPIM_TASKS_DMA_RX_Type RX; /*!< (@ 0x00000008) Peripheral tasks. */ +} NRF_SPIM_TASKS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ============================================== Struct SPIM_SUBSCRIBE_DMA_RX =============================================== */ +/** + * @brief RX [SPIM_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Subscribe configuration for task ENABLEMATCH[n] */ + __IOM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Subscribe configuration for task DISABLEMATCH[n] */ +} NRF_SPIM_SUBSCRIBE_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ================================================ Struct SPIM_SUBSCRIBE_DMA ================================================ */ +/** + * @brief SUBSCRIBE_DMA [SPIM_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IOM NRF_SPIM_SUBSCRIBE_DMA_RX_Type RX; /*!< (@ 0x00000008) Subscribe configuration for tasks */ +} NRF_SPIM_SUBSCRIBE_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ================================================ Struct SPIM_EVENTS_DMA_RX ================================================ */ +/** + * @brief RX [SPIM_EVENTS_DMA_RX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ +} NRF_SPIM_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* SPIM_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ + #define SPIM_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define SPIM_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ + #define SPIM_EVENTS_DMA_RX_END_END_Msk (0x1UL << SPIM_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ + #define SPIM_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIM_EVENTS_DMA_RX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIM_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define SPIM_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define SPIM_EVENTS_DMA_RX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define SPIM_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << SPIM_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define SPIM_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define SPIM_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define SPIM_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define SPIM_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << SPIM_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================ Struct SPIM_EVENTS_DMA_TX ================================================ */ +/** + * @brief TX [SPIM_EVENTS_DMA_TX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_SPIM_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* SPIM_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ + #define SPIM_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define SPIM_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ + #define SPIM_EVENTS_DMA_TX_END_END_Msk (0x1UL << SPIM_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ + #define SPIM_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIM_EVENTS_DMA_TX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIM_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define SPIM_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define SPIM_EVENTS_DMA_TX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define SPIM_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << SPIM_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define SPIM_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define SPIM_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define SPIM_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct SPIM_EVENTS_DMA ================================================== */ +/** + * @brief EVENTS_DMA [SPIM_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_SPIM_EVENTS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral events. */ + __IOM NRF_SPIM_EVENTS_DMA_TX_Type TX; /*!< (@ 0x0000001C) Peripheral events. */ +} NRF_SPIM_EVENTS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* =============================================== Struct SPIM_PUBLISH_DMA_RX ================================================ */ +/** + * @brief RX [SPIM_PUBLISH_DMA_RX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Publish configuration for event MATCH[n] */ +} NRF_SPIM_PUBLISH_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* SPIM_PUBLISH_DMA_RX_END: Publish configuration for event END */ + #define SPIM_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_DMA_RX_READY: Publish configuration for event READY */ + #define SPIM_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */ + #define SPIM_PUBLISH_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */ + #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* =============================================== Struct SPIM_PUBLISH_DMA_TX ================================================ */ +/** + * @brief TX [SPIM_PUBLISH_DMA_TX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_SPIM_PUBLISH_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* SPIM_PUBLISH_DMA_TX_END: Publish configuration for event END */ + #define SPIM_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_DMA_TX_READY: Publish configuration for event READY */ + #define SPIM_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================= Struct SPIM_PUBLISH_DMA ================================================= */ +/** + * @brief PUBLISH_DMA [SPIM_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_SPIM_PUBLISH_DMA_RX_Type RX; /*!< (@ 0x00000000) Publish configuration for events */ + __IOM NRF_SPIM_PUBLISH_DMA_TX_Type TX; /*!< (@ 0x0000001C) Publish configuration for events */ +} NRF_SPIM_PUBLISH_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ================================================== Struct SPIM_IFTIMING =================================================== */ +/** + * @brief IFTIMING [SPIM_IFTIMING] (unspecified) + */ +typedef struct { + __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on SDI */ + __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge of SCK. + When SHORTS.END_START is used, this is also the minimum + duration CSN must stay high between transactions.*/ +} NRF_SPIM_IFTIMING_Type; /*!< Size = 8 (0x008) */ + +/* SPIM_IFTIMING_RXDELAY: Sample delay for input serial data on SDI */ + #define SPIM_IFTIMING_RXDELAY_ResetValue (0x00000002UL) /*!< Reset value of RXDELAY register. */ + +/* RXDELAY @Bits 0..2 : Sample delay for input serial data on SDI. The value specifies the number of SPIM core clock cycles + delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA + = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the + input serial data is sampled on the rising edge of SCK. */ + + #define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */ + #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ + #define SPIM_IFTIMING_RXDELAY_RXDELAY_Min (0x0UL) /*!< Min value of RXDELAY field. */ + #define SPIM_IFTIMING_RXDELAY_RXDELAY_Max (0x7UL) /*!< Max size of RXDELAY field. */ + + +/* SPIM_IFTIMING_CSNDUR: Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the + minimum duration CSN must stay high between transactions. */ + + #define SPIM_IFTIMING_CSNDUR_ResetValue (0x00000002UL) /*!< Reset value of CSNDUR register. */ + +/* CSNDUR @Bits 0..7 : Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum + duration CSN must stay high between transactions. The value is specified in number of SPIM core clock + cycles. */ + + #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */ + #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */ + #define SPIM_IFTIMING_CSNDUR_CSNDUR_Min (0x00UL) /*!< Min value of CSNDUR field. */ + #define SPIM_IFTIMING_CSNDUR_CSNDUR_Max (0xFFUL) /*!< Max size of CSNDUR field. */ + + + +/* ==================================================== Struct SPIM_PSEL ===================================================== */ +/** + * @brief PSEL [SPIM_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for SDO signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for SDI signal */ + __IOM uint32_t DCX; /*!< (@ 0x0000000C) Pin select for DCX signal */ + __IOM uint32_t CSN; /*!< (@ 0x00000010) Pin select for CSN */ +} NRF_SPIM_PSEL_Type; /*!< Size = 20 (0x014) */ + +/* SPIM_PSEL_SCK: Pin select for SCK */ + #define SPIM_PSEL_SCK_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SCK register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIM_PSEL_SCK_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIM_PSEL_SCK_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIM_PSEL_SCK_PORT_Msk (0x7UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIM_PSEL_SCK_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIM_PSEL_SCK_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIM_PSEL_SCK_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIM_PSEL_SCK_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIM_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIM_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIM_PSEL_MOSI: Pin select for SDO signal */ + #define SPIM_PSEL_MOSI_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MOSI register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIM_PSEL_MOSI_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIM_PSEL_MOSI_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIM_PSEL_MOSI_PORT_Msk (0x7UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIM_PSEL_MOSI_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIM_PSEL_MOSI_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIM_PSEL_MOSI_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIM_PSEL_MOSI_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIM_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIM_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIM_PSEL_MISO: Pin select for SDI signal */ + #define SPIM_PSEL_MISO_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MISO register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIM_PSEL_MISO_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIM_PSEL_MISO_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIM_PSEL_MISO_PORT_Msk (0x7UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIM_PSEL_MISO_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIM_PSEL_MISO_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIM_PSEL_MISO_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIM_PSEL_MISO_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIM_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIM_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIM_PSEL_DCX: Pin select for DCX signal */ + #define SPIM_PSEL_DCX_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DCX register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIM_PSEL_DCX_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIM_PSEL_DCX_PIN_Msk (0x1FUL << SPIM_PSEL_DCX_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIM_PSEL_DCX_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIM_PSEL_DCX_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define SPIM_PSEL_DCX_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIM_PSEL_DCX_PORT_Msk (0x7UL << SPIM_PSEL_DCX_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIM_PSEL_DCX_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIM_PSEL_DCX_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIM_PSEL_DCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIM_PSEL_DCX_CONNECT_Msk (0x1UL << SPIM_PSEL_DCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIM_PSEL_DCX_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIM_PSEL_DCX_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIM_PSEL_DCX_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIM_PSEL_DCX_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIM_PSEL_CSN: Pin select for CSN */ + #define SPIM_PSEL_CSN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CSN register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIM_PSEL_CSN_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIM_PSEL_CSN_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIM_PSEL_CSN_PORT_Msk (0x7UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIM_PSEL_CSN_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIM_PSEL_CSN_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIM_PSEL_CSN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIM_PSEL_CSN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIM_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIM_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================ Struct SPIM_DMA_RX_MATCH ================================================= */ +/** + * @brief MATCH [SPIM_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Configure individual match events */ + __IOM uint32_t CANDIDATE[4]; /*!< (@ 0x00000004) The data to look for - any match will trigger the + MATCH[n] event, if enabled.*/ +} NRF_SPIM_DMA_RX_MATCH_Type; /*!< Size = 20 (0x014) */ + +/* SPIM_DMA_RX_MATCH_CONFIG: Configure individual match events */ + #define SPIM_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ENABLE0 @Bit 0 : Enable match filter 0 */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE1 @Bit 1 : Enable match filter 1 */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE2 @Bit 2 : Enable match filter 2 */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE3 @Bit 3 : Enable match filter 3 */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0 + field.*/ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1 + field.*/ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2 + field.*/ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3 + field.*/ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + + +/* SPIM_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array. */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array. */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array. */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register. */ + +/* DATA @Bits 0..31 : Data to look for */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << SPIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA + field.*/ + + + +/* =================================================== Struct SPIM_DMA_RX ==================================================== */ +/** + * @brief RX [SPIM_DMA_RX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ + __IOM NRF_SPIM_DMA_RX_MATCH_Type MATCH; /*!< (@ 0x00000024) Registers to control the behavior of the pattern + matcher engine*/ +} NRF_SPIM_DMA_RX_Type; /*!< Size = 56 (0x038) */ + +/* SPIM_DMA_RX_PTR: RAM buffer start address */ + #define SPIM_DMA_RX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define SPIM_DMA_RX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define SPIM_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* SPIM_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */ + #define SPIM_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define SPIM_DMA_RX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define SPIM_DMA_RX_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define SPIM_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define SPIM_DMA_RX_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ + + +/* SPIM_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define SPIM_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define SPIM_DMA_RX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIM_DMA_RX_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define SPIM_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIM_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIM_DMA_RX_LIST: EasyDMA list type */ + #define SPIM_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIM_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIM_DMA_RX_LIST_TYPE_Msk (0x7UL << SPIM_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIM_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIM_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIM_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIM_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* SPIM_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* SPIM_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define SPIM_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* =================================================== Struct SPIM_DMA_TX ==================================================== */ +/** + * @brief TX [SPIM_DMA_TX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_SPIM_DMA_TX_Type; /*!< Size = 36 (0x024) */ + +/* SPIM_DMA_TX_PTR: RAM buffer start address */ + #define SPIM_DMA_TX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define SPIM_DMA_TX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define SPIM_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* SPIM_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */ + #define SPIM_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define SPIM_DMA_TX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define SPIM_DMA_TX_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define SPIM_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define SPIM_DMA_TX_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ + + +/* SPIM_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define SPIM_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define SPIM_DMA_TX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIM_DMA_TX_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define SPIM_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIM_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIM_DMA_TX_LIST: EasyDMA list type */ + #define SPIM_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIM_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIM_DMA_TX_LIST_TYPE_Msk (0x7UL << SPIM_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIM_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIM_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIM_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIM_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* SPIM_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* SPIM_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define SPIM_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ===================================================== Struct SPIM_DMA ===================================================== */ +/** + * @brief DMA [SPIM_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_SPIM_DMA_RX_Type RX; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_SPIM_DMA_TX_Type TX; /*!< (@ 0x00000038) (unspecified) */ +} NRF_SPIM_DMA_Type; /*!< Size = 92 (0x05C) */ + +/* ======================================================= Struct SPIM ======================================================= */ +/** + * @brief Serial Peripheral Interface Master with EasyDMA + */ + typedef struct { /*!< SPIM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop SPI transaction */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000000C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000010) Resume SPI transaction */ + __IM uint32_t RESERVED1[5]; + __OM NRF_SPIM_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000028) Peripheral tasks. */ + __IM uint32_t RESERVED2[12]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED3; + __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000008C) Subscribe configuration for task SUSPEND */ + __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x00000090) Subscribe configuration for task RESUME */ + __IM uint32_t RESERVED4[5]; + __IOM NRF_SPIM_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks */ + __IM uint32_t RESERVED5[12]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) SPI transaction has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED6[16]; + __IOM NRF_SPIM_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x0000014C) Peripheral events. */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ + __IM uint32_t RESERVED8[16]; + __IOM NRF_SPIM_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001CC) Publish configuration for events */ + __IM uint32_t RESERVED9[3]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED10[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED11[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED12[10]; + __IOM uint32_t PRESCALER; /*!< (@ 0x0000052C) The prescaler is used to set the SPI frequency. */ + __IM uint32_t RESERVED13[9]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED14[21]; + __IOM NRF_SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x000005AC) (unspecified) */ + __IOM uint32_t DCXCNT; /*!< (@ 0x000005B4) DCX configuration */ + __IOM uint32_t CSNPOL; /*!< (@ 0x000005B8) Polarity of CSN output */ + __IM uint32_t RESERVED15; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have been + transmitted in the case when RXD.MAXCNT is greater than + TXD.MAXCNT*/ + __IM uint32_t RESERVED16[15]; + __IOM NRF_SPIM_PSEL_Type PSEL; /*!< (@ 0x00000600) (unspecified) */ + __IM uint32_t RESERVED17[59]; + __IOM NRF_SPIM_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_SPIM_Type; /*!< Size = 1884 (0x75C) */ + +/* SPIM_TASKS_START: Start SPI transaction */ + #define SPIM_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start SPI transaction */ + #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define SPIM_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define SPIM_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define SPIM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIM_TASKS_STOP: Stop SPI transaction */ + #define SPIM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop SPI transaction */ + #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define SPIM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define SPIM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIM_TASKS_SUSPEND: Suspend SPI transaction */ + #define SPIM_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register. */ + +/* TASKS_SUSPEND @Bit 0 : Suspend SPI transaction */ + #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ + #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND + field.*/ + #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field. */ + #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field. */ + #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIM_TASKS_RESUME: Resume SPI transaction */ + #define SPIM_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register. */ + +/* TASKS_RESUME @Bit 0 : Resume SPI transaction */ + #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ + #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/ + #define SPIM_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field. */ + #define SPIM_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field. */ + #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIM_SUBSCRIBE_START: Subscribe configuration for task START */ + #define SPIM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define SPIM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIM_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */ + #define SPIM_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */ + #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIM_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */ + #define SPIM_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */ + #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_SUBSCRIBE_RESUME_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_SUBSCRIBE_RESUME_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_RESUME_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIM_EVENTS_STARTED: SPI transaction has started */ + #define SPIM_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register. */ + +/* EVENTS_STARTED @Bit 0 : SPI transaction has started */ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of + EVENTS_STARTED field.*/ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field. */ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field. */ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_STOPPED: SPI transaction has stopped */ + #define SPIM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : SPI transaction has stopped */ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_END: End of RXD buffer and TXD buffer reached */ + #define SPIM_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : End of RXD buffer and TXD buffer reached */ + #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define SPIM_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define SPIM_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_PUBLISH_STARTED: Publish configuration for event STARTED */ + #define SPIM_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */ + #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_STARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_STARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_STARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_STARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define SPIM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_END: Publish configuration for event END */ + #define SPIM_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_SHORTS: Shortcuts between local events and tasks */ + #define SPIM_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* END_START @Bit 17 : Shortcut between event END and task START */ + #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ + #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ + #define SPIM_SHORTS_END_START_Min (0x0UL) /*!< Min enumerator value of END_START field. */ + #define SPIM_SHORTS_END_START_Max (0x1UL) /*!< Max enumerator value of END_START field. */ + #define SPIM_SHORTS_END_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_END_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows + daisy-chaining match events. */ + + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows + daisy-chaining match events. */ + + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows + daisy-chaining match events. */ + + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows + daisy-chaining match events. */ + + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[0] and task DMA.RX.DISABLEMATCH[0] */ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[1] and task DMA.RX.DISABLEMATCH[1] */ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[2] and task DMA.RX.DISABLEMATCH[2] */ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[3] and task DMA.RX.DISABLEMATCH[3] */ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* SPIM_INTENSET: Enable interrupt */ + #define SPIM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */ + #define SPIM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define SPIM_INTENSET_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define SPIM_INTENSET_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define SPIM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define SPIM_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define SPIM_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define SPIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 2 : Write '1' to enable interrupt for event END */ + #define SPIM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ + #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define SPIM_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIM_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIM_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */ + #define SPIM_INTENSET_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define SPIM_INTENSET_DMARXEND_Msk (0x1UL << SPIM_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define SPIM_INTENSET_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define SPIM_INTENSET_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define SPIM_INTENSET_DMARXEND_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */ + #define SPIM_INTENSET_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define SPIM_INTENSET_DMARXREADY_Msk (0x1UL << SPIM_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define SPIM_INTENSET_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define SPIM_INTENSET_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define SPIM_INTENSET_DMARXREADY_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */ + #define SPIM_INTENSET_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define SPIM_INTENSET_DMARXBUSERROR_Msk (0x1UL << SPIM_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define SPIM_INTENSET_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define SPIM_INTENSET_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define SPIM_INTENSET_DMARXBUSERROR_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */ + #define SPIM_INTENSET_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define SPIM_INTENSET_DMARXMATCH0_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define SPIM_INTENSET_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define SPIM_INTENSET_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define SPIM_INTENSET_DMARXMATCH0_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */ + #define SPIM_INTENSET_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define SPIM_INTENSET_DMARXMATCH1_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define SPIM_INTENSET_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define SPIM_INTENSET_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define SPIM_INTENSET_DMARXMATCH1_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */ + #define SPIM_INTENSET_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define SPIM_INTENSET_DMARXMATCH2_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define SPIM_INTENSET_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define SPIM_INTENSET_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define SPIM_INTENSET_DMARXMATCH2_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */ + #define SPIM_INTENSET_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define SPIM_INTENSET_DMARXMATCH3_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define SPIM_INTENSET_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define SPIM_INTENSET_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define SPIM_INTENSET_DMARXMATCH3_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */ + #define SPIM_INTENSET_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define SPIM_INTENSET_DMATXEND_Msk (0x1UL << SPIM_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define SPIM_INTENSET_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define SPIM_INTENSET_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define SPIM_INTENSET_DMATXEND_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */ + #define SPIM_INTENSET_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define SPIM_INTENSET_DMATXREADY_Msk (0x1UL << SPIM_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define SPIM_INTENSET_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define SPIM_INTENSET_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define SPIM_INTENSET_DMATXREADY_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */ + #define SPIM_INTENSET_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define SPIM_INTENSET_DMATXBUSERROR_Msk (0x1UL << SPIM_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define SPIM_INTENSET_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define SPIM_INTENSET_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define SPIM_INTENSET_DMATXBUSERROR_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPIM_INTENCLR: Disable interrupt */ + #define SPIM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */ + #define SPIM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define SPIM_INTENCLR_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define SPIM_INTENCLR_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define SPIM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define SPIM_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define SPIM_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define SPIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 2 : Write '1' to disable interrupt for event END */ + #define SPIM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ + #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define SPIM_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIM_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIM_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */ + #define SPIM_INTENCLR_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define SPIM_INTENCLR_DMARXEND_Msk (0x1UL << SPIM_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define SPIM_INTENCLR_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define SPIM_INTENCLR_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define SPIM_INTENCLR_DMARXEND_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */ + #define SPIM_INTENCLR_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define SPIM_INTENCLR_DMARXREADY_Msk (0x1UL << SPIM_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define SPIM_INTENCLR_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define SPIM_INTENCLR_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define SPIM_INTENCLR_DMARXREADY_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */ + #define SPIM_INTENCLR_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define SPIM_INTENCLR_DMARXBUSERROR_Msk (0x1UL << SPIM_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define SPIM_INTENCLR_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define SPIM_INTENCLR_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define SPIM_INTENCLR_DMARXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */ + #define SPIM_INTENCLR_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define SPIM_INTENCLR_DMARXMATCH0_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define SPIM_INTENCLR_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define SPIM_INTENCLR_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define SPIM_INTENCLR_DMARXMATCH0_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */ + #define SPIM_INTENCLR_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define SPIM_INTENCLR_DMARXMATCH1_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define SPIM_INTENCLR_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define SPIM_INTENCLR_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define SPIM_INTENCLR_DMARXMATCH1_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */ + #define SPIM_INTENCLR_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define SPIM_INTENCLR_DMARXMATCH2_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define SPIM_INTENCLR_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define SPIM_INTENCLR_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define SPIM_INTENCLR_DMARXMATCH2_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */ + #define SPIM_INTENCLR_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define SPIM_INTENCLR_DMARXMATCH3_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define SPIM_INTENCLR_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define SPIM_INTENCLR_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define SPIM_INTENCLR_DMARXMATCH3_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */ + #define SPIM_INTENCLR_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define SPIM_INTENCLR_DMATXEND_Msk (0x1UL << SPIM_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define SPIM_INTENCLR_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define SPIM_INTENCLR_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define SPIM_INTENCLR_DMATXEND_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */ + #define SPIM_INTENCLR_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define SPIM_INTENCLR_DMATXREADY_Msk (0x1UL << SPIM_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define SPIM_INTENCLR_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define SPIM_INTENCLR_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define SPIM_INTENCLR_DMATXREADY_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */ + #define SPIM_INTENCLR_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define SPIM_INTENCLR_DMATXBUSERROR_Msk (0x1UL << SPIM_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define SPIM_INTENCLR_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define SPIM_INTENCLR_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define SPIM_INTENCLR_DMATXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPIM_ENABLE: Enable SPIM */ + #define SPIM_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..3 : Enable or disable SPIM */ + #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define SPIM_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIM_ENABLE_ENABLE_Max (0x7UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPIM */ + #define SPIM_ENABLE_ENABLE_Enabled (0x7UL) /*!< Enable SPIM */ + + +/* SPIM_PRESCALER: The prescaler is used to set the SPI frequency. */ + #define SPIM_PRESCALER_ResetValue (0x00000040UL) /*!< Reset value of PRESCALER register. */ + +/* DIVISOR @Bits 0..6 : Core clock to SCK divisor */ + #define SPIM_PRESCALER_DIVISOR_Pos (0UL) /*!< Position of DIVISOR field. */ + #define SPIM_PRESCALER_DIVISOR_Msk (0x7FUL << SPIM_PRESCALER_DIVISOR_Pos) /*!< Bit mask of DIVISOR field. */ + #define SPIM_PRESCALER_DIVISOR_Min (0x02UL) /*!< Min value of DIVISOR field. */ + #define SPIM_PRESCALER_DIVISOR_Max (0x7EUL) /*!< Max size of DIVISOR field. */ + + +/* SPIM_CONFIG: Configuration register */ + #define SPIM_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ORDER @Bit 0 : Bit order */ + #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ + #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ + #define SPIM_CONFIG_ORDER_Min (0x0UL) /*!< Min enumerator value of ORDER field. */ + #define SPIM_CONFIG_ORDER_Max (0x1UL) /*!< Max enumerator value of ORDER field. */ + #define SPIM_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */ + #define SPIM_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */ + +/* CPHA @Bit 1 : Serial clock (SCK) phase */ + #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ + #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ + #define SPIM_CONFIG_CPHA_Min (0x0UL) /*!< Min enumerator value of CPHA field. */ + #define SPIM_CONFIG_CPHA_Max (0x1UL) /*!< Max enumerator value of CPHA field. */ + #define SPIM_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ + #define SPIM_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* CPOL @Bit 2 : Serial clock (SCK) polarity */ + #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ + #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ + #define SPIM_CONFIG_CPOL_Min (0x0UL) /*!< Min enumerator value of CPOL field. */ + #define SPIM_CONFIG_CPOL_Max (0x1UL) /*!< Max enumerator value of CPOL field. */ + #define SPIM_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */ + #define SPIM_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */ + + +/* SPIM_DCXCNT: DCX configuration */ + #define SPIM_DCXCNT_ResetValue (0x00000000UL) /*!< Reset value of DCXCNT register. */ + +/* DCXCNT @Bits 0..3 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be + low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates + that all bytes are command bytes. */ + + #define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */ + #define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */ + #define SPIM_DCXCNT_DCXCNT_Min (0x0UL) /*!< Min value of DCXCNT field. */ + #define SPIM_DCXCNT_DCXCNT_Max (0xFUL) /*!< Max size of DCXCNT field. */ + + +/* SPIM_CSNPOL: Polarity of CSN output */ + #define SPIM_CSNPOL_ResetValue (0x00000000UL) /*!< Reset value of CSNPOL register. */ + +/* CSNPOL0 @Bit 0 : Polarity of CSN output */ + #define SPIM_CSNPOL_CSNPOL0_Pos (0UL) /*!< Position of CSNPOL0 field. */ + #define SPIM_CSNPOL_CSNPOL0_Msk (0x1UL << SPIM_CSNPOL_CSNPOL0_Pos) /*!< Bit mask of CSNPOL0 field. */ + #define SPIM_CSNPOL_CSNPOL0_Min (0x0UL) /*!< Min enumerator value of CSNPOL0 field. */ + #define SPIM_CSNPOL_CSNPOL0_Max (0x1UL) /*!< Max enumerator value of CSNPOL0 field. */ + #define SPIM_CSNPOL_CSNPOL0_LOW (0x0UL) /*!< Active low (idle state high) */ + #define SPIM_CSNPOL_CSNPOL0_HIGH (0x1UL) /*!< Active high (idle state low) */ + + +/* SPIM_ORC: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than + TXD.MAXCNT */ + + #define SPIM_ORC_ResetValue (0x00000000UL) /*!< Reset value of ORC register. */ + +/* ORC @Bits 0..7 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than + TXD.MAXCNT. */ + + #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ + #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ SPIS ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct SPIS_TASKS_DMA_RX ================================================= */ +/** + * @brief RX [SPIS_TASKS_DMA_RX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Enables the MATCH[n] event by setting the ENABLE[n] bit + in the CONFIG register.*/ + __OM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Disables the MATCH[n] event by clearing the ENABLE[n] + bit in the CONFIG register.*/ +} NRF_SPIS_TASKS_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* SPIS_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask + of ENABLEMATCH field.*/ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIS_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit + mask of DISABLEMATCH field.*/ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================== Struct SPIS_TASKS_DMA ================================================== */ +/** + * @brief TASKS_DMA [SPIS_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __OM NRF_SPIS_TASKS_DMA_RX_Type RX; /*!< (@ 0x00000008) Peripheral tasks. */ +} NRF_SPIS_TASKS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ============================================== Struct SPIS_SUBSCRIBE_DMA_RX =============================================== */ +/** + * @brief RX [SPIS_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Subscribe configuration for task ENABLEMATCH[n] */ + __IOM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Subscribe configuration for task DISABLEMATCH[n] */ +} NRF_SPIS_SUBSCRIBE_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ================================================ Struct SPIS_SUBSCRIBE_DMA ================================================ */ +/** + * @brief SUBSCRIBE_DMA [SPIS_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IOM NRF_SPIS_SUBSCRIBE_DMA_RX_Type RX; /*!< (@ 0x00000008) Subscribe configuration for tasks */ +} NRF_SPIS_SUBSCRIBE_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ================================================ Struct SPIS_EVENTS_DMA_RX ================================================ */ +/** + * @brief RX [SPIS_EVENTS_DMA_RX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ +} NRF_SPIS_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* SPIS_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ + #define SPIS_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define SPIS_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ + #define SPIS_EVENTS_DMA_RX_END_END_Msk (0x1UL << SPIS_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ + #define SPIS_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIS_EVENTS_DMA_RX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIS_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define SPIS_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define SPIS_EVENTS_DMA_RX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define SPIS_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << SPIS_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define SPIS_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define SPIS_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define SPIS_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define SPIS_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << SPIS_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================ Struct SPIS_EVENTS_DMA_TX ================================================ */ +/** + * @brief TX [SPIS_EVENTS_DMA_TX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_SPIS_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* SPIS_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ + #define SPIS_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define SPIS_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ + #define SPIS_EVENTS_DMA_TX_END_END_Msk (0x1UL << SPIS_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ + #define SPIS_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIS_EVENTS_DMA_TX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIS_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define SPIS_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define SPIS_EVENTS_DMA_TX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define SPIS_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << SPIS_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define SPIS_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define SPIS_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define SPIS_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct SPIS_EVENTS_DMA ================================================== */ +/** + * @brief EVENTS_DMA [SPIS_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_SPIS_EVENTS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral events. */ + __IOM NRF_SPIS_EVENTS_DMA_TX_Type TX; /*!< (@ 0x0000001C) Peripheral events. */ +} NRF_SPIS_EVENTS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* =============================================== Struct SPIS_PUBLISH_DMA_RX ================================================ */ +/** + * @brief RX [SPIS_PUBLISH_DMA_RX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Publish configuration for event MATCH[n] */ +} NRF_SPIS_PUBLISH_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* SPIS_PUBLISH_DMA_RX_END: Publish configuration for event END */ + #define SPIS_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_DMA_RX_READY: Publish configuration for event READY */ + #define SPIS_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */ + #define SPIS_PUBLISH_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */ + #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* =============================================== Struct SPIS_PUBLISH_DMA_TX ================================================ */ +/** + * @brief TX [SPIS_PUBLISH_DMA_TX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_SPIS_PUBLISH_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* SPIS_PUBLISH_DMA_TX_END: Publish configuration for event END */ + #define SPIS_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_DMA_TX_READY: Publish configuration for event READY */ + #define SPIS_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================= Struct SPIS_PUBLISH_DMA ================================================= */ +/** + * @brief PUBLISH_DMA [SPIS_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_SPIS_PUBLISH_DMA_RX_Type RX; /*!< (@ 0x00000000) Publish configuration for events */ + __IOM NRF_SPIS_PUBLISH_DMA_TX_Type TX; /*!< (@ 0x0000001C) Publish configuration for events */ +} NRF_SPIS_PUBLISH_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ==================================================== Struct SPIS_PSEL ===================================================== */ +/** + * @brief PSEL [SPIS_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for SDO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for SDI signal */ + __IM uint32_t RESERVED; + __IOM uint32_t CSN; /*!< (@ 0x00000010) Pin select for CSN signal */ +} NRF_SPIS_PSEL_Type; /*!< Size = 20 (0x014) */ + +/* SPIS_PSEL_SCK: Pin select for SCK */ + #define SPIS_PSEL_SCK_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SCK register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIS_PSEL_SCK_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIS_PSEL_SCK_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIS_PSEL_SCK_PORT_Msk (0x7UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIS_PSEL_SCK_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIS_PSEL_SCK_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIS_PSEL_SCK_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIS_PSEL_SCK_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIS_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIS_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIS_PSEL_MISO: Pin select for SDO signal */ + #define SPIS_PSEL_MISO_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MISO register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIS_PSEL_MISO_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIS_PSEL_MISO_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIS_PSEL_MISO_PORT_Msk (0x7UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIS_PSEL_MISO_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIS_PSEL_MISO_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIS_PSEL_MISO_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIS_PSEL_MISO_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIS_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIS_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIS_PSEL_MOSI: Pin select for SDI signal */ + #define SPIS_PSEL_MOSI_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MOSI register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIS_PSEL_MOSI_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIS_PSEL_MOSI_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIS_PSEL_MOSI_PORT_Msk (0x7UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIS_PSEL_MOSI_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIS_PSEL_MOSI_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIS_PSEL_MOSI_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIS_PSEL_MOSI_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIS_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIS_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIS_PSEL_CSN: Pin select for CSN signal */ + #define SPIS_PSEL_CSN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CSN register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIS_PSEL_CSN_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIS_PSEL_CSN_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIS_PSEL_CSN_PORT_Msk (0x7UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIS_PSEL_CSN_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIS_PSEL_CSN_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIS_PSEL_CSN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIS_PSEL_CSN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIS_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIS_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================ Struct SPIS_DMA_RX_MATCH ================================================= */ +/** + * @brief MATCH [SPIS_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Configure individual match events */ + __IOM uint32_t CANDIDATE[4]; /*!< (@ 0x00000004) The data to look for - any match will trigger the + MATCH[n] event, if enabled.*/ +} NRF_SPIS_DMA_RX_MATCH_Type; /*!< Size = 20 (0x014) */ + +/* SPIS_DMA_RX_MATCH_CONFIG: Configure individual match events */ + #define SPIS_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ENABLE0 @Bit 0 : Enable match filter 0 */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE1 @Bit 1 : Enable match filter 1 */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE2 @Bit 2 : Enable match filter 2 */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE3 @Bit 3 : Enable match filter 3 */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0 + field.*/ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1 + field.*/ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2 + field.*/ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3 + field.*/ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + + +/* SPIS_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array. */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array. */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array. */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register. */ + +/* DATA @Bits 0..31 : Data to look for */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << SPIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA + field.*/ + + + +/* =================================================== Struct SPIS_DMA_RX ==================================================== */ +/** + * @brief RX [SPIS_DMA_RX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ + __IOM NRF_SPIS_DMA_RX_MATCH_Type MATCH; /*!< (@ 0x00000024) Registers to control the behavior of the pattern + matcher engine*/ +} NRF_SPIS_DMA_RX_Type; /*!< Size = 56 (0x038) */ + +/* SPIS_DMA_RX_PTR: RAM buffer start address */ + #define SPIS_DMA_RX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define SPIS_DMA_RX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define SPIS_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* SPIS_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */ + #define SPIS_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define SPIS_DMA_RX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define SPIS_DMA_RX_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define SPIS_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define SPIS_DMA_RX_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ + + +/* SPIS_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define SPIS_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define SPIS_DMA_RX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIS_DMA_RX_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define SPIS_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIS_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIS_DMA_RX_LIST: EasyDMA list type */ + #define SPIS_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIS_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Msk (0x7UL << SPIS_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIS_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* SPIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* SPIS_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define SPIS_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* =================================================== Struct SPIS_DMA_TX ==================================================== */ +/** + * @brief TX [SPIS_DMA_TX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_SPIS_DMA_TX_Type; /*!< Size = 36 (0x024) */ + +/* SPIS_DMA_TX_PTR: RAM buffer start address */ + #define SPIS_DMA_TX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define SPIS_DMA_TX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define SPIS_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* SPIS_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */ + #define SPIS_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define SPIS_DMA_TX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define SPIS_DMA_TX_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define SPIS_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define SPIS_DMA_TX_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ + + +/* SPIS_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define SPIS_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define SPIS_DMA_TX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIS_DMA_TX_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define SPIS_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIS_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIS_DMA_TX_LIST: EasyDMA list type */ + #define SPIS_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIS_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Msk (0x7UL << SPIS_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIS_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* SPIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* SPIS_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define SPIS_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ===================================================== Struct SPIS_DMA ===================================================== */ +/** + * @brief DMA [SPIS_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_SPIS_DMA_RX_Type RX; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_SPIS_DMA_TX_Type TX; /*!< (@ 0x00000038) (unspecified) */ +} NRF_SPIS_DMA_Type; /*!< Size = 92 (0x05C) */ + +/* ======================================================= Struct SPIS ======================================================= */ +/** + * @brief SPI Slave + */ + typedef struct { /*!< SPIS Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000014) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000018) Release SPI semaphore, enabling the SPI slave to + acquire it*/ + __IM uint32_t RESERVED1[3]; + __OM NRF_SPIS_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000028) Peripheral tasks. */ + __IM uint32_t RESERVED2[17]; + __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x00000094) Subscribe configuration for task ACQUIRE */ + __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x00000098) Subscribe configuration for task RELEASE */ + __IM uint32_t RESERVED3[3]; + __IOM NRF_SPIS_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks */ + __IM uint32_t RESERVED4[13]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED5[4]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000118) Semaphore acquired */ + __IM uint32_t RESERVED6[12]; + __IOM NRF_SPIS_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x0000014C) Peripheral events. */ + __IM uint32_t RESERVED7[4]; + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ + __IM uint32_t RESERVED8[4]; + __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x00000198) Publish configuration for event ACQUIRED */ + __IM uint32_t RESERVED9[12]; + __IOM NRF_SPIS_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001CC) Publish configuration for events */ + __IM uint32_t RESERVED10[3]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED11[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED12[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED13[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED14[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED15[20]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED16; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case of an + ignored transaction.*/ + __IM uint32_t RESERVED17[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ + __IM uint32_t RESERVED18[15]; + __IOM NRF_SPIS_PSEL_Type PSEL; /*!< (@ 0x00000600) (unspecified) */ + __IM uint32_t RESERVED19[59]; + __IOM NRF_SPIS_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_SPIS_Type; /*!< Size = 1884 (0x75C) */ + +/* SPIS_TASKS_ACQUIRE: Acquire SPI semaphore */ + #define SPIS_TASKS_ACQUIRE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ACQUIRE register. */ + +/* TASKS_ACQUIRE @Bit 0 : Acquire SPI semaphore */ + #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ + #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE + field.*/ + #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Min (0x1UL) /*!< Min enumerator value of TASKS_ACQUIRE field. */ + #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Max (0x1UL) /*!< Max enumerator value of TASKS_ACQUIRE field. */ + #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIS_TASKS_RELEASE: Release SPI semaphore, enabling the SPI slave to acquire it */ + #define SPIS_TASKS_RELEASE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RELEASE register. */ + +/* TASKS_RELEASE @Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ + #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ + #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE + field.*/ + #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Min (0x1UL) /*!< Min enumerator value of TASKS_RELEASE field. */ + #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Max (0x1UL) /*!< Max enumerator value of TASKS_RELEASE field. */ + #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIS_SUBSCRIBE_ACQUIRE: Subscribe configuration for task ACQUIRE */ + #define SPIS_SUBSCRIBE_ACQUIRE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ACQUIRE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ACQUIRE will subscribe to */ + #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIS_SUBSCRIBE_RELEASE: Subscribe configuration for task RELEASE */ + #define SPIS_SUBSCRIBE_RELEASE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RELEASE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RELEASE will subscribe to */ + #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIS_EVENTS_END: Granted transaction completed */ + #define SPIS_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : Granted transaction completed */ + #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define SPIS_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define SPIS_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_ACQUIRED: Semaphore acquired */ + #define SPIS_EVENTS_ACQUIRED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ACQUIRED register. */ + +/* EVENTS_ACQUIRED @Bit 0 : Semaphore acquired */ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of + EVENTS_ACQUIRED field.*/ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Min (0x0UL) /*!< Min enumerator value of EVENTS_ACQUIRED field. */ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Max (0x1UL) /*!< Max enumerator value of EVENTS_ACQUIRED field. */ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_PUBLISH_END: Publish configuration for event END */ + #define SPIS_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_ACQUIRED: Publish configuration for event ACQUIRED */ + #define SPIS_PUBLISH_ACQUIRED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ACQUIRED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ACQUIRED will publish to */ + #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_ACQUIRED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_ACQUIRED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_ACQUIRED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_ACQUIRED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_SHORTS: Shortcuts between local events and tasks */ + #define SPIS_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* END_ACQUIRE @Bit 2 : Shortcut between event END and task ACQUIRE */ + #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ + #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ + #define SPIS_SHORTS_END_ACQUIRE_Min (0x0UL) /*!< Min enumerator value of END_ACQUIRE field. */ + #define SPIS_SHORTS_END_ACQUIRE_Max (0x1UL) /*!< Max enumerator value of END_ACQUIRE field. */ + #define SPIS_SHORTS_END_ACQUIRE_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_END_ACQUIRE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows + daisy-chaining match events. */ + + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows + daisy-chaining match events. */ + + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows + daisy-chaining match events. */ + + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows + daisy-chaining match events. */ + + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* SPIS_INTENSET: Enable interrupt */ + #define SPIS_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* END @Bit 1 : Write '1' to enable interrupt for event END */ + #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ + #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define SPIS_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIS_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIS_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ACQUIRED @Bit 6 : Write '1' to enable interrupt for event ACQUIRED */ + #define SPIS_INTENSET_ACQUIRED_Pos (6UL) /*!< Position of ACQUIRED field. */ + #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ + #define SPIS_INTENSET_ACQUIRED_Min (0x0UL) /*!< Min enumerator value of ACQUIRED field. */ + #define SPIS_INTENSET_ACQUIRED_Max (0x1UL) /*!< Max enumerator value of ACQUIRED field. */ + #define SPIS_INTENSET_ACQUIRED_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */ + #define SPIS_INTENSET_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define SPIS_INTENSET_DMARXEND_Msk (0x1UL << SPIS_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define SPIS_INTENSET_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define SPIS_INTENSET_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define SPIS_INTENSET_DMARXEND_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */ + #define SPIS_INTENSET_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define SPIS_INTENSET_DMARXREADY_Msk (0x1UL << SPIS_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define SPIS_INTENSET_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define SPIS_INTENSET_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define SPIS_INTENSET_DMARXREADY_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */ + #define SPIS_INTENSET_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define SPIS_INTENSET_DMARXBUSERROR_Msk (0x1UL << SPIS_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define SPIS_INTENSET_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define SPIS_INTENSET_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define SPIS_INTENSET_DMARXBUSERROR_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */ + #define SPIS_INTENSET_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define SPIS_INTENSET_DMARXMATCH0_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define SPIS_INTENSET_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define SPIS_INTENSET_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define SPIS_INTENSET_DMARXMATCH0_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */ + #define SPIS_INTENSET_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define SPIS_INTENSET_DMARXMATCH1_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define SPIS_INTENSET_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define SPIS_INTENSET_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define SPIS_INTENSET_DMARXMATCH1_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */ + #define SPIS_INTENSET_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define SPIS_INTENSET_DMARXMATCH2_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define SPIS_INTENSET_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define SPIS_INTENSET_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define SPIS_INTENSET_DMARXMATCH2_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */ + #define SPIS_INTENSET_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define SPIS_INTENSET_DMARXMATCH3_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define SPIS_INTENSET_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define SPIS_INTENSET_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define SPIS_INTENSET_DMARXMATCH3_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */ + #define SPIS_INTENSET_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define SPIS_INTENSET_DMATXEND_Msk (0x1UL << SPIS_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define SPIS_INTENSET_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define SPIS_INTENSET_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define SPIS_INTENSET_DMATXEND_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */ + #define SPIS_INTENSET_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define SPIS_INTENSET_DMATXREADY_Msk (0x1UL << SPIS_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define SPIS_INTENSET_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define SPIS_INTENSET_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define SPIS_INTENSET_DMATXREADY_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */ + #define SPIS_INTENSET_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define SPIS_INTENSET_DMATXBUSERROR_Msk (0x1UL << SPIS_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define SPIS_INTENSET_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define SPIS_INTENSET_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define SPIS_INTENSET_DMATXBUSERROR_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPIS_INTENCLR: Disable interrupt */ + #define SPIS_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* END @Bit 1 : Write '1' to disable interrupt for event END */ + #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ + #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define SPIS_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIS_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIS_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ACQUIRED @Bit 6 : Write '1' to disable interrupt for event ACQUIRED */ + #define SPIS_INTENCLR_ACQUIRED_Pos (6UL) /*!< Position of ACQUIRED field. */ + #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ + #define SPIS_INTENCLR_ACQUIRED_Min (0x0UL) /*!< Min enumerator value of ACQUIRED field. */ + #define SPIS_INTENCLR_ACQUIRED_Max (0x1UL) /*!< Max enumerator value of ACQUIRED field. */ + #define SPIS_INTENCLR_ACQUIRED_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */ + #define SPIS_INTENCLR_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define SPIS_INTENCLR_DMARXEND_Msk (0x1UL << SPIS_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define SPIS_INTENCLR_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define SPIS_INTENCLR_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define SPIS_INTENCLR_DMARXEND_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */ + #define SPIS_INTENCLR_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define SPIS_INTENCLR_DMARXREADY_Msk (0x1UL << SPIS_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define SPIS_INTENCLR_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define SPIS_INTENCLR_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define SPIS_INTENCLR_DMARXREADY_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */ + #define SPIS_INTENCLR_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define SPIS_INTENCLR_DMARXBUSERROR_Msk (0x1UL << SPIS_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define SPIS_INTENCLR_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define SPIS_INTENCLR_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define SPIS_INTENCLR_DMARXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */ + #define SPIS_INTENCLR_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define SPIS_INTENCLR_DMARXMATCH0_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define SPIS_INTENCLR_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define SPIS_INTENCLR_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define SPIS_INTENCLR_DMARXMATCH0_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */ + #define SPIS_INTENCLR_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define SPIS_INTENCLR_DMARXMATCH1_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define SPIS_INTENCLR_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define SPIS_INTENCLR_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define SPIS_INTENCLR_DMARXMATCH1_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */ + #define SPIS_INTENCLR_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define SPIS_INTENCLR_DMARXMATCH2_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define SPIS_INTENCLR_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define SPIS_INTENCLR_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define SPIS_INTENCLR_DMARXMATCH2_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */ + #define SPIS_INTENCLR_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define SPIS_INTENCLR_DMARXMATCH3_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define SPIS_INTENCLR_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define SPIS_INTENCLR_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define SPIS_INTENCLR_DMARXMATCH3_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */ + #define SPIS_INTENCLR_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define SPIS_INTENCLR_DMATXEND_Msk (0x1UL << SPIS_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define SPIS_INTENCLR_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define SPIS_INTENCLR_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define SPIS_INTENCLR_DMATXEND_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */ + #define SPIS_INTENCLR_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define SPIS_INTENCLR_DMATXREADY_Msk (0x1UL << SPIS_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define SPIS_INTENCLR_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define SPIS_INTENCLR_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define SPIS_INTENCLR_DMATXREADY_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */ + #define SPIS_INTENCLR_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define SPIS_INTENCLR_DMATXBUSERROR_Msk (0x1UL << SPIS_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define SPIS_INTENCLR_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define SPIS_INTENCLR_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define SPIS_INTENCLR_DMATXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPIS_SEMSTAT: Semaphore status register */ + #define SPIS_SEMSTAT_ResetValue (0x00000001UL) /*!< Reset value of SEMSTAT register. */ + +/* SEMSTAT @Bits 0..1 : Semaphore status */ + #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ + #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ + #define SPIS_SEMSTAT_SEMSTAT_Min (0x0UL) /*!< Min enumerator value of SEMSTAT field. */ + #define SPIS_SEMSTAT_SEMSTAT_Max (0x3UL) /*!< Max enumerator value of SEMSTAT field. */ + #define SPIS_SEMSTAT_SEMSTAT_Free (0x0UL) /*!< Semaphore is free */ + #define SPIS_SEMSTAT_SEMSTAT_CPU (0x1UL) /*!< Semaphore is assigned to CPU */ + #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x2UL) /*!< Semaphore is assigned to SPI slave */ + #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + + +/* SPIS_STATUS: Status from last transaction */ + #define SPIS_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* OVERREAD @Bit 0 : TX buffer over-read detected, and prevented */ + #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ + #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ + #define SPIS_STATUS_OVERREAD_Min (0x0UL) /*!< Min enumerator value of OVERREAD field. */ + #define SPIS_STATUS_OVERREAD_Max (0x1UL) /*!< Max enumerator value of OVERREAD field. */ + #define SPIS_STATUS_OVERREAD_NotPresent (0x0UL) /*!< Read: error not present */ + #define SPIS_STATUS_OVERREAD_Present (0x1UL) /*!< Read: error present */ + #define SPIS_STATUS_OVERREAD_Clear (0x1UL) /*!< Write: clear error on writing '1' */ + +/* OVERFLOW @Bit 1 : RX buffer overflow detected, and prevented */ + #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ + #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ + #define SPIS_STATUS_OVERFLOW_Min (0x0UL) /*!< Min enumerator value of OVERFLOW field. */ + #define SPIS_STATUS_OVERFLOW_Max (0x1UL) /*!< Max enumerator value of OVERFLOW field. */ + #define SPIS_STATUS_OVERFLOW_NotPresent (0x0UL) /*!< Read: error not present */ + #define SPIS_STATUS_OVERFLOW_Present (0x1UL) /*!< Read: error present */ + #define SPIS_STATUS_OVERFLOW_Clear (0x1UL) /*!< Write: clear error on writing '1' */ + + +/* SPIS_ENABLE: Enable SPI slave */ + #define SPIS_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..3 : Enable or disable SPI slave */ + #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define SPIS_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIS_ENABLE_ENABLE_Max (0x2UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPI slave */ + #define SPIS_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable SPI slave */ + + +/* SPIS_CONFIG: Configuration register */ + #define SPIS_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ORDER @Bit 0 : Bit order */ + #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ + #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ + #define SPIS_CONFIG_ORDER_Min (0x0UL) /*!< Min enumerator value of ORDER field. */ + #define SPIS_CONFIG_ORDER_Max (0x1UL) /*!< Max enumerator value of ORDER field. */ + #define SPIS_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */ + #define SPIS_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */ + +/* CPHA @Bit 1 : Serial clock (SCK) phase */ + #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ + #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ + #define SPIS_CONFIG_CPHA_Min (0x0UL) /*!< Min enumerator value of CPHA field. */ + #define SPIS_CONFIG_CPHA_Max (0x1UL) /*!< Max enumerator value of CPHA field. */ + #define SPIS_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ + #define SPIS_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* CPOL @Bit 2 : Serial clock (SCK) polarity */ + #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ + #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ + #define SPIS_CONFIG_CPOL_Min (0x0UL) /*!< Min enumerator value of CPOL field. */ + #define SPIS_CONFIG_CPOL_Max (0x1UL) /*!< Max enumerator value of CPOL field. */ + #define SPIS_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */ + #define SPIS_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */ + + +/* SPIS_DEF: Default character. Character clocked out in case of an ignored transaction. */ + #define SPIS_DEF_ResetValue (0x00000000UL) /*!< Reset value of DEF register. */ + +/* DEF @Bits 0..7 : Default character. Character clocked out in case of an ignored transaction. */ + #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ + #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + + +/* SPIS_ORC: Over-read character */ + #define SPIS_ORC_ResetValue (0x00000000UL) /*!< Reset value of ORC register. */ + +/* ORC @Bits 0..7 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ + #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ + #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ SPU ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================= Struct SPU_PERIPHACCERR ================================================= */ +/** + * @brief PERIPHACCERR [SPU_PERIPHACCERR] (unspecified) + */ +typedef struct { + __IM uint32_t ADDRESS; /*!< (@ 0x00000000) Address of the transaction that caused first error. */ +} NRF_SPU_PERIPHACCERR_Type; /*!< Size = 4 (0x004) */ + +/* SPU_PERIPHACCERR_ADDRESS: Address of the transaction that caused first error. */ + #define SPU_PERIPHACCERR_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* ADDRESS @Bits 0..15 : Address */ + #define SPU_PERIPHACCERR_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define SPU_PERIPHACCERR_ADDRESS_ADDRESS_Msk (0xFFFFUL << SPU_PERIPHACCERR_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + + +/* ==================================================== Struct SPU_PERIPH ==================================================== */ +/** + * @brief PERIPH [SPU_PERIPH] (unspecified) + */ +typedef struct { + __IOM uint32_t PERM; /*!< (@ 0x00000000) Get and set the applicable access permissions for the + peripheral slave index n*/ +} NRF_SPU_PERIPH_Type; /*!< Size = 4 (0x004) */ + #define SPU_PERIPH_MaxCount (64UL) /*!< Size of PERIPH[64] array. */ + #define SPU_PERIPH_MaxIndex (63UL) /*!< Max index of PERIPH[64] array. */ + #define SPU_PERIPH_MinIndex (0UL) /*!< Min index of PERIPH[64] array. */ + +/* SPU_PERIPH_PERM: Get and set the applicable access permissions for the peripheral slave index n */ + #define SPU_PERIPH_PERM_ResetValue (0x8000002AUL) /*!< Reset value of PERM register. */ + +/* SECUREMAPPING @Bits 0..1 : Read capabilities for TrustZone Cortex-M secure attribute */ + #define SPU_PERIPH_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ + #define SPU_PERIPH_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPH_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ + #define SPU_PERIPH_PERM_SECUREMAPPING_Min (0x0UL) /*!< Min enumerator value of SECUREMAPPING field. */ + #define SPU_PERIPH_PERM_SECUREMAPPING_Max (0x3UL) /*!< Max enumerator value of SECUREMAPPING field. */ + #define SPU_PERIPH_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< This peripheral is always accessible as a non-secure peripheral */ + #define SPU_PERIPH_PERM_SECUREMAPPING_Secure (0x1UL) /*!< This peripheral is always accessible as a secure peripheral */ + #define SPU_PERIPH_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for this peripheral is + defined by the PERIPH[n].PERM register*/ + #define SPU_PERIPH_PERM_SECUREMAPPING_Split (0x3UL) /*!< This peripheral implements the split security mechanism. */ + +/* DMA @Bits 2..3 : Read the peripheral DMA capabilities */ + #define SPU_PERIPH_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */ + #define SPU_PERIPH_PERM_DMA_Msk (0x3UL << SPU_PERIPH_PERM_DMA_Pos) /*!< Bit mask of DMA field. */ + #define SPU_PERIPH_PERM_DMA_Min (0x0UL) /*!< Min enumerator value of DMA field. */ + #define SPU_PERIPH_PERM_DMA_Max (0x2UL) /*!< Max enumerator value of DMA field. */ + #define SPU_PERIPH_PERM_DMA_NoDMA (0x0UL) /*!< Peripheral has no DMA capability */ + #define SPU_PERIPH_PERM_DMA_NoSeparateAttribute (0x1UL) /*!< Peripheral has DMA and DMA transfers always have the same + security attribute as assigned to the peripheral*/ + #define SPU_PERIPH_PERM_DMA_SeparateAttribute (0x2UL) /*!< Peripheral has DMA and DMA transfers can have a different security + attribute than the one assigned to the peripheral*/ + +/* SECATTR @Bit 4 : Peripheral security mapping */ + #define SPU_PERIPH_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_PERIPH_PERM_SECATTR_Msk (0x1UL << SPU_PERIPH_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_PERIPH_PERM_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_PERIPH_PERM_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_PERIPH_PERM_SECATTR_Secure (0x1UL) /*!< Peripheral is mapped in secure peripheral address space */ + #define SPU_PERIPH_PERM_SECATTR_NonSecure (0x0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure + peripheral address space. If SECUREMAPPING == Split: Peripheral is + mapped in non-secure and secure peripheral address space.*/ + +/* DMASEC @Bit 5 : Security attribution for the DMA transfer */ + #define SPU_PERIPH_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */ + #define SPU_PERIPH_PERM_DMASEC_Msk (0x1UL << SPU_PERIPH_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */ + #define SPU_PERIPH_PERM_DMASEC_Min (0x0UL) /*!< Min enumerator value of DMASEC field. */ + #define SPU_PERIPH_PERM_DMASEC_Max (0x1UL) /*!< Max enumerator value of DMASEC field. */ + #define SPU_PERIPH_PERM_DMASEC_Secure (0x1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute + set*/ + #define SPU_PERIPH_PERM_DMASEC_NonSecure (0x0UL) /*!< DMA transfers initiated by this peripheral have the non-secure + attribute set*/ + +/* LOCK @Bit 8 : Register lock */ + #define SPU_PERIPH_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_PERIPH_PERM_LOCK_Msk (0x1UL << SPU_PERIPH_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_PERIPH_PERM_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_PERIPH_PERM_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_PERIPH_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ + #define SPU_PERIPH_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can not be changed until the next reset */ + +/* PRESENT @Bit 31 : Indicates if a peripheral is present with peripheral slave index n */ + #define SPU_PERIPH_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */ + #define SPU_PERIPH_PERM_PRESENT_Msk (0x1UL << SPU_PERIPH_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ + #define SPU_PERIPH_PERM_PRESENT_Min (0x0UL) /*!< Min enumerator value of PRESENT field. */ + #define SPU_PERIPH_PERM_PRESENT_Max (0x1UL) /*!< Max enumerator value of PRESENT field. */ + #define SPU_PERIPH_PERM_PRESENT_NotPresent (0x0UL) /*!< Peripheral is not present */ + #define SPU_PERIPH_PERM_PRESENT_IsPresent (0x1UL) /*!< Peripheral is present */ + + + +/* ================================================ Struct SPU_FEATURE_DPPIC ================================================= */ +/** + * @brief DPPIC [SPU_FEATURE_DPPIC] (unspecified) + */ +typedef struct { + __IOM uint32_t CH[24]; /*!< (@ 0x00000000) Security configuration for channel n of DPPIC */ + __IOM uint32_t CHG[8]; /*!< (@ 0x00000060) Security configuration for channel group n of DPPIC */ +} NRF_SPU_FEATURE_DPPIC_Type; /*!< Size = 128 (0x080) */ + +/* SPU_FEATURE_DPPIC_CH: Security configuration for channel n of DPPIC */ + #define SPU_FEATURE_DPPIC_CH_MaxCount (24UL) /*!< Max size of CH[24] array. */ + #define SPU_FEATURE_DPPIC_CH_MaxIndex (23UL) /*!< Max index of CH[24] array. */ + #define SPU_FEATURE_DPPIC_CH_MinIndex (0UL) /*!< Min index of CH[24] array. */ + #define SPU_FEATURE_DPPIC_CH_ResetValue (0x00100010UL) /*!< Reset value of CH[24] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_Msk (0x1UL << SPU_FEATURE_DPPIC_CH_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Msk (0x1UL << SPU_FEATURE_DPPIC_CH_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + + +/* SPU_FEATURE_DPPIC_CHG: Security configuration for channel group n of DPPIC */ + #define SPU_FEATURE_DPPIC_CHG_MaxCount (8UL) /*!< Max size of CHG[8] array. */ + #define SPU_FEATURE_DPPIC_CHG_MaxIndex (7UL) /*!< Max index of CHG[8] array. */ + #define SPU_FEATURE_DPPIC_CHG_MinIndex (0UL) /*!< Min index of CHG[8] array. */ + #define SPU_FEATURE_DPPIC_CHG_ResetValue (0x00100010UL) /*!< Reset value of CHG[8] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_Msk (0x1UL << SPU_FEATURE_DPPIC_CHG_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Msk (0x1UL << SPU_FEATURE_DPPIC_CHG_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + + + +/* ================================================ Struct SPU_FEATURE_GPIOTE ================================================ */ +/** + * @brief GPIOTE [SPU_FEATURE_GPIOTE] (unspecified) + */ +typedef struct { + __IOM uint32_t CH[8]; /*!< (@ 0x00000000) Security configuration for channel o of GPIOTE[n] */ + __IOM uint32_t INTERRUPT[8]; /*!< (@ 0x00000020) Security configuration for interrupt o of GPIOTE[n] */ +} NRF_SPU_FEATURE_GPIOTE_Type; /*!< Size = 64 (0x040) */ + #define SPU_FEATURE_GPIOTE_MaxCount (2UL) /*!< Size of GPIOTE[2] array. */ + #define SPU_FEATURE_GPIOTE_MaxIndex (1UL) /*!< Max index of GPIOTE[2] array. */ + #define SPU_FEATURE_GPIOTE_MinIndex (0UL) /*!< Min index of GPIOTE[2] array. */ + +/* SPU_FEATURE_GPIOTE_CH: Security configuration for channel o of GPIOTE[n] */ + #define SPU_FEATURE_GPIOTE_CH_MaxCount (8UL) /*!< Max size of CH[8] array. */ + #define SPU_FEATURE_GPIOTE_CH_MaxIndex (7UL) /*!< Max index of CH[8] array. */ + #define SPU_FEATURE_GPIOTE_CH_MinIndex (0UL) /*!< Min index of CH[8] array. */ + #define SPU_FEATURE_GPIOTE_CH_ResetValue (0x00100010UL) /*!< Reset value of CH[8] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIOTE_CH_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Msk (0x1UL << SPU_FEATURE_GPIOTE_CH_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + + +/* SPU_FEATURE_GPIOTE_INTERRUPT: Security configuration for interrupt o of GPIOTE[n] */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxCount (8UL) /*!< Max size of INTERRUPT[8] array. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxIndex (7UL) /*!< Max index of INTERRUPT[8] array. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[8] array. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_ResetValue (0x00100010UL) /*!< Reset value of INTERRUPT[8] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos) /*!< Bit mask of SECATTR + field.*/ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Msk (0x1UL << SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + + + +/* ================================================= Struct SPU_FEATURE_GPIO ================================================= */ +/** + * @brief GPIO [SPU_FEATURE_GPIO] (unspecified) + */ +typedef struct { + __IOM uint32_t PIN[32]; /*!< (@ 0x00000000) Security configuration for GPIO[n] PIN[o] */ +} NRF_SPU_FEATURE_GPIO_Type; /*!< Size = 128 (0x080) */ + #define SPU_FEATURE_GPIO_MaxCount (4UL) /*!< Size of GPIO[4] array. */ + #define SPU_FEATURE_GPIO_MaxIndex (3UL) /*!< Max index of GPIO[4] array. */ + #define SPU_FEATURE_GPIO_MinIndex (0UL) /*!< Min index of GPIO[4] array. */ + +/* SPU_FEATURE_GPIO_PIN: Security configuration for GPIO[n] PIN[o] */ + #define SPU_FEATURE_GPIO_PIN_MaxCount (32UL) /*!< Max size of PIN[32] array. */ + #define SPU_FEATURE_GPIO_PIN_MaxIndex (31UL) /*!< Max index of PIN[32] array. */ + #define SPU_FEATURE_GPIO_PIN_MinIndex (0UL) /*!< Min index of PIN[32] array. */ + #define SPU_FEATURE_GPIO_PIN_ResetValue (0x00100010UL) /*!< Reset value of PIN[32] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIO_PIN_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Msk (0x1UL << SPU_FEATURE_GPIO_PIN_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + + + +/* ================================================= Struct SPU_FEATURE_GRTC ================================================= */ +/** + * @brief GRTC [SPU_FEATURE_GRTC] (unspecified) + */ +typedef struct { + __IOM uint32_t CC[24]; /*!< (@ 0x00000000) Security configuration for CC n of GRTC */ + __IM uint32_t RESERVED[5]; + __IOM uint32_t PWMCONFIG; /*!< (@ 0x00000074) Security Configuration for PWMCONFIG of GRTC */ + __IOM uint32_t CLK; /*!< (@ 0x00000078) Security configuration for CLKOUT/CLKCFG of GRTC */ + __IOM uint32_t SYSCOUNTER; /*!< (@ 0x0000007C) Security configuration for SYSCOUNTERL/SYSCOUNTERH of + GRTC*/ + __IOM uint32_t INTERRUPT[16]; /*!< (@ 0x00000080) Security configuration for interrupt n of GRTC */ +} NRF_SPU_FEATURE_GRTC_Type; /*!< Size = 192 (0x0C0) */ + +/* SPU_FEATURE_GRTC_CC: Security configuration for CC n of GRTC */ + #define SPU_FEATURE_GRTC_CC_MaxCount (24UL) /*!< Max size of CC[24] array. */ + #define SPU_FEATURE_GRTC_CC_MaxIndex (23UL) /*!< Max index of CC[24] array. */ + #define SPU_FEATURE_GRTC_CC_MinIndex (0UL) /*!< Min index of CC[24] array. */ + #define SPU_FEATURE_GRTC_CC_ResetValue (0x00100010UL) /*!< Reset value of CC[24] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GRTC_CC_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GRTC_CC_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_CC_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_GRTC_CC_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_CC_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_CC_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GRTC_CC_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GRTC_CC_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GRTC_CC_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_CC_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GRTC_CC_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_CC_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_CC_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GRTC_CC_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + + +/* SPU_FEATURE_GRTC_PWMCONFIG: Security Configuration for PWMCONFIG of GRTC */ + #define SPU_FEATURE_GRTC_PWMCONFIG_ResetValue (0x00100010UL) /*!< Reset value of PWMCONFIG register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Pos) /*!< Bit mask of SECATTR + field.*/ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + + +/* SPU_FEATURE_GRTC_CLK: Security configuration for CLKOUT/CLKCFG of GRTC */ + #define SPU_FEATURE_GRTC_CLK_ResetValue (0x00100010UL) /*!< Reset value of CLK register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_CLK_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_CLK_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + + +/* SPU_FEATURE_GRTC_SYSCOUNTER: Security configuration for SYSCOUNTERL/SYSCOUNTERH of GRTC */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_ResetValue (0x00100010UL) /*!< Reset value of SYSCOUNTER register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos) /*!< Bit mask of SECATTR + field.*/ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + + +/* SPU_FEATURE_GRTC_INTERRUPT: Security configuration for interrupt n of GRTC */ + #define SPU_FEATURE_GRTC_INTERRUPT_MaxCount (16UL) /*!< Max size of INTERRUPT[16] array. */ + #define SPU_FEATURE_GRTC_INTERRUPT_MaxIndex (15UL) /*!< Max index of INTERRUPT[16] array. */ + #define SPU_FEATURE_GRTC_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[16] array. */ + #define SPU_FEATURE_GRTC_INTERRUPT_ResetValue (0x00100010UL) /*!< Reset value of INTERRUPT[16] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos) /*!< Bit mask of SECATTR + field.*/ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + + + +/* =================================================== Struct SPU_FEATURE ==================================================== */ +/** + * @brief FEATURE [SPU_FEATURE] (unspecified) + */ +typedef union { + struct { + __IM uint32_t RESERVED[32]; + __IOM NRF_SPU_FEATURE_DPPIC_Type DPPIC; /*!< (@ 0x00000080) (unspecified) */ + __IOM NRF_SPU_FEATURE_GPIOTE_Type GPIOTE[2]; /*!< (@ 0x00000100) (unspecified) */ + __IM uint32_t RESERVED1[32]; + __IOM NRF_SPU_FEATURE_GPIO_Type GPIO[4]; /*!< (@ 0x00000200) (unspecified) */ + __IM uint32_t RESERVED2[192]; + __IOM NRF_SPU_FEATURE_GRTC_Type GRTC; /*!< (@ 0x00000700) (unspecified) */ + }; +} NRF_SPU_FEATURE_Type; /*!< Size = 1984 (0x7C0) */ + +/* ======================================================= Struct SPU ======================================================== */ +/** + * @brief System protection unit + */ + typedef struct { /*!< SPU Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000100) A security violation has been detected on one or + several peripherals*/ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[61]; + __IOM NRF_SPU_PERIPHACCERR_Type PERIPHACCERR; /*!< (@ 0x00000404) (unspecified) */ + __IM uint32_t RESERVED3[62]; + __IOM NRF_SPU_PERIPH_Type PERIPH[64]; /*!< (@ 0x00000500) (unspecified) */ + __IOM NRF_SPU_FEATURE_Type FEATURE; /*!< (@ 0x00000600) (unspecified) */ + } NRF_SPU_Type; /*!< Size = 3520 (0xDC0) */ + +/* SPU_EVENTS_PERIPHACCERR: A security violation has been detected on one or several peripherals */ + #define SPU_EVENTS_PERIPHACCERR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PERIPHACCERR register. */ + +/* EVENTS_PERIPHACCERR @Bit 0 : A security violation has been detected on one or several peripherals */ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit + mask of EVENTS_PERIPHACCERR field.*/ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of EVENTS_PERIPHACCERR field. */ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of EVENTS_PERIPHACCERR field. */ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (0x1UL) /*!< Event generated */ + + +/* SPU_INTEN: Enable or disable interrupt */ + #define SPU_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* PERIPHACCERR @Bit 0 : Enable or disable interrupt for event PERIPHACCERR */ + #define SPU_INTEN_PERIPHACCERR_Pos (0UL) /*!< Position of PERIPHACCERR field. */ + #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ + #define SPU_INTEN_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of PERIPHACCERR field. */ + #define SPU_INTEN_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of PERIPHACCERR field. */ + #define SPU_INTEN_PERIPHACCERR_Disabled (0x0UL) /*!< Disable */ + #define SPU_INTEN_PERIPHACCERR_Enabled (0x1UL) /*!< Enable */ + + +/* SPU_INTENSET: Enable interrupt */ + #define SPU_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* PERIPHACCERR @Bit 0 : Write '1' to enable interrupt for event PERIPHACCERR */ + #define SPU_INTENSET_PERIPHACCERR_Pos (0UL) /*!< Position of PERIPHACCERR field. */ + #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ + #define SPU_INTENSET_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of PERIPHACCERR field. */ + #define SPU_INTENSET_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of PERIPHACCERR field. */ + #define SPU_INTENSET_PERIPHACCERR_Set (0x1UL) /*!< Enable */ + #define SPU_INTENSET_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPU_INTENSET_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPU_INTENCLR: Disable interrupt */ + #define SPU_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* PERIPHACCERR @Bit 0 : Write '1' to disable interrupt for event PERIPHACCERR */ + #define SPU_INTENCLR_PERIPHACCERR_Pos (0UL) /*!< Position of PERIPHACCERR field. */ + #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ + #define SPU_INTENCLR_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of PERIPHACCERR field. */ + #define SPU_INTENCLR_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of PERIPHACCERR field. */ + #define SPU_INTENCLR_PERIPHACCERR_Clear (0x1UL) /*!< Disable */ + #define SPU_INTENCLR_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPU_INTENCLR_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPU_INTPEND: Pending interrupts */ + #define SPU_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* PERIPHACCERR @Bit 0 : Read pending status of interrupt for event PERIPHACCERR */ + #define SPU_INTPEND_PERIPHACCERR_Pos (0UL) /*!< Position of PERIPHACCERR field. */ + #define SPU_INTPEND_PERIPHACCERR_Msk (0x1UL << SPU_INTPEND_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ + #define SPU_INTPEND_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of PERIPHACCERR field. */ + #define SPU_INTPEND_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of PERIPHACCERR field. */ + #define SPU_INTPEND_PERIPHACCERR_NotPending (0x0UL) /*!< Read: Not pending */ + #define SPU_INTPEND_PERIPHACCERR_Pending (0x1UL) /*!< Read: Pending */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ SWI ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct SWI ======================================================== */ +/** + * @brief Software interrupt + */ + typedef struct { /*!< SWI Structure */ + __IM uint32_t RESERVED; + } NRF_SWI_Type; /*!< Size = 4 (0x004) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TAD ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct TAD ======================================================== */ +/** + * @brief Trace and debug control + */ + typedef struct { /*!< TAD Structure */ + __IM uint32_t RESERVED[256]; + __IOM uint32_t SYSPWRUPREQ; /*!< (@ 0x00000400) System power-up request */ + __IOM uint32_t DBGPWRUPREQ; /*!< (@ 0x00000404) Debug power-up request */ + __IM uint32_t RESERVED1[62]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ + __IM uint32_t RESERVED2[5]; + __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Trace port speed */ + } NRF_TAD_Type; /*!< Size = 1308 (0x51C) */ + +/* TAD_SYSPWRUPREQ: System power-up request */ + #define TAD_SYSPWRUPREQ_ResetValue (0x00000000UL) /*!< Reset value of SYSPWRUPREQ register. */ + +/* ACTIVE @Bit 0 : Activate power-up request */ + #define TAD_SYSPWRUPREQ_ACTIVE_Pos (0UL) /*!< Position of ACTIVE field. */ + #define TAD_SYSPWRUPREQ_ACTIVE_Msk (0x1UL << TAD_SYSPWRUPREQ_ACTIVE_Pos) /*!< Bit mask of ACTIVE field. */ + #define TAD_SYSPWRUPREQ_ACTIVE_Min (0x0UL) /*!< Min enumerator value of ACTIVE field. */ + #define TAD_SYSPWRUPREQ_ACTIVE_Max (0x1UL) /*!< Max enumerator value of ACTIVE field. */ + #define TAD_SYSPWRUPREQ_ACTIVE_NotActive (0x0UL) /*!< Power-up request not active */ + #define TAD_SYSPWRUPREQ_ACTIVE_Active (0x1UL) /*!< Power-up request active */ + + +/* TAD_DBGPWRUPREQ: Debug power-up request */ + #define TAD_DBGPWRUPREQ_ResetValue (0x00000000UL) /*!< Reset value of DBGPWRUPREQ register. */ + +/* ACTIVE @Bit 0 : Activate power-up request */ + #define TAD_DBGPWRUPREQ_ACTIVE_Pos (0UL) /*!< Position of ACTIVE field. */ + #define TAD_DBGPWRUPREQ_ACTIVE_Msk (0x1UL << TAD_DBGPWRUPREQ_ACTIVE_Pos) /*!< Bit mask of ACTIVE field. */ + #define TAD_DBGPWRUPREQ_ACTIVE_Min (0x0UL) /*!< Min enumerator value of ACTIVE field. */ + #define TAD_DBGPWRUPREQ_ACTIVE_Max (0x1UL) /*!< Max enumerator value of ACTIVE field. */ + #define TAD_DBGPWRUPREQ_ACTIVE_NotActive (0x0UL) /*!< Power-up request not active */ + #define TAD_DBGPWRUPREQ_ACTIVE_Active (0x1UL) /*!< Power-up request active */ + + +/* TAD_ENABLE: Enable debug domain and aquire selected GPIOs */ + #define TAD_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define TAD_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TAD_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TAD_ENABLE_ENABLE_DISABLED (0x0UL) /*!< Disable debug domain and release selected GPIOs */ + #define TAD_ENABLE_ENABLE_ENABLED (0x1UL) /*!< Enable debug domain and aquire selected GPIOs */ + + +/* TAD_TRACEPORTSPEED: Trace port speed */ + #define TAD_TRACEPORTSPEED_ResetValue (0x00000000UL) /*!< Reset value of TRACEPORTSPEED register. */ + +/* TRACEPORTSPEED @Bits 0..1 : Trace port speed is divided from CPU clock. The TRACECLK pin output will be divided again by two + from the trace port clock. */ + + #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ + #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED + field.*/ + #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Min (0x0UL) /*!< Min enumerator value of TRACEPORTSPEED field. */ + #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Max (0x3UL) /*!< Max enumerator value of TRACEPORTSPEED field. */ + #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV1 (0x0UL) /*!< Trace port speed equals CPU clock */ + #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV2 (0x1UL) /*!< Trace port speed equals CPU clock divided by 2 */ + #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV4 (0x2UL) /*!< Trace port speed equals CPU clock divided by 4 */ + #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV32 (0x3UL) /*!< Trace port speed equals CPU clock divided by 32 */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TAMPC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct TAMPC_ACTIVESHIELD ================================================ */ +/** + * @brief ACTIVESHIELD [TAMPC_ACTIVESHIELD] (unspecified) + */ +typedef struct { + __IOM uint32_t CHEN; /*!< (@ 0x00000000) Active shield detector channel enable register. */ +} NRF_TAMPC_ACTIVESHIELD_Type; /*!< Size = 4 (0x004) */ + +/* TAMPC_ACTIVESHIELD_CHEN: Active shield detector channel enable register. */ + #define TAMPC_ACTIVESHIELD_CHEN_ResetValue (0x00000000UL) /*!< Reset value of CHEN register. */ + +/* CH0 @Bit 0 : Enable or disable active shield channel 0. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH0_Msk (0x1UL << TAMPC_ACTIVESHIELD_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH0_Disabled (0x0UL) /*!< Disable channel. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH0_Enabled (0x1UL) /*!< Enable channel. */ + +/* CH1 @Bit 1 : Enable or disable active shield channel 1. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH1_Msk (0x1UL << TAMPC_ACTIVESHIELD_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH1_Disabled (0x0UL) /*!< Disable channel. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH1_Enabled (0x1UL) /*!< Enable channel. */ + +/* CH2 @Bit 2 : Enable or disable active shield channel 2. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH2_Msk (0x1UL << TAMPC_ACTIVESHIELD_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH2_Disabled (0x0UL) /*!< Disable channel. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH2_Enabled (0x1UL) /*!< Enable channel. */ + +/* CH3 @Bit 3 : Enable or disable active shield channel 3. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH3_Msk (0x1UL << TAMPC_ACTIVESHIELD_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH3_Disabled (0x0UL) /*!< Disable channel. */ + #define TAMPC_ACTIVESHIELD_CHEN_CH3_Enabled (0x1UL) /*!< Enable channel. */ + + + +/* ============================================ Struct TAMPC_PROTECT_DOMAIN_DBGEN ============================================ */ +/** + * @brief DBGEN [TAMPC_PROTECT_DOMAIN_DBGEN] (unspecified) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for invasive (halting) debug enable + for the local debug components within domain n.*/ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for invasive (halting) debug enable for + domain n.*/ +} NRF_TAMPC_PROTECT_DOMAIN_DBGEN_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_DOMAIN_DBGEN_CTRL: Control register for invasive (halting) debug enable for the local debug components within + domain n. */ + + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of dbgen signal. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0, indicating that invasive debug is disabled.*/ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1, indicating that invasive debug is enabled.*/ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK + field.*/ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Pos) + /*!< Bit mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Pos) /*!< Bit mask of KEY + field.*/ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_DOMAIN_DBGEN_STATUS: Status register for invasive (halting) debug enable for domain n. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Pos) /*!< Bit mask of + ERROR field.*/ + #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* ============================================ Struct TAMPC_PROTECT_DOMAIN_NIDEN ============================================ */ +/** + * @brief NIDEN [TAMPC_PROTECT_DOMAIN_NIDEN] (unspecified) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for non-invasive debug enable for the + local debug components within domain n.*/ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for non-invasive debug enable for + domain n.*/ +} NRF_TAMPC_PROTECT_DOMAIN_NIDEN_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_DOMAIN_NIDEN_CTRL: Control register for non-invasive debug enable for the local debug components within domain + n. */ + + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of niden signal. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0, indicating that non-invasive debug is + disabled.*/ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1, indicating that non-invasive debug is + enabled.*/ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK + field.*/ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Pos) + /*!< Bit mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_Pos) /*!< Bit mask of KEY + field.*/ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_DOMAIN_NIDEN_STATUS: Status register for non-invasive debug enable for domain n. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Pos) /*!< Bit mask of + ERROR field.*/ + #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* =========================================== Struct TAMPC_PROTECT_DOMAIN_SPIDEN ============================================ */ +/** + * @brief SPIDEN [TAMPC_PROTECT_DOMAIN_SPIDEN] (unspecified) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for secure priviliged invasive + (halting) debug enable for the local debug components + within domain n.*/ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for secure priviliged invasive + (halting) debug enable for domain n.*/ +} NRF_TAMPC_PROTECT_DOMAIN_SPIDEN_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL: Control register for secure priviliged invasive (halting) debug enable for the local debug + components within domain n. */ + + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of spiden signal. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Pos) /*!< Bit mask of + VALUE field.*/ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0, indicating that secure priviliged invasive + debug is disabled.*/ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1, indicating that secure priviliged invasive + debug is enabled.*/ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK + field.*/ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Pos) + /*!< Bit mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_Pos) /*!< Bit mask of KEY + field.*/ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS: Status register for secure priviliged invasive (halting) debug enable for domain n. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Pos) /*!< Bit mask of + ERROR field.*/ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* =========================================== Struct TAMPC_PROTECT_DOMAIN_SPNIDEN =========================================== */ +/** + * @brief SPNIDEN [TAMPC_PROTECT_DOMAIN_SPNIDEN] (unspecified) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for secure priviliged non-invasive + debug enable for the local debug components within + domain n.*/ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for secure priviliged non-invasive + debug enable for domain n.*/ +} NRF_TAMPC_PROTECT_DOMAIN_SPNIDEN_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL: Control register for secure priviliged non-invasive debug enable for the local debug + components within domain n. */ + + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of spniden signal. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Pos) /*!< Bit mask of + VALUE field.*/ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0, indicating that secure priviliged + non-invasive debug is disabled.*/ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1, indicating that secure priviliged + non-invasive debug is enabled.*/ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK + field.*/ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Pos) + /*!< Bit mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_Pos) /*!< Bit mask of KEY + field.*/ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS: Status register for secure priviliged non-invasive debug enable for domain n. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Pos) /*!< Bit mask + of ERROR field.*/ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* =============================================== Struct TAMPC_PROTECT_DOMAIN =============================================== */ +/** + * @brief DOMAIN [TAMPC_PROTECT_DOMAIN] (unspecified) + */ +typedef struct { + __IOM NRF_TAMPC_PROTECT_DOMAIN_DBGEN_Type DBGEN; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_TAMPC_PROTECT_DOMAIN_NIDEN_Type NIDEN; /*!< (@ 0x00000008) (unspecified) */ + __IOM NRF_TAMPC_PROTECT_DOMAIN_SPIDEN_Type SPIDEN; /*!< (@ 0x00000010) (unspecified) */ + __IOM NRF_TAMPC_PROTECT_DOMAIN_SPNIDEN_Type SPNIDEN; /*!< (@ 0x00000018) (unspecified) */ +} NRF_TAMPC_PROTECT_DOMAIN_Type; /*!< Size = 32 (0x020) */ + #define TAMPC_PROTECT_DOMAIN_MaxCount (1UL) /*!< Size of DOMAIN[1] array. */ + #define TAMPC_PROTECT_DOMAIN_MaxIndex (0UL) /*!< Max index of DOMAIN[1] array. */ + #define TAMPC_PROTECT_DOMAIN_MinIndex (0UL) /*!< Min index of DOMAIN[1] array. */ + + +/* ============================================== Struct TAMPC_PROTECT_AP_DBGEN ============================================== */ +/** + * @brief DBGEN [TAMPC_PROTECT_AP_DBGEN] (unspecified) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register to enable invasive (halting) debug in + domain ns access port.*/ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for invasive (halting) debug enable for + domain ns access port.*/ +} NRF_TAMPC_PROTECT_AP_DBGEN_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_AP_DBGEN_CTRL: Control register to enable invasive (halting) debug in domain ns access port. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of dbgen signal. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0, indicating that invasive debug is disabled. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1, indicating that invasive debug is enabled. */ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Pos) /*!< Bit + mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_Pos) /*!< Bit mask of KEY field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_AP_DBGEN_STATUS: Status register for invasive (halting) debug enable for domain ns access port. */ + #define TAMPC_PROTECT_AP_DBGEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Pos) /*!< Bit mask of ERROR + field.*/ + #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* ================================================= Struct TAMPC_PROTECT_AP ================================================= */ +/** + * @brief AP [TAMPC_PROTECT_AP] (unspecified) + */ +typedef struct { + __IOM NRF_TAMPC_PROTECT_AP_DBGEN_Type DBGEN; /*!< (@ 0x00000000) (unspecified) */ + __IM uint32_t RESERVED[2]; +} NRF_TAMPC_PROTECT_AP_Type; /*!< Size = 16 (0x010) */ + #define TAMPC_PROTECT_AP_MaxCount (1UL) /*!< Size of AP[1] array. */ + #define TAMPC_PROTECT_AP_MaxIndex (0UL) /*!< Max index of AP[1] array. */ + #define TAMPC_PROTECT_AP_MinIndex (0UL) /*!< Min index of AP[1] array. */ + + +/* ============================================ Struct TAMPC_PROTECT_ACTIVESHIELD ============================================ */ +/** + * @brief ACTIVESHIELD [TAMPC_PROTECT_ACTIVESHIELD] Enable active shield detector. + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for active shield detector enable + signal.*/ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for active shield detector enable + signal.*/ +} NRF_TAMPC_PROTECT_ACTIVESHIELD_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_ACTIVESHIELD_CTRL: Control register for active shield detector enable signal. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of active shield enable signal. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Pos) /*!< Bit mask of LOCK + field.*/ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Pos) + /*!< Bit mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_Pos) /*!< Bit mask of KEY + field.*/ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_ACTIVESHIELD_STATUS: Status register for active shield detector enable signal. */ + #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Pos) /*!< Bit mask of + ERROR field.*/ + #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* ============================================= Struct TAMPC_PROTECT_CRACENTAMP ============================================= */ +/** + * @brief CRACENTAMP [TAMPC_PROTECT_CRACENTAMP] Enable tamper detector from CRACEN. + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for CRACEN tamper detector enable + signal.*/ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for CRACEN tamper detector enable + signal.*/ +} NRF_TAMPC_PROTECT_CRACENTAMP_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_CRACENTAMP_CTRL: Control register for CRACEN tamper detector enable signal. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_ResetValue (0x00000011UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of CRACEN tamper detector enable signal. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Pos) /*!< Bit mask of LOCK field.*/ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Pos) /*!< + Bit mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_Pos) /*!< Bit mask of KEY field.*/ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_CRACENTAMP_STATUS: Status register for CRACEN tamper detector enable signal. */ + #define TAMPC_PROTECT_CRACENTAMP_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Pos) /*!< Bit mask of ERROR + field.*/ + #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* ========================================== Struct TAMPC_PROTECT_GLITCHSLOWDOMAIN ========================================== */ +/** + * @brief GLITCHSLOWDOMAIN [TAMPC_PROTECT_GLITCHSLOWDOMAIN] Enable slow domain glitch detectors. + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for slow domain glitch detectors + enable signal.*/ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for slow domain glitch detectors enable + signal.*/ +} NRF_TAMPC_PROTECT_GLITCHSLOWDOMAIN_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL: Control register for slow domain glitch detectors enable signal. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_ResetValue (0x00000011UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of slow domain glitch detectors enable signal. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Pos) /*!< Bit mask + of VALUE field.*/ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Pos) /*!< Bit mask of + LOCK field.*/ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Pos) + /*!< Bit mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_Pos) /*!< Bit mask of + KEY field.*/ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS: Status register for slow domain glitch detectors enable signal. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Pos) /*!< Bit + mask of ERROR field.*/ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* ========================================== Struct TAMPC_PROTECT_GLITCHFASTDOMAIN ========================================== */ +/** + * @brief GLITCHFASTDOMAIN [TAMPC_PROTECT_GLITCHFASTDOMAIN] Enable fast domain glitch detectors. + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for fast domain glitch detectors + enable signal.*/ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for fast domain glitch detectors enable + signal.*/ +} NRF_TAMPC_PROTECT_GLITCHFASTDOMAIN_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL: Control register for fast domain glitch detectors enable signal. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_ResetValue (0x00000011UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of fast domain glitch detector's enable signal. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Pos) /*!< Bit mask + of VALUE field.*/ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Pos) /*!< Bit mask of + LOCK field.*/ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Pos) + /*!< Bit mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_Pos) /*!< Bit mask of + KEY field.*/ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS: Status register for fast domain glitch detectors enable signal. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Pos) /*!< Bit + mask of ERROR field.*/ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* ============================================= Struct TAMPC_PROTECT_EXTRESETEN ============================================= */ +/** + * @brief EXTRESETEN [TAMPC_PROTECT_EXTRESETEN] Trigger a reset when tamper is detected by the external tamper detectors. + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for external tamper reset enable + signal.*/ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for external tamper reset enable + signal.*/ +} NRF_TAMPC_PROTECT_EXTRESETEN_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_EXTRESETEN_CTRL: Control register for external tamper reset enable signal. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of external tamper reset enable signal. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK field.*/ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Pos) /*!< + Bit mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_Pos) /*!< Bit mask of KEY field.*/ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_EXTRESETEN_STATUS: Status register for external tamper reset enable signal. */ + #define TAMPC_PROTECT_EXTRESETEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Pos) /*!< Bit mask of ERROR + field.*/ + #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* ============================================= Struct TAMPC_PROTECT_INTRESETEN ============================================= */ +/** + * @brief INTRESETEN [TAMPC_PROTECT_INTRESETEN] Trigger a reset when tamper is detected by the glitch detectors, signal + protector or CRACEN tamper detector. + + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for internal tamper reset enable + signal.*/ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for internal tamper reset enable + signal.*/ +} NRF_TAMPC_PROTECT_INTRESETEN_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_INTRESETEN_CTRL: Control register for internal tamper reset enable signal. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_ResetValue (0x00000011UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of internal tamper reset enable signal. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK field.*/ + #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Pos) /*!< + Bit mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_INTRESETEN_CTRL_KEY_Pos) /*!< Bit mask of KEY field.*/ + #define TAMPC_PROTECT_INTRESETEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_INTRESETEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_INTRESETEN_STATUS: Status register for internal tamper reset enable signal. */ + #define TAMPC_PROTECT_INTRESETEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Pos) /*!< Bit mask of ERROR + field.*/ + #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* ============================================ Struct TAMPC_PROTECT_ERASEPROTECT ============================================ */ +/** + * @brief ERASEPROTECT [TAMPC_PROTECT_ERASEPROTECT] Device erase protection. + */ +typedef struct { + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for erase protection. */ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for eraseprotect. */ +} NRF_TAMPC_PROTECT_ERASEPROTECT_Type; /*!< Size = 8 (0x008) */ + +/* TAMPC_PROTECT_ERASEPROTECT_CTRL: Control register for erase protection. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ + +/* VALUE @Bit 0 : Set value of eraseprotect signal. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ + +/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Pos) /*!< Bit mask of LOCK + field.*/ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + +/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Pos) + /*!< Bit mask of WRITEPROTECTION field.*/ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ + +/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_Pos) /*!< Bit mask of KEY + field.*/ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ + #define TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ + + +/* TAMPC_PROTECT_ERASEPROTECT_STATUS: Status register for eraseprotect. */ + #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERROR @Bit 0 : Error detection status. */ + #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Pos) /*!< Bit mask of + ERROR field.*/ + #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ + #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ + + + +/* ================================================== Struct TAMPC_PROTECT =================================================== */ +/** + * @brief PROTECT [TAMPC_PROTECT] (unspecified) + */ +typedef struct { + __IOM NRF_TAMPC_PROTECT_DOMAIN_Type DOMAIN[1]; /*!< (@ 0x00000000) (unspecified) */ + __IM uint32_t RESERVED[120]; + __IOM NRF_TAMPC_PROTECT_AP_Type AP[1]; /*!< (@ 0x00000200) (unspecified) */ + __IM uint32_t RESERVED1[124]; + __IOM NRF_TAMPC_PROTECT_ACTIVESHIELD_Type ACTIVESHIELD; /*!< (@ 0x00000400) Enable active shield detector. */ + __IM uint32_t RESERVED2[12]; + __IOM NRF_TAMPC_PROTECT_CRACENTAMP_Type CRACENTAMP; /*!< (@ 0x00000438) Enable tamper detector from CRACEN. */ + __IOM NRF_TAMPC_PROTECT_GLITCHSLOWDOMAIN_Type GLITCHSLOWDOMAIN; /*!< (@ 0x00000440) Enable slow domain glitch detectors. */ + __IOM NRF_TAMPC_PROTECT_GLITCHFASTDOMAIN_Type GLITCHFASTDOMAIN; /*!< (@ 0x00000448) Enable fast domain glitch detectors. */ + __IM uint32_t RESERVED3[8]; + __IOM NRF_TAMPC_PROTECT_EXTRESETEN_Type EXTRESETEN; /*!< (@ 0x00000470) Trigger a reset when tamper is detected by the + external tamper detectors.*/ + __IOM NRF_TAMPC_PROTECT_INTRESETEN_Type INTRESETEN; /*!< (@ 0x00000478) Trigger a reset when tamper is detected by the glitch + detectors, signal protector or CRACEN tamper + detector.*/ + __IOM NRF_TAMPC_PROTECT_ERASEPROTECT_Type ERASEPROTECT; /*!< (@ 0x00000480) Device erase protection. */ +} NRF_TAMPC_PROTECT_Type; /*!< Size = 1160 (0x488) */ + +/* ====================================================== Struct TAMPC ======================================================= */ +/** + * @brief Tamper controller + */ + typedef struct { /*!< TAMPC Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_TAMPER; /*!< (@ 0x00000100) Tamper controller detected an error. */ + __IOM uint32_t EVENTS_WRITEERROR; /*!< (@ 0x00000104) Attempt to write a VALUE in PROTECT registers without + clearing the WRITEPROTECT.*/ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[60]; + __IOM uint32_t STATUS; /*!< (@ 0x00000400) The tamper controller status. */ + __IOM NRF_TAMPC_ACTIVESHIELD_Type ACTIVESHIELD; /*!< (@ 0x00000404) (unspecified) */ + __IM uint32_t RESERVED3[62]; + __IOM NRF_TAMPC_PROTECT_Type PROTECT; /*!< (@ 0x00000500) (unspecified) */ + } NRF_TAMPC_Type; /*!< Size = 2440 (0x988) */ + +/* TAMPC_EVENTS_TAMPER: Tamper controller detected an error. */ + #define TAMPC_EVENTS_TAMPER_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TAMPER register. */ + +/* EVENTS_TAMPER @Bit 0 : Tamper controller detected an error. */ + #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Pos (0UL) /*!< Position of EVENTS_TAMPER field. */ + #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Msk (0x1UL << TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Pos) /*!< Bit mask of EVENTS_TAMPER + field.*/ + #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Min (0x0UL) /*!< Min enumerator value of EVENTS_TAMPER field. */ + #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Max (0x1UL) /*!< Max enumerator value of EVENTS_TAMPER field. */ + #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_NotGenerated (0x0UL) /*!< Event not generated */ + #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Generated (0x1UL) /*!< Event generated */ + + +/* TAMPC_EVENTS_WRITEERROR: Attempt to write a VALUE in PROTECT registers without clearing the WRITEPROTECT. */ + #define TAMPC_EVENTS_WRITEERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_WRITEERROR register. */ + +/* EVENTS_WRITEERROR @Bit 0 : Attempt to write a VALUE in PROTECT registers without clearing the WRITEPROTECT. */ + #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Pos (0UL) /*!< Position of EVENTS_WRITEERROR field. */ + #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Msk (0x1UL << TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Pos) /*!< Bit mask + of EVENTS_WRITEERROR field.*/ + #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_WRITEERROR field. */ + #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_WRITEERROR field. */ + #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Generated (0x1UL) /*!< Event generated */ + + +/* TAMPC_INTEN: Enable or disable interrupt */ + #define TAMPC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* TAMPER @Bit 0 : Enable or disable interrupt for event TAMPER */ + #define TAMPC_INTEN_TAMPER_Pos (0UL) /*!< Position of TAMPER field. */ + #define TAMPC_INTEN_TAMPER_Msk (0x1UL << TAMPC_INTEN_TAMPER_Pos) /*!< Bit mask of TAMPER field. */ + #define TAMPC_INTEN_TAMPER_Min (0x0UL) /*!< Min enumerator value of TAMPER field. */ + #define TAMPC_INTEN_TAMPER_Max (0x1UL) /*!< Max enumerator value of TAMPER field. */ + #define TAMPC_INTEN_TAMPER_Disabled (0x0UL) /*!< Disable */ + #define TAMPC_INTEN_TAMPER_Enabled (0x1UL) /*!< Enable */ + +/* WRITEERROR @Bit 1 : Enable or disable interrupt for event WRITEERROR */ + #define TAMPC_INTEN_WRITEERROR_Pos (1UL) /*!< Position of WRITEERROR field. */ + #define TAMPC_INTEN_WRITEERROR_Msk (0x1UL << TAMPC_INTEN_WRITEERROR_Pos) /*!< Bit mask of WRITEERROR field. */ + #define TAMPC_INTEN_WRITEERROR_Min (0x0UL) /*!< Min enumerator value of WRITEERROR field. */ + #define TAMPC_INTEN_WRITEERROR_Max (0x1UL) /*!< Max enumerator value of WRITEERROR field. */ + #define TAMPC_INTEN_WRITEERROR_Disabled (0x0UL) /*!< Disable */ + #define TAMPC_INTEN_WRITEERROR_Enabled (0x1UL) /*!< Enable */ + + +/* TAMPC_INTENSET: Enable interrupt */ + #define TAMPC_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* TAMPER @Bit 0 : Write '1' to enable interrupt for event TAMPER */ + #define TAMPC_INTENSET_TAMPER_Pos (0UL) /*!< Position of TAMPER field. */ + #define TAMPC_INTENSET_TAMPER_Msk (0x1UL << TAMPC_INTENSET_TAMPER_Pos) /*!< Bit mask of TAMPER field. */ + #define TAMPC_INTENSET_TAMPER_Min (0x0UL) /*!< Min enumerator value of TAMPER field. */ + #define TAMPC_INTENSET_TAMPER_Max (0x1UL) /*!< Max enumerator value of TAMPER field. */ + #define TAMPC_INTENSET_TAMPER_Set (0x1UL) /*!< Enable */ + #define TAMPC_INTENSET_TAMPER_Disabled (0x0UL) /*!< Read: Disabled */ + #define TAMPC_INTENSET_TAMPER_Enabled (0x1UL) /*!< Read: Enabled */ + +/* WRITEERROR @Bit 1 : Write '1' to enable interrupt for event WRITEERROR */ + #define TAMPC_INTENSET_WRITEERROR_Pos (1UL) /*!< Position of WRITEERROR field. */ + #define TAMPC_INTENSET_WRITEERROR_Msk (0x1UL << TAMPC_INTENSET_WRITEERROR_Pos) /*!< Bit mask of WRITEERROR field. */ + #define TAMPC_INTENSET_WRITEERROR_Min (0x0UL) /*!< Min enumerator value of WRITEERROR field. */ + #define TAMPC_INTENSET_WRITEERROR_Max (0x1UL) /*!< Max enumerator value of WRITEERROR field. */ + #define TAMPC_INTENSET_WRITEERROR_Set (0x1UL) /*!< Enable */ + #define TAMPC_INTENSET_WRITEERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TAMPC_INTENSET_WRITEERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TAMPC_INTENCLR: Disable interrupt */ + #define TAMPC_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* TAMPER @Bit 0 : Write '1' to disable interrupt for event TAMPER */ + #define TAMPC_INTENCLR_TAMPER_Pos (0UL) /*!< Position of TAMPER field. */ + #define TAMPC_INTENCLR_TAMPER_Msk (0x1UL << TAMPC_INTENCLR_TAMPER_Pos) /*!< Bit mask of TAMPER field. */ + #define TAMPC_INTENCLR_TAMPER_Min (0x0UL) /*!< Min enumerator value of TAMPER field. */ + #define TAMPC_INTENCLR_TAMPER_Max (0x1UL) /*!< Max enumerator value of TAMPER field. */ + #define TAMPC_INTENCLR_TAMPER_Clear (0x1UL) /*!< Disable */ + #define TAMPC_INTENCLR_TAMPER_Disabled (0x0UL) /*!< Read: Disabled */ + #define TAMPC_INTENCLR_TAMPER_Enabled (0x1UL) /*!< Read: Enabled */ + +/* WRITEERROR @Bit 1 : Write '1' to disable interrupt for event WRITEERROR */ + #define TAMPC_INTENCLR_WRITEERROR_Pos (1UL) /*!< Position of WRITEERROR field. */ + #define TAMPC_INTENCLR_WRITEERROR_Msk (0x1UL << TAMPC_INTENCLR_WRITEERROR_Pos) /*!< Bit mask of WRITEERROR field. */ + #define TAMPC_INTENCLR_WRITEERROR_Min (0x0UL) /*!< Min enumerator value of WRITEERROR field. */ + #define TAMPC_INTENCLR_WRITEERROR_Max (0x1UL) /*!< Max enumerator value of WRITEERROR field. */ + #define TAMPC_INTENCLR_WRITEERROR_Clear (0x1UL) /*!< Disable */ + #define TAMPC_INTENCLR_WRITEERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TAMPC_INTENCLR_WRITEERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TAMPC_INTPEND: Pending interrupts */ + #define TAMPC_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* TAMPER @Bit 0 : Read pending status of interrupt for event TAMPER */ + #define TAMPC_INTPEND_TAMPER_Pos (0UL) /*!< Position of TAMPER field. */ + #define TAMPC_INTPEND_TAMPER_Msk (0x1UL << TAMPC_INTPEND_TAMPER_Pos) /*!< Bit mask of TAMPER field. */ + #define TAMPC_INTPEND_TAMPER_Min (0x0UL) /*!< Min enumerator value of TAMPER field. */ + #define TAMPC_INTPEND_TAMPER_Max (0x1UL) /*!< Max enumerator value of TAMPER field. */ + #define TAMPC_INTPEND_TAMPER_NotPending (0x0UL) /*!< Read: Not pending */ + #define TAMPC_INTPEND_TAMPER_Pending (0x1UL) /*!< Read: Pending */ + +/* WRITEERROR @Bit 1 : Read pending status of interrupt for event WRITEERROR */ + #define TAMPC_INTPEND_WRITEERROR_Pos (1UL) /*!< Position of WRITEERROR field. */ + #define TAMPC_INTPEND_WRITEERROR_Msk (0x1UL << TAMPC_INTPEND_WRITEERROR_Pos) /*!< Bit mask of WRITEERROR field. */ + #define TAMPC_INTPEND_WRITEERROR_Min (0x0UL) /*!< Min enumerator value of WRITEERROR field. */ + #define TAMPC_INTPEND_WRITEERROR_Max (0x1UL) /*!< Max enumerator value of WRITEERROR field. */ + #define TAMPC_INTPEND_WRITEERROR_NotPending (0x0UL) /*!< Read: Not pending */ + #define TAMPC_INTPEND_WRITEERROR_Pending (0x1UL) /*!< Read: Pending */ + + +/* TAMPC_STATUS: The tamper controller status. */ + #define TAMPC_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ACTIVESHIELD @Bit 0 : Active shield detector detected an error. */ + #define TAMPC_STATUS_ACTIVESHIELD_Pos (0UL) /*!< Position of ACTIVESHIELD field. */ + #define TAMPC_STATUS_ACTIVESHIELD_Msk (0x1UL << TAMPC_STATUS_ACTIVESHIELD_Pos) /*!< Bit mask of ACTIVESHIELD field. */ + #define TAMPC_STATUS_ACTIVESHIELD_Min (0x0UL) /*!< Min enumerator value of ACTIVESHIELD field. */ + #define TAMPC_STATUS_ACTIVESHIELD_Max (0x1UL) /*!< Max enumerator value of ACTIVESHIELD field. */ + #define TAMPC_STATUS_ACTIVESHIELD_NotDetected (0x0UL) /*!< Not detected. */ + #define TAMPC_STATUS_ACTIVESHIELD_Detected (0x1UL) /*!< Detected. */ + +/* PROTECT @Bit 4 : Error detected for the protected signals. */ + #define TAMPC_STATUS_PROTECT_Pos (4UL) /*!< Position of PROTECT field. */ + #define TAMPC_STATUS_PROTECT_Msk (0x1UL << TAMPC_STATUS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ + #define TAMPC_STATUS_PROTECT_Min (0x0UL) /*!< Min enumerator value of PROTECT field. */ + #define TAMPC_STATUS_PROTECT_Max (0x1UL) /*!< Max enumerator value of PROTECT field. */ + #define TAMPC_STATUS_PROTECT_NotDetected (0x0UL) /*!< Not detected. */ + #define TAMPC_STATUS_PROTECT_Detected (0x1UL) /*!< Detected. */ + +/* CRACENTAMP @Bit 5 : CRACEN detected an error. */ + #define TAMPC_STATUS_CRACENTAMP_Pos (5UL) /*!< Position of CRACENTAMP field. */ + #define TAMPC_STATUS_CRACENTAMP_Msk (0x1UL << TAMPC_STATUS_CRACENTAMP_Pos) /*!< Bit mask of CRACENTAMP field. */ + #define TAMPC_STATUS_CRACENTAMP_Min (0x0UL) /*!< Min enumerator value of CRACENTAMP field. */ + #define TAMPC_STATUS_CRACENTAMP_Max (0x1UL) /*!< Max enumerator value of CRACENTAMP field. */ + #define TAMPC_STATUS_CRACENTAMP_NotDetected (0x0UL) /*!< Not detected. */ + #define TAMPC_STATUS_CRACENTAMP_Detected (0x1UL) /*!< Detected. */ + +/* GLITCHSLOWDOMAIN0 @Bit 8 : Slow domain glitch detector 0 detected an error. */ + #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_Pos (8UL) /*!< Position of GLITCHSLOWDOMAIN0 field. */ + #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_Msk (0x1UL << TAMPC_STATUS_GLITCHSLOWDOMAIN0_Pos) /*!< Bit mask of GLITCHSLOWDOMAIN0 + field.*/ + #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_Min (0x0UL) /*!< Min enumerator value of GLITCHSLOWDOMAIN0 field. */ + #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_Max (0x1UL) /*!< Max enumerator value of GLITCHSLOWDOMAIN0 field. */ + #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_NotDetected (0x0UL) /*!< Not detected. */ + #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_Detected (0x1UL) /*!< Detected. */ + +/* GLITCHFASTDOMAIN0 @Bit 12 : Fast domain glitch detector 0 detected an error. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN0_Pos (12UL) /*!< Position of GLITCHFASTDOMAIN0 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN0_Msk (0x1UL << TAMPC_STATUS_GLITCHFASTDOMAIN0_Pos) /*!< Bit mask of GLITCHFASTDOMAIN0 + field.*/ + #define TAMPC_STATUS_GLITCHFASTDOMAIN0_Min (0x0UL) /*!< Min enumerator value of GLITCHFASTDOMAIN0 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN0_Max (0x1UL) /*!< Max enumerator value of GLITCHFASTDOMAIN0 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN0_NotDetected (0x0UL) /*!< Not detected. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN0_Detected (0x1UL) /*!< Detected. */ + +/* GLITCHFASTDOMAIN1 @Bit 13 : Fast domain glitch detector 1 detected an error. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN1_Pos (13UL) /*!< Position of GLITCHFASTDOMAIN1 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN1_Msk (0x1UL << TAMPC_STATUS_GLITCHFASTDOMAIN1_Pos) /*!< Bit mask of GLITCHFASTDOMAIN1 + field.*/ + #define TAMPC_STATUS_GLITCHFASTDOMAIN1_Min (0x0UL) /*!< Min enumerator value of GLITCHFASTDOMAIN1 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN1_Max (0x1UL) /*!< Max enumerator value of GLITCHFASTDOMAIN1 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN1_NotDetected (0x0UL) /*!< Not detected. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN1_Detected (0x1UL) /*!< Detected. */ + +/* GLITCHFASTDOMAIN2 @Bit 14 : Fast domain glitch detector 2 detected an error. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN2_Pos (14UL) /*!< Position of GLITCHFASTDOMAIN2 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN2_Msk (0x1UL << TAMPC_STATUS_GLITCHFASTDOMAIN2_Pos) /*!< Bit mask of GLITCHFASTDOMAIN2 + field.*/ + #define TAMPC_STATUS_GLITCHFASTDOMAIN2_Min (0x0UL) /*!< Min enumerator value of GLITCHFASTDOMAIN2 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN2_Max (0x1UL) /*!< Max enumerator value of GLITCHFASTDOMAIN2 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN2_NotDetected (0x0UL) /*!< Not detected. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN2_Detected (0x1UL) /*!< Detected. */ + +/* GLITCHFASTDOMAIN3 @Bit 15 : Fast domain glitch detector 3 detected an error. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN3_Pos (15UL) /*!< Position of GLITCHFASTDOMAIN3 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN3_Msk (0x1UL << TAMPC_STATUS_GLITCHFASTDOMAIN3_Pos) /*!< Bit mask of GLITCHFASTDOMAIN3 + field.*/ + #define TAMPC_STATUS_GLITCHFASTDOMAIN3_Min (0x0UL) /*!< Min enumerator value of GLITCHFASTDOMAIN3 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN3_Max (0x1UL) /*!< Max enumerator value of GLITCHFASTDOMAIN3 field. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN3_NotDetected (0x0UL) /*!< Not detected. */ + #define TAMPC_STATUS_GLITCHFASTDOMAIN3_Detected (0x1UL) /*!< Detected. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TDM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct TDM_CONFIG_MCK ================================================== */ +/** + * @brief MCK [TDM_CONFIG_MCK] (unspecified) + */ +typedef struct { + __IOM uint32_t EN; /*!< (@ 0x00000000) Master clock generator enable. */ + __IOM uint32_t DIV; /*!< (@ 0x00000004) MCK divider. */ + __IOM uint32_t SRC; /*!< (@ 0x00000008) MCK clock source selection */ +} NRF_TDM_CONFIG_MCK_Type; /*!< Size = 12 (0x00C) */ + +/* TDM_CONFIG_MCK_EN: Master clock generator enable. */ + #define TDM_CONFIG_MCK_EN_ResetValue (0x00000000UL) /*!< Reset value of EN register. */ + +/* MCKEN @Bit 0 : Master clock generator enable. */ + #define TDM_CONFIG_MCK_EN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ + #define TDM_CONFIG_MCK_EN_MCKEN_Msk (0x1UL << TDM_CONFIG_MCK_EN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ + #define TDM_CONFIG_MCK_EN_MCKEN_Min (0x0UL) /*!< Min enumerator value of MCKEN field. */ + #define TDM_CONFIG_MCK_EN_MCKEN_Max (0x1UL) /*!< Max enumerator value of MCKEN field. */ + #define TDM_CONFIG_MCK_EN_MCKEN_Disabled (0x0UL) /*!< Master clock generator disabled. */ + #define TDM_CONFIG_MCK_EN_MCKEN_Enabled (0x1UL) /*!< Master clock generator enabled. */ + + +/* TDM_CONFIG_MCK_DIV: MCK divider. */ + #define TDM_CONFIG_MCK_DIV_ResetValue (0x00000000UL) /*!< Reset value of DIV register. */ + +/* DIV @Bits 0..31 : MCK frequency configuration */ + #define TDM_CONFIG_MCK_DIV_DIV_Pos (0UL) /*!< Position of DIV field. */ + #define TDM_CONFIG_MCK_DIV_DIV_Msk (0xFFFFFFFFUL << TDM_CONFIG_MCK_DIV_DIV_Pos) /*!< Bit mask of DIV field. */ + #define TDM_CONFIG_MCK_DIV_DIV_Min (0x020C0000UL) /*!< Min enumerator value of DIV field. */ + #define TDM_CONFIG_MCK_DIV_DIV_Max (0x80000000UL) /*!< Max enumerator value of DIV field. */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV2 (0x80000000UL) /*!< CK divided by 2 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV3 (0x50000000UL) /*!< CK divided by 3 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV4 (0x40000000UL) /*!< CK divided by 4 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV5 (0x30000000UL) /*!< CK divided by 5 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV6 (0x28000000UL) /*!< CK divided by 6 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV8 (0x20000000UL) /*!< CK divided by 8 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV10 (0x18000000UL) /*!< CK divided by 10 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV11 (0x16000000UL) /*!< CK divided by 11 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV15 (0x11000000UL) /*!< CK divided by 15 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV16 (0x10000000UL) /*!< CK divided by 16 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV21 (0x0C000000UL) /*!< CK divided by 21 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV23 (0x0B000000UL) /*!< CK divided by 23 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV30 (0x08800000UL) /*!< CK divided by 30 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV31 (0x08400000UL) /*!< CK divided by 31 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV32 (0x08000000UL) /*!< CK divided by 32 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV42 (0x06000000UL) /*!< CK divided by 42 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV63 (0x04100000UL) /*!< CK divided by 63 */ + #define TDM_CONFIG_MCK_DIV_DIV_CKDIV125 (0x020C0000UL) /*!< CK divided by 125 */ + + +/* TDM_CONFIG_MCK_SRC: MCK clock source selection */ + #define TDM_CONFIG_MCK_SRC_ResetValue (0x00000000UL) /*!< Reset value of SRC register. */ + +/* CLKSRC @Bit 0 : Clock source selection */ + #define TDM_CONFIG_MCK_SRC_CLKSRC_Pos (0UL) /*!< Position of CLKSRC field. */ + #define TDM_CONFIG_MCK_SRC_CLKSRC_Msk (0x1UL << TDM_CONFIG_MCK_SRC_CLKSRC_Pos) /*!< Bit mask of CLKSRC field. */ + #define TDM_CONFIG_MCK_SRC_CLKSRC_Min (0x0UL) /*!< Min enumerator value of CLKSRC field. */ + #define TDM_CONFIG_MCK_SRC_CLKSRC_Max (0x1UL) /*!< Max enumerator value of CLKSRC field. */ + #define TDM_CONFIG_MCK_SRC_CLKSRC_PCLK (0x0UL) /*!< Peripheral clock (instantiation table shows the TDM PCLK frequency) */ + #define TDM_CONFIG_MCK_SRC_CLKSRC_PCLK32M (0x0UL) /*!< Legacy enumerator provided for backward compatibility */ + #define TDM_CONFIG_MCK_SRC_CLKSRC_ACLK (0x1UL) /*!< Audio PLL clock */ + +/* BYPASS @Bit 8 : Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no + effect. */ + + #define TDM_CONFIG_MCK_SRC_BYPASS_Pos (8UL) /*!< Position of BYPASS field. */ + #define TDM_CONFIG_MCK_SRC_BYPASS_Msk (0x1UL << TDM_CONFIG_MCK_SRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ + #define TDM_CONFIG_MCK_SRC_BYPASS_Min (0x0UL) /*!< Min enumerator value of BYPASS field. */ + #define TDM_CONFIG_MCK_SRC_BYPASS_Max (0x1UL) /*!< Max enumerator value of BYPASS field. */ + #define TDM_CONFIG_MCK_SRC_BYPASS_Disable (0x0UL) /*!< Disable bypass */ + #define TDM_CONFIG_MCK_SRC_BYPASS_Enable (0x1UL) /*!< Enable bypass */ + + + +/* ================================================== Struct TDM_CONFIG_SCK ================================================== */ +/** + * @brief SCK [TDM_CONFIG_SCK] (unspecified) + */ +typedef struct { + __IOM uint32_t DIV; /*!< (@ 0x00000000) SCK divider. */ + __IOM uint32_t SRC; /*!< (@ 0x00000004) SCK clock source selection */ + __IOM uint32_t POLARITY; /*!< (@ 0x00000008) Set SCK Polarity. */ +} NRF_TDM_CONFIG_SCK_Type; /*!< Size = 12 (0x00C) */ + +/* TDM_CONFIG_SCK_DIV: SCK divider. */ + #define TDM_CONFIG_SCK_DIV_ResetValue (0x00000000UL) /*!< Reset value of DIV register. */ + +/* SCKDIV @Bits 0..31 : SCK frequency configuration */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_Pos (0UL) /*!< Position of SCKDIV field. */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_Msk (0xFFFFFFFFUL << TDM_CONFIG_SCK_DIV_SCKDIV_Pos) /*!< Bit mask of SCKDIV field. */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_Min (0x020C0000UL) /*!< Min enumerator value of SCKDIV field. */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_Max (0x80000000UL) /*!< Max enumerator value of SCKDIV field. */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV2 (0x80000000UL) /*!< CK divided by 2 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV3 (0x50000000UL) /*!< CK divided by 3 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV4 (0x40000000UL) /*!< CK divided by 4 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV5 (0x30000000UL) /*!< CK divided by 5 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV6 (0x28000000UL) /*!< CK divided by 6 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV8 (0x20000000UL) /*!< CK divided by 8 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV10 (0x18000000UL) /*!< CK divided by 10 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV11 (0x16000000UL) /*!< CK divided by 11 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV15 (0x11000000UL) /*!< CK divided by 15 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV16 (0x10000000UL) /*!< CK divided by 16 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV21 (0x0C000000UL) /*!< CK divided by 21 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV23 (0x0B000000UL) /*!< CK divided by 23 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV30 (0x08800000UL) /*!< CK divided by 30 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV31 (0x08400000UL) /*!< CK divided by 31 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV32 (0x08000000UL) /*!< CK divided by 32 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV42 (0x06000000UL) /*!< CK divided by 42 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV63 (0x04100000UL) /*!< CK divided by 63 */ + #define TDM_CONFIG_SCK_DIV_SCKDIV_CKDIV125 (0x020C0000UL) /*!< CK divided by 125 */ + + +/* TDM_CONFIG_SCK_SRC: SCK clock source selection */ + #define TDM_CONFIG_SCK_SRC_ResetValue (0x00000000UL) /*!< Reset value of SRC register. */ + +/* CLKSRC @Bit 0 : Clock source selection */ + #define TDM_CONFIG_SCK_SRC_CLKSRC_Pos (0UL) /*!< Position of CLKSRC field. */ + #define TDM_CONFIG_SCK_SRC_CLKSRC_Msk (0x1UL << TDM_CONFIG_SCK_SRC_CLKSRC_Pos) /*!< Bit mask of CLKSRC field. */ + #define TDM_CONFIG_SCK_SRC_CLKSRC_Min (0x0UL) /*!< Min enumerator value of CLKSRC field. */ + #define TDM_CONFIG_SCK_SRC_CLKSRC_Max (0x1UL) /*!< Max enumerator value of CLKSRC field. */ + #define TDM_CONFIG_SCK_SRC_CLKSRC_PCLK (0x0UL) /*!< Peripheral clock (instantiation table shows the TDM PCLK frequency) */ + #define TDM_CONFIG_SCK_SRC_CLKSRC_ACLK (0x1UL) /*!< Audio PLL clock */ + +/* BYPASS @Bit 8 : Bypass clock generator. SCK will be equal to source input. If bypass is enabled the SCKFREQ setting has no + effect. */ + + #define TDM_CONFIG_SCK_SRC_BYPASS_Pos (8UL) /*!< Position of BYPASS field. */ + #define TDM_CONFIG_SCK_SRC_BYPASS_Msk (0x1UL << TDM_CONFIG_SCK_SRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ + #define TDM_CONFIG_SCK_SRC_BYPASS_Min (0x0UL) /*!< Min enumerator value of BYPASS field. */ + #define TDM_CONFIG_SCK_SRC_BYPASS_Max (0x1UL) /*!< Max enumerator value of BYPASS field. */ + #define TDM_CONFIG_SCK_SRC_BYPASS_Disable (0x0UL) /*!< Disable bypass */ + #define TDM_CONFIG_SCK_SRC_BYPASS_Enable (0x1UL) /*!< Enable bypass */ + + +/* TDM_CONFIG_SCK_POLARITY: Set SCK Polarity. */ + #define TDM_CONFIG_SCK_POLARITY_ResetValue (0x00000000UL) /*!< Reset value of POLARITY register. */ + +/* SCKPOLARITY @Bit 0 : Set the polarity of the active SCK edge. */ + #define TDM_CONFIG_SCK_POLARITY_SCKPOLARITY_Pos (0UL) /*!< Position of SCKPOLARITY field. */ + #define TDM_CONFIG_SCK_POLARITY_SCKPOLARITY_Msk (0x1UL << TDM_CONFIG_SCK_POLARITY_SCKPOLARITY_Pos) /*!< Bit mask of + SCKPOLARITY field.*/ + #define TDM_CONFIG_SCK_POLARITY_SCKPOLARITY_Min (0x0UL) /*!< Min enumerator value of SCKPOLARITY field. */ + #define TDM_CONFIG_SCK_POLARITY_SCKPOLARITY_Max (0x1UL) /*!< Max enumerator value of SCKPOLARITY field. */ + #define TDM_CONFIG_SCK_POLARITY_SCKPOLARITY_PosEdge (0x0UL) /*!< TX data is written to the SDOUT pin on the falling edge of + SCK, ready to be received on the rising edge of SCK.*/ + #define TDM_CONFIG_SCK_POLARITY_SCKPOLARITY_NegEdge (0x1UL) /*!< TX data is written to the SDOUT pin on the rising edge of + SCK, ready to be received on the falling edge of SCK.*/ + + + +/* ================================================ Struct TDM_CONFIG_CHANNEL ================================================ */ +/** + * @brief CHANNEL [TDM_CONFIG_CHANNEL] (unspecified) + */ +typedef struct { + __IOM uint32_t MASK; /*!< (@ 0x00000000) Select which channels are to be used. */ + __IOM uint32_t NUM; /*!< (@ 0x00000004) Select number of channels. */ + __IOM uint32_t DELAY; /*!< (@ 0x00000008) Set channel delay. */ +} NRF_TDM_CONFIG_CHANNEL_Type; /*!< Size = 12 (0x00C) */ + +/* TDM_CONFIG_CHANNEL_MASK: Select which channels are to be used. */ + #define TDM_CONFIG_CHANNEL_MASK_ResetValue (0x00FF00FFUL) /*!< Reset value of MASK register. */ + +/* Rx0Enable @Bit 0 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Rx0Enable_Pos (0UL) /*!< Position of Rx0Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx0Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Rx0Enable_Pos) /*!< Bit mask of Rx0Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Rx0Enable_Min (0x0UL) /*!< Min enumerator value of Rx0Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx0Enable_Max (0x1UL) /*!< Max enumerator value of Rx0Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx0Enable_Disable (0x0UL) /*!< Disable Rx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx0Enable_Enable (0x1UL) /*!< Enable Rx channel data. */ + +/* Rx1Enable @Bit 1 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Rx1Enable_Pos (1UL) /*!< Position of Rx1Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx1Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Rx1Enable_Pos) /*!< Bit mask of Rx1Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Rx1Enable_Min (0x0UL) /*!< Min enumerator value of Rx1Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx1Enable_Max (0x1UL) /*!< Max enumerator value of Rx1Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx1Enable_Disable (0x0UL) /*!< Disable Rx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx1Enable_Enable (0x1UL) /*!< Enable Rx channel data. */ + +/* Rx2Enable @Bit 2 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Rx2Enable_Pos (2UL) /*!< Position of Rx2Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx2Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Rx2Enable_Pos) /*!< Bit mask of Rx2Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Rx2Enable_Min (0x0UL) /*!< Min enumerator value of Rx2Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx2Enable_Max (0x1UL) /*!< Max enumerator value of Rx2Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx2Enable_Disable (0x0UL) /*!< Disable Rx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx2Enable_Enable (0x1UL) /*!< Enable Rx channel data. */ + +/* Rx3Enable @Bit 3 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Rx3Enable_Pos (3UL) /*!< Position of Rx3Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx3Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Rx3Enable_Pos) /*!< Bit mask of Rx3Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Rx3Enable_Min (0x0UL) /*!< Min enumerator value of Rx3Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx3Enable_Max (0x1UL) /*!< Max enumerator value of Rx3Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx3Enable_Disable (0x0UL) /*!< Disable Rx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx3Enable_Enable (0x1UL) /*!< Enable Rx channel data. */ + +/* Rx4Enable @Bit 4 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Rx4Enable_Pos (4UL) /*!< Position of Rx4Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx4Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Rx4Enable_Pos) /*!< Bit mask of Rx4Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Rx4Enable_Min (0x0UL) /*!< Min enumerator value of Rx4Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx4Enable_Max (0x1UL) /*!< Max enumerator value of Rx4Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx4Enable_Disable (0x0UL) /*!< Disable Rx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx4Enable_Enable (0x1UL) /*!< Enable Rx channel data. */ + +/* Rx5Enable @Bit 5 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Rx5Enable_Pos (5UL) /*!< Position of Rx5Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx5Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Rx5Enable_Pos) /*!< Bit mask of Rx5Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Rx5Enable_Min (0x0UL) /*!< Min enumerator value of Rx5Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx5Enable_Max (0x1UL) /*!< Max enumerator value of Rx5Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx5Enable_Disable (0x0UL) /*!< Disable Rx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx5Enable_Enable (0x1UL) /*!< Enable Rx channel data. */ + +/* Rx6Enable @Bit 6 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Rx6Enable_Pos (6UL) /*!< Position of Rx6Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx6Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Rx6Enable_Pos) /*!< Bit mask of Rx6Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Rx6Enable_Min (0x0UL) /*!< Min enumerator value of Rx6Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx6Enable_Max (0x1UL) /*!< Max enumerator value of Rx6Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx6Enable_Disable (0x0UL) /*!< Disable Rx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx6Enable_Enable (0x1UL) /*!< Enable Rx channel data. */ + +/* Rx7Enable @Bit 7 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Rx7Enable_Pos (7UL) /*!< Position of Rx7Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx7Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Rx7Enable_Pos) /*!< Bit mask of Rx7Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Rx7Enable_Min (0x0UL) /*!< Min enumerator value of Rx7Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx7Enable_Max (0x1UL) /*!< Max enumerator value of Rx7Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx7Enable_Disable (0x0UL) /*!< Disable Rx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Rx7Enable_Enable (0x1UL) /*!< Enable Rx channel data. */ + +/* Tx0Enable @Bit 16 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Tx0Enable_Pos (16UL) /*!< Position of Tx0Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx0Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Tx0Enable_Pos) /*!< Bit mask of Tx0Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Tx0Enable_Min (0x0UL) /*!< Min enumerator value of Tx0Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx0Enable_Max (0x1UL) /*!< Max enumerator value of Tx0Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx0Enable_Disable (0x0UL) /*!< Disable Tx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx0Enable_Enable (0x1UL) /*!< Enable Tx channel data. */ + +/* Tx1Enable @Bit 17 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Tx1Enable_Pos (17UL) /*!< Position of Tx1Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx1Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Tx1Enable_Pos) /*!< Bit mask of Tx1Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Tx1Enable_Min (0x0UL) /*!< Min enumerator value of Tx1Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx1Enable_Max (0x1UL) /*!< Max enumerator value of Tx1Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx1Enable_Disable (0x0UL) /*!< Disable Tx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx1Enable_Enable (0x1UL) /*!< Enable Tx channel data. */ + +/* Tx2Enable @Bit 18 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Tx2Enable_Pos (18UL) /*!< Position of Tx2Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx2Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Tx2Enable_Pos) /*!< Bit mask of Tx2Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Tx2Enable_Min (0x0UL) /*!< Min enumerator value of Tx2Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx2Enable_Max (0x1UL) /*!< Max enumerator value of Tx2Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx2Enable_Disable (0x0UL) /*!< Disable Tx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx2Enable_Enable (0x1UL) /*!< Enable Tx channel data. */ + +/* Tx3Enable @Bit 19 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Tx3Enable_Pos (19UL) /*!< Position of Tx3Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx3Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Tx3Enable_Pos) /*!< Bit mask of Tx3Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Tx3Enable_Min (0x0UL) /*!< Min enumerator value of Tx3Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx3Enable_Max (0x1UL) /*!< Max enumerator value of Tx3Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx3Enable_Disable (0x0UL) /*!< Disable Tx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx3Enable_Enable (0x1UL) /*!< Enable Tx channel data. */ + +/* Tx4Enable @Bit 20 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Tx4Enable_Pos (20UL) /*!< Position of Tx4Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx4Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Tx4Enable_Pos) /*!< Bit mask of Tx4Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Tx4Enable_Min (0x0UL) /*!< Min enumerator value of Tx4Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx4Enable_Max (0x1UL) /*!< Max enumerator value of Tx4Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx4Enable_Disable (0x0UL) /*!< Disable Tx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx4Enable_Enable (0x1UL) /*!< Enable Tx channel data. */ + +/* Tx5Enable @Bit 21 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Tx5Enable_Pos (21UL) /*!< Position of Tx5Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx5Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Tx5Enable_Pos) /*!< Bit mask of Tx5Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Tx5Enable_Min (0x0UL) /*!< Min enumerator value of Tx5Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx5Enable_Max (0x1UL) /*!< Max enumerator value of Tx5Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx5Enable_Disable (0x0UL) /*!< Disable Tx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx5Enable_Enable (0x1UL) /*!< Enable Tx channel data. */ + +/* Tx6Enable @Bit 22 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Tx6Enable_Pos (22UL) /*!< Position of Tx6Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx6Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Tx6Enable_Pos) /*!< Bit mask of Tx6Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Tx6Enable_Min (0x0UL) /*!< Min enumerator value of Tx6Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx6Enable_Max (0x1UL) /*!< Max enumerator value of Tx6Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx6Enable_Disable (0x0UL) /*!< Disable Tx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx6Enable_Enable (0x1UL) /*!< Enable Tx channel data. */ + +/* Tx7Enable @Bit 23 : (unspecified) */ + #define TDM_CONFIG_CHANNEL_MASK_Tx7Enable_Pos (23UL) /*!< Position of Tx7Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx7Enable_Msk (0x1UL << TDM_CONFIG_CHANNEL_MASK_Tx7Enable_Pos) /*!< Bit mask of Tx7Enable + field.*/ + #define TDM_CONFIG_CHANNEL_MASK_Tx7Enable_Min (0x0UL) /*!< Min enumerator value of Tx7Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx7Enable_Max (0x1UL) /*!< Max enumerator value of Tx7Enable field. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx7Enable_Disable (0x0UL) /*!< Disable Tx channel data. */ + #define TDM_CONFIG_CHANNEL_MASK_Tx7Enable_Enable (0x1UL) /*!< Enable Tx channel data. */ + + +/* TDM_CONFIG_CHANNEL_NUM: Select number of channels. */ + #define TDM_CONFIG_CHANNEL_NUM_ResetValue (0x00000001UL) /*!< Reset value of NUM register. */ + +/* NUM @Bits 0..2 : Select number of channels. */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Pos (0UL) /*!< Position of NUM field. */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Msk (0x7UL << TDM_CONFIG_CHANNEL_NUM_NUM_Pos) /*!< Bit mask of NUM field. */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Min (0x0UL) /*!< Min enumerator value of NUM field. */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Max (0x7UL) /*!< Max enumerator value of NUM field. */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Tdm1Ch (0x0UL) /*!< 1-channel audio (mono). */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Tdm2Ch (0x1UL) /*!< 2-channel audio (stereo). */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Tdm3Ch (0x2UL) /*!< 3-channel audio. */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Tdm4Ch (0x3UL) /*!< 4-channel audio. */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Tdm5Ch (0x4UL) /*!< 5-channel audio. */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Tdm6Ch (0x5UL) /*!< 6-channel audio. */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Tdm7Ch (0x6UL) /*!< 7-channel audio. */ + #define TDM_CONFIG_CHANNEL_NUM_NUM_Tdm8Ch (0x7UL) /*!< 8-channel audio. */ + + +/* TDM_CONFIG_CHANNEL_DELAY: Set channel delay. */ + #define TDM_CONFIG_CHANNEL_DELAY_ResetValue (0x00000001UL) /*!< Reset value of DELAY register. */ + +/* DELAY @Bits 0..1 : Configure number of inactive SCK periods from edge of FSYNC until start of first data bit. */ + #define TDM_CONFIG_CHANNEL_DELAY_DELAY_Pos (0UL) /*!< Position of DELAY field. */ + #define TDM_CONFIG_CHANNEL_DELAY_DELAY_Msk (0x3UL << TDM_CONFIG_CHANNEL_DELAY_DELAY_Pos) /*!< Bit mask of DELAY field. */ + #define TDM_CONFIG_CHANNEL_DELAY_DELAY_Min (0x0UL) /*!< Min enumerator value of DELAY field. */ + #define TDM_CONFIG_CHANNEL_DELAY_DELAY_Max (0x2UL) /*!< Max enumerator value of DELAY field. */ + #define TDM_CONFIG_CHANNEL_DELAY_DELAY_Delay0Ck (0x0UL) /*!< No delay. Used with I2S DSP/Aligned format. */ + #define TDM_CONFIG_CHANNEL_DELAY_DELAY_Delay1Ck (0x1UL) /*!< One clock pulse delay. Used with Original I2S format. */ + #define TDM_CONFIG_CHANNEL_DELAY_DELAY_Delay2Ck (0x2UL) /*!< Two clock pulses delay. */ + + + +/* ================================================= Struct TDM_CONFIG_FSYNC ================================================= */ +/** + * @brief FSYNC [TDM_CONFIG_FSYNC] (unspecified) + */ +typedef struct { + __IOM uint32_t POLARITY; /*!< (@ 0x00000000) Set FSYNC Polarity. */ + __IOM uint32_t DURATION; /*!< (@ 0x00000004) Set FSYNC duration. */ +} NRF_TDM_CONFIG_FSYNC_Type; /*!< Size = 8 (0x008) */ + +/* TDM_CONFIG_FSYNC_POLARITY: Set FSYNC Polarity. */ + #define TDM_CONFIG_FSYNC_POLARITY_ResetValue (0x00000000UL) /*!< Reset value of POLARITY register. */ + +/* POLARITY @Bit 0 : Set the polarity of the active period of FSYNC. */ + #define TDM_CONFIG_FSYNC_POLARITY_POLARITY_Pos (0UL) /*!< Position of POLARITY field. */ + #define TDM_CONFIG_FSYNC_POLARITY_POLARITY_Msk (0x1UL << TDM_CONFIG_FSYNC_POLARITY_POLARITY_Pos) /*!< Bit mask of POLARITY + field.*/ + #define TDM_CONFIG_FSYNC_POLARITY_POLARITY_Min (0x0UL) /*!< Min enumerator value of POLARITY field. */ + #define TDM_CONFIG_FSYNC_POLARITY_POLARITY_Max (0x1UL) /*!< Max enumerator value of POLARITY field. */ + #define TDM_CONFIG_FSYNC_POLARITY_POLARITY_NegEdge (0x0UL) /*!< Frame starts at falling edge of FSYNC. */ + #define TDM_CONFIG_FSYNC_POLARITY_POLARITY_PosEdge (0x1UL) /*!< Frame starts at rising edge of FSYNC. */ + + +/* TDM_CONFIG_FSYNC_DURATION: Set FSYNC duration. */ + #define TDM_CONFIG_FSYNC_DURATION_ResetValue (0x00000001UL) /*!< Reset value of DURATION register. */ + +/* DURATION @Bit 0 : Set the duration of the active period of FSYNC in Master mode. */ + #define TDM_CONFIG_FSYNC_DURATION_DURATION_Pos (0UL) /*!< Position of DURATION field. */ + #define TDM_CONFIG_FSYNC_DURATION_DURATION_Msk (0x1UL << TDM_CONFIG_FSYNC_DURATION_DURATION_Pos) /*!< Bit mask of DURATION + field.*/ + #define TDM_CONFIG_FSYNC_DURATION_DURATION_Min (0x0UL) /*!< Min enumerator value of DURATION field. */ + #define TDM_CONFIG_FSYNC_DURATION_DURATION_Max (0x1UL) /*!< Max enumerator value of DURATION field. */ + #define TDM_CONFIG_FSYNC_DURATION_DURATION_Sck (0x0UL) /*!< FSYNC is active for the duration of one SCK period */ + #define TDM_CONFIG_FSYNC_DURATION_DURATION_Channel (0x1UL) /*!< FSYNC is active for the duration of channel */ + + + +/* ==================================================== Struct TDM_CONFIG ==================================================== */ +/** + * @brief CONFIG [TDM_CONFIG] Configuration registers. + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) Mode configuration */ + __IOM uint32_t RXTXEN; /*!< (@ 0x00000004) Reception (RX) and transmission (TX) enable. */ + __IOM NRF_TDM_CONFIG_MCK_Type MCK; /*!< (@ 0x00000008) (unspecified) */ + __IOM NRF_TDM_CONFIG_SCK_Type SCK; /*!< (@ 0x00000014) (unspecified) */ + __IOM uint32_t SWIDTH; /*!< (@ 0x00000020) Sample and word width configuration. */ + __IOM uint32_t ALIGN; /*!< (@ 0x00000024) Alignment of sample within the audio data word. */ + __IOM NRF_TDM_CONFIG_CHANNEL_Type CHANNEL; /*!< (@ 0x00000028) (unspecified) */ + __IOM NRF_TDM_CONFIG_FSYNC_Type FSYNC; /*!< (@ 0x00000034) (unspecified) */ + __IOM uint32_t ORS; /*!< (@ 0x0000003C) Over-read sample: Extra sample(s) to be transmitted + after TXD.MAXCNT bytes have been transmitted.*/ +} NRF_TDM_CONFIG_Type; /*!< Size = 64 (0x040) */ + +/* TDM_CONFIG_MODE: Mode configuration */ + #define TDM_CONFIG_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* MODE @Bit 0 : Mode configuration */ + #define TDM_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define TDM_CONFIG_MODE_MODE_Msk (0x1UL << TDM_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define TDM_CONFIG_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define TDM_CONFIG_MODE_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define TDM_CONFIG_MODE_MODE_Master (0x0UL) /*!< Master mode. SCK and FSYNC are created internally and output on + PSEL.SCK and PSEL.FSYNC.*/ + #define TDM_CONFIG_MODE_MODE_Slave (0x1UL) /*!< Slave mode. SCK and FSYNC are received on PSEL.SCK and PSEL.FSYNC. */ + + +/* TDM_CONFIG_RXTXEN: Reception (RX) and transmission (TX) enable. */ + #define TDM_CONFIG_RXTXEN_ResetValue (0x00000000UL) /*!< Reset value of RXTXEN register. */ + +/* RXTXEN @Bits 0..1 : Enable reception or transmission. */ + #define TDM_CONFIG_RXTXEN_RXTXEN_Pos (0UL) /*!< Position of RXTXEN field. */ + #define TDM_CONFIG_RXTXEN_RXTXEN_Msk (0x3UL << TDM_CONFIG_RXTXEN_RXTXEN_Pos) /*!< Bit mask of RXTXEN field. */ + #define TDM_CONFIG_RXTXEN_RXTXEN_Min (0x0UL) /*!< Min enumerator value of RXTXEN field. */ + #define TDM_CONFIG_RXTXEN_RXTXEN_Max (0x2UL) /*!< Max enumerator value of RXTXEN field. */ + #define TDM_CONFIG_RXTXEN_RXTXEN_Duplex (0x0UL) /*!< Enable both reception and transmission. Data will be written to the + RXD.PTR address and data transmitted from the TXD.PTR address.*/ + #define TDM_CONFIG_RXTXEN_RXTXEN_Rx (0x1UL) /*!< Enable reception, disable transmission. Data will be written to the + RXD.PTR address.*/ + #define TDM_CONFIG_RXTXEN_RXTXEN_Tx (0x2UL) /*!< Enable transmission, disable reception. Data will be transmitted from + the TXD.PTR address.*/ + + +/* TDM_CONFIG_SWIDTH: Sample and word width configuration. */ + #define TDM_CONFIG_SWIDTH_ResetValue (0x00000001UL) /*!< Reset value of SWIDTH register. */ + +/* SWIDTH @Bits 0..2 : Sample and word width */ + #define TDM_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ + #define TDM_CONFIG_SWIDTH_SWIDTH_Msk (0x7UL << TDM_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ + #define TDM_CONFIG_SWIDTH_SWIDTH_Min (0x0UL) /*!< Min enumerator value of SWIDTH field. */ + #define TDM_CONFIG_SWIDTH_SWIDTH_Max (0x7UL) /*!< Max enumerator value of SWIDTH field. */ + #define TDM_CONFIG_SWIDTH_SWIDTH_8Bit (0x0UL) /*!< 8 bit sample in an 8-bit word. */ + #define TDM_CONFIG_SWIDTH_SWIDTH_16Bit (0x1UL) /*!< 16 bit sample in a 16-bit word. */ + #define TDM_CONFIG_SWIDTH_SWIDTH_24Bit (0x2UL) /*!< 24 bit sample in a 24-bit word. */ + #define TDM_CONFIG_SWIDTH_SWIDTH_32Bit (0x3UL) /*!< 32 bit sample in a 32-bit word. */ + #define TDM_CONFIG_SWIDTH_SWIDTH_8BitIn16 (0x4UL) /*!< 8 bit sample in a 16-bit word. */ + #define TDM_CONFIG_SWIDTH_SWIDTH_8BitIn32 (0x5UL) /*!< 8 bit sample in a 32-bit word. */ + #define TDM_CONFIG_SWIDTH_SWIDTH_16BitIn32 (0x6UL) /*!< 16 bit sample in a 32-bit word. */ + #define TDM_CONFIG_SWIDTH_SWIDTH_24BitIn32 (0x7UL) /*!< 24 bit sample in a 32-bit word. */ + + +/* TDM_CONFIG_ALIGN: Alignment of sample within the audio data word. */ + #define TDM_CONFIG_ALIGN_ResetValue (0x00000000UL) /*!< Reset value of ALIGN register. */ + +/* ALIGN @Bit 0 : Alignment of sample within the audio data word. */ + #define TDM_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ + #define TDM_CONFIG_ALIGN_ALIGN_Msk (0x1UL << TDM_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ + #define TDM_CONFIG_ALIGN_ALIGN_Min (0x0UL) /*!< Min enumerator value of ALIGN field. */ + #define TDM_CONFIG_ALIGN_ALIGN_Max (0x1UL) /*!< Max enumerator value of ALIGN field. */ + #define TDM_CONFIG_ALIGN_ALIGN_Left (0x0UL) /*!< Left-aligned. */ + #define TDM_CONFIG_ALIGN_ALIGN_Right (0x1UL) /*!< Right-aligned. */ + + +/* TDM_CONFIG_ORS: Over-read sample: Extra sample(s) to be transmitted after TXD.MAXCNT bytes have been transmitted. */ + #define TDM_CONFIG_ORS_ResetValue (0x00000000UL) /*!< Reset value of ORS register. */ + +/* ORS @Bits 0..31 : Data to transmit after TXD.MAXCNT bytes have been transmitted. */ + #define TDM_CONFIG_ORS_ORS_Pos (0UL) /*!< Position of ORS field. */ + #define TDM_CONFIG_ORS_ORS_Msk (0xFFFFFFFFUL << TDM_CONFIG_ORS_ORS_Pos) /*!< Bit mask of ORS field. */ + + + +/* ===================================================== Struct TDM_PSEL ===================================================== */ +/** + * @brief PSEL [TDM_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal */ + __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal */ + __IOM uint32_t FSYNC; /*!< (@ 0x00000008) Pin select for FSYNC signal */ + __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal */ + __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal */ +} NRF_TDM_PSEL_Type; /*!< Size = 20 (0x014) */ + +/* TDM_PSEL_MCK: Pin select for MCK signal */ + #define TDM_PSEL_MCK_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MCK register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TDM_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TDM_PSEL_MCK_PIN_Msk (0x1FUL << TDM_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TDM_PSEL_MCK_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TDM_PSEL_MCK_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define TDM_PSEL_MCK_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TDM_PSEL_MCK_PORT_Msk (0xFUL << TDM_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TDM_PSEL_MCK_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TDM_PSEL_MCK_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TDM_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TDM_PSEL_MCK_CONNECT_Msk (0x1UL << TDM_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TDM_PSEL_MCK_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TDM_PSEL_MCK_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TDM_PSEL_MCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TDM_PSEL_MCK_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* TDM_PSEL_SCK: Pin select for SCK signal */ + #define TDM_PSEL_SCK_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SCK register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TDM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TDM_PSEL_SCK_PIN_Msk (0x1FUL << TDM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TDM_PSEL_SCK_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TDM_PSEL_SCK_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define TDM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TDM_PSEL_SCK_PORT_Msk (0xFUL << TDM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TDM_PSEL_SCK_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TDM_PSEL_SCK_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TDM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TDM_PSEL_SCK_CONNECT_Msk (0x1UL << TDM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TDM_PSEL_SCK_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TDM_PSEL_SCK_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TDM_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TDM_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* TDM_PSEL_FSYNC: Pin select for FSYNC signal */ + #define TDM_PSEL_FSYNC_ResetValue (0xFFFFFFFFUL) /*!< Reset value of FSYNC register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TDM_PSEL_FSYNC_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TDM_PSEL_FSYNC_PIN_Msk (0x1FUL << TDM_PSEL_FSYNC_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TDM_PSEL_FSYNC_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TDM_PSEL_FSYNC_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define TDM_PSEL_FSYNC_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TDM_PSEL_FSYNC_PORT_Msk (0xFUL << TDM_PSEL_FSYNC_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TDM_PSEL_FSYNC_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TDM_PSEL_FSYNC_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TDM_PSEL_FSYNC_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TDM_PSEL_FSYNC_CONNECT_Msk (0x1UL << TDM_PSEL_FSYNC_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TDM_PSEL_FSYNC_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TDM_PSEL_FSYNC_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TDM_PSEL_FSYNC_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TDM_PSEL_FSYNC_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* TDM_PSEL_SDIN: Pin select for SDIN signal */ + #define TDM_PSEL_SDIN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SDIN register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TDM_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TDM_PSEL_SDIN_PIN_Msk (0x1FUL << TDM_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TDM_PSEL_SDIN_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TDM_PSEL_SDIN_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define TDM_PSEL_SDIN_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TDM_PSEL_SDIN_PORT_Msk (0xFUL << TDM_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TDM_PSEL_SDIN_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TDM_PSEL_SDIN_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TDM_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TDM_PSEL_SDIN_CONNECT_Msk (0x1UL << TDM_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TDM_PSEL_SDIN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TDM_PSEL_SDIN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TDM_PSEL_SDIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TDM_PSEL_SDIN_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* TDM_PSEL_SDOUT: Pin select for SDOUT signal */ + #define TDM_PSEL_SDOUT_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SDOUT register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TDM_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TDM_PSEL_SDOUT_PIN_Msk (0x1FUL << TDM_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TDM_PSEL_SDOUT_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TDM_PSEL_SDOUT_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define TDM_PSEL_SDOUT_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TDM_PSEL_SDOUT_PORT_Msk (0xFUL << TDM_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TDM_PSEL_SDOUT_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TDM_PSEL_SDOUT_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TDM_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TDM_PSEL_SDOUT_CONNECT_Msk (0x1UL << TDM_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TDM_PSEL_SDOUT_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TDM_PSEL_SDOUT_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TDM_PSEL_SDOUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TDM_PSEL_SDOUT_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ===================================================== Struct TDM_RXD ====================================================== */ +/** + * @brief RXD [TDM_RXD] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IM uint32_t RESERVED1; + __IOM uint32_t MODE; /*!< (@ 0x00000018) Configure EasyDMA mode */ + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_TDM_RXD_Type; /*!< Size = 36 (0x024) */ + +/* TDM_RXD_PTR: RAM buffer start address */ + #define TDM_RXD_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define TDM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define TDM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TDM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* TDM_RXD_MAXCNT: Maximum number of bytes in channel buffer */ + #define TDM_RXD_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define TDM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define TDM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TDM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TDM_RXD_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define TDM_RXD_MAXCNT_MAXCNT_Max (0x3FFFUL) /*!< Max size of MAXCNT field. */ + + +/* TDM_RXD_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. */ + #define TDM_RXD_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define TDM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TDM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TDM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TDM_RXD_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TDM_RXD_AMOUNT_AMOUNT_Max (0x3FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TDM_RXD_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define TDM_RXD_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define TDM_RXD_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TDM_RXD_CURRENTAMOUNT_AMOUNT_Msk (0xFFFFUL << TDM_RXD_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TDM_RXD_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TDM_RXD_CURRENTAMOUNT_AMOUNT_Max (0x3FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TDM_RXD_MODE: Configure EasyDMA mode */ + #define TDM_RXD_MODE_ResetValue (0x00000001UL) /*!< Reset value of MODE register. */ + +/* LPOP @Bits 0..1 : Enable low-power operation, or use low-latency */ + #define TDM_RXD_MODE_LPOP_Pos (0UL) /*!< Position of LPOP field. */ + #define TDM_RXD_MODE_LPOP_Msk (0x3UL << TDM_RXD_MODE_LPOP_Pos) /*!< Bit mask of LPOP field. */ + #define TDM_RXD_MODE_LPOP_Min (0x0UL) /*!< Min enumerator value of LPOP field. */ + #define TDM_RXD_MODE_LPOP_Max (0x1UL) /*!< Max enumerator value of LPOP field. */ + #define TDM_RXD_MODE_LPOP_LowLat (0x0UL) /*!< Low-latency operation */ + #define TDM_RXD_MODE_LPOP_LowPower (0x1UL) /*!< Low-power operation */ + + +/* TDM_RXD_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define TDM_RXD_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define TDM_RXD_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TDM_RXD_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TDM_RXD_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of ENABLE + field.*/ + #define TDM_RXD_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TDM_RXD_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TDM_RXD_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define TDM_RXD_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* TDM_RXD_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define TDM_RXD_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define TDM_RXD_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TDM_RXD_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TDM_RXD_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + + +/* ===================================================== Struct TDM_TXD ====================================================== */ +/** + * @brief TXD [TDM_TXD] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IM uint32_t RESERVED1; + __IOM uint32_t MODE; /*!< (@ 0x00000018) Configure EasyDMA mode */ + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_TDM_TXD_Type; /*!< Size = 36 (0x024) */ + +/* TDM_TXD_PTR: RAM buffer start address */ + #define TDM_TXD_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define TDM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define TDM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TDM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* TDM_TXD_MAXCNT: Maximum number of bytes in channel buffer */ + #define TDM_TXD_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define TDM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define TDM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TDM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TDM_TXD_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define TDM_TXD_MAXCNT_MAXCNT_Max (0x3FFFUL) /*!< Max size of MAXCNT field. */ + + +/* TDM_TXD_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. */ + #define TDM_TXD_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define TDM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TDM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TDM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TDM_TXD_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TDM_TXD_AMOUNT_AMOUNT_Max (0x3FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TDM_TXD_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define TDM_TXD_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define TDM_TXD_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TDM_TXD_CURRENTAMOUNT_AMOUNT_Msk (0xFFFFUL << TDM_TXD_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TDM_TXD_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TDM_TXD_CURRENTAMOUNT_AMOUNT_Max (0x3FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TDM_TXD_MODE: Configure EasyDMA mode */ + #define TDM_TXD_MODE_ResetValue (0x00000001UL) /*!< Reset value of MODE register. */ + +/* LPOP @Bits 0..1 : Enable low-power operation, or use low-latency */ + #define TDM_TXD_MODE_LPOP_Pos (0UL) /*!< Position of LPOP field. */ + #define TDM_TXD_MODE_LPOP_Msk (0x3UL << TDM_TXD_MODE_LPOP_Pos) /*!< Bit mask of LPOP field. */ + #define TDM_TXD_MODE_LPOP_Min (0x0UL) /*!< Min enumerator value of LPOP field. */ + #define TDM_TXD_MODE_LPOP_Max (0x1UL) /*!< Max enumerator value of LPOP field. */ + #define TDM_TXD_MODE_LPOP_LowLat (0x0UL) /*!< Low-latency operation */ + #define TDM_TXD_MODE_LPOP_LowPower (0x1UL) /*!< Low-power operation */ + + +/* TDM_TXD_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define TDM_TXD_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define TDM_TXD_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TDM_TXD_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TDM_TXD_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of ENABLE + field.*/ + #define TDM_TXD_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TDM_TXD_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TDM_TXD_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define TDM_TXD_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* TDM_TXD_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define TDM_TXD_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define TDM_TXD_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TDM_TXD_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TDM_TXD_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* ======================================================= Struct TDM ======================================================== */ +/** + * @brief Time division multiplexed audio interface + */ + typedef struct { /*!< TDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous TDM transfer. Also starts MCK when + this is enabled*/ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops TDM transfer after the completion of MAXCNT + bytes. Triggering this task will cause the STOPPED + event to be generated.*/ + __OM uint32_t TASKS_ABORT; /*!< (@ 0x00000008) Abort TDM transfer without completing MAXCNT bytes. + Triggering this task will cause the ABORTED event to be + generated.*/ + __IM uint32_t RESERVED[29]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_ABORT; /*!< (@ 0x00000088) Subscribe configuration for task ABORT */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal + double-buffers. When TDM is started and RX is enabled, + this event will be generated for every RXTXD.MAXCNT + bytes received on the SDIN pin.*/ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) Transfer stopped. */ + __IOM uint32_t EVENTS_ABORTED; /*!< (@ 0x0000010C) Transfer aborted. */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000118) The TDX.PTR register has been copied to internal + double-buffers. When TDM is started and TX is enabled, + this event will be generated for every RXTXD.MAXCNT + bytes that are sent on the SDOUT pin.*/ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_MAXCNT; /*!< (@ 0x00000120) Generated on the active edge of FSYNC, after both RX + and TX DMA transfers have completed. An initial MAXCNT + event is also triggered on the first active edge of + FSYNC after the START task is issued.*/ + __IM uint32_t RESERVED4[24]; + __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ + __IOM uint32_t PUBLISH_ABORTED; /*!< (@ 0x0000018C) Publish configuration for event ABORTED */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000198) Publish configuration for event TXPTRUPD */ + __IM uint32_t RESERVED6; + __IOM uint32_t PUBLISH_MAXCNT; /*!< (@ 0x000001A0) Publish configuration for event MAXCNT */ + __IM uint32_t RESERVED7[87]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED8[124]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TDM */ + __IOM NRF_TDM_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Configuration registers. */ + __IM uint32_t RESERVED9[11]; + __IOM NRF_TDM_PSEL_Type PSEL; /*!< (@ 0x00000570) (unspecified) */ + __IM uint32_t RESERVED10[95]; + __IOM NRF_TDM_RXD_Type RXD; /*!< (@ 0x00000700) (unspecified) */ + __IM uint32_t RESERVED11[7]; + __IOM NRF_TDM_TXD_Type TXD; /*!< (@ 0x00000740) (unspecified) */ + } NRF_TDM_Type; /*!< Size = 1892 (0x764) */ + +/* TDM_TASKS_START: Starts continuous TDM transfer. Also starts MCK when this is enabled */ + #define TDM_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Starts continuous TDM transfer. Also starts MCK when this is enabled */ + #define TDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define TDM_TASKS_START_TASKS_START_Msk (0x1UL << TDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define TDM_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define TDM_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define TDM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* TDM_TASKS_STOP: Stops TDM transfer after the completion of MAXCNT bytes. Triggering this task will cause the STOPPED event to + be generated. */ + + #define TDM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stops TDM transfer after the completion of MAXCNT bytes. Triggering this task will cause the STOPPED + event to be generated. */ + + #define TDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define TDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define TDM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define TDM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define TDM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TDM_TASKS_ABORT: Abort TDM transfer without completing MAXCNT bytes. Triggering this task will cause the ABORTED event to be + generated. */ + + #define TDM_TASKS_ABORT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ABORT register. */ + +/* TASKS_ABORT @Bit 0 : Abort TDM transfer without completing MAXCNT bytes. Triggering this task will cause the ABORTED event to + be generated. */ + + #define TDM_TASKS_ABORT_TASKS_ABORT_Pos (0UL) /*!< Position of TASKS_ABORT field. */ + #define TDM_TASKS_ABORT_TASKS_ABORT_Msk (0x1UL << TDM_TASKS_ABORT_TASKS_ABORT_Pos) /*!< Bit mask of TASKS_ABORT field. */ + #define TDM_TASKS_ABORT_TASKS_ABORT_Min (0x1UL) /*!< Min enumerator value of TASKS_ABORT field. */ + #define TDM_TASKS_ABORT_TASKS_ABORT_Max (0x1UL) /*!< Max enumerator value of TASKS_ABORT field. */ + #define TDM_TASKS_ABORT_TASKS_ABORT_Trigger (0x1UL) /*!< Trigger task */ + + +/* TDM_SUBSCRIBE_START: Subscribe configuration for task START */ + #define TDM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define TDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TDM_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TDM_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define TDM_SUBSCRIBE_START_EN_Msk (0x1UL << TDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define TDM_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TDM_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TDM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TDM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TDM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define TDM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TDM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TDM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TDM_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TDM_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TDM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TDM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TDM_SUBSCRIBE_ABORT: Subscribe configuration for task ABORT */ + #define TDM_SUBSCRIBE_ABORT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ABORT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ABORT will subscribe to */ + #define TDM_SUBSCRIBE_ABORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TDM_SUBSCRIBE_ABORT_CHIDX_Msk (0xFFUL << TDM_SUBSCRIBE_ABORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TDM_SUBSCRIBE_ABORT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TDM_SUBSCRIBE_ABORT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TDM_SUBSCRIBE_ABORT_EN_Pos (31UL) /*!< Position of EN field. */ + #define TDM_SUBSCRIBE_ABORT_EN_Msk (0x1UL << TDM_SUBSCRIBE_ABORT_EN_Pos) /*!< Bit mask of EN field. */ + #define TDM_SUBSCRIBE_ABORT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TDM_SUBSCRIBE_ABORT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TDM_SUBSCRIBE_ABORT_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TDM_SUBSCRIBE_ABORT_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TDM_EVENTS_RXPTRUPD: The RXD.PTR register has been copied to internal double-buffers. When TDM is started and RX is enabled, + this event will be generated for every RXTXD.MAXCNT bytes received on the SDIN pin. */ + + #define TDM_EVENTS_RXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXPTRUPD register. */ + +/* EVENTS_RXPTRUPD @Bit 0 : The RXD.PTR register has been copied to internal double-buffers. When TDM is started and RX is + enabled, this event will be generated for every RXTXD.MAXCNT bytes received on the SDIN pin. */ + + #define TDM_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ + #define TDM_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << TDM_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of + EVENTS_RXPTRUPD field.*/ + #define TDM_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXPTRUPD field. */ + #define TDM_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXPTRUPD field. */ + #define TDM_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */ + #define TDM_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (0x1UL) /*!< Event generated */ + + +/* TDM_EVENTS_STOPPED: Transfer stopped. */ + #define TDM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : Transfer stopped. */ + #define TDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define TDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED + field.*/ + #define TDM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define TDM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define TDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define TDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* TDM_EVENTS_ABORTED: Transfer aborted. */ + #define TDM_EVENTS_ABORTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ABORTED register. */ + +/* EVENTS_ABORTED @Bit 0 : Transfer aborted. */ + #define TDM_EVENTS_ABORTED_EVENTS_ABORTED_Pos (0UL) /*!< Position of EVENTS_ABORTED field. */ + #define TDM_EVENTS_ABORTED_EVENTS_ABORTED_Msk (0x1UL << TDM_EVENTS_ABORTED_EVENTS_ABORTED_Pos) /*!< Bit mask of EVENTS_ABORTED + field.*/ + #define TDM_EVENTS_ABORTED_EVENTS_ABORTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_ABORTED field. */ + #define TDM_EVENTS_ABORTED_EVENTS_ABORTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_ABORTED field. */ + #define TDM_EVENTS_ABORTED_EVENTS_ABORTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define TDM_EVENTS_ABORTED_EVENTS_ABORTED_Generated (0x1UL) /*!< Event generated */ + + +/* TDM_EVENTS_TXPTRUPD: The TDX.PTR register has been copied to internal double-buffers. When TDM is started and TX is enabled, + this event will be generated for every RXTXD.MAXCNT bytes that are sent on the SDOUT pin. */ + + #define TDM_EVENTS_TXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXPTRUPD register. */ + +/* EVENTS_TXPTRUPD @Bit 0 : The TDX.PTR register has been copied to internal double-buffers. When TDM is started and TX is + enabled, this event will be generated for every RXTXD.MAXCNT bytes that are sent on the SDOUT pin. */ + + #define TDM_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ + #define TDM_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << TDM_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of + EVENTS_TXPTRUPD field.*/ + #define TDM_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXPTRUPD field. */ + #define TDM_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXPTRUPD field. */ + #define TDM_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */ + #define TDM_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (0x1UL) /*!< Event generated */ + + +/* TDM_EVENTS_MAXCNT: Generated on the active edge of FSYNC, after both RX and TX DMA transfers have completed. An initial + MAXCNT event is also triggered on the first active edge of FSYNC after the START task is issued. */ + + #define TDM_EVENTS_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_MAXCNT register. */ + +/* EVENTS_MAXCNT @Bit 0 : Generated on the active edge of FSYNC, after both RX and TX DMA transfers have completed. An initial + MAXCNT event is also triggered on the first active edge of FSYNC after the START task is issued. */ + + #define TDM_EVENTS_MAXCNT_EVENTS_MAXCNT_Pos (0UL) /*!< Position of EVENTS_MAXCNT field. */ + #define TDM_EVENTS_MAXCNT_EVENTS_MAXCNT_Msk (0x1UL << TDM_EVENTS_MAXCNT_EVENTS_MAXCNT_Pos) /*!< Bit mask of EVENTS_MAXCNT + field.*/ + #define TDM_EVENTS_MAXCNT_EVENTS_MAXCNT_Min (0x0UL) /*!< Min enumerator value of EVENTS_MAXCNT field. */ + #define TDM_EVENTS_MAXCNT_EVENTS_MAXCNT_Max (0x1UL) /*!< Max enumerator value of EVENTS_MAXCNT field. */ + #define TDM_EVENTS_MAXCNT_EVENTS_MAXCNT_NotGenerated (0x0UL) /*!< Event not generated */ + #define TDM_EVENTS_MAXCNT_EVENTS_MAXCNT_Generated (0x1UL) /*!< Event generated */ + + +/* TDM_PUBLISH_RXPTRUPD: Publish configuration for event RXPTRUPD */ + #define TDM_PUBLISH_RXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXPTRUPD register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXPTRUPD will publish to */ + #define TDM_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TDM_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << TDM_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TDM_PUBLISH_RXPTRUPD_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TDM_PUBLISH_RXPTRUPD_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TDM_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ + #define TDM_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << TDM_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ + #define TDM_PUBLISH_RXPTRUPD_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TDM_PUBLISH_RXPTRUPD_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TDM_PUBLISH_RXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TDM_PUBLISH_RXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TDM_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define TDM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define TDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TDM_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TDM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define TDM_PUBLISH_STOPPED_EN_Msk (0x1UL << TDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define TDM_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TDM_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TDM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TDM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TDM_PUBLISH_ABORTED: Publish configuration for event ABORTED */ + #define TDM_PUBLISH_ABORTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ABORTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ABORTED will publish to */ + #define TDM_PUBLISH_ABORTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TDM_PUBLISH_ABORTED_CHIDX_Msk (0xFFUL << TDM_PUBLISH_ABORTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TDM_PUBLISH_ABORTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TDM_PUBLISH_ABORTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TDM_PUBLISH_ABORTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define TDM_PUBLISH_ABORTED_EN_Msk (0x1UL << TDM_PUBLISH_ABORTED_EN_Pos) /*!< Bit mask of EN field. */ + #define TDM_PUBLISH_ABORTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TDM_PUBLISH_ABORTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TDM_PUBLISH_ABORTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TDM_PUBLISH_ABORTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TDM_PUBLISH_TXPTRUPD: Publish configuration for event TXPTRUPD */ + #define TDM_PUBLISH_TXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXPTRUPD register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TXPTRUPD will publish to */ + #define TDM_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TDM_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << TDM_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TDM_PUBLISH_TXPTRUPD_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TDM_PUBLISH_TXPTRUPD_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TDM_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ + #define TDM_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << TDM_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ + #define TDM_PUBLISH_TXPTRUPD_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TDM_PUBLISH_TXPTRUPD_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TDM_PUBLISH_TXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TDM_PUBLISH_TXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TDM_PUBLISH_MAXCNT: Publish configuration for event MAXCNT */ + #define TDM_PUBLISH_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_MAXCNT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MAXCNT will publish to */ + #define TDM_PUBLISH_MAXCNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TDM_PUBLISH_MAXCNT_CHIDX_Msk (0xFFUL << TDM_PUBLISH_MAXCNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TDM_PUBLISH_MAXCNT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TDM_PUBLISH_MAXCNT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TDM_PUBLISH_MAXCNT_EN_Pos (31UL) /*!< Position of EN field. */ + #define TDM_PUBLISH_MAXCNT_EN_Msk (0x1UL << TDM_PUBLISH_MAXCNT_EN_Pos) /*!< Bit mask of EN field. */ + #define TDM_PUBLISH_MAXCNT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TDM_PUBLISH_MAXCNT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TDM_PUBLISH_MAXCNT_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TDM_PUBLISH_MAXCNT_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TDM_INTEN: Enable or disable interrupt */ + #define TDM_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* RXPTRUPD @Bit 1 : Enable or disable interrupt for event RXPTRUPD */ + #define TDM_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ + #define TDM_INTEN_RXPTRUPD_Msk (0x1UL << TDM_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ + #define TDM_INTEN_RXPTRUPD_Min (0x0UL) /*!< Min enumerator value of RXPTRUPD field. */ + #define TDM_INTEN_RXPTRUPD_Max (0x1UL) /*!< Max enumerator value of RXPTRUPD field. */ + #define TDM_INTEN_RXPTRUPD_Disabled (0x0UL) /*!< Disable */ + #define TDM_INTEN_RXPTRUPD_Enabled (0x1UL) /*!< Enable */ + +/* STOPPED @Bit 2 : Enable or disable interrupt for event STOPPED */ + #define TDM_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ + #define TDM_INTEN_STOPPED_Msk (0x1UL << TDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TDM_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TDM_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TDM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define TDM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* ABORTED @Bit 3 : Enable or disable interrupt for event ABORTED */ + #define TDM_INTEN_ABORTED_Pos (3UL) /*!< Position of ABORTED field. */ + #define TDM_INTEN_ABORTED_Msk (0x1UL << TDM_INTEN_ABORTED_Pos) /*!< Bit mask of ABORTED field. */ + #define TDM_INTEN_ABORTED_Min (0x0UL) /*!< Min enumerator value of ABORTED field. */ + #define TDM_INTEN_ABORTED_Max (0x1UL) /*!< Max enumerator value of ABORTED field. */ + #define TDM_INTEN_ABORTED_Disabled (0x0UL) /*!< Disable */ + #define TDM_INTEN_ABORTED_Enabled (0x1UL) /*!< Enable */ + +/* TXPTRUPD @Bit 6 : Enable or disable interrupt for event TXPTRUPD */ + #define TDM_INTEN_TXPTRUPD_Pos (6UL) /*!< Position of TXPTRUPD field. */ + #define TDM_INTEN_TXPTRUPD_Msk (0x1UL << TDM_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ + #define TDM_INTEN_TXPTRUPD_Min (0x0UL) /*!< Min enumerator value of TXPTRUPD field. */ + #define TDM_INTEN_TXPTRUPD_Max (0x1UL) /*!< Max enumerator value of TXPTRUPD field. */ + #define TDM_INTEN_TXPTRUPD_Disabled (0x0UL) /*!< Disable */ + #define TDM_INTEN_TXPTRUPD_Enabled (0x1UL) /*!< Enable */ + +/* MAXCNT @Bit 8 : Enable or disable interrupt for event MAXCNT */ + #define TDM_INTEN_MAXCNT_Pos (8UL) /*!< Position of MAXCNT field. */ + #define TDM_INTEN_MAXCNT_Msk (0x1UL << TDM_INTEN_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TDM_INTEN_MAXCNT_Min (0x0UL) /*!< Min enumerator value of MAXCNT field. */ + #define TDM_INTEN_MAXCNT_Max (0x1UL) /*!< Max enumerator value of MAXCNT field. */ + #define TDM_INTEN_MAXCNT_Disabled (0x0UL) /*!< Disable */ + #define TDM_INTEN_MAXCNT_Enabled (0x1UL) /*!< Enable */ + + +/* TDM_INTENSET: Enable interrupt */ + #define TDM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* RXPTRUPD @Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */ + #define TDM_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ + #define TDM_INTENSET_RXPTRUPD_Msk (0x1UL << TDM_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ + #define TDM_INTENSET_RXPTRUPD_Min (0x0UL) /*!< Min enumerator value of RXPTRUPD field. */ + #define TDM_INTENSET_RXPTRUPD_Max (0x1UL) /*!< Max enumerator value of RXPTRUPD field. */ + #define TDM_INTENSET_RXPTRUPD_Set (0x1UL) /*!< Enable */ + #define TDM_INTENSET_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ + #define TDM_INTENSET_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 2 : Write '1' to enable interrupt for event STOPPED */ + #define TDM_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ + #define TDM_INTENSET_STOPPED_Msk (0x1UL << TDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TDM_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TDM_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TDM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define TDM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TDM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ABORTED @Bit 3 : Write '1' to enable interrupt for event ABORTED */ + #define TDM_INTENSET_ABORTED_Pos (3UL) /*!< Position of ABORTED field. */ + #define TDM_INTENSET_ABORTED_Msk (0x1UL << TDM_INTENSET_ABORTED_Pos) /*!< Bit mask of ABORTED field. */ + #define TDM_INTENSET_ABORTED_Min (0x0UL) /*!< Min enumerator value of ABORTED field. */ + #define TDM_INTENSET_ABORTED_Max (0x1UL) /*!< Max enumerator value of ABORTED field. */ + #define TDM_INTENSET_ABORTED_Set (0x1UL) /*!< Enable */ + #define TDM_INTENSET_ABORTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TDM_INTENSET_ABORTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXPTRUPD @Bit 6 : Write '1' to enable interrupt for event TXPTRUPD */ + #define TDM_INTENSET_TXPTRUPD_Pos (6UL) /*!< Position of TXPTRUPD field. */ + #define TDM_INTENSET_TXPTRUPD_Msk (0x1UL << TDM_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ + #define TDM_INTENSET_TXPTRUPD_Min (0x0UL) /*!< Min enumerator value of TXPTRUPD field. */ + #define TDM_INTENSET_TXPTRUPD_Max (0x1UL) /*!< Max enumerator value of TXPTRUPD field. */ + #define TDM_INTENSET_TXPTRUPD_Set (0x1UL) /*!< Enable */ + #define TDM_INTENSET_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ + #define TDM_INTENSET_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* MAXCNT @Bit 8 : Write '1' to enable interrupt for event MAXCNT */ + #define TDM_INTENSET_MAXCNT_Pos (8UL) /*!< Position of MAXCNT field. */ + #define TDM_INTENSET_MAXCNT_Msk (0x1UL << TDM_INTENSET_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TDM_INTENSET_MAXCNT_Min (0x0UL) /*!< Min enumerator value of MAXCNT field. */ + #define TDM_INTENSET_MAXCNT_Max (0x1UL) /*!< Max enumerator value of MAXCNT field. */ + #define TDM_INTENSET_MAXCNT_Set (0x1UL) /*!< Enable */ + #define TDM_INTENSET_MAXCNT_Disabled (0x0UL) /*!< Read: Disabled */ + #define TDM_INTENSET_MAXCNT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TDM_INTENCLR: Disable interrupt */ + #define TDM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* RXPTRUPD @Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */ + #define TDM_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ + #define TDM_INTENCLR_RXPTRUPD_Msk (0x1UL << TDM_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ + #define TDM_INTENCLR_RXPTRUPD_Min (0x0UL) /*!< Min enumerator value of RXPTRUPD field. */ + #define TDM_INTENCLR_RXPTRUPD_Max (0x1UL) /*!< Max enumerator value of RXPTRUPD field. */ + #define TDM_INTENCLR_RXPTRUPD_Clear (0x1UL) /*!< Disable */ + #define TDM_INTENCLR_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ + #define TDM_INTENCLR_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 2 : Write '1' to disable interrupt for event STOPPED */ + #define TDM_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ + #define TDM_INTENCLR_STOPPED_Msk (0x1UL << TDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TDM_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TDM_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TDM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define TDM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TDM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ABORTED @Bit 3 : Write '1' to disable interrupt for event ABORTED */ + #define TDM_INTENCLR_ABORTED_Pos (3UL) /*!< Position of ABORTED field. */ + #define TDM_INTENCLR_ABORTED_Msk (0x1UL << TDM_INTENCLR_ABORTED_Pos) /*!< Bit mask of ABORTED field. */ + #define TDM_INTENCLR_ABORTED_Min (0x0UL) /*!< Min enumerator value of ABORTED field. */ + #define TDM_INTENCLR_ABORTED_Max (0x1UL) /*!< Max enumerator value of ABORTED field. */ + #define TDM_INTENCLR_ABORTED_Clear (0x1UL) /*!< Disable */ + #define TDM_INTENCLR_ABORTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TDM_INTENCLR_ABORTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXPTRUPD @Bit 6 : Write '1' to disable interrupt for event TXPTRUPD */ + #define TDM_INTENCLR_TXPTRUPD_Pos (6UL) /*!< Position of TXPTRUPD field. */ + #define TDM_INTENCLR_TXPTRUPD_Msk (0x1UL << TDM_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ + #define TDM_INTENCLR_TXPTRUPD_Min (0x0UL) /*!< Min enumerator value of TXPTRUPD field. */ + #define TDM_INTENCLR_TXPTRUPD_Max (0x1UL) /*!< Max enumerator value of TXPTRUPD field. */ + #define TDM_INTENCLR_TXPTRUPD_Clear (0x1UL) /*!< Disable */ + #define TDM_INTENCLR_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ + #define TDM_INTENCLR_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* MAXCNT @Bit 8 : Write '1' to disable interrupt for event MAXCNT */ + #define TDM_INTENCLR_MAXCNT_Pos (8UL) /*!< Position of MAXCNT field. */ + #define TDM_INTENCLR_MAXCNT_Msk (0x1UL << TDM_INTENCLR_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TDM_INTENCLR_MAXCNT_Min (0x0UL) /*!< Min enumerator value of MAXCNT field. */ + #define TDM_INTENCLR_MAXCNT_Max (0x1UL) /*!< Max enumerator value of MAXCNT field. */ + #define TDM_INTENCLR_MAXCNT_Clear (0x1UL) /*!< Disable */ + #define TDM_INTENCLR_MAXCNT_Disabled (0x0UL) /*!< Read: Disabled */ + #define TDM_INTENCLR_MAXCNT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TDM_INTPEND: Pending interrupts */ + #define TDM_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* RXPTRUPD @Bit 1 : Read pending status of interrupt for event RXPTRUPD */ + #define TDM_INTPEND_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ + #define TDM_INTPEND_RXPTRUPD_Msk (0x1UL << TDM_INTPEND_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ + #define TDM_INTPEND_RXPTRUPD_Min (0x0UL) /*!< Min enumerator value of RXPTRUPD field. */ + #define TDM_INTPEND_RXPTRUPD_Max (0x1UL) /*!< Max enumerator value of RXPTRUPD field. */ + #define TDM_INTPEND_RXPTRUPD_NotPending (0x0UL) /*!< Read: Not pending */ + #define TDM_INTPEND_RXPTRUPD_Pending (0x1UL) /*!< Read: Pending */ + +/* STOPPED @Bit 2 : Read pending status of interrupt for event STOPPED */ + #define TDM_INTPEND_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ + #define TDM_INTPEND_STOPPED_Msk (0x1UL << TDM_INTPEND_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TDM_INTPEND_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TDM_INTPEND_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TDM_INTPEND_STOPPED_NotPending (0x0UL) /*!< Read: Not pending */ + #define TDM_INTPEND_STOPPED_Pending (0x1UL) /*!< Read: Pending */ + +/* ABORTED @Bit 3 : Read pending status of interrupt for event ABORTED */ + #define TDM_INTPEND_ABORTED_Pos (3UL) /*!< Position of ABORTED field. */ + #define TDM_INTPEND_ABORTED_Msk (0x1UL << TDM_INTPEND_ABORTED_Pos) /*!< Bit mask of ABORTED field. */ + #define TDM_INTPEND_ABORTED_Min (0x0UL) /*!< Min enumerator value of ABORTED field. */ + #define TDM_INTPEND_ABORTED_Max (0x1UL) /*!< Max enumerator value of ABORTED field. */ + #define TDM_INTPEND_ABORTED_NotPending (0x0UL) /*!< Read: Not pending */ + #define TDM_INTPEND_ABORTED_Pending (0x1UL) /*!< Read: Pending */ + +/* TXPTRUPD @Bit 6 : Read pending status of interrupt for event TXPTRUPD */ + #define TDM_INTPEND_TXPTRUPD_Pos (6UL) /*!< Position of TXPTRUPD field. */ + #define TDM_INTPEND_TXPTRUPD_Msk (0x1UL << TDM_INTPEND_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ + #define TDM_INTPEND_TXPTRUPD_Min (0x0UL) /*!< Min enumerator value of TXPTRUPD field. */ + #define TDM_INTPEND_TXPTRUPD_Max (0x1UL) /*!< Max enumerator value of TXPTRUPD field. */ + #define TDM_INTPEND_TXPTRUPD_NotPending (0x0UL) /*!< Read: Not pending */ + #define TDM_INTPEND_TXPTRUPD_Pending (0x1UL) /*!< Read: Pending */ + +/* MAXCNT @Bit 8 : Read pending status of interrupt for event MAXCNT */ + #define TDM_INTPEND_MAXCNT_Pos (8UL) /*!< Position of MAXCNT field. */ + #define TDM_INTPEND_MAXCNT_Msk (0x1UL << TDM_INTPEND_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TDM_INTPEND_MAXCNT_Min (0x0UL) /*!< Min enumerator value of MAXCNT field. */ + #define TDM_INTPEND_MAXCNT_Max (0x1UL) /*!< Max enumerator value of MAXCNT field. */ + #define TDM_INTPEND_MAXCNT_NotPending (0x0UL) /*!< Read: Not pending */ + #define TDM_INTPEND_MAXCNT_Pending (0x1UL) /*!< Read: Pending */ + + +/* TDM_ENABLE: Enable TDM */ + #define TDM_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable TDM */ + #define TDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TDM_ENABLE_ENABLE_Msk (0x1UL << TDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define TDM_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TDM_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TDM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define TDM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct TEMP ======================================================= */ +/** + * @brief Temperature Sensor + */ + typedef struct { /*!< TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED2[31]; + __IOM uint32_t PUBLISH_DATARDY; /*!< (@ 0x00000180) Publish configuration for event DATARDY */ + __IM uint32_t RESERVED3[96]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED5[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IOM uint32_t A6; /*!< (@ 0x00000538) Slope of 7th piece wise linear function */ + __IM uint32_t RESERVED6; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IOM uint32_t B6; /*!< (@ 0x00000558) y-intercept of 7th piece wise linear function */ + __IM uint32_t RESERVED7; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ + __IOM uint32_t T5; /*!< (@ 0x00000574) End point of 6th piece wise linear function */ + } NRF_TEMP_Type; /*!< Size = 1400 (0x578) */ + +/* TEMP_TASKS_START: Start temperature measurement */ + #define TEMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start temperature measurement */ + #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define TEMP_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define TEMP_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define TEMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* TEMP_TASKS_STOP: Stop temperature measurement */ + #define TEMP_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop temperature measurement */ + #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define TEMP_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define TEMP_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TEMP_SUBSCRIBE_START: Subscribe configuration for task START */ + #define TEMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define TEMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TEMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TEMP_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TEMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TEMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define TEMP_SUBSCRIBE_START_EN_Msk (0x1UL << TEMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define TEMP_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TEMP_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TEMP_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TEMP_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TEMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define TEMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TEMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TEMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TEMP_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TEMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TEMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TEMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << TEMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TEMP_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TEMP_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TEMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TEMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TEMP_EVENTS_DATARDY: Temperature measurement complete, data ready */ + #define TEMP_EVENTS_DATARDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DATARDY register. */ + +/* EVENTS_DATARDY @Bit 0 : Temperature measurement complete, data ready */ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of + EVENTS_DATARDY field.*/ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_DATARDY field. */ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_DATARDY field. */ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (0x1UL) /*!< Event generated */ + + +/* TEMP_PUBLISH_DATARDY: Publish configuration for event DATARDY */ + #define TEMP_PUBLISH_DATARDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DATARDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DATARDY will publish to */ + #define TEMP_PUBLISH_DATARDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TEMP_PUBLISH_DATARDY_CHIDX_Msk (0xFFUL << TEMP_PUBLISH_DATARDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TEMP_PUBLISH_DATARDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TEMP_PUBLISH_DATARDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TEMP_PUBLISH_DATARDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define TEMP_PUBLISH_DATARDY_EN_Msk (0x1UL << TEMP_PUBLISH_DATARDY_EN_Pos) /*!< Bit mask of EN field. */ + #define TEMP_PUBLISH_DATARDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TEMP_PUBLISH_DATARDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TEMP_PUBLISH_DATARDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TEMP_PUBLISH_DATARDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TEMP_INTENSET: Enable interrupt */ + #define TEMP_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* DATARDY @Bit 0 : Write '1' to enable interrupt for event DATARDY */ + #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ + #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ + #define TEMP_INTENSET_DATARDY_Min (0x0UL) /*!< Min enumerator value of DATARDY field. */ + #define TEMP_INTENSET_DATARDY_Max (0x1UL) /*!< Max enumerator value of DATARDY field. */ + #define TEMP_INTENSET_DATARDY_Set (0x1UL) /*!< Enable */ + #define TEMP_INTENSET_DATARDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TEMP_INTENSET_DATARDY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TEMP_INTENCLR: Disable interrupt */ + #define TEMP_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* DATARDY @Bit 0 : Write '1' to disable interrupt for event DATARDY */ + #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ + #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ + #define TEMP_INTENCLR_DATARDY_Min (0x0UL) /*!< Min enumerator value of DATARDY field. */ + #define TEMP_INTENCLR_DATARDY_Max (0x1UL) /*!< Max enumerator value of DATARDY field. */ + #define TEMP_INTENCLR_DATARDY_Clear (0x1UL) /*!< Disable */ + #define TEMP_INTENCLR_DATARDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TEMP_INTENCLR_DATARDY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TEMP_TEMP: Temperature in degC (0.25deg steps) */ + #define TEMP_TEMP_ResetValue (0x00000000UL) /*!< Reset value of TEMP register. */ + +/* TEMP @Bits 0..31 : Temperature in degC (0.25deg steps) */ + #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ + #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + + +/* TEMP_A0: Slope of 1st piece wise linear function */ + #define TEMP_A0_ResetValue (0x0000038CUL) /*!< Reset value of A0 register. */ + +/* A0 @Bits 0..11 : Slope of 1st piece wise linear function */ + #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ + #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + + +/* TEMP_A1: Slope of 2nd piece wise linear function */ + #define TEMP_A1_ResetValue (0x000003B3UL) /*!< Reset value of A1 register. */ + +/* A1 @Bits 0..11 : Slope of 2nd piece wise linear function */ + #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ + #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + + +/* TEMP_A2: Slope of 3rd piece wise linear function */ + #define TEMP_A2_ResetValue (0x000003FAUL) /*!< Reset value of A2 register. */ + +/* A2 @Bits 0..11 : Slope of 3rd piece wise linear function */ + #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ + #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + + +/* TEMP_A3: Slope of 4th piece wise linear function */ + #define TEMP_A3_ResetValue (0x00000451UL) /*!< Reset value of A3 register. */ + +/* A3 @Bits 0..11 : Slope of 4th piece wise linear function */ + #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ + #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + + +/* TEMP_A4: Slope of 5th piece wise linear function */ + #define TEMP_A4_ResetValue (0x000004AAUL) /*!< Reset value of A4 register. */ + +/* A4 @Bits 0..11 : Slope of 5th piece wise linear function */ + #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ + #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + + +/* TEMP_A5: Slope of 6th piece wise linear function */ + #define TEMP_A5_ResetValue (0x00000539UL) /*!< Reset value of A5 register. */ + +/* A5 @Bits 0..11 : Slope of 6th piece wise linear function */ + #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ + #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + + +/* TEMP_A6: Slope of 7th piece wise linear function */ + #define TEMP_A6_ResetValue (0x00000578UL) /*!< Reset value of A6 register. */ + +/* A6 @Bits 0..11 : Slope of 7th piece wise linear function */ + #define TEMP_A6_A6_Pos (0UL) /*!< Position of A6 field. */ + #define TEMP_A6_A6_Msk (0xFFFUL << TEMP_A6_A6_Pos) /*!< Bit mask of A6 field. */ + + +/* TEMP_B0: y-intercept of 1st piece wise linear function */ + #define TEMP_B0_ResetValue (0x00000037UL) /*!< Reset value of B0 register. */ + +/* B0 @Bits 0..11 : y-intercept of 1st piece wise linear function */ + #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ + #define TEMP_B0_B0_Msk (0xFFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + + +/* TEMP_B1: y-intercept of 2nd piece wise linear function */ + #define TEMP_B1_ResetValue (0x00000011UL) /*!< Reset value of B1 register. */ + +/* B1 @Bits 0..11 : y-intercept of 2nd piece wise linear function */ + #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ + #define TEMP_B1_B1_Msk (0xFFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + + +/* TEMP_B2: y-intercept of 3rd piece wise linear function */ + #define TEMP_B2_ResetValue (0x00000005UL) /*!< Reset value of B2 register. */ + +/* B2 @Bits 0..11 : y-intercept of 3rd piece wise linear function */ + #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ + #define TEMP_B2_B2_Msk (0xFFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + + +/* TEMP_B3: y-intercept of 4th piece wise linear function */ + #define TEMP_B3_ResetValue (0x0000002BUL) /*!< Reset value of B3 register. */ + +/* B3 @Bits 0..11 : y-intercept of 4th piece wise linear function */ + #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ + #define TEMP_B3_B3_Msk (0xFFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + + +/* TEMP_B4: y-intercept of 5th piece wise linear function */ + #define TEMP_B4_ResetValue (0x0000008FUL) /*!< Reset value of B4 register. */ + +/* B4 @Bits 0..11 : y-intercept of 5th piece wise linear function */ + #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ + #define TEMP_B4_B4_Msk (0xFFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + + +/* TEMP_B5: y-intercept of 6th piece wise linear function */ + #define TEMP_B5_ResetValue (0x0000015DUL) /*!< Reset value of B5 register. */ + +/* B5 @Bits 0..11 : y-intercept of 6th piece wise linear function */ + #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ + #define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + + +/* TEMP_B6: y-intercept of 7th piece wise linear function */ + #define TEMP_B6_ResetValue (0x000001C0UL) /*!< Reset value of B6 register. */ + +/* B6 @Bits 0..11 : y-intercept of 7th piece wise linear function */ + #define TEMP_B6_B6_Pos (0UL) /*!< Position of B6 field. */ + #define TEMP_B6_B6_Msk (0xFFFUL << TEMP_B6_B6_Pos) /*!< Bit mask of B6 field. */ + + +/* TEMP_T0: End point of 1st piece wise linear function */ + #define TEMP_T0_ResetValue (0x000000E5UL) /*!< Reset value of T0 register. */ + +/* T0 @Bits 0..7 : End point of 1st piece wise linear function */ + #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ + #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + + +/* TEMP_T1: End point of 2nd piece wise linear function */ + #define TEMP_T1_ResetValue (0x000000FBUL) /*!< Reset value of T1 register. */ + +/* T1 @Bits 0..7 : End point of 2nd piece wise linear function */ + #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ + #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + + +/* TEMP_T2: End point of 3rd piece wise linear function */ + #define TEMP_T2_ResetValue (0x00000010UL) /*!< Reset value of T2 register. */ + +/* T2 @Bits 0..7 : End point of 3rd piece wise linear function */ + #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ + #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + + +/* TEMP_T3: End point of 4th piece wise linear function */ + #define TEMP_T3_ResetValue (0x0000002BUL) /*!< Reset value of T3 register. */ + +/* T3 @Bits 0..7 : End point of 4th piece wise linear function */ + #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ + #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + + +/* TEMP_T4: End point of 5th piece wise linear function */ + #define TEMP_T4_ResetValue (0x00000041UL) /*!< Reset value of T4 register. */ + +/* T4 @Bits 0..7 : End point of 5th piece wise linear function */ + #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ + #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* TEMP_T5: End point of 6th piece wise linear function */ + #define TEMP_T5_ResetValue (0x00000050UL) /*!< Reset value of T5 register. */ + +/* T5 @Bits 0..7 : End point of 6th piece wise linear function */ + #define TEMP_T5_T5_Pos (0UL) /*!< Position of T5 field. */ + #define TEMP_T5_T5_Msk (0xFFUL << TEMP_T5_T5_Pos) /*!< Bit mask of T5 field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TIMER ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ====================================================== Struct TIMER ======================================================= */ +/** + * @brief Timer/Counter + */ + typedef struct { /*!< TIMER Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __IM uint32_t RESERVED[12]; + __OM uint32_t TASKS_CAPTURE[8]; /*!< (@ 0x00000040) Capture Timer value to CC[n] register */ + __IM uint32_t RESERVED1[8]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ + __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ + __IM uint32_t RESERVED2[12]; + __IOM uint32_t SUBSCRIBE_CAPTURE[8]; /*!< (@ 0x000000C0) Subscribe configuration for task CAPTURE[n] */ + __IM uint32_t RESERVED3[24]; + __IOM uint32_t EVENTS_COMPARE[8]; /*!< (@ 0x00000140) Compare event on CC[n] match */ + __IM uint32_t RESERVED4[24]; + __IOM uint32_t PUBLISH_COMPARE[8]; /*!< (@ 0x000001C0) Publish configuration for event COMPARE[n] */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED6[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED8; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED9[11]; + __IOM uint32_t CC[8]; /*!< (@ 0x00000540) Capture/Compare register n */ + __IM uint32_t RESERVED10[8]; + __IOM uint32_t ONESHOTEN[8]; /*!< (@ 0x00000580) Enable one-shot operation for Capture/Compare channel + n*/ + } NRF_TIMER_Type; /*!< Size = 1440 (0x5A0) */ + +/* TIMER_TASKS_START: Start Timer */ + #define TIMER_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start Timer */ + #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define TIMER_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define TIMER_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define TIMER_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* TIMER_TASKS_STOP: Stop Timer */ + #define TIMER_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop Timer */ + #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define TIMER_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define TIMER_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TIMER_TASKS_COUNT: Increment Timer (Counter mode only) */ + #define TIMER_TASKS_COUNT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_COUNT register. */ + +/* TASKS_COUNT @Bit 0 : Increment Timer (Counter mode only) */ + #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ + #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ + #define TIMER_TASKS_COUNT_TASKS_COUNT_Min (0x1UL) /*!< Min enumerator value of TASKS_COUNT field. */ + #define TIMER_TASKS_COUNT_TASKS_COUNT_Max (0x1UL) /*!< Max enumerator value of TASKS_COUNT field. */ + #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (0x1UL) /*!< Trigger task */ + + +/* TIMER_TASKS_CLEAR: Clear time */ + #define TIMER_TASKS_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLEAR register. */ + +/* TASKS_CLEAR @Bit 0 : Clear time */ + #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ + #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ + #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Min (0x1UL) /*!< Min enumerator value of TASKS_CLEAR field. */ + #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Max (0x1UL) /*!< Max enumerator value of TASKS_CLEAR field. */ + #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */ + + +/* TIMER_TASKS_CAPTURE: Capture Timer value to CC[n] register */ + #define TIMER_TASKS_CAPTURE_MaxCount (8UL) /*!< Max size of TASKS_CAPTURE[8] array. */ + #define TIMER_TASKS_CAPTURE_MaxIndex (7UL) /*!< Max index of TASKS_CAPTURE[8] array. */ + #define TIMER_TASKS_CAPTURE_MinIndex (0UL) /*!< Min index of TASKS_CAPTURE[8] array. */ + #define TIMER_TASKS_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CAPTURE[8] register. */ + +/* TASKS_CAPTURE @Bit 0 : Capture Timer value to CC[n] register */ + #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ + #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE + field.*/ + #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Min (0x1UL) /*!< Min enumerator value of TASKS_CAPTURE field. */ + #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Max (0x1UL) /*!< Max enumerator value of TASKS_CAPTURE field. */ + #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task */ + + +/* TIMER_SUBSCRIBE_START: Subscribe configuration for task START */ + #define TIMER_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TIMER_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TIMER_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define TIMER_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TIMER_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TIMER_SUBSCRIBE_COUNT: Subscribe configuration for task COUNT */ + #define TIMER_SUBSCRIBE_COUNT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_COUNT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task COUNT will subscribe to */ + #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_SUBSCRIBE_COUNT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_SUBSCRIBE_COUNT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_SUBSCRIBE_COUNT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_COUNT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TIMER_SUBSCRIBE_CLEAR: Subscribe configuration for task CLEAR */ + #define TIMER_SUBSCRIBE_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLEAR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CLEAR will subscribe to */ + #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TIMER_SUBSCRIBE_CAPTURE: Subscribe configuration for task CAPTURE[n] */ + #define TIMER_SUBSCRIBE_CAPTURE_MaxCount (8UL) /*!< Max size of SUBSCRIBE_CAPTURE[8] array. */ + #define TIMER_SUBSCRIBE_CAPTURE_MaxIndex (7UL) /*!< Max index of SUBSCRIBE_CAPTURE[8] array. */ + #define TIMER_SUBSCRIBE_CAPTURE_MinIndex (0UL) /*!< Min index of SUBSCRIBE_CAPTURE[8] array. */ + #define TIMER_SUBSCRIBE_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAPTURE[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CAPTURE[n] will subscribe to */ + #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TIMER_EVENTS_COMPARE: Compare event on CC[n] match */ + #define TIMER_EVENTS_COMPARE_MaxCount (8UL) /*!< Max size of EVENTS_COMPARE[8] array. */ + #define TIMER_EVENTS_COMPARE_MaxIndex (7UL) /*!< Max index of EVENTS_COMPARE[8] array. */ + #define TIMER_EVENTS_COMPARE_MinIndex (0UL) /*!< Min index of EVENTS_COMPARE[8] array. */ + #define TIMER_EVENTS_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPARE[8] register. */ + +/* EVENTS_COMPARE @Bit 0 : Compare event on CC[n] match */ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of + EVENTS_COMPARE field.*/ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPARE field. */ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPARE field. */ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */ + + +/* TIMER_PUBLISH_COMPARE: Publish configuration for event COMPARE[n] */ + #define TIMER_PUBLISH_COMPARE_MaxCount (8UL) /*!< Max size of PUBLISH_COMPARE[8] array. */ + #define TIMER_PUBLISH_COMPARE_MaxIndex (7UL) /*!< Max index of PUBLISH_COMPARE[8] array. */ + #define TIMER_PUBLISH_COMPARE_MinIndex (0UL) /*!< Min index of PUBLISH_COMPARE[8] array. */ + #define TIMER_PUBLISH_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPARE[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event COMPARE[n] will publish to */ + #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_PUBLISH_COMPARE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_PUBLISH_COMPARE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_PUBLISH_COMPARE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_PUBLISH_COMPARE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TIMER_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TIMER_SHORTS: Shortcuts between local events and tasks */ + #define TIMER_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* COMPARE0_CLEAR @Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE0_CLEAR field. */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE0_CLEAR field. */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE1_CLEAR @Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE1_CLEAR field. */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE1_CLEAR field. */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE2_CLEAR @Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE2_CLEAR field. */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE2_CLEAR field. */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE3_CLEAR @Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE3_CLEAR field. */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE3_CLEAR field. */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE4_CLEAR @Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE4_CLEAR field. */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE4_CLEAR field. */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE5_CLEAR @Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE5_CLEAR field. */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE5_CLEAR field. */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE6_CLEAR @Bit 6 : Shortcut between event COMPARE[6] and task CLEAR */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Pos (6UL) /*!< Position of COMPARE6_CLEAR field. */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE6_CLEAR_Pos) /*!< Bit mask of COMPARE6_CLEAR field. */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE6_CLEAR field. */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE6_CLEAR field. */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE7_CLEAR @Bit 7 : Shortcut between event COMPARE[7] and task CLEAR */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Pos (7UL) /*!< Position of COMPARE7_CLEAR field. */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE7_CLEAR_Pos) /*!< Bit mask of COMPARE7_CLEAR field. */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE7_CLEAR field. */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE7_CLEAR field. */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE0_STOP @Bit 16 : Shortcut between event COMPARE[0] and task STOP */ + #define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL) /*!< Position of COMPARE0_STOP field. */ + #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ + #define TIMER_SHORTS_COMPARE0_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE0_STOP field. */ + #define TIMER_SHORTS_COMPARE0_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE0_STOP field. */ + #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE0_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE1_STOP @Bit 17 : Shortcut between event COMPARE[1] and task STOP */ + #define TIMER_SHORTS_COMPARE1_STOP_Pos (17UL) /*!< Position of COMPARE1_STOP field. */ + #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ + #define TIMER_SHORTS_COMPARE1_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE1_STOP field. */ + #define TIMER_SHORTS_COMPARE1_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE1_STOP field. */ + #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE1_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE2_STOP @Bit 18 : Shortcut between event COMPARE[2] and task STOP */ + #define TIMER_SHORTS_COMPARE2_STOP_Pos (18UL) /*!< Position of COMPARE2_STOP field. */ + #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ + #define TIMER_SHORTS_COMPARE2_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE2_STOP field. */ + #define TIMER_SHORTS_COMPARE2_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE2_STOP field. */ + #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE2_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE3_STOP @Bit 19 : Shortcut between event COMPARE[3] and task STOP */ + #define TIMER_SHORTS_COMPARE3_STOP_Pos (19UL) /*!< Position of COMPARE3_STOP field. */ + #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ + #define TIMER_SHORTS_COMPARE3_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE3_STOP field. */ + #define TIMER_SHORTS_COMPARE3_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE3_STOP field. */ + #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE3_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE4_STOP @Bit 20 : Shortcut between event COMPARE[4] and task STOP */ + #define TIMER_SHORTS_COMPARE4_STOP_Pos (20UL) /*!< Position of COMPARE4_STOP field. */ + #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ + #define TIMER_SHORTS_COMPARE4_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE4_STOP field. */ + #define TIMER_SHORTS_COMPARE4_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE4_STOP field. */ + #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE4_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE5_STOP @Bit 21 : Shortcut between event COMPARE[5] and task STOP */ + #define TIMER_SHORTS_COMPARE5_STOP_Pos (21UL) /*!< Position of COMPARE5_STOP field. */ + #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ + #define TIMER_SHORTS_COMPARE5_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE5_STOP field. */ + #define TIMER_SHORTS_COMPARE5_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE5_STOP field. */ + #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE5_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE6_STOP @Bit 22 : Shortcut between event COMPARE[6] and task STOP */ + #define TIMER_SHORTS_COMPARE6_STOP_Pos (22UL) /*!< Position of COMPARE6_STOP field. */ + #define TIMER_SHORTS_COMPARE6_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE6_STOP_Pos) /*!< Bit mask of COMPARE6_STOP field. */ + #define TIMER_SHORTS_COMPARE6_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE6_STOP field. */ + #define TIMER_SHORTS_COMPARE6_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE6_STOP field. */ + #define TIMER_SHORTS_COMPARE6_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE6_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE7_STOP @Bit 23 : Shortcut between event COMPARE[7] and task STOP */ + #define TIMER_SHORTS_COMPARE7_STOP_Pos (23UL) /*!< Position of COMPARE7_STOP field. */ + #define TIMER_SHORTS_COMPARE7_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE7_STOP_Pos) /*!< Bit mask of COMPARE7_STOP field. */ + #define TIMER_SHORTS_COMPARE7_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE7_STOP field. */ + #define TIMER_SHORTS_COMPARE7_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE7_STOP field. */ + #define TIMER_SHORTS_COMPARE7_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE7_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* TIMER_INTEN: Enable or disable interrupt */ + #define TIMER_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* COMPARE0 @Bit 16 : Enable or disable interrupt for event COMPARE[0] */ + #define TIMER_INTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ + #define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define TIMER_INTEN_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define TIMER_INTEN_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define TIMER_INTEN_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 17 : Enable or disable interrupt for event COMPARE[1] */ + #define TIMER_INTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ + #define TIMER_INTEN_COMPARE1_Msk (0x1UL << TIMER_INTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define TIMER_INTEN_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define TIMER_INTEN_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define TIMER_INTEN_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 18 : Enable or disable interrupt for event COMPARE[2] */ + #define TIMER_INTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ + #define TIMER_INTEN_COMPARE2_Msk (0x1UL << TIMER_INTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define TIMER_INTEN_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define TIMER_INTEN_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define TIMER_INTEN_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 19 : Enable or disable interrupt for event COMPARE[3] */ + #define TIMER_INTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ + #define TIMER_INTEN_COMPARE3_Msk (0x1UL << TIMER_INTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define TIMER_INTEN_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define TIMER_INTEN_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define TIMER_INTEN_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 20 : Enable or disable interrupt for event COMPARE[4] */ + #define TIMER_INTEN_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ + #define TIMER_INTEN_COMPARE4_Msk (0x1UL << TIMER_INTEN_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define TIMER_INTEN_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define TIMER_INTEN_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define TIMER_INTEN_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 21 : Enable or disable interrupt for event COMPARE[5] */ + #define TIMER_INTEN_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ + #define TIMER_INTEN_COMPARE5_Msk (0x1UL << TIMER_INTEN_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define TIMER_INTEN_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define TIMER_INTEN_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define TIMER_INTEN_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 22 : Enable or disable interrupt for event COMPARE[6] */ + #define TIMER_INTEN_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */ + #define TIMER_INTEN_COMPARE6_Msk (0x1UL << TIMER_INTEN_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define TIMER_INTEN_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define TIMER_INTEN_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define TIMER_INTEN_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 23 : Enable or disable interrupt for event COMPARE[7] */ + #define TIMER_INTEN_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ + #define TIMER_INTEN_COMPARE7_Msk (0x1UL << TIMER_INTEN_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define TIMER_INTEN_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define TIMER_INTEN_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define TIMER_INTEN_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE7_Enabled (0x1UL) /*!< Enable */ + + +/* TIMER_INTENSET: Enable interrupt */ + #define TIMER_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* COMPARE0 @Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ + #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ + #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define TIMER_INTENSET_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define TIMER_INTENSET_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define TIMER_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ + #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ + #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define TIMER_INTENSET_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define TIMER_INTENSET_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define TIMER_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ + #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ + #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define TIMER_INTENSET_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define TIMER_INTENSET_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define TIMER_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ + #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ + #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define TIMER_INTENSET_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define TIMER_INTENSET_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define TIMER_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ + #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ + #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define TIMER_INTENSET_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define TIMER_INTENSET_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define TIMER_INTENSET_COMPARE4_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ + #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ + #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define TIMER_INTENSET_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define TIMER_INTENSET_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define TIMER_INTENSET_COMPARE5_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 22 : Write '1' to enable interrupt for event COMPARE[6] */ + #define TIMER_INTENSET_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */ + #define TIMER_INTENSET_COMPARE6_Msk (0x1UL << TIMER_INTENSET_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define TIMER_INTENSET_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define TIMER_INTENSET_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define TIMER_INTENSET_COMPARE6_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 23 : Write '1' to enable interrupt for event COMPARE[7] */ + #define TIMER_INTENSET_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ + #define TIMER_INTENSET_COMPARE7_Msk (0x1UL << TIMER_INTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define TIMER_INTENSET_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define TIMER_INTENSET_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define TIMER_INTENSET_COMPARE7_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TIMER_INTENCLR: Disable interrupt */ + #define TIMER_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* COMPARE0 @Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ + #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ + #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define TIMER_INTENCLR_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define TIMER_INTENCLR_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define TIMER_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ + #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ + #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define TIMER_INTENCLR_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define TIMER_INTENCLR_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define TIMER_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ + #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ + #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define TIMER_INTENCLR_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define TIMER_INTENCLR_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define TIMER_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ + #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ + #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define TIMER_INTENCLR_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define TIMER_INTENCLR_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define TIMER_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ + #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ + #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define TIMER_INTENCLR_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define TIMER_INTENCLR_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define TIMER_INTENCLR_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ + #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ + #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define TIMER_INTENCLR_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define TIMER_INTENCLR_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define TIMER_INTENCLR_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 22 : Write '1' to disable interrupt for event COMPARE[6] */ + #define TIMER_INTENCLR_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */ + #define TIMER_INTENCLR_COMPARE6_Msk (0x1UL << TIMER_INTENCLR_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define TIMER_INTENCLR_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define TIMER_INTENCLR_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define TIMER_INTENCLR_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 23 : Write '1' to disable interrupt for event COMPARE[7] */ + #define TIMER_INTENCLR_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ + #define TIMER_INTENCLR_COMPARE7_Msk (0x1UL << TIMER_INTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define TIMER_INTENCLR_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define TIMER_INTENCLR_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define TIMER_INTENCLR_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TIMER_MODE: Timer mode selection */ + #define TIMER_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* MODE @Bits 0..1 : Timer mode */ + #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define TIMER_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define TIMER_MODE_MODE_Max (0x2UL) /*!< Max enumerator value of MODE field. */ + #define TIMER_MODE_MODE_Timer (0x0UL) /*!< Select Timer mode */ + #define TIMER_MODE_MODE_Counter (0x1UL) /*!< Select Counter mode */ + #define TIMER_MODE_MODE_LowPowerCounter (0x2UL) /*!< Select Low Power Counter mode */ + + +/* TIMER_BITMODE: Configure the number of bits used by the TIMER */ + #define TIMER_BITMODE_ResetValue (0x00000000UL) /*!< Reset value of BITMODE register. */ + +/* BITMODE @Bits 0..1 : Timer bit width */ + #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ + #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ + #define TIMER_BITMODE_BITMODE_Min (0x0UL) /*!< Min enumerator value of BITMODE field. */ + #define TIMER_BITMODE_BITMODE_Max (0x3UL) /*!< Max enumerator value of BITMODE field. */ + #define TIMER_BITMODE_BITMODE_16Bit (0x0UL) /*!< 16 bit timer bit width */ + #define TIMER_BITMODE_BITMODE_08Bit (0x1UL) /*!< 8 bit timer bit width */ + #define TIMER_BITMODE_BITMODE_24Bit (0x2UL) /*!< 24 bit timer bit width */ + #define TIMER_BITMODE_BITMODE_32Bit (0x3UL) /*!< 32 bit timer bit width */ + + +/* TIMER_PRESCALER: Timer prescaler register */ + #define TIMER_PRESCALER_ResetValue (0x00000004UL) /*!< Reset value of PRESCALER register. */ + +/* PRESCALER @Bits 0..3 : Prescaler value */ + #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ + #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + #define TIMER_PRESCALER_PRESCALER_Min (0x0UL) /*!< Min value of PRESCALER field. */ + #define TIMER_PRESCALER_PRESCALER_Max (0x9UL) /*!< Max size of PRESCALER field. */ + + +/* TIMER_CC: Capture/Compare register n */ + #define TIMER_CC_MaxCount (8UL) /*!< Max size of CC[8] array. */ + #define TIMER_CC_MaxIndex (7UL) /*!< Max index of CC[8] array. */ + #define TIMER_CC_MinIndex (0UL) /*!< Min index of CC[8] array. */ + #define TIMER_CC_ResetValue (0x00000000UL) /*!< Reset value of CC[8] register. */ + +/* CC @Bits 0..31 : Capture/Compare value */ + #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ + #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* TIMER_ONESHOTEN: Enable one-shot operation for Capture/Compare channel n */ + #define TIMER_ONESHOTEN_MaxCount (8UL) /*!< Max size of ONESHOTEN[8] array. */ + #define TIMER_ONESHOTEN_MaxIndex (7UL) /*!< Max index of ONESHOTEN[8] array. */ + #define TIMER_ONESHOTEN_MinIndex (0UL) /*!< Min index of ONESHOTEN[8] array. */ + #define TIMER_ONESHOTEN_ResetValue (0x00000000UL) /*!< Reset value of ONESHOTEN[8] register. */ + +/* ONESHOTEN @Bit 0 : Enable one-shot operation */ + #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */ + #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */ + #define TIMER_ONESHOTEN_ONESHOTEN_Min (0x0UL) /*!< Min enumerator value of ONESHOTEN field. */ + #define TIMER_ONESHOTEN_ONESHOTEN_Max (0x1UL) /*!< Max enumerator value of ONESHOTEN field. */ + #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0x0UL) /*!< Disable one-shot operation */ + #define TIMER_ONESHOTEN_ONESHOTEN_Enable (0x1UL) /*!< Enable one-shot operation */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TPIU ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct TPIU ======================================================= */ +/** + * @brief Trace Port Interface Unit + */ + typedef struct { /*!< TPIU Structure */ + __IM uint32_t RESERVED; + } NRF_TPIU_Type; /*!< Size = 4 (0x004) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TWIM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct TWIM_TASKS_DMA_RX ================================================= */ +/** + * @brief RX [TWIM_TASKS_DMA_RX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See + peripheral description for operation using easyDMA.*/ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ + __OM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000008) Enables the MATCH[n] event by setting the ENABLE[n] bit + in the CONFIG register.*/ + __OM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000018) Disables the MATCH[n] event by clearing the ENABLE[n] + bit in the CONFIG register.*/ +} NRF_TWIM_TASKS_DMA_RX_Type; /*!< Size = 40 (0x028) */ + +/* TWIM_TASKS_DMA_RX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using + easyDMA. */ + + #define TWIM_TASKS_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */ + #define TWIM_TASKS_DMA_RX_START_START_Pos (0UL) /*!< Position of START field. */ + #define TWIM_TASKS_DMA_RX_START_START_Msk (0x1UL << TWIM_TASKS_DMA_RX_START_START_Pos) /*!< Bit mask of START field. */ + #define TWIM_TASKS_DMA_RX_START_START_Min (0x1UL) /*!< Min enumerator value of START field. */ + #define TWIM_TASKS_DMA_RX_START_START_Max (0x1UL) /*!< Max enumerator value of START field. */ + #define TWIM_TASKS_DMA_RX_START_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_DMA_RX_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define TWIM_TASKS_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define TWIM_TASKS_DMA_RX_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define TWIM_TASKS_DMA_RX_STOP_STOP_Msk (0x1UL << TWIM_TASKS_DMA_RX_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define TWIM_TASKS_DMA_RX_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define TWIM_TASKS_DMA_RX_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define TWIM_TASKS_DMA_RX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask + of ENABLEMATCH field.*/ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit + mask of DISABLEMATCH field.*/ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================ Struct TWIM_TASKS_DMA_TX ================================================= */ +/** + * @brief TX [TWIM_TASKS_DMA_TX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See + peripheral description for operation using easyDMA.*/ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ +} NRF_TWIM_TASKS_DMA_TX_Type; /*!< Size = 8 (0x008) */ + +/* TWIM_TASKS_DMA_TX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using + easyDMA. */ + + #define TWIM_TASKS_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */ + #define TWIM_TASKS_DMA_TX_START_START_Pos (0UL) /*!< Position of START field. */ + #define TWIM_TASKS_DMA_TX_START_START_Msk (0x1UL << TWIM_TASKS_DMA_TX_START_START_Pos) /*!< Bit mask of START field. */ + #define TWIM_TASKS_DMA_TX_START_START_Min (0x1UL) /*!< Min enumerator value of START field. */ + #define TWIM_TASKS_DMA_TX_START_START_Max (0x1UL) /*!< Max enumerator value of START field. */ + #define TWIM_TASKS_DMA_TX_START_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_DMA_TX_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define TWIM_TASKS_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define TWIM_TASKS_DMA_TX_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define TWIM_TASKS_DMA_TX_STOP_STOP_Msk (0x1UL << TWIM_TASKS_DMA_TX_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define TWIM_TASKS_DMA_TX_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define TWIM_TASKS_DMA_TX_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define TWIM_TASKS_DMA_TX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================== Struct TWIM_TASKS_DMA ================================================== */ +/** + * @brief TASKS_DMA [TWIM_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __OM NRF_TWIM_TASKS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral tasks. */ + __OM NRF_TWIM_TASKS_DMA_TX_Type TX; /*!< (@ 0x00000028) Peripheral tasks. */ +} NRF_TWIM_TASKS_DMA_Type; /*!< Size = 48 (0x030) */ + + +/* ============================================== Struct TWIM_SUBSCRIBE_DMA_RX =============================================== */ +/** + * @brief RX [TWIM_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ + __IOM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000008) Subscribe configuration for task ENABLEMATCH[n] */ + __IOM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000018) Subscribe configuration for task DISABLEMATCH[n] */ +} NRF_TWIM_SUBSCRIBE_DMA_RX_Type; /*!< Size = 40 (0x028) */ + +/* TWIM_SUBSCRIBE_DMA_RX_START: Subscribe configuration for task START */ + #define TWIM_SUBSCRIBE_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_START_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_DMA_RX_STOP: Subscribe configuration for task STOP */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ============================================== Struct TWIM_SUBSCRIBE_DMA_TX =============================================== */ +/** + * @brief TX [TWIM_SUBSCRIBE_DMA_TX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ +} NRF_TWIM_SUBSCRIBE_DMA_TX_Type; /*!< Size = 8 (0x008) */ + +/* TWIM_SUBSCRIBE_DMA_TX_START: Subscribe configuration for task START */ + #define TWIM_SUBSCRIBE_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_TX_START_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_DMA_TX_STOP: Subscribe configuration for task STOP */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ================================================ Struct TWIM_SUBSCRIBE_DMA ================================================ */ +/** + * @brief SUBSCRIBE_DMA [TWIM_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IOM NRF_TWIM_SUBSCRIBE_DMA_RX_Type RX; /*!< (@ 0x00000000) Subscribe configuration for tasks */ + __IOM NRF_TWIM_SUBSCRIBE_DMA_TX_Type TX; /*!< (@ 0x00000028) Subscribe configuration for tasks */ +} NRF_TWIM_SUBSCRIBE_DMA_Type; /*!< Size = 48 (0x030) */ + + +/* ================================================ Struct TWIM_EVENTS_DMA_RX ================================================ */ +/** + * @brief RX [TWIM_EVENTS_DMA_RX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Indicates that the transfer of MAXCNT bytes between + memory and the peripheral has been fully completed.*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ +} NRF_TWIM_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* TWIM_EVENTS_DMA_RX_END: Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully + completed. */ + + #define TWIM_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. */ + #define TWIM_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ + #define TWIM_EVENTS_DMA_RX_END_END_Msk (0x1UL << TWIM_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ + #define TWIM_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define TWIM_EVENTS_DMA_RX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define TWIM_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define TWIM_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define TWIM_EVENTS_DMA_RX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define TWIM_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << TWIM_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define TWIM_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define TWIM_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define TWIM_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define TWIM_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << TWIM_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================ Struct TWIM_EVENTS_DMA_TX ================================================ */ +/** + * @brief TX [TWIM_EVENTS_DMA_TX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Indicates that the transfer of MAXCNT bytes between + memory and the peripheral has been fully completed.*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_TWIM_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* TWIM_EVENTS_DMA_TX_END: Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully + completed. */ + + #define TWIM_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Indicates that the transfer of MAXCNT bytes between memory and the peripheral has been fully completed. */ + #define TWIM_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ + #define TWIM_EVENTS_DMA_TX_END_END_Msk (0x1UL << TWIM_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ + #define TWIM_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define TWIM_EVENTS_DMA_TX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define TWIM_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define TWIM_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define TWIM_EVENTS_DMA_TX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define TWIM_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << TWIM_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define TWIM_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define TWIM_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define TWIM_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct TWIM_EVENTS_DMA ================================================== */ +/** + * @brief EVENTS_DMA [TWIM_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_TWIM_EVENTS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral events. */ + __IOM NRF_TWIM_EVENTS_DMA_TX_Type TX; /*!< (@ 0x0000001C) Peripheral events. */ +} NRF_TWIM_EVENTS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* =============================================== Struct TWIM_PUBLISH_DMA_RX ================================================ */ +/** + * @brief RX [TWIM_PUBLISH_DMA_RX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Publish configuration for event MATCH[n] */ +} NRF_TWIM_PUBLISH_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* TWIM_PUBLISH_DMA_RX_END: Publish configuration for event END */ + #define TWIM_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_DMA_RX_READY: Publish configuration for event READY */ + #define TWIM_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */ + #define TWIM_PUBLISH_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */ + #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* =============================================== Struct TWIM_PUBLISH_DMA_TX ================================================ */ +/** + * @brief TX [TWIM_PUBLISH_DMA_TX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_TWIM_PUBLISH_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* TWIM_PUBLISH_DMA_TX_END: Publish configuration for event END */ + #define TWIM_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_DMA_TX_READY: Publish configuration for event READY */ + #define TWIM_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================= Struct TWIM_PUBLISH_DMA ================================================= */ +/** + * @brief PUBLISH_DMA [TWIM_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_TWIM_PUBLISH_DMA_RX_Type RX; /*!< (@ 0x00000000) Publish configuration for events */ + __IOM NRF_TWIM_PUBLISH_DMA_TX_Type TX; /*!< (@ 0x0000001C) Publish configuration for events */ +} NRF_TWIM_PUBLISH_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ==================================================== Struct TWIM_PSEL ===================================================== */ +/** + * @brief PSEL [TWIM_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} NRF_TWIM_PSEL_Type; /*!< Size = 8 (0x008) */ + +/* TWIM_PSEL_SCL: Pin select for SCL signal */ + #define TWIM_PSEL_SCL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SCL register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TWIM_PSEL_SCL_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TWIM_PSEL_SCL_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TWIM_PSEL_SCL_PORT_Msk (0x7UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TWIM_PSEL_SCL_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TWIM_PSEL_SCL_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TWIM_PSEL_SCL_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TWIM_PSEL_SCL_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TWIM_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TWIM_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* TWIM_PSEL_SDA: Pin select for SDA signal */ + #define TWIM_PSEL_SDA_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SDA register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TWIM_PSEL_SDA_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TWIM_PSEL_SDA_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TWIM_PSEL_SDA_PORT_Msk (0x7UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TWIM_PSEL_SDA_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TWIM_PSEL_SDA_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TWIM_PSEL_SDA_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TWIM_PSEL_SDA_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TWIM_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TWIM_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================ Struct TWIM_DMA_RX_MATCH ================================================= */ +/** + * @brief MATCH [TWIM_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Configure individual match events */ + __IOM uint32_t CANDIDATE[4]; /*!< (@ 0x00000004) The data to look for - any match will trigger the + MATCH[n] event, if enabled.*/ +} NRF_TWIM_DMA_RX_MATCH_Type; /*!< Size = 20 (0x014) */ + +/* TWIM_DMA_RX_MATCH_CONFIG: Configure individual match events */ + #define TWIM_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ENABLE0 @Bit 0 : Enable match filter 0 */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE1 @Bit 1 : Enable match filter 1 */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE2 @Bit 2 : Enable match filter 2 */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE3 @Bit 3 : Enable match filter 3 */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or continous */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0 + field.*/ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or continous */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1 + field.*/ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or continous */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2 + field.*/ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or continous */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3 + field.*/ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + + +/* TWIM_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array. */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array. */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array. */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register. */ + +/* DATA @Bits 0..7 : Data to look for */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFUL << TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA field. */ + + + +/* =================================================== Struct TWIM_DMA_RX ==================================================== */ +/** + * @brief RX [TWIM_DMA_RX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ + __IOM NRF_TWIM_DMA_RX_MATCH_Type MATCH; /*!< (@ 0x00000024) Registers to control the behavior of the pattern + matcher engine*/ +} NRF_TWIM_DMA_RX_Type; /*!< Size = 56 (0x038) */ + +/* TWIM_DMA_RX_PTR: RAM buffer start address */ + #define TWIM_DMA_RX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define TWIM_DMA_RX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define TWIM_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* TWIM_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */ + #define TWIM_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define TWIM_DMA_RX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define TWIM_DMA_RX_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TWIM_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define TWIM_DMA_RX_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ + + +/* TWIM_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define TWIM_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define TWIM_DMA_RX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIM_DMA_RX_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TWIM_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIM_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIM_DMA_RX_LIST: EasyDMA list type */ + #define TWIM_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIM_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Msk (0x7UL << TWIM_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIM_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* TWIM_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* TWIM_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define TWIM_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* =================================================== Struct TWIM_DMA_TX ==================================================== */ +/** + * @brief TX [TWIM_DMA_TX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_TWIM_DMA_TX_Type; /*!< Size = 36 (0x024) */ + +/* TWIM_DMA_TX_PTR: RAM buffer start address */ + #define TWIM_DMA_TX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define TWIM_DMA_TX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define TWIM_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* TWIM_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */ + #define TWIM_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define TWIM_DMA_TX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define TWIM_DMA_TX_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TWIM_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define TWIM_DMA_TX_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ + + +/* TWIM_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define TWIM_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define TWIM_DMA_TX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIM_DMA_TX_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TWIM_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIM_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIM_DMA_TX_LIST: EasyDMA list type */ + #define TWIM_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIM_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Msk (0x7UL << TWIM_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIM_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* TWIM_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* TWIM_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define TWIM_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ===================================================== Struct TWIM_DMA ===================================================== */ +/** + * @brief DMA [TWIM_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_TWIM_DMA_RX_Type RX; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_TWIM_DMA_TX_Type TX; /*!< (@ 0x00000038) (unspecified) */ +} NRF_TWIM_DMA_Type; /*!< Size = 92 (0x05C) */ + +/* ======================================================= Struct TWIM ======================================================= */ +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA + */ + typedef struct { /*!< TWIM Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop TWI transaction. Must be issued while the TWI + master is not suspended.*/ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000000C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000010) Resume TWI transaction */ + __IM uint32_t RESERVED2[5]; + __OM NRF_TWIM_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000028) Peripheral tasks. */ + __IM uint32_t RESERVED3[11]; + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED4; + __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000008C) Subscribe configuration for task SUSPEND */ + __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x00000090) Subscribe configuration for task RESUME */ + __IM uint32_t RESERVED5[5]; + __IOM NRF_TWIM_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000114) TWI error */ + __IM uint32_t RESERVED8[4]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000128) SUSPEND task has been issued, TWI traffic is now + suspended.*/ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x00000134) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000138) Byte boundary, starting to transmit the last byte */ + __IM uint32_t RESERVED10[4]; + __IOM NRF_TWIM_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x0000014C) Peripheral events. */ + __IM uint32_t RESERVED11[4]; + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000194) Publish configuration for event ERROR */ + __IM uint32_t RESERVED13[4]; + __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001A8) Publish configuration for event SUSPENDED */ + __IM uint32_t RESERVED14[2]; + __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001B4) Publish configuration for event LASTRX */ + __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001B8) Publish configuration for event LASTTX */ + __IM uint32_t RESERVED15[4]; + __IOM NRF_TWIM_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001CC) Publish configuration for events */ + __IM uint32_t RESERVED16[3]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED17[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED18[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED19[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED20[8]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK source + selected.*/ + __IM uint32_t RESERVED21[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ + __IM uint32_t RESERVED22[29]; + __IOM NRF_TWIM_PSEL_Type PSEL; /*!< (@ 0x00000600) (unspecified) */ + __IM uint32_t RESERVED23[62]; + __IOM NRF_TWIM_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_TWIM_Type; /*!< Size = 1884 (0x75C) */ + +/* TWIM_TASKS_STOP: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ + #define TWIM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ + #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define TWIM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define TWIM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_SUSPEND: Suspend TWI transaction */ + #define TWIM_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register. */ + +/* TASKS_SUSPEND @Bit 0 : Suspend TWI transaction */ + #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ + #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND + field.*/ + #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field. */ + #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field. */ + #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_RESUME: Resume TWI transaction */ + #define TWIM_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register. */ + +/* TASKS_RESUME @Bit 0 : Resume TWI transaction */ + #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ + #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/ + #define TWIM_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field. */ + #define TWIM_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field. */ + #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define TWIM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */ + #define TWIM_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */ + #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */ + #define TWIM_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */ + #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_SUBSCRIBE_RESUME_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_RESUME_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_RESUME_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_EVENTS_STOPPED: TWI stopped */ + #define TWIM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : TWI stopped */ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_ERROR: TWI error */ + #define TWIM_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : TWI error */ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.*/ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_SUSPENDED: SUSPEND task has been issued, TWI traffic is now suspended. */ + #define TWIM_EVENTS_SUSPENDED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SUSPENDED register. */ + +/* EVENTS_SUSPENDED @Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of + EVENTS_SUSPENDED field.*/ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Min (0x0UL) /*!< Min enumerator value of EVENTS_SUSPENDED field. */ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Max (0x1UL) /*!< Max enumerator value of EVENTS_SUSPENDED field. */ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_LASTRX: Byte boundary, starting to receive the last byte */ + #define TWIM_EVENTS_LASTRX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LASTRX register. */ + +/* EVENTS_LASTRX @Bit 0 : Byte boundary, starting to receive the last byte */ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX + field.*/ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Min (0x0UL) /*!< Min enumerator value of EVENTS_LASTRX field. */ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Max (0x1UL) /*!< Max enumerator value of EVENTS_LASTRX field. */ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_LASTTX: Byte boundary, starting to transmit the last byte */ + #define TWIM_EVENTS_LASTTX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LASTTX register. */ + +/* EVENTS_LASTTX @Bit 0 : Byte boundary, starting to transmit the last byte */ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX + field.*/ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Min (0x0UL) /*!< Min enumerator value of EVENTS_LASTTX field. */ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Max (0x1UL) /*!< Max enumerator value of EVENTS_LASTTX field. */ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define TWIM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define TWIM_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_SUSPENDED: Publish configuration for event SUSPENDED */ + #define TWIM_PUBLISH_SUSPENDED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SUSPENDED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SUSPENDED will publish to */ + #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_SUSPENDED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_SUSPENDED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_SUSPENDED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_SUSPENDED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_LASTRX: Publish configuration for event LASTRX */ + #define TWIM_PUBLISH_LASTRX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LASTRX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event LASTRX will publish to */ + #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_LASTRX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_LASTRX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_LASTRX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_LASTRX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_LASTRX_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_LASTRX_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_LASTTX: Publish configuration for event LASTTX */ + #define TWIM_PUBLISH_LASTTX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LASTTX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event LASTTX will publish to */ + #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_LASTTX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_LASTTX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_LASTTX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_LASTTX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_LASTTX_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_LASTTX_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_SHORTS: Shortcuts between local events and tasks */ + #define TWIM_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* LASTTX_DMA_RX_START @Bit 7 : Shortcut between event LASTTX and task DMA.RX.START */ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Pos (7UL) /*!< Position of LASTTX_DMA_RX_START field. */ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Msk (0x1UL << TWIM_SHORTS_LASTTX_DMA_RX_START_Pos) /*!< Bit mask of + LASTTX_DMA_RX_START field.*/ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Min (0x0UL) /*!< Min enumerator value of LASTTX_DMA_RX_START field. */ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Max (0x1UL) /*!< Max enumerator value of LASTTX_DMA_RX_START field. */ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LASTTX_SUSPEND @Bit 8 : Shortcut between event LASTTX and task SUSPEND */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Min (0x0UL) /*!< Min enumerator value of LASTTX_SUSPEND field. */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Max (0x1UL) /*!< Max enumerator value of LASTTX_SUSPEND field. */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LASTTX_STOP @Bit 9 : Shortcut between event LASTTX and task STOP */ + #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ + #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ + #define TWIM_SHORTS_LASTTX_STOP_Min (0x0UL) /*!< Min enumerator value of LASTTX_STOP field. */ + #define TWIM_SHORTS_LASTTX_STOP_Max (0x1UL) /*!< Max enumerator value of LASTTX_STOP field. */ + #define TWIM_SHORTS_LASTTX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_LASTTX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LASTRX_DMA_TX_START @Bit 10 : Shortcut between event LASTRX and task DMA.TX.START */ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Pos (10UL) /*!< Position of LASTRX_DMA_TX_START field. */ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Msk (0x1UL << TWIM_SHORTS_LASTRX_DMA_TX_START_Pos) /*!< Bit mask of + LASTRX_DMA_TX_START field.*/ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Min (0x0UL) /*!< Min enumerator value of LASTRX_DMA_TX_START field. */ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Max (0x1UL) /*!< Max enumerator value of LASTRX_DMA_TX_START field. */ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LASTRX_STOP @Bit 12 : Shortcut between event LASTRX and task STOP */ + #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ + #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ + #define TWIM_SHORTS_LASTRX_STOP_Min (0x0UL) /*!< Min enumerator value of LASTRX_STOP field. */ + #define TWIM_SHORTS_LASTRX_STOP_Max (0x1UL) /*!< Max enumerator value of LASTRX_STOP field. */ + #define TWIM_SHORTS_LASTRX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_LASTRX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows + daisy-chaining match events. */ + + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows + daisy-chaining match events. */ + + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows + daisy-chaining match events. */ + + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows + daisy-chaining match events. */ + + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* TWIM_INTEN: Enable or disable interrupt */ + #define TWIM_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */ + #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIM_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIM_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* ERROR @Bit 5 : Enable or disable interrupt for event ERROR */ + #define TWIM_INTEN_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIM_INTEN_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIM_INTEN_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIM_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ + +/* SUSPENDED @Bit 10 : Enable or disable interrupt for event SUSPENDED */ + #define TWIM_INTEN_SUSPENDED_Pos (10UL) /*!< Position of SUSPENDED field. */ + #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ + #define TWIM_INTEN_SUSPENDED_Min (0x0UL) /*!< Min enumerator value of SUSPENDED field. */ + #define TWIM_INTEN_SUSPENDED_Max (0x1UL) /*!< Max enumerator value of SUSPENDED field. */ + #define TWIM_INTEN_SUSPENDED_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_SUSPENDED_Enabled (0x1UL) /*!< Enable */ + +/* LASTRX @Bit 13 : Enable or disable interrupt for event LASTRX */ + #define TWIM_INTEN_LASTRX_Pos (13UL) /*!< Position of LASTRX field. */ + #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ + #define TWIM_INTEN_LASTRX_Min (0x0UL) /*!< Min enumerator value of LASTRX field. */ + #define TWIM_INTEN_LASTRX_Max (0x1UL) /*!< Max enumerator value of LASTRX field. */ + #define TWIM_INTEN_LASTRX_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_LASTRX_Enabled (0x1UL) /*!< Enable */ + +/* LASTTX @Bit 14 : Enable or disable interrupt for event LASTTX */ + #define TWIM_INTEN_LASTTX_Pos (14UL) /*!< Position of LASTTX field. */ + #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ + #define TWIM_INTEN_LASTTX_Min (0x0UL) /*!< Min enumerator value of LASTTX field. */ + #define TWIM_INTEN_LASTTX_Max (0x1UL) /*!< Max enumerator value of LASTTX field. */ + #define TWIM_INTEN_LASTTX_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_LASTTX_Enabled (0x1UL) /*!< Enable */ + +/* DMARXEND @Bit 19 : Enable or disable interrupt for event DMARXEND */ + #define TWIM_INTEN_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIM_INTEN_DMARXEND_Msk (0x1UL << TWIM_INTEN_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIM_INTEN_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIM_INTEN_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIM_INTEN_DMARXEND_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMARXREADY @Bit 20 : Enable or disable interrupt for event DMARXREADY */ + #define TWIM_INTEN_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIM_INTEN_DMARXREADY_Msk (0x1UL << TWIM_INTEN_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIM_INTEN_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIM_INTEN_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIM_INTEN_DMARXREADY_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMARXBUSERROR @Bit 21 : Enable or disable interrupt for event DMARXBUSERROR */ + #define TWIM_INTEN_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIM_INTEN_DMARXBUSERROR_Msk (0x1UL << TWIM_INTEN_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIM_INTEN_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTEN_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTEN_DMARXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXBUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH0 @Bit 22 : Enable or disable interrupt for event DMARXMATCH[0] */ + #define TWIM_INTEN_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIM_INTEN_DMARXMATCH0_Msk (0x1UL << TWIM_INTEN_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIM_INTEN_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTEN_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTEN_DMARXMATCH0_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXMATCH0_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH1 @Bit 23 : Enable or disable interrupt for event DMARXMATCH[1] */ + #define TWIM_INTEN_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIM_INTEN_DMARXMATCH1_Msk (0x1UL << TWIM_INTEN_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIM_INTEN_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTEN_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTEN_DMARXMATCH1_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXMATCH1_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH2 @Bit 24 : Enable or disable interrupt for event DMARXMATCH[2] */ + #define TWIM_INTEN_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIM_INTEN_DMARXMATCH2_Msk (0x1UL << TWIM_INTEN_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIM_INTEN_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTEN_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTEN_DMARXMATCH2_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXMATCH2_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH3 @Bit 25 : Enable or disable interrupt for event DMARXMATCH[3] */ + #define TWIM_INTEN_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIM_INTEN_DMARXMATCH3_Msk (0x1UL << TWIM_INTEN_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIM_INTEN_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTEN_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTEN_DMARXMATCH3_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXMATCH3_Enabled (0x1UL) /*!< Enable */ + +/* DMATXEND @Bit 26 : Enable or disable interrupt for event DMATXEND */ + #define TWIM_INTEN_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIM_INTEN_DMATXEND_Msk (0x1UL << TWIM_INTEN_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIM_INTEN_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIM_INTEN_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIM_INTEN_DMATXEND_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMATXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMATXREADY @Bit 27 : Enable or disable interrupt for event DMATXREADY */ + #define TWIM_INTEN_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIM_INTEN_DMATXREADY_Msk (0x1UL << TWIM_INTEN_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIM_INTEN_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIM_INTEN_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIM_INTEN_DMATXREADY_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMATXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMATXBUSERROR @Bit 28 : Enable or disable interrupt for event DMATXBUSERROR */ + #define TWIM_INTEN_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIM_INTEN_DMATXBUSERROR_Msk (0x1UL << TWIM_INTEN_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIM_INTEN_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTEN_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTEN_DMATXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMATXBUSERROR_Enabled (0x1UL) /*!< Enable */ + + +/* TWIM_INTENSET: Enable interrupt */ + #define TWIM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIM_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIM_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to enable interrupt for event ERROR */ + #define TWIM_INTENSET_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIM_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIM_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIM_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SUSPENDED @Bit 10 : Write '1' to enable interrupt for event SUSPENDED */ + #define TWIM_INTENSET_SUSPENDED_Pos (10UL) /*!< Position of SUSPENDED field. */ + #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ + #define TWIM_INTENSET_SUSPENDED_Min (0x0UL) /*!< Min enumerator value of SUSPENDED field. */ + #define TWIM_INTENSET_SUSPENDED_Max (0x1UL) /*!< Max enumerator value of SUSPENDED field. */ + #define TWIM_INTENSET_SUSPENDED_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LASTRX @Bit 13 : Write '1' to enable interrupt for event LASTRX */ + #define TWIM_INTENSET_LASTRX_Pos (13UL) /*!< Position of LASTRX field. */ + #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ + #define TWIM_INTENSET_LASTRX_Min (0x0UL) /*!< Min enumerator value of LASTRX field. */ + #define TWIM_INTENSET_LASTRX_Max (0x1UL) /*!< Max enumerator value of LASTRX field. */ + #define TWIM_INTENSET_LASTRX_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LASTTX @Bit 14 : Write '1' to enable interrupt for event LASTTX */ + #define TWIM_INTENSET_LASTTX_Pos (14UL) /*!< Position of LASTTX field. */ + #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ + #define TWIM_INTENSET_LASTTX_Min (0x0UL) /*!< Min enumerator value of LASTTX field. */ + #define TWIM_INTENSET_LASTTX_Max (0x1UL) /*!< Max enumerator value of LASTTX field. */ + #define TWIM_INTENSET_LASTTX_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */ + #define TWIM_INTENSET_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIM_INTENSET_DMARXEND_Msk (0x1UL << TWIM_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIM_INTENSET_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIM_INTENSET_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIM_INTENSET_DMARXEND_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */ + #define TWIM_INTENSET_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIM_INTENSET_DMARXREADY_Msk (0x1UL << TWIM_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIM_INTENSET_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIM_INTENSET_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIM_INTENSET_DMARXREADY_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */ + #define TWIM_INTENSET_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIM_INTENSET_DMARXBUSERROR_Msk (0x1UL << TWIM_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIM_INTENSET_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTENSET_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTENSET_DMARXBUSERROR_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */ + #define TWIM_INTENSET_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIM_INTENSET_DMARXMATCH0_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIM_INTENSET_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTENSET_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTENSET_DMARXMATCH0_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */ + #define TWIM_INTENSET_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIM_INTENSET_DMARXMATCH1_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIM_INTENSET_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTENSET_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTENSET_DMARXMATCH1_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */ + #define TWIM_INTENSET_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIM_INTENSET_DMARXMATCH2_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIM_INTENSET_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTENSET_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTENSET_DMARXMATCH2_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */ + #define TWIM_INTENSET_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIM_INTENSET_DMARXMATCH3_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIM_INTENSET_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTENSET_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTENSET_DMARXMATCH3_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */ + #define TWIM_INTENSET_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIM_INTENSET_DMATXEND_Msk (0x1UL << TWIM_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIM_INTENSET_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIM_INTENSET_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIM_INTENSET_DMATXEND_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */ + #define TWIM_INTENSET_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIM_INTENSET_DMATXREADY_Msk (0x1UL << TWIM_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIM_INTENSET_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIM_INTENSET_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIM_INTENSET_DMATXREADY_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */ + #define TWIM_INTENSET_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIM_INTENSET_DMATXBUSERROR_Msk (0x1UL << TWIM_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIM_INTENSET_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTENSET_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTENSET_DMATXBUSERROR_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TWIM_INTENCLR: Disable interrupt */ + #define TWIM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIM_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIM_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to disable interrupt for event ERROR */ + #define TWIM_INTENCLR_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIM_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIM_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIM_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SUSPENDED @Bit 10 : Write '1' to disable interrupt for event SUSPENDED */ + #define TWIM_INTENCLR_SUSPENDED_Pos (10UL) /*!< Position of SUSPENDED field. */ + #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ + #define TWIM_INTENCLR_SUSPENDED_Min (0x0UL) /*!< Min enumerator value of SUSPENDED field. */ + #define TWIM_INTENCLR_SUSPENDED_Max (0x1UL) /*!< Max enumerator value of SUSPENDED field. */ + #define TWIM_INTENCLR_SUSPENDED_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LASTRX @Bit 13 : Write '1' to disable interrupt for event LASTRX */ + #define TWIM_INTENCLR_LASTRX_Pos (13UL) /*!< Position of LASTRX field. */ + #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ + #define TWIM_INTENCLR_LASTRX_Min (0x0UL) /*!< Min enumerator value of LASTRX field. */ + #define TWIM_INTENCLR_LASTRX_Max (0x1UL) /*!< Max enumerator value of LASTRX field. */ + #define TWIM_INTENCLR_LASTRX_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LASTTX @Bit 14 : Write '1' to disable interrupt for event LASTTX */ + #define TWIM_INTENCLR_LASTTX_Pos (14UL) /*!< Position of LASTTX field. */ + #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ + #define TWIM_INTENCLR_LASTTX_Min (0x0UL) /*!< Min enumerator value of LASTTX field. */ + #define TWIM_INTENCLR_LASTTX_Max (0x1UL) /*!< Max enumerator value of LASTTX field. */ + #define TWIM_INTENCLR_LASTTX_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */ + #define TWIM_INTENCLR_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIM_INTENCLR_DMARXEND_Msk (0x1UL << TWIM_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIM_INTENCLR_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIM_INTENCLR_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIM_INTENCLR_DMARXEND_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */ + #define TWIM_INTENCLR_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIM_INTENCLR_DMARXREADY_Msk (0x1UL << TWIM_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIM_INTENCLR_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIM_INTENCLR_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIM_INTENCLR_DMARXREADY_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */ + #define TWIM_INTENCLR_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIM_INTENCLR_DMARXBUSERROR_Msk (0x1UL << TWIM_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIM_INTENCLR_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTENCLR_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTENCLR_DMARXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */ + #define TWIM_INTENCLR_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIM_INTENCLR_DMARXMATCH0_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIM_INTENCLR_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTENCLR_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTENCLR_DMARXMATCH0_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */ + #define TWIM_INTENCLR_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIM_INTENCLR_DMARXMATCH1_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIM_INTENCLR_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTENCLR_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTENCLR_DMARXMATCH1_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */ + #define TWIM_INTENCLR_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIM_INTENCLR_DMARXMATCH2_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIM_INTENCLR_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTENCLR_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTENCLR_DMARXMATCH2_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */ + #define TWIM_INTENCLR_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIM_INTENCLR_DMARXMATCH3_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIM_INTENCLR_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTENCLR_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTENCLR_DMARXMATCH3_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */ + #define TWIM_INTENCLR_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIM_INTENCLR_DMATXEND_Msk (0x1UL << TWIM_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIM_INTENCLR_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIM_INTENCLR_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIM_INTENCLR_DMATXEND_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */ + #define TWIM_INTENCLR_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIM_INTENCLR_DMATXREADY_Msk (0x1UL << TWIM_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIM_INTENCLR_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIM_INTENCLR_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIM_INTENCLR_DMATXREADY_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */ + #define TWIM_INTENCLR_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIM_INTENCLR_DMATXBUSERROR_Msk (0x1UL << TWIM_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIM_INTENCLR_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTENCLR_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTENCLR_DMATXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TWIM_ERRORSRC: Error source */ + #define TWIM_ERRORSRC_ResetValue (0x00000000UL) /*!< Reset value of ERRORSRC register. */ + +/* OVERRUN @Bit 0 : Overrun error */ + #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ + #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ + #define TWIM_ERRORSRC_OVERRUN_Min (0x0UL) /*!< Min enumerator value of OVERRUN field. */ + #define TWIM_ERRORSRC_OVERRUN_Max (0x1UL) /*!< Max enumerator value of OVERRUN field. */ + #define TWIM_ERRORSRC_OVERRUN_NotReceived (0x0UL) /*!< Error did not occur */ + #define TWIM_ERRORSRC_OVERRUN_Received (0x1UL) /*!< Error occurred */ + +/* ANACK @Bit 1 : NACK received after sending the address (write '1' to clear) */ + #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ + #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ + #define TWIM_ERRORSRC_ANACK_Min (0x0UL) /*!< Min enumerator value of ANACK field. */ + #define TWIM_ERRORSRC_ANACK_Max (0x1UL) /*!< Max enumerator value of ANACK field. */ + #define TWIM_ERRORSRC_ANACK_NotReceived (0x0UL) /*!< Error did not occur */ + #define TWIM_ERRORSRC_ANACK_Received (0x1UL) /*!< Error occurred */ + +/* DNACK @Bit 2 : NACK received after sending a data byte (write '1' to clear) */ + #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ + #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ + #define TWIM_ERRORSRC_DNACK_Min (0x0UL) /*!< Min enumerator value of DNACK field. */ + #define TWIM_ERRORSRC_DNACK_Max (0x1UL) /*!< Max enumerator value of DNACK field. */ + #define TWIM_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */ + #define TWIM_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */ + + +/* TWIM_ENABLE: Enable TWIM */ + #define TWIM_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..3 : Enable or disable TWIM */ + #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define TWIM_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIM_ENABLE_ENABLE_Max (0x6UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIM */ + #define TWIM_ENABLE_ENABLE_Enabled (0x6UL) /*!< Enable TWIM */ + + +/* TWIM_FREQUENCY: TWI frequency. Accuracy depends on the HFCLK source selected. */ + #define TWIM_FREQUENCY_ResetValue (0x04000000UL) /*!< Reset value of FREQUENCY register. */ + +/* FREQUENCY @Bits 0..31 : TWI master clock frequency */ + #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ + #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + #define TWIM_FREQUENCY_FREQUENCY_Min (0x01980000UL) /*!< Min enumerator value of FREQUENCY field. */ + #define TWIM_FREQUENCY_FREQUENCY_Max (0x0FF00000UL) /*!< Max enumerator value of FREQUENCY field. */ + #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ + #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ + #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + #define TWIM_FREQUENCY_FREQUENCY_K1000 (0x0FF00000UL) /*!< 1000 kbps */ + + +/* TWIM_ADDRESS: Address used in the TWI transfer */ + #define TWIM_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* ADDRESS @Bits 0..6 : Address used in the TWI transfer */ + #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TWIS ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct TWIS_TASKS_DMA_RX ================================================= */ +/** + * @brief RX [TWIS_TASKS_DMA_RX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Enables the MATCH[n] event by setting the ENABLE[n] bit + in the CONFIG register.*/ + __OM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Disables the MATCH[n] event by clearing the ENABLE[n] + bit in the CONFIG register.*/ +} NRF_TWIS_TASKS_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* TWIS_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask + of ENABLEMATCH field.*/ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit + mask of DISABLEMATCH field.*/ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================== Struct TWIS_TASKS_DMA ================================================== */ +/** + * @brief TASKS_DMA [TWIS_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __OM NRF_TWIS_TASKS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral tasks. */ +} NRF_TWIS_TASKS_DMA_Type; /*!< Size = 32 (0x020) */ + + +/* ============================================== Struct TWIS_SUBSCRIBE_DMA_RX =============================================== */ +/** + * @brief RX [TWIS_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Subscribe configuration for task ENABLEMATCH[n] */ + __IOM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Subscribe configuration for task DISABLEMATCH[n] */ +} NRF_TWIS_SUBSCRIBE_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ================================================ Struct TWIS_SUBSCRIBE_DMA ================================================ */ +/** + * @brief SUBSCRIBE_DMA [TWIS_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IOM NRF_TWIS_SUBSCRIBE_DMA_RX_Type RX; /*!< (@ 0x00000000) Subscribe configuration for tasks */ +} NRF_TWIS_SUBSCRIBE_DMA_Type; /*!< Size = 32 (0x020) */ + + +/* ================================================ Struct TWIS_EVENTS_DMA_RX ================================================ */ +/** + * @brief RX [TWIS_EVENTS_DMA_RX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ +} NRF_TWIS_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* TWIS_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ + #define TWIS_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define TWIS_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ + #define TWIS_EVENTS_DMA_RX_END_END_Msk (0x1UL << TWIS_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ + #define TWIS_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define TWIS_EVENTS_DMA_RX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define TWIS_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define TWIS_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define TWIS_EVENTS_DMA_RX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define TWIS_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << TWIS_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define TWIS_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define TWIS_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define TWIS_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define TWIS_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << TWIS_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================ Struct TWIS_EVENTS_DMA_TX ================================================ */ +/** + * @brief TX [TWIS_EVENTS_DMA_TX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_TWIS_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* TWIS_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ + #define TWIS_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define TWIS_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ + #define TWIS_EVENTS_DMA_TX_END_END_Msk (0x1UL << TWIS_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ + #define TWIS_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define TWIS_EVENTS_DMA_TX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define TWIS_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define TWIS_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define TWIS_EVENTS_DMA_TX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define TWIS_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << TWIS_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define TWIS_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define TWIS_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define TWIS_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct TWIS_EVENTS_DMA ================================================== */ +/** + * @brief EVENTS_DMA [TWIS_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_TWIS_EVENTS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral events. */ + __IOM NRF_TWIS_EVENTS_DMA_TX_Type TX; /*!< (@ 0x0000001C) Peripheral events. */ +} NRF_TWIS_EVENTS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* =============================================== Struct TWIS_PUBLISH_DMA_RX ================================================ */ +/** + * @brief RX [TWIS_PUBLISH_DMA_RX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Publish configuration for event MATCH[n] */ +} NRF_TWIS_PUBLISH_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* TWIS_PUBLISH_DMA_RX_END: Publish configuration for event END */ + #define TWIS_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_DMA_RX_READY: Publish configuration for event READY */ + #define TWIS_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */ + #define TWIS_PUBLISH_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */ + #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* =============================================== Struct TWIS_PUBLISH_DMA_TX ================================================ */ +/** + * @brief TX [TWIS_PUBLISH_DMA_TX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_TWIS_PUBLISH_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* TWIS_PUBLISH_DMA_TX_END: Publish configuration for event END */ + #define TWIS_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_DMA_TX_READY: Publish configuration for event READY */ + #define TWIS_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================= Struct TWIS_PUBLISH_DMA ================================================= */ +/** + * @brief PUBLISH_DMA [TWIS_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_TWIS_PUBLISH_DMA_RX_Type RX; /*!< (@ 0x00000000) Publish configuration for events */ + __IOM NRF_TWIS_PUBLISH_DMA_TX_Type TX; /*!< (@ 0x0000001C) Publish configuration for events */ +} NRF_TWIS_PUBLISH_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ==================================================== Struct TWIS_PSEL ===================================================== */ +/** + * @brief PSEL [TWIS_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} NRF_TWIS_PSEL_Type; /*!< Size = 8 (0x008) */ + +/* TWIS_PSEL_SCL: Pin select for SCL signal */ + #define TWIS_PSEL_SCL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SCL register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TWIS_PSEL_SCL_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TWIS_PSEL_SCL_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TWIS_PSEL_SCL_PORT_Msk (0x7UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TWIS_PSEL_SCL_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TWIS_PSEL_SCL_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TWIS_PSEL_SCL_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TWIS_PSEL_SCL_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TWIS_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TWIS_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* TWIS_PSEL_SDA: Pin select for SDA signal */ + #define TWIS_PSEL_SDA_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SDA register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TWIS_PSEL_SDA_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TWIS_PSEL_SDA_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TWIS_PSEL_SDA_PORT_Msk (0x7UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TWIS_PSEL_SDA_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TWIS_PSEL_SDA_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TWIS_PSEL_SDA_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TWIS_PSEL_SDA_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TWIS_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TWIS_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================ Struct TWIS_DMA_RX_MATCH ================================================= */ +/** + * @brief MATCH [TWIS_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Configure individual match events */ + __IOM uint32_t CANDIDATE[4]; /*!< (@ 0x00000004) The data to look for - any match will trigger the + MATCH[n] event, if enabled.*/ +} NRF_TWIS_DMA_RX_MATCH_Type; /*!< Size = 20 (0x014) */ + +/* TWIS_DMA_RX_MATCH_CONFIG: Configure individual match events */ + #define TWIS_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ENABLE0 @Bit 0 : Enable match filter 0 */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE1 @Bit 1 : Enable match filter 1 */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE2 @Bit 2 : Enable match filter 2 */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE3 @Bit 3 : Enable match filter 3 */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0 + field.*/ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1 + field.*/ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2 + field.*/ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3 + field.*/ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + + +/* TWIS_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array. */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array. */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array. */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register. */ + +/* DATA @Bits 0..31 : Data to look for */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << TWIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA + field.*/ + + + +/* =================================================== Struct TWIS_DMA_RX ==================================================== */ +/** + * @brief RX [TWIS_DMA_RX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ + __IOM NRF_TWIS_DMA_RX_MATCH_Type MATCH; /*!< (@ 0x00000024) Registers to control the behavior of the pattern + matcher engine*/ +} NRF_TWIS_DMA_RX_Type; /*!< Size = 56 (0x038) */ + +/* TWIS_DMA_RX_PTR: RAM buffer start address */ + #define TWIS_DMA_RX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define TWIS_DMA_RX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define TWIS_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* TWIS_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */ + #define TWIS_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define TWIS_DMA_RX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define TWIS_DMA_RX_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TWIS_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define TWIS_DMA_RX_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ + + +/* TWIS_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define TWIS_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define TWIS_DMA_RX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIS_DMA_RX_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TWIS_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIS_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIS_DMA_RX_LIST: EasyDMA list type */ + #define TWIS_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIS_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Msk (0x7UL << TWIS_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIS_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* TWIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* TWIS_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define TWIS_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* =================================================== Struct TWIS_DMA_TX ==================================================== */ +/** + * @brief TX [TWIS_DMA_TX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_TWIS_DMA_TX_Type; /*!< Size = 36 (0x024) */ + +/* TWIS_DMA_TX_PTR: RAM buffer start address */ + #define TWIS_DMA_TX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define TWIS_DMA_TX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define TWIS_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* TWIS_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */ + #define TWIS_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define TWIS_DMA_TX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define TWIS_DMA_TX_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TWIS_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define TWIS_DMA_TX_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ + + +/* TWIS_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define TWIS_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define TWIS_DMA_TX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIS_DMA_TX_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TWIS_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIS_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIS_DMA_TX_LIST: EasyDMA list type */ + #define TWIS_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIS_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Msk (0x7UL << TWIS_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIS_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* TWIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* TWIS_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define TWIS_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ===================================================== Struct TWIS_DMA ===================================================== */ +/** + * @brief DMA [TWIS_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_TWIS_DMA_RX_Type RX; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_TWIS_DMA_TX_Type TX; /*!< (@ 0x00000038) (unspecified) */ +} NRF_TWIS_DMA_Type; /*!< Size = 92 (0x05C) */ + +/* ======================================================= Struct TWIS ======================================================= */ +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA + */ + typedef struct { /*!< TWIS Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000000C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000010) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000020) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000024) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[2]; + __OM NRF_TWIS_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000030) Peripheral tasks. */ + __IM uint32_t RESERVED4[13]; + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED5; + __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000008C) Subscribe configuration for task SUSPEND */ + __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x00000090) Subscribe configuration for task RESUME */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000A0) Subscribe configuration for task PREPARERX */ + __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000A4) Subscribe configuration for task PREPARETX */ + __IM uint32_t RESERVED7[2]; + __IOM NRF_TWIS_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000B0) Subscribe configuration for tasks */ + __IM uint32_t RESERVED8[13]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED9[3]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000114) TWI error */ + __IM uint32_t RESERVED10[9]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x0000013C) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000140) Read command received */ + __IM uint32_t RESERVED11[2]; + __IOM NRF_TWIS_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x0000014C) Peripheral events. */ + __IM uint32_t RESERVED12[4]; + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED13[3]; + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000194) Publish configuration for event ERROR */ + __IM uint32_t RESERVED14[9]; + __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001BC) Publish configuration for event WRITE */ + __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001C0) Publish configuration for event READ */ + __IM uint32_t RESERVED15[2]; + __IOM NRF_TWIS_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001CC) Publish configuration for events */ + __IM uint32_t RESERVED16[3]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED17[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED18[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had a match */ + __IM uint32_t RESERVED19[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED20[33]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) TWI slave address n */ + __IM uint32_t RESERVED21; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match mechanism*/ + __IM uint32_t RESERVED22[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case of an + over-read of the transmit buffer.*/ + __IM uint32_t RESERVED23[15]; + __IOM NRF_TWIS_PSEL_Type PSEL; /*!< (@ 0x00000600) (unspecified) */ + __IM uint32_t RESERVED24[62]; + __IOM NRF_TWIS_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_TWIS_Type; /*!< Size = 1884 (0x75C) */ + +/* TWIS_TASKS_STOP: Stop TWI transaction */ + #define TWIS_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop TWI transaction */ + #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define TWIS_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define TWIS_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_TASKS_SUSPEND: Suspend TWI transaction */ + #define TWIS_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register. */ + +/* TASKS_SUSPEND @Bit 0 : Suspend TWI transaction */ + #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ + #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND + field.*/ + #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field. */ + #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field. */ + #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_TASKS_RESUME: Resume TWI transaction */ + #define TWIS_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register. */ + +/* TASKS_RESUME @Bit 0 : Resume TWI transaction */ + #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ + #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/ + #define TWIS_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field. */ + #define TWIS_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field. */ + #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_TASKS_PREPARERX: Prepare the TWI slave to respond to a write command */ + #define TWIS_TASKS_PREPARERX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PREPARERX register. */ + +/* TASKS_PREPARERX @Bit 0 : Prepare the TWI slave to respond to a write command */ + #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ + #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of + TASKS_PREPARERX field.*/ + #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Min (0x1UL) /*!< Min enumerator value of TASKS_PREPARERX field. */ + #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Max (0x1UL) /*!< Max enumerator value of TASKS_PREPARERX field. */ + #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_TASKS_PREPARETX: Prepare the TWI slave to respond to a read command */ + #define TWIS_TASKS_PREPARETX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PREPARETX register. */ + +/* TASKS_PREPARETX @Bit 0 : Prepare the TWI slave to respond to a read command */ + #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ + #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of + TASKS_PREPARETX field.*/ + #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Min (0x1UL) /*!< Min enumerator value of TASKS_PREPARETX field. */ + #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Max (0x1UL) /*!< Max enumerator value of TASKS_PREPARETX field. */ + #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define TWIS_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */ + #define TWIS_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */ + #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */ + #define TWIS_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */ + #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_SUBSCRIBE_RESUME_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_SUBSCRIBE_RESUME_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_RESUME_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_SUBSCRIBE_PREPARERX: Subscribe configuration for task PREPARERX */ + #define TWIS_SUBSCRIBE_PREPARERX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PREPARERX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task PREPARERX will subscribe to */ + #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_SUBSCRIBE_PREPARETX: Subscribe configuration for task PREPARETX */ + #define TWIS_SUBSCRIBE_PREPARETX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PREPARETX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task PREPARETX will subscribe to */ + #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_EVENTS_STOPPED: TWI stopped */ + #define TWIS_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : TWI stopped */ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_ERROR: TWI error */ + #define TWIS_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : TWI error */ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.*/ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_WRITE: Write command received */ + #define TWIS_EVENTS_WRITE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_WRITE register. */ + +/* EVENTS_WRITE @Bit 0 : Write command received */ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field.*/ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Min (0x0UL) /*!< Min enumerator value of EVENTS_WRITE field. */ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Max (0x1UL) /*!< Max enumerator value of EVENTS_WRITE field. */ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_READ: Read command received */ + #define TWIS_EVENTS_READ_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READ register. */ + +/* EVENTS_READ @Bit 0 : Read command received */ + #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ + #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ + #define TWIS_EVENTS_READ_EVENTS_READ_Min (0x0UL) /*!< Min enumerator value of EVENTS_READ field. */ + #define TWIS_EVENTS_READ_EVENTS_READ_Max (0x1UL) /*!< Max enumerator value of EVENTS_READ field. */ + #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_READ_EVENTS_READ_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define TWIS_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define TWIS_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_WRITE: Publish configuration for event WRITE */ + #define TWIS_PUBLISH_WRITE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_WRITE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event WRITE will publish to */ + #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_WRITE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_WRITE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_WRITE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_WRITE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_WRITE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_WRITE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_READ: Publish configuration for event READ */ + #define TWIS_PUBLISH_READ_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READ register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READ will publish to */ + #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_READ_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_READ_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_READ_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_READ_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_READ_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_READ_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_SHORTS: Shortcuts between local events and tasks */ + #define TWIS_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* WRITE_SUSPEND @Bit 13 : Shortcut between event WRITE and task SUSPEND */ + #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ + #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ + #define TWIS_SHORTS_WRITE_SUSPEND_Min (0x0UL) /*!< Min enumerator value of WRITE_SUSPEND field. */ + #define TWIS_SHORTS_WRITE_SUSPEND_Max (0x1UL) /*!< Max enumerator value of WRITE_SUSPEND field. */ + #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ + +/* READ_SUSPEND @Bit 14 : Shortcut between event READ and task SUSPEND */ + #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ + #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ + #define TWIS_SHORTS_READ_SUSPEND_Min (0x0UL) /*!< Min enumerator value of READ_SUSPEND field. */ + #define TWIS_SHORTS_READ_SUSPEND_Max (0x1UL) /*!< Max enumerator value of READ_SUSPEND field. */ + #define TWIS_SHORTS_READ_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_READ_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows + daisy-chaining match events. */ + + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows + daisy-chaining match events. */ + + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows + daisy-chaining match events. */ + + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows + daisy-chaining match events. */ + + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* TWIS_INTEN: Enable or disable interrupt */ + #define TWIS_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */ + #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIS_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIS_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIS_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* ERROR @Bit 5 : Enable or disable interrupt for event ERROR */ + #define TWIS_INTEN_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIS_INTEN_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIS_INTEN_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIS_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ + +/* WRITE @Bit 15 : Enable or disable interrupt for event WRITE */ + #define TWIS_INTEN_WRITE_Pos (15UL) /*!< Position of WRITE field. */ + #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define TWIS_INTEN_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define TWIS_INTEN_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define TWIS_INTEN_WRITE_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_WRITE_Enabled (0x1UL) /*!< Enable */ + +/* READ @Bit 16 : Enable or disable interrupt for event READ */ + #define TWIS_INTEN_READ_Pos (16UL) /*!< Position of READ field. */ + #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ + #define TWIS_INTEN_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define TWIS_INTEN_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define TWIS_INTEN_READ_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_READ_Enabled (0x1UL) /*!< Enable */ + +/* DMARXEND @Bit 19 : Enable or disable interrupt for event DMARXEND */ + #define TWIS_INTEN_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIS_INTEN_DMARXEND_Msk (0x1UL << TWIS_INTEN_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIS_INTEN_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIS_INTEN_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIS_INTEN_DMARXEND_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMARXREADY @Bit 20 : Enable or disable interrupt for event DMARXREADY */ + #define TWIS_INTEN_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIS_INTEN_DMARXREADY_Msk (0x1UL << TWIS_INTEN_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIS_INTEN_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIS_INTEN_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIS_INTEN_DMARXREADY_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMARXBUSERROR @Bit 21 : Enable or disable interrupt for event DMARXBUSERROR */ + #define TWIS_INTEN_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIS_INTEN_DMARXBUSERROR_Msk (0x1UL << TWIS_INTEN_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIS_INTEN_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTEN_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTEN_DMARXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXBUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH0 @Bit 22 : Enable or disable interrupt for event DMARXMATCH[0] */ + #define TWIS_INTEN_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIS_INTEN_DMARXMATCH0_Msk (0x1UL << TWIS_INTEN_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIS_INTEN_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTEN_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTEN_DMARXMATCH0_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXMATCH0_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH1 @Bit 23 : Enable or disable interrupt for event DMARXMATCH[1] */ + #define TWIS_INTEN_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIS_INTEN_DMARXMATCH1_Msk (0x1UL << TWIS_INTEN_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIS_INTEN_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTEN_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTEN_DMARXMATCH1_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXMATCH1_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH2 @Bit 24 : Enable or disable interrupt for event DMARXMATCH[2] */ + #define TWIS_INTEN_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIS_INTEN_DMARXMATCH2_Msk (0x1UL << TWIS_INTEN_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIS_INTEN_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTEN_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTEN_DMARXMATCH2_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXMATCH2_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH3 @Bit 25 : Enable or disable interrupt for event DMARXMATCH[3] */ + #define TWIS_INTEN_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIS_INTEN_DMARXMATCH3_Msk (0x1UL << TWIS_INTEN_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIS_INTEN_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTEN_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTEN_DMARXMATCH3_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXMATCH3_Enabled (0x1UL) /*!< Enable */ + +/* DMATXEND @Bit 26 : Enable or disable interrupt for event DMATXEND */ + #define TWIS_INTEN_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIS_INTEN_DMATXEND_Msk (0x1UL << TWIS_INTEN_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIS_INTEN_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIS_INTEN_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIS_INTEN_DMATXEND_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMATXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMATXREADY @Bit 27 : Enable or disable interrupt for event DMATXREADY */ + #define TWIS_INTEN_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIS_INTEN_DMATXREADY_Msk (0x1UL << TWIS_INTEN_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIS_INTEN_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIS_INTEN_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIS_INTEN_DMATXREADY_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMATXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMATXBUSERROR @Bit 28 : Enable or disable interrupt for event DMATXBUSERROR */ + #define TWIS_INTEN_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIS_INTEN_DMATXBUSERROR_Msk (0x1UL << TWIS_INTEN_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIS_INTEN_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTEN_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTEN_DMATXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMATXBUSERROR_Enabled (0x1UL) /*!< Enable */ + + +/* TWIS_INTENSET: Enable interrupt */ + #define TWIS_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIS_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIS_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIS_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to enable interrupt for event ERROR */ + #define TWIS_INTENSET_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIS_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIS_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIS_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* WRITE @Bit 15 : Write '1' to enable interrupt for event WRITE */ + #define TWIS_INTENSET_WRITE_Pos (15UL) /*!< Position of WRITE field. */ + #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define TWIS_INTENSET_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define TWIS_INTENSET_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define TWIS_INTENSET_WRITE_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_WRITE_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_WRITE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READ @Bit 16 : Write '1' to enable interrupt for event READ */ + #define TWIS_INTENSET_READ_Pos (16UL) /*!< Position of READ field. */ + #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ + #define TWIS_INTENSET_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define TWIS_INTENSET_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define TWIS_INTENSET_READ_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_READ_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_READ_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */ + #define TWIS_INTENSET_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIS_INTENSET_DMARXEND_Msk (0x1UL << TWIS_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIS_INTENSET_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIS_INTENSET_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIS_INTENSET_DMARXEND_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */ + #define TWIS_INTENSET_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIS_INTENSET_DMARXREADY_Msk (0x1UL << TWIS_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIS_INTENSET_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIS_INTENSET_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIS_INTENSET_DMARXREADY_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */ + #define TWIS_INTENSET_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIS_INTENSET_DMARXBUSERROR_Msk (0x1UL << TWIS_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIS_INTENSET_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTENSET_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTENSET_DMARXBUSERROR_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */ + #define TWIS_INTENSET_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIS_INTENSET_DMARXMATCH0_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIS_INTENSET_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTENSET_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTENSET_DMARXMATCH0_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */ + #define TWIS_INTENSET_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIS_INTENSET_DMARXMATCH1_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIS_INTENSET_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTENSET_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTENSET_DMARXMATCH1_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */ + #define TWIS_INTENSET_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIS_INTENSET_DMARXMATCH2_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIS_INTENSET_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTENSET_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTENSET_DMARXMATCH2_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */ + #define TWIS_INTENSET_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIS_INTENSET_DMARXMATCH3_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIS_INTENSET_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTENSET_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTENSET_DMARXMATCH3_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */ + #define TWIS_INTENSET_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIS_INTENSET_DMATXEND_Msk (0x1UL << TWIS_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIS_INTENSET_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIS_INTENSET_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIS_INTENSET_DMATXEND_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */ + #define TWIS_INTENSET_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIS_INTENSET_DMATXREADY_Msk (0x1UL << TWIS_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIS_INTENSET_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIS_INTENSET_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIS_INTENSET_DMATXREADY_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */ + #define TWIS_INTENSET_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIS_INTENSET_DMATXBUSERROR_Msk (0x1UL << TWIS_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIS_INTENSET_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTENSET_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTENSET_DMATXBUSERROR_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TWIS_INTENCLR: Disable interrupt */ + #define TWIS_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIS_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIS_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIS_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to disable interrupt for event ERROR */ + #define TWIS_INTENCLR_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIS_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIS_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIS_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* WRITE @Bit 15 : Write '1' to disable interrupt for event WRITE */ + #define TWIS_INTENCLR_WRITE_Pos (15UL) /*!< Position of WRITE field. */ + #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define TWIS_INTENCLR_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define TWIS_INTENCLR_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define TWIS_INTENCLR_WRITE_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_WRITE_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_WRITE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READ @Bit 16 : Write '1' to disable interrupt for event READ */ + #define TWIS_INTENCLR_READ_Pos (16UL) /*!< Position of READ field. */ + #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ + #define TWIS_INTENCLR_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define TWIS_INTENCLR_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define TWIS_INTENCLR_READ_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_READ_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_READ_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */ + #define TWIS_INTENCLR_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIS_INTENCLR_DMARXEND_Msk (0x1UL << TWIS_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIS_INTENCLR_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIS_INTENCLR_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIS_INTENCLR_DMARXEND_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */ + #define TWIS_INTENCLR_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIS_INTENCLR_DMARXREADY_Msk (0x1UL << TWIS_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIS_INTENCLR_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIS_INTENCLR_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIS_INTENCLR_DMARXREADY_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */ + #define TWIS_INTENCLR_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIS_INTENCLR_DMARXBUSERROR_Msk (0x1UL << TWIS_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIS_INTENCLR_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTENCLR_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTENCLR_DMARXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */ + #define TWIS_INTENCLR_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIS_INTENCLR_DMARXMATCH0_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIS_INTENCLR_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTENCLR_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTENCLR_DMARXMATCH0_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */ + #define TWIS_INTENCLR_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIS_INTENCLR_DMARXMATCH1_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIS_INTENCLR_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTENCLR_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTENCLR_DMARXMATCH1_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */ + #define TWIS_INTENCLR_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIS_INTENCLR_DMARXMATCH2_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIS_INTENCLR_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTENCLR_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTENCLR_DMARXMATCH2_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */ + #define TWIS_INTENCLR_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIS_INTENCLR_DMARXMATCH3_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIS_INTENCLR_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTENCLR_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTENCLR_DMARXMATCH3_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */ + #define TWIS_INTENCLR_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIS_INTENCLR_DMATXEND_Msk (0x1UL << TWIS_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIS_INTENCLR_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIS_INTENCLR_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIS_INTENCLR_DMATXEND_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */ + #define TWIS_INTENCLR_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIS_INTENCLR_DMATXREADY_Msk (0x1UL << TWIS_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIS_INTENCLR_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIS_INTENCLR_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIS_INTENCLR_DMATXREADY_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */ + #define TWIS_INTENCLR_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIS_INTENCLR_DMATXBUSERROR_Msk (0x1UL << TWIS_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIS_INTENCLR_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTENCLR_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTENCLR_DMATXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TWIS_ERRORSRC: Error source */ + #define TWIS_ERRORSRC_ResetValue (0x00000000UL) /*!< Reset value of ERRORSRC register. */ + +/* OVERFLOW @Bit 0 : RX buffer overflow detected, and prevented */ + #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ + #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ + #define TWIS_ERRORSRC_OVERFLOW_Min (0x0UL) /*!< Min enumerator value of OVERFLOW field. */ + #define TWIS_ERRORSRC_OVERFLOW_Max (0x1UL) /*!< Max enumerator value of OVERFLOW field. */ + #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0x0UL) /*!< Error did not occur */ + #define TWIS_ERRORSRC_OVERFLOW_Detected (0x1UL) /*!< Error occurred */ + +/* DNACK @Bit 2 : NACK sent after receiving a data byte */ + #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ + #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ + #define TWIS_ERRORSRC_DNACK_Min (0x0UL) /*!< Min enumerator value of DNACK field. */ + #define TWIS_ERRORSRC_DNACK_Max (0x1UL) /*!< Max enumerator value of DNACK field. */ + #define TWIS_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */ + #define TWIS_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */ + +/* OVERREAD @Bit 3 : TX buffer over-read detected, and prevented */ + #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ + #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ + #define TWIS_ERRORSRC_OVERREAD_Min (0x0UL) /*!< Min enumerator value of OVERREAD field. */ + #define TWIS_ERRORSRC_OVERREAD_Max (0x1UL) /*!< Max enumerator value of OVERREAD field. */ + #define TWIS_ERRORSRC_OVERREAD_NotDetected (0x0UL) /*!< Error did not occur */ + #define TWIS_ERRORSRC_OVERREAD_Detected (0x1UL) /*!< Error occurred */ + + +/* TWIS_MATCH: Status register indicating which address had a match */ + #define TWIS_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH register. */ + +/* MATCH @Bit 0 : Indication of which address in ADDRESS that matched the incoming address */ + #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define TWIS_MATCH_MATCH_Min (0x0UL) /*!< Min value of MATCH field. */ + #define TWIS_MATCH_MATCH_Max (0x1UL) /*!< Max size of MATCH field. */ + + +/* TWIS_ENABLE: Enable TWIS */ + #define TWIS_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..3 : Enable or disable TWIS */ + #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define TWIS_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIS_ENABLE_ENABLE_Max (0x9UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIS */ + #define TWIS_ENABLE_ENABLE_Enabled (0x9UL) /*!< Enable TWIS */ + + +/* TWIS_ADDRESS: TWI slave address n */ + #define TWIS_ADDRESS_MaxCount (2UL) /*!< Max size of ADDRESS[2] array. */ + #define TWIS_ADDRESS_MaxIndex (1UL) /*!< Max index of ADDRESS[2] array. */ + #define TWIS_ADDRESS_MinIndex (0UL) /*!< Min index of ADDRESS[2] array. */ + #define TWIS_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS[2] register. */ + +/* ADDRESS @Bits 0..6 : TWI slave address */ + #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* TWIS_CONFIG: Configuration register for the address match mechanism */ + #define TWIS_CONFIG_ResetValue (0x00000001UL) /*!< Reset value of CONFIG register. */ + +/* ADDRESS0 @Bit 0 : Enable or disable address matching on ADDRESS[0] */ + #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ + #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ + #define TWIS_CONFIG_ADDRESS0_Min (0x0UL) /*!< Min enumerator value of ADDRESS0 field. */ + #define TWIS_CONFIG_ADDRESS0_Max (0x1UL) /*!< Max enumerator value of ADDRESS0 field. */ + #define TWIS_CONFIG_ADDRESS0_Disabled (0x0UL) /*!< Disabled */ + #define TWIS_CONFIG_ADDRESS0_Enabled (0x1UL) /*!< Enabled */ + +/* ADDRESS1 @Bit 1 : Enable or disable address matching on ADDRESS[1] */ + #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ + #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ + #define TWIS_CONFIG_ADDRESS1_Min (0x0UL) /*!< Min enumerator value of ADDRESS1 field. */ + #define TWIS_CONFIG_ADDRESS1_Max (0x1UL) /*!< Max enumerator value of ADDRESS1 field. */ + #define TWIS_CONFIG_ADDRESS1_Disabled (0x0UL) /*!< Disabled */ + #define TWIS_CONFIG_ADDRESS1_Enabled (0x1UL) /*!< Enabled */ + + +/* TWIS_ORC: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + #define TWIS_ORC_ResetValue (0x00000000UL) /*!< Reset value of ORC register. */ + +/* ORC @Bits 0..7 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ + #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ UARTE ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct UARTE_TASKS_DMA_RX ================================================ */ +/** + * @brief RX [UARTE_TASKS_DMA_RX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See + peripheral description for operation using easyDMA.*/ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ + __OM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000008) Enables the MATCH[n] event by setting the ENABLE[n] bit + in the CONFIG register.*/ + __OM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000018) Disables the MATCH[n] event by clearing the ENABLE[n] + bit in the CONFIG register.*/ +} NRF_UARTE_TASKS_DMA_RX_Type; /*!< Size = 40 (0x028) */ + +/* UARTE_TASKS_DMA_RX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using + easyDMA. */ + + #define UARTE_TASKS_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */ + #define UARTE_TASKS_DMA_RX_START_START_Pos (0UL) /*!< Position of START field. */ + #define UARTE_TASKS_DMA_RX_START_START_Msk (0x1UL << UARTE_TASKS_DMA_RX_START_START_Pos) /*!< Bit mask of START field. */ + #define UARTE_TASKS_DMA_RX_START_START_Min (0x1UL) /*!< Min enumerator value of START field. */ + #define UARTE_TASKS_DMA_RX_START_START_Max (0x1UL) /*!< Max enumerator value of START field. */ + #define UARTE_TASKS_DMA_RX_START_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* UARTE_TASKS_DMA_RX_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define UARTE_TASKS_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define UARTE_TASKS_DMA_RX_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define UARTE_TASKS_DMA_RX_STOP_STOP_Msk (0x1UL << UARTE_TASKS_DMA_RX_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define UARTE_TASKS_DMA_RX_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define UARTE_TASKS_DMA_RX_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define UARTE_TASKS_DMA_RX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* UARTE_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask + of ENABLEMATCH field.*/ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + +/* UARTE_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit + mask of DISABLEMATCH field.*/ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================ Struct UARTE_TASKS_DMA_TX ================================================ */ +/** + * @brief TX [UARTE_TASKS_DMA_TX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See + peripheral description for operation using easyDMA.*/ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ +} NRF_UARTE_TASKS_DMA_TX_Type; /*!< Size = 8 (0x008) */ + +/* UARTE_TASKS_DMA_TX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using + easyDMA. */ + + #define UARTE_TASKS_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */ + #define UARTE_TASKS_DMA_TX_START_START_Pos (0UL) /*!< Position of START field. */ + #define UARTE_TASKS_DMA_TX_START_START_Msk (0x1UL << UARTE_TASKS_DMA_TX_START_START_Pos) /*!< Bit mask of START field. */ + #define UARTE_TASKS_DMA_TX_START_START_Min (0x1UL) /*!< Min enumerator value of START field. */ + #define UARTE_TASKS_DMA_TX_START_START_Max (0x1UL) /*!< Max enumerator value of START field. */ + #define UARTE_TASKS_DMA_TX_START_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* UARTE_TASKS_DMA_TX_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define UARTE_TASKS_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define UARTE_TASKS_DMA_TX_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define UARTE_TASKS_DMA_TX_STOP_STOP_Msk (0x1UL << UARTE_TASKS_DMA_TX_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define UARTE_TASKS_DMA_TX_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define UARTE_TASKS_DMA_TX_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define UARTE_TASKS_DMA_TX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================= Struct UARTE_TASKS_DMA ================================================== */ +/** + * @brief TASKS_DMA [UARTE_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __OM NRF_UARTE_TASKS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral tasks. */ + __OM NRF_UARTE_TASKS_DMA_TX_Type TX; /*!< (@ 0x00000028) Peripheral tasks. */ +} NRF_UARTE_TASKS_DMA_Type; /*!< Size = 48 (0x030) */ + + +/* ============================================== Struct UARTE_SUBSCRIBE_DMA_RX ============================================== */ +/** + * @brief RX [UARTE_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ + __IOM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000008) Subscribe configuration for task ENABLEMATCH[n] */ + __IOM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000018) Subscribe configuration for task DISABLEMATCH[n] */ +} NRF_UARTE_SUBSCRIBE_DMA_RX_Type; /*!< Size = 40 (0x028) */ + +/* UARTE_SUBSCRIBE_DMA_RX_START: Subscribe configuration for task START */ + #define UARTE_SUBSCRIBE_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_START_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* UARTE_SUBSCRIBE_DMA_RX_STOP: Subscribe configuration for task STOP */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask + of CHIDX field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ============================================== Struct UARTE_SUBSCRIBE_DMA_TX ============================================== */ +/** + * @brief TX [UARTE_SUBSCRIBE_DMA_TX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ +} NRF_UARTE_SUBSCRIBE_DMA_TX_Type; /*!< Size = 8 (0x008) */ + +/* UARTE_SUBSCRIBE_DMA_TX_START: Subscribe configuration for task START */ + #define UARTE_SUBSCRIBE_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_TX_START_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* UARTE_SUBSCRIBE_DMA_TX_STOP: Subscribe configuration for task STOP */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* =============================================== Struct UARTE_SUBSCRIBE_DMA ================================================ */ +/** + * @brief SUBSCRIBE_DMA [UARTE_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IOM NRF_UARTE_SUBSCRIBE_DMA_RX_Type RX; /*!< (@ 0x00000000) Subscribe configuration for tasks */ + __IOM NRF_UARTE_SUBSCRIBE_DMA_TX_Type TX; /*!< (@ 0x00000028) Subscribe configuration for tasks */ +} NRF_UARTE_SUBSCRIBE_DMA_Type; /*!< Size = 48 (0x030) */ + + +/* =============================================== Struct UARTE_EVENTS_DMA_RX ================================================ */ +/** + * @brief RX [UARTE_EVENTS_DMA_RX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ +} NRF_UARTE_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* UARTE_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ + #define UARTE_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define UARTE_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ + #define UARTE_EVENTS_DMA_RX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ + #define UARTE_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define UARTE_EVENTS_DMA_RX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define UARTE_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define UARTE_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define UARTE_EVENTS_DMA_RX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define UARTE_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << UARTE_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define UARTE_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define UARTE_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define UARTE_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of + BUSERROR field.*/ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define UARTE_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << UARTE_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated */ + + + +/* =============================================== Struct UARTE_EVENTS_DMA_TX ================================================ */ +/** + * @brief TX [UARTE_EVENTS_DMA_TX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_UARTE_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* UARTE_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ + #define UARTE_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define UARTE_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ + #define UARTE_EVENTS_DMA_TX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ + #define UARTE_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define UARTE_EVENTS_DMA_TX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define UARTE_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define UARTE_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define UARTE_EVENTS_DMA_TX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define UARTE_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << UARTE_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define UARTE_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define UARTE_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define UARTE_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of + BUSERROR field.*/ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct UARTE_EVENTS_DMA ================================================= */ +/** + * @brief EVENTS_DMA [UARTE_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_UARTE_EVENTS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral events. */ + __IOM NRF_UARTE_EVENTS_DMA_TX_Type TX; /*!< (@ 0x0000001C) Peripheral events. */ +} NRF_UARTE_EVENTS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* =============================================== Struct UARTE_PUBLISH_DMA_RX =============================================== */ +/** + * @brief RX [UARTE_PUBLISH_DMA_RX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Publish configuration for event MATCH[n] */ +} NRF_UARTE_PUBLISH_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* UARTE_PUBLISH_DMA_RX_END: Publish configuration for event END */ + #define UARTE_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_DMA_RX_READY: Publish configuration for event READY */ + #define UARTE_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */ + #define UARTE_PUBLISH_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */ + #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* =============================================== Struct UARTE_PUBLISH_DMA_TX =============================================== */ +/** + * @brief TX [UARTE_PUBLISH_DMA_TX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_UARTE_PUBLISH_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* UARTE_PUBLISH_DMA_TX_END: Publish configuration for event END */ + #define UARTE_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_DMA_TX_READY: Publish configuration for event READY */ + #define UARTE_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================ Struct UARTE_PUBLISH_DMA ================================================= */ +/** + * @brief PUBLISH_DMA [UARTE_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_UARTE_PUBLISH_DMA_RX_Type RX; /*!< (@ 0x00000000) Publish configuration for events */ + __IOM NRF_UARTE_PUBLISH_DMA_TX_Type TX; /*!< (@ 0x0000001C) Publish configuration for events */ +} NRF_UARTE_PUBLISH_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ==================================================== Struct UARTE_PSEL ==================================================== */ +/** + * @brief PSEL [UARTE_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t TXD; /*!< (@ 0x00000000) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000004) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x00000008) Pin select for RXD signal */ + __IOM uint32_t RTS; /*!< (@ 0x0000000C) Pin select for RTS signal */ +} NRF_UARTE_PSEL_Type; /*!< Size = 16 (0x010) */ + +/* UARTE_PSEL_TXD: Pin select for TXD signal */ + #define UARTE_PSEL_TXD_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TXD register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + #define UARTE_PSEL_TXD_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define UARTE_PSEL_TXD_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define UARTE_PSEL_TXD_PORT_Msk (0x7UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ + #define UARTE_PSEL_TXD_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define UARTE_PSEL_TXD_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define UARTE_PSEL_TXD_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define UARTE_PSEL_TXD_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define UARTE_PSEL_TXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define UARTE_PSEL_TXD_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* UARTE_PSEL_CTS: Pin select for CTS signal */ + #define UARTE_PSEL_CTS_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CTS register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + #define UARTE_PSEL_CTS_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define UARTE_PSEL_CTS_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define UARTE_PSEL_CTS_PORT_Msk (0x7UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ + #define UARTE_PSEL_CTS_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define UARTE_PSEL_CTS_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define UARTE_PSEL_CTS_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define UARTE_PSEL_CTS_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define UARTE_PSEL_CTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define UARTE_PSEL_CTS_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* UARTE_PSEL_RXD: Pin select for RXD signal */ + #define UARTE_PSEL_RXD_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RXD register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + #define UARTE_PSEL_RXD_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define UARTE_PSEL_RXD_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define UARTE_PSEL_RXD_PORT_Msk (0x7UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ + #define UARTE_PSEL_RXD_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define UARTE_PSEL_RXD_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define UARTE_PSEL_RXD_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define UARTE_PSEL_RXD_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define UARTE_PSEL_RXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define UARTE_PSEL_RXD_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* UARTE_PSEL_RTS: Pin select for RTS signal */ + #define UARTE_PSEL_RTS_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RTS register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + #define UARTE_PSEL_RTS_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define UARTE_PSEL_RTS_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..7 : Port number */ + #define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define UARTE_PSEL_RTS_PORT_Msk (0x7UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ + #define UARTE_PSEL_RTS_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define UARTE_PSEL_RTS_PORT_Max (0x7UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define UARTE_PSEL_RTS_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define UARTE_PSEL_RTS_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define UARTE_PSEL_RTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define UARTE_PSEL_RTS_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================ Struct UARTE_DMA_RX_MATCH ================================================ */ +/** + * @brief MATCH [UARTE_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Configure individual match events */ + __IOM uint32_t CANDIDATE[4]; /*!< (@ 0x00000004) The data to look for - any match will trigger the + MATCH[n] event, if enabled.*/ +} NRF_UARTE_DMA_RX_MATCH_Type; /*!< Size = 20 (0x014) */ + +/* UARTE_DMA_RX_MATCH_CONFIG: Configure individual match events */ + #define UARTE_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ENABLE0 @Bit 0 : Enable match filter 0 */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE1 @Bit 1 : Enable match filter 1 */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE2 @Bit 2 : Enable match filter 2 */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE3 @Bit 3 : Enable match filter 3 */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or continous */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or continous */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or continous */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or continous */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + + +/* UARTE_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array. */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array. */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array. */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register. */ + +/* DATA @Bits 0..7 : Data to look for */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFUL << UARTE_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA field. */ + + + +/* =================================================== Struct UARTE_DMA_RX =================================================== */ +/** + * @brief RX [UARTE_DMA_RX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ + __IOM NRF_UARTE_DMA_RX_MATCH_Type MATCH; /*!< (@ 0x00000024) Registers to control the behavior of the pattern + matcher engine*/ +} NRF_UARTE_DMA_RX_Type; /*!< Size = 56 (0x038) */ + +/* UARTE_DMA_RX_PTR: RAM buffer start address */ + #define UARTE_DMA_RX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define UARTE_DMA_RX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define UARTE_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* UARTE_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */ + #define UARTE_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define UARTE_DMA_RX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define UARTE_DMA_RX_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define UARTE_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define UARTE_DMA_RX_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ + + +/* UARTE_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after + each MATCH event. */ + + #define UARTE_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define UARTE_DMA_RX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define UARTE_DMA_RX_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define UARTE_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define UARTE_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ + + +/* UARTE_DMA_RX_LIST: EasyDMA list type */ + #define UARTE_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define UARTE_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Msk (0x7UL << UARTE_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define UARTE_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* UARTE_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* UARTE_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define UARTE_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* =================================================== Struct UARTE_DMA_TX =================================================== */ +/** + * @brief TX [UARTE_DMA_TX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED2; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_UARTE_DMA_TX_Type; /*!< Size = 36 (0x024) */ + +/* UARTE_DMA_TX_PTR: RAM buffer start address */ + #define UARTE_DMA_TX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define UARTE_DMA_TX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define UARTE_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* UARTE_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */ + #define UARTE_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */ + #define UARTE_DMA_TX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define UARTE_DMA_TX_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define UARTE_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define UARTE_DMA_TX_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ + + +/* UARTE_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after + each MATCH event. */ + + #define UARTE_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define UARTE_DMA_TX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define UARTE_DMA_TX_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define UARTE_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define UARTE_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL) /*!< Max size of AMOUNT field. */ + + +/* UARTE_DMA_TX_LIST: EasyDMA list type */ + #define UARTE_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define UARTE_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Msk (0x7UL << UARTE_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define UARTE_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* UARTE_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* UARTE_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define UARTE_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ==================================================== Struct UARTE_DMA ===================================================== */ +/** + * @brief DMA [UARTE_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_UARTE_DMA_RX_Type RX; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_UARTE_DMA_TX_Type TX; /*!< (@ 0x00000038) (unspecified) */ +} NRF_UARTE_DMA_Type; /*!< Size = 92 (0x05C) */ + +/* ====================================================== Struct UARTE ======================================================= */ +/** + * @brief UART with EasyDMA + */ + typedef struct { /*!< UARTE Structure */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000001C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[2]; + __OM NRF_UARTE_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000028) Peripheral tasks. */ + __IM uint32_t RESERVED2[17]; + __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x0000009C) Subscribe configuration for task FLUSHRX */ + __IM uint32_t RESERVED3[2]; + __IOM NRF_UARTE_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks */ + __IM uint32_t RESERVED4[10]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000010C) Data sent from TXD */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000110) Data received in RXD (but potentially not yet + transferred to Data RAM)*/ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000114) Error detected */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000124) Receiver timeout */ + __IM uint32_t RESERVED7[2]; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000130) Transmitter stopped */ + __IM uint32_t RESERVED8[6]; + __IOM NRF_UARTE_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x0000014C) Peripheral events. */ + __IOM uint32_t EVENTS_FRAMETIMEOUT; /*!< (@ 0x00000174) Timed out due to bus being idle while receiving data. */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ + __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ + __IM uint32_t RESERVED10; + __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000018C) Publish configuration for event TXDRDY */ + __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000190) Publish configuration for event RXDRDY */ + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000194) Publish configuration for event ERROR */ + __IM uint32_t RESERVED11[3]; + __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001A4) Publish configuration for event RXTO */ + __IM uint32_t RESERVED12[2]; + __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001B0) Publish configuration for event TXSTOPPED */ + __IM uint32_t RESERVED13[6]; + __IOM NRF_UARTE_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001CC) Publish configuration for events */ + __IOM uint32_t PUBLISH_FRAMETIMEOUT; /*!< (@ 0x000001F4) Publish configuration for event FRAMETIMEOUT */ + __IM uint32_t RESERVED14[2]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED15[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED16[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED17[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED18[8]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected.*/ + __IM uint32_t RESERVED19[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity, hardware flow control, + framesize, and packet timeout.*/ + __IM uint32_t RESERVED20; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000574) Set the address of the UARTE for RX when used in 9 bit + data frame mode.*/ + __IOM uint32_t FRAMETIMEOUT; /*!< (@ 0x00000578) Set the number of UARTE bits to count before triggering + packet timeout.*/ + __IM uint32_t RESERVED21[34]; + __IOM NRF_UARTE_PSEL_Type PSEL; /*!< (@ 0x00000604) (unspecified) */ + __IM uint32_t RESERVED22[59]; + __IOM NRF_UARTE_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_UARTE_Type; /*!< Size = 1884 (0x75C) */ + +/* UARTE_TASKS_FLUSHRX: Flush RX FIFO into RX buffer */ + #define UARTE_TASKS_FLUSHRX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FLUSHRX register. */ + +/* TASKS_FLUSHRX @Bit 0 : Flush RX FIFO into RX buffer */ + #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ + #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX + field.*/ + #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Min (0x1UL) /*!< Min enumerator value of TASKS_FLUSHRX field. */ + #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Max (0x1UL) /*!< Max enumerator value of TASKS_FLUSHRX field. */ + #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (0x1UL) /*!< Trigger task */ + + +/* UARTE_SUBSCRIBE_FLUSHRX: Subscribe configuration for task FLUSHRX */ + #define UARTE_SUBSCRIBE_FLUSHRX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_FLUSHRX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task FLUSHRX will subscribe to */ + #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* UARTE_EVENTS_CTS: CTS is activated (set low). Clear To Send. */ + #define UARTE_EVENTS_CTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CTS register. */ + +/* EVENTS_CTS @Bit 0 : CTS is activated (set low). Clear To Send. */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_Min (0x0UL) /*!< Min enumerator value of EVENTS_CTS field. */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_Max (0x1UL) /*!< Max enumerator value of EVENTS_CTS field. */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_NCTS: CTS is deactivated (set high). Not Clear To Send. */ + #define UARTE_EVENTS_NCTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_NCTS register. */ + +/* EVENTS_NCTS @Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Min (0x0UL) /*!< Min enumerator value of EVENTS_NCTS field. */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Max (0x1UL) /*!< Max enumerator value of EVENTS_NCTS field. */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_TXDRDY: Data sent from TXD */ + #define UARTE_EVENTS_TXDRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXDRDY register. */ + +/* EVENTS_TXDRDY @Bit 0 : Data sent from TXD */ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY + field.*/ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXDRDY field. */ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXDRDY field. */ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_RXDRDY: Data received in RXD (but potentially not yet transferred to Data RAM) */ + #define UARTE_EVENTS_RXDRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXDRDY register. */ + +/* EVENTS_RXDRDY @Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY + field.*/ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXDRDY field. */ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXDRDY field. */ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_ERROR: Error detected */ + #define UARTE_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : Error detected */ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR + field.*/ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_RXTO: Receiver timeout */ + #define UARTE_EVENTS_RXTO_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXTO register. */ + +/* EVENTS_RXTO @Bit 0 : Receiver timeout */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXTO field. */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXTO field. */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_TXSTOPPED: Transmitter stopped */ + #define UARTE_EVENTS_TXSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXSTOPPED register. */ + +/* EVENTS_TXSTOPPED @Bit 0 : Transmitter stopped */ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of + EVENTS_TXSTOPPED field.*/ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXSTOPPED field. */ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXSTOPPED field. */ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_FRAMETIMEOUT: Timed out due to bus being idle while receiving data. */ + #define UARTE_EVENTS_FRAMETIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FRAMETIMEOUT register. */ + +/* EVENTS_FRAMETIMEOUT @Bit 0 : Timed out due to bus being idle while receiving data. */ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Pos (0UL) /*!< Position of EVENTS_FRAMETIMEOUT field. */ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Msk (0x1UL << UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Pos) /*!< + Bit mask of EVENTS_FRAMETIMEOUT field.*/ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Min (0x0UL) /*!< Min enumerator value of EVENTS_FRAMETIMEOUT field. */ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Max (0x1UL) /*!< Max enumerator value of EVENTS_FRAMETIMEOUT field. */ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_PUBLISH_CTS: Publish configuration for event CTS */ + #define UARTE_PUBLISH_CTS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CTS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CTS will publish to */ + #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_CTS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_CTS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_CTS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_CTS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_CTS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_CTS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_NCTS: Publish configuration for event NCTS */ + #define UARTE_PUBLISH_NCTS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_NCTS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event NCTS will publish to */ + #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_NCTS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_NCTS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_NCTS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_NCTS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_NCTS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_NCTS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_TXDRDY: Publish configuration for event TXDRDY */ + #define UARTE_PUBLISH_TXDRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXDRDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TXDRDY will publish to */ + #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_TXDRDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_TXDRDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_TXDRDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_TXDRDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_TXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_RXDRDY: Publish configuration for event RXDRDY */ + #define UARTE_PUBLISH_RXDRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXDRDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXDRDY will publish to */ + #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_RXDRDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_RXDRDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_RXDRDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_RXDRDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_RXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define UARTE_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_RXTO: Publish configuration for event RXTO */ + #define UARTE_PUBLISH_RXTO_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXTO register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXTO will publish to */ + #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_RXTO_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_RXTO_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_RXTO_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_RXTO_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_RXTO_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_RXTO_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_TXSTOPPED: Publish configuration for event TXSTOPPED */ + #define UARTE_PUBLISH_TXSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXSTOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TXSTOPPED will publish to */ + #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_FRAMETIMEOUT: Publish configuration for event FRAMETIMEOUT */ + #define UARTE_PUBLISH_FRAMETIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FRAMETIMEOUT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event FRAMETIMEOUT will publish to */ + #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Msk (0x1UL << UARTE_PUBLISH_FRAMETIMEOUT_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_SHORTS: Shortcuts between local events and tasks */ + #define UARTE_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* DMA_RX_END_DMA_RX_START @Bit 5 : Shortcut between event DMA.RX.END and task DMA.RX.START */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Pos (5UL) /*!< Position of DMA_RX_END_DMA_RX_START field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Msk (0x1UL << UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Pos) /*!< Bit mask of + DMA_RX_END_DMA_RX_START field.*/ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Min (0x0UL) /*!< Min enumerator value of DMA_RX_END_DMA_RX_START field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Max (0x1UL) /*!< Max enumerator value of DMA_RX_END_DMA_RX_START field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_END_DMA_RX_STOP @Bit 6 : Shortcut between event DMA.RX.END and task DMA.RX.STOP */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Pos (6UL) /*!< Position of DMA_RX_END_DMA_RX_STOP field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Msk (0x1UL << UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Pos) /*!< Bit mask of + DMA_RX_END_DMA_RX_STOP field.*/ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_RX_END_DMA_RX_STOP field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_RX_END_DMA_RX_STOP field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_TX_END_DMA_TX_STOP @Bit 18 : Shortcut between event DMA.TX.END and task DMA.TX.STOP */ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Pos (18UL) /*!< Position of DMA_TX_END_DMA_TX_STOP field. */ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Msk (0x1UL << UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Pos) /*!< Bit mask of + DMA_TX_END_DMA_TX_STOP field.*/ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_TX_END_DMA_TX_STOP field. */ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_TX_END_DMA_TX_STOP field. */ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows + daisy-chaining match events. */ + + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field. */ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows + daisy-chaining match events. */ + + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field. */ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows + daisy-chaining match events. */ + + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field. */ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows + daisy-chaining match events. */ + + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field. */ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) + /*!< Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) + /*!< Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) + /*!< Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) + /*!< Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* FRAMETIMEOUT_DMA_RX_STOP @Bit 29 : Shortcut between event FRAMETIMEOUT and task DMA.RX.STOP */ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Pos (29UL) /*!< Position of FRAMETIMEOUT_DMA_RX_STOP field. */ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Msk (0x1UL << UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Pos) /*!< Bit mask of + FRAMETIMEOUT_DMA_RX_STOP field.*/ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Min (0x0UL) /*!< Min enumerator value of FRAMETIMEOUT_DMA_RX_STOP field. */ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Max (0x1UL) /*!< Max enumerator value of FRAMETIMEOUT_DMA_RX_STOP field. */ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* UARTE_INTEN: Enable or disable interrupt */ + #define UARTE_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* CTS @Bit 0 : Enable or disable interrupt for event CTS */ + #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ + #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ + #define UARTE_INTEN_CTS_Min (0x0UL) /*!< Min enumerator value of CTS field. */ + #define UARTE_INTEN_CTS_Max (0x1UL) /*!< Max enumerator value of CTS field. */ + #define UARTE_INTEN_CTS_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_CTS_Enabled (0x1UL) /*!< Enable */ + +/* NCTS @Bit 1 : Enable or disable interrupt for event NCTS */ + #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ + #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ + #define UARTE_INTEN_NCTS_Min (0x0UL) /*!< Min enumerator value of NCTS field. */ + #define UARTE_INTEN_NCTS_Max (0x1UL) /*!< Max enumerator value of NCTS field. */ + #define UARTE_INTEN_NCTS_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_NCTS_Enabled (0x1UL) /*!< Enable */ + +/* TXDRDY @Bit 3 : Enable or disable interrupt for event TXDRDY */ + #define UARTE_INTEN_TXDRDY_Pos (3UL) /*!< Position of TXDRDY field. */ + #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ + #define UARTE_INTEN_TXDRDY_Min (0x0UL) /*!< Min enumerator value of TXDRDY field. */ + #define UARTE_INTEN_TXDRDY_Max (0x1UL) /*!< Max enumerator value of TXDRDY field. */ + #define UARTE_INTEN_TXDRDY_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_TXDRDY_Enabled (0x1UL) /*!< Enable */ + +/* RXDRDY @Bit 4 : Enable or disable interrupt for event RXDRDY */ + #define UARTE_INTEN_RXDRDY_Pos (4UL) /*!< Position of RXDRDY field. */ + #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ + #define UARTE_INTEN_RXDRDY_Min (0x0UL) /*!< Min enumerator value of RXDRDY field. */ + #define UARTE_INTEN_RXDRDY_Max (0x1UL) /*!< Max enumerator value of RXDRDY field. */ + #define UARTE_INTEN_RXDRDY_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_RXDRDY_Enabled (0x1UL) /*!< Enable */ + +/* ERROR @Bit 5 : Enable or disable interrupt for event ERROR */ + #define UARTE_INTEN_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define UARTE_INTEN_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define UARTE_INTEN_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define UARTE_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ + +/* RXTO @Bit 9 : Enable or disable interrupt for event RXTO */ + #define UARTE_INTEN_RXTO_Pos (9UL) /*!< Position of RXTO field. */ + #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ + #define UARTE_INTEN_RXTO_Min (0x0UL) /*!< Min enumerator value of RXTO field. */ + #define UARTE_INTEN_RXTO_Max (0x1UL) /*!< Max enumerator value of RXTO field. */ + #define UARTE_INTEN_RXTO_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_RXTO_Enabled (0x1UL) /*!< Enable */ + +/* TXSTOPPED @Bit 12 : Enable or disable interrupt for event TXSTOPPED */ + #define UARTE_INTEN_TXSTOPPED_Pos (12UL) /*!< Position of TXSTOPPED field. */ + #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ + #define UARTE_INTEN_TXSTOPPED_Min (0x0UL) /*!< Min enumerator value of TXSTOPPED field. */ + #define UARTE_INTEN_TXSTOPPED_Max (0x1UL) /*!< Max enumerator value of TXSTOPPED field. */ + #define UARTE_INTEN_TXSTOPPED_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_TXSTOPPED_Enabled (0x1UL) /*!< Enable */ + +/* DMARXEND @Bit 19 : Enable or disable interrupt for event DMARXEND */ + #define UARTE_INTEN_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define UARTE_INTEN_DMARXEND_Msk (0x1UL << UARTE_INTEN_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define UARTE_INTEN_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define UARTE_INTEN_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define UARTE_INTEN_DMARXEND_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMARXREADY @Bit 20 : Enable or disable interrupt for event DMARXREADY */ + #define UARTE_INTEN_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define UARTE_INTEN_DMARXREADY_Msk (0x1UL << UARTE_INTEN_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define UARTE_INTEN_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define UARTE_INTEN_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define UARTE_INTEN_DMARXREADY_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMARXBUSERROR @Bit 21 : Enable or disable interrupt for event DMARXBUSERROR */ + #define UARTE_INTEN_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define UARTE_INTEN_DMARXBUSERROR_Msk (0x1UL << UARTE_INTEN_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define UARTE_INTEN_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTEN_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTEN_DMARXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXBUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH0 @Bit 22 : Enable or disable interrupt for event DMARXMATCH[0] */ + #define UARTE_INTEN_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define UARTE_INTEN_DMARXMATCH0_Msk (0x1UL << UARTE_INTEN_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define UARTE_INTEN_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTEN_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTEN_DMARXMATCH0_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXMATCH0_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH1 @Bit 23 : Enable or disable interrupt for event DMARXMATCH[1] */ + #define UARTE_INTEN_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define UARTE_INTEN_DMARXMATCH1_Msk (0x1UL << UARTE_INTEN_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define UARTE_INTEN_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTEN_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTEN_DMARXMATCH1_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXMATCH1_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH2 @Bit 24 : Enable or disable interrupt for event DMARXMATCH[2] */ + #define UARTE_INTEN_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define UARTE_INTEN_DMARXMATCH2_Msk (0x1UL << UARTE_INTEN_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define UARTE_INTEN_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTEN_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTEN_DMARXMATCH2_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXMATCH2_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH3 @Bit 25 : Enable or disable interrupt for event DMARXMATCH[3] */ + #define UARTE_INTEN_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define UARTE_INTEN_DMARXMATCH3_Msk (0x1UL << UARTE_INTEN_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define UARTE_INTEN_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTEN_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTEN_DMARXMATCH3_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXMATCH3_Enabled (0x1UL) /*!< Enable */ + +/* DMATXEND @Bit 26 : Enable or disable interrupt for event DMATXEND */ + #define UARTE_INTEN_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define UARTE_INTEN_DMATXEND_Msk (0x1UL << UARTE_INTEN_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define UARTE_INTEN_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define UARTE_INTEN_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define UARTE_INTEN_DMATXEND_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMATXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMATXREADY @Bit 27 : Enable or disable interrupt for event DMATXREADY */ + #define UARTE_INTEN_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define UARTE_INTEN_DMATXREADY_Msk (0x1UL << UARTE_INTEN_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define UARTE_INTEN_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define UARTE_INTEN_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define UARTE_INTEN_DMATXREADY_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMATXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMATXBUSERROR @Bit 28 : Enable or disable interrupt for event DMATXBUSERROR */ + #define UARTE_INTEN_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define UARTE_INTEN_DMATXBUSERROR_Msk (0x1UL << UARTE_INTEN_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define UARTE_INTEN_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTEN_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTEN_DMATXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMATXBUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* FRAMETIMEOUT @Bit 29 : Enable or disable interrupt for event FRAMETIMEOUT */ + #define UARTE_INTEN_FRAMETIMEOUT_Pos (29UL) /*!< Position of FRAMETIMEOUT field. */ + #define UARTE_INTEN_FRAMETIMEOUT_Msk (0x1UL << UARTE_INTEN_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field. */ + #define UARTE_INTEN_FRAMETIMEOUT_Min (0x0UL) /*!< Min enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTEN_FRAMETIMEOUT_Max (0x1UL) /*!< Max enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTEN_FRAMETIMEOUT_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_FRAMETIMEOUT_Enabled (0x1UL) /*!< Enable */ + + +/* UARTE_INTENSET: Enable interrupt */ + #define UARTE_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* CTS @Bit 0 : Write '1' to enable interrupt for event CTS */ + #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ + #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ + #define UARTE_INTENSET_CTS_Min (0x0UL) /*!< Min enumerator value of CTS field. */ + #define UARTE_INTENSET_CTS_Max (0x1UL) /*!< Max enumerator value of CTS field. */ + #define UARTE_INTENSET_CTS_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_CTS_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_CTS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* NCTS @Bit 1 : Write '1' to enable interrupt for event NCTS */ + #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ + #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ + #define UARTE_INTENSET_NCTS_Min (0x0UL) /*!< Min enumerator value of NCTS field. */ + #define UARTE_INTENSET_NCTS_Max (0x1UL) /*!< Max enumerator value of NCTS field. */ + #define UARTE_INTENSET_NCTS_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_NCTS_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_NCTS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXDRDY @Bit 3 : Write '1' to enable interrupt for event TXDRDY */ + #define UARTE_INTENSET_TXDRDY_Pos (3UL) /*!< Position of TXDRDY field. */ + #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ + #define UARTE_INTENSET_TXDRDY_Min (0x0UL) /*!< Min enumerator value of TXDRDY field. */ + #define UARTE_INTENSET_TXDRDY_Max (0x1UL) /*!< Max enumerator value of TXDRDY field. */ + #define UARTE_INTENSET_TXDRDY_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXDRDY @Bit 4 : Write '1' to enable interrupt for event RXDRDY */ + #define UARTE_INTENSET_RXDRDY_Pos (4UL) /*!< Position of RXDRDY field. */ + #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ + #define UARTE_INTENSET_RXDRDY_Min (0x0UL) /*!< Min enumerator value of RXDRDY field. */ + #define UARTE_INTENSET_RXDRDY_Max (0x1UL) /*!< Max enumerator value of RXDRDY field. */ + #define UARTE_INTENSET_RXDRDY_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to enable interrupt for event ERROR */ + #define UARTE_INTENSET_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define UARTE_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define UARTE_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define UARTE_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXTO @Bit 9 : Write '1' to enable interrupt for event RXTO */ + #define UARTE_INTENSET_RXTO_Pos (9UL) /*!< Position of RXTO field. */ + #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ + #define UARTE_INTENSET_RXTO_Min (0x0UL) /*!< Min enumerator value of RXTO field. */ + #define UARTE_INTENSET_RXTO_Max (0x1UL) /*!< Max enumerator value of RXTO field. */ + #define UARTE_INTENSET_RXTO_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_RXTO_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_RXTO_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXSTOPPED @Bit 12 : Write '1' to enable interrupt for event TXSTOPPED */ + #define UARTE_INTENSET_TXSTOPPED_Pos (12UL) /*!< Position of TXSTOPPED field. */ + #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ + #define UARTE_INTENSET_TXSTOPPED_Min (0x0UL) /*!< Min enumerator value of TXSTOPPED field. */ + #define UARTE_INTENSET_TXSTOPPED_Max (0x1UL) /*!< Max enumerator value of TXSTOPPED field. */ + #define UARTE_INTENSET_TXSTOPPED_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */ + #define UARTE_INTENSET_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define UARTE_INTENSET_DMARXEND_Msk (0x1UL << UARTE_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define UARTE_INTENSET_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define UARTE_INTENSET_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define UARTE_INTENSET_DMARXEND_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */ + #define UARTE_INTENSET_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define UARTE_INTENSET_DMARXREADY_Msk (0x1UL << UARTE_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define UARTE_INTENSET_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define UARTE_INTENSET_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define UARTE_INTENSET_DMARXREADY_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */ + #define UARTE_INTENSET_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define UARTE_INTENSET_DMARXBUSERROR_Msk (0x1UL << UARTE_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define UARTE_INTENSET_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTENSET_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTENSET_DMARXBUSERROR_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */ + #define UARTE_INTENSET_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define UARTE_INTENSET_DMARXMATCH0_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define UARTE_INTENSET_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTENSET_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTENSET_DMARXMATCH0_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */ + #define UARTE_INTENSET_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define UARTE_INTENSET_DMARXMATCH1_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define UARTE_INTENSET_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTENSET_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTENSET_DMARXMATCH1_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */ + #define UARTE_INTENSET_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define UARTE_INTENSET_DMARXMATCH2_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define UARTE_INTENSET_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTENSET_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTENSET_DMARXMATCH2_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */ + #define UARTE_INTENSET_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define UARTE_INTENSET_DMARXMATCH3_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define UARTE_INTENSET_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTENSET_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTENSET_DMARXMATCH3_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */ + #define UARTE_INTENSET_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define UARTE_INTENSET_DMATXEND_Msk (0x1UL << UARTE_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define UARTE_INTENSET_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define UARTE_INTENSET_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define UARTE_INTENSET_DMATXEND_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */ + #define UARTE_INTENSET_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define UARTE_INTENSET_DMATXREADY_Msk (0x1UL << UARTE_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define UARTE_INTENSET_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define UARTE_INTENSET_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define UARTE_INTENSET_DMATXREADY_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */ + #define UARTE_INTENSET_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define UARTE_INTENSET_DMATXBUSERROR_Msk (0x1UL << UARTE_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define UARTE_INTENSET_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTENSET_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTENSET_DMATXBUSERROR_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMETIMEOUT @Bit 29 : Write '1' to enable interrupt for event FRAMETIMEOUT */ + #define UARTE_INTENSET_FRAMETIMEOUT_Pos (29UL) /*!< Position of FRAMETIMEOUT field. */ + #define UARTE_INTENSET_FRAMETIMEOUT_Msk (0x1UL << UARTE_INTENSET_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field. */ + #define UARTE_INTENSET_FRAMETIMEOUT_Min (0x0UL) /*!< Min enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTENSET_FRAMETIMEOUT_Max (0x1UL) /*!< Max enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTENSET_FRAMETIMEOUT_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_FRAMETIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_FRAMETIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* UARTE_INTENCLR: Disable interrupt */ + #define UARTE_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* CTS @Bit 0 : Write '1' to disable interrupt for event CTS */ + #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ + #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ + #define UARTE_INTENCLR_CTS_Min (0x0UL) /*!< Min enumerator value of CTS field. */ + #define UARTE_INTENCLR_CTS_Max (0x1UL) /*!< Max enumerator value of CTS field. */ + #define UARTE_INTENCLR_CTS_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_CTS_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_CTS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* NCTS @Bit 1 : Write '1' to disable interrupt for event NCTS */ + #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ + #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ + #define UARTE_INTENCLR_NCTS_Min (0x0UL) /*!< Min enumerator value of NCTS field. */ + #define UARTE_INTENCLR_NCTS_Max (0x1UL) /*!< Max enumerator value of NCTS field. */ + #define UARTE_INTENCLR_NCTS_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_NCTS_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_NCTS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXDRDY @Bit 3 : Write '1' to disable interrupt for event TXDRDY */ + #define UARTE_INTENCLR_TXDRDY_Pos (3UL) /*!< Position of TXDRDY field. */ + #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ + #define UARTE_INTENCLR_TXDRDY_Min (0x0UL) /*!< Min enumerator value of TXDRDY field. */ + #define UARTE_INTENCLR_TXDRDY_Max (0x1UL) /*!< Max enumerator value of TXDRDY field. */ + #define UARTE_INTENCLR_TXDRDY_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXDRDY @Bit 4 : Write '1' to disable interrupt for event RXDRDY */ + #define UARTE_INTENCLR_RXDRDY_Pos (4UL) /*!< Position of RXDRDY field. */ + #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ + #define UARTE_INTENCLR_RXDRDY_Min (0x0UL) /*!< Min enumerator value of RXDRDY field. */ + #define UARTE_INTENCLR_RXDRDY_Max (0x1UL) /*!< Max enumerator value of RXDRDY field. */ + #define UARTE_INTENCLR_RXDRDY_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to disable interrupt for event ERROR */ + #define UARTE_INTENCLR_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define UARTE_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define UARTE_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define UARTE_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXTO @Bit 9 : Write '1' to disable interrupt for event RXTO */ + #define UARTE_INTENCLR_RXTO_Pos (9UL) /*!< Position of RXTO field. */ + #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ + #define UARTE_INTENCLR_RXTO_Min (0x0UL) /*!< Min enumerator value of RXTO field. */ + #define UARTE_INTENCLR_RXTO_Max (0x1UL) /*!< Max enumerator value of RXTO field. */ + #define UARTE_INTENCLR_RXTO_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_RXTO_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_RXTO_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXSTOPPED @Bit 12 : Write '1' to disable interrupt for event TXSTOPPED */ + #define UARTE_INTENCLR_TXSTOPPED_Pos (12UL) /*!< Position of TXSTOPPED field. */ + #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ + #define UARTE_INTENCLR_TXSTOPPED_Min (0x0UL) /*!< Min enumerator value of TXSTOPPED field. */ + #define UARTE_INTENCLR_TXSTOPPED_Max (0x1UL) /*!< Max enumerator value of TXSTOPPED field. */ + #define UARTE_INTENCLR_TXSTOPPED_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */ + #define UARTE_INTENCLR_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define UARTE_INTENCLR_DMARXEND_Msk (0x1UL << UARTE_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define UARTE_INTENCLR_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define UARTE_INTENCLR_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define UARTE_INTENCLR_DMARXEND_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */ + #define UARTE_INTENCLR_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define UARTE_INTENCLR_DMARXREADY_Msk (0x1UL << UARTE_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define UARTE_INTENCLR_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define UARTE_INTENCLR_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define UARTE_INTENCLR_DMARXREADY_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */ + #define UARTE_INTENCLR_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define UARTE_INTENCLR_DMARXBUSERROR_Msk (0x1UL << UARTE_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define UARTE_INTENCLR_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTENCLR_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTENCLR_DMARXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */ + #define UARTE_INTENCLR_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define UARTE_INTENCLR_DMARXMATCH0_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define UARTE_INTENCLR_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTENCLR_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTENCLR_DMARXMATCH0_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */ + #define UARTE_INTENCLR_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define UARTE_INTENCLR_DMARXMATCH1_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define UARTE_INTENCLR_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTENCLR_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTENCLR_DMARXMATCH1_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */ + #define UARTE_INTENCLR_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define UARTE_INTENCLR_DMARXMATCH2_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define UARTE_INTENCLR_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTENCLR_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTENCLR_DMARXMATCH2_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */ + #define UARTE_INTENCLR_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define UARTE_INTENCLR_DMARXMATCH3_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define UARTE_INTENCLR_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTENCLR_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTENCLR_DMARXMATCH3_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */ + #define UARTE_INTENCLR_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define UARTE_INTENCLR_DMATXEND_Msk (0x1UL << UARTE_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define UARTE_INTENCLR_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define UARTE_INTENCLR_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define UARTE_INTENCLR_DMATXEND_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */ + #define UARTE_INTENCLR_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define UARTE_INTENCLR_DMATXREADY_Msk (0x1UL << UARTE_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define UARTE_INTENCLR_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define UARTE_INTENCLR_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define UARTE_INTENCLR_DMATXREADY_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */ + #define UARTE_INTENCLR_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define UARTE_INTENCLR_DMATXBUSERROR_Msk (0x1UL << UARTE_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define UARTE_INTENCLR_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTENCLR_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTENCLR_DMATXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMETIMEOUT @Bit 29 : Write '1' to disable interrupt for event FRAMETIMEOUT */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Pos (29UL) /*!< Position of FRAMETIMEOUT field. */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Msk (0x1UL << UARTE_INTENCLR_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field. */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Min (0x0UL) /*!< Min enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Max (0x1UL) /*!< Max enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* UARTE_ERRORSRC: Error source */ + #define UARTE_ERRORSRC_ResetValue (0x00000000UL) /*!< Reset value of ERRORSRC register. */ + +/* OVERRUN @Bit 0 : Overrun error */ + #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ + #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ + #define UARTE_ERRORSRC_OVERRUN_Min (0x0UL) /*!< Min enumerator value of OVERRUN field. */ + #define UARTE_ERRORSRC_OVERRUN_Max (0x1UL) /*!< Max enumerator value of OVERRUN field. */ + #define UARTE_ERRORSRC_OVERRUN_NotPresent (0x0UL) /*!< Read: error not present */ + #define UARTE_ERRORSRC_OVERRUN_Present (0x1UL) /*!< Read: error present */ + +/* PARITY @Bit 1 : Parity error */ + #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ + #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ + #define UARTE_ERRORSRC_PARITY_Min (0x0UL) /*!< Min enumerator value of PARITY field. */ + #define UARTE_ERRORSRC_PARITY_Max (0x1UL) /*!< Max enumerator value of PARITY field. */ + #define UARTE_ERRORSRC_PARITY_NotPresent (0x0UL) /*!< Read: error not present */ + #define UARTE_ERRORSRC_PARITY_Present (0x1UL) /*!< Read: error present */ + +/* FRAMING @Bit 2 : Framing error occurred */ + #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ + #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ + #define UARTE_ERRORSRC_FRAMING_Min (0x0UL) /*!< Min enumerator value of FRAMING field. */ + #define UARTE_ERRORSRC_FRAMING_Max (0x1UL) /*!< Max enumerator value of FRAMING field. */ + #define UARTE_ERRORSRC_FRAMING_NotPresent (0x0UL) /*!< Read: error not present */ + #define UARTE_ERRORSRC_FRAMING_Present (0x1UL) /*!< Read: error present */ + +/* BREAK @Bit 3 : Break condition */ + #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ + #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ + #define UARTE_ERRORSRC_BREAK_Min (0x0UL) /*!< Min enumerator value of BREAK field. */ + #define UARTE_ERRORSRC_BREAK_Max (0x1UL) /*!< Max enumerator value of BREAK field. */ + #define UARTE_ERRORSRC_BREAK_NotPresent (0x0UL) /*!< Read: error not present */ + #define UARTE_ERRORSRC_BREAK_Present (0x1UL) /*!< Read: error present */ + + +/* UARTE_ENABLE: Enable UART */ + #define UARTE_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..3 : Enable or disable UARTE */ + #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define UARTE_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define UARTE_ENABLE_ENABLE_Max (0x8UL) /*!< Max enumerator value of ENABLE field. */ + #define UARTE_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable UARTE */ + #define UARTE_ENABLE_ENABLE_Enabled (0x8UL) /*!< Enable UARTE */ + + +/* UARTE_BAUDRATE: Baud rate. Accuracy depends on the HFCLK source selected. */ + #define UARTE_BAUDRATE_ResetValue (0x04000000UL) /*!< Reset value of BAUDRATE register. */ + +/* BAUDRATE @Bits 0..31 : Baud rate */ + #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ + #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ + #define UARTE_BAUDRATE_BAUDRATE_Min (0x0004F000UL) /*!< Min enumerator value of BAUDRATE field. */ + #define UARTE_BAUDRATE_BAUDRATE_Max (0x10000000UL) /*!< Max enumerator value of BAUDRATE field. */ + #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud when UARTE has 16 MHz peripheral clock frequency */ + #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud when UARTE has 16 MHz peripheral clock frequency */ + #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud when UARTE has 16 MHz peripheral clock frequency */ + + +/* UARTE_CONFIG: Configuration of parity, hardware flow control, framesize, and packet timeout. */ + #define UARTE_CONFIG_ResetValue (0x00001000UL) /*!< Reset value of CONFIG register. */ + +/* HWFC @Bit 0 : Hardware flow control */ + #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ + #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ + #define UARTE_CONFIG_HWFC_Min (0x0UL) /*!< Min enumerator value of HWFC field. */ + #define UARTE_CONFIG_HWFC_Max (0x1UL) /*!< Max enumerator value of HWFC field. */ + #define UARTE_CONFIG_HWFC_Disabled (0x0UL) /*!< Disabled */ + #define UARTE_CONFIG_HWFC_Enabled (0x1UL) /*!< Enabled */ + +/* PARITY @Bits 1..3 : Parity */ + #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ + #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ + #define UARTE_CONFIG_PARITY_Min (0x0UL) /*!< Min enumerator value of PARITY field. */ + #define UARTE_CONFIG_PARITY_Max (0x7UL) /*!< Max enumerator value of PARITY field. */ + #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ + #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* STOP @Bit 4 : Stop bits */ + #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ + #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ + #define UARTE_CONFIG_STOP_Min (0x0UL) /*!< Min enumerator value of STOP field. */ + #define UARTE_CONFIG_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define UARTE_CONFIG_STOP_One (0x0UL) /*!< One stop bit */ + #define UARTE_CONFIG_STOP_Two (0x1UL) /*!< Two stop bits */ + +/* PARITYTYPE @Bit 8 : Even or odd parity type */ + #define UARTE_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */ + #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */ + #define UARTE_CONFIG_PARITYTYPE_Min (0x0UL) /*!< Min enumerator value of PARITYTYPE field. */ + #define UARTE_CONFIG_PARITYTYPE_Max (0x1UL) /*!< Max enumerator value of PARITYTYPE field. */ + #define UARTE_CONFIG_PARITYTYPE_Even (0x0UL) /*!< Even parity */ + #define UARTE_CONFIG_PARITYTYPE_Odd (0x1UL) /*!< Odd parity */ + +/* FRAMESIZE @Bits 9..12 : Set the data frame size */ + #define UARTE_CONFIG_FRAMESIZE_Pos (9UL) /*!< Position of FRAMESIZE field. */ + #define UARTE_CONFIG_FRAMESIZE_Msk (0xFUL << UARTE_CONFIG_FRAMESIZE_Pos) /*!< Bit mask of FRAMESIZE field. */ + #define UARTE_CONFIG_FRAMESIZE_Min (0x4UL) /*!< Min enumerator value of FRAMESIZE field. */ + #define UARTE_CONFIG_FRAMESIZE_Max (0x9UL) /*!< Max enumerator value of FRAMESIZE field. */ + #define UARTE_CONFIG_FRAMESIZE_9bit (0x9UL) /*!< 9 bit data frame size. 9th bit is treated as address bit. */ + #define UARTE_CONFIG_FRAMESIZE_8bit (0x8UL) /*!< 8 bit data frame size. */ + #define UARTE_CONFIG_FRAMESIZE_7bit (0x7UL) /*!< 7 bit data frame size. */ + #define UARTE_CONFIG_FRAMESIZE_6bit (0x6UL) /*!< 6 bit data frame size. */ + #define UARTE_CONFIG_FRAMESIZE_5bit (0x5UL) /*!< 5 bit data frame size. */ + #define UARTE_CONFIG_FRAMESIZE_4bit (0x4UL) /*!< 4 bit data frame size. */ + +/* ENDIAN @Bit 13 : Select if data is trimmed from MSB or LSB end when the data frame size is less than 8. */ + #define UARTE_CONFIG_ENDIAN_Pos (13UL) /*!< Position of ENDIAN field. */ + #define UARTE_CONFIG_ENDIAN_Msk (0x1UL << UARTE_CONFIG_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ + #define UARTE_CONFIG_ENDIAN_Min (0x0UL) /*!< Min enumerator value of ENDIAN field. */ + #define UARTE_CONFIG_ENDIAN_Max (0x1UL) /*!< Max enumerator value of ENDIAN field. */ + #define UARTE_CONFIG_ENDIAN_MSB (0x0UL) /*!< Data is trimmed from MSB end. */ + #define UARTE_CONFIG_ENDIAN_LSB (0x1UL) /*!< Data is trimmed from LSB end. */ + +/* FRAMETIMEOUT @Bit 14 : Enable packet timeout. */ + #define UARTE_CONFIG_FRAMETIMEOUT_Pos (14UL) /*!< Position of FRAMETIMEOUT field. */ + #define UARTE_CONFIG_FRAMETIMEOUT_Msk (0x1UL << UARTE_CONFIG_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field. */ + #define UARTE_CONFIG_FRAMETIMEOUT_Min (0x0UL) /*!< Min enumerator value of FRAMETIMEOUT field. */ + #define UARTE_CONFIG_FRAMETIMEOUT_Max (0x1UL) /*!< Max enumerator value of FRAMETIMEOUT field. */ + #define UARTE_CONFIG_FRAMETIMEOUT_DISABLED (0x0UL) /*!< Packet timeout is disabled. */ + #define UARTE_CONFIG_FRAMETIMEOUT_ENABLED (0x1UL) /*!< Packet timeout is enabled. */ + #define UARTE_CONFIG_FRAMETIMEOUT_Disabled (0x0UL) /*!< Packet timeout is disabled. */ + #define UARTE_CONFIG_FRAMETIMEOUT_Enabled (0x1UL) /*!< Packet timeout is enabled. */ + + +/* UARTE_ADDRESS: Set the address of the UARTE for RX when used in 9 bit data frame mode. */ + #define UARTE_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* ADDRESS @Bits 0..7 : Set address */ + #define UARTE_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UARTE_ADDRESS_ADDRESS_Msk (0xFFUL << UARTE_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* UARTE_FRAMETIMEOUT: Set the number of UARTE bits to count before triggering packet timeout. */ + #define UARTE_FRAMETIMEOUT_ResetValue (0x00000010UL) /*!< Reset value of FRAMETIMEOUT register. */ + +/* COUNTERTOP @Bits 0..9 : Number of UARTE bits before timeout. */ + #define UARTE_FRAMETIMEOUT_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ + #define UARTE_FRAMETIMEOUT_COUNTERTOP_Msk (0x3FFUL << UARTE_FRAMETIMEOUT_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct UICR_APPROTECT ================================================== */ +/** + * @brief APPROTECT [UICR_APPROTECT] Access Port Protection Registers + */ +typedef struct { + __IOM uint32_t PROTECT0; /*!< (@ 0x00000000) Access port protection */ + __IM uint32_t RESERVED[6]; + __IOM uint32_t PROTECT1; /*!< (@ 0x0000001C) Access port protection */ +} NRF_UICR_APPROTECT_Type; /*!< Size = 32 (0x020) */ + #define UICR_APPROTECT_MaxCount (1UL) /*!< Size of APPROTECT[1] array. */ + #define UICR_APPROTECT_MaxIndex (0UL) /*!< Max index of APPROTECT[1] array. */ + #define UICR_APPROTECT_MinIndex (0UL) /*!< Min index of APPROTECT[1] array. */ + +/* UICR_APPROTECT_PROTECT0: Access port protection */ + #define UICR_APPROTECT_PROTECT0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT0 register. */ + +/* PALL @Bits 0..31 : (unspecified) */ + #define UICR_APPROTECT_PROTECT0_PALL_Pos (0UL) /*!< Position of PALL field. */ + #define UICR_APPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL field. */ + #define UICR_APPROTECT_PROTECT0_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_APPROTECT_PROTECT0_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_APPROTECT_PROTECT0_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal + protectors unlocked and under CPU control.*/ + + +/* UICR_APPROTECT_PROTECT1: Access port protection */ + #define UICR_APPROTECT_PROTECT1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT1 register. */ + +/* PALL @Bits 0..31 : (unspecified) */ + #define UICR_APPROTECT_PROTECT1_PALL_Pos (0UL) /*!< Position of PALL field. */ + #define UICR_APPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL field. */ + #define UICR_APPROTECT_PROTECT1_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_APPROTECT_PROTECT1_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_APPROTECT_PROTECT1_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal + protectors unlocked and under CPU control.*/ + + + +/* =============================================== Struct UICR_SECUREAPPROTECT =============================================== */ +/** + * @brief SECUREAPPROTECT [UICR_SECUREAPPROTECT] Access Port Protection Registers + */ +typedef struct { + __IOM uint32_t PROTECT0; /*!< (@ 0x00000000) Access port protection */ + __IM uint32_t RESERVED[6]; + __IOM uint32_t PROTECT1; /*!< (@ 0x0000001C) Access port protection register */ +} NRF_UICR_SECUREAPPROTECT_Type; /*!< Size = 32 (0x020) */ + #define UICR_SECUREAPPROTECT_MaxCount (1UL) /*!< Size of SECUREAPPROTECT[1] array. */ + #define UICR_SECUREAPPROTECT_MaxIndex (0UL) /*!< Max index of SECUREAPPROTECT[1] array. */ + #define UICR_SECUREAPPROTECT_MinIndex (0UL) /*!< Min index of SECUREAPPROTECT[1] array. */ + +/* UICR_SECUREAPPROTECT_PROTECT0: Access port protection */ + #define UICR_SECUREAPPROTECT_PROTECT0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT0 register. */ + +/* PALL @Bits 0..31 : (unspecified) */ + #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Pos (0UL) /*!< Position of PALL field. */ + #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL + field.*/ + #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN + signal protectors unlocked and under CPU control.*/ + + +/* UICR_SECUREAPPROTECT_PROTECT1: Access port protection register */ + #define UICR_SECUREAPPROTECT_PROTECT1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT1 register. */ + +/* PALL @Bits 0..31 : (unspecified) */ + #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Pos (0UL) /*!< Position of PALL field. */ + #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL + field.*/ + #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN + signal protectors unlocked and under CPU control.*/ + + + +/* ================================================ Struct UICR_AUXAPPROTECT ================================================= */ +/** + * @brief AUXAPPROTECT [UICR_AUXAPPROTECT] Access Port Protection Registers + */ +typedef struct { + __IOM uint32_t PROTECT0; /*!< (@ 0x00000000) Access port protection */ + __IM uint32_t RESERVED[6]; + __IOM uint32_t PROTECT1; /*!< (@ 0x0000001C) Access port protection register */ +} NRF_UICR_AUXAPPROTECT_Type; /*!< Size = 32 (0x020) */ + #define UICR_AUXAPPROTECT_MaxCount (1UL) /*!< Size of AUXAPPROTECT[1] array. */ + #define UICR_AUXAPPROTECT_MaxIndex (0UL) /*!< Max index of AUXAPPROTECT[1] array. */ + #define UICR_AUXAPPROTECT_MinIndex (0UL) /*!< Min index of AUXAPPROTECT[1] array. */ + +/* UICR_AUXAPPROTECT_PROTECT0: Access port protection */ + #define UICR_AUXAPPROTECT_PROTECT0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT0 register. */ + +/* PALL @Bits 0..31 : (unspecified) */ + #define UICR_AUXAPPROTECT_PROTECT0_PALL_Pos (0UL) /*!< Position of PALL field. */ + #define UICR_AUXAPPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_AUXAPPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL + field.*/ + #define UICR_AUXAPPROTECT_PROTECT0_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_AUXAPPROTECT_PROTECT0_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_AUXAPPROTECT_PROTECT0_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.AP DBGEN signal protector + unlocked and under CPU control.*/ + + +/* UICR_AUXAPPROTECT_PROTECT1: Access port protection register */ + #define UICR_AUXAPPROTECT_PROTECT1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT1 register. */ + +/* PALL @Bits 0..31 : (unspecified) */ + #define UICR_AUXAPPROTECT_PROTECT1_PALL_Pos (0UL) /*!< Position of PALL field. */ + #define UICR_AUXAPPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_AUXAPPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL + field.*/ + #define UICR_AUXAPPROTECT_PROTECT1_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_AUXAPPROTECT_PROTECT1_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_AUXAPPROTECT_PROTECT1_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.AP DBGEN signal protector + unlocked and under CPU control.*/ + + + +/* ================================================ Struct UICR_ERASEPROTECT ================================================= */ +/** + * @brief ERASEPROTECT [UICR_ERASEPROTECT] Erase Protection Registers + */ +typedef struct { + __IOM uint32_t PROTECT0; /*!< (@ 0x00000000) Erase protection */ + __IM uint32_t RESERVED[6]; + __IOM uint32_t PROTECT1; /*!< (@ 0x0000001C) Erase protection */ +} NRF_UICR_ERASEPROTECT_Type; /*!< Size = 32 (0x020) */ + #define UICR_ERASEPROTECT_MaxCount (1UL) /*!< Size of ERASEPROTECT[1] array. */ + #define UICR_ERASEPROTECT_MaxIndex (0UL) /*!< Max index of ERASEPROTECT[1] array. */ + #define UICR_ERASEPROTECT_MinIndex (0UL) /*!< Min index of ERASEPROTECT[1] array. */ + +/* UICR_ERASEPROTECT_PROTECT0: Erase protection */ + #define UICR_ERASEPROTECT_PROTECT0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT0 register. */ + +/* PALL @Bits 0..31 : (unspecified) */ + #define UICR_ERASEPROTECT_PROTECT0_PALL_Pos (0UL) /*!< Position of PALL field. */ + #define UICR_ERASEPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL + field.*/ + #define UICR_ERASEPROTECT_PROTECT0_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field. */ + #define UICR_ERASEPROTECT_PROTECT0_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field. */ + #define UICR_ERASEPROTECT_PROTECT0_PALL_Protected (0x50FA50FAUL) /*!< Erase protection is enabled and the signal protector is + locked.*/ + + +/* UICR_ERASEPROTECT_PROTECT1: Erase protection */ + #define UICR_ERASEPROTECT_PROTECT1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT1 register. */ + +/* PALL @Bits 0..31 : (unspecified) */ + #define UICR_ERASEPROTECT_PROTECT1_PALL_Pos (0UL) /*!< Position of PALL field. */ + #define UICR_ERASEPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL + field.*/ + #define UICR_ERASEPROTECT_PROTECT1_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field. */ + #define UICR_ERASEPROTECT_PROTECT1_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field. */ + #define UICR_ERASEPROTECT_PROTECT1_PALL_Protected (0x50FA50FAUL) /*!< Erase protection is enabled and the signal protector is + locked.*/ + + + +/* =============================================== Struct UICR_USER_ROT_PUBKEY =============================================== */ +/** + * @brief PUBKEY [UICR_USER_ROT_PUBKEY] (unspecified) + */ +typedef struct { + __IOM uint32_t DIGEST[8]; /*!< (@ 0x00000000) First 256 bits of SHA2-512 digest over RoT public key + generation [n].*/ + __IOM uint32_t REVOKE[3]; /*!< (@ 0x00000020) Revocation status for RoT public key generation [n]. */ +} NRF_UICR_USER_ROT_PUBKEY_Type; /*!< Size = 44 (0x02C) */ + #define UICR_USER_ROT_PUBKEY_MaxCount (4UL) /*!< Size of PUBKEY[4] array. */ + #define UICR_USER_ROT_PUBKEY_MaxIndex (3UL) /*!< Max index of PUBKEY[4] array. */ + #define UICR_USER_ROT_PUBKEY_MinIndex (0UL) /*!< Min index of PUBKEY[4] array. */ + +/* UICR_USER_ROT_PUBKEY_DIGEST: First 256 bits of SHA2-512 digest over RoT public key generation [n]. */ + #define UICR_USER_ROT_PUBKEY_DIGEST_MaxCount (8UL) /*!< Max size of DIGEST[8] array. */ + #define UICR_USER_ROT_PUBKEY_DIGEST_MaxIndex (7UL) /*!< Max index of DIGEST[8] array. */ + #define UICR_USER_ROT_PUBKEY_DIGEST_MinIndex (0UL) /*!< Min index of DIGEST[8] array. */ + #define UICR_USER_ROT_PUBKEY_DIGEST_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DIGEST[8] register. */ + +/* VALUE @Bits 0..31 : Value for word [o] in the key digest [n]. */ + #define UICR_USER_ROT_PUBKEY_DIGEST_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define UICR_USER_ROT_PUBKEY_DIGEST_VALUE_Msk (0xFFFFFFFFUL << UICR_USER_ROT_PUBKEY_DIGEST_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + + +/* UICR_USER_ROT_PUBKEY_REVOKE: Revocation status for RoT public key generation [n]. */ + #define UICR_USER_ROT_PUBKEY_REVOKE_MaxCount (3UL) /*!< Max size of REVOKE[3] array. */ + #define UICR_USER_ROT_PUBKEY_REVOKE_MaxIndex (2UL) /*!< Max index of REVOKE[3] array. */ + #define UICR_USER_ROT_PUBKEY_REVOKE_MinIndex (0UL) /*!< Min index of REVOKE[3] array. */ + #define UICR_USER_ROT_PUBKEY_REVOKE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of REVOKE[3] register. */ + +/* STATUS @Bits 0..31 : Revocation status. */ + #define UICR_USER_ROT_PUBKEY_REVOKE_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define UICR_USER_ROT_PUBKEY_REVOKE_STATUS_Msk (0xFFFFFFFFUL << UICR_USER_ROT_PUBKEY_REVOKE_STATUS_Pos) /*!< Bit mask of + STATUS field.*/ + #define UICR_USER_ROT_PUBKEY_REVOKE_STATUS_Min (0xFFFFFFFFUL) /*!< Min enumerator value of STATUS field. */ + #define UICR_USER_ROT_PUBKEY_REVOKE_STATUS_Max (0xFFFFFFFFUL) /*!< Max enumerator value of STATUS field. */ + #define UICR_USER_ROT_PUBKEY_REVOKE_STATUS_NotRevoked (0xFFFFFFFFUL) /*!< Key not revoked. */ + + + +/* ============================================= Struct UICR_USER_ROT_AUTHOPKEY ============================================== */ +/** + * @brief AUTHOPKEY [UICR_USER_ROT_AUTHOPKEY] (unspecified) + */ +typedef struct { + __IOM uint32_t DIGEST[8]; /*!< (@ 0x00000000) First 256 bits of SHA2-512 digest over RoT + authenticated operation public key generation [n].*/ + __IOM uint32_t REVOKE[3]; /*!< (@ 0x00000020) Revocation status for RoT authenticated operation + public key generation [n].*/ +} NRF_UICR_USER_ROT_AUTHOPKEY_Type; /*!< Size = 44 (0x02C) */ + #define UICR_USER_ROT_AUTHOPKEY_MaxCount (4UL) /*!< Size of AUTHOPKEY[4] array. */ + #define UICR_USER_ROT_AUTHOPKEY_MaxIndex (3UL) /*!< Max index of AUTHOPKEY[4] array. */ + #define UICR_USER_ROT_AUTHOPKEY_MinIndex (0UL) /*!< Min index of AUTHOPKEY[4] array. */ + +/* UICR_USER_ROT_AUTHOPKEY_DIGEST: First 256 bits of SHA2-512 digest over RoT authenticated operation public key generation [n]. + */ + + #define UICR_USER_ROT_AUTHOPKEY_DIGEST_MaxCount (8UL) /*!< Max size of DIGEST[8] array. */ + #define UICR_USER_ROT_AUTHOPKEY_DIGEST_MaxIndex (7UL) /*!< Max index of DIGEST[8] array. */ + #define UICR_USER_ROT_AUTHOPKEY_DIGEST_MinIndex (0UL) /*!< Min index of DIGEST[8] array. */ + #define UICR_USER_ROT_AUTHOPKEY_DIGEST_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DIGEST[8] register. */ + +/* VALUE @Bits 0..31 : Value for word [o] in the key digest [n]. */ + #define UICR_USER_ROT_AUTHOPKEY_DIGEST_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define UICR_USER_ROT_AUTHOPKEY_DIGEST_VALUE_Msk (0xFFFFFFFFUL << UICR_USER_ROT_AUTHOPKEY_DIGEST_VALUE_Pos) /*!< Bit mask of + VALUE field.*/ + + +/* UICR_USER_ROT_AUTHOPKEY_REVOKE: Revocation status for RoT authenticated operation public key generation [n]. */ + #define UICR_USER_ROT_AUTHOPKEY_REVOKE_MaxCount (3UL) /*!< Max size of REVOKE[3] array. */ + #define UICR_USER_ROT_AUTHOPKEY_REVOKE_MaxIndex (2UL) /*!< Max index of REVOKE[3] array. */ + #define UICR_USER_ROT_AUTHOPKEY_REVOKE_MinIndex (0UL) /*!< Min index of REVOKE[3] array. */ + #define UICR_USER_ROT_AUTHOPKEY_REVOKE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of REVOKE[3] register. */ + +/* STATUS @Bits 0..31 : Revocation status. */ + #define UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_Msk (0xFFFFFFFFUL << UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_Pos) /*!< Bit mask of + STATUS field.*/ + #define UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_Min (0xFFFFFFFFUL) /*!< Min enumerator value of STATUS field. */ + #define UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_Max (0xFFFFFFFFUL) /*!< Max enumerator value of STATUS field. */ + #define UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_NotRevoked (0xFFFFFFFFUL) /*!< Key not revoked. */ + + + +/* ================================================== Struct UICR_USER_ROT =================================================== */ +/** + * @brief ROT [UICR_USER_ROT] Assets installed to establish initial Root of Trust in the device. + */ +typedef struct { + __IOM NRF_UICR_USER_ROT_PUBKEY_Type PUBKEY[4]; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_UICR_USER_ROT_AUTHOPKEY_Type AUTHOPKEY[4]; /*!< (@ 0x000000B0) (unspecified) */ +} NRF_UICR_USER_ROT_Type; /*!< Size = 352 (0x160) */ + + +/* ==================================================== Struct UICR_USER ===================================================== */ +/** + * @brief USER [UICR_USER] (unspecified) + */ +typedef struct { + __IOM NRF_UICR_USER_ROT_Type ROT; /*!< (@ 0x00000000) Assets installed to establish initial Root of Trust in + the device.*/ +} NRF_UICR_USER_Type; /*!< Size = 352 (0x160) */ + +/* ======================================================= Struct UICR ======================================================= */ +/** + * @brief User Information Configuration Registers + */ + typedef struct { /*!< UICR Structure */ + __IOM NRF_UICR_APPROTECT_Type APPROTECT[1]; /*!< (@ 0x00000000) Access Port Protection Registers */ + __IOM NRF_UICR_SECUREAPPROTECT_Type SECUREAPPROTECT[1]; /*!< (@ 0x00000020) Access Port Protection Registers */ + __IOM NRF_UICR_AUXAPPROTECT_Type AUXAPPROTECT[1]; /*!< (@ 0x00000040) Access Port Protection Registers */ + __IOM NRF_UICR_ERASEPROTECT_Type ERASEPROTECT[1]; /*!< (@ 0x00000060) Erase Protection Registers */ + __IOM uint32_t BOOTCONF; /*!< (@ 0x00000080) Immutable boot region configuration. */ + __IM uint32_t RESERVED[95]; + __IOM NRF_UICR_USER_Type USER; /*!< (@ 0x00000200) (unspecified) */ + __IM uint32_t RESERVED1[104]; + __IOM uint32_t OTP[320]; /*!< (@ 0x00000500) One time programmable memory */ + } NRF_UICR_Type; /*!< Size = 2560 (0xA00) */ + +/* UICR_BOOTCONF: Immutable boot region configuration. */ + #define UICR_BOOTCONF_ResetValue (0xFFFFFFFFUL) /*!< Reset value of BOOTCONF register. */ + +/* READ @Bit 0 : Read access. Must be enabled in order for the Arm Cortex CPU to start executing from RRAM. */ + #define UICR_BOOTCONF_READ_Pos (0UL) /*!< Position of READ field. */ + #define UICR_BOOTCONF_READ_Msk (0x1UL << UICR_BOOTCONF_READ_Pos) /*!< Bit mask of READ field. */ + #define UICR_BOOTCONF_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define UICR_BOOTCONF_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define UICR_BOOTCONF_READ_NotAllowed (0x0UL) /*!< Reading from the region is not allowed. */ + #define UICR_BOOTCONF_READ_Allowed (0x1UL) /*!< Reading from the region is allowed */ + +/* WRITE @Bit 1 : Write access */ + #define UICR_BOOTCONF_WRITE_Pos (1UL) /*!< Position of WRITE field. */ + #define UICR_BOOTCONF_WRITE_Msk (0x1UL << UICR_BOOTCONF_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define UICR_BOOTCONF_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define UICR_BOOTCONF_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define UICR_BOOTCONF_WRITE_NotAllowed (0x0UL) /*!< Writing to the region is not allowed */ + #define UICR_BOOTCONF_WRITE_Allowed (0x1UL) /*!< Writing to the region is allowed */ + +/* EXECUTE @Bit 2 : Execute access */ + #define UICR_BOOTCONF_EXECUTE_Pos (2UL) /*!< Position of EXECUTE field. */ + #define UICR_BOOTCONF_EXECUTE_Msk (0x1UL << UICR_BOOTCONF_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ + #define UICR_BOOTCONF_EXECUTE_Min (0x0UL) /*!< Min enumerator value of EXECUTE field. */ + #define UICR_BOOTCONF_EXECUTE_Max (0x1UL) /*!< Max enumerator value of EXECUTE field. */ + #define UICR_BOOTCONF_EXECUTE_NotAllowed (0x0UL) /*!< Executing code from the region is not allowed */ + #define UICR_BOOTCONF_EXECUTE_Allowed (0x1UL) /*!< Executing code from the region is allowed */ + +/* SECURE @Bit 3 : Secure access */ + #define UICR_BOOTCONF_SECURE_Pos (3UL) /*!< Position of SECURE field. */ + #define UICR_BOOTCONF_SECURE_Msk (0x1UL << UICR_BOOTCONF_SECURE_Pos) /*!< Bit mask of SECURE field. */ + #define UICR_BOOTCONF_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field. */ + #define UICR_BOOTCONF_SECURE_Max (0x1UL) /*!< Max enumerator value of SECURE field. */ + #define UICR_BOOTCONF_SECURE_NonSecure (0x0UL) /*!< Both secure and non-secure access to region is allowed */ + #define UICR_BOOTCONF_SECURE_Secure (0x1UL) /*!< Only secure access to region is allowed */ + +/* WRITEONCE @Bit 12 : Write-once */ + #define UICR_BOOTCONF_WRITEONCE_Pos (12UL) /*!< Position of WRITEONCE field. */ + #define UICR_BOOTCONF_WRITEONCE_Msk (0x1UL << UICR_BOOTCONF_WRITEONCE_Pos) /*!< Bit mask of WRITEONCE field. */ + #define UICR_BOOTCONF_WRITEONCE_Min (0x0UL) /*!< Min enumerator value of WRITEONCE field. */ + #define UICR_BOOTCONF_WRITEONCE_Max (0x1UL) /*!< Max enumerator value of WRITEONCE field. */ + #define UICR_BOOTCONF_WRITEONCE_Disabled (0x0UL) /*!< Write-once disabled */ + #define UICR_BOOTCONF_WRITEONCE_Enabled (0x1UL) /*!< Write-once enabled */ + +/* LOCK @Bit 13 : Enable lock of configuration register */ + #define UICR_BOOTCONF_LOCK_Pos (13UL) /*!< Position of LOCK field. */ + #define UICR_BOOTCONF_LOCK_Msk (0x1UL << UICR_BOOTCONF_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define UICR_BOOTCONF_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define UICR_BOOTCONF_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define UICR_BOOTCONF_LOCK_Disabled (0x0UL) /*!< Lock is disabled, and the RRAMC region configuration registers for the + immutable boot region are writable.*/ + #define UICR_BOOTCONF_LOCK_Enabled (0x1UL) /*!< Lock is enabled, and the RRAMC configuration registers for the + immutable boot region are read-only.*/ + +/* SIZE @Bits 16..22 : Immutable boot region size */ + #define UICR_BOOTCONF_SIZE_Pos (16UL) /*!< Position of SIZE field. */ + #define UICR_BOOTCONF_SIZE_Msk (0x7FUL << UICR_BOOTCONF_SIZE_Pos) /*!< Bit mask of SIZE field. */ + + +/* UICR_OTP: One time programmable memory */ + #define UICR_OTP_MaxCount (320UL) /*!< Max size of OTP[320] array. */ + #define UICR_OTP_MaxIndex (319UL) /*!< Max index of OTP[320] array. */ + #define UICR_OTP_MinIndex (0UL) /*!< Min index of OTP[320] array. */ + #define UICR_OTP_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OTP[320] register. */ + +/* OTP @Bits 0..31 : OTP word */ + #define UICR_OTP_OTP_Pos (0UL) /*!< Position of OTP field. */ + #define UICR_OTP_OTP_Msk (0xFFFFFFFFUL << UICR_OTP_OTP_Pos) /*!< Bit mask of OTP field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ USBHS ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ==================================================== Struct USBHS_PHY ===================================================== */ +/** + * @brief PHY [USBHS_PHY] (unspecified) + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) USB PHY parameter overrides */ + __IOM uint32_t CLOCK; /*!< (@ 0x00000004) USB PHY clock configurations */ + __IOM uint32_t BATTCHRG; /*!< (@ 0x00000008) Battery Charging Configuration */ + __IM uint32_t BATTCHRGSTATUS; /*!< (@ 0x0000000C) Battery charger input signals */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t INPUTOVERRIDE; /*!< (@ 0x00000018) Enables overriding of individual signals to the PHY, + the override values are set in PHY.OVERRIDEVALUES*/ + __IOM uint32_t OVERRIDEVALUES; /*!< (@ 0x0000001C) Values that are used to override the input signals to + the PHY.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t RTUNE; /*!< (@ 0x00000024) The RTUNE mode is an alternative method for calibrating + the DP and DM 45-Ohm source impedance.*/ +} NRF_USBHS_PHY_Type; /*!< Size = 40 (0x028) */ + +/* USBHS_PHY_CONFIG: USB PHY parameter overrides */ + #define USBHS_PHY_CONFIG_ResetValue (0x5533D6F0UL) /*!< Reset value of CONFIG register. */ + +/* PLLITUNE @Bits 0..1 : PLL Integral Path Tune */ + #define USBHS_PHY_CONFIG_PLLITUNE_Pos (0UL) /*!< Position of PLLITUNE field. */ + #define USBHS_PHY_CONFIG_PLLITUNE_Msk (0x3UL << USBHS_PHY_CONFIG_PLLITUNE_Pos) /*!< Bit mask of PLLITUNE field. */ + #define USBHS_PHY_CONFIG_PLLITUNE_Min (0x0UL) /*!< Min value of PLLITUNE field. */ + #define USBHS_PHY_CONFIG_PLLITUNE_Max (0x3UL) /*!< Max size of PLLITUNE field. */ + +/* PLLPTUNE @Bits 2..5 : PLL Proportional Path Tune */ + #define USBHS_PHY_CONFIG_PLLPTUNE_Pos (2UL) /*!< Position of PLLPTUNE field. */ + #define USBHS_PHY_CONFIG_PLLPTUNE_Msk (0xFUL << USBHS_PHY_CONFIG_PLLPTUNE_Pos) /*!< Bit mask of PLLPTUNE field. */ + #define USBHS_PHY_CONFIG_PLLPTUNE_Min (0x0UL) /*!< Min value of PLLPTUNE field. */ + #define USBHS_PHY_CONFIG_PLLPTUNE_Max (0xFUL) /*!< Max size of PLLPTUNE field. */ + +/* COMPDISTUNE0 @Bits 6..8 : Disconnect Threshold Adjustment */ + #define USBHS_PHY_CONFIG_COMPDISTUNE0_Pos (6UL) /*!< Position of COMPDISTUNE0 field. */ + #define USBHS_PHY_CONFIG_COMPDISTUNE0_Msk (0x7UL << USBHS_PHY_CONFIG_COMPDISTUNE0_Pos) /*!< Bit mask of COMPDISTUNE0 field. */ + #define USBHS_PHY_CONFIG_COMPDISTUNE0_Min (0x0UL) /*!< Min value of COMPDISTUNE0 field. */ + #define USBHS_PHY_CONFIG_COMPDISTUNE0_Max (0x7UL) /*!< Max size of COMPDISTUNE0 field. */ + +/* SQRXTUNE0 @Bits 9..11 : Squelch Threshold Adjustment */ + #define USBHS_PHY_CONFIG_SQRXTUNE0_Pos (9UL) /*!< Position of SQRXTUNE0 field. */ + #define USBHS_PHY_CONFIG_SQRXTUNE0_Msk (0x7UL << USBHS_PHY_CONFIG_SQRXTUNE0_Pos) /*!< Bit mask of SQRXTUNE0 field. */ + #define USBHS_PHY_CONFIG_SQRXTUNE0_Min (0x0UL) /*!< Min value of SQRXTUNE0 field. */ + #define USBHS_PHY_CONFIG_SQRXTUNE0_Max (0x3UL) /*!< Max size of SQRXTUNE0 field. */ + +/* VDATREFTUNE0 @Bits 12..13 : Data Detect Voltage Adjustment */ + #define USBHS_PHY_CONFIG_VDATREFTUNE0_Pos (12UL) /*!< Position of VDATREFTUNE0 field. */ + #define USBHS_PHY_CONFIG_VDATREFTUNE0_Msk (0x3UL << USBHS_PHY_CONFIG_VDATREFTUNE0_Pos) /*!< Bit mask of VDATREFTUNE0 field. */ + #define USBHS_PHY_CONFIG_VDATREFTUNE0_Min (0x0UL) /*!< Min value of VDATREFTUNE0 field. */ + #define USBHS_PHY_CONFIG_VDATREFTUNE0_Max (0x3UL) /*!< Max size of VDATREFTUNE0 field. */ + +/* TXHSXVTUNE0 @Bits 14..15 : Transmitter High-Speed Crossover Adjustment */ + #define USBHS_PHY_CONFIG_TXHSXVTUNE0_Pos (14UL) /*!< Position of TXHSXVTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXHSXVTUNE0_Msk (0x3UL << USBHS_PHY_CONFIG_TXHSXVTUNE0_Pos) /*!< Bit mask of TXHSXVTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXHSXVTUNE0_Min (0x0UL) /*!< Min value of TXHSXVTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXHSXVTUNE0_Max (0x2UL) /*!< Max size of TXHSXVTUNE0 field. */ + +/* TXFSLSTUNE0 @Bits 16..19 : FS/LS Source Impedance Adjustment */ + #define USBHS_PHY_CONFIG_TXFSLSTUNE0_Pos (16UL) /*!< Position of TXFSLSTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXFSLSTUNE0_Msk (0xFUL << USBHS_PHY_CONFIG_TXFSLSTUNE0_Pos) /*!< Bit mask of TXFSLSTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXFSLSTUNE0_Min (0x0UL) /*!< Min value of TXFSLSTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXFSLSTUNE0_Max (0x7UL) /*!< Max size of TXFSLSTUNE0 field. */ + +/* TXVREFTUNE0 @Bits 20..23 : HS DC Voltage Level Adjustment */ + #define USBHS_PHY_CONFIG_TXVREFTUNE0_Pos (20UL) /*!< Position of TXVREFTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXVREFTUNE0_Msk (0xFUL << USBHS_PHY_CONFIG_TXVREFTUNE0_Pos) /*!< Bit mask of TXVREFTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXVREFTUNE0_Min (0x0UL) /*!< Min value of TXVREFTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXVREFTUNE0_Max (0x7UL) /*!< Max size of TXVREFTUNE0 field. */ + +/* TXRISETUNE0 @Bits 24..25 : HS Transmitter Rise/Fall Time Adjustment */ + #define USBHS_PHY_CONFIG_TXRISETUNE0_Pos (24UL) /*!< Position of TXRISETUNE0 field. */ + #define USBHS_PHY_CONFIG_TXRISETUNE0_Msk (0x3UL << USBHS_PHY_CONFIG_TXRISETUNE0_Pos) /*!< Bit mask of TXRISETUNE0 field. */ + #define USBHS_PHY_CONFIG_TXRISETUNE0_Min (0x0UL) /*!< Min value of TXRISETUNE0 field. */ + #define USBHS_PHY_CONFIG_TXRISETUNE0_Max (0x2UL) /*!< Max size of TXRISETUNE0 field. */ + +/* TXRESTUNE0 @Bits 26..27 : USB Source Impedance Adjustment */ + #define USBHS_PHY_CONFIG_TXRESTUNE0_Pos (26UL) /*!< Position of TXRESTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXRESTUNE0_Msk (0x3UL << USBHS_PHY_CONFIG_TXRESTUNE0_Pos) /*!< Bit mask of TXRESTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXRESTUNE0_Min (0x0UL) /*!< Min value of TXRESTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXRESTUNE0_Max (0x2UL) /*!< Max size of TXRESTUNE0 field. */ + +/* TXPREEMPAMPTUNE0 @Bits 28..29 : HS Transmitter Pre-Emphasis Current Control */ + #define USBHS_PHY_CONFIG_TXPREEMPAMPTUNE0_Pos (28UL) /*!< Position of TXPREEMPAMPTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXPREEMPAMPTUNE0_Msk (0x3UL << USBHS_PHY_CONFIG_TXPREEMPAMPTUNE0_Pos) /*!< Bit mask of + TXPREEMPAMPTUNE0 field.*/ + #define USBHS_PHY_CONFIG_TXPREEMPAMPTUNE0_Min (0x0UL) /*!< Min value of TXPREEMPAMPTUNE0 field. */ + #define USBHS_PHY_CONFIG_TXPREEMPAMPTUNE0_Max (0x2UL) /*!< Max size of TXPREEMPAMPTUNE0 field. */ + +/* TXPREEMPPULSETUNE0 @Bit 30 : HS Transmitter Pre-Emphasis Duration Control */ + #define USBHS_PHY_CONFIG_TXPREEMPPULSETUNE0_Pos (30UL) /*!< Position of TXPREEMPPULSETUNE0 field. */ + #define USBHS_PHY_CONFIG_TXPREEMPPULSETUNE0_Msk (0x1UL << USBHS_PHY_CONFIG_TXPREEMPPULSETUNE0_Pos) /*!< Bit mask of + TXPREEMPPULSETUNE0 field.*/ + #define USBHS_PHY_CONFIG_TXPREEMPPULSETUNE0_Min (0x0UL) /*!< Min value of TXPREEMPPULSETUNE0 field. */ + #define USBHS_PHY_CONFIG_TXPREEMPPULSETUNE0_Max (0x1UL) /*!< Max size of TXPREEMPPULSETUNE0 field. */ + + +/* USBHS_PHY_CLOCK: USB PHY clock configurations */ + #define USBHS_PHY_CLOCK_ResetValue (0x0000001AUL) /*!< Reset value of CLOCK register. */ + +/* FSEL @Bits 0..2 : Select reference clock frequency */ + #define USBHS_PHY_CLOCK_FSEL_Pos (0UL) /*!< Position of FSEL field. */ + #define USBHS_PHY_CLOCK_FSEL_Msk (0x7UL << USBHS_PHY_CLOCK_FSEL_Pos) /*!< Bit mask of FSEL field. */ + #define USBHS_PHY_CLOCK_FSEL_Min (0x0UL) /*!< Min enumerator value of FSEL field. */ + #define USBHS_PHY_CLOCK_FSEL_Max (0x7UL) /*!< Max enumerator value of FSEL field. */ + #define USBHS_PHY_CLOCK_FSEL_Clock19200KHz (0x0UL) /*!< Reference clock is 19.2MHz. */ + #define USBHS_PHY_CLOCK_FSEL_Clock20000KHz (0x1UL) /*!< Reference clock is 20MHz. */ + #define USBHS_PHY_CLOCK_FSEL_Clock24000KHz (0x2UL) /*!< Reference clock is 24MHz. */ + #define USBHS_PHY_CLOCK_FSEL_Clock50000KHz (0x7UL) /*!< Reference clock is 50MHz. */ + +/* PLLBTUNE @Bit 3 : PLL bandwidth adjustment */ + #define USBHS_PHY_CLOCK_PLLBTUNE_Pos (3UL) /*!< Position of PLLBTUNE field. */ + #define USBHS_PHY_CLOCK_PLLBTUNE_Msk (0x1UL << USBHS_PHY_CLOCK_PLLBTUNE_Pos) /*!< Bit mask of PLLBTUNE field. */ + #define USBHS_PHY_CLOCK_PLLBTUNE_Min (0x0UL) /*!< Min enumerator value of PLLBTUNE field. */ + #define USBHS_PHY_CLOCK_PLLBTUNE_Max (0x1UL) /*!< Max enumerator value of PLLBTUNE field. */ + #define USBHS_PHY_CLOCK_PLLBTUNE_Disabled (0x0UL) /*!< PLL bandwidth adjustment disabled. */ + #define USBHS_PHY_CLOCK_PLLBTUNE_Enabled (0x1UL) /*!< PLL bandwidth adjustment enabled. */ + +/* COMMONONN @Bit 4 : Common block power down control */ + #define USBHS_PHY_CLOCK_COMMONONN_Pos (4UL) /*!< Position of COMMONONN field. */ + #define USBHS_PHY_CLOCK_COMMONONN_Msk (0x1UL << USBHS_PHY_CLOCK_COMMONONN_Pos) /*!< Bit mask of COMMONONN field. */ + #define USBHS_PHY_CLOCK_COMMONONN_Min (0x0UL) /*!< Min enumerator value of COMMONONN field. */ + #define USBHS_PHY_CLOCK_COMMONONN_Max (0x1UL) /*!< Max enumerator value of COMMONONN field. */ + #define USBHS_PHY_CLOCK_COMMONONN_POWERED (0x0UL) /*!< The REFCLOCK_LOGIC,bias and PLL blocks are powered in sleep or suspend + mode.*/ + #define USBHS_PHY_CLOCK_COMMONONN_SUSPEND (0x1UL) /*!< The REFCLOCK_LOGIC, bias and PLL blocks are powered down in suspend + mode and bias and PLL blocks are powered down in sleep mode.*/ + + +/* USBHS_PHY_BATTCHRG: Battery Charging Configuration */ + #define USBHS_PHY_BATTCHRG_ResetValue (0x00000000UL) /*!< Reset value of BATTCHRG register. */ + +/* CHRGSEL0 @Bit 0 : Battery charging source select */ + #define USBHS_PHY_BATTCHRG_CHRGSEL0_Pos (0UL) /*!< Position of CHRGSEL0 field. */ + #define USBHS_PHY_BATTCHRG_CHRGSEL0_Msk (0x1UL << USBHS_PHY_BATTCHRG_CHRGSEL0_Pos) /*!< Bit mask of CHRGSEL0 field. */ + #define USBHS_PHY_BATTCHRG_CHRGSEL0_Min (0x0UL) /*!< Min enumerator value of CHRGSEL0 field. */ + #define USBHS_PHY_BATTCHRG_CHRGSEL0_Max (0x1UL) /*!< Max enumerator value of CHRGSEL0 field. */ + #define USBHS_PHY_BATTCHRG_CHRGSEL0_SourceDP0SinkDM0 (0x0UL) /*!< Data source voltage (VDAT_SRC) is sourced onto DP0 and sunk + from DM0*/ + #define USBHS_PHY_BATTCHRG_CHRGSEL0_SourceDM0SinkDP0 (0x1UL) /*!< Data source voltage (VDAT_SRC) is sourced onto DM0 and sunk + from DP0*/ + +/* VDATENB0 @Bit 1 : Attach/Connect Detection Enable */ + #define USBHS_PHY_BATTCHRG_VDATENB0_Pos (1UL) /*!< Position of VDATENB0 field. */ + #define USBHS_PHY_BATTCHRG_VDATENB0_Msk (0x1UL << USBHS_PHY_BATTCHRG_VDATENB0_Pos) /*!< Bit mask of VDATENB0 field. */ + #define USBHS_PHY_BATTCHRG_VDATENB0_Min (0x0UL) /*!< Min enumerator value of VDATENB0 field. */ + #define USBHS_PHY_BATTCHRG_VDATENB0_Max (0x1UL) /*!< Max enumerator value of VDATENB0 field. */ + #define USBHS_PHY_BATTCHRG_VDATENB0_Disabled (0x0UL) /*!< Data detect voltage (CHG_DET) is disabled */ + #define USBHS_PHY_BATTCHRG_VDATENB0_Enabled (0x1UL) /*!< Data detect voltage (CHG_DET) is enabled */ + +/* VDATSRCENB0 @Bit 2 : Battery Charging Source Select */ + #define USBHS_PHY_BATTCHRG_VDATSRCENB0_Pos (2UL) /*!< Position of VDATSRCENB0 field. */ + #define USBHS_PHY_BATTCHRG_VDATSRCENB0_Msk (0x1UL << USBHS_PHY_BATTCHRG_VDATSRCENB0_Pos) /*!< Bit mask of VDATSRCENB0 field. */ + #define USBHS_PHY_BATTCHRG_VDATSRCENB0_Min (0x0UL) /*!< Min enumerator value of VDATSRCENB0 field. */ + #define USBHS_PHY_BATTCHRG_VDATSRCENB0_Max (0x1UL) /*!< Max enumerator value of VDATSRCENB0 field. */ + #define USBHS_PHY_BATTCHRG_VDATSRCENB0_Disabled (0x0UL) /*!< Data source voltage (VDAT_SRC) is disabled */ + #define USBHS_PHY_BATTCHRG_VDATSRCENB0_Enabled (0x1UL) /*!< Data source voltage (VDAT_SRC) is enabled */ + + +/* USBHS_PHY_BATTCHRGSTATUS: Battery charger input signals */ + #define USBHS_PHY_BATTCHRGSTATUS_ResetValue (0x00000000UL) /*!< Reset value of BATTCHRGSTATUS register. */ + +/* CHGDET @Bit 1 : (unspecified) */ + #define USBHS_PHY_BATTCHRGSTATUS_CHGDET_Pos (1UL) /*!< Position of CHGDET field. */ + #define USBHS_PHY_BATTCHRGSTATUS_CHGDET_Msk (0x1UL << USBHS_PHY_BATTCHRGSTATUS_CHGDET_Pos) /*!< Bit mask of CHGDET field. */ + +/* FSVPLUS @Bit 2 : (unspecified) */ + #define USBHS_PHY_BATTCHRGSTATUS_FSVPLUS_Pos (2UL) /*!< Position of FSVPLUS field. */ + #define USBHS_PHY_BATTCHRGSTATUS_FSVPLUS_Msk (0x1UL << USBHS_PHY_BATTCHRGSTATUS_FSVPLUS_Pos) /*!< Bit mask of FSVPLUS field. */ + +/* FSVMINUS @Bit 3 : (unspecified) */ + #define USBHS_PHY_BATTCHRGSTATUS_FSVMINUS_Pos (3UL) /*!< Position of FSVMINUS field. */ + #define USBHS_PHY_BATTCHRGSTATUS_FSVMINUS_Msk (0x1UL << USBHS_PHY_BATTCHRGSTATUS_FSVMINUS_Pos) /*!< Bit mask of FSVMINUS + field.*/ + + +/* USBHS_PHY_INPUTOVERRIDE: Enables overriding of individual signals to the PHY, the override values are set in + PHY.OVERRIDEVALUES */ + + #define USBHS_PHY_INPUTOVERRIDE_ResetValue (0x00000000UL) /*!< Reset value of INPUTOVERRIDE register. */ + +/* OPMODE0 @Bits 18..19 : (unspecified) */ + #define USBHS_PHY_INPUTOVERRIDE_OPMODE0_Pos (18UL) /*!< Position of OPMODE0 field. */ + #define USBHS_PHY_INPUTOVERRIDE_OPMODE0_Msk (0x3UL << USBHS_PHY_INPUTOVERRIDE_OPMODE0_Pos) /*!< Bit mask of OPMODE0 field. */ + #define USBHS_PHY_INPUTOVERRIDE_OPMODE0_Min (0x0UL) /*!< Min enumerator value of OPMODE0 field. */ + #define USBHS_PHY_INPUTOVERRIDE_OPMODE0_Max (0x3UL) /*!< Max enumerator value of OPMODE0 field. */ + #define USBHS_PHY_INPUTOVERRIDE_OPMODE0_Disabled (0x0UL) /*!< Overrides are disabled */ + #define USBHS_PHY_INPUTOVERRIDE_OPMODE0_Enabled (0x3UL) /*!< Overrides are enabled */ + +/* XCVRSEL0 @Bits 20..21 : (unspecified) */ + #define USBHS_PHY_INPUTOVERRIDE_XCVRSEL0_Pos (20UL) /*!< Position of XCVRSEL0 field. */ + #define USBHS_PHY_INPUTOVERRIDE_XCVRSEL0_Msk (0x3UL << USBHS_PHY_INPUTOVERRIDE_XCVRSEL0_Pos) /*!< Bit mask of XCVRSEL0 field.*/ + #define USBHS_PHY_INPUTOVERRIDE_XCVRSEL0_Min (0x0UL) /*!< Min enumerator value of XCVRSEL0 field. */ + #define USBHS_PHY_INPUTOVERRIDE_XCVRSEL0_Max (0x3UL) /*!< Max enumerator value of XCVRSEL0 field. */ + #define USBHS_PHY_INPUTOVERRIDE_XCVRSEL0_Disabled (0x0UL) /*!< Overrides are disabled */ + #define USBHS_PHY_INPUTOVERRIDE_XCVRSEL0_Enabled (0x3UL) /*!< Overrides are enabled */ + +/* DPPULLDOWN @Bit 23 : (unspecified) */ + #define USBHS_PHY_INPUTOVERRIDE_DPPULLDOWN_Pos (23UL) /*!< Position of DPPULLDOWN field. */ + #define USBHS_PHY_INPUTOVERRIDE_DPPULLDOWN_Msk (0x1UL << USBHS_PHY_INPUTOVERRIDE_DPPULLDOWN_Pos) /*!< Bit mask of DPPULLDOWN + field.*/ + +/* DMPULLDOWN @Bit 24 : (unspecified) */ + #define USBHS_PHY_INPUTOVERRIDE_DMPULLDOWN_Pos (24UL) /*!< Position of DMPULLDOWN field. */ + #define USBHS_PHY_INPUTOVERRIDE_DMPULLDOWN_Msk (0x1UL << USBHS_PHY_INPUTOVERRIDE_DMPULLDOWN_Pos) /*!< Bit mask of DMPULLDOWN + field.*/ + +/* SUSPENDM0 @Bit 25 : (unspecified) */ + #define USBHS_PHY_INPUTOVERRIDE_SUSPENDM0_Pos (25UL) /*!< Position of SUSPENDM0 field. */ + #define USBHS_PHY_INPUTOVERRIDE_SUSPENDM0_Msk (0x1UL << USBHS_PHY_INPUTOVERRIDE_SUSPENDM0_Pos) /*!< Bit mask of SUSPENDM0 + field.*/ + +/* VBUSVALID @Bit 30 : (unspecified) */ + #define USBHS_PHY_INPUTOVERRIDE_VBUSVALID_Pos (30UL) /*!< Position of VBUSVALID field. */ + #define USBHS_PHY_INPUTOVERRIDE_VBUSVALID_Msk (0x1UL << USBHS_PHY_INPUTOVERRIDE_VBUSVALID_Pos) /*!< Bit mask of VBUSVALID + field.*/ + +/* ID @Bit 31 : Overrides OTG ID pin signal */ + #define USBHS_PHY_INPUTOVERRIDE_ID_Pos (31UL) /*!< Position of ID field. */ + #define USBHS_PHY_INPUTOVERRIDE_ID_Msk (0x1UL << USBHS_PHY_INPUTOVERRIDE_ID_Pos) /*!< Bit mask of ID field. */ + + +/* USBHS_PHY_OVERRIDEVALUES: Values that are used to override the input signals to the PHY. */ + #define USBHS_PHY_OVERRIDEVALUES_ResetValue (0x02000000UL) /*!< Reset value of OVERRIDEVALUES register. */ + +/* OPMODE0 @Bits 18..19 : (unspecified) */ + #define USBHS_PHY_OVERRIDEVALUES_OPMODE0_Pos (18UL) /*!< Position of OPMODE0 field. */ + #define USBHS_PHY_OVERRIDEVALUES_OPMODE0_Msk (0x3UL << USBHS_PHY_OVERRIDEVALUES_OPMODE0_Pos) /*!< Bit mask of OPMODE0 field. */ + +/* XCVRSEL0 @Bits 20..21 : (unspecified) */ + #define USBHS_PHY_OVERRIDEVALUES_XCVRSEL0_Pos (20UL) /*!< Position of XCVRSEL0 field. */ + #define USBHS_PHY_OVERRIDEVALUES_XCVRSEL0_Msk (0x3UL << USBHS_PHY_OVERRIDEVALUES_XCVRSEL0_Pos) /*!< Bit mask of XCVRSEL0 + field.*/ + +/* DPPULLDOWN @Bit 23 : This field controls the pull-down resistor on D+ */ + #define USBHS_PHY_OVERRIDEVALUES_DPPULLDOWN_Pos (23UL) /*!< Position of DPPULLDOWN field. */ + #define USBHS_PHY_OVERRIDEVALUES_DPPULLDOWN_Msk (0x1UL << USBHS_PHY_OVERRIDEVALUES_DPPULLDOWN_Pos) /*!< Bit mask of DPPULLDOWN + field.*/ + #define USBHS_PHY_OVERRIDEVALUES_DPPULLDOWN_Min (0x0UL) /*!< Min enumerator value of DPPULLDOWN field. */ + #define USBHS_PHY_OVERRIDEVALUES_DPPULLDOWN_Max (0x1UL) /*!< Max enumerator value of DPPULLDOWN field. */ + #define USBHS_PHY_OVERRIDEVALUES_DPPULLDOWN_Enable (0x1UL) /*!< The pull-down resistor on D+ is enabled */ + #define USBHS_PHY_OVERRIDEVALUES_DPPULLDOWN_Disable (0x0UL) /*!< The pull-down resistor on D+ is disabled */ + +/* DMPULLDOWN @Bit 24 : This field controls the pull-down resistor on D- */ + #define USBHS_PHY_OVERRIDEVALUES_DMPULLDOWN_Pos (24UL) /*!< Position of DMPULLDOWN field. */ + #define USBHS_PHY_OVERRIDEVALUES_DMPULLDOWN_Msk (0x1UL << USBHS_PHY_OVERRIDEVALUES_DMPULLDOWN_Pos) /*!< Bit mask of DMPULLDOWN + field.*/ + #define USBHS_PHY_OVERRIDEVALUES_DMPULLDOWN_Min (0x0UL) /*!< Min enumerator value of DMPULLDOWN field. */ + #define USBHS_PHY_OVERRIDEVALUES_DMPULLDOWN_Max (0x1UL) /*!< Max enumerator value of DMPULLDOWN field. */ + #define USBHS_PHY_OVERRIDEVALUES_DMPULLDOWN_Enable (0x1UL) /*!< The pull-down resistor on D- is enabled */ + #define USBHS_PHY_OVERRIDEVALUES_DMPULLDOWN_Disable (0x0UL) /*!< The pull-down resistor on D- is disabled */ + +/* SUSPENDM0 @Bit 25 : (unspecified) */ + #define USBHS_PHY_OVERRIDEVALUES_SUSPENDM0_Pos (25UL) /*!< Position of SUSPENDM0 field. */ + #define USBHS_PHY_OVERRIDEVALUES_SUSPENDM0_Msk (0x1UL << USBHS_PHY_OVERRIDEVALUES_SUSPENDM0_Pos) /*!< Bit mask of SUSPENDM0 + field.*/ + +/* VBUSVALID @Bit 30 : Signals to the PHY that VBUS is valid, and enables the pull-up resistor on D+ */ + #define USBHS_PHY_OVERRIDEVALUES_VBUSVALID_Pos (30UL) /*!< Position of VBUSVALID field. */ + #define USBHS_PHY_OVERRIDEVALUES_VBUSVALID_Msk (0x1UL << USBHS_PHY_OVERRIDEVALUES_VBUSVALID_Pos) /*!< Bit mask of VBUSVALID + field.*/ + #define USBHS_PHY_OVERRIDEVALUES_VBUSVALID_Min (0x0UL) /*!< Min enumerator value of VBUSVALID field. */ + #define USBHS_PHY_OVERRIDEVALUES_VBUSVALID_Max (0x1UL) /*!< Max enumerator value of VBUSVALID field. */ + #define USBHS_PHY_OVERRIDEVALUES_VBUSVALID_Valid (0x1UL) /*!< VBUS is valid, and the pull-up resistor on D+ is enabled */ + #define USBHS_PHY_OVERRIDEVALUES_VBUSVALID_NotValid (0x0UL) /*!< VBUS is not valid, and the pull-up resistor on D+ is + disabled.*/ + +/* ID @Bit 31 : Overrides OTG ID pin signal */ + #define USBHS_PHY_OVERRIDEVALUES_ID_Pos (31UL) /*!< Position of ID field. */ + #define USBHS_PHY_OVERRIDEVALUES_ID_Msk (0x1UL << USBHS_PHY_OVERRIDEVALUES_ID_Pos) /*!< Bit mask of ID field. */ + #define USBHS_PHY_OVERRIDEVALUES_ID_Min (0x0UL) /*!< Min enumerator value of ID field. */ + #define USBHS_PHY_OVERRIDEVALUES_ID_Max (0x1UL) /*!< Max enumerator value of ID field. */ + #define USBHS_PHY_OVERRIDEVALUES_ID_Device (0x1UL) /*!< Role is Device */ + #define USBHS_PHY_OVERRIDEVALUES_ID_Host (0x0UL) /*!< Role is Host. */ + + +/* USBHS_PHY_RTUNE: The RTUNE mode is an alternative method for calibrating the DP and DM 45-Ohm source impedance. */ + #define USBHS_PHY_RTUNE_ResetValue (0x0000000FUL) /*!< Reset value of RTUNE register. */ + +/* RTUNESEL @Bit 0 : This signal selects the tuning method for the high-speed DP and DM source impedance of the USBHS. */ + #define USBHS_PHY_RTUNE_RTUNESEL_Pos (0UL) /*!< Position of RTUNESEL field. */ + #define USBHS_PHY_RTUNE_RTUNESEL_Msk (0x1UL << USBHS_PHY_RTUNE_RTUNESEL_Pos) /*!< Bit mask of RTUNESEL field. */ + #define USBHS_PHY_RTUNE_RTUNESEL_Min (0x0UL) /*!< Min enumerator value of RTUNESEL field. */ + #define USBHS_PHY_RTUNE_RTUNESEL_Max (0x1UL) /*!< Max enumerator value of RTUNESEL field. */ + #define USBHS_PHY_RTUNE_RTUNESEL_TXRTUNE (0x1UL) /*!< The TXRTUNE pin, external resistor REXT, and resulting internal + digital calibration code are used for tuning the high-speed source + impedance.*/ + #define USBHS_PHY_RTUNE_RTUNESEL_RTUNE (0x0UL) /*!< The RCALCODE value is used for tuning the high-speed source + impedance.*/ + +/* RCALCODE @Bits 1..4 : This signal is used to tune the internal 200 ohm resistor or the USBHS DP and DM high-speed source + impedance. */ + + #define USBHS_PHY_RTUNE_RCALCODE_Pos (1UL) /*!< Position of RCALCODE field. */ + #define USBHS_PHY_RTUNE_RCALCODE_Msk (0xFUL << USBHS_PHY_RTUNE_RCALCODE_Pos) /*!< Bit mask of RCALCODE field. */ + + +/* ====================================================== Struct USBHS ======================================================= */ +/** + * @brief USBHS + */ + typedef struct { /*!< USBHS Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the USB peripheral. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the USB peripheral */ + __IM uint32_t RESERVED[94]; + __IOM uint32_t PUBLISH_SOF; /*!< (@ 0x00000180) Publish configuration for SOF event. */ + __IM uint32_t RESERVED1[159]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000400) Enable USB peripheral. */ + __IM uint32_t RESERVED2[15]; + __IOM NRF_USBHS_PHY_Type PHY; /*!< (@ 0x00000440) (unspecified) */ + } NRF_USBHS_Type; /*!< Size = 1128 (0x468) */ + +/* USBHS_TASKS_START: Start the USB peripheral. */ + #define USBHS_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start the USB peripheral. */ + #define USBHS_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define USBHS_TASKS_START_TASKS_START_Msk (0x1UL << USBHS_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define USBHS_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define USBHS_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define USBHS_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* USBHS_TASKS_STOP: Stop the USB peripheral */ + #define USBHS_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop the USB peripheral */ + #define USBHS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define USBHS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << USBHS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define USBHS_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define USBHS_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define USBHS_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* USBHS_PUBLISH_SOF: Publish configuration for SOF event. */ + #define USBHS_PUBLISH_SOF_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SOF register. */ + +/* CHIDX @Bits 0..7 : DPPI channel to publish to */ + #define USBHS_PUBLISH_SOF_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define USBHS_PUBLISH_SOF_CHIDX_Msk (0xFFUL << USBHS_PUBLISH_SOF_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define USBHS_PUBLISH_SOF_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define USBHS_PUBLISH_SOF_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : Enable publishing of SOF event */ + #define USBHS_PUBLISH_SOF_EN_Pos (31UL) /*!< Position of EN field. */ + #define USBHS_PUBLISH_SOF_EN_Msk (0x1UL << USBHS_PUBLISH_SOF_EN_Pos) /*!< Bit mask of EN field. */ + #define USBHS_PUBLISH_SOF_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define USBHS_PUBLISH_SOF_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define USBHS_PUBLISH_SOF_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define USBHS_PUBLISH_SOF_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* USBHS_ENABLE: Enable USB peripheral. */ + #define USBHS_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* CORE @Bit 0 : Enable USB Controller */ + #define USBHS_ENABLE_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define USBHS_ENABLE_CORE_Msk (0x1UL << USBHS_ENABLE_CORE_Pos) /*!< Bit mask of CORE field. */ + #define USBHS_ENABLE_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define USBHS_ENABLE_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define USBHS_ENABLE_CORE_Disabled (0x0UL) /*!< USB Controller disabled. */ + #define USBHS_ENABLE_CORE_Enabled (0x1UL) /*!< USB Controller enabled. */ + +/* PHY @Bit 1 : Enable USB PHY */ + #define USBHS_ENABLE_PHY_Pos (1UL) /*!< Position of PHY field. */ + #define USBHS_ENABLE_PHY_Msk (0x1UL << USBHS_ENABLE_PHY_Pos) /*!< Bit mask of PHY field. */ + #define USBHS_ENABLE_PHY_Min (0x0UL) /*!< Min enumerator value of PHY field. */ + #define USBHS_ENABLE_PHY_Max (0x1UL) /*!< Max enumerator value of PHY field. */ + #define USBHS_ENABLE_PHY_Disabled (0x0UL) /*!< USB PHY disabled. */ + #define USBHS_ENABLE_PHY_Enabled (0x1UL) /*!< USB PHY enabled. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ USBHSCORE ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =================================================== Struct USBHSCORE_HC =================================================== */ +/** + * @brief HC [USBHSCORE_HC] (unspecified) + */ +typedef struct { + __IOM uint32_t CHAR; /*!< (@ 0x00000000) Host Channel Characteristics Register 0 */ + __IOM uint32_t SPLT; /*!< (@ 0x00000004) Host Channel Split Control Register 0 */ + __IOM uint32_t INT; /*!< (@ 0x00000008) Host Channel Interrupt Register 0 */ + __IOM uint32_t INTMSK; /*!< (@ 0x0000000C) Host Channel Interrupt Mask Register 0 */ + __IOM uint32_t TSIZ; /*!< (@ 0x00000010) Host Channel Transfer Size Register 0 */ + __IOM uint32_t DMA; /*!< (@ 0x00000014) Host Channel DMA Address Register 0 */ +} NRF_USBHSCORE_HC_Type; /*!< Size = 24 (0x018) */ + #define USBHSCORE_HC_MaxCount (16UL) /*!< Size of HC[16] array. */ + #define USBHSCORE_HC_MaxIndex (15UL) /*!< Max index of HC[16] array. */ + #define USBHSCORE_HC_MinIndex (0UL) /*!< Min index of HC[16] array. */ + +/* USBHSCORE_HC_CHAR: Host Channel Characteristics Register 0 */ + #define USBHSCORE_HC_CHAR_ResetValue (0x00000000UL) /*!< Reset value of CHAR register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_HC_CHAR_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_HC_CHAR_MPS_Msk (0x7FFUL << USBHSCORE_HC_CHAR_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* EPNUM @Bits 11..14 : Endpoint Number (EPNum) */ + #define USBHSCORE_HC_CHAR_EPNUM_Pos (11UL) /*!< Position of EPNUM field. */ + #define USBHSCORE_HC_CHAR_EPNUM_Msk (0xFUL << USBHSCORE_HC_CHAR_EPNUM_Pos) /*!< Bit mask of EPNUM field. */ + #define USBHSCORE_HC_CHAR_EPNUM_Min (0x0UL) /*!< Min enumerator value of EPNUM field. */ + #define USBHSCORE_HC_CHAR_EPNUM_Max (0xFUL) /*!< Max enumerator value of EPNUM field. */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT0 (0x0UL) /*!< End point 0 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT1 (0x1UL) /*!< End point 1 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT2 (0x2UL) /*!< End point 2 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT3 (0x3UL) /*!< End point 3 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT4 (0x4UL) /*!< End point 4 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT5 (0x5UL) /*!< End point 5 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT6 (0x6UL) /*!< End point 6 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT7 (0x7UL) /*!< End point 7 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT8 (0x8UL) /*!< End point 8 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT9 (0x9UL) /*!< End point 9 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT10 (0xAUL) /*!< End point 10 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT11 (0xBUL) /*!< End point 11 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT12 (0xCUL) /*!< End point 12 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT13 (0xDUL) /*!< End point 13 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT14 (0xEUL) /*!< End point 14 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT15 (0xFUL) /*!< End point 15 */ + +/* EPDIR @Bit 15 : Endpoint Direction (EPDir) */ + #define USBHSCORE_HC_CHAR_EPDIR_Pos (15UL) /*!< Position of EPDIR field. */ + #define USBHSCORE_HC_CHAR_EPDIR_Msk (0x1UL << USBHSCORE_HC_CHAR_EPDIR_Pos) /*!< Bit mask of EPDIR field. */ + #define USBHSCORE_HC_CHAR_EPDIR_Min (0x0UL) /*!< Min enumerator value of EPDIR field. */ + #define USBHSCORE_HC_CHAR_EPDIR_Max (0x1UL) /*!< Max enumerator value of EPDIR field. */ + #define USBHSCORE_HC_CHAR_EPDIR_OUT (0x0UL) /*!< OUT Direction */ + #define USBHSCORE_HC_CHAR_EPDIR_IN (0x1UL) /*!< IN Direction */ + +/* LSPDDEV @Bit 17 : Low-Speed Device (LSpdDev) */ + #define USBHSCORE_HC_CHAR_LSPDDEV_Pos (17UL) /*!< Position of LSPDDEV field. */ + #define USBHSCORE_HC_CHAR_LSPDDEV_Msk (0x1UL << USBHSCORE_HC_CHAR_LSPDDEV_Pos) /*!< Bit mask of LSPDDEV field. */ + #define USBHSCORE_HC_CHAR_LSPDDEV_Min (0x0UL) /*!< Min enumerator value of LSPDDEV field. */ + #define USBHSCORE_HC_CHAR_LSPDDEV_Max (0x1UL) /*!< Max enumerator value of LSPDDEV field. */ + #define USBHSCORE_HC_CHAR_LSPDDEV_DISABLED (0x0UL) /*!< Not Communicating with low speed device */ + #define USBHSCORE_HC_CHAR_LSPDDEV_ENABLED (0x1UL) /*!< Communicating with low speed device */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_HC_CHAR_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_HC_CHAR_EPTYPE_Msk (0x3UL << USBHSCORE_HC_CHAR_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_HC_CHAR_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_HC_CHAR_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_HC_CHAR_EPTYPE_CTRL (0x0UL) /*!< Control */ + #define USBHSCORE_HC_CHAR_EPTYPE_ISOC (0x1UL) /*!< Isochronous */ + #define USBHSCORE_HC_CHAR_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_HC_CHAR_EPTYPE_INTERR (0x3UL) /*!< Interrupt */ + +/* EC @Bits 20..21 : Multi Count (MC) / Error Count (EC) */ + #define USBHSCORE_HC_CHAR_EC_Pos (20UL) /*!< Position of EC field. */ + #define USBHSCORE_HC_CHAR_EC_Msk (0x3UL << USBHSCORE_HC_CHAR_EC_Pos) /*!< Bit mask of EC field. */ + #define USBHSCORE_HC_CHAR_EC_Min (0x1UL) /*!< Min enumerator value of EC field. */ + #define USBHSCORE_HC_CHAR_EC_Max (0x3UL) /*!< Max enumerator value of EC field. */ + #define USBHSCORE_HC_CHAR_EC_TRANSONE (0x1UL) /*!< 1 transaction */ + #define USBHSCORE_HC_CHAR_EC_TRANSTWO (0x2UL) /*!< 2 transactions to be issued for this endpoint per microframe */ + #define USBHSCORE_HC_CHAR_EC_TRANSTHREE (0x3UL) /*!< 3 transactions to be issued for this endpoint per microframe */ + +/* DEVADDR @Bits 22..28 : Device Address (DevAddr) */ + #define USBHSCORE_HC_CHAR_DEVADDR_Pos (22UL) /*!< Position of DEVADDR field. */ + #define USBHSCORE_HC_CHAR_DEVADDR_Msk (0x7FUL << USBHSCORE_HC_CHAR_DEVADDR_Pos) /*!< Bit mask of DEVADDR field. */ + +/* ODDFRM @Bit 29 : Odd Frame (OddFrm) */ + #define USBHSCORE_HC_CHAR_ODDFRM_Pos (29UL) /*!< Position of ODDFRM field. */ + #define USBHSCORE_HC_CHAR_ODDFRM_Msk (0x1UL << USBHSCORE_HC_CHAR_ODDFRM_Pos) /*!< Bit mask of ODDFRM field. */ + #define USBHSCORE_HC_CHAR_ODDFRM_Min (0x0UL) /*!< Min enumerator value of ODDFRM field. */ + #define USBHSCORE_HC_CHAR_ODDFRM_Max (0x1UL) /*!< Max enumerator value of ODDFRM field. */ + #define USBHSCORE_HC_CHAR_ODDFRM_EFRAME (0x0UL) /*!< Even Frame Transfer */ + #define USBHSCORE_HC_CHAR_ODDFRM_OFRAME (0x1UL) /*!< Odd Frame Transfer */ + +/* CHDIS @Bit 30 : Channel Disable (ChDis) */ + #define USBHSCORE_HC_CHAR_CHDIS_Pos (30UL) /*!< Position of CHDIS field. */ + #define USBHSCORE_HC_CHAR_CHDIS_Msk (0x1UL << USBHSCORE_HC_CHAR_CHDIS_Pos) /*!< Bit mask of CHDIS field. */ + #define USBHSCORE_HC_CHAR_CHDIS_Min (0x0UL) /*!< Min enumerator value of CHDIS field. */ + #define USBHSCORE_HC_CHAR_CHDIS_Max (0x1UL) /*!< Max enumerator value of CHDIS field. */ + #define USBHSCORE_HC_CHAR_CHDIS_INACTIVE (0x0UL) /*!< Transmit/Recieve normal */ + #define USBHSCORE_HC_CHAR_CHDIS_ACTIVE (0x1UL) /*!< Stop transmitting/receiving data on channel */ + +/* CHENA @Bit 31 : Channel Enable (ChEna) */ + #define USBHSCORE_HC_CHAR_CHENA_Pos (31UL) /*!< Position of CHENA field. */ + #define USBHSCORE_HC_CHAR_CHENA_Msk (0x1UL << USBHSCORE_HC_CHAR_CHENA_Pos) /*!< Bit mask of CHENA field. */ + #define USBHSCORE_HC_CHAR_CHENA_Min (0x0UL) /*!< Min enumerator value of CHENA field. */ + #define USBHSCORE_HC_CHAR_CHENA_Max (0x1UL) /*!< Max enumerator value of CHENA field. */ + #define USBHSCORE_HC_CHAR_CHENA_DISABLED (0x0UL) /*!< If Scatter/Gather mode is enabled, indicates that the descriptor + structure is not yet ready. If Scatter/Gather mode is disabled, + indicates that the channel is disabled.*/ + #define USBHSCORE_HC_CHAR_CHENA_ENABLED (0x1UL) /*!< If Scatter/Gather mode is enabled, indicates that the descriptor + structure and data buffer with data is set up and this channel can + access the descriptor. If Scatter/Gather mode is disabled, indicates + that the channel is enabled.*/ + + +/* USBHSCORE_HC_SPLT: Host Channel Split Control Register 0 */ + #define USBHSCORE_HC_SPLT_ResetValue (0x00000000UL) /*!< Reset value of SPLT register. */ + +/* PRTADDR @Bits 0..6 : Port Address (PrtAddr) */ + #define USBHSCORE_HC_SPLT_PRTADDR_Pos (0UL) /*!< Position of PRTADDR field. */ + #define USBHSCORE_HC_SPLT_PRTADDR_Msk (0x7FUL << USBHSCORE_HC_SPLT_PRTADDR_Pos) /*!< Bit mask of PRTADDR field. */ + +/* HUBADDR @Bits 7..13 : Hub Address (HubAddr) */ + #define USBHSCORE_HC_SPLT_HUBADDR_Pos (7UL) /*!< Position of HUBADDR field. */ + #define USBHSCORE_HC_SPLT_HUBADDR_Msk (0x7FUL << USBHSCORE_HC_SPLT_HUBADDR_Pos) /*!< Bit mask of HUBADDR field. */ + +/* XACTPOS @Bits 14..15 : Transaction Position (XactPos) */ + #define USBHSCORE_HC_SPLT_XACTPOS_Pos (14UL) /*!< Position of XACTPOS field. */ + #define USBHSCORE_HC_SPLT_XACTPOS_Msk (0x3UL << USBHSCORE_HC_SPLT_XACTPOS_Pos) /*!< Bit mask of XACTPOS field. */ + #define USBHSCORE_HC_SPLT_XACTPOS_Min (0x0UL) /*!< Min enumerator value of XACTPOS field. */ + #define USBHSCORE_HC_SPLT_XACTPOS_Max (0x3UL) /*!< Max enumerator value of XACTPOS field. */ + #define USBHSCORE_HC_SPLT_XACTPOS_MIDDLE (0x0UL) /*!< Mid. This is the middle payload of this transaction (which is larger + than 188 bytes)*/ + #define USBHSCORE_HC_SPLT_XACTPOS_END (0x1UL) /*!< End. This is the last payload of this transaction (which is larger + than 188 bytes)*/ + #define USBHSCORE_HC_SPLT_XACTPOS_BEGIN (0x2UL) /*!< Begin. This is the first data payload of this transaction (which is + larger than 188 bytes)*/ + #define USBHSCORE_HC_SPLT_XACTPOS_ALL (0x3UL) /*!< All. This is the entire data payload of this transaction (which is + less than or equal to 188 bytes)*/ + +/* COMPSPLT @Bit 16 : Do Complete Split (CompSplt) */ + #define USBHSCORE_HC_SPLT_COMPSPLT_Pos (16UL) /*!< Position of COMPSPLT field. */ + #define USBHSCORE_HC_SPLT_COMPSPLT_Msk (0x1UL << USBHSCORE_HC_SPLT_COMPSPLT_Pos) /*!< Bit mask of COMPSPLT field. */ + #define USBHSCORE_HC_SPLT_COMPSPLT_Min (0x0UL) /*!< Min enumerator value of COMPSPLT field. */ + #define USBHSCORE_HC_SPLT_COMPSPLT_Max (0x1UL) /*!< Max enumerator value of COMPSPLT field. */ + #define USBHSCORE_HC_SPLT_COMPSPLT_NOSPLIT (0x0UL) /*!< No complete split transaction */ + #define USBHSCORE_HC_SPLT_COMPSPLT_SPLIT (0x1UL) /*!< Complete Split transaction */ + +/* SPLTENA @Bit 31 : Split Enable (SpltEna) */ + #define USBHSCORE_HC_SPLT_SPLTENA_Pos (31UL) /*!< Position of SPLTENA field. */ + #define USBHSCORE_HC_SPLT_SPLTENA_Msk (0x1UL << USBHSCORE_HC_SPLT_SPLTENA_Pos) /*!< Bit mask of SPLTENA field. */ + #define USBHSCORE_HC_SPLT_SPLTENA_Min (0x0UL) /*!< Min enumerator value of SPLTENA field. */ + #define USBHSCORE_HC_SPLT_SPLTENA_Max (0x1UL) /*!< Max enumerator value of SPLTENA field. */ + #define USBHSCORE_HC_SPLT_SPLTENA_DISABLED (0x0UL) /*!< Split not enabled */ + #define USBHSCORE_HC_SPLT_SPLTENA_ENABLED (0x1UL) /*!< Split enabled */ + + +/* USBHSCORE_HC_INT: Host Channel Interrupt Register 0 */ + #define USBHSCORE_HC_INT_ResetValue (0x00000000UL) /*!< Reset value of INT register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed (XferCompl) */ + #define USBHSCORE_HC_INT_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_HC_INT_XFERCOMPL_Msk (0x1UL << USBHSCORE_HC_INT_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_HC_INT_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_HC_INT_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_HC_INT_XFERCOMPL_INACTIVE (0x0UL) /*!< Transfer in progress or No Active Transfer */ + #define USBHSCORE_HC_INT_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer completed normally without any errors */ + +/* CHHLTD @Bit 1 : Channel Halted (ChHltd) */ + #define USBHSCORE_HC_INT_CHHLTD_Pos (1UL) /*!< Position of CHHLTD field. */ + #define USBHSCORE_HC_INT_CHHLTD_Msk (0x1UL << USBHSCORE_HC_INT_CHHLTD_Pos) /*!< Bit mask of CHHLTD field. */ + #define USBHSCORE_HC_INT_CHHLTD_Min (0x0UL) /*!< Min enumerator value of CHHLTD field. */ + #define USBHSCORE_HC_INT_CHHLTD_Max (0x1UL) /*!< Max enumerator value of CHHLTD field. */ + #define USBHSCORE_HC_INT_CHHLTD_INACTIVE (0x0UL) /*!< Channel not halted */ + #define USBHSCORE_HC_INT_CHHLTD_ACTIVE (0x1UL) /*!< Channel Halted */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_HC_INT_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_HC_INT_AHBERR_Msk (0x1UL << USBHSCORE_HC_INT_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_HC_INT_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_HC_INT_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_HC_INT_AHBERR_INACTIVE (0x0UL) /*!< No AHB error */ + #define USBHSCORE_HC_INT_AHBERR_ACTIVE (0x1UL) /*!< AHB error during AHB read/write */ + +/* STALL @Bit 3 : STALL Response Received Interrupt (STALL) */ + #define USBHSCORE_HC_INT_STALL_Pos (3UL) /*!< Position of STALL field. */ + #define USBHSCORE_HC_INT_STALL_Msk (0x1UL << USBHSCORE_HC_INT_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_HC_INT_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_HC_INT_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_HC_INT_STALL_INACTIVE (0x0UL) /*!< No Stall Response Received Interrupt */ + #define USBHSCORE_HC_INT_STALL_ACTIVE (0x1UL) /*!< Stall Response Received Interrupt */ + +/* NAK @Bit 4 : NAK Response Received Interrupt (NAK) */ + #define USBHSCORE_HC_INT_NAK_Pos (4UL) /*!< Position of NAK field. */ + #define USBHSCORE_HC_INT_NAK_Msk (0x1UL << USBHSCORE_HC_INT_NAK_Pos) /*!< Bit mask of NAK field. */ + #define USBHSCORE_HC_INT_NAK_Min (0x0UL) /*!< Min enumerator value of NAK field. */ + #define USBHSCORE_HC_INT_NAK_Max (0x1UL) /*!< Max enumerator value of NAK field. */ + #define USBHSCORE_HC_INT_NAK_INACTIVE (0x0UL) /*!< No NAK Response Received Interrupt */ + #define USBHSCORE_HC_INT_NAK_ACTIVE (0x1UL) /*!< NAK Response Received Interrupt */ + +/* ACK @Bit 5 : ACK Response Received/Transmitted Interrupt (ACK) */ + #define USBHSCORE_HC_INT_ACK_Pos (5UL) /*!< Position of ACK field. */ + #define USBHSCORE_HC_INT_ACK_Msk (0x1UL << USBHSCORE_HC_INT_ACK_Pos) /*!< Bit mask of ACK field. */ + #define USBHSCORE_HC_INT_ACK_Min (0x0UL) /*!< Min enumerator value of ACK field. */ + #define USBHSCORE_HC_INT_ACK_Max (0x1UL) /*!< Max enumerator value of ACK field. */ + #define USBHSCORE_HC_INT_ACK_INACTIVE (0x0UL) /*!< No ACK Response Received or Transmitted Interrupt */ + #define USBHSCORE_HC_INT_ACK_ACTIVE (0x1UL) /*!< ACK Response Received or Transmitted Interrup */ + +/* NYET @Bit 6 : NYET Response Received Interrupt (NYET) */ + #define USBHSCORE_HC_INT_NYET_Pos (6UL) /*!< Position of NYET field. */ + #define USBHSCORE_HC_INT_NYET_Msk (0x1UL << USBHSCORE_HC_INT_NYET_Pos) /*!< Bit mask of NYET field. */ + #define USBHSCORE_HC_INT_NYET_Min (0x0UL) /*!< Min enumerator value of NYET field. */ + #define USBHSCORE_HC_INT_NYET_Max (0x1UL) /*!< Max enumerator value of NYET field. */ + #define USBHSCORE_HC_INT_NYET_INACTIVE (0x0UL) /*!< No NYET Response Received Interrupt */ + #define USBHSCORE_HC_INT_NYET_ACTIVE (0x1UL) /*!< NYET Response Received Interrupt */ + +/* XACTERR @Bit 7 : Transaction Error (XactErr) */ + #define USBHSCORE_HC_INT_XACTERR_Pos (7UL) /*!< Position of XACTERR field. */ + #define USBHSCORE_HC_INT_XACTERR_Msk (0x1UL << USBHSCORE_HC_INT_XACTERR_Pos) /*!< Bit mask of XACTERR field. */ + #define USBHSCORE_HC_INT_XACTERR_Min (0x0UL) /*!< Min enumerator value of XACTERR field. */ + #define USBHSCORE_HC_INT_XACTERR_Max (0x1UL) /*!< Max enumerator value of XACTERR field. */ + #define USBHSCORE_HC_INT_XACTERR_INACTIVE (0x0UL) /*!< No Transaction Error */ + #define USBHSCORE_HC_INT_XACTERR_ACTIVE (0x1UL) /*!< Transaction Error */ + +/* BBLERR @Bit 8 : Babble Error (BblErr) */ + #define USBHSCORE_HC_INT_BBLERR_Pos (8UL) /*!< Position of BBLERR field. */ + #define USBHSCORE_HC_INT_BBLERR_Msk (0x1UL << USBHSCORE_HC_INT_BBLERR_Pos) /*!< Bit mask of BBLERR field. */ + #define USBHSCORE_HC_INT_BBLERR_Min (0x0UL) /*!< Min enumerator value of BBLERR field. */ + #define USBHSCORE_HC_INT_BBLERR_Max (0x1UL) /*!< Max enumerator value of BBLERR field. */ + #define USBHSCORE_HC_INT_BBLERR_INACTIVE (0x0UL) /*!< No Babble Error */ + #define USBHSCORE_HC_INT_BBLERR_ACTIVE (0x1UL) /*!< Babble Error */ + +/* FRMOVRUN @Bit 9 : Frame Overrun (FrmOvrun). */ + #define USBHSCORE_HC_INT_FRMOVRUN_Pos (9UL) /*!< Position of FRMOVRUN field. */ + #define USBHSCORE_HC_INT_FRMOVRUN_Msk (0x1UL << USBHSCORE_HC_INT_FRMOVRUN_Pos) /*!< Bit mask of FRMOVRUN field. */ + #define USBHSCORE_HC_INT_FRMOVRUN_Min (0x0UL) /*!< Min enumerator value of FRMOVRUN field. */ + #define USBHSCORE_HC_INT_FRMOVRUN_Max (0x1UL) /*!< Max enumerator value of FRMOVRUN field. */ + #define USBHSCORE_HC_INT_FRMOVRUN_INACTIVE (0x0UL) /*!< No Frame Overrun */ + #define USBHSCORE_HC_INT_FRMOVRUN_ACTIVE (0x1UL) /*!< Frame Overrun */ + +/* DATATGLERR @Bit 10 : (unspecified) */ + #define USBHSCORE_HC_INT_DATATGLERR_Pos (10UL) /*!< Position of DATATGLERR field. */ + #define USBHSCORE_HC_INT_DATATGLERR_Msk (0x1UL << USBHSCORE_HC_INT_DATATGLERR_Pos) /*!< Bit mask of DATATGLERR field. */ + #define USBHSCORE_HC_INT_DATATGLERR_Min (0x0UL) /*!< Min enumerator value of DATATGLERR field. */ + #define USBHSCORE_HC_INT_DATATGLERR_Max (0x1UL) /*!< Max enumerator value of DATATGLERR field. */ + #define USBHSCORE_HC_INT_DATATGLERR_INACTIVE (0x0UL) /*!< No Data Toggle Error */ + #define USBHSCORE_HC_INT_DATATGLERR_ACTIVE (0x1UL) /*!< Data Toggle Error */ + + +/* USBHSCORE_HC_INTMSK: Host Channel Interrupt Mask Register 0 */ + #define USBHSCORE_HC_INTMSK_ResetValue (0x00000000UL) /*!< Reset value of INTMSK register. */ + +/* XFERCOMPLMSK @Bit 0 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Pos (0UL) /*!< Position of XFERCOMPLMSK field. */ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Pos) /*!< Bit mask of XFERCOMPLMSK + field.*/ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Min (0x0UL) /*!< Min enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Max (0x1UL) /*!< Max enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_MASK (0x0UL) /*!< Transfer Completed Mask */ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_NOMASK (0x1UL) /*!< No Transfer Completed Mask */ + +/* CHHLTDMSK @Bit 1 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Pos (1UL) /*!< Position of CHHLTDMSK field. */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_CHHLTDMSK_Pos) /*!< Bit mask of CHHLTDMSK field. */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Min (0x0UL) /*!< Min enumerator value of CHHLTDMSK field. */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Max (0x1UL) /*!< Max enumerator value of CHHLTDMSK field. */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_MASK (0x0UL) /*!< Channel Halted Mask */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_NOMASK (0x1UL) /*!< No Channel Halted Mask */ + +/* AHBERRMSK @Bit 2 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_Pos (2UL) /*!< Position of AHBERRMSK field. */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_AHBERRMSK_Pos) /*!< Bit mask of AHBERRMSK field. */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_Min (0x0UL) /*!< Min enumerator value of AHBERRMSK field. */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_Max (0x1UL) /*!< Max enumerator value of AHBERRMSK field. */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_MASK (0x0UL) /*!< AHB Error Mask */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_NOMASK (0x1UL) /*!< No AHB Error Mask */ + +/* STALLMSK @Bit 3 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_STALLMSK_Pos (3UL) /*!< Position of STALLMSK field. */ + #define USBHSCORE_HC_INTMSK_STALLMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_STALLMSK_Pos) /*!< Bit mask of STALLMSK field. */ + #define USBHSCORE_HC_INTMSK_STALLMSK_Min (0x0UL) /*!< Min enumerator value of STALLMSK field. */ + #define USBHSCORE_HC_INTMSK_STALLMSK_Max (0x1UL) /*!< Max enumerator value of STALLMSK field. */ + #define USBHSCORE_HC_INTMSK_STALLMSK_MASK (0x0UL) /*!< Mask STALL Response Received Interrupt */ + #define USBHSCORE_HC_INTMSK_STALLMSK_NOMASK (0x1UL) /*!< No STALL Response Received Interrupt Mask */ + +/* NAKMSK @Bit 4 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_NAKMSK_Pos (4UL) /*!< Position of NAKMSK field. */ + #define USBHSCORE_HC_INTMSK_NAKMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_NAKMSK_Pos) /*!< Bit mask of NAKMSK field. */ + #define USBHSCORE_HC_INTMSK_NAKMSK_Min (0x0UL) /*!< Min enumerator value of NAKMSK field. */ + #define USBHSCORE_HC_INTMSK_NAKMSK_Max (0x1UL) /*!< Max enumerator value of NAKMSK field. */ + #define USBHSCORE_HC_INTMSK_NAKMSK_MASK (0x0UL) /*!< Mask NAK Response Received Interrupt */ + #define USBHSCORE_HC_INTMSK_NAKMSK_NOMASK (0x1UL) /*!< No NAK Response Received Interrupt Mask */ + +/* ACKMSK @Bit 5 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_ACKMSK_Pos (5UL) /*!< Position of ACKMSK field. */ + #define USBHSCORE_HC_INTMSK_ACKMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_ACKMSK_Pos) /*!< Bit mask of ACKMSK field. */ + #define USBHSCORE_HC_INTMSK_ACKMSK_Min (0x0UL) /*!< Min enumerator value of ACKMSK field. */ + #define USBHSCORE_HC_INTMSK_ACKMSK_Max (0x1UL) /*!< Max enumerator value of ACKMSK field. */ + #define USBHSCORE_HC_INTMSK_ACKMSK_MASK (0x0UL) /*!< Mask ACK Response Received/Transmitted Interrupt */ + #define USBHSCORE_HC_INTMSK_ACKMSK_NOMASK (0x1UL) /*!< No ACK Response Received/Transmitted Interrupt Mask */ + +/* NYETMSK @Bit 6 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_NYETMSK_Pos (6UL) /*!< Position of NYETMSK field. */ + #define USBHSCORE_HC_INTMSK_NYETMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_NYETMSK_Pos) /*!< Bit mask of NYETMSK field. */ + #define USBHSCORE_HC_INTMSK_NYETMSK_Min (0x0UL) /*!< Min enumerator value of NYETMSK field. */ + #define USBHSCORE_HC_INTMSK_NYETMSK_Max (0x1UL) /*!< Max enumerator value of NYETMSK field. */ + #define USBHSCORE_HC_INTMSK_NYETMSK_MASK (0x0UL) /*!< Mask NYET Response Received Interrupt */ + #define USBHSCORE_HC_INTMSK_NYETMSK_NOMASK (0x1UL) /*!< No NYET Response Received Interrupt Mask */ + +/* XACTERRMSK @Bit 7 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_Pos (7UL) /*!< Position of XACTERRMSK field. */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_XACTERRMSK_Pos) /*!< Bit mask of XACTERRMSK field. */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_Min (0x0UL) /*!< Min enumerator value of XACTERRMSK field. */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_Max (0x1UL) /*!< Max enumerator value of XACTERRMSK field. */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_MASK (0x0UL) /*!< Mask Transaction Error */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_NOMASK (0x1UL) /*!< No Transaction Error Mask */ + +/* BBLERRMSK @Bit 8 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_Pos (8UL) /*!< Position of BBLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_BBLERRMSK_Pos) /*!< Bit mask of BBLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_Min (0x0UL) /*!< Min enumerator value of BBLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_Max (0x1UL) /*!< Max enumerator value of BBLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_MASK (0x0UL) /*!< Mask Babble Error */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_NOMASK (0x1UL) /*!< No Babble Error Mask */ + +/* FRMOVRUNMSK @Bit 9 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Pos (9UL) /*!< Position of FRMOVRUNMSK field. */ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Pos) /*!< Bit mask of FRMOVRUNMSK + field.*/ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Min (0x0UL) /*!< Min enumerator value of FRMOVRUNMSK field. */ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Max (0x1UL) /*!< Max enumerator value of FRMOVRUNMSK field. */ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_MASK (0x0UL) /*!< Mask Overrun Mask */ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_NOMASK (0x1UL) /*!< No Frame Overrun Mask */ + +/* DATATGLERRMSK @Bit 10 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Pos (10UL) /*!< Position of DATATGLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_DATATGLERRMSK_Pos) /*!< Bit mask of DATATGLERRMSK + field.*/ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Min (0x0UL) /*!< Min enumerator value of DATATGLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Max (0x1UL) /*!< Max enumerator value of DATATGLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_MASK (0x0UL) /*!< Mask Data Toggle Error */ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_NOMASK (0x1UL) /*!< No Data Toggle Error Mask */ + + +/* USBHSCORE_HC_TSIZ: Host Channel Transfer Size Register 0 */ + #define USBHSCORE_HC_TSIZ_ResetValue (0x00000000UL) /*!< Reset value of TSIZ register. */ + +/* XFERSIZE @Bits 0..18 : Non-Scatter/Gather DMA Mode: */ + #define USBHSCORE_HC_TSIZ_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_HC_TSIZ_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_HC_TSIZ_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Non-Scatter/Gather DMA Mode: */ + #define USBHSCORE_HC_TSIZ_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_HC_TSIZ_PKTCNT_Msk (0x3FFUL << USBHSCORE_HC_TSIZ_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* PID @Bits 29..30 : PID (Pid) */ + #define USBHSCORE_HC_TSIZ_PID_Pos (29UL) /*!< Position of PID field. */ + #define USBHSCORE_HC_TSIZ_PID_Msk (0x3UL << USBHSCORE_HC_TSIZ_PID_Pos) /*!< Bit mask of PID field. */ + #define USBHSCORE_HC_TSIZ_PID_Min (0x0UL) /*!< Min enumerator value of PID field. */ + #define USBHSCORE_HC_TSIZ_PID_Max (0x3UL) /*!< Max enumerator value of PID field. */ + #define USBHSCORE_HC_TSIZ_PID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_HC_TSIZ_PID_DATA2 (0x1UL) /*!< DATA2 */ + #define USBHSCORE_HC_TSIZ_PID_DATA1 (0x2UL) /*!< DATA1 */ + #define USBHSCORE_HC_TSIZ_PID_MDATA (0x3UL) /*!< MDATA (non-control)/SETUP (control) */ + +/* DOPNG @Bit 31 : Do Ping (DoPng) */ + #define USBHSCORE_HC_TSIZ_DOPNG_Pos (31UL) /*!< Position of DOPNG field. */ + #define USBHSCORE_HC_TSIZ_DOPNG_Msk (0x1UL << USBHSCORE_HC_TSIZ_DOPNG_Pos) /*!< Bit mask of DOPNG field. */ + #define USBHSCORE_HC_TSIZ_DOPNG_Min (0x0UL) /*!< Min enumerator value of DOPNG field. */ + #define USBHSCORE_HC_TSIZ_DOPNG_Max (0x1UL) /*!< Max enumerator value of DOPNG field. */ + #define USBHSCORE_HC_TSIZ_DOPNG_NOPING (0x0UL) /*!< No ping protocol */ + #define USBHSCORE_HC_TSIZ_DOPNG_PING (0x1UL) /*!< Ping protocol */ + + +/* USBHSCORE_HC_DMA: Host Channel DMA Address Register 0 */ + #define USBHSCORE_HC_DMA_ResetValue (0x00000000UL) /*!< Reset value of DMA register. */ + +/* DMAADDR @Bits 0..31 : In Buffer DMA Mode: */ + #define USBHSCORE_HC_DMA_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_HC_DMA_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_HC_DMA_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + + +/* ============================================== Struct USBHSCORE_DWCOTGDFIFO =============================================== */ +/** + * @brief DWCOTGDFIFO [USBHSCORE_DWCOTGDFIFO] (unspecified) + */ +typedef struct { + __IOM uint32_t DATA[1024]; /*!< (@ 0x00000000) Data FIFO Access Register Map 0 */ +} NRF_USBHSCORE_DWCOTGDFIFO_Type; /*!< Size = 4096 (0x1000) */ + #define USBHSCORE_DWCOTGDFIFO_MaxCount (16UL) /*!< Size of DWCOTGDFIFO[16] array. */ + #define USBHSCORE_DWCOTGDFIFO_MaxIndex (15UL) /*!< Max index of DWCOTGDFIFO[16] array. */ + #define USBHSCORE_DWCOTGDFIFO_MinIndex (0UL) /*!< Min index of DWCOTGDFIFO[16] array. */ + + +/* ======================================== Struct USBHSCORE_DWCOTGDFIFODIRECTACCESS ========================================= */ +/** + * @brief DWCOTGDFIFODIRECTACCESS [USBHSCORE_DWCOTGDFIFODIRECTACCESS] (unspecified) + */ +typedef struct { + __IOM uint32_t DATA[3072]; /*!< (@ 0x00000000) Data FIFO Direct Access Register Map */ + __IM uint32_t RESERVED[29696]; +} NRF_USBHSCORE_DWCOTGDFIFODIRECTACCESS_Type; /*!< Size = 131072 (0x20000) */ + +/* ==================================================== Struct USBHSCORE ===================================================== */ +/** + * @brief USBHSCORE + */ + typedef struct { /*!< USBHSCORE Structure */ + __IOM uint32_t GOTGCTL; /*!< (@ 0x00000000) Control and Status Register */ + __IOM uint32_t GOTGINT; /*!< (@ 0x00000004) Interrupt Register */ + __IOM uint32_t GAHBCFG; /*!< (@ 0x00000008) AHB Configuration Register */ + __IOM uint32_t GUSBCFG; /*!< (@ 0x0000000C) USB Configuration Register */ + __IOM uint32_t GRSTCTL; /*!< (@ 0x00000010) Reset Register */ + __IOM uint32_t GINTSTS; /*!< (@ 0x00000014) Interrupt STATUS Register */ + __IOM uint32_t GINTMSK; /*!< (@ 0x00000018) Interrupt Mask Register */ + __IOM uint32_t GRXSTSR; /*!< (@ 0x0000001C) Receive Status Debug Read Register */ + __IOM uint32_t GRXSTSP; /*!< (@ 0x00000020) Receive Status Read/Pop Register */ + __IOM uint32_t GRXFSIZ; /*!< (@ 0x00000024) Receive FIFO Size Register */ + __IOM uint32_t GNPTXFSIZ; /*!< (@ 0x00000028) Non-periodic Transmit FIFO Size Register */ + __IOM uint32_t GNPTXSTS; /*!< (@ 0x0000002C) Non-periodic Transmit FIFO/Queue Status Register */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t GGPIO; /*!< (@ 0x00000038) General Purpose Input/Output Register */ + __IOM uint32_t GUID; /*!< (@ 0x0000003C) User ID Register */ + __IOM uint32_t GSNPSID; /*!< (@ 0x00000040) Synopsys ID Register */ + __IOM uint32_t GHWCFG1; /*!< (@ 0x00000044) User Hardware Configuration 1 Register */ + __IOM uint32_t GHWCFG2; /*!< (@ 0x00000048) User Hardware Configuration 2 Register */ + __IOM uint32_t GHWCFG3; /*!< (@ 0x0000004C) User Hardware Configuration 3 Register */ + __IOM uint32_t GHWCFG4; /*!< (@ 0x00000050) User Hardware Configuration 4 Register */ + __IOM uint32_t GLPMCFG; /*!< (@ 0x00000054) LPM Config Register */ + __IOM uint32_t GPWRDN; /*!< (@ 0x00000058) Global Power Down Register */ + __IOM uint32_t GDFIFOCFG; /*!< (@ 0x0000005C) Global DFIFO Configuration Register */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t GINTMSK2; /*!< (@ 0x00000068) Interrupt Mask Register 2 */ + __IOM uint32_t GINTSTS2; /*!< (@ 0x0000006C) Interrupt Register 2 */ + __IM uint32_t RESERVED2[36]; + __IOM uint32_t HPTXFSIZ; /*!< (@ 0x00000100) Host Periodic Transmit FIFO Size Register */ + __IOM uint32_t DIEPTXF[16]; /*!< (@ 0x00000104) Device IN Endpoint Transmit FIFO 1 Size Register */ + __IM uint32_t RESERVED3[175]; + __IOM uint32_t HCFG; /*!< (@ 0x00000400) Host Configuration Register */ + __IOM uint32_t HFIR; /*!< (@ 0x00000404) Host Frame Interval Register */ + __IOM uint32_t HFNUM; /*!< (@ 0x00000408) Host Frame Number/Frame Time Remaining Register */ + __IM uint32_t RESERVED4; + __IOM uint32_t HPTXSTS; /*!< (@ 0x00000410) Host Periodic Transmit FIFO/Queue Status Register */ + __IOM uint32_t HAINT; /*!< (@ 0x00000414) Host All Channels Interrupt Register */ + __IOM uint32_t HAINTMSK; /*!< (@ 0x00000418) Host All Channels Interrupt Mask Register */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t HPRT; /*!< (@ 0x00000440) Host Port Control and Status Register */ + __IM uint32_t RESERVED6[47]; + __IOM NRF_USBHSCORE_HC_Type HC[16]; /*!< (@ 0x00000500) (unspecified) */ + __IM uint32_t RESERVED7[96]; + __IOM uint32_t DCFG; /*!< (@ 0x00000800) Device Configuration Register */ + __IOM uint32_t DCTL; /*!< (@ 0x00000804) Device Control Register */ + __IOM uint32_t DSTS; /*!< (@ 0x00000808) Device Status Register */ + __IM uint32_t RESERVED8; + __IOM uint32_t DIEPMSK; /*!< (@ 0x00000810) Device IN Endpoint Common Interrupt Mask Register */ + __IOM uint32_t DOEPMSK; /*!< (@ 0x00000814) Device OUT Endpoint Common Interrupt Mask Register */ + __IOM uint32_t DAINT; /*!< (@ 0x00000818) Device All Endpoints Interrupt Register */ + __IOM uint32_t DAINTMSK; /*!< (@ 0x0000081C) Device All Endpoints Interrupt Mask Register */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t DVBUSDIS; /*!< (@ 0x00000828) Device VBUS Discharge Time Register */ + __IOM uint32_t DVBUSPULSE; /*!< (@ 0x0000082C) Device VBUS Pulsing Time Register */ + __IOM uint32_t DTHRCTL; /*!< (@ 0x00000830) Device Threshold Control Register */ + __IOM uint32_t DIEPEMPMSK; /*!< (@ 0x00000834) Device IN Endpoint FIFO Empty Interrupt Mask Register */ + __IM uint32_t RESERVED10[50]; + __IOM uint32_t DIEPCTL0; /*!< (@ 0x00000900) Device Control IN Endpoint 0 Control Register */ + __IM uint32_t RESERVED11; + __IOM uint32_t DIEPINT0; /*!< (@ 0x00000908) Device IN Endpoint 0 Interrupt Register */ + __IM uint32_t RESERVED12; + __IOM uint32_t DIEPTSIZ0; /*!< (@ 0x00000910) Device IN Endpoint 0 Transfer Size Register */ + __IOM uint32_t DIEPDMA0; /*!< (@ 0x00000914) Device IN Endpoint 0 DMA Address Register */ + __IOM uint32_t DTXFSTS0; /*!< (@ 0x00000918) Device IN Endpoint Transmit FIFO Status Register 0 */ + __IM uint32_t RESERVED13; + __IOM uint32_t DIEPCTL1; /*!< (@ 0x00000920) Device Control IN Endpoint Control Register 1 */ + __IM uint32_t RESERVED14; + __IOM uint32_t DIEPINT1; /*!< (@ 0x00000928) Device IN Endpoint Interrupt Register 1 */ + __IM uint32_t RESERVED15; + __IOM uint32_t DIEPTSIZ1; /*!< (@ 0x00000930) Device IN Endpoint Transfer Size Register 1 */ + __IOM uint32_t DIEPDMA1; /*!< (@ 0x00000934) Device IN Endpoint DMA Address Register 1 */ + __IOM uint32_t DTXFSTS1; /*!< (@ 0x00000938) Device IN Endpoint Transmit FIFO Status Register 1 */ + __IM uint32_t RESERVED16; + __IOM uint32_t DIEPCTL2; /*!< (@ 0x00000940) Device Control IN Endpoint Control Register 2 */ + __IM uint32_t RESERVED17; + __IOM uint32_t DIEPINT2; /*!< (@ 0x00000948) Device IN Endpoint Interrupt Register 2 */ + __IM uint32_t RESERVED18; + __IOM uint32_t DIEPTSIZ2; /*!< (@ 0x00000950) Device IN Endpoint Transfer Size Register 2 */ + __IOM uint32_t DIEPDMA2; /*!< (@ 0x00000954) Device IN Endpoint DMA Address Register 2 */ + __IOM uint32_t DTXFSTS2; /*!< (@ 0x00000958) Device IN Endpoint Transmit FIFO Status Register 2 */ + __IM uint32_t RESERVED19; + __IOM uint32_t DIEPCTL3; /*!< (@ 0x00000960) Device Control IN Endpoint Control Register 3 */ + __IM uint32_t RESERVED20; + __IOM uint32_t DIEPINT3; /*!< (@ 0x00000968) Device IN Endpoint Interrupt Register 3 */ + __IM uint32_t RESERVED21; + __IOM uint32_t DIEPTSIZ3; /*!< (@ 0x00000970) Device IN Endpoint Transfer Size Register 3 */ + __IOM uint32_t DIEPDMA3; /*!< (@ 0x00000974) Device IN Endpoint DMA Address Register 3 */ + __IOM uint32_t DTXFSTS3; /*!< (@ 0x00000978) Device IN Endpoint Transmit FIFO Status Register 3 */ + __IM uint32_t RESERVED22; + __IOM uint32_t DIEPCTL4; /*!< (@ 0x00000980) Device Control IN Endpoint Control Register 4 */ + __IM uint32_t RESERVED23; + __IOM uint32_t DIEPINT4; /*!< (@ 0x00000988) Device IN Endpoint Interrupt Register 4 */ + __IM uint32_t RESERVED24; + __IOM uint32_t DIEPTSIZ4; /*!< (@ 0x00000990) Device IN Endpoint Transfer Size Register 4 */ + __IOM uint32_t DIEPDMA4; /*!< (@ 0x00000994) Device IN Endpoint DMA Address Register 4 */ + __IOM uint32_t DTXFSTS4; /*!< (@ 0x00000998) Device IN Endpoint Transmit FIFO Status Register 4 */ + __IM uint32_t RESERVED25; + __IOM uint32_t DIEPCTL5; /*!< (@ 0x000009A0) Device Control IN Endpoint Control Register 5 */ + __IM uint32_t RESERVED26; + __IOM uint32_t DIEPINT5; /*!< (@ 0x000009A8) Device IN Endpoint Interrupt Register 5 */ + __IM uint32_t RESERVED27; + __IOM uint32_t DIEPTSIZ5; /*!< (@ 0x000009B0) Device IN Endpoint Transfer Size Register 5 */ + __IOM uint32_t DIEPDMA5; /*!< (@ 0x000009B4) Device IN Endpoint DMA Address Register 5 */ + __IOM uint32_t DTXFSTS5; /*!< (@ 0x000009B8) Device IN Endpoint Transmit FIFO Status Register 5 */ + __IM uint32_t RESERVED28; + __IOM uint32_t DIEPCTL6; /*!< (@ 0x000009C0) Device Control IN Endpoint Control Register 6 */ + __IM uint32_t RESERVED29; + __IOM uint32_t DIEPINT6; /*!< (@ 0x000009C8) Device IN Endpoint Interrupt Register 6 */ + __IM uint32_t RESERVED30; + __IOM uint32_t DIEPTSIZ6; /*!< (@ 0x000009D0) Device IN Endpoint Transfer Size Register 6 */ + __IOM uint32_t DIEPDMA6; /*!< (@ 0x000009D4) Device IN Endpoint DMA Address Register 6 */ + __IOM uint32_t DTXFSTS6; /*!< (@ 0x000009D8) Device IN Endpoint Transmit FIFO Status Register 6 */ + __IM uint32_t RESERVED31; + __IOM uint32_t DIEPCTL7; /*!< (@ 0x000009E0) Device Control IN Endpoint Control Register 7 */ + __IM uint32_t RESERVED32; + __IOM uint32_t DIEPINT7; /*!< (@ 0x000009E8) Device IN Endpoint Interrupt Register 7 */ + __IM uint32_t RESERVED33; + __IOM uint32_t DIEPTSIZ7; /*!< (@ 0x000009F0) Device IN Endpoint Transfer Size Register 7 */ + __IOM uint32_t DIEPDMA7; /*!< (@ 0x000009F4) Device IN Endpoint DMA Address Register 7 */ + __IOM uint32_t DTXFSTS7; /*!< (@ 0x000009F8) Device IN Endpoint Transmit FIFO Status Register 7 */ + __IM uint32_t RESERVED34; + __IOM uint32_t DIEPCTL8; /*!< (@ 0x00000A00) Device Control IN Endpoint Control Register 8 */ + __IM uint32_t RESERVED35; + __IOM uint32_t DIEPINT8; /*!< (@ 0x00000A08) Device IN Endpoint Interrupt Register 8 */ + __IM uint32_t RESERVED36; + __IOM uint32_t DIEPTSIZ8; /*!< (@ 0x00000A10) Device IN Endpoint Transfer Size Register 8 */ + __IOM uint32_t DIEPDMA8; /*!< (@ 0x00000A14) Device IN Endpoint DMA Address Register 8 */ + __IOM uint32_t DTXFSTS8; /*!< (@ 0x00000A18) Device IN Endpoint Transmit FIFO Status Register 8 */ + __IM uint32_t RESERVED37; + __IOM uint32_t DIEPCTL9; /*!< (@ 0x00000A20) Device Control IN Endpoint Control Register 9 */ + __IM uint32_t RESERVED38; + __IOM uint32_t DIEPINT9; /*!< (@ 0x00000A28) Device IN Endpoint Interrupt Register 9 */ + __IM uint32_t RESERVED39; + __IOM uint32_t DIEPTSIZ9; /*!< (@ 0x00000A30) Device IN Endpoint Transfer Size Register 9 */ + __IOM uint32_t DIEPDMA9; /*!< (@ 0x00000A34) Device IN Endpoint DMA Address Register 9 */ + __IOM uint32_t DTXFSTS9; /*!< (@ 0x00000A38) Device IN Endpoint Transmit FIFO Status Register 9 */ + __IM uint32_t RESERVED40; + __IOM uint32_t DIEPCTL10; /*!< (@ 0x00000A40) Device Control IN Endpoint Control Register 10 */ + __IM uint32_t RESERVED41; + __IOM uint32_t DIEPINT10; /*!< (@ 0x00000A48) Device IN Endpoint Interrupt Register 10 */ + __IM uint32_t RESERVED42; + __IOM uint32_t DIEPTSIZ10; /*!< (@ 0x00000A50) Device IN Endpoint Transfer Size Register 10 */ + __IOM uint32_t DIEPDMA10; /*!< (@ 0x00000A54) Device IN Endpoint DMA Address Register 10 */ + __IOM uint32_t DTXFSTS10; /*!< (@ 0x00000A58) Device IN Endpoint Transmit FIFO Status Register 10 */ + __IM uint32_t RESERVED43; + __IOM uint32_t DIEPCTL11; /*!< (@ 0x00000A60) Device Control IN Endpoint Control Register 11 */ + __IM uint32_t RESERVED44; + __IOM uint32_t DIEPINT11; /*!< (@ 0x00000A68) Device IN Endpoint Interrupt Register 11 */ + __IM uint32_t RESERVED45; + __IOM uint32_t DIEPTSIZ11; /*!< (@ 0x00000A70) Device IN Endpoint Transfer Size Register 11 */ + __IOM uint32_t DIEPDMA11; /*!< (@ 0x00000A74) Device IN Endpoint DMA Address Register 11 */ + __IOM uint32_t DTXFSTS11; /*!< (@ 0x00000A78) Device IN Endpoint Transmit FIFO Status Register 11 */ + __IM uint32_t RESERVED46; + __IOM uint32_t DIEPCTL12; /*!< (@ 0x00000A80) Device Control IN Endpoint Control Register 12 */ + __IM uint32_t RESERVED47; + __IOM uint32_t DIEPINT12; /*!< (@ 0x00000A88) Device IN Endpoint Interrupt Register 12 */ + __IM uint32_t RESERVED48; + __IOM uint32_t DIEPTSIZ12; /*!< (@ 0x00000A90) Device IN Endpoint Transfer Size Register 12 */ + __IOM uint32_t DIEPDMA12; /*!< (@ 0x00000A94) Device IN Endpoint DMA Address Register 12 */ + __IOM uint32_t DTXFSTS12; /*!< (@ 0x00000A98) Device IN Endpoint Transmit FIFO Status Register 12 */ + __IM uint32_t RESERVED49; + __IOM uint32_t DIEPCTL13; /*!< (@ 0x00000AA0) Device Control IN Endpoint Control Register 13 */ + __IM uint32_t RESERVED50; + __IOM uint32_t DIEPINT13; /*!< (@ 0x00000AA8) Device IN Endpoint Interrupt Register 13 */ + __IM uint32_t RESERVED51; + __IOM uint32_t DIEPTSIZ13; /*!< (@ 0x00000AB0) Device IN Endpoint Transfer Size Register 13 */ + __IOM uint32_t DIEPDMA13; /*!< (@ 0x00000AB4) Device IN Endpoint DMA Address Register 13 */ + __IOM uint32_t DTXFSTS13; /*!< (@ 0x00000AB8) Device IN Endpoint Transmit FIFO Status Register 13 */ + __IM uint32_t RESERVED52; + __IOM uint32_t DIEPCTL14; /*!< (@ 0x00000AC0) Device Control IN Endpoint Control Register 14 */ + __IM uint32_t RESERVED53; + __IOM uint32_t DIEPINT14; /*!< (@ 0x00000AC8) Device IN Endpoint Interrupt Register 14 */ + __IM uint32_t RESERVED54; + __IOM uint32_t DIEPTSIZ14; /*!< (@ 0x00000AD0) Device IN Endpoint Transfer Size Register 14 */ + __IOM uint32_t DIEPDMA14; /*!< (@ 0x00000AD4) Device IN Endpoint DMA Address Register 14 */ + __IOM uint32_t DTXFSTS14; /*!< (@ 0x00000AD8) Device IN Endpoint Transmit FIFO Status Register 14 */ + __IM uint32_t RESERVED55; + __IOM uint32_t DIEPCTL15; /*!< (@ 0x00000AE0) Device Control IN Endpoint Control Register 15 */ + __IM uint32_t RESERVED56; + __IOM uint32_t DIEPINT15; /*!< (@ 0x00000AE8) Device IN Endpoint Interrupt Register 15 */ + __IM uint32_t RESERVED57; + __IOM uint32_t DIEPTSIZ15; /*!< (@ 0x00000AF0) Device IN Endpoint Transfer Size Register 15 */ + __IOM uint32_t DIEPDMA15; /*!< (@ 0x00000AF4) Device IN Endpoint DMA Address Register 15 */ + __IOM uint32_t DTXFSTS15; /*!< (@ 0x00000AF8) Device IN Endpoint Transmit FIFO Status Register 15 */ + __IM uint32_t RESERVED58; + __IOM uint32_t DOEPCTL0; /*!< (@ 0x00000B00) Device Control OUT Endpoint 0 Control Register */ + __IM uint32_t RESERVED59; + __IOM uint32_t DOEPINT0; /*!< (@ 0x00000B08) Device OUT Endpoint 0 Interrupt Register */ + __IM uint32_t RESERVED60; + __IOM uint32_t DOEPTSIZ0; /*!< (@ 0x00000B10) Device OUT Endpoint 0 Transfer Size Register */ + __IOM uint32_t DOEPDMA0; /*!< (@ 0x00000B14) Device OUT Endpoint 0 DMA Address Register */ + __IM uint32_t RESERVED61[2]; + __IOM uint32_t DOEPCTL1; /*!< (@ 0x00000B20) Device Control OUT Endpoint Control Register 1 */ + __IM uint32_t RESERVED62; + __IOM uint32_t DOEPINT1; /*!< (@ 0x00000B28) Device OUT Endpoint Interrupt Register 1 */ + __IM uint32_t RESERVED63; + __IOM uint32_t DOEPTSIZ1; /*!< (@ 0x00000B30) Device OUT Endpoint Transfer Size Register 1 */ + __IOM uint32_t DOEPDMA1; /*!< (@ 0x00000B34) Device OUT Endpoint DMA Address Register 1 */ + __IM uint32_t RESERVED64[2]; + __IOM uint32_t DOEPCTL2; /*!< (@ 0x00000B40) Device Control OUT Endpoint Control Register 2 */ + __IM uint32_t RESERVED65; + __IOM uint32_t DOEPINT2; /*!< (@ 0x00000B48) Device OUT Endpoint Interrupt Register 2 */ + __IM uint32_t RESERVED66; + __IOM uint32_t DOEPTSIZ2; /*!< (@ 0x00000B50) Device OUT Endpoint Transfer Size Register 2 */ + __IOM uint32_t DOEPDMA2; /*!< (@ 0x00000B54) Device OUT Endpoint DMA Address Register 2 */ + __IM uint32_t RESERVED67[2]; + __IOM uint32_t DOEPCTL3; /*!< (@ 0x00000B60) Device Control OUT Endpoint Control Register 3 */ + __IM uint32_t RESERVED68; + __IOM uint32_t DOEPINT3; /*!< (@ 0x00000B68) Device OUT Endpoint Interrupt Register 3 */ + __IM uint32_t RESERVED69; + __IOM uint32_t DOEPTSIZ3; /*!< (@ 0x00000B70) Device OUT Endpoint Transfer Size Register 3 */ + __IOM uint32_t DOEPDMA3; /*!< (@ 0x00000B74) Device OUT Endpoint DMA Address Register 3 */ + __IM uint32_t RESERVED70[2]; + __IOM uint32_t DOEPCTL4; /*!< (@ 0x00000B80) Device Control OUT Endpoint Control Register 4 */ + __IM uint32_t RESERVED71; + __IOM uint32_t DOEPINT4; /*!< (@ 0x00000B88) Device OUT Endpoint Interrupt Register 4 */ + __IM uint32_t RESERVED72; + __IOM uint32_t DOEPTSIZ4; /*!< (@ 0x00000B90) Device OUT Endpoint Transfer Size Register 4 */ + __IOM uint32_t DOEPDMA4; /*!< (@ 0x00000B94) Device OUT Endpoint DMA Address Register 4 */ + __IM uint32_t RESERVED73[2]; + __IOM uint32_t DOEPCTL5; /*!< (@ 0x00000BA0) Device Control OUT Endpoint Control Register 5 */ + __IM uint32_t RESERVED74; + __IOM uint32_t DOEPINT5; /*!< (@ 0x00000BA8) Device OUT Endpoint Interrupt Register 5 */ + __IM uint32_t RESERVED75; + __IOM uint32_t DOEPTSIZ5; /*!< (@ 0x00000BB0) Device OUT Endpoint Transfer Size Register 5 */ + __IOM uint32_t DOEPDMA5; /*!< (@ 0x00000BB4) Device OUT Endpoint DMA Address Register 5 */ + __IM uint32_t RESERVED76[2]; + __IOM uint32_t DOEPCTL6; /*!< (@ 0x00000BC0) Device Control OUT Endpoint Control Register 6 */ + __IM uint32_t RESERVED77; + __IOM uint32_t DOEPINT6; /*!< (@ 0x00000BC8) Device OUT Endpoint Interrupt Register 6 */ + __IM uint32_t RESERVED78; + __IOM uint32_t DOEPTSIZ6; /*!< (@ 0x00000BD0) Device OUT Endpoint Transfer Size Register 6 */ + __IOM uint32_t DOEPDMA6; /*!< (@ 0x00000BD4) Device OUT Endpoint DMA Address Register 6 */ + __IM uint32_t RESERVED79[2]; + __IOM uint32_t DOEPCTL7; /*!< (@ 0x00000BE0) Device Control OUT Endpoint Control Register 7 */ + __IM uint32_t RESERVED80; + __IOM uint32_t DOEPINT7; /*!< (@ 0x00000BE8) Device OUT Endpoint Interrupt Register 7 */ + __IM uint32_t RESERVED81; + __IOM uint32_t DOEPTSIZ7; /*!< (@ 0x00000BF0) Device OUT Endpoint Transfer Size Register 7 */ + __IOM uint32_t DOEPDMA7; /*!< (@ 0x00000BF4) Device OUT Endpoint DMA Address Register 7 */ + __IM uint32_t RESERVED82[2]; + __IOM uint32_t DOEPCTL8; /*!< (@ 0x00000C00) Device Control OUT Endpoint Control Register 8 */ + __IM uint32_t RESERVED83; + __IOM uint32_t DOEPINT8; /*!< (@ 0x00000C08) Device OUT Endpoint Interrupt Register 8 */ + __IM uint32_t RESERVED84; + __IOM uint32_t DOEPTSIZ8; /*!< (@ 0x00000C10) Device OUT Endpoint Transfer Size Register 8 */ + __IOM uint32_t DOEPDMA8; /*!< (@ 0x00000C14) Device OUT Endpoint DMA Address Register 8 */ + __IM uint32_t RESERVED85[2]; + __IOM uint32_t DOEPCTL9; /*!< (@ 0x00000C20) Device Control OUT Endpoint Control Register 9 */ + __IM uint32_t RESERVED86; + __IOM uint32_t DOEPINT9; /*!< (@ 0x00000C28) Device OUT Endpoint Interrupt Register 9 */ + __IM uint32_t RESERVED87; + __IOM uint32_t DOEPTSIZ9; /*!< (@ 0x00000C30) Device OUT Endpoint Transfer Size Register 9 */ + __IOM uint32_t DOEPDMA9; /*!< (@ 0x00000C34) Device OUT Endpoint DMA Address Register 9 */ + __IM uint32_t RESERVED88[2]; + __IOM uint32_t DOEPCTL10; /*!< (@ 0x00000C40) Device Control OUT Endpoint Control Register 10 */ + __IM uint32_t RESERVED89; + __IOM uint32_t DOEPINT10; /*!< (@ 0x00000C48) Device OUT Endpoint Interrupt Register 10 */ + __IM uint32_t RESERVED90; + __IOM uint32_t DOEPTSIZ10; /*!< (@ 0x00000C50) Device OUT Endpoint Transfer Size Register 10 */ + __IOM uint32_t DOEPDMA10; /*!< (@ 0x00000C54) Device OUT Endpoint DMA Address Register 10 */ + __IM uint32_t RESERVED91[2]; + __IOM uint32_t DOEPCTL11; /*!< (@ 0x00000C60) Device Control OUT Endpoint Control Register 11 */ + __IM uint32_t RESERVED92; + __IOM uint32_t DOEPINT11; /*!< (@ 0x00000C68) Device OUT Endpoint Interrupt Register 11 */ + __IM uint32_t RESERVED93; + __IOM uint32_t DOEPTSIZ11; /*!< (@ 0x00000C70) Device OUT Endpoint Transfer Size Register 11 */ + __IOM uint32_t DOEPDMA11; /*!< (@ 0x00000C74) Device OUT Endpoint DMA Address Register 11 */ + __IM uint32_t RESERVED94[2]; + __IOM uint32_t DOEPCTL12; /*!< (@ 0x00000C80) Device Control OUT Endpoint Control Register 12 */ + __IM uint32_t RESERVED95; + __IOM uint32_t DOEPINT12; /*!< (@ 0x00000C88) Device OUT Endpoint Interrupt Register 12 */ + __IM uint32_t RESERVED96; + __IOM uint32_t DOEPTSIZ12; /*!< (@ 0x00000C90) Device OUT Endpoint Transfer Size Register 12 */ + __IOM uint32_t DOEPDMA12; /*!< (@ 0x00000C94) Device OUT Endpoint DMA Address Register 12 */ + __IM uint32_t RESERVED97[2]; + __IOM uint32_t DOEPCTL13; /*!< (@ 0x00000CA0) Device Control OUT Endpoint Control Register 13 */ + __IM uint32_t RESERVED98; + __IOM uint32_t DOEPINT13; /*!< (@ 0x00000CA8) Device OUT Endpoint Interrupt Register 13 */ + __IM uint32_t RESERVED99; + __IOM uint32_t DOEPTSIZ13; /*!< (@ 0x00000CB0) Device OUT Endpoint Transfer Size Register 13 */ + __IOM uint32_t DOEPDMA13; /*!< (@ 0x00000CB4) Device OUT Endpoint DMA Address Register 13 */ + __IM uint32_t RESERVED100[2]; + __IOM uint32_t DOEPCTL14; /*!< (@ 0x00000CC0) Device Control OUT Endpoint Control Register 14 */ + __IM uint32_t RESERVED101; + __IOM uint32_t DOEPINT14; /*!< (@ 0x00000CC8) Device OUT Endpoint Interrupt Register 14 */ + __IM uint32_t RESERVED102; + __IOM uint32_t DOEPTSIZ14; /*!< (@ 0x00000CD0) Device OUT Endpoint Transfer Size Register 14 */ + __IOM uint32_t DOEPDMA14; /*!< (@ 0x00000CD4) Device OUT Endpoint DMA Address Register 14 */ + __IM uint32_t RESERVED103[2]; + __IOM uint32_t DOEPCTL15; /*!< (@ 0x00000CE0) Device Control OUT Endpoint Control Register 15 */ + __IM uint32_t RESERVED104; + __IOM uint32_t DOEPINT15; /*!< (@ 0x00000CE8) Device OUT Endpoint Interrupt Register 15 */ + __IM uint32_t RESERVED105; + __IOM uint32_t DOEPTSIZ15; /*!< (@ 0x00000CF0) Device OUT Endpoint Transfer Size Register 15 */ + __IOM uint32_t DOEPDMA15; /*!< (@ 0x00000CF4) Device OUT Endpoint DMA Address Register 15 */ + __IM uint32_t RESERVED106[66]; + __IOM uint32_t PCGCCTL; /*!< (@ 0x00000E00) Power and Clock Gating Control Register */ + __IM uint32_t RESERVED107[63]; + __IOM uint32_t GSTARFXDIS; /*!< (@ 0x00000F00) Global STAR Fix Disable Register */ + __IM uint32_t RESERVED108[63]; + __IOM NRF_USBHSCORE_DWCOTGDFIFO_Type DWCOTGDFIFO[16]; /*!< (@ 0x00001000) (unspecified) */ + __IOM NRF_USBHSCORE_DWCOTGDFIFODIRECTACCESS_Type DWCOTGDFIFODIRECTACCESS; /*!< (@ 0x00011000) (unspecified) */ + } NRF_USBHSCORE_Type; /*!< Size = 200704 (0x31000) */ + +/* USBHSCORE_GOTGCTL: Control and Status Register */ + #define USBHSCORE_GOTGCTL_ResetValue (0x000D0000UL) /*!< Reset value of GOTGCTL register. */ + +/* VBVALIDOVEN @Bit 2 : Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn) */ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Pos (2UL) /*!< Position of VBVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Msk (0x1UL << USBHSCORE_GOTGCTL_VBVALIDOVEN_Pos) /*!< Bit mask of VBVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Min (0x0UL) /*!< Min enumerator value of VBVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Max (0x1UL) /*!< Max enumerator value of VBVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_DISABLED (0x0UL) /*!< Override is disabled and bvalid signal from the respective PHY + selected is used internally by the controller*/ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_ENABLED (0x1UL) /*!< The vbus-valid signal received from the PHY is overridden with + GOTGCTL.VbvalidOvVal*/ + +/* VBVALIDOVVAL @Bit 3 : Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal) */ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Pos (3UL) /*!< Position of VBVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Msk (0x1UL << USBHSCORE_GOTGCTL_VBVALIDOVVAL_Pos) /*!< Bit mask of VBVALIDOVVAL field.*/ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Min (0x0UL) /*!< Min enumerator value of VBVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Max (0x1UL) /*!< Max enumerator value of VBVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_SET0 (0x0UL) /*!< vbusvalid value when GOTGCTL.VbvalidOvEn = 1 */ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_SET1 (0x1UL) /*!< vbusvalid value when GOTGCTL.VbvalidOvEn is 1 */ + +/* AVALIDOVEN @Bit 4 : Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn) */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_Pos (4UL) /*!< Position of AVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_Msk (0x1UL << USBHSCORE_GOTGCTL_AVALIDOVEN_Pos) /*!< Bit mask of AVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_Min (0x0UL) /*!< Min enumerator value of AVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_Max (0x1UL) /*!< Max enumerator value of AVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_DISABLED (0x0UL) /*!< Derive AValid from PHY */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_ENABLED (0x1UL) /*!< Derive Avalid from GOTGCTL.AvalidOvVal */ + +/* AVALIDOVVAL @Bit 5 : Mode: Host only. A-Peripheral Session Valid OverrideValue (AvalidOvVal) */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Pos (5UL) /*!< Position of AVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Msk (0x1UL << USBHSCORE_GOTGCTL_AVALIDOVVAL_Pos) /*!< Bit mask of AVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Min (0x0UL) /*!< Min enumerator value of AVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Max (0x1UL) /*!< Max enumerator value of AVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_VALUE0 (0x0UL) /*!< Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1 */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_VALUE1 (0x1UL) /*!< Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1 */ + +/* BVALIDOVEN @Bit 6 : Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn) */ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_Pos (6UL) /*!< Position of BVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_Msk (0x1UL << USBHSCORE_GOTGCTL_BVALIDOVEN_Pos) /*!< Bit mask of BVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_Min (0x0UL) /*!< Min enumerator value of BVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_Max (0x1UL) /*!< Max enumerator value of BVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_DISABLED (0x0UL) /*!< Override is disabled and bvalid signal from the respective PHY + selected is used internally by the core*/ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_ENABLED (0x1UL) /*!< Internally Bvalid received from the PHY is overridden with + GOTGCTL.BvalidOvVal*/ + +/* BVALIDOVVAL @Bit 7 : Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal) */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Pos (7UL) /*!< Position of BVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Msk (0x1UL << USBHSCORE_GOTGCTL_BVALIDOVVAL_Pos) /*!< Bit mask of BVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Min (0x0UL) /*!< Min enumerator value of BVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Max (0x1UL) /*!< Max enumerator value of BVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_VALUE0 (0x0UL) /*!< Bvalid value when GOTGCTL.BvalidOvEn =1 */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_VALUE1 (0x1UL) /*!< Bvalid value when GOTGCTL.BvalidOvEn =1 */ + +/* DBNCEFLTRBYPASS @Bit 15 : Mode: Host and Device. Debounce Filter Bypass */ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Pos (15UL) /*!< Position of DBNCEFLTRBYPASS field. */ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Msk (0x1UL << USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Pos) /*!< Bit mask of + DBNCEFLTRBYPASS field.*/ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Min (0x0UL) /*!< Min enumerator value of DBNCEFLTRBYPASS field. */ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Max (0x1UL) /*!< Max enumerator value of DBNCEFLTRBYPASS field. */ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_DISABLED (0x0UL) /*!< Debounce Filter Bypass is disabled. */ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_ENABLED (0x1UL) /*!< Debounce Filter Bypass is enabled. */ + +/* CONIDSTS @Bit 16 : Mode: Host and Device. Connector ID Status (ConIDSts) */ + #define USBHSCORE_GOTGCTL_CONIDSTS_Pos (16UL) /*!< Position of CONIDSTS field. */ + #define USBHSCORE_GOTGCTL_CONIDSTS_Msk (0x1UL << USBHSCORE_GOTGCTL_CONIDSTS_Pos) /*!< Bit mask of CONIDSTS field. */ + #define USBHSCORE_GOTGCTL_CONIDSTS_Min (0x0UL) /*!< Min enumerator value of CONIDSTS field. */ + #define USBHSCORE_GOTGCTL_CONIDSTS_Max (0x1UL) /*!< Max enumerator value of CONIDSTS field. */ + #define USBHSCORE_GOTGCTL_CONIDSTS_MODEA (0x0UL) /*!< The core is in A-Device mode. */ + #define USBHSCORE_GOTGCTL_CONIDSTS_MODEB (0x1UL) /*!< The core is in B-Device mode. */ + +/* DBNCTIME @Bit 17 : Mode: Host only. Long/Short Debounce Time (DbncTime) */ + #define USBHSCORE_GOTGCTL_DBNCTIME_Pos (17UL) /*!< Position of DBNCTIME field. */ + #define USBHSCORE_GOTGCTL_DBNCTIME_Msk (0x1UL << USBHSCORE_GOTGCTL_DBNCTIME_Pos) /*!< Bit mask of DBNCTIME field. */ + #define USBHSCORE_GOTGCTL_DBNCTIME_Min (0x0UL) /*!< Min enumerator value of DBNCTIME field. */ + #define USBHSCORE_GOTGCTL_DBNCTIME_Max (0x1UL) /*!< Max enumerator value of DBNCTIME field. */ + #define USBHSCORE_GOTGCTL_DBNCTIME_LONG (0x0UL) /*!< Long debounce time, used for physical connections (100 ms + 2.5 + micro-sec)*/ + #define USBHSCORE_GOTGCTL_DBNCTIME_SHORT (0x1UL) /*!< Short debounce time, used for soft connections (2.5 micro-sec) */ + +/* ASESVLD @Bit 18 : Mode: Host only. A-Session Valid (ASesVld) */ + #define USBHSCORE_GOTGCTL_ASESVLD_Pos (18UL) /*!< Position of ASESVLD field. */ + #define USBHSCORE_GOTGCTL_ASESVLD_Msk (0x1UL << USBHSCORE_GOTGCTL_ASESVLD_Pos) /*!< Bit mask of ASESVLD field. */ + #define USBHSCORE_GOTGCTL_ASESVLD_Min (0x0UL) /*!< Min enumerator value of ASESVLD field. */ + #define USBHSCORE_GOTGCTL_ASESVLD_Max (0x1UL) /*!< Max enumerator value of ASESVLD field. */ + #define USBHSCORE_GOTGCTL_ASESVLD_NOTVALID (0x0UL) /*!< A-session is not valid. */ + #define USBHSCORE_GOTGCTL_ASESVLD_VALID (0x1UL) /*!< A-session is valid. */ + +/* BSESVLD @Bit 19 : Mode: Device only. B-Session Valid (BSesVld) */ + #define USBHSCORE_GOTGCTL_BSESVLD_Pos (19UL) /*!< Position of BSESVLD field. */ + #define USBHSCORE_GOTGCTL_BSESVLD_Msk (0x1UL << USBHSCORE_GOTGCTL_BSESVLD_Pos) /*!< Bit mask of BSESVLD field. */ + #define USBHSCORE_GOTGCTL_BSESVLD_Min (0x0UL) /*!< Min enumerator value of BSESVLD field. */ + #define USBHSCORE_GOTGCTL_BSESVLD_Max (0x1UL) /*!< Max enumerator value of BSESVLD field. */ + #define USBHSCORE_GOTGCTL_BSESVLD_NOTVALID (0x0UL) /*!< B-session is not valid. */ + #define USBHSCORE_GOTGCTL_BSESVLD_VALID (0x1UL) /*!< B-session is valid. */ + +/* OTGVER @Bit 20 : OTG Version (OTGVer) */ + #define USBHSCORE_GOTGCTL_OTGVER_Pos (20UL) /*!< Position of OTGVER field. */ + #define USBHSCORE_GOTGCTL_OTGVER_Msk (0x1UL << USBHSCORE_GOTGCTL_OTGVER_Pos) /*!< Bit mask of OTGVER field. */ + #define USBHSCORE_GOTGCTL_OTGVER_Min (0x0UL) /*!< Min enumerator value of OTGVER field. */ + #define USBHSCORE_GOTGCTL_OTGVER_Max (0x1UL) /*!< Max enumerator value of OTGVER field. */ + #define USBHSCORE_GOTGCTL_OTGVER_VER13 (0x0UL) /*!< Supports OTG Version 1.3 */ + #define USBHSCORE_GOTGCTL_OTGVER_VER20 (0x1UL) /*!< Supports OTG Version 2.0 */ + +/* CURMOD @Bit 21 : Current Mode of Operation (CurMod) */ + #define USBHSCORE_GOTGCTL_CURMOD_Pos (21UL) /*!< Position of CURMOD field. */ + #define USBHSCORE_GOTGCTL_CURMOD_Msk (0x1UL << USBHSCORE_GOTGCTL_CURMOD_Pos) /*!< Bit mask of CURMOD field. */ + #define USBHSCORE_GOTGCTL_CURMOD_Min (0x0UL) /*!< Min enumerator value of CURMOD field. */ + #define USBHSCORE_GOTGCTL_CURMOD_Max (0x1UL) /*!< Max enumerator value of CURMOD field. */ + #define USBHSCORE_GOTGCTL_CURMOD_DEVICEMODE (0x0UL) /*!< Current mode is device mode. */ + #define USBHSCORE_GOTGCTL_CURMOD_HOSTMODE (0x1UL) /*!< Current mode is host mode. */ + +/* MULTVALIDBC @Bits 22..26 : Mode: Host and Device. Multi Valued ID pin (MultValIdBC) */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_Pos (22UL) /*!< Position of MULTVALIDBC field. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_Msk (0x1FUL << USBHSCORE_GOTGCTL_MULTVALIDBC_Pos) /*!< Bit mask of MULTVALIDBC field. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_Min (0x01UL) /*!< Min enumerator value of MULTVALIDBC field. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_Max (0x10UL) /*!< Max enumerator value of MULTVALIDBC field. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_RIDC (0x01UL) /*!< B-Device connected to ACA. VBUS is on. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_RIDB (0x02UL) /*!< B-Device connected to ACA. VBUS is off. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_RIDA (0x04UL) /*!< A-Device connected to ACA */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_RIDGND (0x08UL) /*!< A-Device not connected to ACA */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_RIDFLOAT (0x10UL) /*!< B-Device not connected to ACA */ + +/* CHIRPEN @Bit 27 : Mode: Device Only. This bit when programmed to 1'b1 results in the core asserting chirp_on before sending + an actual Chirp 'K' signal on USB. This bit is present only if OTG_BC_SUPPORT = 1.If OTG_BC_SUPPORT!=1, + this bit is a reserved bit. Do not set this bit when core is operating in HSIC mode because HSIC always + operates at High Speed and High speed chirp is not used */ + + #define USBHSCORE_GOTGCTL_CHIRPEN_Pos (27UL) /*!< Position of CHIRPEN field. */ + #define USBHSCORE_GOTGCTL_CHIRPEN_Msk (0x1UL << USBHSCORE_GOTGCTL_CHIRPEN_Pos) /*!< Bit mask of CHIRPEN field. */ + #define USBHSCORE_GOTGCTL_CHIRPEN_Min (0x0UL) /*!< Min enumerator value of CHIRPEN field. */ + #define USBHSCORE_GOTGCTL_CHIRPEN_Max (0x1UL) /*!< Max enumerator value of CHIRPEN field. */ + #define USBHSCORE_GOTGCTL_CHIRPEN_CHIRPDISABLE (0x0UL) /*!< The controller does not assert chirp_on before sending an actual + Chirp 'K' signal on USB.*/ + #define USBHSCORE_GOTGCTL_CHIRPEN_CHIRPENABLE (0x1UL) /*!< The controller asserts chirp_on before sending an actual Chirp 'K' + signal on USB.*/ + +/* EUSB2PHYDISCSUPP @Bit 28 : This field is only applicable to Device mode and must be set to 1'b1 if eUSB2 PHY is used. */ + #define USBHSCORE_GOTGCTL_EUSB2PHYDISCSUPP_Pos (28UL) /*!< Position of EUSB2PHYDISCSUPP field. */ + #define USBHSCORE_GOTGCTL_EUSB2PHYDISCSUPP_Msk (0x1UL << USBHSCORE_GOTGCTL_EUSB2PHYDISCSUPP_Pos) /*!< Bit mask of + EUSB2PHYDISCSUPP field.*/ + #define USBHSCORE_GOTGCTL_EUSB2PHYDISCSUPP_Min (0x0UL) /*!< Min enumerator value of EUSB2PHYDISCSUPP field. */ + #define USBHSCORE_GOTGCTL_EUSB2PHYDISCSUPP_Max (0x1UL) /*!< Max enumerator value of EUSB2PHYDISCSUPP field. */ + #define USBHSCORE_GOTGCTL_EUSB2PHYDISCSUPP_DISABLED (0x0UL) /*!< Device disconnect detection using GINTSTS.USBRst interrupt + when not in hibernation and GPWRDN.ResetDetected when in + hibernation*/ + #define USBHSCORE_GOTGCTL_EUSB2PHYDISCSUPP_ENABLED (0x1UL) /*!< Device disconnect detection using GOTGINT.SesEEndDet interrupt + when not in hibernation and GPWRDN.StsChngInt when in + hibernation*/ + + +/* USBHSCORE_GOTGINT: Interrupt Register */ + #define USBHSCORE_GOTGINT_ResetValue (0x00000000UL) /*!< Reset value of GOTGINT register. */ + +/* SESENDDET @Bit 2 : Mode: Host and Device. Session End Detected (SesEndDet) */ + #define USBHSCORE_GOTGINT_SESENDDET_Pos (2UL) /*!< Position of SESENDDET field. */ + #define USBHSCORE_GOTGINT_SESENDDET_Msk (0x1UL << USBHSCORE_GOTGINT_SESENDDET_Pos) /*!< Bit mask of SESENDDET field. */ + #define USBHSCORE_GOTGINT_SESENDDET_Min (0x0UL) /*!< Min enumerator value of SESENDDET field. */ + #define USBHSCORE_GOTGINT_SESENDDET_Max (0x1UL) /*!< Max enumerator value of SESENDDET field. */ + #define USBHSCORE_GOTGINT_SESENDDET_INACTIVE (0x0UL) /*!< Session is Active */ + #define USBHSCORE_GOTGINT_SESENDDET_ACTIVE (0x1UL) /*!< SessionEnd utmiotg_bvalid signal is deasserted */ + +/* SESREQSUCSTSCHNG @Bit 8 : Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng) */ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Pos (8UL) /*!< Position of SESREQSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Msk (0x1UL << USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Pos) /*!< Bit mask of + SESREQSUCSTSCHNG field.*/ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Min (0x0UL) /*!< Min enumerator value of SESREQSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Max (0x1UL) /*!< Max enumerator value of SESREQSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_INACTIVE (0x0UL) /*!< No Change in Session Request Status */ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_ACTIVE (0x1UL) /*!< Session Request Status has changed */ + +/* HSTNEGSUCSTSCHNG @Bit 9 : Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng) */ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Pos (9UL) /*!< Position of HSTNEGSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Msk (0x1UL << USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Pos) /*!< Bit mask of + HSTNEGSUCSTSCHNG field.*/ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Min (0x0UL) /*!< Min enumerator value of HSTNEGSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Max (0x1UL) /*!< Max enumerator value of HSTNEGSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_INACTIVE (0x0UL) /*!< No Change */ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_ACTIVE (0x1UL) /*!< Host Negotiation Status Change */ + +/* HSTNEGDET @Bit 17 : Mode:Host and Device. Host Negotiation Detected (HstNegDet) */ + #define USBHSCORE_GOTGINT_HSTNEGDET_Pos (17UL) /*!< Position of HSTNEGDET field. */ + #define USBHSCORE_GOTGINT_HSTNEGDET_Msk (0x1UL << USBHSCORE_GOTGINT_HSTNEGDET_Pos) /*!< Bit mask of HSTNEGDET field. */ + #define USBHSCORE_GOTGINT_HSTNEGDET_Min (0x0UL) /*!< Min enumerator value of HSTNEGDET field. */ + #define USBHSCORE_GOTGINT_HSTNEGDET_Max (0x1UL) /*!< Max enumerator value of HSTNEGDET field. */ + #define USBHSCORE_GOTGINT_HSTNEGDET_INACTIVE (0x0UL) /*!< No Active HNP Request */ + #define USBHSCORE_GOTGINT_HSTNEGDET_ACTIVE (0x1UL) /*!< Active HNP request detected */ + +/* ADEVTOUTCHG @Bit 18 : Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg) */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Pos (18UL) /*!< Position of ADEVTOUTCHG field. */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Msk (0x1UL << USBHSCORE_GOTGINT_ADEVTOUTCHG_Pos) /*!< Bit mask of ADEVTOUTCHG field. */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Min (0x0UL) /*!< Min enumerator value of ADEVTOUTCHG field. */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Max (0x1UL) /*!< Max enumerator value of ADEVTOUTCHG field. */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_INACTIVE (0x0UL) /*!< No A-Device Timeout */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_ACTIVE (0x1UL) /*!< A-Device Timeout */ + +/* DBNCEDONE @Bit 19 : Mode: Host only. Debounce Done (DbnceDone) */ + #define USBHSCORE_GOTGINT_DBNCEDONE_Pos (19UL) /*!< Position of DBNCEDONE field. */ + #define USBHSCORE_GOTGINT_DBNCEDONE_Msk (0x1UL << USBHSCORE_GOTGINT_DBNCEDONE_Pos) /*!< Bit mask of DBNCEDONE field. */ + #define USBHSCORE_GOTGINT_DBNCEDONE_Min (0x0UL) /*!< Min enumerator value of DBNCEDONE field. */ + #define USBHSCORE_GOTGINT_DBNCEDONE_Max (0x1UL) /*!< Max enumerator value of DBNCEDONE field. */ + #define USBHSCORE_GOTGINT_DBNCEDONE_INACTIVE (0x0UL) /*!< After Connect waiting for Debounce to complete */ + #define USBHSCORE_GOTGINT_DBNCEDONE_ACTIVE (0x1UL) /*!< Debounce completed */ + +/* MULTVALIPCHNG @Bit 20 : This bit when set indicates that there is a change in the value of at least one ACA pin value. */ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Pos (20UL) /*!< Position of MULTVALIPCHNG field. */ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Msk (0x1UL << USBHSCORE_GOTGINT_MULTVALIPCHNG_Pos) /*!< Bit mask of MULTVALIPCHNG + field.*/ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Min (0x0UL) /*!< Min enumerator value of MULTVALIPCHNG field. */ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Max (0x1UL) /*!< Max enumerator value of MULTVALIPCHNG field. */ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_NOACAPINCHANGE (0x0UL) /*!< Indicates there is no change in ACA pin value */ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_ACAPINCHANGE (0x1UL) /*!< Indicates there is a change in ACA pin value */ + + +/* USBHSCORE_GAHBCFG: AHB Configuration Register */ + #define USBHSCORE_GAHBCFG_ResetValue (0x0A000000UL) /*!< Reset value of GAHBCFG register. */ + +/* GLBLINTRMSK @Bit 0 : Mode: Host and device. Global Interrupt Mask (GlblIntrMsk) */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Pos (0UL) /*!< Position of GLBLINTRMSK field. */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Msk (0x1UL << USBHSCORE_GAHBCFG_GLBLINTRMSK_Pos) /*!< Bit mask of GLBLINTRMSK field. */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Min (0x0UL) /*!< Min enumerator value of GLBLINTRMSK field. */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Max (0x1UL) /*!< Max enumerator value of GLBLINTRMSK field. */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_MASK (0x0UL) /*!< Mask the interrupt assertion to the application */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_NOMASK (0x1UL) /*!< Unmask the interrupt assertion to the application. */ + +/* HBSTLEN @Bits 1..4 : Mode: Host and device. Burst Length/Type (HBstLen) */ + #define USBHSCORE_GAHBCFG_HBSTLEN_Pos (1UL) /*!< Position of HBSTLEN field. */ + #define USBHSCORE_GAHBCFG_HBSTLEN_Msk (0xFUL << USBHSCORE_GAHBCFG_HBSTLEN_Pos) /*!< Bit mask of HBSTLEN field. */ + #define USBHSCORE_GAHBCFG_HBSTLEN_Min (0x0UL) /*!< Min enumerator value of HBSTLEN field. */ + #define USBHSCORE_GAHBCFG_HBSTLEN_Max (0x8UL) /*!< Max enumerator value of HBSTLEN field. */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD1ORSINGLE (0x0UL) /*!< 1 word or single */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD4ORINCR (0x1UL) /*!< 4 words or INCR */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD8 (0x2UL) /*!< 8 words */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD16ORINCR4 (0x3UL) /*!< 16 words or INCR4 */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD32 (0x4UL) /*!< 32 words */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD64ORINCR8 (0x5UL) /*!< 64 words or INCR8 */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD128 (0x6UL) /*!< 128 words */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD256ORINCR16 (0x7UL) /*!< 256 words or INCR16 */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORDX (0x8UL) /*!< Others reserved */ + +/* DMAEN @Bit 5 : Mode: Host and device. DMA Enable (DMAEn) */ + #define USBHSCORE_GAHBCFG_DMAEN_Pos (5UL) /*!< Position of DMAEN field. */ + #define USBHSCORE_GAHBCFG_DMAEN_Msk (0x1UL << USBHSCORE_GAHBCFG_DMAEN_Pos) /*!< Bit mask of DMAEN field. */ + #define USBHSCORE_GAHBCFG_DMAEN_Min (0x0UL) /*!< Min enumerator value of DMAEN field. */ + #define USBHSCORE_GAHBCFG_DMAEN_Max (0x1UL) /*!< Max enumerator value of DMAEN field. */ + #define USBHSCORE_GAHBCFG_DMAEN_COMPLETERMODE (0x0UL) /*!< Core operates in Completer mode */ + #define USBHSCORE_GAHBCFG_DMAEN_DMAMODE (0x1UL) /*!< Core operates in a DMA mode */ + +/* NPTXFEMPLVL @Bit 7 : Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) */ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Pos (7UL) /*!< Position of NPTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Msk (0x1UL << USBHSCORE_GAHBCFG_NPTXFEMPLVL_Pos) /*!< Bit mask of NPTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Min (0x0UL) /*!< Min enumerator value of NPTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Max (0x1UL) /*!< Max enumerator value of NPTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_HALFEMPTY (0x0UL) /*!< DIEPINTn.TxFEmp interrupt indicates that the Non-Periodic TxFIFO + is half empty or that the IN Endpoint TxFIFO is half empty.*/ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_EMPTY (0x1UL) /*!< GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is + completely empty or that the IN Endpoint TxFIFO is completely empty.*/ + +/* PTXFEMPLVL @Bit 8 : Mode: Host only. Periodic TxFIFO Empty Level (PTxFEmpLvl) */ + #define USBHSCORE_GAHBCFG_PTXFEMPLVL_Pos (8UL) /*!< Position of PTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_PTXFEMPLVL_Msk (0x1UL << USBHSCORE_GAHBCFG_PTXFEMPLVL_Pos) /*!< Bit mask of PTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_PTXFEMPLVL_Min (0x0UL) /*!< Min enumerator value of PTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_PTXFEMPLVL_Max (0x1UL) /*!< Max enumerator value of PTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_PTXFEMPLVL_HALFEMPTY (0x0UL) /*!< GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is + half empty.*/ + #define USBHSCORE_GAHBCFG_PTXFEMPLVL_EMPTY (0x1UL) /*!< GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is + completely empty.*/ + +/* REMMEMSUPP @Bit 21 : Mode: Host and Device. Remote Memory Support (RemMemSupp) */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_Pos (21UL) /*!< Position of REMMEMSUPP field. */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_Msk (0x1UL << USBHSCORE_GAHBCFG_REMMEMSUPP_Pos) /*!< Bit mask of REMMEMSUPP field. */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_Min (0x0UL) /*!< Min enumerator value of REMMEMSUPP field. */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_Max (0x1UL) /*!< Max enumerator value of REMMEMSUPP field. */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_DISABLED (0x0UL) /*!< Remote Memory Support Feature disabled */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_ENABLED (0x1UL) /*!< Remote Memory Support Feature enabled */ + +/* NOTIALLDMAWRIT @Bit 22 : Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit) */ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Pos (22UL) /*!< Position of NOTIALLDMAWRIT field. */ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Msk (0x1UL << USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Pos) /*!< Bit mask of NOTIALLDMAWRIT + field.*/ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Min (0x0UL) /*!< Min enumerator value of NOTIALLDMAWRIT field. */ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Max (0x1UL) /*!< Max enumerator value of NOTIALLDMAWRIT field. */ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_LASTTRANS (0x0UL) /*!< (unspecified) */ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_ALLTRANS (0x1UL) /*!< The core asserts int_dma_req for all the DMA write transactions + on the AHB interface along with int_dma_done, + chep_last_transact and chep_number signal informations. The + core waits for sys_dma_done signal for all the DMA write + transactions in order to complete the transfer of a particular + Channel/Endpoint*/ + +/* AHBSINGLE @Bit 23 : Mode: Host and Device. AHB Single Support (AHBSingle) */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_Pos (23UL) /*!< Position of AHBSINGLE field. */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_Msk (0x1UL << USBHSCORE_GAHBCFG_AHBSINGLE_Pos) /*!< Bit mask of AHBSINGLE field. */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_Min (0x0UL) /*!< Min enumerator value of AHBSINGLE field. */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_Max (0x1UL) /*!< Max enumerator value of AHBSINGLE field. */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_INCRBURST (0x0UL) /*!< The remaining data in the transfer is sent using INCR burst size */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_SINGLEBURST (0x1UL) /*!< The remaining data in the transfer is sent using Single burst + size*/ + +/* LOAEOPCHECKCLKSBYTE @Bits 25..26 : Mode: Host. Number of clock cycles to check for EOP SE0 for LOA logic */ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSBYTE_Pos (25UL) /*!< Position of LOAEOPCHECKCLKSBYTE field. */ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSBYTE_Msk (0x3UL << USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSBYTE_Pos) /*!< Bit mask of + LOAEOPCHECKCLKSBYTE field.*/ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSBYTE_Min (0x1UL) /*!< Min enumerator value of LOAEOPCHECKCLKSBYTE field. */ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSBYTE_Max (0x2UL) /*!< Max enumerator value of LOAEOPCHECKCLKSBYTE field. */ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSBYTE_ONE (0x1UL) /*!< Check for 2 clocks of EOP SE0 */ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSBYTE_TWO (0x2UL) /*!< Check for 3 clocks of EOP SE0 */ + +/* LOAEOPCHECKCLKSWORD @Bits 27..28 : Mode: Host. Number of clock cycles to check for EOP SE0 for LOA logic */ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSWORD_Pos (27UL) /*!< Position of LOAEOPCHECKCLKSWORD field. */ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSWORD_Msk (0x3UL << USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSWORD_Pos) /*!< Bit mask of + LOAEOPCHECKCLKSWORD field.*/ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSWORD_Min (0x1UL) /*!< Min enumerator value of LOAEOPCHECKCLKSWORD field. */ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSWORD_Max (0x2UL) /*!< Max enumerator value of LOAEOPCHECKCLKSWORD field. */ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSWORD_ONE (0x1UL) /*!< Check for 2 clocks of EOP SE0 */ + #define USBHSCORE_GAHBCFG_LOAEOPCHECKCLKSWORD_TWO (0x2UL) /*!< Check for 3 clocks of EOP SE0 */ + + +/* USBHSCORE_GUSBCFG: USB Configuration Register */ + #define USBHSCORE_GUSBCFG_ResetValue (0x10001400UL) /*!< Reset value of GUSBCFG register. */ + +/* TOUTCAL @Bits 0..2 : Mode: Host and Device. HS/FS Timeout Calibration (TOutCal) */ + #define USBHSCORE_GUSBCFG_TOUTCAL_Pos (0UL) /*!< Position of TOUTCAL field. */ + #define USBHSCORE_GUSBCFG_TOUTCAL_Msk (0x7UL << USBHSCORE_GUSBCFG_TOUTCAL_Pos) /*!< Bit mask of TOUTCAL field. */ + #define USBHSCORE_GUSBCFG_TOUTCAL_Min (0x0UL) /*!< Min enumerator value of TOUTCAL field. */ + #define USBHSCORE_GUSBCFG_TOUTCAL_Max (0x7UL) /*!< Max enumerator value of TOUTCAL field. */ + #define USBHSCORE_GUSBCFG_TOUTCAL_ZERO (0x0UL) /*!< Add 0 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_ONE (0x1UL) /*!< Add 1 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_TWO (0x2UL) /*!< Add 2 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_THREE (0x3UL) /*!< Add 3 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_FOUR (0x4UL) /*!< Add 4 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_FIVE (0x5UL) /*!< Add 5 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_SIX (0x6UL) /*!< Add 6 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_SEVEN (0x7UL) /*!< Add 7 PHY clocks */ + +/* PHYIF @Bit 3 : Mode: Host and Device. PHY Interface (PHYIf) */ + #define USBHSCORE_GUSBCFG_PHYIF_Pos (3UL) /*!< Position of PHYIF field. */ + #define USBHSCORE_GUSBCFG_PHYIF_Msk (0x1UL << USBHSCORE_GUSBCFG_PHYIF_Pos) /*!< Bit mask of PHYIF field. */ + #define USBHSCORE_GUSBCFG_PHYIF_Min (0x0UL) /*!< Min enumerator value of PHYIF field. */ + #define USBHSCORE_GUSBCFG_PHYIF_Max (0x1UL) /*!< Max enumerator value of PHYIF field. */ + #define USBHSCORE_GUSBCFG_PHYIF_BITS8 (0x0UL) /*!< PHY 8bit Mode */ + #define USBHSCORE_GUSBCFG_PHYIF_BITS16 (0x1UL) /*!< PHY 16bit Mode */ + +/* ULPIUTMISEL @Bit 4 : Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel) */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Pos (4UL) /*!< Position of ULPIUTMISEL field. */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Msk (0x1UL << USBHSCORE_GUSBCFG_ULPIUTMISEL_Pos) /*!< Bit mask of ULPIUTMISEL field. */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Min (0x0UL) /*!< Min enumerator value of ULPIUTMISEL field. */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Max (0x1UL) /*!< Max enumerator value of ULPIUTMISEL field. */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_UTMI (0x0UL) /*!< UTMI+ Interface */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_ULPI (0x1UL) /*!< ULPI Interface */ + +/* FSINTF @Bit 5 : Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf) */ + #define USBHSCORE_GUSBCFG_FSINTF_Pos (5UL) /*!< Position of FSINTF field. */ + #define USBHSCORE_GUSBCFG_FSINTF_Msk (0x1UL << USBHSCORE_GUSBCFG_FSINTF_Pos) /*!< Bit mask of FSINTF field. */ + #define USBHSCORE_GUSBCFG_FSINTF_Min (0x0UL) /*!< Min enumerator value of FSINTF field. */ + #define USBHSCORE_GUSBCFG_FSINTF_Max (0x1UL) /*!< Max enumerator value of FSINTF field. */ + #define USBHSCORE_GUSBCFG_FSINTF_FS6PIN (0x0UL) /*!< 6-pin unidirectional full-speed serial interface */ + #define USBHSCORE_GUSBCFG_FSINTF_FS3PIN (0x1UL) /*!< 3-pin bidirectional full-speed serial interface */ + +/* PHYSEL @Bit 6 : PHYSel */ + #define USBHSCORE_GUSBCFG_PHYSEL_Pos (6UL) /*!< Position of PHYSEL field. */ + #define USBHSCORE_GUSBCFG_PHYSEL_Msk (0x1UL << USBHSCORE_GUSBCFG_PHYSEL_Pos) /*!< Bit mask of PHYSEL field. */ + #define USBHSCORE_GUSBCFG_PHYSEL_Min (0x0UL) /*!< Min enumerator value of PHYSEL field. */ + #define USBHSCORE_GUSBCFG_PHYSEL_Max (0x1UL) /*!< Max enumerator value of PHYSEL field. */ + #define USBHSCORE_GUSBCFG_PHYSEL_USB20 (0x0UL) /*!< USB 2.0 high-speed UTMI+ or ULPI PHY is selected */ + #define USBHSCORE_GUSBCFG_PHYSEL_USB11 (0x1UL) /*!< USB 1.1 full-speed serial transceiver is selected */ + +/* USBTRDTIM @Bits 10..13 : Mode: Device only. USB Turnaround Time (USBTrdTim) */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_Pos (10UL) /*!< Position of USBTRDTIM field. */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_Msk (0xFUL << USBHSCORE_GUSBCFG_USBTRDTIM_Pos) /*!< Bit mask of USBTRDTIM field. */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_Min (0x5UL) /*!< Min enumerator value of USBTRDTIM field. */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_Max (0x9UL) /*!< Max enumerator value of USBTRDTIM field. */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_TURNTIME16BIT (0x5UL) /*!< MAC interface is 16-bit UTMI+. */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_TURNTIME8BIT (0x9UL) /*!< MAC interface is 8-bit UTMI+. */ + +/* PHYLPWRCLKSEL @Bit 15 : PHY Low-Power Clock Select (PhyLPwrClkSel) */ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Pos (15UL) /*!< Position of PHYLPWRCLKSEL field. */ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Msk (0x1UL << USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Pos) /*!< Bit mask of PHYLPWRCLKSEL + field.*/ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Min (0x0UL) /*!< Min enumerator value of PHYLPWRCLKSEL field. */ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Max (0x1UL) /*!< Max enumerator value of PHYLPWRCLKSEL field. */ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_INTPLLCLK (0x0UL) /*!< 480-MHz Internal PLL clock */ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_EXTCLK (0x1UL) /*!< 48-MHz External Clock */ + +/* TERMSELDLPULSE @Bit 22 : Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse) */ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Pos (22UL) /*!< Position of TERMSELDLPULSE field. */ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Msk (0x1UL << USBHSCORE_GUSBCFG_TERMSELDLPULSE_Pos) /*!< Bit mask of TERMSELDLPULSE + field.*/ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Min (0x0UL) /*!< Min enumerator value of TERMSELDLPULSE field. */ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Max (0x1UL) /*!< Max enumerator value of TERMSELDLPULSE field. */ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_TXVALID (0x0UL) /*!< Data line pulsing using utmi_txvalid */ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_TERMSEL (0x1UL) /*!< Data line pulsing using utmi_termsel */ + +/* ICUSBCAP @Bit 26 : Mode: Host and Device. IC_USB-Capable (IC_USBCap) */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_Pos (26UL) /*!< Position of ICUSBCAP field. */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_Msk (0x1UL << USBHSCORE_GUSBCFG_ICUSBCAP_Pos) /*!< Bit mask of ICUSBCAP field. */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_Min (0x0UL) /*!< Min enumerator value of ICUSBCAP field. */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_Max (0x1UL) /*!< Max enumerator value of ICUSBCAP field. */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_NOTSELECTED (0x0UL) /*!< IC_USB PHY Interface is not selected */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_SELECTED (0x1UL) /*!< IC_USB PHY Interface is selected */ + +/* TXENDDELAY @Bit 28 : Mode: Device only. Tx End Delay (TxEndDelay) */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_Pos (28UL) /*!< Position of TXENDDELAY field. */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_Msk (0x1UL << USBHSCORE_GUSBCFG_TXENDDELAY_Pos) /*!< Bit mask of TXENDDELAY field. */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_Min (0x0UL) /*!< Min enumerator value of TXENDDELAY field. */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_Max (0x1UL) /*!< Max enumerator value of TXENDDELAY field. */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_DISABLED (0x0UL) /*!< Normal Mode */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_ENABLED (0x1UL) /*!< Tx End delay */ + +/* FORCEHSTMODE @Bit 29 : Mode: Host and device. Force Host Mode (ForceHstMode) */ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Pos (29UL) /*!< Position of FORCEHSTMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Msk (0x1UL << USBHSCORE_GUSBCFG_FORCEHSTMODE_Pos) /*!< Bit mask of FORCEHSTMODE field.*/ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Min (0x0UL) /*!< Min enumerator value of FORCEHSTMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Max (0x1UL) /*!< Max enumerator value of FORCEHSTMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_DISABLED (0x0UL) /*!< Normal Mode */ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_ENABLED (0x1UL) /*!< Force Host Mode */ + +/* FORCEDEVMODE @Bit 30 : Mode:Host and device. Force Device Mode (ForceDevMode) */ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Pos (30UL) /*!< Position of FORCEDEVMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Msk (0x1UL << USBHSCORE_GUSBCFG_FORCEDEVMODE_Pos) /*!< Bit mask of FORCEDEVMODE field.*/ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Min (0x0UL) /*!< Min enumerator value of FORCEDEVMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Max (0x1UL) /*!< Max enumerator value of FORCEDEVMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_DISABLED (0x0UL) /*!< Normal Mode */ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_ENABLED (0x1UL) /*!< Force Device Mode */ + +/* CORRUPTTXPKT @Bit 31 : Mode: Host and device. Corrupt Tx packet (CorruptTxPkt) */ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Pos (31UL) /*!< Position of CORRUPTTXPKT field. */ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Msk (0x1UL << USBHSCORE_GUSBCFG_CORRUPTTXPKT_Pos) /*!< Bit mask of CORRUPTTXPKT field.*/ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Min (0x0UL) /*!< Min enumerator value of CORRUPTTXPKT field. */ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Max (0x1UL) /*!< Max enumerator value of CORRUPTTXPKT field. */ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Disabled (0x0UL) /*!< Normal Mode */ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Enabled (0x1UL) /*!< Debug Mode */ + + +/* USBHSCORE_GRSTCTL: Reset Register */ + #define USBHSCORE_GRSTCTL_ResetValue (0x80000000UL) /*!< Reset value of GRSTCTL register. */ + +/* CSFTRST @Bit 0 : Mode: Host and Device. Core Soft Reset (CSftRst) */ + #define USBHSCORE_GRSTCTL_CSFTRST_Pos (0UL) /*!< Position of CSFTRST field. */ + #define USBHSCORE_GRSTCTL_CSFTRST_Msk (0x1UL << USBHSCORE_GRSTCTL_CSFTRST_Pos) /*!< Bit mask of CSFTRST field. */ + #define USBHSCORE_GRSTCTL_CSFTRST_Min (0x0UL) /*!< Min enumerator value of CSFTRST field. */ + #define USBHSCORE_GRSTCTL_CSFTRST_Max (0x1UL) /*!< Max enumerator value of CSFTRST field. */ + #define USBHSCORE_GRSTCTL_CSFTRST_NOTACTIVE (0x0UL) /*!< No reset */ + #define USBHSCORE_GRSTCTL_CSFTRST_ACTIVE (0x1UL) /*!< Resets hclk and phy_clock domains */ + +/* PIUFSSFTRST @Bit 1 : Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst) */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Pos (1UL) /*!< Position of PIUFSSFTRST field. */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Msk (0x1UL << USBHSCORE_GRSTCTL_PIUFSSFTRST_Pos) /*!< Bit mask of PIUFSSFTRST field. */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Min (0x0UL) /*!< Min enumerator value of PIUFSSFTRST field. */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Max (0x1UL) /*!< Max enumerator value of PIUFSSFTRST field. */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_RESETINACTIVE (0x0UL) /*!< No Reset */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_RESETACTIVE (0x1UL) /*!< PIU FS Dedicated Controller Soft Reset */ + +/* FRMCNTRRST @Bit 2 : Mode: Host only. Host Frame Counter Reset (FrmCntrRst) */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_Pos (2UL) /*!< Position of FRMCNTRRST field. */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_Msk (0x1UL << USBHSCORE_GRSTCTL_FRMCNTRRST_Pos) /*!< Bit mask of FRMCNTRRST field. */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_Min (0x0UL) /*!< Min enumerator value of FRMCNTRRST field. */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_Max (0x1UL) /*!< Max enumerator value of FRMCNTRRST field. */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_NOTACTIVE (0x0UL) /*!< No reset */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_ACTIVE (0x1UL) /*!< Host Frame Counter Reset */ + +/* RXFFLSH @Bit 4 : Mode: Host and Device. RxFIFO Flush (RxFFlsh) */ + #define USBHSCORE_GRSTCTL_RXFFLSH_Pos (4UL) /*!< Position of RXFFLSH field. */ + #define USBHSCORE_GRSTCTL_RXFFLSH_Msk (0x1UL << USBHSCORE_GRSTCTL_RXFFLSH_Pos) /*!< Bit mask of RXFFLSH field. */ + #define USBHSCORE_GRSTCTL_RXFFLSH_Min (0x0UL) /*!< Min enumerator value of RXFFLSH field. */ + #define USBHSCORE_GRSTCTL_RXFFLSH_Max (0x1UL) /*!< Max enumerator value of RXFFLSH field. */ + #define USBHSCORE_GRSTCTL_RXFFLSH_INACTIVE (0x0UL) /*!< Does not flush the entire RxFIFO */ + #define USBHSCORE_GRSTCTL_RXFFLSH_ACTIVE (0x1UL) /*!< Flushes the entire RxFIFO */ + +/* TXFFLSH @Bit 5 : Mode: Host and Device. TxFIFO Flush (TxFFlsh) */ + #define USBHSCORE_GRSTCTL_TXFFLSH_Pos (5UL) /*!< Position of TXFFLSH field. */ + #define USBHSCORE_GRSTCTL_TXFFLSH_Msk (0x1UL << USBHSCORE_GRSTCTL_TXFFLSH_Pos) /*!< Bit mask of TXFFLSH field. */ + #define USBHSCORE_GRSTCTL_TXFFLSH_Min (0x0UL) /*!< Min enumerator value of TXFFLSH field. */ + #define USBHSCORE_GRSTCTL_TXFFLSH_Max (0x1UL) /*!< Max enumerator value of TXFFLSH field. */ + #define USBHSCORE_GRSTCTL_TXFFLSH_INACTIVE (0x0UL) /*!< No Flush */ + #define USBHSCORE_GRSTCTL_TXFFLSH_ACTIVE (0x1UL) /*!< Selectively flushes a single or all transmit FIFOs */ + +/* TXFNUM @Bits 6..10 : Mode: Host and Device. TxFIFO Number (TxFNum) */ + #define USBHSCORE_GRSTCTL_TXFNUM_Pos (6UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_GRSTCTL_TXFNUM_Msk (0x1FUL << USBHSCORE_GRSTCTL_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_GRSTCTL_TXFNUM_Min (0x00UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_GRSTCTL_TXFNUM_Max (0x10UL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF0 (0x00UL) /*!< -Periodic TxFIFO flush in host mode -Periodic TxFIFO 0 flush in device + mode when in shared FIFO operation -TXFIFO 0 flush in device mode when + in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF1 (0x01UL) /*!< -Periodic TxFIFO flush in host mode -Periodic TxFIFO 1 flush in device + mode when in shared FIFO operation -TXFIFO 1 flush in device mode when + in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF2 (0x02UL) /*!< -Periodic TxFIFO 2 flush in device mode when in shared FIFO operation + -TXFIFO 2 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF3 (0x03UL) /*!< -Periodic TxFIFO 3 flush in device mode when in shared FIFO operation + -TXFIFO 3 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF4 (0x04UL) /*!< -Periodic TxFIFO 4 flush in device mode when in shared FIFO operation + -TXFIFO 4 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF5 (0x05UL) /*!< -Periodic TxFIFO 5 flush in device mode when in shared FIFO operation + -TXFIFO 5 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF6 (0x06UL) /*!< -Periodic TxFIFO 6 flush in device mode when in shared FIFO operation + -TXFIFO 6 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF7 (0x07UL) /*!< -Periodic TxFIFO 7 flush in device mode when in shared FIFO operation + -TXFIFO 7 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF8 (0x08UL) /*!< -Periodic TxFIFO 8 flush in device mode when in shared FIFO operation + -TXFIFO 8 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF9 (0x09UL) /*!< -Periodic TxFIFO 9 flush in device mode when in shared FIFO operation + -TXFIFO 9 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF10 (0x0AUL) /*!< -Periodic TxFIFO 10 flush in device mode when in shared FIFO operation + -TXFIFO 10 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF11 (0x0BUL) /*!< -Periodic TxFIFO 11 flush in device mode when in shared FIFO operation + -TXFIFO 11 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF12 (0x0CUL) /*!< -Periodic TxFIFO 12 flush in device mode when in shared FIFO operation + -TXFIFO 12 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF13 (0x0DUL) /*!< -Periodic TxFIFO 13 flush in Device mode when in shared FIFO operation + -TXFIFO 13 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF14 (0x0EUL) /*!< -Periodic TxFIFO 14 flush in Device mode when in shared FIFO operation + -TXFIFO 14 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF15 (0x0FUL) /*!< -Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation + - TXFIFO 15 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF16 (0x10UL) /*!< Flush all the transmit FIFOs in device or host mode */ + +/* CLOCKSWITCHTIMER @Bits 11..13 : This field is applicable if the controller is configured with multiple PHY interfaces. */ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_Pos (11UL) /*!< Position of CLOCKSWITCHTIMER field. */ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_Msk (0x7UL << USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_Pos) /*!< Bit mask of + CLOCKSWITCHTIMER field.*/ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_Min (0x0UL) /*!< Min enumerator value of CLOCKSWITCHTIMER field. */ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_Max (0x7UL) /*!< Max enumerator value of CLOCKSWITCHTIMER field. */ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_TIMERVALUE19 (0x0UL) /*!< timer value set to 19 */ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_TIMERVALUE15 (0x1UL) /*!< timer value set to 15 */ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_TIMERVALUE147 (0x2UL) /*!< timer value set to 147 */ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_TIMERVALUE50 (0x3UL) /*!< timer value set to 50 */ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_TIMERVALUE100 (0x4UL) /*!< timer value set to 100 */ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_TIMERVALUE125 (0x5UL) /*!< timer value set to 125 */ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_TIMERVALUE200 (0x6UL) /*!< timer value set to 200 */ + #define USBHSCORE_GRSTCTL_CLOCKSWITCHTIMER_TIMERDISABLED (0x7UL) /*!< timer is disabled */ + +/* CSFTRSTDONE @Bit 29 : Mode: Host and Device. Core Soft Reset Done (CSftRstDone) */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Pos (29UL) /*!< Position of CSFTRSTDONE field. */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Msk (0x1UL << USBHSCORE_GRSTCTL_CSFTRSTDONE_Pos) /*!< Bit mask of CSFTRSTDONE field. */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Min (0x0UL) /*!< Min enumerator value of CSFTRSTDONE field. */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Max (0x1UL) /*!< Max enumerator value of CSFTRSTDONE field. */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_INACTIVE (0x0UL) /*!< No reset */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_ACTIVE (0x1UL) /*!< Core Soft Reset is done */ + +/* DMAREQ @Bit 30 : Mode: Host and Device. DMA Request Signal (DMAReq) */ + #define USBHSCORE_GRSTCTL_DMAREQ_Pos (30UL) /*!< Position of DMAREQ field. */ + #define USBHSCORE_GRSTCTL_DMAREQ_Msk (0x1UL << USBHSCORE_GRSTCTL_DMAREQ_Pos) /*!< Bit mask of DMAREQ field. */ + #define USBHSCORE_GRSTCTL_DMAREQ_Min (0x0UL) /*!< Min enumerator value of DMAREQ field. */ + #define USBHSCORE_GRSTCTL_DMAREQ_Max (0x1UL) /*!< Max enumerator value of DMAREQ field. */ + #define USBHSCORE_GRSTCTL_DMAREQ_INACTIVE (0x0UL) /*!< No DMA request */ + #define USBHSCORE_GRSTCTL_DMAREQ_ACTIVE (0x1UL) /*!< DMA request is in progress */ + +/* AHBIDLE @Bit 31 : Mode: Host and Device. AHB Requester Idle (AHBIdle) */ + #define USBHSCORE_GRSTCTL_AHBIDLE_Pos (31UL) /*!< Position of AHBIDLE field. */ + #define USBHSCORE_GRSTCTL_AHBIDLE_Msk (0x1UL << USBHSCORE_GRSTCTL_AHBIDLE_Pos) /*!< Bit mask of AHBIDLE field. */ + #define USBHSCORE_GRSTCTL_AHBIDLE_Min (0x0UL) /*!< Min enumerator value of AHBIDLE field. */ + #define USBHSCORE_GRSTCTL_AHBIDLE_Max (0x1UL) /*!< Max enumerator value of AHBIDLE field. */ + #define USBHSCORE_GRSTCTL_AHBIDLE_INACTIVE (0x0UL) /*!< Not Idle */ + #define USBHSCORE_GRSTCTL_AHBIDLE_ACTIVE (0x1UL) /*!< AHB Requester Idle */ + + +/* USBHSCORE_GINTSTS: Interrupt STATUS Register */ + #define USBHSCORE_GINTSTS_ResetValue (0x04000020UL) /*!< Reset value of GINTSTS register. */ + +/* CURMOD @Bit 0 : Mode: Host and Device. Current Mode of Operation (CurMod) */ + #define USBHSCORE_GINTSTS_CURMOD_Pos (0UL) /*!< Position of CURMOD field. */ + #define USBHSCORE_GINTSTS_CURMOD_Msk (0x1UL << USBHSCORE_GINTSTS_CURMOD_Pos) /*!< Bit mask of CURMOD field. */ + #define USBHSCORE_GINTSTS_CURMOD_Min (0x0UL) /*!< Min enumerator value of CURMOD field. */ + #define USBHSCORE_GINTSTS_CURMOD_Max (0x1UL) /*!< Max enumerator value of CURMOD field. */ + #define USBHSCORE_GINTSTS_CURMOD_DEVICE (0x0UL) /*!< Device mode */ + #define USBHSCORE_GINTSTS_CURMOD_HOST (0x1UL) /*!< Host mode */ + +/* MODEMIS @Bit 1 : Mode: Host and Device. Mode Mismatch Interrupt (ModeMis) */ + #define USBHSCORE_GINTSTS_MODEMIS_Pos (1UL) /*!< Position of MODEMIS field. */ + #define USBHSCORE_GINTSTS_MODEMIS_Msk (0x1UL << USBHSCORE_GINTSTS_MODEMIS_Pos) /*!< Bit mask of MODEMIS field. */ + #define USBHSCORE_GINTSTS_MODEMIS_Min (0x0UL) /*!< Min enumerator value of MODEMIS field. */ + #define USBHSCORE_GINTSTS_MODEMIS_Max (0x1UL) /*!< Max enumerator value of MODEMIS field. */ + #define USBHSCORE_GINTSTS_MODEMIS_INACTIVE (0x0UL) /*!< No Mode Mismatch Interrupt */ + #define USBHSCORE_GINTSTS_MODEMIS_ACTIVE (0x1UL) /*!< Mode Mismatch Interrupt */ + +/* OTGINT @Bit 2 : Mode: Host and Device. OTG Interrupt (OTGInt) */ + #define USBHSCORE_GINTSTS_OTGINT_Pos (2UL) /*!< Position of OTGINT field. */ + #define USBHSCORE_GINTSTS_OTGINT_Msk (0x1UL << USBHSCORE_GINTSTS_OTGINT_Pos) /*!< Bit mask of OTGINT field. */ + #define USBHSCORE_GINTSTS_OTGINT_Min (0x0UL) /*!< Min enumerator value of OTGINT field. */ + #define USBHSCORE_GINTSTS_OTGINT_Max (0x1UL) /*!< Max enumerator value of OTGINT field. */ + #define USBHSCORE_GINTSTS_OTGINT_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_GINTSTS_OTGINT_ACTIVE (0x1UL) /*!< OTG Interrupt */ + +/* SOF @Bit 3 : Mode: Host and Device. Start of (micro)Frame (Sof) */ + #define USBHSCORE_GINTSTS_SOF_Pos (3UL) /*!< Position of SOF field. */ + #define USBHSCORE_GINTSTS_SOF_Msk (0x1UL << USBHSCORE_GINTSTS_SOF_Pos) /*!< Bit mask of SOF field. */ + #define USBHSCORE_GINTSTS_SOF_Min (0x0UL) /*!< Min enumerator value of SOF field. */ + #define USBHSCORE_GINTSTS_SOF_Max (0x1UL) /*!< Max enumerator value of SOF field. */ + #define USBHSCORE_GINTSTS_SOF_INACTIVE (0x0UL) /*!< No Start of Frame */ + #define USBHSCORE_GINTSTS_SOF_ACTIVE (0x1UL) /*!< Start of Frame */ + +/* RXFLVL @Bit 4 : Mode: Host and Device. RxFIFO Non-Empty (RxFLvl) */ + #define USBHSCORE_GINTSTS_RXFLVL_Pos (4UL) /*!< Position of RXFLVL field. */ + #define USBHSCORE_GINTSTS_RXFLVL_Msk (0x1UL << USBHSCORE_GINTSTS_RXFLVL_Pos) /*!< Bit mask of RXFLVL field. */ + #define USBHSCORE_GINTSTS_RXFLVL_Min (0x0UL) /*!< Min enumerator value of RXFLVL field. */ + #define USBHSCORE_GINTSTS_RXFLVL_Max (0x1UL) /*!< Max enumerator value of RXFLVL field. */ + #define USBHSCORE_GINTSTS_RXFLVL_INACTIVE (0x0UL) /*!< Rx Fifo is empty */ + #define USBHSCORE_GINTSTS_RXFLVL_ACTIVE (0x1UL) /*!< Rx Fifo is not empty */ + +/* NPTXFEMP @Bit 5 : Mode: Host and Device. Non-periodic TxFIFO Empty (NPTxFEmp) */ + #define USBHSCORE_GINTSTS_NPTXFEMP_Pos (5UL) /*!< Position of NPTXFEMP field. */ + #define USBHSCORE_GINTSTS_NPTXFEMP_Msk (0x1UL << USBHSCORE_GINTSTS_NPTXFEMP_Pos) /*!< Bit mask of NPTXFEMP field. */ + #define USBHSCORE_GINTSTS_NPTXFEMP_Min (0x0UL) /*!< Min enumerator value of NPTXFEMP field. */ + #define USBHSCORE_GINTSTS_NPTXFEMP_Max (0x1UL) /*!< Max enumerator value of NPTXFEMP field. */ + #define USBHSCORE_GINTSTS_NPTXFEMP_INACTIVE (0x0UL) /*!< Non-periodic TxFIFO is not empty */ + #define USBHSCORE_GINTSTS_NPTXFEMP_ACTIVE (0x1UL) /*!< Non-periodic TxFIFO is empty */ + +/* GINNAKEFF @Bit 6 : Mode: Device only. Global IN Non-periodic NAK Effective (GINNakEff) */ + #define USBHSCORE_GINTSTS_GINNAKEFF_Pos (6UL) /*!< Position of GINNAKEFF field. */ + #define USBHSCORE_GINTSTS_GINNAKEFF_Msk (0x1UL << USBHSCORE_GINTSTS_GINNAKEFF_Pos) /*!< Bit mask of GINNAKEFF field. */ + #define USBHSCORE_GINTSTS_GINNAKEFF_Min (0x0UL) /*!< Min enumerator value of GINNAKEFF field. */ + #define USBHSCORE_GINTSTS_GINNAKEFF_Max (0x1UL) /*!< Max enumerator value of GINNAKEFF field. */ + #define USBHSCORE_GINTSTS_GINNAKEFF_INACTIVE (0x0UL) /*!< Global Non-periodic IN NAK not active */ + #define USBHSCORE_GINTSTS_GINNAKEFF_ACTIVE (0x1UL) /*!< Set Global Non-periodic IN NAK bit */ + +/* GOUTNAKEFF @Bit 7 : Mode: Device only. Global OUT NAK Effective (GOUTNakEff) */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_Pos (7UL) /*!< Position of GOUTNAKEFF field. */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_Msk (0x1UL << USBHSCORE_GINTSTS_GOUTNAKEFF_Pos) /*!< Bit mask of GOUTNAKEFF field. */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_Min (0x0UL) /*!< Min enumerator value of GOUTNAKEFF field. */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_Max (0x1UL) /*!< Max enumerator value of GOUTNAKEFF field. */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_INACTIVE (0x0UL) /*!< Not Active */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_ACTIVE (0x1UL) /*!< Global OUT NAK Effective */ + +/* ERLYSUSP @Bit 10 : Mode: Device only. Early Suspend (ErlySusp) */ + #define USBHSCORE_GINTSTS_ERLYSUSP_Pos (10UL) /*!< Position of ERLYSUSP field. */ + #define USBHSCORE_GINTSTS_ERLYSUSP_Msk (0x1UL << USBHSCORE_GINTSTS_ERLYSUSP_Pos) /*!< Bit mask of ERLYSUSP field. */ + #define USBHSCORE_GINTSTS_ERLYSUSP_Min (0x0UL) /*!< Min enumerator value of ERLYSUSP field. */ + #define USBHSCORE_GINTSTS_ERLYSUSP_Max (0x1UL) /*!< Max enumerator value of ERLYSUSP field. */ + #define USBHSCORE_GINTSTS_ERLYSUSP_INACTIVE (0x0UL) /*!< No Idle state detected */ + #define USBHSCORE_GINTSTS_ERLYSUSP_ACTIVE (0x1UL) /*!< 3ms of Idle state detected */ + +/* USBSUSP @Bit 11 : Mode: Device only. USB Suspend (USBSusp) */ + #define USBHSCORE_GINTSTS_USBSUSP_Pos (11UL) /*!< Position of USBSUSP field. */ + #define USBHSCORE_GINTSTS_USBSUSP_Msk (0x1UL << USBHSCORE_GINTSTS_USBSUSP_Pos) /*!< Bit mask of USBSUSP field. */ + #define USBHSCORE_GINTSTS_USBSUSP_Min (0x0UL) /*!< Min enumerator value of USBSUSP field. */ + #define USBHSCORE_GINTSTS_USBSUSP_Max (0x1UL) /*!< Max enumerator value of USBSUSP field. */ + #define USBHSCORE_GINTSTS_USBSUSP_INACTIVE (0x0UL) /*!< Not Active */ + #define USBHSCORE_GINTSTS_USBSUSP_ACTIVE (0x1UL) /*!< USB Suspend */ + +/* USBRST @Bit 12 : Mode: Device only. USB Reset (USBRst) */ + #define USBHSCORE_GINTSTS_USBRST_Pos (12UL) /*!< Position of USBRST field. */ + #define USBHSCORE_GINTSTS_USBRST_Msk (0x1UL << USBHSCORE_GINTSTS_USBRST_Pos) /*!< Bit mask of USBRST field. */ + #define USBHSCORE_GINTSTS_USBRST_Min (0x0UL) /*!< Min enumerator value of USBRST field. */ + #define USBHSCORE_GINTSTS_USBRST_Max (0x1UL) /*!< Max enumerator value of USBRST field. */ + #define USBHSCORE_GINTSTS_USBRST_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_USBRST_ACTIVE (0x1UL) /*!< USB Reset */ + +/* ENUMDONE @Bit 13 : Mode: Device only. Enumeration Done (EnumDone) */ + #define USBHSCORE_GINTSTS_ENUMDONE_Pos (13UL) /*!< Position of ENUMDONE field. */ + #define USBHSCORE_GINTSTS_ENUMDONE_Msk (0x1UL << USBHSCORE_GINTSTS_ENUMDONE_Pos) /*!< Bit mask of ENUMDONE field. */ + #define USBHSCORE_GINTSTS_ENUMDONE_Min (0x0UL) /*!< Min enumerator value of ENUMDONE field. */ + #define USBHSCORE_GINTSTS_ENUMDONE_Max (0x1UL) /*!< Max enumerator value of ENUMDONE field. */ + #define USBHSCORE_GINTSTS_ENUMDONE_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_ENUMDONE_ACTIVE (0x1UL) /*!< Enumeration Done */ + +/* ISOOUTDROP @Bit 14 : Mode: Device only. Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_Pos (14UL) /*!< Position of ISOOUTDROP field. */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_Msk (0x1UL << USBHSCORE_GINTSTS_ISOOUTDROP_Pos) /*!< Bit mask of ISOOUTDROP field. */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_Min (0x0UL) /*!< Min enumerator value of ISOOUTDROP field. */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_Max (0x1UL) /*!< Max enumerator value of ISOOUTDROP field. */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_ACTIVE (0x1UL) /*!< Isochronous OUT Packet Dropped Interrupt */ + +/* EOPF @Bit 15 : Mode: Device only. End of Periodic Frame Interrupt (EOPF) */ + #define USBHSCORE_GINTSTS_EOPF_Pos (15UL) /*!< Position of EOPF field. */ + #define USBHSCORE_GINTSTS_EOPF_Msk (0x1UL << USBHSCORE_GINTSTS_EOPF_Pos) /*!< Bit mask of EOPF field. */ + #define USBHSCORE_GINTSTS_EOPF_Min (0x0UL) /*!< Min enumerator value of EOPF field. */ + #define USBHSCORE_GINTSTS_EOPF_Max (0x1UL) /*!< Max enumerator value of EOPF field. */ + #define USBHSCORE_GINTSTS_EOPF_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_EOPF_ACTIVE (0x1UL) /*!< End of Periodic Frame Interrupt */ + +/* RSTRDONEINT @Bit 16 : Mode: Device only. Restore Done Interrupt (RstrDoneInt) */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_Pos (16UL) /*!< Position of RSTRDONEINT field. */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_Msk (0x1UL << USBHSCORE_GINTSTS_RSTRDONEINT_Pos) /*!< Bit mask of RSTRDONEINT field. */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_Min (0x0UL) /*!< Min enumerator value of RSTRDONEINT field. */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_Max (0x1UL) /*!< Max enumerator value of RSTRDONEINT field. */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_ACTIVE (0x1UL) /*!< Restore Done Interrupt */ + +/* EPMIS @Bit 17 : Mode: Device only. Endpoint Mismatch Interrupt (EPMis) */ + #define USBHSCORE_GINTSTS_EPMIS_Pos (17UL) /*!< Position of EPMIS field. */ + #define USBHSCORE_GINTSTS_EPMIS_Msk (0x1UL << USBHSCORE_GINTSTS_EPMIS_Pos) /*!< Bit mask of EPMIS field. */ + #define USBHSCORE_GINTSTS_EPMIS_Min (0x0UL) /*!< Min enumerator value of EPMIS field. */ + #define USBHSCORE_GINTSTS_EPMIS_Max (0x1UL) /*!< Max enumerator value of EPMIS field. */ + #define USBHSCORE_GINTSTS_EPMIS_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_EPMIS_ACTIVE (0x1UL) /*!< Endpoint Mismatch Interrupt */ + +/* IEPINT @Bit 18 : Mode: Device only. IN Endpoints Interrupt (IEPInt) */ + #define USBHSCORE_GINTSTS_IEPINT_Pos (18UL) /*!< Position of IEPINT field. */ + #define USBHSCORE_GINTSTS_IEPINT_Msk (0x1UL << USBHSCORE_GINTSTS_IEPINT_Pos) /*!< Bit mask of IEPINT field. */ + #define USBHSCORE_GINTSTS_IEPINT_Min (0x0UL) /*!< Min enumerator value of IEPINT field. */ + #define USBHSCORE_GINTSTS_IEPINT_Max (0x1UL) /*!< Max enumerator value of IEPINT field. */ + #define USBHSCORE_GINTSTS_IEPINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_IEPINT_ACTIVE (0x1UL) /*!< IN Endpoints Interrupt */ + +/* OEPINT @Bit 19 : Mode: Device only. OUT Endpoints Interrupt (OEPInt) */ + #define USBHSCORE_GINTSTS_OEPINT_Pos (19UL) /*!< Position of OEPINT field. */ + #define USBHSCORE_GINTSTS_OEPINT_Msk (0x1UL << USBHSCORE_GINTSTS_OEPINT_Pos) /*!< Bit mask of OEPINT field. */ + #define USBHSCORE_GINTSTS_OEPINT_Min (0x0UL) /*!< Min enumerator value of OEPINT field. */ + #define USBHSCORE_GINTSTS_OEPINT_Max (0x1UL) /*!< Max enumerator value of OEPINT field. */ + #define USBHSCORE_GINTSTS_OEPINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_OEPINT_ACTIVE (0x1UL) /*!< OUT Endpoints Interrupt */ + +/* INCOMPISOIN @Bit 20 : Mode: Device only. Incomplete Isochronous IN Transfer (incompISOIN) */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_Pos (20UL) /*!< Position of INCOMPISOIN field. */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_Msk (0x1UL << USBHSCORE_GINTSTS_INCOMPISOIN_Pos) /*!< Bit mask of INCOMPISOIN field. */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_Min (0x0UL) /*!< Min enumerator value of INCOMPISOIN field. */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_Max (0x1UL) /*!< Max enumerator value of INCOMPISOIN field. */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_ACTIVE (0x1UL) /*!< Incomplete Isochronous IN Transfer */ + +/* INCOMPLP @Bit 21 : Incomplete Periodic Transfer (incomplP) */ + #define USBHSCORE_GINTSTS_INCOMPLP_Pos (21UL) /*!< Position of INCOMPLP field. */ + #define USBHSCORE_GINTSTS_INCOMPLP_Msk (0x1UL << USBHSCORE_GINTSTS_INCOMPLP_Pos) /*!< Bit mask of INCOMPLP field. */ + #define USBHSCORE_GINTSTS_INCOMPLP_Min (0x0UL) /*!< Min enumerator value of INCOMPLP field. */ + #define USBHSCORE_GINTSTS_INCOMPLP_Max (0x1UL) /*!< Max enumerator value of INCOMPLP field. */ + #define USBHSCORE_GINTSTS_INCOMPLP_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_INCOMPLP_ACTIVE (0x1UL) /*!< Incomplete Periodic Transfer */ + +/* FETSUSP @Bit 22 : Mode: Device only. Data Fetch Suspended (FetSusp) */ + #define USBHSCORE_GINTSTS_FETSUSP_Pos (22UL) /*!< Position of FETSUSP field. */ + #define USBHSCORE_GINTSTS_FETSUSP_Msk (0x1UL << USBHSCORE_GINTSTS_FETSUSP_Pos) /*!< Bit mask of FETSUSP field. */ + #define USBHSCORE_GINTSTS_FETSUSP_Min (0x0UL) /*!< Min enumerator value of FETSUSP field. */ + #define USBHSCORE_GINTSTS_FETSUSP_Max (0x1UL) /*!< Max enumerator value of FETSUSP field. */ + #define USBHSCORE_GINTSTS_FETSUSP_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_FETSUSP_ACTIVE (0x1UL) /*!< Data Fetch Suspended */ + +/* RESETDET @Bit 23 : Mode: Device only. Reset detected Interrupt (ResetDet) */ + #define USBHSCORE_GINTSTS_RESETDET_Pos (23UL) /*!< Position of RESETDET field. */ + #define USBHSCORE_GINTSTS_RESETDET_Msk (0x1UL << USBHSCORE_GINTSTS_RESETDET_Pos) /*!< Bit mask of RESETDET field. */ + #define USBHSCORE_GINTSTS_RESETDET_Min (0x0UL) /*!< Min enumerator value of RESETDET field. */ + #define USBHSCORE_GINTSTS_RESETDET_Max (0x1UL) /*!< Max enumerator value of RESETDET field. */ + #define USBHSCORE_GINTSTS_RESETDET_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_RESETDET_ACTIVE (0x1UL) /*!< Reset detected Interrupt */ + +/* PRTINT @Bit 24 : Mode: Host only. Host Port Interrupt (PrtInt) */ + #define USBHSCORE_GINTSTS_PRTINT_Pos (24UL) /*!< Position of PRTINT field. */ + #define USBHSCORE_GINTSTS_PRTINT_Msk (0x1UL << USBHSCORE_GINTSTS_PRTINT_Pos) /*!< Bit mask of PRTINT field. */ + #define USBHSCORE_GINTSTS_PRTINT_Min (0x0UL) /*!< Min enumerator value of PRTINT field. */ + #define USBHSCORE_GINTSTS_PRTINT_Max (0x1UL) /*!< Max enumerator value of PRTINT field. */ + #define USBHSCORE_GINTSTS_PRTINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_PRTINT_ACTIVE (0x1UL) /*!< Host Port Interrupt */ + +/* HCHINT @Bit 25 : Mode: Host only. Host Channels Interrupt (HChInt) */ + #define USBHSCORE_GINTSTS_HCHINT_Pos (25UL) /*!< Position of HCHINT field. */ + #define USBHSCORE_GINTSTS_HCHINT_Msk (0x1UL << USBHSCORE_GINTSTS_HCHINT_Pos) /*!< Bit mask of HCHINT field. */ + #define USBHSCORE_GINTSTS_HCHINT_Min (0x0UL) /*!< Min enumerator value of HCHINT field. */ + #define USBHSCORE_GINTSTS_HCHINT_Max (0x1UL) /*!< Max enumerator value of HCHINT field. */ + #define USBHSCORE_GINTSTS_HCHINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_HCHINT_ACTIVE (0x1UL) /*!< Host Channels Interrupt */ + +/* PTXFEMP @Bit 26 : Mode: Host only. Periodic TxFIFO Empty (PTxFEmp) */ + #define USBHSCORE_GINTSTS_PTXFEMP_Pos (26UL) /*!< Position of PTXFEMP field. */ + #define USBHSCORE_GINTSTS_PTXFEMP_Msk (0x1UL << USBHSCORE_GINTSTS_PTXFEMP_Pos) /*!< Bit mask of PTXFEMP field. */ + #define USBHSCORE_GINTSTS_PTXFEMP_Min (0x0UL) /*!< Min enumerator value of PTXFEMP field. */ + #define USBHSCORE_GINTSTS_PTXFEMP_Max (0x1UL) /*!< Max enumerator value of PTXFEMP field. */ + #define USBHSCORE_GINTSTS_PTXFEMP_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_PTXFEMP_ACTIVE (0x1UL) /*!< Periodic TxFIFO Empty */ + +/* LPMINT @Bit 27 : Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int). */ + #define USBHSCORE_GINTSTS_LPMINT_Pos (27UL) /*!< Position of LPMINT field. */ + #define USBHSCORE_GINTSTS_LPMINT_Msk (0x1UL << USBHSCORE_GINTSTS_LPMINT_Pos) /*!< Bit mask of LPMINT field. */ + #define USBHSCORE_GINTSTS_LPMINT_Min (0x0UL) /*!< Min enumerator value of LPMINT field. */ + #define USBHSCORE_GINTSTS_LPMINT_Max (0x1UL) /*!< Max enumerator value of LPMINT field. */ + #define USBHSCORE_GINTSTS_LPMINT_INACTIVE (0x0UL) /*!< Not Active */ + #define USBHSCORE_GINTSTS_LPMINT_ACTIVE (0x1UL) /*!< LPM Transaction Received Interrupt */ + +/* CONIDSTSCHNG @Bit 28 : Mode: Host and Device. Connector ID Status Change (ConIDStsChng) */ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Pos (28UL) /*!< Position of CONIDSTSCHNG field. */ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Msk (0x1UL << USBHSCORE_GINTSTS_CONIDSTSCHNG_Pos) /*!< Bit mask of CONIDSTSCHNG field.*/ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Min (0x0UL) /*!< Min enumerator value of CONIDSTSCHNG field. */ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Max (0x1UL) /*!< Max enumerator value of CONIDSTSCHNG field. */ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_INACTIVE (0x0UL) /*!< Not Active */ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_ACTIVE (0x1UL) /*!< Connector ID Status Change */ + +/* DISCONNINT @Bit 29 : Mode: Host only. Disconnect Detected Interrupt (DisconnInt) */ + #define USBHSCORE_GINTSTS_DISCONNINT_Pos (29UL) /*!< Position of DISCONNINT field. */ + #define USBHSCORE_GINTSTS_DISCONNINT_Msk (0x1UL << USBHSCORE_GINTSTS_DISCONNINT_Pos) /*!< Bit mask of DISCONNINT field. */ + #define USBHSCORE_GINTSTS_DISCONNINT_Min (0x0UL) /*!< Min enumerator value of DISCONNINT field. */ + #define USBHSCORE_GINTSTS_DISCONNINT_Max (0x1UL) /*!< Max enumerator value of DISCONNINT field. */ + #define USBHSCORE_GINTSTS_DISCONNINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_DISCONNINT_ACTIVE (0x1UL) /*!< Disconnect Detected Interrupt */ + +/* SESSREQINT @Bit 30 : Mode: Host and Device. Session Request/New Session Detected Interrupt (SessReqInt) */ + #define USBHSCORE_GINTSTS_SESSREQINT_Pos (30UL) /*!< Position of SESSREQINT field. */ + #define USBHSCORE_GINTSTS_SESSREQINT_Msk (0x1UL << USBHSCORE_GINTSTS_SESSREQINT_Pos) /*!< Bit mask of SESSREQINT field. */ + #define USBHSCORE_GINTSTS_SESSREQINT_Min (0x0UL) /*!< Min enumerator value of SESSREQINT field. */ + #define USBHSCORE_GINTSTS_SESSREQINT_Max (0x1UL) /*!< Max enumerator value of SESSREQINT field. */ + #define USBHSCORE_GINTSTS_SESSREQINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_SESSREQINT_ACTIVE (0x1UL) /*!< Session Request New Session Detected Interrupt */ + +/* WKUPINT @Bit 31 : Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt (WkUpInt) */ + #define USBHSCORE_GINTSTS_WKUPINT_Pos (31UL) /*!< Position of WKUPINT field. */ + #define USBHSCORE_GINTSTS_WKUPINT_Msk (0x1UL << USBHSCORE_GINTSTS_WKUPINT_Pos) /*!< Bit mask of WKUPINT field. */ + #define USBHSCORE_GINTSTS_WKUPINT_Min (0x0UL) /*!< Min enumerator value of WKUPINT field. */ + #define USBHSCORE_GINTSTS_WKUPINT_Max (0x1UL) /*!< Max enumerator value of WKUPINT field. */ + #define USBHSCORE_GINTSTS_WKUPINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_WKUPINT_ACTIVE (0x1UL) /*!< Resume or Remote Wakeup Detected Interrupt */ + + +/* USBHSCORE_GINTMSK: Interrupt Mask Register */ + #define USBHSCORE_GINTMSK_ResetValue (0x00000000UL) /*!< Reset value of GINTMSK register. */ + +/* MODEMISMSK @Bit 1 : Mode: Host and Device. Mode Mismatch Interrupt Mask (ModeMisMsk) */ + #define USBHSCORE_GINTMSK_MODEMISMSK_Pos (1UL) /*!< Position of MODEMISMSK field. */ + #define USBHSCORE_GINTMSK_MODEMISMSK_Msk (0x1UL << USBHSCORE_GINTMSK_MODEMISMSK_Pos) /*!< Bit mask of MODEMISMSK field. */ + #define USBHSCORE_GINTMSK_MODEMISMSK_Min (0x0UL) /*!< Min enumerator value of MODEMISMSK field. */ + #define USBHSCORE_GINTMSK_MODEMISMSK_Max (0x1UL) /*!< Max enumerator value of MODEMISMSK field. */ + #define USBHSCORE_GINTMSK_MODEMISMSK_MASK (0x0UL) /*!< Mode Mismatch Interrupt Mask */ + #define USBHSCORE_GINTMSK_MODEMISMSK_NOMASK (0x1UL) /*!< No Mode Mismatch Interrupt Mask */ + +/* OTGINTMSK @Bit 2 : Mode: Host and Device. OTG Interrupt Mask (OTGIntMsk) */ + #define USBHSCORE_GINTMSK_OTGINTMSK_Pos (2UL) /*!< Position of OTGINTMSK field. */ + #define USBHSCORE_GINTMSK_OTGINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_OTGINTMSK_Pos) /*!< Bit mask of OTGINTMSK field. */ + #define USBHSCORE_GINTMSK_OTGINTMSK_Min (0x0UL) /*!< Min enumerator value of OTGINTMSK field. */ + #define USBHSCORE_GINTMSK_OTGINTMSK_Max (0x1UL) /*!< Max enumerator value of OTGINTMSK field. */ + #define USBHSCORE_GINTMSK_OTGINTMSK_MASK (0x0UL) /*!< OTG Interrupt Mask */ + #define USBHSCORE_GINTMSK_OTGINTMSK_NOMASK (0x1UL) /*!< No OTG Interrupt Mask */ + +/* SOFMSK @Bit 3 : Mode: Host and Device. Start of (micro)Frame Mask (SofMsk) */ + #define USBHSCORE_GINTMSK_SOFMSK_Pos (3UL) /*!< Position of SOFMSK field. */ + #define USBHSCORE_GINTMSK_SOFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_SOFMSK_Pos) /*!< Bit mask of SOFMSK field. */ + #define USBHSCORE_GINTMSK_SOFMSK_Min (0x0UL) /*!< Min enumerator value of SOFMSK field. */ + #define USBHSCORE_GINTMSK_SOFMSK_Max (0x1UL) /*!< Max enumerator value of SOFMSK field. */ + #define USBHSCORE_GINTMSK_SOFMSK_MASK (0x0UL) /*!< Start of Frame Mask */ + #define USBHSCORE_GINTMSK_SOFMSK_NOMASK (0x1UL) /*!< No Start of Frame Mask */ + +/* RXFLVLMSK @Bit 4 : Mode: Host and Device. Receive FIFO Non-Empty Mask (RxFLvlMsk) */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_Pos (4UL) /*!< Position of RXFLVLMSK field. */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_Msk (0x1UL << USBHSCORE_GINTMSK_RXFLVLMSK_Pos) /*!< Bit mask of RXFLVLMSK field. */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_Min (0x0UL) /*!< Min enumerator value of RXFLVLMSK field. */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_Max (0x1UL) /*!< Max enumerator value of RXFLVLMSK field. */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_MASK (0x0UL) /*!< Receive FIFO Non-Empty Mask */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_NOMASK (0x1UL) /*!< No Receive FIFO Non-Empty Mask */ + +/* NPTXFEMPMSK @Bit 5 : Mode: Host and Device. Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk) */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Pos (5UL) /*!< Position of NPTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_NPTXFEMPMSK_Pos) /*!< Bit mask of NPTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Min (0x0UL) /*!< Min enumerator value of NPTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Max (0x1UL) /*!< Max enumerator value of NPTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_MASK (0x0UL) /*!< Non-periodic TxFIFO Empty Mask */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_NOMASK (0x1UL) /*!< No Non-periodic TxFIFO Empty Mask */ + +/* GINNAKEFFMSK @Bit 6 : Mode: Device only,. Global Non-periodic IN NAK Effective Mask (GINNakEffMsk) */ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Pos (6UL) /*!< Position of GINNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_GINNAKEFFMSK_Pos) /*!< Bit mask of GINNAKEFFMSK field.*/ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Min (0x0UL) /*!< Min enumerator value of GINNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Max (0x1UL) /*!< Max enumerator value of GINNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_MASK (0x0UL) /*!< Global Non-periodic IN NAK Effective Mask */ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_NOMASK (0x1UL) /*!< No Global Non-periodic IN NAK Effective Mask */ + +/* GOUTNAKEFFMSK @Bit 7 : Mode: Device only. Global OUT NAK Effective Mask (GOUTNakEffMsk) */ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Pos (7UL) /*!< Position of GOUTNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Pos) /*!< Bit mask of GOUTNAKEFFMSK + field.*/ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Min (0x0UL) /*!< Min enumerator value of GOUTNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Max (0x1UL) /*!< Max enumerator value of GOUTNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_MASK (0x0UL) /*!< Global OUT NAK Effective Mask */ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_NOMASK (0x1UL) /*!< No Global OUT NAK Effective Mask */ + +/* ERLYSUSPMSK @Bit 10 : Mode: Device only. Early Suspend Mask (ErlySuspMsk) */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Pos (10UL) /*!< Position of ERLYSUSPMSK field. */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_ERLYSUSPMSK_Pos) /*!< Bit mask of ERLYSUSPMSK field. */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Min (0x0UL) /*!< Min enumerator value of ERLYSUSPMSK field. */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Max (0x1UL) /*!< Max enumerator value of ERLYSUSPMSK field. */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_MASK (0x0UL) /*!< Early Suspend Mask */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_NOMASK (0x1UL) /*!< No Early Suspend Mask */ + +/* USBSUSPMSK @Bit 11 : Mode: Device only. USB Suspend Mask (USBSuspMsk) */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_Pos (11UL) /*!< Position of USBSUSPMSK field. */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_USBSUSPMSK_Pos) /*!< Bit mask of USBSUSPMSK field. */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_Min (0x0UL) /*!< Min enumerator value of USBSUSPMSK field. */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_Max (0x1UL) /*!< Max enumerator value of USBSUSPMSK field. */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_MASK (0x0UL) /*!< USB Suspend Mask */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_NOMASK (0x1UL) /*!< No USB Suspend Mask */ + +/* USBRSTMSK @Bit 12 : Mode: Device only. USB Reset Mask (USBRstMsk) */ + #define USBHSCORE_GINTMSK_USBRSTMSK_Pos (12UL) /*!< Position of USBRSTMSK field. */ + #define USBHSCORE_GINTMSK_USBRSTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_USBRSTMSK_Pos) /*!< Bit mask of USBRSTMSK field. */ + #define USBHSCORE_GINTMSK_USBRSTMSK_Min (0x0UL) /*!< Min enumerator value of USBRSTMSK field. */ + #define USBHSCORE_GINTMSK_USBRSTMSK_Max (0x1UL) /*!< Max enumerator value of USBRSTMSK field. */ + #define USBHSCORE_GINTMSK_USBRSTMSK_MASK (0x0UL) /*!< USB Reset Mask */ + #define USBHSCORE_GINTMSK_USBRSTMSK_NOMASK (0x1UL) /*!< No USB Reset Mask */ + +/* ENUMDONEMSK @Bit 13 : Mode: Device only. Enumeration Done Mask (EnumDoneMsk) */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_Pos (13UL) /*!< Position of ENUMDONEMSK field. */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_Msk (0x1UL << USBHSCORE_GINTMSK_ENUMDONEMSK_Pos) /*!< Bit mask of ENUMDONEMSK field. */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_Min (0x0UL) /*!< Min enumerator value of ENUMDONEMSK field. */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_Max (0x1UL) /*!< Max enumerator value of ENUMDONEMSK field. */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_MASK (0x0UL) /*!< Enumeration Done Mask */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_NOMASK (0x1UL) /*!< No Enumeration Done Mask */ + +/* ISOOUTDROPMSK @Bit 14 : Mode: Device only. Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk) */ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Pos (14UL) /*!< Position of ISOOUTDROPMSK field. */ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_ISOOUTDROPMSK_Pos) /*!< Bit mask of ISOOUTDROPMSK + field.*/ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Min (0x0UL) /*!< Min enumerator value of ISOOUTDROPMSK field. */ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Max (0x1UL) /*!< Max enumerator value of ISOOUTDROPMSK field. */ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_MASK (0x0UL) /*!< Isochronous OUT Packet Dropped Interrupt Mask */ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_NOMASK (0x1UL) /*!< No Isochronous OUT Packet Dropped Interrupt Mask */ + +/* EOPFMSK @Bit 15 : Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk) */ + #define USBHSCORE_GINTMSK_EOPFMSK_Pos (15UL) /*!< Position of EOPFMSK field. */ + #define USBHSCORE_GINTMSK_EOPFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_EOPFMSK_Pos) /*!< Bit mask of EOPFMSK field. */ + #define USBHSCORE_GINTMSK_EOPFMSK_Min (0x0UL) /*!< Min enumerator value of EOPFMSK field. */ + #define USBHSCORE_GINTMSK_EOPFMSK_Max (0x1UL) /*!< Max enumerator value of EOPFMSK field. */ + #define USBHSCORE_GINTMSK_EOPFMSK_MASK (0x0UL) /*!< End of Periodic Frame Interrupt Mask */ + #define USBHSCORE_GINTMSK_EOPFMSK_NOMASK (0x1UL) /*!< No End of Periodic Frame Interrupt Mask */ + +/* RSTRDONEINTMSK @Bit 16 : Mode: Host and Device. Restore Done Interrupt Mask (RstrDoneIntMsk) */ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Pos (16UL) /*!< Position of RSTRDONEINTMSK field. */ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_RSTRDONEINTMSK_Pos) /*!< Bit mask of RSTRDONEINTMSK + field.*/ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Min (0x0UL) /*!< Min enumerator value of RSTRDONEINTMSK field. */ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Max (0x1UL) /*!< Max enumerator value of RSTRDONEINTMSK field. */ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_MASK (0x0UL) /*!< Restore Done Interrupt Mask */ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_NOMASK (0x1UL) /*!< No Restore Done Interrupt Mask */ + +/* EPMISMSK @Bit 17 : Mode: Device only. Endpoint Mismatch Interrupt Mask (EPMisMsk) */ + #define USBHSCORE_GINTMSK_EPMISMSK_Pos (17UL) /*!< Position of EPMISMSK field. */ + #define USBHSCORE_GINTMSK_EPMISMSK_Msk (0x1UL << USBHSCORE_GINTMSK_EPMISMSK_Pos) /*!< Bit mask of EPMISMSK field. */ + #define USBHSCORE_GINTMSK_EPMISMSK_Min (0x0UL) /*!< Min enumerator value of EPMISMSK field. */ + #define USBHSCORE_GINTMSK_EPMISMSK_Max (0x1UL) /*!< Max enumerator value of EPMISMSK field. */ + #define USBHSCORE_GINTMSK_EPMISMSK_MASK (0x0UL) /*!< Endpoint Mismatch Interrupt Mask */ + #define USBHSCORE_GINTMSK_EPMISMSK_NOMASK (0x1UL) /*!< No Endpoint Mismatch Interrupt Mask */ + +/* IEPINTMSK @Bit 18 : Mode: Device only. IN Endpoints Interrupt Mask (IEPIntMsk) */ + #define USBHSCORE_GINTMSK_IEPINTMSK_Pos (18UL) /*!< Position of IEPINTMSK field. */ + #define USBHSCORE_GINTMSK_IEPINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_IEPINTMSK_Pos) /*!< Bit mask of IEPINTMSK field. */ + #define USBHSCORE_GINTMSK_IEPINTMSK_Min (0x0UL) /*!< Min enumerator value of IEPINTMSK field. */ + #define USBHSCORE_GINTMSK_IEPINTMSK_Max (0x1UL) /*!< Max enumerator value of IEPINTMSK field. */ + #define USBHSCORE_GINTMSK_IEPINTMSK_MASK (0x0UL) /*!< IN Endpoints Interrupt Mask */ + #define USBHSCORE_GINTMSK_IEPINTMSK_NOMASK (0x1UL) /*!< No IN Endpoints Interrupt Mask */ + +/* OEPINTMSK @Bit 19 : Mode: Device only. OUT Endpoints Interrupt Mask (OEPIntMsk) */ + #define USBHSCORE_GINTMSK_OEPINTMSK_Pos (19UL) /*!< Position of OEPINTMSK field. */ + #define USBHSCORE_GINTMSK_OEPINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_OEPINTMSK_Pos) /*!< Bit mask of OEPINTMSK field. */ + #define USBHSCORE_GINTMSK_OEPINTMSK_Min (0x0UL) /*!< Min enumerator value of OEPINTMSK field. */ + #define USBHSCORE_GINTMSK_OEPINTMSK_Max (0x1UL) /*!< Max enumerator value of OEPINTMSK field. */ + #define USBHSCORE_GINTMSK_OEPINTMSK_MASK (0x0UL) /*!< OUT Endpoints Interrupt Mask */ + #define USBHSCORE_GINTMSK_OEPINTMSK_NOMASK (0x1UL) /*!< No OUT Endpoints Interrupt Mask */ + +/* INCOMPLPMSK @Bit 21 : Incomplete Periodic Transfer Mask (incomplPMsk) */ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_Pos (21UL) /*!< Position of INCOMPLPMSK field. */ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_INCOMPLPMSK_Pos) /*!< Bit mask of INCOMPLPMSK field. */ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_Min (0x0UL) /*!< Min enumerator value of INCOMPLPMSK field. */ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_Max (0x1UL) /*!< Max enumerator value of INCOMPLPMSK field. */ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_MASK (0x0UL) /*!< Host mode: Incomplete Periodic Transfer MaskDevice mode: Incomplete + Isochronous OUT Transfer Mask*/ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_NOMASK (0x1UL) /*!< Host mode: No Incomplete Periodic Transfer MaskDevice mode: No + Incomplete Isochronous OUT Transfer Mask*/ + +/* FETSUSPMSK @Bit 22 : Mode: Device only. Data Fetch Suspended Mask (FetSuspMsk) */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_Pos (22UL) /*!< Position of FETSUSPMSK field. */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_FETSUSPMSK_Pos) /*!< Bit mask of FETSUSPMSK field. */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_Min (0x0UL) /*!< Min enumerator value of FETSUSPMSK field. */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_Max (0x1UL) /*!< Max enumerator value of FETSUSPMSK field. */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_MASK (0x0UL) /*!< Data Fetch Suspended Mask */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_NOMASK (0x1UL) /*!< No Data Fetch Suspended Mask */ + +/* RESETDETMSK @Bit 23 : Mode: Device only. Reset detected Interrupt Mask (ResetDetMsk) */ + #define USBHSCORE_GINTMSK_RESETDETMSK_Pos (23UL) /*!< Position of RESETDETMSK field. */ + #define USBHSCORE_GINTMSK_RESETDETMSK_Msk (0x1UL << USBHSCORE_GINTMSK_RESETDETMSK_Pos) /*!< Bit mask of RESETDETMSK field. */ + #define USBHSCORE_GINTMSK_RESETDETMSK_Min (0x0UL) /*!< Min enumerator value of RESETDETMSK field. */ + #define USBHSCORE_GINTMSK_RESETDETMSK_Max (0x1UL) /*!< Max enumerator value of RESETDETMSK field. */ + #define USBHSCORE_GINTMSK_RESETDETMSK_MASK (0x0UL) /*!< Reset detected Interrupt Mask */ + #define USBHSCORE_GINTMSK_RESETDETMSK_NOMASK (0x1UL) /*!< No Reset detected Interrupt Mask */ + +/* PRTINTMSK @Bit 24 : Mode: Host only. Host Port Interrupt Mask (PrtIntMsk) */ + #define USBHSCORE_GINTMSK_PRTINTMSK_Pos (24UL) /*!< Position of PRTINTMSK field. */ + #define USBHSCORE_GINTMSK_PRTINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_PRTINTMSK_Pos) /*!< Bit mask of PRTINTMSK field. */ + #define USBHSCORE_GINTMSK_PRTINTMSK_Min (0x0UL) /*!< Min enumerator value of PRTINTMSK field. */ + #define USBHSCORE_GINTMSK_PRTINTMSK_Max (0x1UL) /*!< Max enumerator value of PRTINTMSK field. */ + #define USBHSCORE_GINTMSK_PRTINTMSK_MASK (0x0UL) /*!< Host Port Interrupt Mask */ + #define USBHSCORE_GINTMSK_PRTINTMSK_NOMASK (0x1UL) /*!< No Host Port Interrupt Mask */ + +/* HCHINTMSK @Bit 25 : Mode: Host only. Host Channels Interrupt Mask (HChIntMsk) */ + #define USBHSCORE_GINTMSK_HCHINTMSK_Pos (25UL) /*!< Position of HCHINTMSK field. */ + #define USBHSCORE_GINTMSK_HCHINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_HCHINTMSK_Pos) /*!< Bit mask of HCHINTMSK field. */ + #define USBHSCORE_GINTMSK_HCHINTMSK_Min (0x0UL) /*!< Min enumerator value of HCHINTMSK field. */ + #define USBHSCORE_GINTMSK_HCHINTMSK_Max (0x1UL) /*!< Max enumerator value of HCHINTMSK field. */ + #define USBHSCORE_GINTMSK_HCHINTMSK_MASK (0x0UL) /*!< Host Channels Interrupt Mask */ + #define USBHSCORE_GINTMSK_HCHINTMSK_NOMASK (0x1UL) /*!< No Host Channels Interrupt Mask */ + +/* PTXFEMPMSK @Bit 26 : Mode: Host only. Periodic TxFIFO Empty Mask (PTxFEmpMsk) */ + #define USBHSCORE_GINTMSK_PTXFEMPMSK_Pos (26UL) /*!< Position of PTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_PTXFEMPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_PTXFEMPMSK_Pos) /*!< Bit mask of PTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_PTXFEMPMSK_Min (0x0UL) /*!< Min enumerator value of PTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_PTXFEMPMSK_Max (0x1UL) /*!< Max enumerator value of PTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_PTXFEMPMSK_MASK (0x0UL) /*!< Periodic TxFIFO Empty Mask */ + #define USBHSCORE_GINTMSK_PTXFEMPMSK_NOMASK (0x1UL) /*!< No Periodic TxFIFO Empty Mask */ + +/* LPMINTMSK @Bit 27 : Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int) */ + #define USBHSCORE_GINTMSK_LPMINTMSK_Pos (27UL) /*!< Position of LPMINTMSK field. */ + #define USBHSCORE_GINTMSK_LPMINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_LPMINTMSK_Pos) /*!< Bit mask of LPMINTMSK field. */ + #define USBHSCORE_GINTMSK_LPMINTMSK_Min (0x0UL) /*!< Min enumerator value of LPMINTMSK field. */ + #define USBHSCORE_GINTMSK_LPMINTMSK_Max (0x1UL) /*!< Max enumerator value of LPMINTMSK field. */ + #define USBHSCORE_GINTMSK_LPMINTMSK_MASK (0x0UL) /*!< LPM Transaction received interrupt Mask */ + #define USBHSCORE_GINTMSK_LPMINTMSK_NOMASK (0x1UL) /*!< No LPM Transaction received interrupt Mask */ + +/* CONIDSTSCHNGMSK @Bit 28 : Mode: Host and Device. Connector ID Status Change Mask (ConIDStsChngMsk) */ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Pos (28UL) /*!< Position of CONIDSTSCHNGMSK field. */ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Msk (0x1UL << USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Pos) /*!< Bit mask of + CONIDSTSCHNGMSK field.*/ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Min (0x0UL) /*!< Min enumerator value of CONIDSTSCHNGMSK field. */ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Max (0x1UL) /*!< Max enumerator value of CONIDSTSCHNGMSK field. */ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_MASK (0x0UL) /*!< Connector ID Status Change Mask */ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_NOMASK (0x1UL) /*!< No Connector ID Status Change Mask */ + +/* DISCONNINTMSK @Bit 29 : Mode: Host and Device. Disconnect Detected Interrupt Mask (DisconnIntMsk) */ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_Pos (29UL) /*!< Position of DISCONNINTMSK field. */ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_DISCONNINTMSK_Pos) /*!< Bit mask of DISCONNINTMSK + field.*/ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_Min (0x0UL) /*!< Min enumerator value of DISCONNINTMSK field. */ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_Max (0x1UL) /*!< Max enumerator value of DISCONNINTMSK field. */ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_MASK (0x0UL) /*!< Disconnect Detected Interrupt Mask */ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_NOMASK (0x1UL) /*!< No Disconnect Detected Interrupt Mask */ + +/* SESSREQINTMSK @Bit 30 : Mode: Host and Device. Session Request/New Session Detected Interrupt Mask (SessReqIntMsk) */ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_Pos (30UL) /*!< Position of SESSREQINTMSK field. */ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_SESSREQINTMSK_Pos) /*!< Bit mask of SESSREQINTMSK + field.*/ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_Min (0x0UL) /*!< Min enumerator value of SESSREQINTMSK field. */ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_Max (0x1UL) /*!< Max enumerator value of SESSREQINTMSK field. */ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_MASK (0x0UL) /*!< Session Request or New Session Detected Interrupt Mask */ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_NOMASK (0x1UL) /*!< No Session Request or New Session Detected Interrupt Mask */ + +/* WKUPINTMSK @Bit 31 : Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk) */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_Pos (31UL) /*!< Position of WKUPINTMSK field. */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_WKUPINTMSK_Pos) /*!< Bit mask of WKUPINTMSK field. */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_Min (0x0UL) /*!< Min enumerator value of WKUPINTMSK field. */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_Max (0x1UL) /*!< Max enumerator value of WKUPINTMSK field. */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_MASK (0x0UL) /*!< Resume or Remote Wakeup Detected Interrupt Mask */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_NOMASK (0x1UL) /*!< Unmask Resume Remote Wakeup Detected Interrupt */ + + +/* USBHSCORE_GRXSTSR: Receive Status Debug Read Register */ + #define USBHSCORE_GRXSTSR_ResetValue (0x00000000UL) /*!< Reset value of GRXSTSR register. */ + +/* CHNUM @Bits 0..3 : Channel Number (ChNum) */ + #define USBHSCORE_GRXSTSR_CHNUM_Pos (0UL) /*!< Position of CHNUM field. */ + #define USBHSCORE_GRXSTSR_CHNUM_Msk (0xFUL << USBHSCORE_GRXSTSR_CHNUM_Pos) /*!< Bit mask of CHNUM field. */ + #define USBHSCORE_GRXSTSR_CHNUM_Min (0x0UL) /*!< Min enumerator value of CHNUM field. */ + #define USBHSCORE_GRXSTSR_CHNUM_Max (0xFUL) /*!< Max enumerator value of CHNUM field. */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP0 (0x0UL) /*!< Channel or EndPoint 0 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP1 (0x1UL) /*!< Channel or EndPoint 1 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP2 (0x2UL) /*!< Channel or EndPoint 2 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP3 (0x3UL) /*!< Channel or EndPoint 3 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP4 (0x4UL) /*!< Channel or EndPoint 4 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP5 (0x5UL) /*!< Channel or EndPoint 5 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP6 (0x6UL) /*!< Channel or EndPoint 6 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP7 (0x7UL) /*!< Channel or EndPoint 7 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP8 (0x8UL) /*!< Channel or EndPoint 8 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP9 (0x9UL) /*!< Channel or EndPoint 9 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP10 (0xAUL) /*!< Channel or EndPoint 10 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP11 (0xBUL) /*!< Channel or EndPoint 11 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP12 (0xCUL) /*!< Channel or EndPoint 12 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP13 (0xDUL) /*!< Channel or EndPoint 13 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP14 (0xEUL) /*!< Channel or EndPoint 14 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP15 (0xFUL) /*!< Channel or EndPoint 15 */ + +/* BCNT @Bits 4..14 : Byte Count (BCnt) */ + #define USBHSCORE_GRXSTSR_BCNT_Pos (4UL) /*!< Position of BCNT field. */ + #define USBHSCORE_GRXSTSR_BCNT_Msk (0x7FFUL << USBHSCORE_GRXSTSR_BCNT_Pos) /*!< Bit mask of BCNT field. */ + +/* DPID @Bits 15..16 : Data PID (DPID) */ + #define USBHSCORE_GRXSTSR_DPID_Pos (15UL) /*!< Position of DPID field. */ + #define USBHSCORE_GRXSTSR_DPID_Msk (0x3UL << USBHSCORE_GRXSTSR_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_GRXSTSR_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_GRXSTSR_DPID_Max (0x3UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_GRXSTSR_DPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_GRXSTSR_DPID_DATA2 (0x1UL) /*!< DATA2 */ + #define USBHSCORE_GRXSTSR_DPID_DATA1 (0x2UL) /*!< DATA1 */ + #define USBHSCORE_GRXSTSR_DPID_MDATA (0x3UL) /*!< MDATA */ + +/* PKTSTS @Bits 17..20 : Packet Status (PktSts) indicates the status of the received packet. */ + #define USBHSCORE_GRXSTSR_PKTSTS_Pos (17UL) /*!< Position of PKTSTS field. */ + #define USBHSCORE_GRXSTSR_PKTSTS_Msk (0xFUL << USBHSCORE_GRXSTSR_PKTSTS_Pos) /*!< Bit mask of PKTSTS field. */ + #define USBHSCORE_GRXSTSR_PKTSTS_Min (0x1UL) /*!< Min enumerator value of PKTSTS field. */ + #define USBHSCORE_GRXSTSR_PKTSTS_Max (0x7UL) /*!< Max enumerator value of PKTSTS field. */ + #define USBHSCORE_GRXSTSR_PKTSTS_OUTNAK (0x1UL) /*!< Global OUT NAK in device mode (triggers an interrupt) */ + #define USBHSCORE_GRXSTSR_PKTSTS_INOUTDPRX (0x2UL) /*!< IN data packet received in host mode and OUT data packet received in + device mode*/ + #define USBHSCORE_GRXSTSR_PKTSTS_INOUTTRCOM (0x3UL) /*!< IN or OUT transfer completed in both host and device mode (triggers + an interrupt)*/ + #define USBHSCORE_GRXSTSR_PKTSTS_DSETUPCOM (0x4UL) /*!< SETUP transaction completed in device mode (triggers an interrupt) */ + #define USBHSCORE_GRXSTSR_PKTSTS_DTTOG (0x5UL) /*!< Data toggle error (triggers an interrupt) in host mode */ + #define USBHSCORE_GRXSTSR_PKTSTS_DSETUPRX (0x6UL) /*!< SETUP data packet received in device mode */ + #define USBHSCORE_GRXSTSR_PKTSTS_CHHALT (0x7UL) /*!< Channel halted in host mode (triggers an interrupt) */ + +/* FN @Bits 21..24 : Mode: Device only. Frame Number (FN) */ + #define USBHSCORE_GRXSTSR_FN_Pos (21UL) /*!< Position of FN field. */ + #define USBHSCORE_GRXSTSR_FN_Msk (0xFUL << USBHSCORE_GRXSTSR_FN_Pos) /*!< Bit mask of FN field. */ + + +/* USBHSCORE_GRXSTSP: Receive Status Read/Pop Register */ + #define USBHSCORE_GRXSTSP_ResetValue (0x00000000UL) /*!< Reset value of GRXSTSP register. */ + +/* CHNUM @Bits 0..3 : Channel Number (ChNum) */ + #define USBHSCORE_GRXSTSP_CHNUM_Pos (0UL) /*!< Position of CHNUM field. */ + #define USBHSCORE_GRXSTSP_CHNUM_Msk (0xFUL << USBHSCORE_GRXSTSP_CHNUM_Pos) /*!< Bit mask of CHNUM field. */ + #define USBHSCORE_GRXSTSP_CHNUM_Min (0x0UL) /*!< Min enumerator value of CHNUM field. */ + #define USBHSCORE_GRXSTSP_CHNUM_Max (0xFUL) /*!< Max enumerator value of CHNUM field. */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP0 (0x0UL) /*!< Channel or EndPoint 0 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP1 (0x1UL) /*!< Channel or EndPoint 1 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP2 (0x2UL) /*!< Channel or EndPoint 2 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP3 (0x3UL) /*!< Channel or EndPoint 3 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP4 (0x4UL) /*!< Channel or EndPoint 4 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP5 (0x5UL) /*!< Channel or EndPoint 5 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP6 (0x6UL) /*!< Channel or EndPoint 6 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP7 (0x7UL) /*!< Channel or EndPoint 7 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP8 (0x8UL) /*!< Channel or EndPoint 8 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP9 (0x9UL) /*!< Channel or EndPoint 9 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP10 (0xAUL) /*!< Channel or EndPoint 10 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP11 (0xBUL) /*!< Channel or EndPoint 11 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP12 (0xCUL) /*!< Channel or EndPoint 12 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP13 (0xDUL) /*!< Channel or EndPoint 13 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP14 (0xEUL) /*!< Channel or EndPoint 14 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP15 (0xFUL) /*!< Channel or EndPoint 15 */ + +/* BCNT @Bits 4..14 : Byte Count (BCnt) */ + #define USBHSCORE_GRXSTSP_BCNT_Pos (4UL) /*!< Position of BCNT field. */ + #define USBHSCORE_GRXSTSP_BCNT_Msk (0x7FFUL << USBHSCORE_GRXSTSP_BCNT_Pos) /*!< Bit mask of BCNT field. */ + +/* DPID @Bits 15..16 : Data PID (DPID) */ + #define USBHSCORE_GRXSTSP_DPID_Pos (15UL) /*!< Position of DPID field. */ + #define USBHSCORE_GRXSTSP_DPID_Msk (0x3UL << USBHSCORE_GRXSTSP_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_GRXSTSP_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_GRXSTSP_DPID_Max (0x3UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_GRXSTSP_DPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_GRXSTSP_DPID_DATA2 (0x1UL) /*!< DATA2 */ + #define USBHSCORE_GRXSTSP_DPID_DATA1 (0x2UL) /*!< DATA1 */ + #define USBHSCORE_GRXSTSP_DPID_MDATA (0x3UL) /*!< MDATA */ + +/* PKTSTS @Bits 17..20 : Packet Status (PktSts) indicates the status of the received packet. */ + #define USBHSCORE_GRXSTSP_PKTSTS_Pos (17UL) /*!< Position of PKTSTS field. */ + #define USBHSCORE_GRXSTSP_PKTSTS_Msk (0xFUL << USBHSCORE_GRXSTSP_PKTSTS_Pos) /*!< Bit mask of PKTSTS field. */ + #define USBHSCORE_GRXSTSP_PKTSTS_Min (0x1UL) /*!< Min enumerator value of PKTSTS field. */ + #define USBHSCORE_GRXSTSP_PKTSTS_Max (0x5UL) /*!< Max enumerator value of PKTSTS field. */ + #define USBHSCORE_GRXSTSP_PKTSTS_OUTNAK (0x1UL) /*!< Global OUT NAK in device mode (triggers an interrupt) */ + #define USBHSCORE_GRXSTSP_PKTSTS_INOUTDPRX (0x2UL) /*!< IN data packet received in host mode and OUT data packet received in + device mode*/ + #define USBHSCORE_GRXSTSP_PKTSTS_INOUTTRCOM (0x3UL) /*!< IN or OUT transfer completed in both host and device mode (triggers + an interrupt)*/ + #define USBHSCORE_GRXSTSP_PKTSTS_DSETUPCOM (0x4UL) /*!< SETUP transaction completed in device mode (triggers an interrupt) */ + #define USBHSCORE_GRXSTSP_PKTSTS_DTTOG (0x5UL) /*!< Data toggle error (triggers an interrupt) in host mode */ + +/* FN @Bits 21..24 : Mode: Device only. Frame Number (FN) */ + #define USBHSCORE_GRXSTSP_FN_Pos (21UL) /*!< Position of FN field. */ + #define USBHSCORE_GRXSTSP_FN_Msk (0xFUL << USBHSCORE_GRXSTSP_FN_Pos) /*!< Bit mask of FN field. */ + + +/* USBHSCORE_GRXFSIZ: Receive FIFO Size Register */ + #define USBHSCORE_GRXFSIZ_ResetValue (0x00000C00UL) /*!< Reset value of GRXFSIZ register. */ + +/* RXFDEP @Bits 0..11 : Mode: Host and Device. RxFIFO Depth (RxFDep) */ + #define USBHSCORE_GRXFSIZ_RXFDEP_Pos (0UL) /*!< Position of RXFDEP field. */ + #define USBHSCORE_GRXFSIZ_RXFDEP_Msk (0xFFFUL << USBHSCORE_GRXFSIZ_RXFDEP_Pos) /*!< Bit mask of RXFDEP field. */ + + +/* USBHSCORE_GNPTXFSIZ: Non-periodic Transmit FIFO Size Register */ + #define USBHSCORE_GNPTXFSIZ_ResetValue (0x0C000C00UL) /*!< Reset value of GNPTXFSIZ register. */ + +/* NPTXFSTADDR @Bits 0..11 : Non-periodic Transmit RAM Start Address (NPTxFStAddr) */ + #define USBHSCORE_GNPTXFSIZ_NPTXFSTADDR_Pos (0UL) /*!< Position of NPTXFSTADDR field. */ + #define USBHSCORE_GNPTXFSIZ_NPTXFSTADDR_Msk (0xFFFUL << USBHSCORE_GNPTXFSIZ_NPTXFSTADDR_Pos) /*!< Bit mask of NPTXFSTADDR + field.*/ + +/* NPTXFDEP @Bits 16..27 : Mode: Host only. Non-periodic TxFIFO Depth (NPTxFDep) */ + #define USBHSCORE_GNPTXFSIZ_NPTXFDEP_Pos (16UL) /*!< Position of NPTXFDEP field. */ + #define USBHSCORE_GNPTXFSIZ_NPTXFDEP_Msk (0xFFFUL << USBHSCORE_GNPTXFSIZ_NPTXFDEP_Pos) /*!< Bit mask of NPTXFDEP field. */ + + +/* USBHSCORE_GNPTXSTS: Non-periodic Transmit FIFO/Queue Status Register */ + #define USBHSCORE_GNPTXSTS_ResetValue (0x00080C00UL) /*!< Reset value of GNPTXSTS register. */ + +/* NPTXFSPCAVAIL @Bits 0..15 : Non-periodic TxFIFO Space Avail (NPTxFSpcAvail) */ + #define USBHSCORE_GNPTXSTS_NPTXFSPCAVAIL_Pos (0UL) /*!< Position of NPTXFSPCAVAIL field. */ + #define USBHSCORE_GNPTXSTS_NPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_GNPTXSTS_NPTXFSPCAVAIL_Pos) /*!< Bit mask of NPTXFSPCAVAIL + field.*/ + +/* NPTXQSPCAVAIL @Bits 16..23 : Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail) */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Pos (16UL) /*!< Position of NPTXQSPCAVAIL field. */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Msk (0xFFUL << USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Pos) /*!< Bit mask of NPTXQSPCAVAIL + field.*/ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Min (0x00UL) /*!< Min enumerator value of NPTXQSPCAVAIL field. */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Max (0x08UL) /*!< Max enumerator value of NPTXQSPCAVAIL field. */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_FULL (0x00UL) /*!< Non-periodic Transmit Request Queue is full */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE1 (0x01UL) /*!< 1 location available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE2 (0x02UL) /*!< 2 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE3 (0x03UL) /*!< 3 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE4 (0x04UL) /*!< 4 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE5 (0x05UL) /*!< 5 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE6 (0x06UL) /*!< 6 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE7 (0x07UL) /*!< 7 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE8 (0x08UL) /*!< 8 locations available */ + +/* NPTXQTOP @Bits 24..30 : Top of the Non-periodic Transmit Request Queue (NPTxQTop) */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_Pos (24UL) /*!< Position of NPTXQTOP field. */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USBHSCORE_GNPTXSTS_NPTXQTOP_Pos) /*!< Bit mask of NPTXQTOP field. */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_Min (0x00UL) /*!< Min enumerator value of NPTXQTOP field. */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_Max (0x03UL) /*!< Max enumerator value of NPTXQTOP field. */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_INOUTTK (0x00UL) /*!< IN/OUT token */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_ZEROTX (0x01UL) /*!< Zero-length transmit packet (device IN/host OUT) */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_PINGCSPLIT (0x02UL) /*!< PING/CSPLIT token */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_CHNHALT (0x03UL) /*!< Channel halt command */ + + +/* USBHSCORE_GGPIO: General Purpose Input/Output Register */ + #define USBHSCORE_GGPIO_ResetValue (0x00000000UL) /*!< Reset value of GGPIO register. */ + +/* GPI @Bits 0..15 : (unspecified) */ + #define USBHSCORE_GGPIO_GPI_Pos (0UL) /*!< Position of GPI field. */ + #define USBHSCORE_GGPIO_GPI_Msk (0xFFFFUL << USBHSCORE_GGPIO_GPI_Pos) /*!< Bit mask of GPI field. */ + +/* GPO @Bits 16..31 : (unspecified) */ + #define USBHSCORE_GGPIO_GPO_Pos (16UL) /*!< Position of GPO field. */ + #define USBHSCORE_GGPIO_GPO_Msk (0xFFFFUL << USBHSCORE_GGPIO_GPO_Pos) /*!< Bit mask of GPO field. */ + + +/* USBHSCORE_GUID: User ID Register */ + #define USBHSCORE_GUID_ResetValue (0x00000000UL) /*!< Reset value of GUID register. */ + +/* GUID @Bits 0..31 : User ID (UserID) Application-programmable ID field. */ + #define USBHSCORE_GUID_GUID_Pos (0UL) /*!< Position of GUID field. */ + #define USBHSCORE_GUID_GUID_Msk (0xFFFFFFFFUL << USBHSCORE_GUID_GUID_Pos) /*!< Bit mask of GUID field. */ + + +/* USBHSCORE_GSNPSID: Synopsys ID Register */ + #define USBHSCORE_GSNPSID_ResetValue (0x4F54500BUL) /*!< Reset value of GSNPSID register. */ + +/* SYNOPSYSID @Bits 0..31 : Release number of the controller being used currently. */ + #define USBHSCORE_GSNPSID_SYNOPSYSID_Pos (0UL) /*!< Position of SYNOPSYSID field. */ + #define USBHSCORE_GSNPSID_SYNOPSYSID_Msk (0xFFFFFFFFUL << USBHSCORE_GSNPSID_SYNOPSYSID_Pos) /*!< Bit mask of SYNOPSYSID + field.*/ + + +/* USBHSCORE_GHWCFG1: User Hardware Configuration 1 Register */ + #define USBHSCORE_GHWCFG1_ResetValue (0x00000000UL) /*!< Reset value of GHWCFG1 register. */ + +/* EPDIR @Bits 0..31 : This 32-bit field uses two bits per */ + #define USBHSCORE_GHWCFG1_EPDIR_Pos (0UL) /*!< Position of EPDIR field. */ + #define USBHSCORE_GHWCFG1_EPDIR_Msk (0xFFFFFFFFUL << USBHSCORE_GHWCFG1_EPDIR_Pos) /*!< Bit mask of EPDIR field. */ + + +/* USBHSCORE_GHWCFG2: User Hardware Configuration 2 Register */ + #define USBHSCORE_GHWCFG2_ResetValue (0x228FFC52UL) /*!< Reset value of GHWCFG2 register. */ + +/* OTGMODE @Bits 0..2 : Mode of Operation (OtgMode) */ + #define USBHSCORE_GHWCFG2_OTGMODE_Pos (0UL) /*!< Position of OTGMODE field. */ + #define USBHSCORE_GHWCFG2_OTGMODE_Msk (0x7UL << USBHSCORE_GHWCFG2_OTGMODE_Pos) /*!< Bit mask of OTGMODE field. */ + #define USBHSCORE_GHWCFG2_OTGMODE_Min (0x0UL) /*!< Min enumerator value of OTGMODE field. */ + #define USBHSCORE_GHWCFG2_OTGMODE_Max (0x6UL) /*!< Max enumerator value of OTGMODE field. */ + #define USBHSCORE_GHWCFG2_OTGMODE_HNPSRP (0x0UL) /*!< HNP- and SRP-Capable OTG (Host and Device) */ + #define USBHSCORE_GHWCFG2_OTGMODE_SRPOTG (0x1UL) /*!< SRP-Capable OTG (Host and Device) */ + #define USBHSCORE_GHWCFG2_OTGMODE_NHNPNSRP (0x2UL) /*!< Non-HNP and Non-SRP Capable OTG (Host and Device) */ + #define USBHSCORE_GHWCFG2_OTGMODE_SRPCAPD (0x3UL) /*!< SRP-Capable Device */ + #define USBHSCORE_GHWCFG2_OTGMODE_NONOTGD (0x4UL) /*!< Non-OTG Device */ + #define USBHSCORE_GHWCFG2_OTGMODE_SRPCAPH (0x5UL) /*!< SRP-Capable Host */ + #define USBHSCORE_GHWCFG2_OTGMODE_NONOTGH (0x6UL) /*!< Non-OTG Host */ + +/* OTGARCH @Bits 3..4 : Architecture (OtgArch) */ + #define USBHSCORE_GHWCFG2_OTGARCH_Pos (3UL) /*!< Position of OTGARCH field. */ + #define USBHSCORE_GHWCFG2_OTGARCH_Msk (0x3UL << USBHSCORE_GHWCFG2_OTGARCH_Pos) /*!< Bit mask of OTGARCH field. */ + #define USBHSCORE_GHWCFG2_OTGARCH_Min (0x0UL) /*!< Min enumerator value of OTGARCH field. */ + #define USBHSCORE_GHWCFG2_OTGARCH_Max (0x2UL) /*!< Max enumerator value of OTGARCH field. */ + #define USBHSCORE_GHWCFG2_OTGARCH_COMPLETERMODE (0x0UL) /*!< Completer Mode */ + #define USBHSCORE_GHWCFG2_OTGARCH_EXTERNALDMA (0x1UL) /*!< External DMA Mode */ + #define USBHSCORE_GHWCFG2_OTGARCH_INTERNALDMA (0x2UL) /*!< Internal DMA Mode */ + +/* SINGPNT @Bit 5 : Point-to-Point (SingPnt) */ + #define USBHSCORE_GHWCFG2_SINGPNT_Pos (5UL) /*!< Position of SINGPNT field. */ + #define USBHSCORE_GHWCFG2_SINGPNT_Msk (0x1UL << USBHSCORE_GHWCFG2_SINGPNT_Pos) /*!< Bit mask of SINGPNT field. */ + #define USBHSCORE_GHWCFG2_SINGPNT_Min (0x0UL) /*!< Min enumerator value of SINGPNT field. */ + #define USBHSCORE_GHWCFG2_SINGPNT_Max (0x1UL) /*!< Max enumerator value of SINGPNT field. */ + #define USBHSCORE_GHWCFG2_SINGPNT_MULTIPOINT (0x0UL) /*!< Multi-point application (hub and split support) */ + #define USBHSCORE_GHWCFG2_SINGPNT_SINGLEPOINT (0x1UL) /*!< Single-point application (no hub and split support) */ + +/* HSPHYTYPE @Bits 6..7 : High-Speed PHY Interface Type (HSPhyType) */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_Pos (6UL) /*!< Position of HSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_Msk (0x3UL << USBHSCORE_GHWCFG2_HSPHYTYPE_Pos) /*!< Bit mask of HSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_Min (0x0UL) /*!< Min enumerator value of HSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_Max (0x3UL) /*!< Max enumerator value of HSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_NOHS (0x0UL) /*!< High-Speed interface not supported */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_UTMIPLUS (0x1UL) /*!< High Speed Interface UTMI+ is supported */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_ULPI (0x2UL) /*!< High Speed Interface ULPI is supported */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_UTMIPUSULPI (0x3UL) /*!< High Speed Interfaces UTMI+ and ULPI is supported */ + +/* FSPHYTYPE @Bits 8..9 : Full-Speed PHY Interface Type (FSPhyType) */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_Pos (8UL) /*!< Position of FSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_Msk (0x3UL << USBHSCORE_GHWCFG2_FSPHYTYPE_Pos) /*!< Bit mask of FSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_Min (0x0UL) /*!< Min enumerator value of FSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_Max (0x3UL) /*!< Max enumerator value of FSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_NOFS (0x0UL) /*!< Full-speed interface not supported */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_FS (0x1UL) /*!< Dedicated full-speed interface is supported */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_FSPLUSUTMI (0x2UL) /*!< FS pins shared with UTMI+ pins is supported */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_FSPLUSULPI (0x3UL) /*!< FS pins shared with ULPI pins is supported */ + +/* NUMDEVEPS @Bits 10..13 : Number of Device Endpoints (NumDevEps) */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_Pos (10UL) /*!< Position of NUMDEVEPS field. */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_Msk (0xFUL << USBHSCORE_GHWCFG2_NUMDEVEPS_Pos) /*!< Bit mask of NUMDEVEPS field. */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_Min (0x0UL) /*!< Min enumerator value of NUMDEVEPS field. */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_Max (0xFUL) /*!< Max enumerator value of NUMDEVEPS field. */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT0 (0x0UL) /*!< End point 0 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT1 (0x1UL) /*!< End point 1 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT2 (0x2UL) /*!< End point 2 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT3 (0x3UL) /*!< End point 3 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT4 (0x4UL) /*!< End point 4 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT5 (0x5UL) /*!< End point 5 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT6 (0x6UL) /*!< End point 6 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT7 (0x7UL) /*!< End point 7 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT8 (0x8UL) /*!< End point 8 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT9 (0x9UL) /*!< End point 9 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT10 (0xAUL) /*!< End point 10 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT11 (0xBUL) /*!< End point 11 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT12 (0xCUL) /*!< End point 12 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT13 (0xDUL) /*!< End point 13 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT14 (0xEUL) /*!< End point 14 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT15 (0xFUL) /*!< End point 15 */ + +/* NUMHSTCHNL @Bits 14..17 : Number of Host Channels (NumHstChnl) */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Pos (14UL) /*!< Position of NUMHSTCHNL field. */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Msk (0xFUL << USBHSCORE_GHWCFG2_NUMHSTCHNL_Pos) /*!< Bit mask of NUMHSTCHNL field. */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Min (0x0UL) /*!< Min enumerator value of NUMHSTCHNL field. */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Max (0xFUL) /*!< Max enumerator value of NUMHSTCHNL field. */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH0 (0x0UL) /*!< Host Channel 1 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH1 (0x1UL) /*!< Host Channel 2 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH2 (0x2UL) /*!< Host Channel 3 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH3 (0x3UL) /*!< Host Channel 4 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH4 (0x4UL) /*!< Host Channel 5 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH5 (0x5UL) /*!< Host Channel 6 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH6 (0x6UL) /*!< Host Channel 7 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH7 (0x7UL) /*!< Host Channel 8 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH8 (0x8UL) /*!< Host Channel 9 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH9 (0x9UL) /*!< Host Channel 10 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH10 (0xAUL) /*!< Host Channel 11 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH11 (0xBUL) /*!< Host Channel 12 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH12 (0xCUL) /*!< Host Channel 13 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH13 (0xDUL) /*!< Host Channel 14 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH14 (0xEUL) /*!< Host Channel 15 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH15 (0xFUL) /*!< Host Channel 16 */ + +/* PERIOSUPPORT @Bit 18 : Periodic OUT Channels Supported in Host Mode (PerioSupport) */ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Pos (18UL) /*!< Position of PERIOSUPPORT field. */ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Msk (0x1UL << USBHSCORE_GHWCFG2_PERIOSUPPORT_Pos) /*!< Bit mask of PERIOSUPPORT field.*/ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Min (0x0UL) /*!< Min enumerator value of PERIOSUPPORT field. */ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Max (0x1UL) /*!< Max enumerator value of PERIOSUPPORT field. */ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_DISABLED (0x0UL) /*!< Periodic OUT Channels is not supported in Host Mode */ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_ENABLED (0x1UL) /*!< Periodic OUT Channels Supported in Host Mode Supported */ + +/* DYNFIFOSIZING @Bit 19 : Dynamic FIFO Sizing Enabled (DynFifoSizing) */ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Pos (19UL) /*!< Position of DYNFIFOSIZING field. */ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Msk (0x1UL << USBHSCORE_GHWCFG2_DYNFIFOSIZING_Pos) /*!< Bit mask of DYNFIFOSIZING + field.*/ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Min (0x0UL) /*!< Min enumerator value of DYNFIFOSIZING field. */ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Max (0x1UL) /*!< Max enumerator value of DYNFIFOSIZING field. */ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_DISABLED (0x0UL) /*!< Dynamic FIFO Sizing Disabled */ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_ENABLED (0x1UL) /*!< Dynamic FIFO Sizing Enabled */ + +/* MULTIPROCINTRPT @Bit 20 : Multi Processor Interrupt Enabled (MultiProcIntrpt) */ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Pos (20UL) /*!< Position of MULTIPROCINTRPT field. */ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Msk (0x1UL << USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Pos) /*!< Bit mask of + MULTIPROCINTRPT field.*/ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Min (0x0UL) /*!< Min enumerator value of MULTIPROCINTRPT field. */ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Max (0x1UL) /*!< Max enumerator value of MULTIPROCINTRPT field. */ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_DISABLED (0x0UL) /*!< No Multi Processor Interrupt Enabled */ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_ENABLED (0x1UL) /*!< Multi Processor Interrupt Enabled */ + +/* NPTXQDEPTH @Bits 22..23 : Non-periodic Request Queue Depth (NPTxQDepth) */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Pos (22UL) /*!< Position of NPTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Msk (0x3UL << USBHSCORE_GHWCFG2_NPTXQDEPTH_Pos) /*!< Bit mask of NPTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Min (0x0UL) /*!< Min enumerator value of NPTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Max (0x2UL) /*!< Max enumerator value of NPTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_TWO (0x0UL) /*!< Queue size 2 */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_FOUR (0x1UL) /*!< Queue size 4 */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_EIGHT (0x2UL) /*!< Queue size 8 */ + +/* PTXQDEPTH @Bits 24..25 : Host Mode Periodic Request Queue Depth (PTxQDepth) */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_Pos (24UL) /*!< Position of PTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_Msk (0x3UL << USBHSCORE_GHWCFG2_PTXQDEPTH_Pos) /*!< Bit mask of PTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_Min (0x0UL) /*!< Min enumerator value of PTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_Max (0x3UL) /*!< Max enumerator value of PTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE2 (0x0UL) /*!< Queue Depth 2 */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE4 (0x1UL) /*!< Queue Depth 4 */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE8 (0x2UL) /*!< Queue Depth 8 */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE16 (0x3UL) /*!< Queue Depth 16 */ + +/* TKNQDEPTH @Bits 26..30 : Device Mode IN Token Sequence Learning Queue Depth (TknQDepth) */ + #define USBHSCORE_GHWCFG2_TKNQDEPTH_Pos (26UL) /*!< Position of TKNQDEPTH field. */ + #define USBHSCORE_GHWCFG2_TKNQDEPTH_Msk (0x1FUL << USBHSCORE_GHWCFG2_TKNQDEPTH_Pos) /*!< Bit mask of TKNQDEPTH field. */ + + +/* USBHSCORE_GHWCFG3: User Hardware Configuration 3 Register */ + #define USBHSCORE_GHWCFG3_ResetValue (0x0BE0C0E8UL) /*!< Reset value of GHWCFG3 register. */ + +/* XFERSIZEWIDTH @Bits 0..3 : Width of Transfer Size Counters (XferSizeWidth) */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Pos (0UL) /*!< Position of XFERSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Msk (0xFUL << USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Pos) /*!< Bit mask of XFERSIZEWIDTH + field.*/ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Min (0x0UL) /*!< Min enumerator value of XFERSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Max (0x8UL) /*!< Max enumerator value of XFERSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH11 (0x0UL) /*!< Width of Transfer Size Counter 11 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH12 (0x1UL) /*!< Width of Transfer Size Counter 12 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH13 (0x2UL) /*!< Width of Transfer Size Counter 13 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH14 (0x3UL) /*!< Width of Transfer Size Counter 14 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH15 (0x4UL) /*!< Width of Transfer Size Counter 15 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH16 (0x5UL) /*!< Width of Transfer Size Counter 16 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH17 (0x6UL) /*!< Width of Transfer Size Counter 17 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH18 (0x7UL) /*!< Width of Transfer Size Counter 18 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH19 (0x8UL) /*!< Width of Transfer Size Counter 19 bits */ + +/* PKTSIZEWIDTH @Bits 4..6 : Width of Packet Size Counters (PktSizeWidth) */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Pos (4UL) /*!< Position of PKTSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Msk (0x7UL << USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Pos) /*!< Bit mask of PKTSIZEWIDTH field.*/ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Min (0x0UL) /*!< Min enumerator value of PKTSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Max (0x6UL) /*!< Max enumerator value of PKTSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS4 (0x0UL) /*!< Width of Packet Size Counter 4 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS5 (0x1UL) /*!< Width of Packet Size Counter 5 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS6 (0x2UL) /*!< Width of Packet Size Counter 6 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS7 (0x3UL) /*!< Width of Packet Size Counter 7 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS8 (0x4UL) /*!< Width of Packet Size Counter 8 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS9 (0x5UL) /*!< Width of Packet Size Counter 9 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS10 (0x6UL) /*!< Width of Packet Size Counter 10 */ + +/* OTGEN @Bit 7 : OTG Function Enabled (OtgEn) */ + #define USBHSCORE_GHWCFG3_OTGEN_Pos (7UL) /*!< Position of OTGEN field. */ + #define USBHSCORE_GHWCFG3_OTGEN_Msk (0x1UL << USBHSCORE_GHWCFG3_OTGEN_Pos) /*!< Bit mask of OTGEN field. */ + #define USBHSCORE_GHWCFG3_OTGEN_Min (0x0UL) /*!< Min enumerator value of OTGEN field. */ + #define USBHSCORE_GHWCFG3_OTGEN_Max (0x1UL) /*!< Max enumerator value of OTGEN field. */ + #define USBHSCORE_GHWCFG3_OTGEN_DISABLED (0x0UL) /*!< Not OTG Capable */ + #define USBHSCORE_GHWCFG3_OTGEN_ENABLED (0x1UL) /*!< OTG Capable */ + +/* I2CINTSEL @Bit 8 : I2C Selection (I2CIntSel) */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_Pos (8UL) /*!< Position of I2CINTSEL field. */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_Msk (0x1UL << USBHSCORE_GHWCFG3_I2CINTSEL_Pos) /*!< Bit mask of I2CINTSEL field. */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_Min (0x0UL) /*!< Min enumerator value of I2CINTSEL field. */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_Max (0x1UL) /*!< Max enumerator value of I2CINTSEL field. */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_DISABLED (0x0UL) /*!< I2C Interface is not available */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_ENABLED (0x1UL) /*!< I2C Interface is available */ + +/* VNDCTLSUPT @Bit 9 : Vendor Control Interface Support (VndctlSupt) */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Pos (9UL) /*!< Position of VNDCTLSUPT field. */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Msk (0x1UL << USBHSCORE_GHWCFG3_VNDCTLSUPT_Pos) /*!< Bit mask of VNDCTLSUPT field. */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Min (0x0UL) /*!< Min enumerator value of VNDCTLSUPT field. */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Max (0x1UL) /*!< Max enumerator value of VNDCTLSUPT field. */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_DISABLED (0x0UL) /*!< Vendor Control Interface is not available. */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_ENABLED (0x1UL) /*!< Vendor Control Interface is available. */ + +/* OPTFEATURE @Bit 10 : Optional Features Removed (OptFeature) */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_Pos (10UL) /*!< Position of OPTFEATURE field. */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_Msk (0x1UL << USBHSCORE_GHWCFG3_OPTFEATURE_Pos) /*!< Bit mask of OPTFEATURE field. */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_Min (0x0UL) /*!< Min enumerator value of OPTFEATURE field. */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_Max (0x1UL) /*!< Max enumerator value of OPTFEATURE field. */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_DISABLED (0x0UL) /*!< Optional features were not Removed */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_ENABLED (0x1UL) /*!< Optional Features have been Removed */ + +/* RSTTYPE @Bit 11 : Reset Style for Clocked always Blocks in RTL (RstType) */ + #define USBHSCORE_GHWCFG3_RSTTYPE_Pos (11UL) /*!< Position of RSTTYPE field. */ + #define USBHSCORE_GHWCFG3_RSTTYPE_Msk (0x1UL << USBHSCORE_GHWCFG3_RSTTYPE_Pos) /*!< Bit mask of RSTTYPE field. */ + #define USBHSCORE_GHWCFG3_RSTTYPE_Min (0x0UL) /*!< Min enumerator value of RSTTYPE field. */ + #define USBHSCORE_GHWCFG3_RSTTYPE_Max (0x1UL) /*!< Max enumerator value of RSTTYPE field. */ + #define USBHSCORE_GHWCFG3_RSTTYPE_ASYNCRST (0x0UL) /*!< Asynchronous reset is used in the core */ + #define USBHSCORE_GHWCFG3_RSTTYPE_SYNCRST (0x1UL) /*!< Synchronous reset is used in the core */ + +/* ADPSUPPORT @Bit 12 : This bit indicates whether ADP logic is present within or external to the controller */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_Pos (12UL) /*!< Position of ADPSUPPORT field. */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_Msk (0x1UL << USBHSCORE_GHWCFG3_ADPSUPPORT_Pos) /*!< Bit mask of ADPSUPPORT field. */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_Min (0x0UL) /*!< Min enumerator value of ADPSUPPORT field. */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_Max (0x1UL) /*!< Max enumerator value of ADPSUPPORT field. */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_DISABLED (0x0UL) /*!< ADP logic is not present along with the controller */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_ENABLED (0x1UL) /*!< ADP logic is present along with the controller */ + +/* HSICMODE @Bit 13 : HSIC mode specified for Mode of Operation */ + #define USBHSCORE_GHWCFG3_HSICMODE_Pos (13UL) /*!< Position of HSICMODE field. */ + #define USBHSCORE_GHWCFG3_HSICMODE_Msk (0x1UL << USBHSCORE_GHWCFG3_HSICMODE_Pos) /*!< Bit mask of HSICMODE field. */ + #define USBHSCORE_GHWCFG3_HSICMODE_Min (0x0UL) /*!< Min enumerator value of HSICMODE field. */ + #define USBHSCORE_GHWCFG3_HSICMODE_Max (0x1UL) /*!< Max enumerator value of HSICMODE field. */ + #define USBHSCORE_GHWCFG3_HSICMODE_DISABLED (0x0UL) /*!< No HSIC capability */ + #define USBHSCORE_GHWCFG3_HSICMODE_ENABLED (0x1UL) /*!< HSIC-capable with shared UTMI PHY interface */ + +/* BCSUPPORT @Bit 14 : This bit indicates the controller support for Battery Charger. */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_Pos (14UL) /*!< Position of BCSUPPORT field. */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_Msk (0x1UL << USBHSCORE_GHWCFG3_BCSUPPORT_Pos) /*!< Bit mask of BCSUPPORT field. */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_Min (0x0UL) /*!< Min enumerator value of BCSUPPORT field. */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_Max (0x1UL) /*!< Max enumerator value of BCSUPPORT field. */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_DISABLED (0x0UL) /*!< No Battery Charger Support */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_ENABLED (0x1UL) /*!< Battery Charger Support present */ + +/* LPMMODE @Bit 15 : LPM mode specified for Mode of Operation. */ + #define USBHSCORE_GHWCFG3_LPMMODE_Pos (15UL) /*!< Position of LPMMODE field. */ + #define USBHSCORE_GHWCFG3_LPMMODE_Msk (0x1UL << USBHSCORE_GHWCFG3_LPMMODE_Pos) /*!< Bit mask of LPMMODE field. */ + #define USBHSCORE_GHWCFG3_LPMMODE_Min (0x0UL) /*!< Min enumerator value of LPMMODE field. */ + #define USBHSCORE_GHWCFG3_LPMMODE_Max (0x1UL) /*!< Max enumerator value of LPMMODE field. */ + #define USBHSCORE_GHWCFG3_LPMMODE_DISABLED (0x0UL) /*!< LPM disabled */ + #define USBHSCORE_GHWCFG3_LPMMODE_ENABLED (0x1UL) /*!< LPM enabled */ + +/* DFIFODEPTH @Bits 16..31 : DFIFO Depth (DfifoDepth - EP_LOC_CNT) */ + #define USBHSCORE_GHWCFG3_DFIFODEPTH_Pos (16UL) /*!< Position of DFIFODEPTH field. */ + #define USBHSCORE_GHWCFG3_DFIFODEPTH_Msk (0xFFFFUL << USBHSCORE_GHWCFG3_DFIFODEPTH_Pos) /*!< Bit mask of DFIFODEPTH field. */ + + +/* USBHSCORE_GHWCFG4: User Hardware Configuration 4 Register */ + #define USBHSCORE_GHWCFG4_ResetValue (0x3E10AA60UL) /*!< Reset value of GHWCFG4 register. */ + +/* NUMDEVPERIOEPS @Bits 0..3 : Number of Device Mode Periodic IN Endpoints (NumDevPerioEps) */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Pos (0UL) /*!< Position of NUMDEVPERIOEPS field. */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Msk (0xFUL << USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Pos) /*!< Bit mask of NUMDEVPERIOEPS + field.*/ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Min (0x0UL) /*!< Min enumerator value of NUMDEVPERIOEPS field. */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Max (0xFUL) /*!< Max enumerator value of NUMDEVPERIOEPS field. */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE0 (0x0UL) /*!< Number of Periodic IN EPs is 0 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE1 (0x1UL) /*!< Number of Periodic IN EPs is 1 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE2 (0x2UL) /*!< Number of Periodic IN EPs is 2 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE3 (0x3UL) /*!< Number of Periodic IN EPs is 3 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE4 (0x4UL) /*!< Number of Periodic IN EPs is 4 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE5 (0x5UL) /*!< Number of Periodic IN EPs is 5 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE6 (0x6UL) /*!< Number of Periodic IN EPs is 6 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE7 (0x7UL) /*!< Number of Periodic IN EPs is 7 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE8 (0x8UL) /*!< Number of Periodic IN EPs is 8 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE9 (0x9UL) /*!< Number of Periodic IN EPs is 9 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE10 (0xAUL) /*!< Number of Periodic IN EPs is 10 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE11 (0xBUL) /*!< Number of Periodic IN EPs is 11 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE12 (0xCUL) /*!< Number of Periodic IN EPs is 12 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE13 (0xDUL) /*!< Number of Periodic IN EPs is 13 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE14 (0xEUL) /*!< Number of Periodic IN EPs is 14 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_VALUE15 (0xFUL) /*!< Number of Periodic IN EPs is 15 */ + +/* PARTIALPWRDN @Bit 4 : Enable Partial Power Down (PartialPwrDn) */ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Pos (4UL) /*!< Position of PARTIALPWRDN field. */ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Msk (0x1UL << USBHSCORE_GHWCFG4_PARTIALPWRDN_Pos) /*!< Bit mask of PARTIALPWRDN field.*/ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Min (0x0UL) /*!< Min enumerator value of PARTIALPWRDN field. */ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Max (0x1UL) /*!< Max enumerator value of PARTIALPWRDN field. */ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_DISABLED (0x0UL) /*!< Partial Power Down disabled */ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_ENABLED (0x1UL) /*!< Partial Power Down enabled */ + +/* AHBFREQ @Bit 5 : Minimum AHB Frequency Less Than 60 MHz (AhbFreq) */ + #define USBHSCORE_GHWCFG4_AHBFREQ_Pos (5UL) /*!< Position of AHBFREQ field. */ + #define USBHSCORE_GHWCFG4_AHBFREQ_Msk (0x1UL << USBHSCORE_GHWCFG4_AHBFREQ_Pos) /*!< Bit mask of AHBFREQ field. */ + #define USBHSCORE_GHWCFG4_AHBFREQ_Min (0x0UL) /*!< Min enumerator value of AHBFREQ field. */ + #define USBHSCORE_GHWCFG4_AHBFREQ_Max (0x1UL) /*!< Max enumerator value of AHBFREQ field. */ + #define USBHSCORE_GHWCFG4_AHBFREQ_DISABLED (0x0UL) /*!< Minimum AHB Frequency More Than 60 MHz */ + #define USBHSCORE_GHWCFG4_AHBFREQ_ENABLED (0x1UL) /*!< Minimum AHB Frequency Less Than 60 MHz */ + +/* HIBERNATION @Bit 6 : Enable Hibernation (Hibernation) */ + #define USBHSCORE_GHWCFG4_HIBERNATION_Pos (6UL) /*!< Position of HIBERNATION field. */ + #define USBHSCORE_GHWCFG4_HIBERNATION_Msk (0x1UL << USBHSCORE_GHWCFG4_HIBERNATION_Pos) /*!< Bit mask of HIBERNATION field. */ + #define USBHSCORE_GHWCFG4_HIBERNATION_Min (0x0UL) /*!< Min enumerator value of HIBERNATION field. */ + #define USBHSCORE_GHWCFG4_HIBERNATION_Max (0x1UL) /*!< Max enumerator value of HIBERNATION field. */ + #define USBHSCORE_GHWCFG4_HIBERNATION_DISABLED (0x0UL) /*!< Hibernation feature disabled */ + #define USBHSCORE_GHWCFG4_HIBERNATION_ENABLED (0x1UL) /*!< Hibernation feature enabled */ + +/* EXTENDEDHIBERNATION @Bit 7 : Enable Hibernation */ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Pos (7UL) /*!< Position of EXTENDEDHIBERNATION field. */ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Msk (0x1UL << USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Pos) /*!< Bit mask of + EXTENDEDHIBERNATION field.*/ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Min (0x0UL) /*!< Min enumerator value of EXTENDEDHIBERNATION field. */ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Max (0x1UL) /*!< Max enumerator value of EXTENDEDHIBERNATION field. */ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_DISABLED (0x0UL) /*!< Extended Hibernation feature not enabled */ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_ENABLED (0x1UL) /*!< Extended Hibernation feature enabled */ + +/* ENHANCEDLPMSUPT1 @Bit 9 : Enhanced LPM Support1 (EnhancedLPMSupt1) */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Pos (9UL) /*!< Position of ENHANCEDLPMSUPT1 field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Msk (0x1UL << USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Pos) /*!< Bit mask of + ENHANCEDLPMSUPT1 field.*/ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Min (0x0UL) /*!< Min enumerator value of ENHANCEDLPMSUPT1 field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Max (0x1UL) /*!< Max enumerator value of ENHANCEDLPMSUPT1 field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_DISABLED (0x0UL) /*!< Reject L1 Request even if Non-Periodic (Bulk/Interrupt) + TxFIFO is not empty.*/ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_ENABLED (0x1UL) /*!< Accept L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO + is not empty*/ + +/* SERVINTFLOW @Bit 10 : Service Interval Flow */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_Pos (10UL) /*!< Position of SERVINTFLOW field. */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_Msk (0x1UL << USBHSCORE_GHWCFG4_SERVINTFLOW_Pos) /*!< Bit mask of SERVINTFLOW field. */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_Min (0x0UL) /*!< Min enumerator value of SERVINTFLOW field. */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_Max (0x1UL) /*!< Max enumerator value of SERVINTFLOW field. */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_DISABLED (0x0UL) /*!< Service Interval Flow not supported */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_ENABLED (0x1UL) /*!< Service Interval Flow supported */ + +/* IPGISOCSUPT @Bit 11 : Interpacket Gap ISOC OUT Worst-case Support (ipgisocSupt) */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Pos (11UL) /*!< Position of IPGISOCSUPT field. */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Msk (0x1UL << USBHSCORE_GHWCFG4_IPGISOCSUPT_Pos) /*!< Bit mask of IPGISOCSUPT field. */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Min (0x0UL) /*!< Min enumerator value of IPGISOCSUPT field. */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Max (0x1UL) /*!< Max enumerator value of IPGISOCSUPT field. */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_DISABLED (0x0UL) /*!< Interpacket Gap ISOC OUT Worst-case Support is Disabled */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_ENABLED (0x1UL) /*!< Interpacket Gap ISOC OUT Worst-case Support is Enabled (Default) */ + +/* ACGSUPT @Bit 12 : Active Clock Gating Support */ + #define USBHSCORE_GHWCFG4_ACGSUPT_Pos (12UL) /*!< Position of ACGSUPT field. */ + #define USBHSCORE_GHWCFG4_ACGSUPT_Msk (0x1UL << USBHSCORE_GHWCFG4_ACGSUPT_Pos) /*!< Bit mask of ACGSUPT field. */ + #define USBHSCORE_GHWCFG4_ACGSUPT_Min (0x0UL) /*!< Min enumerator value of ACGSUPT field. */ + #define USBHSCORE_GHWCFG4_ACGSUPT_Max (0x1UL) /*!< Max enumerator value of ACGSUPT field. */ + #define USBHSCORE_GHWCFG4_ACGSUPT_DISABLED (0x0UL) /*!< (unspecified) */ + #define USBHSCORE_GHWCFG4_ACGSUPT_ENABLED (0x1UL) /*!< Active Clock Gating Support */ + +/* ENHANCEDLPMSUPT @Bit 13 : Enhanced LPM Support (EnhancedLPMSupt) */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Pos (13UL) /*!< Position of ENHANCEDLPMSUPT field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Msk (0x1UL << USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Pos) /*!< Bit mask of + ENHANCEDLPMSUPT field.*/ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Min (0x1UL) /*!< Min enumerator value of ENHANCEDLPMSUPT field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Max (0x1UL) /*!< Max enumerator value of ENHANCEDLPMSUPT field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_ENABLED (0x1UL) /*!< Enhanced LPM Support is enabled */ + +/* PHYDATAWIDTH @Bits 14..15 : UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Pos (14UL) /*!< Position of PHYDATAWIDTH field. */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Msk (0x3UL << USBHSCORE_GHWCFG4_PHYDATAWIDTH_Pos) /*!< Bit mask of PHYDATAWIDTH field.*/ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of PHYDATAWIDTH field. */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Max (0x2UL) /*!< Max enumerator value of PHYDATAWIDTH field. */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_WIDTH1 (0x0UL) /*!< 8 bits */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_WIDTH2 (0x1UL) /*!< 16 bits */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_WIDTH3 (0x2UL) /*!< 8/16 bits, software selectable */ + +/* NUMCTLEPS @Bits 16..19 : Number of Device Mode Control Endpoints in Addition to */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_Pos (16UL) /*!< Position of NUMCTLEPS field. */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_Msk (0xFUL << USBHSCORE_GHWCFG4_NUMCTLEPS_Pos) /*!< Bit mask of NUMCTLEPS field. */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_Min (0x0UL) /*!< Min enumerator value of NUMCTLEPS field. */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_Max (0xFUL) /*!< Max enumerator value of NUMCTLEPS field. */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT0 (0x0UL) /*!< End point 0 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT1 (0x1UL) /*!< End point 1 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT2 (0x2UL) /*!< End point 2 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT3 (0x3UL) /*!< End point 3 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT4 (0x4UL) /*!< End point 4 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT5 (0x5UL) /*!< End point 5 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT6 (0x6UL) /*!< End point 6 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT7 (0x7UL) /*!< End point 7 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT8 (0x8UL) /*!< End point 8 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT9 (0x9UL) /*!< End point 9 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT10 (0xAUL) /*!< End point 10 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT11 (0xBUL) /*!< End point 11 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT12 (0xCUL) /*!< End point 12 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT13 (0xDUL) /*!< End point 13 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT14 (0xEUL) /*!< End point 14 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT15 (0xFUL) /*!< End point 15 */ + +/* IDDGFLTR @Bit 20 : IDDIG Filter Enable (IddgFltr) */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_Pos (20UL) /*!< Position of IDDGFLTR field. */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_IDDGFLTR_Pos) /*!< Bit mask of IDDGFLTR field. */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_Min (0x0UL) /*!< Min enumerator value of IDDGFLTR field. */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_Max (0x1UL) /*!< Max enumerator value of IDDGFLTR field. */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_DISABLED (0x0UL) /*!< Iddig Filter Disabled */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_ENABLED (0x1UL) /*!< Iddig Filter Enabled */ + +/* VBUSVALIDFLTR @Bit 21 : VBUS Valid Filter Enabled (VBusValidFltr) */ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Pos (21UL) /*!< Position of VBUSVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Pos) /*!< Bit mask of VBUSVALIDFLTR + field.*/ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Min (0x0UL) /*!< Min enumerator value of VBUSVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Max (0x1UL) /*!< Max enumerator value of VBUSVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_DISABLED (0x0UL) /*!< Vbus Valid Filter Disabled */ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_ENABLED (0x1UL) /*!< Vbus Valid Filter Enabled */ + +/* AVALIDFLTR @Bit 22 : a_valid Filter Enabled (AValidFltr) */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_Pos (22UL) /*!< Position of AVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_AVALIDFLTR_Pos) /*!< Bit mask of AVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_Min (0x0UL) /*!< Min enumerator value of AVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_Max (0x1UL) /*!< Max enumerator value of AVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_DISABLED (0x0UL) /*!< No filter */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_ENABLED (0x1UL) /*!< Filter */ + +/* BVALIDFLTR @Bit 23 : b_valid Filter Enabled (BValidFltr) */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_Pos (23UL) /*!< Position of BVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_BVALIDFLTR_Pos) /*!< Bit mask of BVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_Min (0x0UL) /*!< Min enumerator value of BVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_Max (0x1UL) /*!< Max enumerator value of BVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_DISABLED (0x0UL) /*!< No Filter */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_ENABLED (0x1UL) /*!< Filter */ + +/* SESSENDFLTR @Bit 24 : session_end Filter Enabled (SessEndFltr) */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_Pos (24UL) /*!< Position of SESSENDFLTR field. */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_SESSENDFLTR_Pos) /*!< Bit mask of SESSENDFLTR field. */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_Min (0x0UL) /*!< Min enumerator value of SESSENDFLTR field. */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_Max (0x1UL) /*!< Max enumerator value of SESSENDFLTR field. */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_DISABLED (0x0UL) /*!< No filter */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_ENABLED (0x1UL) /*!< Filter */ + +/* DEDFIFOMODE @Bit 25 : Enable Dedicated Transmit FIFO for device IN Endpoints */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Pos (25UL) /*!< Position of DEDFIFOMODE field. */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Msk (0x1UL << USBHSCORE_GHWCFG4_DEDFIFOMODE_Pos) /*!< Bit mask of DEDFIFOMODE field. */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Min (0x0UL) /*!< Min enumerator value of DEDFIFOMODE field. */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Max (0x1UL) /*!< Max enumerator value of DEDFIFOMODE field. */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_DISABLED (0x0UL) /*!< Dedicated Transmit FIFO Operation not enabled */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_ENABLED (0x1UL) /*!< Dedicated Transmit FIFO Operation enabled */ + +/* INEPS @Bits 26..29 : Number of Device Mode IN Endpoints Including Control Endpoints (INEps) */ + #define USBHSCORE_GHWCFG4_INEPS_Pos (26UL) /*!< Position of INEPS field. */ + #define USBHSCORE_GHWCFG4_INEPS_Msk (0xFUL << USBHSCORE_GHWCFG4_INEPS_Pos) /*!< Bit mask of INEPS field. */ + #define USBHSCORE_GHWCFG4_INEPS_Min (0x0UL) /*!< Min enumerator value of INEPS field. */ + #define USBHSCORE_GHWCFG4_INEPS_Max (0xFUL) /*!< Max enumerator value of INEPS field. */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT1 (0x0UL) /*!< 1 IN Endpoint */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT2 (0x1UL) /*!< 2 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT3 (0x2UL) /*!< 3 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT4 (0x3UL) /*!< 4 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT5 (0x4UL) /*!< 5 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT6 (0x5UL) /*!< 6 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT7 (0x6UL) /*!< 7 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT8 (0x7UL) /*!< 8 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT9 (0x8UL) /*!< 9 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT10 (0x9UL) /*!< 10 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT11 (0xAUL) /*!< 11 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT12 (0xBUL) /*!< 12 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT13 (0xCUL) /*!< 13 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT14 (0xDUL) /*!< 14 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT15 (0xEUL) /*!< 15 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT16 (0xFUL) /*!< 16 IN Endpoints */ + +/* DESCDMAENABLED @Bit 30 : Scatter/Gather DMA configuration */ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Pos (30UL) /*!< Position of DESCDMAENABLED field. */ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Msk (0x1UL << USBHSCORE_GHWCFG4_DESCDMAENABLED_Pos) /*!< Bit mask of DESCDMAENABLED + field.*/ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Min (0x0UL) /*!< Min enumerator value of DESCDMAENABLED field. */ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Max (0x1UL) /*!< Max enumerator value of DESCDMAENABLED field. */ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_DISABLE (0x0UL) /*!< Non-Scatter/Gather DMA configuration */ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_ENABLE (0x1UL) /*!< Scatter/Gather DMA configuration */ + +/* DESCDMA @Bit 31 : Scatter/Gather DMA configuration */ + #define USBHSCORE_GHWCFG4_DESCDMA_Pos (31UL) /*!< Position of DESCDMA field. */ + #define USBHSCORE_GHWCFG4_DESCDMA_Msk (0x1UL << USBHSCORE_GHWCFG4_DESCDMA_Pos) /*!< Bit mask of DESCDMA field. */ + #define USBHSCORE_GHWCFG4_DESCDMA_Min (0x0UL) /*!< Min enumerator value of DESCDMA field. */ + #define USBHSCORE_GHWCFG4_DESCDMA_Max (0x1UL) /*!< Max enumerator value of DESCDMA field. */ + #define USBHSCORE_GHWCFG4_DESCDMA_CONFIG1 (0x0UL) /*!< Non Dynamic configuration */ + #define USBHSCORE_GHWCFG4_DESCDMA_CONFIG2 (0x1UL) /*!< Dynamic configuration */ + + +/* USBHSCORE_GLPMCFG: LPM Config Register */ + #define USBHSCORE_GLPMCFG_ResetValue (0x00000000UL) /*!< Reset value of GLPMCFG register. */ + +/* LPMCAP @Bit 0 : LPM-Capable (LPMCap) */ + #define USBHSCORE_GLPMCFG_LPMCAP_Pos (0UL) /*!< Position of LPMCAP field. */ + #define USBHSCORE_GLPMCFG_LPMCAP_Msk (0x1UL << USBHSCORE_GLPMCFG_LPMCAP_Pos) /*!< Bit mask of LPMCAP field. */ + #define USBHSCORE_GLPMCFG_LPMCAP_Min (0x0UL) /*!< Min enumerator value of LPMCAP field. */ + #define USBHSCORE_GLPMCFG_LPMCAP_Max (0x1UL) /*!< Max enumerator value of LPMCAP field. */ + #define USBHSCORE_GLPMCFG_LPMCAP_DISABLED (0x0UL) /*!< LPM capability is not enabled */ + #define USBHSCORE_GLPMCFG_LPMCAP_ENABLED (0x1UL) /*!< LPM capability is enabled */ + +/* APPL1RES @Bit 1 : Mode: Device only. LPM response programmed by application (AppL1Res) */ + #define USBHSCORE_GLPMCFG_APPL1RES_Pos (1UL) /*!< Position of APPL1RES field. */ + #define USBHSCORE_GLPMCFG_APPL1RES_Msk (0x1UL << USBHSCORE_GLPMCFG_APPL1RES_Pos) /*!< Bit mask of APPL1RES field. */ + #define USBHSCORE_GLPMCFG_APPL1RES_Min (0x0UL) /*!< Min enumerator value of APPL1RES field. */ + #define USBHSCORE_GLPMCFG_APPL1RES_Max (0x1UL) /*!< Max enumerator value of APPL1RES field. */ + #define USBHSCORE_GLPMCFG_APPL1RES_NYETRESP (0x0UL) /*!< The core responds with a NYET when an error is detected in either of + the LPM token packets due to corruption*/ + #define USBHSCORE_GLPMCFG_APPL1RES_ACKRESP (0x1UL) /*!< The core responds with an ACK only on a successful LPM transaction */ + +/* HIRD @Bits 2..5 : Host-Initiated Resume Duration (HIRD) */ + #define USBHSCORE_GLPMCFG_HIRD_Pos (2UL) /*!< Position of HIRD field. */ + #define USBHSCORE_GLPMCFG_HIRD_Msk (0xFUL << USBHSCORE_GLPMCFG_HIRD_Pos) /*!< Bit mask of HIRD field. */ + +/* BREMOTEWAKE @Bit 6 : RemoteWakeEnable (bRemoteWake) */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Pos (6UL) /*!< Position of BREMOTEWAKE field. */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Msk (0x1UL << USBHSCORE_GLPMCFG_BREMOTEWAKE_Pos) /*!< Bit mask of BREMOTEWAKE field. */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Min (0x0UL) /*!< Min enumerator value of BREMOTEWAKE field. */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Max (0x1UL) /*!< Max enumerator value of BREMOTEWAKE field. */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_DISABLED (0x0UL) /*!< Remote Wakeup is disabled */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_ENABLED (0x1UL) /*!< In Host or device mode, this field takes the value of remote wake + up*/ + +/* ENBLSLPM @Bit 7 : Enable utmi_sleep_n (EnblSlpM) */ + #define USBHSCORE_GLPMCFG_ENBLSLPM_Pos (7UL) /*!< Position of ENBLSLPM field. */ + #define USBHSCORE_GLPMCFG_ENBLSLPM_Msk (0x1UL << USBHSCORE_GLPMCFG_ENBLSLPM_Pos) /*!< Bit mask of ENBLSLPM field. */ + #define USBHSCORE_GLPMCFG_ENBLSLPM_Min (0x0UL) /*!< Min enumerator value of ENBLSLPM field. */ + #define USBHSCORE_GLPMCFG_ENBLSLPM_Max (0x1UL) /*!< Max enumerator value of ENBLSLPM field. */ + #define USBHSCORE_GLPMCFG_ENBLSLPM_DISABLED (0x0UL) /*!< utmi_sleep_n assertion from the core is not transferred to the + external PHY*/ + #define USBHSCORE_GLPMCFG_ENBLSLPM_ENABLED (0x1UL) /*!< utmi_sleep_n assertion from the core is transferred to the external + PHY when utmi_l1_suspend_n cannot be asserted*/ + +/* HIRDTHRES @Bits 8..12 : BESL/HIRD Threshold (HIRD_Thres) */ + #define USBHSCORE_GLPMCFG_HIRDTHRES_Pos (8UL) /*!< Position of HIRDTHRES field. */ + #define USBHSCORE_GLPMCFG_HIRDTHRES_Msk (0x1FUL << USBHSCORE_GLPMCFG_HIRDTHRES_Pos) /*!< Bit mask of HIRDTHRES field. */ + +/* COREL1RES @Bits 13..14 : LPM Response (CoreL1Res) */ + #define USBHSCORE_GLPMCFG_COREL1RES_Pos (13UL) /*!< Position of COREL1RES field. */ + #define USBHSCORE_GLPMCFG_COREL1RES_Msk (0x3UL << USBHSCORE_GLPMCFG_COREL1RES_Pos) /*!< Bit mask of COREL1RES field. */ + #define USBHSCORE_GLPMCFG_COREL1RES_Min (0x0UL) /*!< Min enumerator value of COREL1RES field. */ + #define USBHSCORE_GLPMCFG_COREL1RES_Max (0x3UL) /*!< Max enumerator value of COREL1RES field. */ + #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP1 (0x0UL) /*!< ERROR : No handshake response */ + #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP2 (0x1UL) /*!< STALL response */ + #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP3 (0x2UL) /*!< NYET response */ + #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP4 (0x3UL) /*!< ACK response */ + +/* SLPSTS @Bit 15 : Port Sleep Status (SlpSts) */ + #define USBHSCORE_GLPMCFG_SLPSTS_Pos (15UL) /*!< Position of SLPSTS field. */ + #define USBHSCORE_GLPMCFG_SLPSTS_Msk (0x1UL << USBHSCORE_GLPMCFG_SLPSTS_Pos) /*!< Bit mask of SLPSTS field. */ + #define USBHSCORE_GLPMCFG_SLPSTS_Min (0x0UL) /*!< Min enumerator value of SLPSTS field. */ + #define USBHSCORE_GLPMCFG_SLPSTS_Max (0x1UL) /*!< Max enumerator value of SLPSTS field. */ + #define USBHSCORE_GLPMCFG_SLPSTS_CORENOTINL1 (0x0UL) /*!< In Host or Device mode, this bit indicates core is not in L1 */ + #define USBHSCORE_GLPMCFG_SLPSTS_COREINL1 (0x1UL) /*!< In Host mode, this bit indicates the core transitions to Sleep state + as a successful LPM transaction. In Device mode, the core enters the + Sleep state when an ACK response is sent to an LPM transaction*/ + +/* L1RESUMEOK @Bit 16 : Sleep State Resume OK (L1ResumeOK) */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_Pos (16UL) /*!< Position of L1RESUMEOK field. */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_Msk (0x1UL << USBHSCORE_GLPMCFG_L1RESUMEOK_Pos) /*!< Bit mask of L1RESUMEOK field. */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_Min (0x0UL) /*!< Min enumerator value of L1RESUMEOK field. */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_Max (0x1UL) /*!< Max enumerator value of L1RESUMEOK field. */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_NOTOK (0x0UL) /*!< The application/core cannot start Resume from Sleep state */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_OK (0x1UL) /*!< The application/core can start Resume from Sleep state */ + +/* LPMCHNLINDX @Bits 17..20 : LPM Channel Index */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Pos (17UL) /*!< Position of LPMCHNLINDX field. */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Msk (0xFUL << USBHSCORE_GLPMCFG_LPMCHNLINDX_Pos) /*!< Bit mask of LPMCHNLINDX field. */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Min (0x0UL) /*!< Min enumerator value of LPMCHNLINDX field. */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Max (0xFUL) /*!< Max enumerator value of LPMCHNLINDX field. */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH0 (0x0UL) /*!< Channel 0 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH1 (0x1UL) /*!< Channel 1 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH2 (0x2UL) /*!< Channel 2 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH3 (0x3UL) /*!< Channel 3 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH4 (0x4UL) /*!< Channel 4 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH5 (0x5UL) /*!< Channel 5 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH6 (0x6UL) /*!< Channel 6 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH7 (0x7UL) /*!< Channel 7 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH8 (0x8UL) /*!< Channel 8 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH9 (0x9UL) /*!< Channel 9 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH10 (0xAUL) /*!< Channel 10 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH11 (0xBUL) /*!< Channel 11 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH12 (0xCUL) /*!< Channel 12 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH13 (0xDUL) /*!< Channel 13 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH14 (0xEUL) /*!< Channel 14 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH15 (0xFUL) /*!< Channel15 */ + +/* LPMRETRYCNT @Bits 21..23 : LPM Retry Count (LPM_Retry_Cnt) */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Pos (21UL) /*!< Position of LPMRETRYCNT field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Msk (0x7UL << USBHSCORE_GLPMCFG_LPMRETRYCNT_Pos) /*!< Bit mask of LPMRETRYCNT field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Min (0x0UL) /*!< Min enumerator value of LPMRETRYCNT field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Max (0x7UL) /*!< Max enumerator value of LPMRETRYCNT field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY0 (0x0UL) /*!< Zero LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY1 (0x1UL) /*!< One LPM retry */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY2 (0x2UL) /*!< Two LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY3 (0x3UL) /*!< Three LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY4 (0x4UL) /*!< Four LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY5 (0x5UL) /*!< Five LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY6 (0x6UL) /*!< Six LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY7 (0x7UL) /*!< Seven LPM retries */ + +/* SNDLPM @Bit 24 : Send LPM Transaction (SndLPM) */ + #define USBHSCORE_GLPMCFG_SNDLPM_Pos (24UL) /*!< Position of SNDLPM field. */ + #define USBHSCORE_GLPMCFG_SNDLPM_Msk (0x1UL << USBHSCORE_GLPMCFG_SNDLPM_Pos) /*!< Bit mask of SNDLPM field. */ + #define USBHSCORE_GLPMCFG_SNDLPM_Min (0x0UL) /*!< Min enumerator value of SNDLPM field. */ + #define USBHSCORE_GLPMCFG_SNDLPM_Max (0x1UL) /*!< Max enumerator value of SNDLPM field. */ + #define USBHSCORE_GLPMCFG_SNDLPM_DISABLED (0x0UL) /*!< In host-only mode: Received the response from the device for the LPM + transaction*/ + #define USBHSCORE_GLPMCFG_SNDLPM_ENABLED (0x1UL) /*!< In host-only mode: Sending LPM transaction containing EXT and LPM + tokens*/ + +/* LPMRETRYCNTSTS @Bits 25..27 : LPM Retry Count Status (LPM_RetryCnt_Sts) */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Pos (25UL) /*!< Position of LPMRETRYCNTSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Msk (0x7UL << USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Pos) /*!< Bit mask of LPMRETRYCNTSTS + field.*/ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Min (0x0UL) /*!< Min enumerator value of LPMRETRYCNTSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Max (0x7UL) /*!< Max enumerator value of LPMRETRYCNTSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRYREM0 (0x0UL) /*!< Zero LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRYREM1 (0x1UL) /*!< One LPM retry remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRYREM2 (0x2UL) /*!< Two LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRYREM3 (0x3UL) /*!< Three LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRYREM4 (0x4UL) /*!< Four LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRYREM5 (0x5UL) /*!< Five LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRYREM6 (0x6UL) /*!< Six LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRYREM7 (0x7UL) /*!< Seven LPM retries remaining */ + +/* LPMENBESL @Bit 28 : LPM Enable BESL (LPM_EnBESL) */ + #define USBHSCORE_GLPMCFG_LPMENBESL_Pos (28UL) /*!< Position of LPMENBESL field. */ + #define USBHSCORE_GLPMCFG_LPMENBESL_Msk (0x1UL << USBHSCORE_GLPMCFG_LPMENBESL_Pos) /*!< Bit mask of LPMENBESL field. */ + #define USBHSCORE_GLPMCFG_LPMENBESL_Min (0x0UL) /*!< Min enumerator value of LPMENBESL field. */ + #define USBHSCORE_GLPMCFG_LPMENBESL_Max (0x1UL) /*!< Max enumerator value of LPMENBESL field. */ + #define USBHSCORE_GLPMCFG_LPMENBESL_DISABLED (0x0UL) /*!< BESL is disabled */ + #define USBHSCORE_GLPMCFG_LPMENBESL_ENABLED (0x1UL) /*!< BESL is enabled as defined in LPM Errata */ + +/* LPMRESTORESLPSTS @Bit 29 : LPM Restore Sleep Status (LPM_RestoreSlpSts) */ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Pos (29UL) /*!< Position of LPMRESTORESLPSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Msk (0x1UL << USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Pos) /*!< Bit mask of + LPMRESTORESLPSTS field.*/ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Min (0x0UL) /*!< Min enumerator value of LPMRESTORESLPSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Max (0x1UL) /*!< Max enumerator value of LPMRESTORESLPSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_DISABLED (0x0UL) /*!< Puts the core in Shallow Sleep mode based on the BESL value + from the Host*/ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_ENABLED (0x1UL) /*!< Puts the core in Deep Sleep mode based on the BESL value from + the Host*/ + + +/* USBHSCORE_GPWRDN: Global Power Down Register */ + #define USBHSCORE_GPWRDN_ResetValue (0x00000010UL) /*!< Reset value of GPWRDN register. */ + +/* PMUINTSEL @Bit 0 : PMU Interrupt Select (PMUIntSel) */ + #define USBHSCORE_GPWRDN_PMUINTSEL_Pos (0UL) /*!< Position of PMUINTSEL field. */ + #define USBHSCORE_GPWRDN_PMUINTSEL_Msk (0x1UL << USBHSCORE_GPWRDN_PMUINTSEL_Pos) /*!< Bit mask of PMUINTSEL field. */ + #define USBHSCORE_GPWRDN_PMUINTSEL_Min (0x0UL) /*!< Min enumerator value of PMUINTSEL field. */ + #define USBHSCORE_GPWRDN_PMUINTSEL_Max (0x1UL) /*!< Max enumerator value of PMUINTSEL field. */ + #define USBHSCORE_GPWRDN_PMUINTSEL_DISABLE (0x0UL) /*!< Internal DWC_otg_core interrupt is selected */ + #define USBHSCORE_GPWRDN_PMUINTSEL_ENABLE (0x1UL) /*!< External DWC_otg_pmu interrupt is selected */ + +/* PMUACTV @Bit 1 : PMU Active (PMUActv) */ + #define USBHSCORE_GPWRDN_PMUACTV_Pos (1UL) /*!< Position of PMUACTV field. */ + #define USBHSCORE_GPWRDN_PMUACTV_Msk (0x1UL << USBHSCORE_GPWRDN_PMUACTV_Pos) /*!< Bit mask of PMUACTV field. */ + #define USBHSCORE_GPWRDN_PMUACTV_Min (0x0UL) /*!< Min enumerator value of PMUACTV field. */ + #define USBHSCORE_GPWRDN_PMUACTV_Max (0x1UL) /*!< Max enumerator value of PMUACTV field. */ + #define USBHSCORE_GPWRDN_PMUACTV_DISABLE (0x0UL) /*!< Disable PMU module */ + #define USBHSCORE_GPWRDN_PMUACTV_ENABLE (0x1UL) /*!< Enable PMU module */ + +/* RESTORE @Bit 2 : Restore */ + #define USBHSCORE_GPWRDN_RESTORE_Pos (2UL) /*!< Position of RESTORE field. */ + #define USBHSCORE_GPWRDN_RESTORE_Msk (0x1UL << USBHSCORE_GPWRDN_RESTORE_Pos) /*!< Bit mask of RESTORE field. */ + #define USBHSCORE_GPWRDN_RESTORE_Min (0x0UL) /*!< Min enumerator value of RESTORE field. */ + #define USBHSCORE_GPWRDN_RESTORE_Max (0x1UL) /*!< Max enumerator value of RESTORE field. */ + #define USBHSCORE_GPWRDN_RESTORE_DISABLE (0x0UL) /*!< The controller in normal mode of operation */ + #define USBHSCORE_GPWRDN_RESTORE_ENABLE (0x1UL) /*!< The controller in Restore mode */ + +/* PWRDNCLMP @Bit 3 : Power Down Clamp (PwrDnClmp) */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_Pos (3UL) /*!< Position of PWRDNCLMP field. */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_Msk (0x1UL << USBHSCORE_GPWRDN_PWRDNCLMP_Pos) /*!< Bit mask of PWRDNCLMP field. */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_Min (0x0UL) /*!< Min enumerator value of PWRDNCLMP field. */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_Max (0x1UL) /*!< Max enumerator value of PWRDNCLMP field. */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_DISABLE (0x0UL) /*!< Disable PMU power clamp */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_ENABLE (0x1UL) /*!< Enable PMU power clamp */ + +/* PWRDNRSTN @Bit 4 : Power Down ResetN (PwrDnRst_n) */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_Pos (4UL) /*!< Position of PWRDNRSTN field. */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_Msk (0x1UL << USBHSCORE_GPWRDN_PWRDNRSTN_Pos) /*!< Bit mask of PWRDNRSTN field. */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_Min (0x0UL) /*!< Min enumerator value of PWRDNRSTN field. */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_Max (0x1UL) /*!< Max enumerator value of PWRDNRSTN field. */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_DISABLE (0x0UL) /*!< Reset the controller */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_ENABLE (0x1UL) /*!< The controller is in normal operation */ + +/* PWRDNSWTCH @Bit 5 : Power Down Switch (PwrDnSwtch) */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_Pos (5UL) /*!< Position of PWRDNSWTCH field. */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_Msk (0x1UL << USBHSCORE_GPWRDN_PWRDNSWTCH_Pos) /*!< Bit mask of PWRDNSWTCH field. */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_Min (0x0UL) /*!< Min enumerator value of PWRDNSWTCH field. */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_Max (0x1UL) /*!< Max enumerator value of PWRDNSWTCH field. */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_ON (0x0UL) /*!< The controller is in ON state */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_OFF (0x1UL) /*!< The controller is in OFF state */ + +/* DISABLEVBUS @Bit 6 : DisableVBUS */ + #define USBHSCORE_GPWRDN_DISABLEVBUS_Pos (6UL) /*!< Position of DISABLEVBUS field. */ + #define USBHSCORE_GPWRDN_DISABLEVBUS_Msk (0x1UL << USBHSCORE_GPWRDN_DISABLEVBUS_Pos) /*!< Bit mask of DISABLEVBUS field. */ + #define USBHSCORE_GPWRDN_DISABLEVBUS_Min (0x0UL) /*!< Min enumerator value of DISABLEVBUS field. */ + #define USBHSCORE_GPWRDN_DISABLEVBUS_Max (0x1UL) /*!< Max enumerator value of DISABLEVBUS field. */ + #define USBHSCORE_GPWRDN_DISABLEVBUS_DISABLED (0x0UL) /*!< Host mode:HPRT0.PrtPwr was not programmed to 0, and in Device + mode:Session Valid*/ + #define USBHSCORE_GPWRDN_DISABLEVBUS_ENABLED (0x1UL) /*!< Host mode:HPRT0.PrtPwr was programmed to 0 and in Device + mode:Session End*/ + +/* LNSTSCHNG @Bit 7 : Line State Change (LnStsChng) */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_Pos (7UL) /*!< Position of LNSTSCHNG field. */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_Msk (0x1UL << USBHSCORE_GPWRDN_LNSTSCHNG_Pos) /*!< Bit mask of LNSTSCHNG field. */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_Min (0x0UL) /*!< Min enumerator value of LNSTSCHNG field. */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_Max (0x1UL) /*!< Max enumerator value of LNSTSCHNG field. */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_DISABLED (0x0UL) /*!< No LineState change on USB */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_ENABLED (0x1UL) /*!< LineState change on USB */ + +/* LINESTAGECHANGEMSK @Bit 8 : LineStageChangeMsk */ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Pos (8UL) /*!< Position of LINESTAGECHANGEMSK field. */ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Msk (0x1UL << USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Pos) /*!< Bit mask of + LINESTAGECHANGEMSK field.*/ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Min (0x0UL) /*!< Min enumerator value of LINESTAGECHANGEMSK field. */ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Max (0x1UL) /*!< Max enumerator value of LINESTAGECHANGEMSK field. */ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_MASK (0x0UL) /*!< Mask for LineStateChange Interrupt */ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_NOMASK (0x1UL) /*!< No LineStateChange Interrupt Mask */ + +/* RESETDETECTED @Bit 9 : ResetDetected */ + #define USBHSCORE_GPWRDN_RESETDETECTED_Pos (9UL) /*!< Position of RESETDETECTED field. */ + #define USBHSCORE_GPWRDN_RESETDETECTED_Msk (0x1UL << USBHSCORE_GPWRDN_RESETDETECTED_Pos) /*!< Bit mask of RESETDETECTED + field.*/ + #define USBHSCORE_GPWRDN_RESETDETECTED_Min (0x0UL) /*!< Min enumerator value of RESETDETECTED field. */ + #define USBHSCORE_GPWRDN_RESETDETECTED_Max (0x1UL) /*!< Max enumerator value of RESETDETECTED field. */ + #define USBHSCORE_GPWRDN_RESETDETECTED_DISABLED (0x0UL) /*!< Reset not detected */ + #define USBHSCORE_GPWRDN_RESETDETECTED_ENABLED (0x1UL) /*!< Reset detected */ + +/* RESETDETMSK @Bit 10 : ResetDetMsk */ + #define USBHSCORE_GPWRDN_RESETDETMSK_Pos (10UL) /*!< Position of RESETDETMSK field. */ + #define USBHSCORE_GPWRDN_RESETDETMSK_Msk (0x1UL << USBHSCORE_GPWRDN_RESETDETMSK_Pos) /*!< Bit mask of RESETDETMSK field. */ + #define USBHSCORE_GPWRDN_RESETDETMSK_Min (0x0UL) /*!< Min enumerator value of RESETDETMSK field. */ + #define USBHSCORE_GPWRDN_RESETDETMSK_Max (0x1UL) /*!< Max enumerator value of RESETDETMSK field. */ + #define USBHSCORE_GPWRDN_RESETDETMSK_MASK (0x0UL) /*!< Mask for ResetDetect Interrupt */ + #define USBHSCORE_GPWRDN_RESETDETMSK_NOMASK (0x1UL) /*!< No ResetDetect Interrupt Mask */ + +/* DISCONNECTDETECT @Bit 11 : DisconnectDetect */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Pos (11UL) /*!< Position of DISCONNECTDETECT field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Msk (0x1UL << USBHSCORE_GPWRDN_DISCONNECTDETECT_Pos) /*!< Bit mask of + DISCONNECTDETECT field.*/ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Min (0x0UL) /*!< Min enumerator value of DISCONNECTDETECT field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Max (0x1UL) /*!< Max enumerator value of DISCONNECTDETECT field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_DISABLED (0x0UL) /*!< Disconnect not detected */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_ENABLED (0x1UL) /*!< Disconnect detected */ + +/* DISCONNECTDETECTMSK @Bit 12 : DisconnectDetectMsk */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Pos (12UL) /*!< Position of DISCONNECTDETECTMSK field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Msk (0x1UL << USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Pos) /*!< Bit mask of + DISCONNECTDETECTMSK field.*/ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Min (0x0UL) /*!< Min enumerator value of DISCONNECTDETECTMSK field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Max (0x1UL) /*!< Max enumerator value of DISCONNECTDETECTMSK field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_MASK (0x0UL) /*!< Mask for DisconnectDetect Interrupt */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_NOMASK (0x1UL) /*!< No DisconnectDetect Interrupt Mask */ + +/* CONNECTDET @Bit 13 : ConnectDet */ + #define USBHSCORE_GPWRDN_CONNECTDET_Pos (13UL) /*!< Position of CONNECTDET field. */ + #define USBHSCORE_GPWRDN_CONNECTDET_Msk (0x1UL << USBHSCORE_GPWRDN_CONNECTDET_Pos) /*!< Bit mask of CONNECTDET field. */ + #define USBHSCORE_GPWRDN_CONNECTDET_Min (0x0UL) /*!< Min enumerator value of CONNECTDET field. */ + #define USBHSCORE_GPWRDN_CONNECTDET_Max (0x1UL) /*!< Max enumerator value of CONNECTDET field. */ + #define USBHSCORE_GPWRDN_CONNECTDET_DISABLED (0x0UL) /*!< Connect not detected */ + #define USBHSCORE_GPWRDN_CONNECTDET_ENABLED (0x1UL) /*!< Connect detected */ + +/* CONNDETMSK @Bit 14 : ConnDetMsk */ + #define USBHSCORE_GPWRDN_CONNDETMSK_Pos (14UL) /*!< Position of CONNDETMSK field. */ + #define USBHSCORE_GPWRDN_CONNDETMSK_Msk (0x1UL << USBHSCORE_GPWRDN_CONNDETMSK_Pos) /*!< Bit mask of CONNDETMSK field. */ + #define USBHSCORE_GPWRDN_CONNDETMSK_Min (0x0UL) /*!< Min enumerator value of CONNDETMSK field. */ + #define USBHSCORE_GPWRDN_CONNDETMSK_Max (0x1UL) /*!< Max enumerator value of CONNDETMSK field. */ + #define USBHSCORE_GPWRDN_CONNDETMSK_NOMASK (0x0UL) /*!< No ConnectDet Interrupt Mask */ + #define USBHSCORE_GPWRDN_CONNDETMSK_MASK (0x1UL) /*!< Mask for ConnectDet Interrupt */ + +/* SRPDETECT @Bit 15 : SRPDetect */ + #define USBHSCORE_GPWRDN_SRPDETECT_Pos (15UL) /*!< Position of SRPDETECT field. */ + #define USBHSCORE_GPWRDN_SRPDETECT_Msk (0x1UL << USBHSCORE_GPWRDN_SRPDETECT_Pos) /*!< Bit mask of SRPDETECT field. */ + #define USBHSCORE_GPWRDN_SRPDETECT_Min (0x0UL) /*!< Min enumerator value of SRPDETECT field. */ + #define USBHSCORE_GPWRDN_SRPDETECT_Max (0x1UL) /*!< Max enumerator value of SRPDETECT field. */ + #define USBHSCORE_GPWRDN_SRPDETECT_DISABLED (0x0UL) /*!< SRP not detected */ + #define USBHSCORE_GPWRDN_SRPDETECT_ENABLED (0x1UL) /*!< SRP detected */ + +/* SRPDETECTMSK @Bit 16 : SRPDetectMsk */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_Pos (16UL) /*!< Position of SRPDETECTMSK field. */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_Msk (0x1UL << USBHSCORE_GPWRDN_SRPDETECTMSK_Pos) /*!< Bit mask of SRPDETECTMSK field. */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_Min (0x0UL) /*!< Min enumerator value of SRPDETECTMSK field. */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_Max (0x1UL) /*!< Max enumerator value of SRPDETECTMSK field. */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_NOMASK (0x0UL) /*!< No SRPDetect Interrupt Mask */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_MASK (0x1UL) /*!< Mask for SRPDetect Interrupt */ + +/* STSCHNGINT @Bit 17 : Status Change Interrupt (StsChngInt) */ + #define USBHSCORE_GPWRDN_STSCHNGINT_Pos (17UL) /*!< Position of STSCHNGINT field. */ + #define USBHSCORE_GPWRDN_STSCHNGINT_Msk (0x1UL << USBHSCORE_GPWRDN_STSCHNGINT_Pos) /*!< Bit mask of STSCHNGINT field. */ + #define USBHSCORE_GPWRDN_STSCHNGINT_Min (0x0UL) /*!< Min enumerator value of STSCHNGINT field. */ + #define USBHSCORE_GPWRDN_STSCHNGINT_Max (0x1UL) /*!< Max enumerator value of STSCHNGINT field. */ + #define USBHSCORE_GPWRDN_STSCHNGINT_DISABLED (0x0UL) /*!< No Status change */ + #define USBHSCORE_GPWRDN_STSCHNGINT_ENABLED (0x1UL) /*!< Status change detected */ + +/* STSCHNGINTMSK @Bit 18 : StsChngIntMsk */ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Pos (18UL) /*!< Position of STSCHNGINTMSK field. */ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Msk (0x1UL << USBHSCORE_GPWRDN_STSCHNGINTMSK_Pos) /*!< Bit mask of STSCHNGINTMSK + field.*/ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Min (0x0UL) /*!< Min enumerator value of STSCHNGINTMSK field. */ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Max (0x1UL) /*!< Max enumerator value of STSCHNGINTMSK field. */ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_MASK (0x0UL) /*!< Mask for Status Change Interrupt */ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_NOMASK (0x1UL) /*!< No Status Change Interrupt Mask */ + +/* LINESTATE @Bits 19..20 : LineState */ + #define USBHSCORE_GPWRDN_LINESTATE_Pos (19UL) /*!< Position of LINESTATE field. */ + #define USBHSCORE_GPWRDN_LINESTATE_Msk (0x3UL << USBHSCORE_GPWRDN_LINESTATE_Pos) /*!< Bit mask of LINESTATE field. */ + #define USBHSCORE_GPWRDN_LINESTATE_Min (0x0UL) /*!< Min enumerator value of LINESTATE field. */ + #define USBHSCORE_GPWRDN_LINESTATE_Max (0x3UL) /*!< Max enumerator value of LINESTATE field. */ + #define USBHSCORE_GPWRDN_LINESTATE_LS1 (0x0UL) /*!< Linestate on USB: DM = 0, DP = 0 */ + #define USBHSCORE_GPWRDN_LINESTATE_LS2 (0x1UL) /*!< Linestate on USB: DM = 0, DP = 1 */ + #define USBHSCORE_GPWRDN_LINESTATE_LS3 (0x2UL) /*!< Linestate on USB: DM = 1, DP = 0 */ + #define USBHSCORE_GPWRDN_LINESTATE_LS4 (0x3UL) /*!< Linestate on USB: Not-defined */ + +/* IDDIG @Bit 21 : This bit indicates the status of the signal IDDIG. The application must read this bit after receiving + GPWRDN.StsChngInt and decode based on the previous value stored by the application. */ + + #define USBHSCORE_GPWRDN_IDDIG_Pos (21UL) /*!< Position of IDDIG field. */ + #define USBHSCORE_GPWRDN_IDDIG_Msk (0x1UL << USBHSCORE_GPWRDN_IDDIG_Pos) /*!< Bit mask of IDDIG field. */ + #define USBHSCORE_GPWRDN_IDDIG_Min (0x0UL) /*!< Min enumerator value of IDDIG field. */ + #define USBHSCORE_GPWRDN_IDDIG_Max (0x1UL) /*!< Max enumerator value of IDDIG field. */ + #define USBHSCORE_GPWRDN_IDDIG_DISABLED (0x0UL) /*!< Host Mode */ + #define USBHSCORE_GPWRDN_IDDIG_ENABLED (0x1UL) /*!< Device Mode */ + +/* BSESSVLD @Bit 22 : B Session Valid (BSessVld) */ + #define USBHSCORE_GPWRDN_BSESSVLD_Pos (22UL) /*!< Position of BSESSVLD field. */ + #define USBHSCORE_GPWRDN_BSESSVLD_Msk (0x1UL << USBHSCORE_GPWRDN_BSESSVLD_Pos) /*!< Bit mask of BSESSVLD field. */ + #define USBHSCORE_GPWRDN_BSESSVLD_Min (0x0UL) /*!< Min enumerator value of BSESSVLD field. */ + #define USBHSCORE_GPWRDN_BSESSVLD_Max (0x1UL) /*!< Max enumerator value of BSESSVLD field. */ + #define USBHSCORE_GPWRDN_BSESSVLD_NOTVALID (0x0UL) /*!< B_Valid is 0 */ + #define USBHSCORE_GPWRDN_BSESSVLD_VALID (0x1UL) /*!< B_Valid is 1 */ + +/* MULTVALIDBC @Bits 24..28 : MultValIdBC */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_Pos (24UL) /*!< Position of MULTVALIDBC field. */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_Msk (0x1FUL << USBHSCORE_GPWRDN_MULTVALIDBC_Pos) /*!< Bit mask of MULTVALIDBC field. */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_Min (0x00UL) /*!< Min enumerator value of MULTVALIDBC field. */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_Max (0x1FUL) /*!< Max enumerator value of MULTVALIDBC field. */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID0 (0x00UL) /*!< OTG device as B-device */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RIDC (0x01UL) /*!< OTG device as B-device, can connect */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RIDB (0x02UL) /*!< OTG device as B-device, cannot connect */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RIDA (0x04UL) /*!< OTG device as A-device */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RIDGND (0x08UL) /*!< ID_OTG pin is grounded */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RIDARIDGND (0x0CUL) /*!< OTG device as A-device, RID_A=1 and RID_GND=1 */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RIDFLOAT (0x10UL) /*!< ID pull down when ID_OTG is floating */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RIDCRIDFLOAT (0x11UL) /*!< OTG device as B-device, can connect, RID_C=1 and RID_FLOAT=1 */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RIDBRIDFLOAT (0x12UL) /*!< OTG device as B-device, cannot connect, RID_B=1 and + RID_FLOAT=1*/ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID1 (0x1FUL) /*!< OTG device as A-device */ + + +/* USBHSCORE_GDFIFOCFG: Global DFIFO Configuration Register */ + #define USBHSCORE_GDFIFOCFG_ResetValue (0x0BE00C00UL) /*!< Reset value of GDFIFOCFG register. */ + +/* GDFIFOCFG @Bits 0..15 : GDFIFOCfg */ + #define USBHSCORE_GDFIFOCFG_GDFIFOCFG_Pos (0UL) /*!< Position of GDFIFOCFG field. */ + #define USBHSCORE_GDFIFOCFG_GDFIFOCFG_Msk (0xFFFFUL << USBHSCORE_GDFIFOCFG_GDFIFOCFG_Pos) /*!< Bit mask of GDFIFOCFG field. */ + +/* EPINFOBASEADDR @Bits 16..31 : This field provides the start address of the EP info controller. */ + #define USBHSCORE_GDFIFOCFG_EPINFOBASEADDR_Pos (16UL) /*!< Position of EPINFOBASEADDR field. */ + #define USBHSCORE_GDFIFOCFG_EPINFOBASEADDR_Msk (0xFFFFUL << USBHSCORE_GDFIFOCFG_EPINFOBASEADDR_Pos) /*!< Bit mask of + EPINFOBASEADDR field.*/ + + +/* USBHSCORE_GINTMSK2: Interrupt Mask Register 2 */ + #define USBHSCORE_GINTMSK2_ResetValue (0x00000000UL) /*!< Reset value of GINTMSK2 register. */ + +/* GINTMSK2 @Bits 0..31 : (unspecified) */ + #define USBHSCORE_GINTMSK2_GINTMSK2_Pos (0UL) /*!< Position of GINTMSK2 field. */ + #define USBHSCORE_GINTMSK2_GINTMSK2_Msk (0xFFFFFFFFUL << USBHSCORE_GINTMSK2_GINTMSK2_Pos) /*!< Bit mask of GINTMSK2 field. */ + + +/* USBHSCORE_GINTSTS2: Interrupt Register 2 */ + #define USBHSCORE_GINTSTS2_ResetValue (0x00000000UL) /*!< Reset value of GINTSTS2 register. */ + +/* GINTSTS2 @Bits 0..31 : (unspecified) */ + #define USBHSCORE_GINTSTS2_GINTSTS2_Pos (0UL) /*!< Position of GINTSTS2 field. */ + #define USBHSCORE_GINTSTS2_GINTSTS2_Msk (0xFFFFFFFFUL << USBHSCORE_GINTSTS2_GINTSTS2_Pos) /*!< Bit mask of GINTSTS2 field. */ + + +/* USBHSCORE_HPTXFSIZ: Host Periodic Transmit FIFO Size Register */ + #define USBHSCORE_HPTXFSIZ_ResetValue (0x0C001800UL) /*!< Reset value of HPTXFSIZ register. */ + +/* PTXFSTADDR @Bits 0..12 : Host Periodic TxFIFO Start Address (PTxFStAddr) */ + #define USBHSCORE_HPTXFSIZ_PTXFSTADDR_Pos (0UL) /*!< Position of PTXFSTADDR field. */ + #define USBHSCORE_HPTXFSIZ_PTXFSTADDR_Msk (0x1FFFUL << USBHSCORE_HPTXFSIZ_PTXFSTADDR_Pos) /*!< Bit mask of PTXFSTADDR field. */ + +/* PTXFSIZE @Bits 16..27 : Host Periodic TxFIFO Depth (PTxFSize) */ + #define USBHSCORE_HPTXFSIZ_PTXFSIZE_Pos (16UL) /*!< Position of PTXFSIZE field. */ + #define USBHSCORE_HPTXFSIZ_PTXFSIZE_Msk (0xFFFUL << USBHSCORE_HPTXFSIZ_PTXFSIZE_Pos) /*!< Bit mask of PTXFSIZE field. */ + + +/* USBHSCORE_DIEPTXF: Device IN Endpoint Transmit FIFO 1 Size Register */ + #define USBHSCORE_DIEPTXF_MaxCount (15UL) /*!< Max size of DIEPTXF[16] array. */ + #define USBHSCORE_DIEPTXF_MaxIndex (15UL) /*!< Max index of DIEPTXF[16] array. */ + #define USBHSCORE_DIEPTXF_MinIndex (1UL) /*!< Min index of DIEPTXF[16] array. */ + #define USBHSCORE_DIEPTXF_ResetValue (0x0C001800UL) /*!< Reset value of DIEPTXF[16] register. */ + +/* INEPNTXFSTADDR @Bits 0..12 : IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) */ + #define USBHSCORE_DIEPTXF_INEPNTXFSTADDR_Pos (0UL) /*!< Position of INEPNTXFSTADDR field. */ + #define USBHSCORE_DIEPTXF_INEPNTXFSTADDR_Msk (0x1FFFUL << USBHSCORE_DIEPTXF_INEPNTXFSTADDR_Pos) /*!< Bit mask of + INEPNTXFSTADDR field.*/ + +/* INEPNTXFDEP @Bits 16..27 : IN Endpoint TxFIFO Depth (INEPnTxFDep) */ + #define USBHSCORE_DIEPTXF_INEPNTXFDEP_Pos (16UL) /*!< Position of INEPNTXFDEP field. */ + #define USBHSCORE_DIEPTXF_INEPNTXFDEP_Msk (0xFFFUL << USBHSCORE_DIEPTXF_INEPNTXFDEP_Pos) /*!< Bit mask of INEPNTXFDEP field. */ + + +/* USBHSCORE_HCFG: Host Configuration Register */ + #define USBHSCORE_HCFG_ResetValue (0x00000200UL) /*!< Reset value of HCFG register. */ + +/* FSLSPCLKSEL @Bits 0..1 : FS/LS PHY Clock Select (FSLSPclkSel) */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_Pos (0UL) /*!< Position of FSLSPCLKSEL field. */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_Msk (0x3UL << USBHSCORE_HCFG_FSLSPCLKSEL_Pos) /*!< Bit mask of FSLSPCLKSEL field. */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_Min (0x0UL) /*!< Min enumerator value of FSLSPCLKSEL field. */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_Max (0x2UL) /*!< Max enumerator value of FSLSPCLKSEL field. */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_CLK3060 (0x0UL) /*!< PHY clock is running at 30/60 MHz */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_CLK48 (0x1UL) /*!< PHY clock is running at 48 MHz */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_CLK6 (0x2UL) /*!< PHY clock is running at 6 MHz */ + +/* FSLSSUPP @Bit 2 : FS- and LS-Only Support (FSLSSupp) */ + #define USBHSCORE_HCFG_FSLSSUPP_Pos (2UL) /*!< Position of FSLSSUPP field. */ + #define USBHSCORE_HCFG_FSLSSUPP_Msk (0x1UL << USBHSCORE_HCFG_FSLSSUPP_Pos) /*!< Bit mask of FSLSSUPP field. */ + #define USBHSCORE_HCFG_FSLSSUPP_Min (0x0UL) /*!< Min enumerator value of FSLSSUPP field. */ + #define USBHSCORE_HCFG_FSLSSUPP_Max (0x1UL) /*!< Max enumerator value of FSLSSUPP field. */ + #define USBHSCORE_HCFG_FSLSSUPP_HSFSLS (0x0UL) /*!< HS/FS/LS, based on the maximum speed supported by the connected + device*/ + #define USBHSCORE_HCFG_FSLSSUPP_FSLS (0x1UL) /*!< FS/LS-only, even if the connected device can support HS */ + +/* ENA32KHZS @Bit 7 : Enable 32 KHz Suspend mode (Ena32KHzS) */ + #define USBHSCORE_HCFG_ENA32KHZS_Pos (7UL) /*!< Position of ENA32KHZS field. */ + #define USBHSCORE_HCFG_ENA32KHZS_Msk (0x1UL << USBHSCORE_HCFG_ENA32KHZS_Pos) /*!< Bit mask of ENA32KHZS field. */ + #define USBHSCORE_HCFG_ENA32KHZS_Min (0x0UL) /*!< Min enumerator value of ENA32KHZS field. */ + #define USBHSCORE_HCFG_ENA32KHZS_Max (0x1UL) /*!< Max enumerator value of ENA32KHZS field. */ + #define USBHSCORE_HCFG_ENA32KHZS_DISABLED (0x0UL) /*!< 32 KHz Suspend mode disabled */ + #define USBHSCORE_HCFG_ENA32KHZS_ENABLED (0x1UL) /*!< 32 KHz Suspend mode enabled */ + +/* RESVALID @Bits 8..15 : Resume Validation Period (ResValid) */ + #define USBHSCORE_HCFG_RESVALID_Pos (8UL) /*!< Position of RESVALID field. */ + #define USBHSCORE_HCFG_RESVALID_Msk (0xFFUL << USBHSCORE_HCFG_RESVALID_Pos) /*!< Bit mask of RESVALID field. */ + +/* MODECHTIMEN @Bit 31 : Mode Change Ready Timer Enable (ModeChTimEn) */ + #define USBHSCORE_HCFG_MODECHTIMEN_Pos (31UL) /*!< Position of MODECHTIMEN field. */ + #define USBHSCORE_HCFG_MODECHTIMEN_Msk (0x1UL << USBHSCORE_HCFG_MODECHTIMEN_Pos) /*!< Bit mask of MODECHTIMEN field. */ + #define USBHSCORE_HCFG_MODECHTIMEN_Min (0x0UL) /*!< Min enumerator value of MODECHTIMEN field. */ + #define USBHSCORE_HCFG_MODECHTIMEN_Max (0x1UL) /*!< Max enumerator value of MODECHTIMEN field. */ + #define USBHSCORE_HCFG_MODECHTIMEN_ENABLED (0x0UL) /*!< The Host core waits for either 200 PHY clock cycles or a linestate of + SE0 at the end of resume to change the opmode from 0x2 to 0x0*/ + #define USBHSCORE_HCFG_MODECHTIMEN_DISABLED (0x1UL) /*!< The Host core waits only for a linestate of SE0 at the end of resume + to change the opmode from 0x2 to 0x0*/ + + +/* USBHSCORE_HFIR: Host Frame Interval Register */ + #define USBHSCORE_HFIR_ResetValue (0x0000EA60UL) /*!< Reset value of HFIR register. */ + +/* FRINT @Bits 0..15 : Frame Interval (FrInt) */ + #define USBHSCORE_HFIR_FRINT_Pos (0UL) /*!< Position of FRINT field. */ + #define USBHSCORE_HFIR_FRINT_Msk (0xFFFFUL << USBHSCORE_HFIR_FRINT_Pos) /*!< Bit mask of FRINT field. */ + +/* HFIRRLDCTRL @Bit 16 : Reload Control (HFIRRldCtrl) */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_Pos (16UL) /*!< Position of HFIRRLDCTRL field. */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_Msk (0x1UL << USBHSCORE_HFIR_HFIRRLDCTRL_Pos) /*!< Bit mask of HFIRRLDCTRL field. */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_Min (0x0UL) /*!< Min enumerator value of HFIRRLDCTRL field. */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_Max (0x1UL) /*!< Max enumerator value of HFIRRLDCTRL field. */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_DISABLED (0x0UL) /*!< The HFIR cannot be reloaded dynamically */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_ENABLED (0x1UL) /*!< The HFIR can be dynamically reloaded during runtime */ + + +/* USBHSCORE_HFNUM: Host Frame Number/Frame Time Remaining Register */ + #define USBHSCORE_HFNUM_ResetValue (0x00003FFFUL) /*!< Reset value of HFNUM register. */ + +/* FRNUM @Bits 0..15 : Frame Number (FrNum) */ + #define USBHSCORE_HFNUM_FRNUM_Pos (0UL) /*!< Position of FRNUM field. */ + #define USBHSCORE_HFNUM_FRNUM_Msk (0xFFFFUL << USBHSCORE_HFNUM_FRNUM_Pos) /*!< Bit mask of FRNUM field. */ + #define USBHSCORE_HFNUM_FRNUM_Min (0x0000UL) /*!< Min enumerator value of FRNUM field. */ + #define USBHSCORE_HFNUM_FRNUM_Max (0x0001UL) /*!< Max enumerator value of FRNUM field. */ + #define USBHSCORE_HFNUM_FRNUM_INACTIVE (0x0000UL) /*!< No SOF is transmitted */ + #define USBHSCORE_HFNUM_FRNUM_ACTIVE (0x0001UL) /*!< SOF is transmitted */ + +/* FRREM @Bits 16..31 : Frame Time Remaining (FrRem) */ + #define USBHSCORE_HFNUM_FRREM_Pos (16UL) /*!< Position of FRREM field. */ + #define USBHSCORE_HFNUM_FRREM_Msk (0xFFFFUL << USBHSCORE_HFNUM_FRREM_Pos) /*!< Bit mask of FRREM field. */ + + +/* USBHSCORE_HPTXSTS: Host Periodic Transmit FIFO/Queue Status Register */ + #define USBHSCORE_HPTXSTS_ResetValue (0x00080C00UL) /*!< Reset value of HPTXSTS register. */ + +/* PTXFSPCAVAIL @Bits 0..15 : Periodic Transmit Data FIFO Space Available (PTxFSpcAvail) */ + #define USBHSCORE_HPTXSTS_PTXFSPCAVAIL_Pos (0UL) /*!< Position of PTXFSPCAVAIL field. */ + #define USBHSCORE_HPTXSTS_PTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_HPTXSTS_PTXFSPCAVAIL_Pos) /*!< Bit mask of PTXFSPCAVAIL + field.*/ + +/* PTXQSPCAVAIL @Bits 16..22 : Periodic Transmit Request Queue Space Available (PTxQSpcAvail) */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_Pos (16UL) /*!< Position of PTXQSPCAVAIL field. */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_Msk (0x7FUL << USBHSCORE_HPTXSTS_PTXQSPCAVAIL_Pos) /*!< Bit mask of PTXQSPCAVAIL + field.*/ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_Min (0x00UL) /*!< Min enumerator value of PTXQSPCAVAIL field. */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_Max (0x0FUL) /*!< Max enumerator value of PTXQSPCAVAIL field. */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FULL (0x00UL) /*!< Periodic Transmit Request Queue is full */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE1 (0x01UL) /*!< 1 location available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE2 (0x02UL) /*!< 2 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE3 (0x03UL) /*!< 3 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE4 (0x04UL) /*!< 4 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE5 (0x05UL) /*!< 5 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE6 (0x06UL) /*!< 6 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE7 (0x07UL) /*!< 7 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE8 (0x08UL) /*!< 8 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE9 (0x09UL) /*!< 9 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE10 (0x0AUL) /*!< 10 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE11 (0x0BUL) /*!< 11 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE12 (0x0CUL) /*!< 12 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE13 (0x0DUL) /*!< 13 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE14 (0x0EUL) /*!< 14 locations available */ + #define USBHSCORE_HPTXSTS_PTXQSPCAVAIL_FREE15 (0x0FUL) /*!< 15 locations available */ + +/* PTXQTOP @Bits 23..31 : Top of the Periodic Transmit Request Queue (PTxQTop) */ + #define USBHSCORE_HPTXSTS_PTXQTOP_Pos (23UL) /*!< Position of PTXQTOP field. */ + #define USBHSCORE_HPTXSTS_PTXQTOP_Msk (0x1FFUL << USBHSCORE_HPTXSTS_PTXQTOP_Pos) /*!< Bit mask of PTXQTOP field. */ + + +/* USBHSCORE_HAINT: Host All Channels Interrupt Register */ + #define USBHSCORE_HAINT_ResetValue (0x00000000UL) /*!< Reset value of HAINT register. */ + +/* HAINT @Bits 0..15 : (unspecified) */ + #define USBHSCORE_HAINT_HAINT_Pos (0UL) /*!< Position of HAINT field. */ + #define USBHSCORE_HAINT_HAINT_Msk (0xFFFFUL << USBHSCORE_HAINT_HAINT_Pos) /*!< Bit mask of HAINT field. */ + #define USBHSCORE_HAINT_HAINT_Min (0x0000UL) /*!< Min enumerator value of HAINT field. */ + #define USBHSCORE_HAINT_HAINT_Max (0x0001UL) /*!< Max enumerator value of HAINT field. */ + #define USBHSCORE_HAINT_HAINT_INACTIVE (0x0000UL) /*!< Not active */ + #define USBHSCORE_HAINT_HAINT_ACTIVE (0x0001UL) /*!< Host Channel Interrupt */ + + +/* USBHSCORE_HAINTMSK: Host All Channels Interrupt Mask Register */ + #define USBHSCORE_HAINTMSK_ResetValue (0x00000000UL) /*!< Reset value of HAINTMSK register. */ + +/* HAINTMSK @Bits 0..15 : Channel Interrupt Mask (HAINTMsk) */ + #define USBHSCORE_HAINTMSK_HAINTMSK_Pos (0UL) /*!< Position of HAINTMSK field. */ + #define USBHSCORE_HAINTMSK_HAINTMSK_Msk (0xFFFFUL << USBHSCORE_HAINTMSK_HAINTMSK_Pos) /*!< Bit mask of HAINTMSK field. */ + #define USBHSCORE_HAINTMSK_HAINTMSK_Min (0x0000UL) /*!< Min enumerator value of HAINTMSK field. */ + #define USBHSCORE_HAINTMSK_HAINTMSK_Max (0x0001UL) /*!< Max enumerator value of HAINTMSK field. */ + #define USBHSCORE_HAINTMSK_HAINTMSK_MASK (0x0000UL) /*!< Mask Channel interrupt */ + #define USBHSCORE_HAINTMSK_HAINTMSK_UNMASK (0x0001UL) /*!< UnMask Channel interrupt */ + + +/* USBHSCORE_HPRT: Host Port Control and Status Register */ + #define USBHSCORE_HPRT_ResetValue (0x00000000UL) /*!< Reset value of HPRT register. */ + +/* PRTCONNSTS @Bit 0 : Port Connect Status (PrtConnSts) */ + #define USBHSCORE_HPRT_PRTCONNSTS_Pos (0UL) /*!< Position of PRTCONNSTS field. */ + #define USBHSCORE_HPRT_PRTCONNSTS_Msk (0x1UL << USBHSCORE_HPRT_PRTCONNSTS_Pos) /*!< Bit mask of PRTCONNSTS field. */ + #define USBHSCORE_HPRT_PRTCONNSTS_Min (0x0UL) /*!< Min enumerator value of PRTCONNSTS field. */ + #define USBHSCORE_HPRT_PRTCONNSTS_Max (0x1UL) /*!< Max enumerator value of PRTCONNSTS field. */ + #define USBHSCORE_HPRT_PRTCONNSTS_NOTATTACHED (0x0UL) /*!< No device is attached to the port */ + #define USBHSCORE_HPRT_PRTCONNSTS_ATTACHED (0x1UL) /*!< A device is attached to the port */ + +/* PRTCONNDET @Bit 1 : Port Connect Detected (PrtConnDet) */ + #define USBHSCORE_HPRT_PRTCONNDET_Pos (1UL) /*!< Position of PRTCONNDET field. */ + #define USBHSCORE_HPRT_PRTCONNDET_Msk (0x1UL << USBHSCORE_HPRT_PRTCONNDET_Pos) /*!< Bit mask of PRTCONNDET field. */ + #define USBHSCORE_HPRT_PRTCONNDET_Min (0x0UL) /*!< Min enumerator value of PRTCONNDET field. */ + #define USBHSCORE_HPRT_PRTCONNDET_Max (0x1UL) /*!< Max enumerator value of PRTCONNDET field. */ + #define USBHSCORE_HPRT_PRTCONNDET_INACTIVE (0x0UL) /*!< No device connection detected */ + #define USBHSCORE_HPRT_PRTCONNDET_ACTIVE (0x1UL) /*!< Device connection detected */ + +/* PRTENA @Bit 2 : Port Enable (PrtEna) */ + #define USBHSCORE_HPRT_PRTENA_Pos (2UL) /*!< Position of PRTENA field. */ + #define USBHSCORE_HPRT_PRTENA_Msk (0x1UL << USBHSCORE_HPRT_PRTENA_Pos) /*!< Bit mask of PRTENA field. */ + #define USBHSCORE_HPRT_PRTENA_Min (0x0UL) /*!< Min enumerator value of PRTENA field. */ + #define USBHSCORE_HPRT_PRTENA_Max (0x1UL) /*!< Max enumerator value of PRTENA field. */ + #define USBHSCORE_HPRT_PRTENA_DISABLED (0x0UL) /*!< Port disabled */ + #define USBHSCORE_HPRT_PRTENA_ENABLED (0x1UL) /*!< Port enabled */ + +/* PRTENCHNG @Bit 3 : Port Enable/Disable Change (PrtEnChng) */ + #define USBHSCORE_HPRT_PRTENCHNG_Pos (3UL) /*!< Position of PRTENCHNG field. */ + #define USBHSCORE_HPRT_PRTENCHNG_Msk (0x1UL << USBHSCORE_HPRT_PRTENCHNG_Pos) /*!< Bit mask of PRTENCHNG field. */ + #define USBHSCORE_HPRT_PRTENCHNG_Min (0x0UL) /*!< Min enumerator value of PRTENCHNG field. */ + #define USBHSCORE_HPRT_PRTENCHNG_Max (0x1UL) /*!< Max enumerator value of PRTENCHNG field. */ + #define USBHSCORE_HPRT_PRTENCHNG_INACTIVE (0x0UL) /*!< Port Enable bit 2 has not changed */ + #define USBHSCORE_HPRT_PRTENCHNG_ACTIVE (0x1UL) /*!< Port Enable bit 2 changed */ + +/* PRTOVRCURRACT @Bit 4 : Port Overcurrent Active (PrtOvrCurrAct) */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_Pos (4UL) /*!< Position of PRTOVRCURRACT field. */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_Msk (0x1UL << USBHSCORE_HPRT_PRTOVRCURRACT_Pos) /*!< Bit mask of PRTOVRCURRACT field. */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_Min (0x0UL) /*!< Min enumerator value of PRTOVRCURRACT field. */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_Max (0x1UL) /*!< Max enumerator value of PRTOVRCURRACT field. */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_INACTIVE (0x0UL) /*!< No overcurrent condition */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_ACTIVE (0x1UL) /*!< Overcurrent condition */ + +/* PRTOVRCURRCHNG @Bit 5 : Port Overcurrent Change (PrtOvrCurrChng) */ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Pos (5UL) /*!< Position of PRTOVRCURRCHNG field. */ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Msk (0x1UL << USBHSCORE_HPRT_PRTOVRCURRCHNG_Pos) /*!< Bit mask of PRTOVRCURRCHNG field.*/ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Min (0x0UL) /*!< Min enumerator value of PRTOVRCURRCHNG field. */ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Max (0x1UL) /*!< Max enumerator value of PRTOVRCURRCHNG field. */ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_INACTIVE (0x0UL) /*!< Status of port overcurrent status is not changed */ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_ACTIVE (0x1UL) /*!< Status of port overcurrent changed */ + +/* PRTRES @Bit 6 : Port Resume (PrtRes) */ + #define USBHSCORE_HPRT_PRTRES_Pos (6UL) /*!< Position of PRTRES field. */ + #define USBHSCORE_HPRT_PRTRES_Msk (0x1UL << USBHSCORE_HPRT_PRTRES_Pos) /*!< Bit mask of PRTRES field. */ + #define USBHSCORE_HPRT_PRTRES_Min (0x0UL) /*!< Min enumerator value of PRTRES field. */ + #define USBHSCORE_HPRT_PRTRES_Max (0x1UL) /*!< Max enumerator value of PRTRES field. */ + #define USBHSCORE_HPRT_PRTRES_NORESUME (0x0UL) /*!< No resume driven */ + #define USBHSCORE_HPRT_PRTRES_RESUME (0x1UL) /*!< Resume driven */ + +/* PRTSUSP @Bit 7 : Port Suspend (PrtSusp) */ + #define USBHSCORE_HPRT_PRTSUSP_Pos (7UL) /*!< Position of PRTSUSP field. */ + #define USBHSCORE_HPRT_PRTSUSP_Msk (0x1UL << USBHSCORE_HPRT_PRTSUSP_Pos) /*!< Bit mask of PRTSUSP field. */ + #define USBHSCORE_HPRT_PRTSUSP_Min (0x0UL) /*!< Min enumerator value of PRTSUSP field. */ + #define USBHSCORE_HPRT_PRTSUSP_Max (0x1UL) /*!< Max enumerator value of PRTSUSP field. */ + #define USBHSCORE_HPRT_PRTSUSP_INACTIVE (0x0UL) /*!< Port not in Suspend mode */ + #define USBHSCORE_HPRT_PRTSUSP_ACTIVE (0x1UL) /*!< Port in Suspend mode */ + +/* PRTRST @Bit 8 : Port Reset (PrtRst) */ + #define USBHSCORE_HPRT_PRTRST_Pos (8UL) /*!< Position of PRTRST field. */ + #define USBHSCORE_HPRT_PRTRST_Msk (0x1UL << USBHSCORE_HPRT_PRTRST_Pos) /*!< Bit mask of PRTRST field. */ + #define USBHSCORE_HPRT_PRTRST_Min (0x0UL) /*!< Min enumerator value of PRTRST field. */ + #define USBHSCORE_HPRT_PRTRST_Max (0x1UL) /*!< Max enumerator value of PRTRST field. */ + #define USBHSCORE_HPRT_PRTRST_DISABLED (0x0UL) /*!< Port not in reset */ + #define USBHSCORE_HPRT_PRTRST_ENABLED (0x1UL) /*!< Port in reset */ + +/* PRTLNSTS @Bits 10..11 : Port Line Status (PrtLnSts) */ + #define USBHSCORE_HPRT_PRTLNSTS_Pos (10UL) /*!< Position of PRTLNSTS field. */ + #define USBHSCORE_HPRT_PRTLNSTS_Msk (0x3UL << USBHSCORE_HPRT_PRTLNSTS_Pos) /*!< Bit mask of PRTLNSTS field. */ + #define USBHSCORE_HPRT_PRTLNSTS_Min (0x1UL) /*!< Min enumerator value of PRTLNSTS field. */ + #define USBHSCORE_HPRT_PRTLNSTS_Max (0x2UL) /*!< Max enumerator value of PRTLNSTS field. */ + #define USBHSCORE_HPRT_PRTLNSTS_PLUSD (0x1UL) /*!< Logic level of D+ */ + #define USBHSCORE_HPRT_PRTLNSTS_MINUSD (0x2UL) /*!< Logic level of D- */ + +/* PRTPWR @Bit 12 : Port Power (PrtPwr) */ + #define USBHSCORE_HPRT_PRTPWR_Pos (12UL) /*!< Position of PRTPWR field. */ + #define USBHSCORE_HPRT_PRTPWR_Msk (0x1UL << USBHSCORE_HPRT_PRTPWR_Pos) /*!< Bit mask of PRTPWR field. */ + #define USBHSCORE_HPRT_PRTPWR_Min (0x0UL) /*!< Min enumerator value of PRTPWR field. */ + #define USBHSCORE_HPRT_PRTPWR_Max (0x1UL) /*!< Max enumerator value of PRTPWR field. */ + #define USBHSCORE_HPRT_PRTPWR_OFF (0x0UL) /*!< Power off */ + #define USBHSCORE_HPRT_PRTPWR_ON (0x1UL) /*!< Power on */ + +/* PRTTSTCTL @Bits 13..16 : Port Test Control (PrtTstCtl) */ + #define USBHSCORE_HPRT_PRTTSTCTL_Pos (13UL) /*!< Position of PRTTSTCTL field. */ + #define USBHSCORE_HPRT_PRTTSTCTL_Msk (0xFUL << USBHSCORE_HPRT_PRTTSTCTL_Pos) /*!< Bit mask of PRTTSTCTL field. */ + #define USBHSCORE_HPRT_PRTTSTCTL_Min (0x0UL) /*!< Min enumerator value of PRTTSTCTL field. */ + #define USBHSCORE_HPRT_PRTTSTCTL_Max (0x5UL) /*!< Max enumerator value of PRTTSTCTL field. */ + #define USBHSCORE_HPRT_PRTTSTCTL_DISABLED (0x0UL) /*!< Test mode disabled */ + #define USBHSCORE_HPRT_PRTTSTCTL_TESTJ (0x1UL) /*!< Test_J mode */ + #define USBHSCORE_HPRT_PRTTSTCTL_TESTK (0x2UL) /*!< Test_K mode */ + #define USBHSCORE_HPRT_PRTTSTCTL_TESTSN (0x3UL) /*!< Test_SE0_NAK mode */ + #define USBHSCORE_HPRT_PRTTSTCTL_TESTPM (0x4UL) /*!< Test_Packet mode */ + #define USBHSCORE_HPRT_PRTTSTCTL_TESTFENB (0x5UL) /*!< Test_force_Enable */ + +/* PRTSPD @Bits 17..18 : Port Speed (PrtSpd) */ + #define USBHSCORE_HPRT_PRTSPD_Pos (17UL) /*!< Position of PRTSPD field. */ + #define USBHSCORE_HPRT_PRTSPD_Msk (0x3UL << USBHSCORE_HPRT_PRTSPD_Pos) /*!< Bit mask of PRTSPD field. */ + #define USBHSCORE_HPRT_PRTSPD_Min (0x0UL) /*!< Min enumerator value of PRTSPD field. */ + #define USBHSCORE_HPRT_PRTSPD_Max (0x2UL) /*!< Max enumerator value of PRTSPD field. */ + #define USBHSCORE_HPRT_PRTSPD_HIGHSPD (0x0UL) /*!< High speed */ + #define USBHSCORE_HPRT_PRTSPD_FULLSPD (0x1UL) /*!< Full speed */ + #define USBHSCORE_HPRT_PRTSPD_LOWSPD (0x2UL) /*!< Low speed */ + + +/* USBHSCORE_DCFG: Device Configuration Register */ + #define USBHSCORE_DCFG_ResetValue (0x08020000UL) /*!< Reset value of DCFG register. */ + +/* DEVSPD @Bits 0..1 : Device Speed (DevSpd) */ + #define USBHSCORE_DCFG_DEVSPD_Pos (0UL) /*!< Position of DEVSPD field. */ + #define USBHSCORE_DCFG_DEVSPD_Msk (0x3UL << USBHSCORE_DCFG_DEVSPD_Pos) /*!< Bit mask of DEVSPD field. */ + #define USBHSCORE_DCFG_DEVSPD_Min (0x0UL) /*!< Min enumerator value of DEVSPD field. */ + #define USBHSCORE_DCFG_DEVSPD_Max (0x3UL) /*!< Max enumerator value of DEVSPD field. */ + #define USBHSCORE_DCFG_DEVSPD_USBHS20 (0x0UL) /*!< High speed USB 2.0 PHY clock is 30 MHz or 60 MHz */ + #define USBHSCORE_DCFG_DEVSPD_USBFS20 (0x1UL) /*!< Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz */ + #define USBHSCORE_DCFG_DEVSPD_USBLS116 (0x2UL) /*!< Low speed USB 1.1 transceiver clock is 6 MHz */ + #define USBHSCORE_DCFG_DEVSPD_USBFS1148 (0x3UL) /*!< Full speed USB 1.1 transceiver clock is 48 MHz */ + +/* NZSTSOUTHSHK @Bit 2 : Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) */ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_Pos (2UL) /*!< Position of NZSTSOUTHSHK field. */ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_Msk (0x1UL << USBHSCORE_DCFG_NZSTSOUTHSHK_Pos) /*!< Bit mask of NZSTSOUTHSHK field. */ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_Min (0x0UL) /*!< Min enumerator value of NZSTSOUTHSHK field. */ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_Max (0x1UL) /*!< Max enumerator value of NZSTSOUTHSHK field. */ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_SENDOUT (0x0UL) /*!< Send the received OUT packet to the application (zero-length or + non-zero length) and send a handshake based on NAK and STALL bits for + the endpoint in the Devce Endpoint Control Register*/ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_SENDSTALL (0x1UL) /*!< Send a STALL handshake on a nonzero-length status OUT transaction + and do not send the received OUT packet to the application*/ + +/* ENA32KHZSUSP @Bit 3 : Enable 32 KHz Suspend mode (Ena32KHzSusp) */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_Pos (3UL) /*!< Position of ENA32KHZSUSP field. */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_Msk (0x1UL << USBHSCORE_DCFG_ENA32KHZSUSP_Pos) /*!< Bit mask of ENA32KHZSUSP field. */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_Min (0x0UL) /*!< Min enumerator value of ENA32KHZSUSP field. */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_Max (0x1UL) /*!< Max enumerator value of ENA32KHZSUSP field. */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_DISABLED (0x0UL) /*!< USB 1.1 Full-Speed Serial Transceiver not selected */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_ENABLED (0x1UL) /*!< USB 1.1 Full-Speed Serial Transceiver Interface selected */ + +/* DEVADDR @Bits 4..10 : Device Address (DevAddr) */ + #define USBHSCORE_DCFG_DEVADDR_Pos (4UL) /*!< Position of DEVADDR field. */ + #define USBHSCORE_DCFG_DEVADDR_Msk (0x7FUL << USBHSCORE_DCFG_DEVADDR_Pos) /*!< Bit mask of DEVADDR field. */ + +/* PERFRINT @Bits 11..12 : Periodic Frame Interval (PerFrInt) */ + #define USBHSCORE_DCFG_PERFRINT_Pos (11UL) /*!< Position of PERFRINT field. */ + #define USBHSCORE_DCFG_PERFRINT_Msk (0x3UL << USBHSCORE_DCFG_PERFRINT_Pos) /*!< Bit mask of PERFRINT field. */ + #define USBHSCORE_DCFG_PERFRINT_Min (0x0UL) /*!< Min enumerator value of PERFRINT field. */ + #define USBHSCORE_DCFG_PERFRINT_Max (0x3UL) /*!< Max enumerator value of PERFRINT field. */ + #define USBHSCORE_DCFG_PERFRINT_EOPF80 (0x0UL) /*!< 80 percent of the (micro)Frame interval */ + #define USBHSCORE_DCFG_PERFRINT_EOPF85 (0x1UL) /*!< 85 percent of the (micro)Frame interval */ + #define USBHSCORE_DCFG_PERFRINT_EOPF90 (0x2UL) /*!< 90 percent of the (micro)Frame interval */ + #define USBHSCORE_DCFG_PERFRINT_EOPF95 (0x3UL) /*!< 95 percent of the (micro)Frame interval */ + +/* XCVRDLY @Bit 14 : XCVRDLY */ + #define USBHSCORE_DCFG_XCVRDLY_Pos (14UL) /*!< Position of XCVRDLY field. */ + #define USBHSCORE_DCFG_XCVRDLY_Msk (0x1UL << USBHSCORE_DCFG_XCVRDLY_Pos) /*!< Bit mask of XCVRDLY field. */ + #define USBHSCORE_DCFG_XCVRDLY_Min (0x0UL) /*!< Min enumerator value of XCVRDLY field. */ + #define USBHSCORE_DCFG_XCVRDLY_Max (0x1UL) /*!< Max enumerator value of XCVRDLY field. */ + #define USBHSCORE_DCFG_XCVRDLY_DISABLE (0x0UL) /*!< No delay between xcvr_sel and txvalid during Device chirp */ + #define USBHSCORE_DCFG_XCVRDLY_ENABLE (0x1UL) /*!< Enable delay between xcvr_sel and txvalid during Device chirp */ + +/* ERRATICINTMSK @Bit 15 : Erratic Error Interrupt Mask */ + #define USBHSCORE_DCFG_ERRATICINTMSK_Pos (15UL) /*!< Position of ERRATICINTMSK field. */ + #define USBHSCORE_DCFG_ERRATICINTMSK_Msk (0x1UL << USBHSCORE_DCFG_ERRATICINTMSK_Pos) /*!< Bit mask of ERRATICINTMSK field. */ + #define USBHSCORE_DCFG_ERRATICINTMSK_Min (0x0UL) /*!< Min enumerator value of ERRATICINTMSK field. */ + #define USBHSCORE_DCFG_ERRATICINTMSK_Max (0x1UL) /*!< Max enumerator value of ERRATICINTMSK field. */ + #define USBHSCORE_DCFG_ERRATICINTMSK_NOMASK (0x0UL) /*!< Early suspend interrupt is generated on erratic error */ + #define USBHSCORE_DCFG_ERRATICINTMSK_MASK (0x1UL) /*!< Mask early suspend interrupt on erratic error */ + +/* IPGISOCSUPT @Bit 17 : Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt) */ + #define USBHSCORE_DCFG_IPGISOCSUPT_Pos (17UL) /*!< Position of IPGISOCSUPT field. */ + #define USBHSCORE_DCFG_IPGISOCSUPT_Msk (0x1UL << USBHSCORE_DCFG_IPGISOCSUPT_Pos) /*!< Bit mask of IPGISOCSUPT field. */ + #define USBHSCORE_DCFG_IPGISOCSUPT_Min (0x0UL) /*!< Min enumerator value of IPGISOCSUPT field. */ + #define USBHSCORE_DCFG_IPGISOCSUPT_Max (0x1UL) /*!< Max enumerator value of IPGISOCSUPT field. */ + #define USBHSCORE_DCFG_IPGISOCSUPT_DISABLED (0x0UL) /*!< Worst-Case Inter-Packet Gap ISOC OUT Support is disabled */ + #define USBHSCORE_DCFG_IPGISOCSUPT_ENABLED (0x1UL) /*!< Worst-Case Inter-Packet Gap ISOC OUT Support is enabled */ + +/* PERSCHINTVL @Bits 24..25 : Periodic Scheduling Interval (PerSchIntvl) */ + #define USBHSCORE_DCFG_PERSCHINTVL_Pos (24UL) /*!< Position of PERSCHINTVL field. */ + #define USBHSCORE_DCFG_PERSCHINTVL_Msk (0x3UL << USBHSCORE_DCFG_PERSCHINTVL_Pos) /*!< Bit mask of PERSCHINTVL field. */ + #define USBHSCORE_DCFG_PERSCHINTVL_Min (0x0UL) /*!< Min enumerator value of PERSCHINTVL field. */ + #define USBHSCORE_DCFG_PERSCHINTVL_Max (0x2UL) /*!< Max enumerator value of PERSCHINTVL field. */ + #define USBHSCORE_DCFG_PERSCHINTVL_MF25 (0x0UL) /*!< 25 percent of (micro)Frame */ + #define USBHSCORE_DCFG_PERSCHINTVL_MF50 (0x1UL) /*!< 50 percent of (micro)Frame */ + #define USBHSCORE_DCFG_PERSCHINTVL_MF75 (0x2UL) /*!< 75 percent of (micro)Frame */ + +/* RESVALID @Bits 26..31 : Resume Validation Period (ResValid) */ + #define USBHSCORE_DCFG_RESVALID_Pos (26UL) /*!< Position of RESVALID field. */ + #define USBHSCORE_DCFG_RESVALID_Msk (0x3FUL << USBHSCORE_DCFG_RESVALID_Pos) /*!< Bit mask of RESVALID field. */ + + +/* USBHSCORE_DCTL: Device Control Register */ + #define USBHSCORE_DCTL_ResetValue (0x00000002UL) /*!< Reset value of DCTL register. */ + +/* RMTWKUPSIG @Bit 0 : Remote Wakeup Signaling (RmtWkUpSig) */ + #define USBHSCORE_DCTL_RMTWKUPSIG_Pos (0UL) /*!< Position of RMTWKUPSIG field. */ + #define USBHSCORE_DCTL_RMTWKUPSIG_Msk (0x1UL << USBHSCORE_DCTL_RMTWKUPSIG_Pos) /*!< Bit mask of RMTWKUPSIG field. */ + #define USBHSCORE_DCTL_RMTWKUPSIG_Min (0x0UL) /*!< Min enumerator value of RMTWKUPSIG field. */ + #define USBHSCORE_DCTL_RMTWKUPSIG_Max (0x1UL) /*!< Max enumerator value of RMTWKUPSIG field. */ + #define USBHSCORE_DCTL_RMTWKUPSIG_DISABLEDRMWKUP (0x0UL) /*!< Core does not send Remote Wakeup Signaling */ + #define USBHSCORE_DCTL_RMTWKUPSIG_ENABLERMWKUP (0x1UL) /*!< Core sends Remote Wakeup Signaling */ + +/* SFTDISCON @Bit 1 : Soft Disconnect (SftDiscon) */ + #define USBHSCORE_DCTL_SFTDISCON_Pos (1UL) /*!< Position of SFTDISCON field. */ + #define USBHSCORE_DCTL_SFTDISCON_Msk (0x1UL << USBHSCORE_DCTL_SFTDISCON_Pos) /*!< Bit mask of SFTDISCON field. */ + #define USBHSCORE_DCTL_SFTDISCON_Min (0x0UL) /*!< Min enumerator value of SFTDISCON field. */ + #define USBHSCORE_DCTL_SFTDISCON_Max (0x1UL) /*!< Max enumerator value of SFTDISCON field. */ + #define USBHSCORE_DCTL_SFTDISCON_NODISCONNECT (0x0UL) /*!< The core drives the phy_opmode_o signal on the UTMI+ to 2'b00, + which generates a device connect event to the USB host*/ + #define USBHSCORE_DCTL_SFTDISCON_DISCONNECT (0x1UL) /*!< The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which + generates a device disconnect event to the USB host*/ + +/* GNPINNAKSTS @Bit 2 : Global Non-periodic IN NAK Status (GNPINNakSts) */ + #define USBHSCORE_DCTL_GNPINNAKSTS_Pos (2UL) /*!< Position of GNPINNAKSTS field. */ + #define USBHSCORE_DCTL_GNPINNAKSTS_Msk (0x1UL << USBHSCORE_DCTL_GNPINNAKSTS_Pos) /*!< Bit mask of GNPINNAKSTS field. */ + #define USBHSCORE_DCTL_GNPINNAKSTS_Min (0x0UL) /*!< Min enumerator value of GNPINNAKSTS field. */ + #define USBHSCORE_DCTL_GNPINNAKSTS_Max (0x1UL) /*!< Max enumerator value of GNPINNAKSTS field. */ + #define USBHSCORE_DCTL_GNPINNAKSTS_INACTIVE (0x0UL) /*!< A handshake is sent out based on the data availability in the + transmit FIFO*/ + #define USBHSCORE_DCTL_GNPINNAKSTS_ACTIVE (0x1UL) /*!< A NAK handshake is sent out on all non-periodic IN endpoints, + irrespective of the data availability in the transmit FIFO.*/ + +/* GOUTNAKSTS @Bit 3 : Global OUT NAK Status (GOUTNakSts) */ + #define USBHSCORE_DCTL_GOUTNAKSTS_Pos (3UL) /*!< Position of GOUTNAKSTS field. */ + #define USBHSCORE_DCTL_GOUTNAKSTS_Msk (0x1UL << USBHSCORE_DCTL_GOUTNAKSTS_Pos) /*!< Bit mask of GOUTNAKSTS field. */ + #define USBHSCORE_DCTL_GOUTNAKSTS_Min (0x0UL) /*!< Min enumerator value of GOUTNAKSTS field. */ + #define USBHSCORE_DCTL_GOUTNAKSTS_Max (0x1UL) /*!< Max enumerator value of GOUTNAKSTS field. */ + #define USBHSCORE_DCTL_GOUTNAKSTS_INACTIVE (0x0UL) /*!< A handshake is sent based on the FIFO Status and the NAK and STALL bit + settings.*/ + #define USBHSCORE_DCTL_GOUTNAKSTS_ACTIVE (0x1UL) /*!< No data is written to the RxFIFO, irrespective of space availability. + Sends a NAK handshake on all packets, except on SETUP transactions. + All isochronous OUT packets are dropped.*/ + +/* TSTCTL @Bits 4..6 : Test Control (TstCtl) */ + #define USBHSCORE_DCTL_TSTCTL_Pos (4UL) /*!< Position of TSTCTL field. */ + #define USBHSCORE_DCTL_TSTCTL_Msk (0x7UL << USBHSCORE_DCTL_TSTCTL_Pos) /*!< Bit mask of TSTCTL field. */ + #define USBHSCORE_DCTL_TSTCTL_Min (0x0UL) /*!< Min enumerator value of TSTCTL field. */ + #define USBHSCORE_DCTL_TSTCTL_Max (0x5UL) /*!< Max enumerator value of TSTCTL field. */ + #define USBHSCORE_DCTL_TSTCTL_DISABLED (0x0UL) /*!< Test mode disabled */ + #define USBHSCORE_DCTL_TSTCTL_TESTJ (0x1UL) /*!< Test_J mode */ + #define USBHSCORE_DCTL_TSTCTL_TESTK (0x2UL) /*!< Test_K mode */ + #define USBHSCORE_DCTL_TSTCTL_TESTSN (0x3UL) /*!< Test_SE0_NAK mode */ + #define USBHSCORE_DCTL_TSTCTL_TESTPM (0x4UL) /*!< Test_Packet mode */ + #define USBHSCORE_DCTL_TSTCTL_TESTFE (0x5UL) /*!< Test_force_Enable */ + +/* SGNPINNAK @Bit 7 : Set Global Non-periodic IN NAK (SGNPInNak) */ + #define USBHSCORE_DCTL_SGNPINNAK_Pos (7UL) /*!< Position of SGNPINNAK field. */ + #define USBHSCORE_DCTL_SGNPINNAK_Msk (0x1UL << USBHSCORE_DCTL_SGNPINNAK_Pos) /*!< Bit mask of SGNPINNAK field. */ + #define USBHSCORE_DCTL_SGNPINNAK_Min (0x0UL) /*!< Min enumerator value of SGNPINNAK field. */ + #define USBHSCORE_DCTL_SGNPINNAK_Max (0x1UL) /*!< Max enumerator value of SGNPINNAK field. */ + #define USBHSCORE_DCTL_SGNPINNAK_DISABLE (0x0UL) /*!< Disable Global Non-periodic IN NAK */ + #define USBHSCORE_DCTL_SGNPINNAK_ENABLE (0x1UL) /*!< Set Global Non-periodic IN NAK */ + +/* CGNPINNAK @Bit 8 : Clear Global Non-periodic IN NAK (CGNPInNak) */ + #define USBHSCORE_DCTL_CGNPINNAK_Pos (8UL) /*!< Position of CGNPINNAK field. */ + #define USBHSCORE_DCTL_CGNPINNAK_Msk (0x1UL << USBHSCORE_DCTL_CGNPINNAK_Pos) /*!< Bit mask of CGNPINNAK field. */ + #define USBHSCORE_DCTL_CGNPINNAK_Min (0x0UL) /*!< Min enumerator value of CGNPINNAK field. */ + #define USBHSCORE_DCTL_CGNPINNAK_Max (0x1UL) /*!< Max enumerator value of CGNPINNAK field. */ + #define USBHSCORE_DCTL_CGNPINNAK_DISABLE (0x0UL) /*!< Disable Global Non-periodic IN NAK */ + #define USBHSCORE_DCTL_CGNPINNAK_ENABLE (0x1UL) /*!< Clear Global Non-periodic IN NAK */ + +/* SGOUTNAK @Bit 9 : Set Global OUT NAK (SGOUTNak) */ + #define USBHSCORE_DCTL_SGOUTNAK_Pos (9UL) /*!< Position of SGOUTNAK field. */ + #define USBHSCORE_DCTL_SGOUTNAK_Msk (0x1UL << USBHSCORE_DCTL_SGOUTNAK_Pos) /*!< Bit mask of SGOUTNAK field. */ + #define USBHSCORE_DCTL_SGOUTNAK_Min (0x0UL) /*!< Min enumerator value of SGOUTNAK field. */ + #define USBHSCORE_DCTL_SGOUTNAK_Max (0x1UL) /*!< Max enumerator value of SGOUTNAK field. */ + #define USBHSCORE_DCTL_SGOUTNAK_DISABLED (0x0UL) /*!< Disable Global OUT NAK */ + #define USBHSCORE_DCTL_SGOUTNAK_ENABLED (0x1UL) /*!< Set Global OUT NAK */ + +/* CGOUTNAK @Bit 10 : Clear Global OUT NAK (CGOUTNak) */ + #define USBHSCORE_DCTL_CGOUTNAK_Pos (10UL) /*!< Position of CGOUTNAK field. */ + #define USBHSCORE_DCTL_CGOUTNAK_Msk (0x1UL << USBHSCORE_DCTL_CGOUTNAK_Pos) /*!< Bit mask of CGOUTNAK field. */ + #define USBHSCORE_DCTL_CGOUTNAK_Min (0x0UL) /*!< Min enumerator value of CGOUTNAK field. */ + #define USBHSCORE_DCTL_CGOUTNAK_Max (0x1UL) /*!< Max enumerator value of CGOUTNAK field. */ + #define USBHSCORE_DCTL_CGOUTNAK_DISABLED (0x0UL) /*!< Disable Clear Global OUT NAK */ + #define USBHSCORE_DCTL_CGOUTNAK_ENABLED (0x1UL) /*!< Clear Global OUT NAK */ + +/* PWRONPRGDONE @Bit 11 : Power-On Programming Done (PWROnPrgDone) */ + #define USBHSCORE_DCTL_PWRONPRGDONE_Pos (11UL) /*!< Position of PWRONPRGDONE field. */ + #define USBHSCORE_DCTL_PWRONPRGDONE_Msk (0x1UL << USBHSCORE_DCTL_PWRONPRGDONE_Pos) /*!< Bit mask of PWRONPRGDONE field. */ + #define USBHSCORE_DCTL_PWRONPRGDONE_Min (0x0UL) /*!< Min enumerator value of PWRONPRGDONE field. */ + #define USBHSCORE_DCTL_PWRONPRGDONE_Max (0x1UL) /*!< Max enumerator value of PWRONPRGDONE field. */ + #define USBHSCORE_DCTL_PWRONPRGDONE_NOTDONE (0x0UL) /*!< Power-On Programming not done */ + #define USBHSCORE_DCTL_PWRONPRGDONE_DONE (0x1UL) /*!< Power-On Programming Done */ + +/* IGNRFRMNUM @Bit 15 : Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) */ + #define USBHSCORE_DCTL_IGNRFRMNUM_Pos (15UL) /*!< Position of IGNRFRMNUM field. */ + #define USBHSCORE_DCTL_IGNRFRMNUM_Msk (0x1UL << USBHSCORE_DCTL_IGNRFRMNUM_Pos) /*!< Bit mask of IGNRFRMNUM field. */ + #define USBHSCORE_DCTL_IGNRFRMNUM_Min (0x0UL) /*!< Min enumerator value of IGNRFRMNUM field. */ + #define USBHSCORE_DCTL_IGNRFRMNUM_Max (0x1UL) /*!< Max enumerator value of IGNRFRMNUM field. */ + #define USBHSCORE_DCTL_IGNRFRMNUM_DISABLED (0x0UL) /*!< Scatter/Gather DMA Mode: The core transmits the packets only in the + frame number in which they are intended to be + transmitted.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt + feature is disabled.*/ + #define USBHSCORE_DCTL_IGNRFRMNUM_ENABLED (0x1UL) /*!< Scatter/Gather DMA Mode: The core ignores the frame number, sending + packets immediately as the packets are ready.Non-Scatter/Gather DMA + Mode: Periodic Transfer Interrupt feature is enabled.*/ + +/* NAKONBBLE @Bit 16 : NAK on Babble Error (NakOnBble) */ + #define USBHSCORE_DCTL_NAKONBBLE_Pos (16UL) /*!< Position of NAKONBBLE field. */ + #define USBHSCORE_DCTL_NAKONBBLE_Msk (0x1UL << USBHSCORE_DCTL_NAKONBBLE_Pos) /*!< Bit mask of NAKONBBLE field. */ + #define USBHSCORE_DCTL_NAKONBBLE_Min (0x0UL) /*!< Min enumerator value of NAKONBBLE field. */ + #define USBHSCORE_DCTL_NAKONBBLE_Max (0x1UL) /*!< Max enumerator value of NAKONBBLE field. */ + #define USBHSCORE_DCTL_NAKONBBLE_DISABLED (0x0UL) /*!< Disable NAK on Babble Error */ + #define USBHSCORE_DCTL_NAKONBBLE_ENABLED (0x1UL) /*!< NAK on Babble Error */ + +/* DEEPSLEEPBESLREJECT @Bit 18 : DeepSleepBESLReject */ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Pos (18UL) /*!< Position of DEEPSLEEPBESLREJECT field. */ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Msk (0x1UL << USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Pos) /*!< Bit mask of + DEEPSLEEPBESLREJECT field.*/ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Min (0x0UL) /*!< Min enumerator value of DEEPSLEEPBESLREJECT field. */ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Max (0x1UL) /*!< Max enumerator value of DEEPSLEEPBESLREJECT field. */ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_DISABLED (0x0UL) /*!< Deep Sleep BESL Reject feature is disabled */ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_ENABLED (0x1UL) /*!< Deep Sleep BESL Reject feature is enabled */ + +/* SERVINT @Bit 19 : Service Interval based scheduling for Isochronous IN Endpoints */ + #define USBHSCORE_DCTL_SERVINT_Pos (19UL) /*!< Position of SERVINT field. */ + #define USBHSCORE_DCTL_SERVINT_Msk (0x1UL << USBHSCORE_DCTL_SERVINT_Pos) /*!< Bit mask of SERVINT field. */ + #define USBHSCORE_DCTL_SERVINT_Min (0x0UL) /*!< Min enumerator value of SERVINT field. */ + #define USBHSCORE_DCTL_SERVINT_Max (0x1UL) /*!< Max enumerator value of SERVINT field. */ + #define USBHSCORE_DCTL_SERVINT_DISABLED (0x0UL) /*!< The controller behavior depends on DCTL.IgnrFrmNum field. */ + #define USBHSCORE_DCTL_SERVINT_ENABLED (0x1UL) /*!< Scatter/Gather DMA Mode: The controller can transmit the packets in + any frame of the service interval.*/ + +/* UTMITERMSELCORRDIS @Bit 31 : Disable the correction of TermSel on UTMI Interface. */ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_Pos (31UL) /*!< Position of UTMITERMSELCORRDIS field. */ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_Msk (0x1UL << USBHSCORE_DCTL_UTMITERMSELCORRDIS_Pos) /*!< Bit mask of + UTMITERMSELCORRDIS field.*/ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_Min (0x0UL) /*!< Min enumerator value of UTMITERMSELCORRDIS field. */ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_Max (0x1UL) /*!< Max enumerator value of UTMITERMSELCORRDIS field. */ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_DISABLED (0x0UL) /*!< Valid Combination of XcvrSel and TermSel is driven by the + Device Controller.*/ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_ENABLED (0x1UL) /*!< Invalid Combination of XcvrSel and TermSel is driven by the + Device Controller.*/ + + +/* USBHSCORE_DSTS: Device Status Register */ + #define USBHSCORE_DSTS_ResetValue (0x00000002UL) /*!< Reset value of DSTS register. */ + +/* SUSPSTS @Bit 0 : Suspend Status (SuspSts) */ + #define USBHSCORE_DSTS_SUSPSTS_Pos (0UL) /*!< Position of SUSPSTS field. */ + #define USBHSCORE_DSTS_SUSPSTS_Msk (0x1UL << USBHSCORE_DSTS_SUSPSTS_Pos) /*!< Bit mask of SUSPSTS field. */ + #define USBHSCORE_DSTS_SUSPSTS_Min (0x0UL) /*!< Min enumerator value of SUSPSTS field. */ + #define USBHSCORE_DSTS_SUSPSTS_Max (0x1UL) /*!< Max enumerator value of SUSPSTS field. */ + #define USBHSCORE_DSTS_SUSPSTS_INACTIVE (0x0UL) /*!< No suspend state */ + #define USBHSCORE_DSTS_SUSPSTS_ACTIVE (0x1UL) /*!< Suspend state */ + +/* ENUMSPD @Bits 1..2 : Enumerated Speed (EnumSpd) */ + #define USBHSCORE_DSTS_ENUMSPD_Pos (1UL) /*!< Position of ENUMSPD field. */ + #define USBHSCORE_DSTS_ENUMSPD_Msk (0x3UL << USBHSCORE_DSTS_ENUMSPD_Pos) /*!< Bit mask of ENUMSPD field. */ + #define USBHSCORE_DSTS_ENUMSPD_Min (0x0UL) /*!< Min enumerator value of ENUMSPD field. */ + #define USBHSCORE_DSTS_ENUMSPD_Max (0x3UL) /*!< Max enumerator value of ENUMSPD field. */ + #define USBHSCORE_DSTS_ENUMSPD_HS3060 (0x0UL) /*!< High speed (PHY clock is running at 30 or 60 MHz) */ + #define USBHSCORE_DSTS_ENUMSPD_FS3060 (0x1UL) /*!< Full speed (PHY clock is running at 30 or 60 MHz) */ + #define USBHSCORE_DSTS_ENUMSPD_LS6 (0x2UL) /*!< Low speed (PHY clock is running at 6 MHz) */ + #define USBHSCORE_DSTS_ENUMSPD_FS48 (0x3UL) /*!< Full speed (PHY clock is running at 48 MHz) */ + +/* ERRTICERR @Bit 3 : Erratic Error (ErrticErr) */ + #define USBHSCORE_DSTS_ERRTICERR_Pos (3UL) /*!< Position of ERRTICERR field. */ + #define USBHSCORE_DSTS_ERRTICERR_Msk (0x1UL << USBHSCORE_DSTS_ERRTICERR_Pos) /*!< Bit mask of ERRTICERR field. */ + #define USBHSCORE_DSTS_ERRTICERR_Min (0x0UL) /*!< Min enumerator value of ERRTICERR field. */ + #define USBHSCORE_DSTS_ERRTICERR_Max (0x1UL) /*!< Max enumerator value of ERRTICERR field. */ + #define USBHSCORE_DSTS_ERRTICERR_INACTIVE (0x0UL) /*!< No Erratic Error */ + #define USBHSCORE_DSTS_ERRTICERR_ACTIVE (0x1UL) /*!< Erratic Error */ + +/* SOFFN @Bits 8..21 : Frame or Microframe Number of the Received SOF (SOFFN) */ + #define USBHSCORE_DSTS_SOFFN_Pos (8UL) /*!< Position of SOFFN field. */ + #define USBHSCORE_DSTS_SOFFN_Msk (0x3FFFUL << USBHSCORE_DSTS_SOFFN_Pos) /*!< Bit mask of SOFFN field. */ + +/* DEVLNSTS @Bits 22..23 : Device Line Status (DevLnSts) */ + #define USBHSCORE_DSTS_DEVLNSTS_Pos (22UL) /*!< Position of DEVLNSTS field. */ + #define USBHSCORE_DSTS_DEVLNSTS_Msk (0x3UL << USBHSCORE_DSTS_DEVLNSTS_Pos) /*!< Bit mask of DEVLNSTS field. */ + + +/* USBHSCORE_DIEPMSK: Device IN Endpoint Common Interrupt Mask Register */ + #define USBHSCORE_DIEPMSK_ResetValue (0x00000000UL) /*!< Reset value of DIEPMSK register. */ + +/* XFERCOMPLMSK @Bit 0 : Transfer Completed Interrupt Mask (XferComplMsk) */ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Pos (0UL) /*!< Position of XFERCOMPLMSK field. */ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_XFERCOMPLMSK_Pos) /*!< Bit mask of XFERCOMPLMSK field.*/ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Min (0x0UL) /*!< Min enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Max (0x1UL) /*!< Max enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_MASK (0x0UL) /*!< Mask Transfer Completed Interrupt */ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_NOMASK (0x1UL) /*!< No Transfer Completed Interrupt Mask */ + +/* EPDISBLDMSK @Bit 1 : Endpoint Disabled Interrupt Mask (EPDisbldMsk) */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Pos (1UL) /*!< Position of EPDISBLDMSK field. */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_EPDISBLDMSK_Pos) /*!< Bit mask of EPDISBLDMSK field. */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Min (0x0UL) /*!< Min enumerator value of EPDISBLDMSK field. */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Max (0x1UL) /*!< Max enumerator value of EPDISBLDMSK field. */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_MASK (0x0UL) /*!< Mask Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_NOMASK (0x1UL) /*!< No Endpoint Disabled Interrupt Mask */ + +/* AHBERRMSK @Bit 2 : AHB Error Mask (AHBErrMsk) */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_Pos (2UL) /*!< Position of AHBERRMSK field. */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_AHBERRMSK_Pos) /*!< Bit mask of AHBERRMSK field. */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_Min (0x0UL) /*!< Min enumerator value of AHBERRMSK field. */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_Max (0x1UL) /*!< Max enumerator value of AHBERRMSK field. */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_MASK (0x0UL) /*!< Mask AHB Error Interrupt */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_NOMASK (0x1UL) /*!< No AHB Error Interrupt Mask */ + +/* TIMEOUTMSK @Bit 3 : Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints) */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Pos (3UL) /*!< Position of TIMEOUTMSK field. */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_TIMEOUTMSK_Pos) /*!< Bit mask of TIMEOUTMSK field. */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Min (0x0UL) /*!< Min enumerator value of TIMEOUTMSK field. */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Max (0x1UL) /*!< Max enumerator value of TIMEOUTMSK field. */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_MASK (0x0UL) /*!< Mask Timeout Condition Interrupt */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_NOMASK (0x1UL) /*!< No Timeout Condition Interrupt Mask */ + +/* INTKNTXFEMPMSK @Bit 4 : IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk) */ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Pos (4UL) /*!< Position of INTKNTXFEMPMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Pos) /*!< Bit mask of INTKNTXFEMPMSK + field.*/ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMPMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMPMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_MASK (0x0UL) /*!< Mask IN Token Received When TxFIFO Empty Interrupt */ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_NOMASK (0x1UL) /*!< No IN Token Received When TxFIFO Empty Interrupt */ + +/* INTKNEPMISMSK @Bit 5 : IN Token received with EP Mismatch Mask (INTknEPMisMsk) */ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Pos (5UL) /*!< Position of INTKNEPMISMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_INTKNEPMISMSK_Pos) /*!< Bit mask of INTKNEPMISMSK + field.*/ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Min (0x0UL) /*!< Min enumerator value of INTKNEPMISMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Max (0x1UL) /*!< Max enumerator value of INTKNEPMISMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_MASK (0x0UL) /*!< Mask IN Token received with EP Mismatch Interrupt */ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_NOMASK (0x1UL) /*!< No Mask IN Token received with EP Mismatch Interrupt */ + +/* INEPNAKEFFMSK @Bit 6 : IN Endpoint NAK Effective Mask (INEPNakEffMsk) */ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Pos (6UL) /*!< Position of INEPNAKEFFMSK field. */ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Pos) /*!< Bit mask of INEPNAKEFFMSK + field.*/ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFFMSK field. */ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFFMSK field. */ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_MASK (0x0UL) /*!< Mask IN Endpoint NAK Effective Interrupt */ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_NOMASK (0x1UL) /*!< No IN Endpoint NAK Effective Interrupt Mask */ + +/* TXFIFOUNDRNMSK @Bit 8 : Fifo Underrun Mask (TxfifoUndrnMsk) */ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Pos (8UL) /*!< Position of TXFIFOUNDRNMSK field. */ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Pos) /*!< Bit mask of TXFIFOUNDRNMSK + field.*/ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRNMSK field. */ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRNMSK field. */ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_MASK (0x0UL) /*!< Mask Fifo Underrun Interrupt */ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_NOMASK (0x1UL) /*!< No Fifo Underrun Interrupt Mask */ + +/* NAKMSK @Bit 13 : NAK interrupt Mask (NAKMsk) */ + #define USBHSCORE_DIEPMSK_NAKMSK_Pos (13UL) /*!< Position of NAKMSK field. */ + #define USBHSCORE_DIEPMSK_NAKMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_NAKMSK_Pos) /*!< Bit mask of NAKMSK field. */ + #define USBHSCORE_DIEPMSK_NAKMSK_Min (0x0UL) /*!< Min enumerator value of NAKMSK field. */ + #define USBHSCORE_DIEPMSK_NAKMSK_Max (0x1UL) /*!< Max enumerator value of NAKMSK field. */ + #define USBHSCORE_DIEPMSK_NAKMSK_MASK (0x0UL) /*!< Mask NAK Interrupt */ + #define USBHSCORE_DIEPMSK_NAKMSK_NOMASK (0x1UL) /*!< No Mask NAK Interrupt */ + + +/* USBHSCORE_DOEPMSK: Device OUT Endpoint Common Interrupt Mask Register */ + #define USBHSCORE_DOEPMSK_ResetValue (0x00000000UL) /*!< Reset value of DOEPMSK register. */ + +/* XFERCOMPLMSK @Bit 0 : Transfer Completed Interrupt Mask (XferComplMsk) */ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Pos (0UL) /*!< Position of XFERCOMPLMSK field. */ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_XFERCOMPLMSK_Pos) /*!< Bit mask of XFERCOMPLMSK field.*/ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Min (0x0UL) /*!< Min enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Max (0x1UL) /*!< Max enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_MASK (0x0UL) /*!< Mask Transfer Completed Interrupt */ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_NOMASK (0x1UL) /*!< No Transfer Completed Interrupt Mask */ + +/* EPDISBLDMSK @Bit 1 : Endpoint Disabled Interrupt Mask (EPDisbldMsk) */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Pos (1UL) /*!< Position of EPDISBLDMSK field. */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_EPDISBLDMSK_Pos) /*!< Bit mask of EPDISBLDMSK field. */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Min (0x0UL) /*!< Min enumerator value of EPDISBLDMSK field. */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Max (0x1UL) /*!< Max enumerator value of EPDISBLDMSK field. */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_MASK (0x0UL) /*!< Mask Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_NOMASK (0x1UL) /*!< No Endpoint Disabled Interrupt Mask */ + +/* AHBERRMSK @Bit 2 : AHB Error (AHBErrMsk) */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_Pos (2UL) /*!< Position of AHBERRMSK field. */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_AHBERRMSK_Pos) /*!< Bit mask of AHBERRMSK field. */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_Min (0x0UL) /*!< Min enumerator value of AHBERRMSK field. */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_Max (0x1UL) /*!< Max enumerator value of AHBERRMSK field. */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_MASK (0x0UL) /*!< Mask AHB Error Interrupt */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_NOMASK (0x1UL) /*!< No AHB Error Interrupt Mask */ + +/* SETUPMSK @Bit 3 : SETUP Phase Done Mask (SetUPMsk) */ + #define USBHSCORE_DOEPMSK_SETUPMSK_Pos (3UL) /*!< Position of SETUPMSK field. */ + #define USBHSCORE_DOEPMSK_SETUPMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_SETUPMSK_Pos) /*!< Bit mask of SETUPMSK field. */ + #define USBHSCORE_DOEPMSK_SETUPMSK_Min (0x0UL) /*!< Min enumerator value of SETUPMSK field. */ + #define USBHSCORE_DOEPMSK_SETUPMSK_Max (0x1UL) /*!< Max enumerator value of SETUPMSK field. */ + #define USBHSCORE_DOEPMSK_SETUPMSK_MASK (0x0UL) /*!< Mask SETUP Phase Done Interrupt */ + #define USBHSCORE_DOEPMSK_SETUPMSK_NOMASK (0x1UL) /*!< No SETUP Phase Done Interrupt Mask */ + +/* OUTTKNEPDISMSK @Bit 4 : OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk) */ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Pos (4UL) /*!< Position of OUTTKNEPDISMSK field. */ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Pos) /*!< Bit mask of OUTTKNEPDISMSK + field.*/ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDISMSK field. */ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDISMSK field. */ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_MASK (0x0UL) /*!< Mask OUT Token Received when Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_NOMASK (0x1UL) /*!< No OUT Token Received when Endpoint Disabled Interrupt Mask */ + +/* STSPHSERCVDMSK @Bit 5 : Status Phase Received Mask (StsPhseRcvdMsk) */ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Pos (5UL) /*!< Position of STSPHSERCVDMSK field. */ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Pos) /*!< Bit mask of STSPHSERCVDMSK + field.*/ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVDMSK field. */ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVDMSK field. */ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_MASK (0x0UL) /*!< Status Phase Received Mask */ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_NOMASK (0x1UL) /*!< No Status Phase Received Mask */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received Mask (Back2BackSETup) */ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPMSK_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_MASK (0x0UL) /*!< Mask Back-to-Back SETUP Packets Received Interrupt */ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_NOMASK (0x1UL) /*!< No Back-to-Back SETUP Packets Received Interrupt Mask */ + +/* OUTPKTERRMSK @Bit 8 : OUT Packet Error Mask (OutPktErrMsk) */ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Pos (8UL) /*!< Position of OUTPKTERRMSK field. */ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_OUTPKTERRMSK_Pos) /*!< Bit mask of OUTPKTERRMSK field.*/ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Min (0x0UL) /*!< Min enumerator value of OUTPKTERRMSK field. */ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Max (0x1UL) /*!< Max enumerator value of OUTPKTERRMSK field. */ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_MASK (0x0UL) /*!< Mask OUT Packet Error Interrupt */ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_NOMASK (0x1UL) /*!< No OUT Packet Error Interrupt Mask */ + +/* BBLEERRMSK @Bit 12 : Babble Error interrupt Mask (BbleErrMsk) */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_Pos (12UL) /*!< Position of BBLEERRMSK field. */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_BBLEERRMSK_Pos) /*!< Bit mask of BBLEERRMSK field. */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_Min (0x0UL) /*!< Min enumerator value of BBLEERRMSK field. */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_Max (0x1UL) /*!< Max enumerator value of BBLEERRMSK field. */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_MASK (0x0UL) /*!< Mask Babble Error Interrupt */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_NOMASK (0x1UL) /*!< No Babble Error Interrupt Mask */ + +/* NAKMSK @Bit 13 : NAK interrupt Mask (NAKMsk) */ + #define USBHSCORE_DOEPMSK_NAKMSK_Pos (13UL) /*!< Position of NAKMSK field. */ + #define USBHSCORE_DOEPMSK_NAKMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_NAKMSK_Pos) /*!< Bit mask of NAKMSK field. */ + #define USBHSCORE_DOEPMSK_NAKMSK_Min (0x0UL) /*!< Min enumerator value of NAKMSK field. */ + #define USBHSCORE_DOEPMSK_NAKMSK_Max (0x1UL) /*!< Max enumerator value of NAKMSK field. */ + #define USBHSCORE_DOEPMSK_NAKMSK_MASK (0x0UL) /*!< Mask NAK Interrupt */ + #define USBHSCORE_DOEPMSK_NAKMSK_NOMASK (0x1UL) /*!< No NAK Interrupt Mask */ + +/* NYETMSK @Bit 14 : NYET interrupt Mask (NYETMsk) */ + #define USBHSCORE_DOEPMSK_NYETMSK_Pos (14UL) /*!< Position of NYETMSK field. */ + #define USBHSCORE_DOEPMSK_NYETMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_NYETMSK_Pos) /*!< Bit mask of NYETMSK field. */ + #define USBHSCORE_DOEPMSK_NYETMSK_Min (0x0UL) /*!< Min enumerator value of NYETMSK field. */ + #define USBHSCORE_DOEPMSK_NYETMSK_Max (0x1UL) /*!< Max enumerator value of NYETMSK field. */ + #define USBHSCORE_DOEPMSK_NYETMSK_MASK (0x0UL) /*!< Mask NYET Interrupt */ + #define USBHSCORE_DOEPMSK_NYETMSK_NOMASK (0x1UL) /*!< No NYET Interrupt Mask */ + + +/* USBHSCORE_DAINT: Device All Endpoints Interrupt Register */ + #define USBHSCORE_DAINT_ResetValue (0x00000000UL) /*!< Reset value of DAINT register. */ + +/* INEPINT0 @Bit 0 : IN Endpoint 0 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT0_Pos (0UL) /*!< Position of INEPINT0 field. */ + #define USBHSCORE_DAINT_INEPINT0_Msk (0x1UL << USBHSCORE_DAINT_INEPINT0_Pos) /*!< Bit mask of INEPINT0 field. */ + #define USBHSCORE_DAINT_INEPINT0_Min (0x0UL) /*!< Min enumerator value of INEPINT0 field. */ + #define USBHSCORE_DAINT_INEPINT0_Max (0x1UL) /*!< Max enumerator value of INEPINT0 field. */ + #define USBHSCORE_DAINT_INEPINT0_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT0_ACTIVE (0x1UL) /*!< Interrupt is active for IN EP0 */ + +/* INEPINT1 @Bit 1 : IN Endpoint 1 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT1_Pos (1UL) /*!< Position of INEPINT1 field. */ + #define USBHSCORE_DAINT_INEPINT1_Msk (0x1UL << USBHSCORE_DAINT_INEPINT1_Pos) /*!< Bit mask of INEPINT1 field. */ + #define USBHSCORE_DAINT_INEPINT1_Min (0x0UL) /*!< Min enumerator value of INEPINT1 field. */ + #define USBHSCORE_DAINT_INEPINT1_Max (0x1UL) /*!< Max enumerator value of INEPINT1 field. */ + #define USBHSCORE_DAINT_INEPINT1_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT1_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT2 @Bit 2 : IN Endpoint 2 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT2_Pos (2UL) /*!< Position of INEPINT2 field. */ + #define USBHSCORE_DAINT_INEPINT2_Msk (0x1UL << USBHSCORE_DAINT_INEPINT2_Pos) /*!< Bit mask of INEPINT2 field. */ + #define USBHSCORE_DAINT_INEPINT2_Min (0x0UL) /*!< Min enumerator value of INEPINT2 field. */ + #define USBHSCORE_DAINT_INEPINT2_Max (0x1UL) /*!< Max enumerator value of INEPINT2 field. */ + #define USBHSCORE_DAINT_INEPINT2_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT2_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT3 @Bit 3 : IN Endpoint 3 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT3_Pos (3UL) /*!< Position of INEPINT3 field. */ + #define USBHSCORE_DAINT_INEPINT3_Msk (0x1UL << USBHSCORE_DAINT_INEPINT3_Pos) /*!< Bit mask of INEPINT3 field. */ + #define USBHSCORE_DAINT_INEPINT3_Min (0x0UL) /*!< Min enumerator value of INEPINT3 field. */ + #define USBHSCORE_DAINT_INEPINT3_Max (0x1UL) /*!< Max enumerator value of INEPINT3 field. */ + #define USBHSCORE_DAINT_INEPINT3_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT3_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT4 @Bit 4 : IN Endpoint 4 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT4_Pos (4UL) /*!< Position of INEPINT4 field. */ + #define USBHSCORE_DAINT_INEPINT4_Msk (0x1UL << USBHSCORE_DAINT_INEPINT4_Pos) /*!< Bit mask of INEPINT4 field. */ + #define USBHSCORE_DAINT_INEPINT4_Min (0x0UL) /*!< Min enumerator value of INEPINT4 field. */ + #define USBHSCORE_DAINT_INEPINT4_Max (0x1UL) /*!< Max enumerator value of INEPINT4 field. */ + #define USBHSCORE_DAINT_INEPINT4_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT4_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT5 @Bit 5 : IN Endpoint 5 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT5_Pos (5UL) /*!< Position of INEPINT5 field. */ + #define USBHSCORE_DAINT_INEPINT5_Msk (0x1UL << USBHSCORE_DAINT_INEPINT5_Pos) /*!< Bit mask of INEPINT5 field. */ + #define USBHSCORE_DAINT_INEPINT5_Min (0x0UL) /*!< Min enumerator value of INEPINT5 field. */ + #define USBHSCORE_DAINT_INEPINT5_Max (0x1UL) /*!< Max enumerator value of INEPINT5 field. */ + #define USBHSCORE_DAINT_INEPINT5_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT5_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT6 @Bit 6 : IN Endpoint 6 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT6_Pos (6UL) /*!< Position of INEPINT6 field. */ + #define USBHSCORE_DAINT_INEPINT6_Msk (0x1UL << USBHSCORE_DAINT_INEPINT6_Pos) /*!< Bit mask of INEPINT6 field. */ + #define USBHSCORE_DAINT_INEPINT6_Min (0x0UL) /*!< Min enumerator value of INEPINT6 field. */ + #define USBHSCORE_DAINT_INEPINT6_Max (0x1UL) /*!< Max enumerator value of INEPINT6 field. */ + #define USBHSCORE_DAINT_INEPINT6_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT6_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT7 @Bit 7 : IN Endpoint 7 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT7_Pos (7UL) /*!< Position of INEPINT7 field. */ + #define USBHSCORE_DAINT_INEPINT7_Msk (0x1UL << USBHSCORE_DAINT_INEPINT7_Pos) /*!< Bit mask of INEPINT7 field. */ + #define USBHSCORE_DAINT_INEPINT7_Min (0x0UL) /*!< Min enumerator value of INEPINT7 field. */ + #define USBHSCORE_DAINT_INEPINT7_Max (0x1UL) /*!< Max enumerator value of INEPINT7 field. */ + #define USBHSCORE_DAINT_INEPINT7_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT7_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT8 @Bit 8 : IN Endpoint 8 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT8_Pos (8UL) /*!< Position of INEPINT8 field. */ + #define USBHSCORE_DAINT_INEPINT8_Msk (0x1UL << USBHSCORE_DAINT_INEPINT8_Pos) /*!< Bit mask of INEPINT8 field. */ + #define USBHSCORE_DAINT_INEPINT8_Min (0x0UL) /*!< Min enumerator value of INEPINT8 field. */ + #define USBHSCORE_DAINT_INEPINT8_Max (0x1UL) /*!< Max enumerator value of INEPINT8 field. */ + #define USBHSCORE_DAINT_INEPINT8_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT8_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT9 @Bit 9 : IN Endpoint 9 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT9_Pos (9UL) /*!< Position of INEPINT9 field. */ + #define USBHSCORE_DAINT_INEPINT9_Msk (0x1UL << USBHSCORE_DAINT_INEPINT9_Pos) /*!< Bit mask of INEPINT9 field. */ + #define USBHSCORE_DAINT_INEPINT9_Min (0x0UL) /*!< Min enumerator value of INEPINT9 field. */ + #define USBHSCORE_DAINT_INEPINT9_Max (0x1UL) /*!< Max enumerator value of INEPINT9 field. */ + #define USBHSCORE_DAINT_INEPINT9_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT9_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT10 @Bit 10 : IN Endpoint 10 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT10_Pos (10UL) /*!< Position of INEPINT10 field. */ + #define USBHSCORE_DAINT_INEPINT10_Msk (0x1UL << USBHSCORE_DAINT_INEPINT10_Pos) /*!< Bit mask of INEPINT10 field. */ + #define USBHSCORE_DAINT_INEPINT10_Min (0x0UL) /*!< Min enumerator value of INEPINT10 field. */ + #define USBHSCORE_DAINT_INEPINT10_Max (0x1UL) /*!< Max enumerator value of INEPINT10 field. */ + #define USBHSCORE_DAINT_INEPINT10_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT10_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT11 @Bit 11 : IN Endpoint 11 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT11_Pos (11UL) /*!< Position of INEPINT11 field. */ + #define USBHSCORE_DAINT_INEPINT11_Msk (0x1UL << USBHSCORE_DAINT_INEPINT11_Pos) /*!< Bit mask of INEPINT11 field. */ + #define USBHSCORE_DAINT_INEPINT11_Min (0x0UL) /*!< Min enumerator value of INEPINT11 field. */ + #define USBHSCORE_DAINT_INEPINT11_Max (0x1UL) /*!< Max enumerator value of INEPINT11 field. */ + #define USBHSCORE_DAINT_INEPINT11_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT11_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT12 @Bit 12 : IN Endpoint 12 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT12_Pos (12UL) /*!< Position of INEPINT12 field. */ + #define USBHSCORE_DAINT_INEPINT12_Msk (0x1UL << USBHSCORE_DAINT_INEPINT12_Pos) /*!< Bit mask of INEPINT12 field. */ + #define USBHSCORE_DAINT_INEPINT12_Min (0x0UL) /*!< Min enumerator value of INEPINT12 field. */ + #define USBHSCORE_DAINT_INEPINT12_Max (0x1UL) /*!< Max enumerator value of INEPINT12 field. */ + #define USBHSCORE_DAINT_INEPINT12_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT12_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT13 @Bit 13 : IN Endpoint 13 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT13_Pos (13UL) /*!< Position of INEPINT13 field. */ + #define USBHSCORE_DAINT_INEPINT13_Msk (0x1UL << USBHSCORE_DAINT_INEPINT13_Pos) /*!< Bit mask of INEPINT13 field. */ + #define USBHSCORE_DAINT_INEPINT13_Min (0x0UL) /*!< Min enumerator value of INEPINT13 field. */ + #define USBHSCORE_DAINT_INEPINT13_Max (0x1UL) /*!< Max enumerator value of INEPINT13 field. */ + #define USBHSCORE_DAINT_INEPINT13_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT13_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT14 @Bit 14 : IN Endpoint 14 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT14_Pos (14UL) /*!< Position of INEPINT14 field. */ + #define USBHSCORE_DAINT_INEPINT14_Msk (0x1UL << USBHSCORE_DAINT_INEPINT14_Pos) /*!< Bit mask of INEPINT14 field. */ + #define USBHSCORE_DAINT_INEPINT14_Min (0x0UL) /*!< Min enumerator value of INEPINT14 field. */ + #define USBHSCORE_DAINT_INEPINT14_Max (0x1UL) /*!< Max enumerator value of INEPINT14 field. */ + #define USBHSCORE_DAINT_INEPINT14_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT14_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT15 @Bit 15 : IN Endpoint 15 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT15_Pos (15UL) /*!< Position of INEPINT15 field. */ + #define USBHSCORE_DAINT_INEPINT15_Msk (0x1UL << USBHSCORE_DAINT_INEPINT15_Pos) /*!< Bit mask of INEPINT15 field. */ + #define USBHSCORE_DAINT_INEPINT15_Min (0x0UL) /*!< Min enumerator value of INEPINT15 field. */ + #define USBHSCORE_DAINT_INEPINT15_Max (0x1UL) /*!< Max enumerator value of INEPINT15 field. */ + #define USBHSCORE_DAINT_INEPINT15_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT15_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* OUTEPINT0 @Bit 16 : OUT Endpoint 0 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT0_Pos (16UL) /*!< Position of OUTEPINT0 field. */ + #define USBHSCORE_DAINT_OUTEPINT0_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT0_Pos) /*!< Bit mask of OUTEPINT0 field. */ + #define USBHSCORE_DAINT_OUTEPINT0_Min (0x0UL) /*!< Min enumerator value of OUTEPINT0 field. */ + #define USBHSCORE_DAINT_OUTEPINT0_Max (0x1UL) /*!< Max enumerator value of OUTEPINT0 field. */ + #define USBHSCORE_DAINT_OUTEPINT0_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT0_ACTIVE (0x1UL) /*!< Interrupt is active for OUT EP0 */ + +/* OUTEPINT1 @Bit 17 : OUT Endpoint 1 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT1_Pos (17UL) /*!< Position of OUTEPINT1 field. */ + #define USBHSCORE_DAINT_OUTEPINT1_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT1_Pos) /*!< Bit mask of OUTEPINT1 field. */ + #define USBHSCORE_DAINT_OUTEPINT1_Min (0x0UL) /*!< Min enumerator value of OUTEPINT1 field. */ + #define USBHSCORE_DAINT_OUTEPINT1_Max (0x1UL) /*!< Max enumerator value of OUTEPINT1 field. */ + #define USBHSCORE_DAINT_OUTEPINT1_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT1_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT2 @Bit 18 : OUT Endpoint 2 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT2_Pos (18UL) /*!< Position of OUTEPINT2 field. */ + #define USBHSCORE_DAINT_OUTEPINT2_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT2_Pos) /*!< Bit mask of OUTEPINT2 field. */ + #define USBHSCORE_DAINT_OUTEPINT2_Min (0x0UL) /*!< Min enumerator value of OUTEPINT2 field. */ + #define USBHSCORE_DAINT_OUTEPINT2_Max (0x1UL) /*!< Max enumerator value of OUTEPINT2 field. */ + #define USBHSCORE_DAINT_OUTEPINT2_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT2_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT3 @Bit 19 : OUT Endpoint 3 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT3_Pos (19UL) /*!< Position of OUTEPINT3 field. */ + #define USBHSCORE_DAINT_OUTEPINT3_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT3_Pos) /*!< Bit mask of OUTEPINT3 field. */ + #define USBHSCORE_DAINT_OUTEPINT3_Min (0x0UL) /*!< Min enumerator value of OUTEPINT3 field. */ + #define USBHSCORE_DAINT_OUTEPINT3_Max (0x1UL) /*!< Max enumerator value of OUTEPINT3 field. */ + #define USBHSCORE_DAINT_OUTEPINT3_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT3_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT4 @Bit 20 : OUT Endpoint 4 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT4_Pos (20UL) /*!< Position of OUTEPINT4 field. */ + #define USBHSCORE_DAINT_OUTEPINT4_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT4_Pos) /*!< Bit mask of OUTEPINT4 field. */ + #define USBHSCORE_DAINT_OUTEPINT4_Min (0x0UL) /*!< Min enumerator value of OUTEPINT4 field. */ + #define USBHSCORE_DAINT_OUTEPINT4_Max (0x1UL) /*!< Max enumerator value of OUTEPINT4 field. */ + #define USBHSCORE_DAINT_OUTEPINT4_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT4_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT5 @Bit 21 : OUT Endpoint 5 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT5_Pos (21UL) /*!< Position of OUTEPINT5 field. */ + #define USBHSCORE_DAINT_OUTEPINT5_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT5_Pos) /*!< Bit mask of OUTEPINT5 field. */ + #define USBHSCORE_DAINT_OUTEPINT5_Min (0x0UL) /*!< Min enumerator value of OUTEPINT5 field. */ + #define USBHSCORE_DAINT_OUTEPINT5_Max (0x1UL) /*!< Max enumerator value of OUTEPINT5 field. */ + #define USBHSCORE_DAINT_OUTEPINT5_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT5_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT6 @Bit 22 : OUT Endpoint 6 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT6_Pos (22UL) /*!< Position of OUTEPINT6 field. */ + #define USBHSCORE_DAINT_OUTEPINT6_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT6_Pos) /*!< Bit mask of OUTEPINT6 field. */ + #define USBHSCORE_DAINT_OUTEPINT6_Min (0x0UL) /*!< Min enumerator value of OUTEPINT6 field. */ + #define USBHSCORE_DAINT_OUTEPINT6_Max (0x1UL) /*!< Max enumerator value of OUTEPINT6 field. */ + #define USBHSCORE_DAINT_OUTEPINT6_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT6_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT7 @Bit 23 : OUT Endpoint 7 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT7_Pos (23UL) /*!< Position of OUTEPINT7 field. */ + #define USBHSCORE_DAINT_OUTEPINT7_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT7_Pos) /*!< Bit mask of OUTEPINT7 field. */ + #define USBHSCORE_DAINT_OUTEPINT7_Min (0x0UL) /*!< Min enumerator value of OUTEPINT7 field. */ + #define USBHSCORE_DAINT_OUTEPINT7_Max (0x1UL) /*!< Max enumerator value of OUTEPINT7 field. */ + #define USBHSCORE_DAINT_OUTEPINT7_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT7_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT8 @Bit 24 : OUT Endpoint 8 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT8_Pos (24UL) /*!< Position of OUTEPINT8 field. */ + #define USBHSCORE_DAINT_OUTEPINT8_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT8_Pos) /*!< Bit mask of OUTEPINT8 field. */ + #define USBHSCORE_DAINT_OUTEPINT8_Min (0x0UL) /*!< Min enumerator value of OUTEPINT8 field. */ + #define USBHSCORE_DAINT_OUTEPINT8_Max (0x1UL) /*!< Max enumerator value of OUTEPINT8 field. */ + #define USBHSCORE_DAINT_OUTEPINT8_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT8_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT9 @Bit 25 : OUT Endpoint 9 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT9_Pos (25UL) /*!< Position of OUTEPINT9 field. */ + #define USBHSCORE_DAINT_OUTEPINT9_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT9_Pos) /*!< Bit mask of OUTEPINT9 field. */ + #define USBHSCORE_DAINT_OUTEPINT9_Min (0x0UL) /*!< Min enumerator value of OUTEPINT9 field. */ + #define USBHSCORE_DAINT_OUTEPINT9_Max (0x1UL) /*!< Max enumerator value of OUTEPINT9 field. */ + #define USBHSCORE_DAINT_OUTEPINT9_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT9_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT10 @Bit 26 : OUT Endpoint 10 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT10_Pos (26UL) /*!< Position of OUTEPINT10 field. */ + #define USBHSCORE_DAINT_OUTEPINT10_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT10_Pos) /*!< Bit mask of OUTEPINT10 field. */ + #define USBHSCORE_DAINT_OUTEPINT10_Min (0x0UL) /*!< Min enumerator value of OUTEPINT10 field. */ + #define USBHSCORE_DAINT_OUTEPINT10_Max (0x1UL) /*!< Max enumerator value of OUTEPINT10 field. */ + #define USBHSCORE_DAINT_OUTEPINT10_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT10_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT11 @Bit 27 : OUT Endpoint 11 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT11_Pos (27UL) /*!< Position of OUTEPINT11 field. */ + #define USBHSCORE_DAINT_OUTEPINT11_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT11_Pos) /*!< Bit mask of OUTEPINT11 field. */ + #define USBHSCORE_DAINT_OUTEPINT11_Min (0x0UL) /*!< Min enumerator value of OUTEPINT11 field. */ + #define USBHSCORE_DAINT_OUTEPINT11_Max (0x1UL) /*!< Max enumerator value of OUTEPINT11 field. */ + #define USBHSCORE_DAINT_OUTEPINT11_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT11_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT12 @Bit 28 : OUT Endpoint 12 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT12_Pos (28UL) /*!< Position of OUTEPINT12 field. */ + #define USBHSCORE_DAINT_OUTEPINT12_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT12_Pos) /*!< Bit mask of OUTEPINT12 field. */ + #define USBHSCORE_DAINT_OUTEPINT12_Min (0x0UL) /*!< Min enumerator value of OUTEPINT12 field. */ + #define USBHSCORE_DAINT_OUTEPINT12_Max (0x1UL) /*!< Max enumerator value of OUTEPINT12 field. */ + #define USBHSCORE_DAINT_OUTEPINT12_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT12_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT13 @Bit 29 : OUT Endpoint 13 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT13_Pos (29UL) /*!< Position of OUTEPINT13 field. */ + #define USBHSCORE_DAINT_OUTEPINT13_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT13_Pos) /*!< Bit mask of OUTEPINT13 field. */ + #define USBHSCORE_DAINT_OUTEPINT13_Min (0x0UL) /*!< Min enumerator value of OUTEPINT13 field. */ + #define USBHSCORE_DAINT_OUTEPINT13_Max (0x1UL) /*!< Max enumerator value of OUTEPINT13 field. */ + #define USBHSCORE_DAINT_OUTEPINT13_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT13_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT14 @Bit 30 : OUT Endpoint 14 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT14_Pos (30UL) /*!< Position of OUTEPINT14 field. */ + #define USBHSCORE_DAINT_OUTEPINT14_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT14_Pos) /*!< Bit mask of OUTEPINT14 field. */ + #define USBHSCORE_DAINT_OUTEPINT14_Min (0x0UL) /*!< Min enumerator value of OUTEPINT14 field. */ + #define USBHSCORE_DAINT_OUTEPINT14_Max (0x1UL) /*!< Max enumerator value of OUTEPINT14 field. */ + #define USBHSCORE_DAINT_OUTEPINT14_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT14_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT15 @Bit 31 : OUT Endpoint 15 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT15_Pos (31UL) /*!< Position of OUTEPINT15 field. */ + #define USBHSCORE_DAINT_OUTEPINT15_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT15_Pos) /*!< Bit mask of OUTEPINT15 field. */ + #define USBHSCORE_DAINT_OUTEPINT15_Min (0x0UL) /*!< Min enumerator value of OUTEPINT15 field. */ + #define USBHSCORE_DAINT_OUTEPINT15_Max (0x1UL) /*!< Max enumerator value of OUTEPINT15 field. */ + #define USBHSCORE_DAINT_OUTEPINT15_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT15_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + + +/* USBHSCORE_DAINTMSK: Device All Endpoints Interrupt Mask Register */ + #define USBHSCORE_DAINTMSK_ResetValue (0x00000000UL) /*!< Reset value of DAINTMSK register. */ + +/* INEPMSK0 @Bit 0 : IN Endpoint 0 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK0_Pos (0UL) /*!< Position of INEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK0_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK0_Pos) /*!< Bit mask of INEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK0_Min (0x0UL) /*!< Min enumerator value of INEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK0_Max (0x1UL) /*!< Max enumerator value of INEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK0_MASK (0x0UL) /*!< Mask IN Endpoint 0 Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK0_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK1 @Bit 1 : IN Endpoint 1 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK1_Pos (1UL) /*!< Position of INEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK1_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK1_Pos) /*!< Bit mask of INEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK1_Min (0x0UL) /*!< Min enumerator value of INEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK1_Max (0x1UL) /*!< Max enumerator value of INEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK1_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK1_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK2 @Bit 2 : IN Endpoint 2 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK2_Pos (2UL) /*!< Position of INEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK2_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK2_Pos) /*!< Bit mask of INEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK2_Min (0x0UL) /*!< Min enumerator value of INEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK2_Max (0x1UL) /*!< Max enumerator value of INEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK2_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK2_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK3 @Bit 3 : IN Endpoint 3 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK3_Pos (3UL) /*!< Position of INEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK3_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK3_Pos) /*!< Bit mask of INEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK3_Min (0x0UL) /*!< Min enumerator value of INEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK3_Max (0x1UL) /*!< Max enumerator value of INEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK3_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK3_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK4 @Bit 4 : IN Endpoint 4 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK4_Pos (4UL) /*!< Position of INEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK4_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK4_Pos) /*!< Bit mask of INEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK4_Min (0x0UL) /*!< Min enumerator value of INEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK4_Max (0x1UL) /*!< Max enumerator value of INEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK4_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK4_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK5 @Bit 5 : IN Endpoint 5 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK5_Pos (5UL) /*!< Position of INEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK5_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK5_Pos) /*!< Bit mask of INEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK5_Min (0x0UL) /*!< Min enumerator value of INEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK5_Max (0x1UL) /*!< Max enumerator value of INEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK5_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK5_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK6 @Bit 6 : IN Endpoint 6 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK6_Pos (6UL) /*!< Position of INEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK6_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK6_Pos) /*!< Bit mask of INEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK6_Min (0x0UL) /*!< Min enumerator value of INEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK6_Max (0x1UL) /*!< Max enumerator value of INEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK6_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK6_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK7 @Bit 7 : IN Endpoint 7 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK7_Pos (7UL) /*!< Position of INEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK7_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK7_Pos) /*!< Bit mask of INEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK7_Min (0x0UL) /*!< Min enumerator value of INEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK7_Max (0x1UL) /*!< Max enumerator value of INEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK7_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK7_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK8 @Bit 8 : IN Endpoint 8 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK8_Pos (8UL) /*!< Position of INEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK8_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK8_Pos) /*!< Bit mask of INEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK8_Min (0x0UL) /*!< Min enumerator value of INEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK8_Max (0x1UL) /*!< Max enumerator value of INEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK8_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK8_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK9 @Bit 9 : IN Endpoint 9 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK9_Pos (9UL) /*!< Position of INEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK9_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK9_Pos) /*!< Bit mask of INEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK9_Min (0x0UL) /*!< Min enumerator value of INEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK9_Max (0x1UL) /*!< Max enumerator value of INEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK9_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK9_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK10 @Bit 10 : IN Endpoint 10 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK10_Pos (10UL) /*!< Position of INEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK10_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK10_Pos) /*!< Bit mask of INEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK10_Min (0x0UL) /*!< Min enumerator value of INEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK10_Max (0x1UL) /*!< Max enumerator value of INEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK10_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK10_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK11 @Bit 11 : IN Endpoint 11 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK11_Pos (11UL) /*!< Position of INEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK11_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK11_Pos) /*!< Bit mask of INEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK11_Min (0x0UL) /*!< Min enumerator value of INEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK11_Max (0x1UL) /*!< Max enumerator value of INEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK11_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK11_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK12 @Bit 12 : IN Endpoint 12 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK12_Pos (12UL) /*!< Position of INEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK12_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK12_Pos) /*!< Bit mask of INEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK12_Min (0x0UL) /*!< Min enumerator value of INEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK12_Max (0x1UL) /*!< Max enumerator value of INEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK12_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK12_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK13 @Bit 13 : IN Endpoint 13 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK13_Pos (13UL) /*!< Position of INEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK13_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK13_Pos) /*!< Bit mask of INEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK13_Min (0x0UL) /*!< Min enumerator value of INEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK13_Max (0x1UL) /*!< Max enumerator value of INEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK13_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK13_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK14 @Bit 14 : IN Endpoint 14 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK14_Pos (14UL) /*!< Position of INEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK14_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK14_Pos) /*!< Bit mask of INEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK14_Min (0x0UL) /*!< Min enumerator value of INEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK14_Max (0x1UL) /*!< Max enumerator value of INEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK14_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK14_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK15 @Bit 15 : IN Endpoint 15 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK15_Pos (15UL) /*!< Position of INEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK15_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK15_Pos) /*!< Bit mask of INEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK15_Min (0x0UL) /*!< Min enumerator value of INEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK15_Max (0x1UL) /*!< Max enumerator value of INEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK15_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK15_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK0 @Bit 16 : OUT Endpoint 0 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_Pos (16UL) /*!< Position of OUTEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK0_Pos) /*!< Bit mask of OUTEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_MASK (0x0UL) /*!< Mask OUT Endpoint 0 Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK1 @Bit 17 : OUT Endpoint 1 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_Pos (17UL) /*!< Position of OUTEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK1_Pos) /*!< Bit mask of OUTEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK2 @Bit 18 : OUT Endpoint 2 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_Pos (18UL) /*!< Position of OUTEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK2_Pos) /*!< Bit mask of OUTEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK3 @Bit 19 : OUT Endpoint 3 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_Pos (19UL) /*!< Position of OUTEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK3_Pos) /*!< Bit mask of OUTEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK4 @Bit 20 : OUT Endpoint 4 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_Pos (20UL) /*!< Position of OUTEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK4_Pos) /*!< Bit mask of OUTEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK5 @Bit 21 : OUT Endpoint 5 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_Pos (21UL) /*!< Position of OUTEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK5_Pos) /*!< Bit mask of OUTEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK6 @Bit 22 : OUT Endpoint 6 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK6_Pos (22UL) /*!< Position of OUTEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK6_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK6_Pos) /*!< Bit mask of OUTEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK6_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK6_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK6_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK6_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK7 @Bit 23 : OUT Endpoint 7 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK7_Pos (23UL) /*!< Position of OUTEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK7_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK7_Pos) /*!< Bit mask of OUTEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK7_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK7_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK7_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK7_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK8 @Bit 24 : OUT Endpoint 8 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK8_Pos (24UL) /*!< Position of OUTEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK8_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK8_Pos) /*!< Bit mask of OUTEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK8_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK8_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK8_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK8_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK9 @Bit 25 : OUT Endpoint 9 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK9_Pos (25UL) /*!< Position of OUTEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK9_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK9_Pos) /*!< Bit mask of OUTEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK9_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK9_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK9_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK9_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK10 @Bit 26 : OUT Endpoint 10 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK10_Pos (26UL) /*!< Position of OUTEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK10_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK10_Pos) /*!< Bit mask of OUTEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK10_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK10_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK10_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK10_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK11 @Bit 27 : OUT Endpoint 11 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK11_Pos (27UL) /*!< Position of OUTEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK11_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK11_Pos) /*!< Bit mask of OUTEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK11_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK11_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK11_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK11_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK12 @Bit 28 : OUT Endpoint 12 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_Pos (28UL) /*!< Position of OUTEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK12_Pos) /*!< Bit mask of OUTEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK13 @Bit 29 : OUT Endpoint 13 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_Pos (29UL) /*!< Position of OUTEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK13_Pos) /*!< Bit mask of OUTEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK14 @Bit 30 : OUT Endpoint 14 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_Pos (30UL) /*!< Position of OUTEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK14_Pos) /*!< Bit mask of OUTEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK15 @Bit 31 : OUT Endpoint 15 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_Pos (31UL) /*!< Position of OUTEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK15_Pos) /*!< Bit mask of OUTEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_NOMASK (0x1UL) /*!< No Interrupt mask */ + + +/* USBHSCORE_DVBUSDIS: Device VBUS Discharge Time Register */ + #define USBHSCORE_DVBUSDIS_ResetValue (0x000017D7UL) /*!< Reset value of DVBUSDIS register. */ + +/* DVBUSDIS @Bits 0..15 : Device VBUS Discharge Time (DVBUSDis) */ + #define USBHSCORE_DVBUSDIS_DVBUSDIS_Pos (0UL) /*!< Position of DVBUSDIS field. */ + #define USBHSCORE_DVBUSDIS_DVBUSDIS_Msk (0xFFFFUL << USBHSCORE_DVBUSDIS_DVBUSDIS_Pos) /*!< Bit mask of DVBUSDIS field. */ + + +/* USBHSCORE_DVBUSPULSE: Device VBUS Pulsing Time Register */ + #define USBHSCORE_DVBUSPULSE_ResetValue (0x000005B8UL) /*!< Reset value of DVBUSPULSE register. */ + +/* DVBUSPULSE @Bits 0..11 : Device VBUS Pulsing Time (DVBUSPulse) */ + #define USBHSCORE_DVBUSPULSE_DVBUSPULSE_Pos (0UL) /*!< Position of DVBUSPULSE field. */ + #define USBHSCORE_DVBUSPULSE_DVBUSPULSE_Msk (0xFFFUL << USBHSCORE_DVBUSPULSE_DVBUSPULSE_Pos) /*!< Bit mask of DVBUSPULSE + field.*/ + + +/* USBHSCORE_DTHRCTL: Device Threshold Control Register */ + #define USBHSCORE_DTHRCTL_ResetValue (0x08100020UL) /*!< Reset value of DTHRCTL register. */ + +/* NONISOTHREN @Bit 0 : Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn) */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_Pos (0UL) /*!< Position of NONISOTHREN field. */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_Msk (0x1UL << USBHSCORE_DTHRCTL_NONISOTHREN_Pos) /*!< Bit mask of NONISOTHREN field. */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_Min (0x0UL) /*!< Min enumerator value of NONISOTHREN field. */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_Max (0x1UL) /*!< Max enumerator value of NONISOTHREN field. */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_DISABLED (0x0UL) /*!< No thresholding */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_ENABLED (0x1UL) /*!< Enable thresholding for non-isochronous IN endpoints */ + +/* ISOTHREN @Bit 1 : (unspecified) */ + #define USBHSCORE_DTHRCTL_ISOTHREN_Pos (1UL) /*!< Position of ISOTHREN field. */ + #define USBHSCORE_DTHRCTL_ISOTHREN_Msk (0x1UL << USBHSCORE_DTHRCTL_ISOTHREN_Pos) /*!< Bit mask of ISOTHREN field. */ + #define USBHSCORE_DTHRCTL_ISOTHREN_Min (0x0UL) /*!< Min enumerator value of ISOTHREN field. */ + #define USBHSCORE_DTHRCTL_ISOTHREN_Max (0x1UL) /*!< Max enumerator value of ISOTHREN field. */ + #define USBHSCORE_DTHRCTL_ISOTHREN_DISABLED (0x0UL) /*!< No thresholding */ + #define USBHSCORE_DTHRCTL_ISOTHREN_ENABLED (0x1UL) /*!< Enables thresholding for isochronous IN endpoints */ + +/* TXTHRLEN @Bits 2..10 : Transmit Threshold Length (TxThrLen) */ + #define USBHSCORE_DTHRCTL_TXTHRLEN_Pos (2UL) /*!< Position of TXTHRLEN field. */ + #define USBHSCORE_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USBHSCORE_DTHRCTL_TXTHRLEN_Pos) /*!< Bit mask of TXTHRLEN field. */ + +/* AHBTHRRATIO @Bits 11..12 : AHB Threshold Ratio (AHBThrRatio) */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Pos (11UL) /*!< Position of AHBTHRRATIO field. */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Msk (0x3UL << USBHSCORE_DTHRCTL_AHBTHRRATIO_Pos) /*!< Bit mask of AHBTHRRATIO field. */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Min (0x0UL) /*!< Min enumerator value of AHBTHRRATIO field. */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Max (0x3UL) /*!< Max enumerator value of AHBTHRRATIO field. */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESZERO (0x0UL) /*!< AHB threshold = MAC threshold */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESONE (0x1UL) /*!< AHB threshold = MAC threshold /2 */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESTWO (0x2UL) /*!< AHB threshold = MAC threshold /4 */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESTHREE (0x3UL) /*!< AHB threshold = MAC threshold /8 */ + +/* RXTHREN @Bit 16 : Receive Threshold Enable (RxThrEn) */ + #define USBHSCORE_DTHRCTL_RXTHREN_Pos (16UL) /*!< Position of RXTHREN field. */ + #define USBHSCORE_DTHRCTL_RXTHREN_Msk (0x1UL << USBHSCORE_DTHRCTL_RXTHREN_Pos) /*!< Bit mask of RXTHREN field. */ + #define USBHSCORE_DTHRCTL_RXTHREN_Min (0x0UL) /*!< Min enumerator value of RXTHREN field. */ + #define USBHSCORE_DTHRCTL_RXTHREN_Max (0x1UL) /*!< Max enumerator value of RXTHREN field. */ + #define USBHSCORE_DTHRCTL_RXTHREN_DISABLED (0x0UL) /*!< Disable thresholding */ + #define USBHSCORE_DTHRCTL_RXTHREN_ENABLED (0x1UL) /*!< Enable thresholding in the receive direction */ + +/* RXTHRLEN @Bits 17..25 : Receive Threshold Length (RxThrLen) */ + #define USBHSCORE_DTHRCTL_RXTHRLEN_Pos (17UL) /*!< Position of RXTHRLEN field. */ + #define USBHSCORE_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USBHSCORE_DTHRCTL_RXTHRLEN_Pos) /*!< Bit mask of RXTHRLEN field. */ + +/* ARBPRKEN @Bit 27 : Arbiter Parking Enable (ArbPrkEn) */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_Pos (27UL) /*!< Position of ARBPRKEN field. */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_Msk (0x1UL << USBHSCORE_DTHRCTL_ARBPRKEN_Pos) /*!< Bit mask of ARBPRKEN field. */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_Min (0x0UL) /*!< Min enumerator value of ARBPRKEN field. */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_Max (0x1UL) /*!< Max enumerator value of ARBPRKEN field. */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_DISABLED (0x0UL) /*!< Disable DMA arbiter parking */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_ENABLED (0x1UL) /*!< Enable DMA arbiter parking for IN endpoints */ + + +/* USBHSCORE_DIEPEMPMSK: Device IN Endpoint FIFO Empty Interrupt Mask Register */ + #define USBHSCORE_DIEPEMPMSK_ResetValue (0x00000000UL) /*!< Reset value of DIEPEMPMSK register. */ + +/* INEPTXFEMPMSK @Bits 0..15 : IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Pos (0UL) /*!< Position of INEPTXFEMPMSK field. */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Msk (0xFFFFUL << USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Pos) /*!< Bit mask of + INEPTXFEMPMSK field.*/ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Min (0x0001UL) /*!< Min enumerator value of INEPTXFEMPMSK field. */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Max (0x8000UL) /*!< Max enumerator value of INEPTXFEMPMSK field. */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP0MASK (0x0001UL) /*!< Mask IN EP0 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP1MASK (0x0002UL) /*!< Mask IN EP1 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP2MASK (0x0004UL) /*!< Mask IN EP2 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP3MASK (0x0008UL) /*!< Mask IN EP3 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP4MASK (0x0010UL) /*!< Mask IN EP4 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP5MASK (0x0020UL) /*!< Mask IN EP5 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP6MASK (0x0040UL) /*!< Mask IN EP6 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP7MASK (0x0080UL) /*!< Mask IN EP7 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP8MASK (0x0100UL) /*!< Mask IN EP8 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP9MASK (0x0200UL) /*!< Mask IN EP9 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP10MASK (0x0400UL) /*!< Mask IN EP10 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP11MASK (0x0800UL) /*!< Mask IN EP11 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP12MASK (0x1000UL) /*!< Mask IN EP12 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP13MASK (0x2000UL) /*!< Mask IN EP13 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP14MASK (0x4000UL) /*!< Mask IN EP14 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP15MASK (0x8000UL) /*!< Mask IN EP15 Tx FIFO Empty Interrupt */ + + +/* USBHSCORE_DIEPCTL0: Device Control IN Endpoint 0 Control Register */ + #define USBHSCORE_DIEPCTL0_ResetValue (0x00008000UL) /*!< Reset value of DIEPCTL0 register. */ + +/* MPS @Bits 0..1 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL0_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL0_MPS_Msk (0x3UL << USBHSCORE_DIEPCTL0_MPS_Pos) /*!< Bit mask of MPS field. */ + #define USBHSCORE_DIEPCTL0_MPS_Min (0x0UL) /*!< Min enumerator value of MPS field. */ + #define USBHSCORE_DIEPCTL0_MPS_Max (0x3UL) /*!< Max enumerator value of MPS field. */ + #define USBHSCORE_DIEPCTL0_MPS_BYTES64 (0x0UL) /*!< 64 bytes */ + #define USBHSCORE_DIEPCTL0_MPS_BYTES32 (0x1UL) /*!< 32 bytes */ + #define USBHSCORE_DIEPCTL0_MPS_BYTES16 (0x2UL) /*!< 16 bytes */ + #define USBHSCORE_DIEPCTL0_MPS_BYTES8 (0x3UL) /*!< 8 bytes */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL0_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL0_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL0_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL0_USBACTEP_Min (0x1UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL0_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL0_USBACTEP_ACTIVE0 (0x1UL) /*!< Control endpoint is always active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL0_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL0_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL0_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL0_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL0_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL0_NAKSTS_INACTIVE (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL0_NAKSTS_ACTIVE (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL0_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL0_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL0_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL0_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL0_EPTYPE_Max (0x0UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL0_EPTYPE_ACTIVE (0x0UL) /*!< Endpoint Control 0 */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL0_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL0_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL0_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL0_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL0_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL0_STALL_INACTIVE (0x0UL) /*!< No Stall */ + #define USBHSCORE_DIEPCTL0_STALL_ACTIVE (0x1UL) /*!< Stall Handshake */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL0_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL0_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL0_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL0_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL0_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DIEPCTL0_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL0_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL0_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL0_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL0_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL0_CNAK_NOCLEAR (0x0UL) /*!< No action */ + #define USBHSCORE_DIEPCTL0_CNAK_CLEAR (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : (unspecified) */ + #define USBHSCORE_DIEPCTL0_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL0_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL0_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL0_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL0_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL0_SNAK_NOSET (0x0UL) /*!< No action */ + #define USBHSCORE_DIEPCTL0_SNAK_SET (0x1UL) /*!< Set NAK */ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL0_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL0_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL0_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL0_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL0_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL0_EPDIS_INACTIVE (0x0UL) /*!< No action */ + #define USBHSCORE_DIEPCTL0_EPDIS_ACTIVE (0x1UL) /*!< Disabled Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL0_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL0_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL0_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL0_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL0_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL0_EPENA_INACTIVE (0x0UL) /*!< No action */ + #define USBHSCORE_DIEPCTL0_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT0: Device IN Endpoint 0 Interrupt Register */ + #define USBHSCORE_DIEPINT0_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT0 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT0_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Completed Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT0_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT0_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT0_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT0_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT0_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT0_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT0_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT0_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT0_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT0_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT0_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT0_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT0_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT0_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT0_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT0_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT0_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT0_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT0_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT0_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT0_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT0_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received when TxFIFO Empty interrupt */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received when TxFIFO Empty Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT0_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT0_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_INACTIVE (0x0UL) /*!< No IN Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT0_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT0_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT0_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT0_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT0_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT0_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT0_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT0_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Fifo Underrun interrupt */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< Fifo Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT0_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT0_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT0_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT0_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT0_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT0_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT0_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT0_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT0_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT0_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT0_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT0_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT0_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT0_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT0_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT0_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT0_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ0: Device IN Endpoint 0 Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ0_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ0 register. */ + +/* XFERSIZE @Bits 0..6 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ0_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ0_XFERSIZE_Msk (0x7FUL << USBHSCORE_DIEPTSIZ0_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..20 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ0_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ0_PKTCNT_Msk (0x3UL << USBHSCORE_DIEPTSIZ0_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + + +/* USBHSCORE_DIEPDMA0: Device IN Endpoint 0 DMA Address Register */ + #define USBHSCORE_DIEPDMA0_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA0 register. */ + +/* DMAADDR @Bits 0..31 : DMAAddr */ + #define USBHSCORE_DIEPDMA0_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA0_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA0_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS0: Device IN Endpoint Transmit FIFO Status Register 0 */ + #define USBHSCORE_DTXFSTS0_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS0 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS0_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS0_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS0_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL1: Device Control IN Endpoint Control Register 1 */ + #define USBHSCORE_DIEPCTL1_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL1 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL1_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL1_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL1_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL1_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL1_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL1_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL1_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL1_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL1_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL1_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL1_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL1_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL1_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL1_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL1_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL1_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL1_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL1_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL1_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL1_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL1_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL1_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL1_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL1_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL1_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL1_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL1_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL1_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL1_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL1_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL1_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL1_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL1_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL1_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL1_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL1_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL1_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL1_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL1_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL1_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL1_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL1_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL1_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL1_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL1_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL1_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL1_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL1_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL1_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL1_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL1_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL1_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL1_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL1_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL1_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL1_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL1_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL1_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL1_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL1_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL1_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL1_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL1_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL1_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL1_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL1_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL1_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL1_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL1_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL1_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL1_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL1_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL1_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL1_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL1_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL1_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL1_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL1_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL1_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL1_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL1_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL1_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL1_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL1_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL1_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL1_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL1_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT1: Device IN Endpoint Interrupt Register 1 */ + #define USBHSCORE_DIEPINT1_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT1 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT1_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT1_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT1_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT1_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT1_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT1_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT1_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT1_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT1_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT1_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT1_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT1_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT1_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT1_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT1_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT1_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT1_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT1_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT1_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT1_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT1_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT1_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT1_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT1_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT1_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT1_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT1_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT1_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT1_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT1_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT1_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT1_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT1_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT1_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT1_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT1_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT1_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT1_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT1_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT1_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT1_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT1_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT1_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT1_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT1_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT1_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT1_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT1_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT1_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT1_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ1: Device IN Endpoint Transfer Size Register 1 */ + #define USBHSCORE_DIEPTSIZ1_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ1 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ1_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ1_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ1_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ1_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ1_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ1_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ1_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ1_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ1_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ1_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ1_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ1_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ1_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ1_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA1: Device IN Endpoint DMA Address Register 1 */ + #define USBHSCORE_DIEPDMA1_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA1 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA1_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA1_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA1_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS1: Device IN Endpoint Transmit FIFO Status Register 1 */ + #define USBHSCORE_DTXFSTS1_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS1 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS1_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS1_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS1_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL2: Device Control IN Endpoint Control Register 2 */ + #define USBHSCORE_DIEPCTL2_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL2 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL2_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL2_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL2_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL2_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL2_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL2_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL2_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL2_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL2_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL2_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL2_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL2_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL2_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL2_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL2_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL2_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL2_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL2_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL2_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL2_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL2_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL2_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL2_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL2_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL2_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL2_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL2_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL2_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL2_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL2_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL2_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL2_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL2_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL2_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL2_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL2_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL2_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL2_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL2_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL2_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL2_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL2_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL2_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL2_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL2_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL2_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL2_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL2_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL2_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL2_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL2_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL2_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL2_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL2_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL2_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL2_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL2_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL2_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL2_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL2_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL2_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL2_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL2_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL2_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL2_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL2_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL2_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL2_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL2_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL2_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL2_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL2_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL2_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL2_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL2_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL2_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL2_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL2_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL2_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL2_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL2_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL2_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL2_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL2_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL2_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL2_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL2_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT2: Device IN Endpoint Interrupt Register 2 */ + #define USBHSCORE_DIEPINT2_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT2 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT2_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT2_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT2_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT2_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT2_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT2_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT2_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT2_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT2_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT2_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT2_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT2_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT2_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT2_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT2_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT2_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT2_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT2_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT2_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT2_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT2_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT2_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT2_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT2_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT2_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT2_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT2_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT2_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT2_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT2_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT2_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT2_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT2_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT2_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT2_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT2_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT2_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT2_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT2_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT2_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT2_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT2_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT2_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT2_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT2_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT2_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT2_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT2_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT2_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT2_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ2: Device IN Endpoint Transfer Size Register 2 */ + #define USBHSCORE_DIEPTSIZ2_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ2 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ2_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ2_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ2_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ2_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ2_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ2_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ2_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ2_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ2_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ2_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ2_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ2_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ2_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ2_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA2: Device IN Endpoint DMA Address Register 2 */ + #define USBHSCORE_DIEPDMA2_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA2 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA2_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA2_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA2_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS2: Device IN Endpoint Transmit FIFO Status Register 2 */ + #define USBHSCORE_DTXFSTS2_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS2 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS2_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS2_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS2_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL3: Device Control IN Endpoint Control Register 3 */ + #define USBHSCORE_DIEPCTL3_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL3 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL3_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL3_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL3_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL3_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL3_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL3_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL3_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL3_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL3_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL3_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL3_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL3_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL3_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL3_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL3_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL3_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL3_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL3_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL3_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL3_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL3_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL3_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL3_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL3_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL3_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL3_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL3_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL3_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL3_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL3_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL3_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL3_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL3_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL3_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL3_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL3_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL3_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL3_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL3_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL3_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL3_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL3_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL3_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL3_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL3_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL3_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL3_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL3_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL3_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL3_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL3_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL3_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL3_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL3_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL3_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL3_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL3_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL3_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL3_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL3_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL3_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL3_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL3_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL3_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL3_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL3_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL3_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL3_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL3_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL3_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL3_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL3_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL3_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL3_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL3_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL3_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL3_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL3_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL3_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL3_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL3_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL3_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL3_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL3_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL3_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL3_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL3_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT3: Device IN Endpoint Interrupt Register 3 */ + #define USBHSCORE_DIEPINT3_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT3 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT3_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT3_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT3_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT3_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT3_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT3_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT3_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT3_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT3_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT3_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT3_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT3_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT3_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT3_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT3_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT3_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT3_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT3_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT3_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT3_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT3_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT3_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT3_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT3_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT3_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT3_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT3_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT3_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT3_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT3_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT3_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT3_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT3_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT3_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT3_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT3_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT3_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT3_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT3_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT3_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT3_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT3_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT3_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT3_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT3_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT3_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT3_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT3_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT3_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT3_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ3: Device IN Endpoint Transfer Size Register 3 */ + #define USBHSCORE_DIEPTSIZ3_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ3 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ3_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ3_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ3_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ3_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ3_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ3_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ3_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ3_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ3_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ3_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ3_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ3_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ3_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ3_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA3: Device IN Endpoint DMA Address Register 3 */ + #define USBHSCORE_DIEPDMA3_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA3 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA3_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA3_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA3_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS3: Device IN Endpoint Transmit FIFO Status Register 3 */ + #define USBHSCORE_DTXFSTS3_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS3 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS3_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS3_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS3_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL4: Device Control IN Endpoint Control Register 4 */ + #define USBHSCORE_DIEPCTL4_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL4 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL4_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL4_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL4_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL4_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL4_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL4_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL4_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL4_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL4_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL4_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL4_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL4_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL4_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL4_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL4_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL4_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL4_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL4_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL4_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL4_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL4_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL4_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL4_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL4_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL4_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL4_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL4_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL4_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL4_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL4_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL4_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL4_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL4_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL4_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL4_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL4_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL4_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL4_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL4_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL4_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL4_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL4_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL4_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL4_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL4_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL4_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL4_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL4_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL4_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL4_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL4_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL4_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL4_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL4_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL4_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL4_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL4_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL4_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL4_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL4_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL4_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL4_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL4_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL4_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL4_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL4_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL4_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL4_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL4_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL4_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL4_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL4_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL4_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL4_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL4_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL4_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL4_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL4_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL4_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL4_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL4_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL4_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL4_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL4_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL4_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL4_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL4_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT4: Device IN Endpoint Interrupt Register 4 */ + #define USBHSCORE_DIEPINT4_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT4 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT4_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT4_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT4_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT4_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT4_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT4_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT4_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT4_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT4_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT4_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT4_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT4_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT4_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT4_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT4_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT4_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT4_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT4_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT4_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT4_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT4_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT4_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT4_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT4_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT4_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT4_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT4_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT4_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT4_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT4_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT4_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT4_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT4_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT4_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT4_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT4_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT4_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT4_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT4_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT4_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT4_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT4_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT4_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT4_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT4_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT4_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT4_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT4_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT4_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT4_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ4: Device IN Endpoint Transfer Size Register 4 */ + #define USBHSCORE_DIEPTSIZ4_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ4 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ4_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ4_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ4_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ4_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ4_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ4_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ4_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ4_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ4_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ4_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ4_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ4_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ4_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ4_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA4: Device IN Endpoint DMA Address Register 4 */ + #define USBHSCORE_DIEPDMA4_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA4 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA4_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA4_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA4_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS4: Device IN Endpoint Transmit FIFO Status Register 4 */ + #define USBHSCORE_DTXFSTS4_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS4 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS4_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS4_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS4_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL5: Device Control IN Endpoint Control Register 5 */ + #define USBHSCORE_DIEPCTL5_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL5 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL5_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL5_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL5_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL5_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL5_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL5_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL5_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL5_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL5_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL5_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL5_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL5_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL5_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL5_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL5_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL5_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL5_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL5_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL5_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL5_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL5_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL5_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL5_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL5_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL5_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL5_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL5_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL5_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL5_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL5_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL5_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL5_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL5_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL5_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL5_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL5_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL5_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL5_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL5_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL5_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL5_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL5_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL5_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL5_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL5_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL5_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL5_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL5_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL5_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL5_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL5_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL5_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL5_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL5_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL5_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL5_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL5_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL5_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL5_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL5_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL5_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL5_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL5_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL5_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL5_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL5_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL5_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL5_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL5_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL5_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL5_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL5_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL5_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL5_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL5_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL5_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL5_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL5_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL5_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL5_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL5_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL5_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL5_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL5_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL5_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL5_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL5_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT5: Device IN Endpoint Interrupt Register 5 */ + #define USBHSCORE_DIEPINT5_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT5 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT5_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT5_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT5_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT5_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT5_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT5_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT5_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT5_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT5_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT5_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT5_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT5_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT5_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT5_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT5_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT5_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT5_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT5_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT5_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT5_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT5_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT5_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT5_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT5_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT5_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT5_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT5_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT5_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT5_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT5_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT5_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT5_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT5_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT5_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT5_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT5_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT5_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT5_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT5_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT5_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT5_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT5_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT5_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT5_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT5_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT5_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT5_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT5_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT5_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT5_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ5: Device IN Endpoint Transfer Size Register 5 */ + #define USBHSCORE_DIEPTSIZ5_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ5 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ5_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ5_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ5_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ5_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ5_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ5_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ5_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ5_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ5_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ5_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ5_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ5_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ5_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ5_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA5: Device IN Endpoint DMA Address Register 5 */ + #define USBHSCORE_DIEPDMA5_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA5 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA5_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA5_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA5_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS5: Device IN Endpoint Transmit FIFO Status Register 5 */ + #define USBHSCORE_DTXFSTS5_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS5 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS5_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS5_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS5_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL6: Device Control IN Endpoint Control Register 6 */ + #define USBHSCORE_DIEPCTL6_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL6 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL6_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL6_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL6_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL6_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL6_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL6_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL6_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL6_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL6_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL6_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL6_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL6_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL6_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL6_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL6_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL6_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL6_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL6_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL6_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL6_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL6_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL6_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL6_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL6_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL6_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL6_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL6_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL6_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL6_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL6_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL6_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL6_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL6_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL6_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL6_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL6_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL6_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL6_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL6_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL6_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL6_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL6_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL6_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL6_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL6_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL6_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL6_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL6_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL6_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL6_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL6_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL6_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL6_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL6_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL6_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL6_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL6_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL6_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL6_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL6_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL6_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL6_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL6_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL6_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL6_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL6_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL6_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL6_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL6_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL6_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL6_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL6_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL6_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL6_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL6_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL6_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL6_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL6_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL6_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL6_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL6_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL6_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL6_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL6_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL6_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL6_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL6_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT6: Device IN Endpoint Interrupt Register 6 */ + #define USBHSCORE_DIEPINT6_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT6 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT6_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT6_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT6_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT6_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT6_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT6_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT6_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT6_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT6_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT6_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT6_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT6_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT6_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT6_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT6_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT6_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT6_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT6_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT6_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT6_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT6_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT6_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT6_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT6_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT6_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT6_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT6_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT6_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT6_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT6_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT6_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT6_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT6_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT6_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT6_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT6_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT6_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT6_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT6_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT6_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT6_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT6_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT6_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT6_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT6_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT6_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT6_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT6_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT6_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT6_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ6: Device IN Endpoint Transfer Size Register 6 */ + #define USBHSCORE_DIEPTSIZ6_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ6 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ6_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ6_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ6_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ6_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ6_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ6_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ6_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ6_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ6_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ6_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ6_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ6_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ6_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ6_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA6: Device IN Endpoint DMA Address Register 6 */ + #define USBHSCORE_DIEPDMA6_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA6 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA6_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA6_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA6_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS6: Device IN Endpoint Transmit FIFO Status Register 6 */ + #define USBHSCORE_DTXFSTS6_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS6 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS6_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS6_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS6_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL7: Device Control IN Endpoint Control Register 7 */ + #define USBHSCORE_DIEPCTL7_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL7 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL7_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL7_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL7_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL7_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL7_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL7_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL7_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL7_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL7_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL7_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL7_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL7_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL7_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL7_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL7_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL7_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL7_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL7_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL7_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL7_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL7_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL7_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL7_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL7_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL7_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL7_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL7_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL7_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL7_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL7_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL7_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL7_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL7_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL7_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL7_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL7_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL7_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL7_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL7_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL7_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL7_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL7_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL7_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL7_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL7_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL7_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL7_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL7_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL7_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL7_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL7_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL7_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL7_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL7_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL7_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL7_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL7_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL7_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL7_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL7_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL7_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL7_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL7_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL7_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL7_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL7_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL7_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL7_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL7_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL7_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL7_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL7_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL7_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL7_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL7_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL7_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL7_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL7_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL7_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL7_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL7_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL7_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL7_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL7_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL7_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL7_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL7_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT7: Device IN Endpoint Interrupt Register 7 */ + #define USBHSCORE_DIEPINT7_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT7 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT7_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT7_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT7_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT7_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT7_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT7_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT7_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT7_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT7_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT7_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT7_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT7_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT7_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT7_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT7_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT7_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT7_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT7_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT7_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT7_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT7_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT7_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT7_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT7_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT7_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT7_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT7_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT7_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT7_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT7_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT7_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT7_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT7_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT7_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT7_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT7_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT7_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT7_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT7_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT7_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT7_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT7_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT7_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT7_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT7_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT7_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT7_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT7_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT7_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT7_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ7: Device IN Endpoint Transfer Size Register 7 */ + #define USBHSCORE_DIEPTSIZ7_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ7 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ7_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ7_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ7_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ7_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ7_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ7_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ7_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ7_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ7_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ7_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ7_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ7_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ7_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ7_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA7: Device IN Endpoint DMA Address Register 7 */ + #define USBHSCORE_DIEPDMA7_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA7 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA7_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA7_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA7_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS7: Device IN Endpoint Transmit FIFO Status Register 7 */ + #define USBHSCORE_DTXFSTS7_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS7 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS7_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS7_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS7_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL8: Device Control IN Endpoint Control Register 8 */ + #define USBHSCORE_DIEPCTL8_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL8 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL8_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL8_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL8_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL8_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL8_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL8_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL8_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL8_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL8_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL8_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL8_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL8_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL8_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL8_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL8_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL8_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL8_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL8_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL8_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL8_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL8_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL8_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL8_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL8_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL8_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL8_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL8_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL8_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL8_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL8_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL8_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL8_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL8_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL8_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL8_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL8_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL8_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL8_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL8_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL8_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL8_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL8_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL8_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL8_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL8_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL8_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL8_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL8_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL8_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL8_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL8_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL8_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL8_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL8_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL8_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL8_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL8_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL8_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL8_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL8_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL8_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL8_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL8_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL8_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL8_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL8_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL8_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL8_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL8_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL8_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL8_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL8_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL8_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL8_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL8_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL8_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL8_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL8_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL8_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL8_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL8_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL8_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL8_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL8_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL8_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL8_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL8_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT8: Device IN Endpoint Interrupt Register 8 */ + #define USBHSCORE_DIEPINT8_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT8 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT8_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT8_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT8_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT8_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT8_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT8_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT8_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT8_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT8_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT8_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT8_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT8_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT8_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT8_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT8_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT8_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT8_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT8_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT8_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT8_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT8_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT8_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT8_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT8_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT8_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT8_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT8_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT8_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT8_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT8_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT8_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT8_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT8_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT8_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT8_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT8_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT8_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT8_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT8_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT8_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT8_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT8_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT8_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT8_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT8_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT8_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT8_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT8_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT8_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT8_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ8: Device IN Endpoint Transfer Size Register 8 */ + #define USBHSCORE_DIEPTSIZ8_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ8 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ8_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ8_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ8_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ8_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ8_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ8_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ8_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ8_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ8_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ8_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ8_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ8_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ8_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ8_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA8: Device IN Endpoint DMA Address Register 8 */ + #define USBHSCORE_DIEPDMA8_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA8 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA8_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA8_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA8_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS8: Device IN Endpoint Transmit FIFO Status Register 8 */ + #define USBHSCORE_DTXFSTS8_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS8 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS8_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS8_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS8_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL9: Device Control IN Endpoint Control Register 9 */ + #define USBHSCORE_DIEPCTL9_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL9 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL9_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL9_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL9_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL9_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL9_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL9_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL9_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL9_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL9_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL9_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL9_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL9_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL9_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL9_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL9_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL9_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL9_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL9_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL9_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL9_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL9_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL9_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL9_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL9_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL9_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL9_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL9_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL9_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL9_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL9_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL9_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL9_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL9_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL9_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL9_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL9_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL9_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL9_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL9_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL9_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL9_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL9_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL9_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL9_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL9_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL9_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL9_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL9_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL9_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL9_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL9_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL9_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL9_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL9_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL9_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL9_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL9_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL9_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL9_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL9_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL9_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL9_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL9_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL9_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL9_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL9_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL9_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL9_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL9_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL9_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL9_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL9_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL9_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL9_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL9_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL9_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL9_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL9_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL9_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL9_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL9_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL9_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL9_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL9_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL9_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL9_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL9_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT9: Device IN Endpoint Interrupt Register 9 */ + #define USBHSCORE_DIEPINT9_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT9 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT9_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT9_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT9_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT9_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT9_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT9_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT9_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT9_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT9_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT9_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT9_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT9_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT9_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT9_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT9_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT9_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT9_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT9_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT9_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT9_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT9_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT9_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT9_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT9_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT9_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT9_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT9_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT9_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT9_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT9_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT9_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT9_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT9_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT9_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT9_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT9_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT9_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT9_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT9_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT9_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT9_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT9_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT9_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT9_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT9_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT9_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT9_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT9_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT9_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT9_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ9: Device IN Endpoint Transfer Size Register 9 */ + #define USBHSCORE_DIEPTSIZ9_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ9 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ9_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ9_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ9_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ9_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ9_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ9_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ9_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ9_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ9_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ9_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ9_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ9_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ9_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ9_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA9: Device IN Endpoint DMA Address Register 9 */ + #define USBHSCORE_DIEPDMA9_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA9 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA9_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA9_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA9_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS9: Device IN Endpoint Transmit FIFO Status Register 9 */ + #define USBHSCORE_DTXFSTS9_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS9 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS9_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS9_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS9_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL10: Device Control IN Endpoint Control Register 10 */ + #define USBHSCORE_DIEPCTL10_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL10 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL10_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL10_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL10_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL10_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL10_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL10_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL10_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL10_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL10_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL10_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL10_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL10_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL10_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL10_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL10_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL10_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL10_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL10_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL10_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL10_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL10_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL10_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL10_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL10_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL10_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL10_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL10_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL10_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL10_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL10_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL10_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL10_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL10_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL10_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL10_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL10_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL10_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL10_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL10_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL10_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL10_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL10_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL10_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL10_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL10_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL10_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL10_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL10_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL10_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL10_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL10_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL10_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL10_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL10_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL10_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL10_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL10_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL10_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL10_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL10_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL10_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL10_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL10_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL10_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL10_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL10_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL10_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL10_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL10_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL10_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL10_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL10_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL10_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL10_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL10_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL10_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL10_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL10_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL10_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL10_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL10_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL10_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL10_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL10_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL10_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL10_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL10_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT10: Device IN Endpoint Interrupt Register 10 */ + #define USBHSCORE_DIEPINT10_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT10 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT10_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT10_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT10_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT10_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT10_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT10_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT10_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT10_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT10_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT10_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT10_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT10_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT10_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT10_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT10_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT10_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT10_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT10_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT10_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT10_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT10_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT10_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT10_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP + field.*/ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT10_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT10_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT10_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT10_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT10_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT10_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT10_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT10_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT10_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT10_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN + field.*/ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT10_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT10_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT10_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT10_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT10_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT10_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT10_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT10_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT10_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT10_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT10_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT10_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT10_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT10_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT10_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT10_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT10_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ10: Device IN Endpoint Transfer Size Register 10 */ + #define USBHSCORE_DIEPTSIZ10_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ10 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ10_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ10_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ10_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ10_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ10_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ10_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ10_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ10_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ10_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ10_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ10_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ10_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ10_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ10_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA10: Device IN Endpoint DMA Address Register 10 */ + #define USBHSCORE_DIEPDMA10_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA10 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA10_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA10_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA10_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS10: Device IN Endpoint Transmit FIFO Status Register 10 */ + #define USBHSCORE_DTXFSTS10_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS10 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS10_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS10_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS10_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL11: Device Control IN Endpoint Control Register 11 */ + #define USBHSCORE_DIEPCTL11_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL11 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL11_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL11_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL11_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL11_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL11_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL11_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL11_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL11_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL11_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL11_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL11_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL11_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL11_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL11_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL11_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL11_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL11_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL11_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL11_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL11_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL11_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL11_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL11_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL11_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL11_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL11_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL11_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL11_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL11_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL11_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL11_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL11_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL11_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL11_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL11_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL11_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL11_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL11_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL11_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL11_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL11_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL11_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL11_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL11_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL11_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL11_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL11_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL11_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL11_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL11_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL11_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL11_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL11_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL11_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL11_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL11_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL11_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL11_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL11_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL11_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL11_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL11_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL11_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL11_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL11_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL11_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL11_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL11_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL11_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL11_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL11_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL11_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL11_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL11_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL11_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL11_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL11_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL11_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL11_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL11_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL11_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL11_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL11_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL11_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL11_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL11_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL11_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT11: Device IN Endpoint Interrupt Register 11 */ + #define USBHSCORE_DIEPINT11_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT11 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT11_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT11_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT11_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT11_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT11_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT11_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT11_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT11_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT11_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT11_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT11_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT11_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT11_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT11_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT11_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT11_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT11_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT11_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT11_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT11_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT11_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT11_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT11_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP + field.*/ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT11_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT11_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT11_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT11_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT11_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT11_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT11_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT11_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT11_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT11_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN + field.*/ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT11_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT11_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT11_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT11_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT11_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT11_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT11_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT11_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT11_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT11_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT11_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT11_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT11_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT11_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT11_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT11_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT11_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ11: Device IN Endpoint Transfer Size Register 11 */ + #define USBHSCORE_DIEPTSIZ11_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ11 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ11_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ11_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ11_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ11_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ11_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ11_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ11_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ11_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ11_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ11_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ11_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ11_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ11_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ11_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA11: Device IN Endpoint DMA Address Register 11 */ + #define USBHSCORE_DIEPDMA11_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA11 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA11_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA11_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA11_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS11: Device IN Endpoint Transmit FIFO Status Register 11 */ + #define USBHSCORE_DTXFSTS11_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS11 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS11_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS11_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS11_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL12: Device Control IN Endpoint Control Register 12 */ + #define USBHSCORE_DIEPCTL12_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL12 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL12_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL12_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL12_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL12_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL12_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL12_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL12_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL12_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL12_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL12_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL12_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL12_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL12_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL12_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL12_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL12_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL12_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL12_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL12_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL12_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL12_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL12_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL12_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL12_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL12_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL12_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL12_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL12_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL12_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL12_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL12_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL12_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL12_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL12_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL12_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL12_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL12_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL12_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL12_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL12_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL12_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL12_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL12_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL12_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL12_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL12_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL12_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL12_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL12_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL12_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL12_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL12_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL12_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL12_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL12_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL12_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL12_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL12_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL12_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL12_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL12_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL12_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL12_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL12_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL12_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL12_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL12_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL12_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL12_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL12_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL12_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL12_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL12_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL12_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL12_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL12_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL12_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL12_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL12_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL12_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL12_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL12_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL12_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL12_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL12_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL12_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL12_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL12_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT12: Device IN Endpoint Interrupt Register 12 */ + #define USBHSCORE_DIEPINT12_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT12 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT12_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT12_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT12_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT12_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT12_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT12_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT12_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT12_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT12_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT12_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT12_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT12_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT12_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT12_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT12_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT12_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT12_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT12_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT12_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT12_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT12_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT12_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT12_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT12_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT12_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT12_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT12_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT12_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT12_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT12_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT12_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP + field.*/ + #define USBHSCORE_DIEPINT12_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT12_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT12_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT12_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT12_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT12_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT12_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT12_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT12_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT12_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT12_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT12_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT12_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT12_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT12_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT12_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT12_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT12_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT12_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT12_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT12_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT12_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT12_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT12_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT12_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT12_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT12_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT12_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN + field.*/ + #define USBHSCORE_DIEPINT12_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT12_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT12_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT12_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT12_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT12_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT12_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT12_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT12_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT12_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT12_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT12_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT12_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT12_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT12_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT12_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT12_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT12_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT12_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT12_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT12_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT12_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT12_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT12_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT12_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT12_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT12_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT12_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT12_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT12_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT12_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT12_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT12_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT12_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT12_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT12_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT12_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT12_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT12_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ12: Device IN Endpoint Transfer Size Register 12 */ + #define USBHSCORE_DIEPTSIZ12_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ12 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ12_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ12_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ12_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ12_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ12_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ12_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ12_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ12_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ12_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ12_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ12_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ12_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ12_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ12_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA12: Device IN Endpoint DMA Address Register 12 */ + #define USBHSCORE_DIEPDMA12_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA12 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA12_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA12_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA12_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS12: Device IN Endpoint Transmit FIFO Status Register 12 */ + #define USBHSCORE_DTXFSTS12_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS12 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS12_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS12_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS12_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL13: Device Control IN Endpoint Control Register 13 */ + #define USBHSCORE_DIEPCTL13_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL13 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL13_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL13_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL13_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL13_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL13_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL13_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL13_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL13_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL13_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL13_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL13_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL13_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL13_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL13_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL13_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL13_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL13_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL13_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL13_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL13_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL13_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL13_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL13_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL13_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL13_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL13_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL13_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL13_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL13_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL13_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL13_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL13_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL13_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL13_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL13_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL13_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL13_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL13_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL13_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL13_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL13_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL13_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL13_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL13_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL13_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL13_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL13_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL13_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL13_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL13_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL13_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL13_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL13_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL13_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL13_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL13_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL13_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL13_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL13_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL13_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL13_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL13_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL13_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL13_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL13_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL13_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL13_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL13_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL13_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL13_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL13_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL13_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL13_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL13_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL13_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL13_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL13_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL13_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL13_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL13_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL13_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL13_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL13_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL13_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL13_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL13_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL13_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL13_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT13: Device IN Endpoint Interrupt Register 13 */ + #define USBHSCORE_DIEPINT13_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT13 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT13_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT13_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT13_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT13_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT13_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT13_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT13_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT13_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT13_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT13_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT13_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT13_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT13_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT13_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT13_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT13_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT13_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT13_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT13_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT13_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT13_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT13_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT13_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT13_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT13_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT13_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT13_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT13_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT13_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT13_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT13_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP + field.*/ + #define USBHSCORE_DIEPINT13_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT13_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT13_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT13_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT13_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT13_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT13_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT13_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT13_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT13_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT13_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT13_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT13_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT13_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT13_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT13_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT13_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT13_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT13_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT13_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT13_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT13_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT13_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT13_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT13_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT13_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT13_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT13_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN + field.*/ + #define USBHSCORE_DIEPINT13_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT13_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT13_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT13_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT13_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT13_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT13_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT13_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT13_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT13_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT13_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT13_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT13_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT13_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT13_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT13_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT13_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT13_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT13_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT13_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT13_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT13_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT13_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT13_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT13_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT13_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT13_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT13_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT13_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT13_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT13_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT13_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT13_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT13_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT13_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT13_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT13_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT13_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT13_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ13: Device IN Endpoint Transfer Size Register 13 */ + #define USBHSCORE_DIEPTSIZ13_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ13 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ13_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ13_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ13_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ13_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ13_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ13_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ13_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ13_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ13_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ13_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ13_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ13_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ13_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ13_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA13: Device IN Endpoint DMA Address Register 13 */ + #define USBHSCORE_DIEPDMA13_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA13 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA13_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA13_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA13_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS13: Device IN Endpoint Transmit FIFO Status Register 13 */ + #define USBHSCORE_DTXFSTS13_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS13 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS13_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS13_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS13_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL14: Device Control IN Endpoint Control Register 14 */ + #define USBHSCORE_DIEPCTL14_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL14 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL14_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL14_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL14_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL14_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL14_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL14_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL14_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL14_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL14_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL14_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL14_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL14_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL14_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL14_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL14_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL14_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL14_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL14_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL14_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL14_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL14_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL14_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL14_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL14_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL14_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL14_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL14_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL14_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL14_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL14_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL14_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL14_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL14_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL14_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL14_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL14_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL14_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL14_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL14_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL14_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL14_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL14_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL14_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL14_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL14_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL14_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL14_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL14_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL14_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL14_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL14_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL14_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL14_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL14_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL14_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL14_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL14_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL14_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL14_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL14_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL14_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL14_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL14_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL14_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL14_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL14_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL14_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL14_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL14_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL14_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL14_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL14_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL14_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL14_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL14_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL14_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL14_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL14_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL14_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL14_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL14_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL14_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL14_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL14_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL14_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL14_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL14_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL14_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT14: Device IN Endpoint Interrupt Register 14 */ + #define USBHSCORE_DIEPINT14_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT14 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT14_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT14_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT14_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT14_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT14_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT14_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT14_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT14_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT14_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT14_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT14_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT14_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT14_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT14_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT14_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT14_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT14_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT14_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT14_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT14_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT14_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT14_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT14_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT14_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT14_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT14_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT14_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT14_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT14_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT14_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT14_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP + field.*/ + #define USBHSCORE_DIEPINT14_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT14_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT14_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT14_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT14_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT14_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT14_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT14_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT14_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT14_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT14_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT14_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT14_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT14_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT14_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT14_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT14_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT14_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT14_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT14_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT14_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT14_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT14_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT14_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT14_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT14_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT14_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT14_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN + field.*/ + #define USBHSCORE_DIEPINT14_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT14_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT14_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT14_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT14_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT14_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT14_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT14_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT14_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT14_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT14_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT14_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT14_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT14_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT14_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT14_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT14_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT14_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT14_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT14_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT14_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT14_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT14_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT14_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT14_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT14_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT14_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT14_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT14_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT14_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT14_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT14_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT14_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT14_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT14_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT14_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT14_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT14_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT14_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ14: Device IN Endpoint Transfer Size Register 14 */ + #define USBHSCORE_DIEPTSIZ14_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ14 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ14_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ14_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ14_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ14_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ14_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ14_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ14_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ14_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ14_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ14_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ14_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ14_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ14_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ14_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA14: Device IN Endpoint DMA Address Register 14 */ + #define USBHSCORE_DIEPDMA14_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA14 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA14_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA14_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA14_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS14: Device IN Endpoint Transmit FIFO Status Register 14 */ + #define USBHSCORE_DTXFSTS14_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS14 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS14_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS14_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS14_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL15: Device Control IN Endpoint Control Register 15 */ + #define USBHSCORE_DIEPCTL15_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL15 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL15_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL15_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL15_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL15_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL15_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL15_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL15_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL15_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL15_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL15_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL15_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL15_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL15_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL15_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL15_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL15_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL15_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL15_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL15_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL15_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL15_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL15_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL15_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL15_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL15_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL15_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL15_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL15_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL15_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL15_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL15_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL15_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL15_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL15_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL15_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL15_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL15_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL15_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL15_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL15_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL15_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL15_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL15_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL15_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL15_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL15_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL15_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL15_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL15_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL15_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL15_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL15_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL15_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL15_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL15_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL15_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL15_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL15_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL15_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL15_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL15_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL15_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL15_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL15_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL15_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL15_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL15_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL15_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL15_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL15_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL15_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL15_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL15_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL15_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL15_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL15_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL15_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL15_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL15_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL15_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL15_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL15_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL15_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL15_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL15_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL15_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL15_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL15_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT15: Device IN Endpoint Interrupt Register 15 */ + #define USBHSCORE_DIEPINT15_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT15 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT15_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT15_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT15_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT15_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT15_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT15_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT15_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT15_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT15_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT15_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT15_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT15_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT15_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT15_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT15_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT15_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT15_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT15_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT15_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT15_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT15_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT15_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT15_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT15_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT15_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT15_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT15_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT15_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT15_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT15_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT15_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP + field.*/ + #define USBHSCORE_DIEPINT15_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT15_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT15_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT15_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT15_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT15_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT15_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT15_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT15_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT15_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT15_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT15_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT15_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT15_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT15_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT15_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT15_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT15_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT15_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT15_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT15_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT15_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT15_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT15_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT15_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT15_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT15_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT15_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN + field.*/ + #define USBHSCORE_DIEPINT15_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT15_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT15_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT15_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT15_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT15_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT15_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT15_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT15_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT15_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT15_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT15_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT15_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT15_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT15_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT15_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT15_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT15_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT15_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT15_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT15_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT15_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT15_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT15_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT15_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT15_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT15_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT15_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT15_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT15_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT15_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT15_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT15_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT15_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT15_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT15_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT15_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT15_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT15_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ15: Device IN Endpoint Transfer Size Register 15 */ + #define USBHSCORE_DIEPTSIZ15_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ15 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ15_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ15_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ15_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ15_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ15_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ15_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ15_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ15_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ15_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ15_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ15_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ15_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ15_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ15_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA15: Device IN Endpoint DMA Address Register 15 */ + #define USBHSCORE_DIEPDMA15_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA15 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA15_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA15_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA15_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS15: Device IN Endpoint Transmit FIFO Status Register 15 */ + #define USBHSCORE_DTXFSTS15_ResetValue (0x00000C00UL) /*!< Reset value of DTXFSTS15 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS15_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS15_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS15_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DOEPCTL0: Device Control OUT Endpoint 0 Control Register */ + #define USBHSCORE_DOEPCTL0_ResetValue (0x00008000UL) /*!< Reset value of DOEPCTL0 register. */ + +/* MPS @Bits 0..1 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL0_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL0_MPS_Msk (0x3UL << USBHSCORE_DOEPCTL0_MPS_Pos) /*!< Bit mask of MPS field. */ + #define USBHSCORE_DOEPCTL0_MPS_Min (0x0UL) /*!< Min enumerator value of MPS field. */ + #define USBHSCORE_DOEPCTL0_MPS_Max (0x3UL) /*!< Max enumerator value of MPS field. */ + #define USBHSCORE_DOEPCTL0_MPS_BYTE64 (0x0UL) /*!< 64 bytes */ + #define USBHSCORE_DOEPCTL0_MPS_BYTE32 (0x1UL) /*!< 32 bytes */ + #define USBHSCORE_DOEPCTL0_MPS_BYTE16 (0x2UL) /*!< 16 bytes */ + #define USBHSCORE_DOEPCTL0_MPS_BYTE8 (0x3UL) /*!< 8 bytes */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL0_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL0_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL0_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL0_USBACTEP_Min (0x1UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL0_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL0_USBACTEP_ACTIVE (0x1UL) /*!< USB Active Endpoint 0 */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL0_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL0_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL0_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL0_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL0_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL0_NAKSTS_INACTIVE (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL0_NAKSTS_ACTIVE (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL0_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL0_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL0_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL0_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL0_EPTYPE_Max (0x0UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL0_EPTYPE_ACTIVE (0x0UL) /*!< Endpoint Control 0 */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL0_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL0_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL0_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL0_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL0_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL0_STALL_INACTIVE (0x0UL) /*!< No Stall */ + #define USBHSCORE_DOEPCTL0_STALL_ACTIVE (0x1UL) /*!< Stall Handshake */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DOEPCTL0_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL0_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL0_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL0_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL0_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL0_CNAK_NOCLEAR (0x0UL) /*!< No action */ + #define USBHSCORE_DOEPCTL0_CNAK_CLEAR (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL0_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL0_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL0_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL0_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL0_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL0_SNAK_NOSET (0x0UL) /*!< No action */ + #define USBHSCORE_DOEPCTL0_SNAK_SET (0x1UL) /*!< Set NAK */ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL0_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL0_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL0_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL0_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL0_EPDIS_Max (0x0UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL0_EPDIS_INACTIVE (0x0UL) /*!< No Endpoint disable */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL0_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL0_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL0_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL0_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL0_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL0_EPENA_INACTIVE (0x0UL) /*!< No action */ + #define USBHSCORE_DOEPCTL0_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT0: Device OUT Endpoint 0 Interrupt Register */ + #define USBHSCORE_DOEPINT0_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT0 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT0_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT0_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT0_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT0_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT0_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT0_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT0_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT0_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT0_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT0_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT0_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT0_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT0_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT0_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT0_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT0_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT0_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT0_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT0_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT0_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT0_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT0_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT0_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT0_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT0_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT0_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT0_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT0_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT0_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT0_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT0_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT0_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT0_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT0_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT0_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT0_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT0_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT0_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT0_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT0_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT0_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT0_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT0_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT0_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ0: Device OUT Endpoint 0 Transfer Size Register */ + #define USBHSCORE_DOEPTSIZ0_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ0 register. */ + +/* XFERSIZE @Bits 0..6 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ0_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ0_XFERSIZE_Msk (0x7FUL << USBHSCORE_DOEPTSIZ0_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bit 19 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ0_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ0_PKTCNT_Msk (0x1UL << USBHSCORE_DOEPTSIZ0_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* SUPCNT @Bits 29..30 : SETUP Packet Count (SUPCnt) */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_Pos (29UL) /*!< Position of SUPCNT field. */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_Msk (0x3UL << USBHSCORE_DOEPTSIZ0_SUPCNT_Pos) /*!< Bit mask of SUPCNT field. */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_Min (0x1UL) /*!< Min enumerator value of SUPCNT field. */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_Max (0x3UL) /*!< Max enumerator value of SUPCNT field. */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_ONEPACKET (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_TWOPACKET (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_THREEPACKET (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DOEPDMA0: Device OUT Endpoint 0 DMA Address Register */ + #define USBHSCORE_DOEPDMA0_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA0 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA0_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA0_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA0_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL1: Device Control OUT Endpoint Control Register 1 */ + #define USBHSCORE_DOEPCTL1_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL1 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL1_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL1_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL1_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL1_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL1_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL1_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL1_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL1_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL1_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL1_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL1_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL1_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL1_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL1_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL1_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL1_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL1_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL1_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL1_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL1_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL1_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL1_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL1_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL1_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL1_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL1_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL1_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL1_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL1_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL1_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL1_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL1_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL1_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL1_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL1_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL1_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL1_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL1_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL1_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL1_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL1_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL1_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL1_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL1_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL1_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL1_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL1_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL1_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL1_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL1_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL1_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL1_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL1_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL1_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL1_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL1_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL1_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL1_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL1_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL1_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL1_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL1_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL1_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL1_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL1_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL1_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL1_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL1_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL1_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL1_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL1_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL1_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL1_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL1_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL1_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL1_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL1_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL1_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL1_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL1_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL1_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL1_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT1: Device OUT Endpoint Interrupt Register 1 */ + #define USBHSCORE_DOEPINT1_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT1 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT1_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT1_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT1_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT1_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT1_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT1_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT1_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT1_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT1_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT1_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT1_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT1_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT1_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT1_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT1_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT1_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT1_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT1_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT1_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT1_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT1_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT1_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT1_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT1_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT1_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT1_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT1_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT1_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT1_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT1_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT1_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT1_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT1_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT1_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT1_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT1_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT1_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT1_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT1_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT1_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT1_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT1_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT1_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT1_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ1: Device OUT Endpoint Transfer Size Register 1 */ + #define USBHSCORE_DOEPTSIZ1_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ1 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ1_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ1_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ1_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ1_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ1_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ1_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ1_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA1: Device OUT Endpoint DMA Address Register 1 */ + #define USBHSCORE_DOEPDMA1_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA1 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA1_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA1_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA1_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL2: Device Control OUT Endpoint Control Register 2 */ + #define USBHSCORE_DOEPCTL2_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL2 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL2_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL2_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL2_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL2_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL2_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL2_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL2_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL2_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL2_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL2_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL2_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL2_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL2_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL2_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL2_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL2_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL2_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL2_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL2_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL2_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL2_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL2_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL2_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL2_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL2_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL2_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL2_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL2_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL2_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL2_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL2_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL2_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL2_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL2_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL2_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL2_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL2_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL2_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL2_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL2_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL2_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL2_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL2_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL2_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL2_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL2_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL2_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL2_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL2_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL2_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL2_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL2_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL2_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL2_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL2_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL2_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL2_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL2_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL2_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL2_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL2_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL2_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL2_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL2_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL2_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL2_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL2_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL2_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL2_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL2_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL2_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL2_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL2_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL2_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL2_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL2_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL2_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL2_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL2_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL2_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL2_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL2_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT2: Device OUT Endpoint Interrupt Register 2 */ + #define USBHSCORE_DOEPINT2_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT2 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT2_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT2_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT2_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT2_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT2_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT2_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT2_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT2_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT2_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT2_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT2_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT2_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT2_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT2_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT2_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT2_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT2_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT2_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT2_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT2_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT2_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT2_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT2_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT2_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT2_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT2_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT2_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT2_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT2_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT2_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT2_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT2_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT2_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT2_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT2_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT2_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT2_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT2_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT2_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT2_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT2_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT2_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT2_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT2_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ2: Device OUT Endpoint Transfer Size Register 2 */ + #define USBHSCORE_DOEPTSIZ2_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ2 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ2_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ2_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ2_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ2_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ2_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ2_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ2_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA2: Device OUT Endpoint DMA Address Register 2 */ + #define USBHSCORE_DOEPDMA2_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA2 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA2_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA2_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA2_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL3: Device Control OUT Endpoint Control Register 3 */ + #define USBHSCORE_DOEPCTL3_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL3 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL3_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL3_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL3_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL3_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL3_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL3_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL3_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL3_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL3_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL3_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL3_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL3_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL3_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL3_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL3_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL3_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL3_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL3_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL3_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL3_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL3_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL3_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL3_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL3_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL3_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL3_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL3_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL3_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL3_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL3_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL3_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL3_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL3_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL3_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL3_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL3_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL3_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL3_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL3_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL3_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL3_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL3_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL3_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL3_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL3_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL3_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL3_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL3_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL3_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL3_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL3_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL3_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL3_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL3_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL3_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL3_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL3_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL3_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL3_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL3_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL3_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL3_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL3_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL3_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL3_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL3_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL3_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL3_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL3_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL3_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL3_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL3_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL3_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL3_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL3_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL3_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL3_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL3_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL3_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL3_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL3_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL3_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT3: Device OUT Endpoint Interrupt Register 3 */ + #define USBHSCORE_DOEPINT3_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT3 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT3_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT3_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT3_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT3_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT3_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT3_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT3_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT3_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT3_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT3_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT3_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT3_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT3_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT3_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT3_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT3_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT3_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT3_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT3_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT3_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT3_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT3_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT3_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT3_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT3_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT3_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT3_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT3_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT3_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT3_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT3_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT3_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT3_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT3_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT3_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT3_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT3_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT3_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT3_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT3_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT3_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT3_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT3_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT3_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ3: Device OUT Endpoint Transfer Size Register 3 */ + #define USBHSCORE_DOEPTSIZ3_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ3 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ3_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ3_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ3_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ3_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ3_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ3_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ3_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA3: Device OUT Endpoint DMA Address Register 3 */ + #define USBHSCORE_DOEPDMA3_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA3 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA3_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA3_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA3_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL4: Device Control OUT Endpoint Control Register 4 */ + #define USBHSCORE_DOEPCTL4_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL4 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL4_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL4_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL4_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL4_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL4_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL4_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL4_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL4_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL4_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL4_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL4_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL4_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL4_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL4_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL4_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL4_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL4_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL4_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL4_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL4_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL4_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL4_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL4_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL4_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL4_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL4_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL4_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL4_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL4_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL4_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL4_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL4_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL4_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL4_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL4_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL4_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL4_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL4_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL4_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL4_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL4_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL4_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL4_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL4_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL4_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL4_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL4_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL4_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL4_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL4_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL4_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL4_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL4_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL4_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL4_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL4_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL4_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL4_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL4_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL4_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL4_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL4_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL4_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL4_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL4_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL4_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL4_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL4_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL4_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL4_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL4_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL4_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL4_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL4_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL4_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL4_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL4_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL4_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL4_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL4_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL4_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL4_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT4: Device OUT Endpoint Interrupt Register 4 */ + #define USBHSCORE_DOEPINT4_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT4 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT4_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT4_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT4_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT4_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT4_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT4_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT4_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT4_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT4_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT4_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT4_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT4_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT4_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT4_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT4_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT4_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT4_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT4_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT4_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT4_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT4_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT4_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT4_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT4_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT4_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT4_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT4_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT4_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT4_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT4_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT4_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT4_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT4_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT4_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT4_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT4_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT4_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT4_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT4_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT4_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT4_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT4_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT4_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT4_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ4: Device OUT Endpoint Transfer Size Register 4 */ + #define USBHSCORE_DOEPTSIZ4_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ4 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ4_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ4_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ4_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ4_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ4_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ4_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ4_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA4: Device OUT Endpoint DMA Address Register 4 */ + #define USBHSCORE_DOEPDMA4_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA4 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA4_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA4_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA4_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL5: Device Control OUT Endpoint Control Register 5 */ + #define USBHSCORE_DOEPCTL5_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL5 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL5_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL5_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL5_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL5_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL5_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL5_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL5_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL5_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL5_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL5_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL5_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL5_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL5_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL5_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL5_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL5_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL5_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL5_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL5_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL5_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL5_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL5_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL5_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL5_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL5_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL5_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL5_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL5_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL5_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL5_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL5_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL5_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL5_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL5_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL5_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL5_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL5_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL5_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL5_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL5_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL5_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL5_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL5_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL5_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL5_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL5_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL5_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL5_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL5_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL5_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL5_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL5_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL5_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL5_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL5_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL5_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL5_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL5_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL5_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL5_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL5_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL5_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL5_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL5_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL5_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL5_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL5_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL5_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL5_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL5_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL5_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL5_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL5_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL5_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL5_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL5_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL5_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL5_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL5_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL5_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL5_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL5_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT5: Device OUT Endpoint Interrupt Register 5 */ + #define USBHSCORE_DOEPINT5_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT5 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT5_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT5_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT5_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT5_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT5_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT5_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT5_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT5_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT5_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT5_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT5_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT5_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT5_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT5_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT5_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT5_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT5_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT5_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT5_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT5_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT5_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT5_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT5_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT5_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT5_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT5_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT5_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT5_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT5_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT5_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT5_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT5_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT5_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT5_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT5_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT5_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT5_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT5_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT5_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT5_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT5_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT5_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT5_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT5_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ5: Device OUT Endpoint Transfer Size Register 5 */ + #define USBHSCORE_DOEPTSIZ5_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ5 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ5_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ5_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ5_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ5_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ5_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ5_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ5_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA5: Device OUT Endpoint DMA Address Register 5 */ + #define USBHSCORE_DOEPDMA5_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA5 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA5_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA5_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA5_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL6: Device Control OUT Endpoint Control Register 6 */ + #define USBHSCORE_DOEPCTL6_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL6 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL6_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL6_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL6_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL6_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL6_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL6_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL6_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL6_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL6_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL6_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL6_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL6_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL6_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL6_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL6_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL6_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL6_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL6_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL6_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL6_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL6_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL6_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL6_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL6_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL6_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL6_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL6_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL6_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL6_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL6_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL6_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL6_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL6_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL6_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL6_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL6_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL6_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL6_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL6_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL6_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL6_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL6_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL6_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL6_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL6_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL6_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL6_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL6_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL6_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL6_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL6_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL6_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL6_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL6_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL6_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL6_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL6_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL6_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL6_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL6_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL6_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL6_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL6_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL6_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL6_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL6_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL6_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL6_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL6_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL6_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL6_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL6_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL6_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL6_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL6_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL6_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL6_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL6_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL6_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL6_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL6_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL6_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT6: Device OUT Endpoint Interrupt Register 6 */ + #define USBHSCORE_DOEPINT6_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT6 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT6_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT6_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT6_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT6_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT6_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT6_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT6_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT6_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT6_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT6_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT6_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT6_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT6_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT6_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT6_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT6_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT6_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT6_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT6_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT6_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT6_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT6_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT6_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT6_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT6_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT6_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT6_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT6_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT6_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT6_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT6_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT6_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT6_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT6_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT6_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT6_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT6_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT6_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT6_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT6_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT6_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT6_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT6_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT6_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT6_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT6_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT6_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT6_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT6_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT6_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT6_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT6_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT6_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT6_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT6_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT6_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT6_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT6_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT6_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT6_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT6_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT6_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT6_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT6_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT6_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT6_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT6_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT6_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT6_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT6_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT6_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT6_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT6_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT6_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT6_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT6_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT6_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT6_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT6_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT6_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT6_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT6_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT6_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT6_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT6_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT6_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT6_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT6_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT6_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT6_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT6_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT6_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT6_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT6_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT6_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT6_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT6_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT6_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ6: Device OUT Endpoint Transfer Size Register 6 */ + #define USBHSCORE_DOEPTSIZ6_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ6 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ6_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ6_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ6_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ6_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ6_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ6_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ6_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ6_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ6_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ6_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ6_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ6_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ6_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ6_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ6_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA6: Device OUT Endpoint DMA Address Register 6 */ + #define USBHSCORE_DOEPDMA6_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA6 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA6_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA6_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA6_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL7: Device Control OUT Endpoint Control Register 7 */ + #define USBHSCORE_DOEPCTL7_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL7 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL7_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL7_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL7_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL7_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL7_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL7_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL7_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL7_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL7_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL7_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL7_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL7_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL7_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL7_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL7_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL7_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL7_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL7_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL7_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL7_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL7_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL7_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL7_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL7_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL7_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL7_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL7_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL7_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL7_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL7_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL7_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL7_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL7_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL7_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL7_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL7_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL7_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL7_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL7_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL7_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL7_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL7_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL7_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL7_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL7_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL7_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL7_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL7_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL7_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL7_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL7_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL7_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL7_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL7_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL7_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL7_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL7_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL7_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL7_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL7_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL7_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL7_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL7_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL7_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL7_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL7_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL7_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL7_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL7_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL7_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL7_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL7_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL7_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL7_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL7_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL7_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL7_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL7_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL7_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL7_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL7_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL7_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT7: Device OUT Endpoint Interrupt Register 7 */ + #define USBHSCORE_DOEPINT7_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT7 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT7_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT7_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT7_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT7_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT7_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT7_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT7_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT7_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT7_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT7_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT7_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT7_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT7_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT7_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT7_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT7_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT7_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT7_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT7_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT7_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT7_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT7_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT7_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT7_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT7_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT7_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT7_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT7_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT7_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT7_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT7_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT7_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT7_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT7_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT7_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT7_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT7_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT7_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT7_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT7_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT7_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT7_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT7_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT7_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT7_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT7_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT7_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT7_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT7_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT7_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT7_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT7_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT7_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT7_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT7_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT7_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT7_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT7_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT7_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT7_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT7_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT7_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT7_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT7_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT7_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT7_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT7_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT7_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT7_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT7_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT7_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT7_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT7_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT7_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT7_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT7_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT7_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT7_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT7_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT7_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT7_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT7_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT7_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT7_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT7_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT7_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT7_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT7_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT7_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT7_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT7_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT7_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT7_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT7_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT7_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT7_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT7_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT7_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ7: Device OUT Endpoint Transfer Size Register 7 */ + #define USBHSCORE_DOEPTSIZ7_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ7 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ7_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ7_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ7_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ7_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ7_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ7_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ7_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ7_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ7_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ7_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ7_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ7_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ7_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ7_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ7_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA7: Device OUT Endpoint DMA Address Register 7 */ + #define USBHSCORE_DOEPDMA7_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA7 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA7_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA7_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA7_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL8: Device Control OUT Endpoint Control Register 8 */ + #define USBHSCORE_DOEPCTL8_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL8 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL8_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL8_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL8_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL8_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL8_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL8_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL8_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL8_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL8_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL8_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL8_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL8_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL8_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL8_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL8_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL8_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL8_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL8_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL8_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL8_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL8_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL8_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL8_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL8_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL8_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL8_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL8_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL8_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL8_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL8_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL8_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL8_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL8_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL8_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL8_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL8_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL8_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL8_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL8_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL8_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL8_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL8_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL8_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL8_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL8_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL8_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL8_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL8_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL8_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL8_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL8_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL8_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL8_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL8_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL8_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL8_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL8_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL8_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL8_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL8_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL8_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL8_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL8_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL8_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL8_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL8_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL8_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL8_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL8_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL8_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL8_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL8_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL8_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL8_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL8_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL8_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL8_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL8_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL8_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL8_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL8_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL8_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT8: Device OUT Endpoint Interrupt Register 8 */ + #define USBHSCORE_DOEPINT8_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT8 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT8_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT8_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT8_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT8_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT8_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT8_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT8_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT8_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT8_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT8_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT8_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT8_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT8_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT8_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT8_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT8_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT8_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT8_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT8_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT8_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT8_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT8_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT8_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT8_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT8_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT8_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT8_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT8_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT8_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT8_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT8_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT8_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT8_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT8_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT8_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT8_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT8_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT8_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT8_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT8_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT8_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT8_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT8_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT8_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT8_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT8_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT8_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT8_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT8_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT8_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT8_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT8_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT8_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT8_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT8_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT8_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT8_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT8_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT8_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT8_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT8_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT8_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT8_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT8_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT8_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT8_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT8_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT8_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT8_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT8_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT8_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT8_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT8_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT8_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT8_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT8_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT8_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT8_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT8_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT8_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT8_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT8_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT8_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT8_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT8_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT8_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT8_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT8_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT8_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT8_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT8_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT8_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT8_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT8_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT8_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT8_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT8_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT8_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ8: Device OUT Endpoint Transfer Size Register 8 */ + #define USBHSCORE_DOEPTSIZ8_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ8 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ8_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ8_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ8_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ8_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ8_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ8_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ8_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ8_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ8_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ8_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ8_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ8_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ8_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ8_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ8_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA8: Device OUT Endpoint DMA Address Register 8 */ + #define USBHSCORE_DOEPDMA8_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA8 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA8_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA8_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA8_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL9: Device Control OUT Endpoint Control Register 9 */ + #define USBHSCORE_DOEPCTL9_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL9 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL9_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL9_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL9_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL9_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL9_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL9_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL9_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL9_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL9_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL9_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL9_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL9_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL9_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL9_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL9_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL9_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL9_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL9_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL9_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL9_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL9_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL9_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL9_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL9_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL9_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL9_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL9_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL9_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL9_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL9_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL9_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL9_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL9_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL9_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL9_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL9_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL9_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL9_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL9_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL9_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL9_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL9_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL9_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL9_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL9_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL9_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL9_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL9_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL9_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL9_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL9_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL9_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL9_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL9_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL9_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL9_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL9_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL9_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL9_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL9_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL9_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL9_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL9_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL9_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL9_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL9_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL9_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL9_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL9_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL9_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL9_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL9_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL9_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL9_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL9_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL9_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL9_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL9_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL9_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL9_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL9_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL9_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT9: Device OUT Endpoint Interrupt Register 9 */ + #define USBHSCORE_DOEPINT9_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT9 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT9_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT9_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT9_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT9_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT9_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT9_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT9_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT9_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT9_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT9_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT9_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT9_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT9_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT9_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT9_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT9_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT9_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT9_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT9_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT9_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT9_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT9_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT9_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT9_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT9_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT9_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT9_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT9_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT9_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT9_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT9_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT9_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT9_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT9_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT9_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT9_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT9_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT9_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT9_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT9_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT9_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT9_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT9_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT9_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT9_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT9_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT9_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT9_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT9_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT9_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT9_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT9_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT9_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT9_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT9_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT9_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT9_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT9_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT9_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT9_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT9_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT9_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT9_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT9_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT9_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT9_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT9_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT9_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT9_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT9_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT9_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT9_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT9_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT9_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT9_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT9_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT9_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT9_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT9_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT9_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT9_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT9_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT9_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT9_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT9_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT9_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT9_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT9_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT9_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT9_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT9_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT9_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT9_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT9_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT9_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT9_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT9_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT9_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ9: Device OUT Endpoint Transfer Size Register 9 */ + #define USBHSCORE_DOEPTSIZ9_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ9 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ9_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ9_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ9_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ9_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ9_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ9_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ9_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ9_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ9_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ9_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ9_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ9_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ9_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ9_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ9_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA9: Device OUT Endpoint DMA Address Register 9 */ + #define USBHSCORE_DOEPDMA9_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA9 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA9_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA9_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA9_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL10: Device Control OUT Endpoint Control Register 10 */ + #define USBHSCORE_DOEPCTL10_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL10 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL10_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL10_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL10_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL10_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL10_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL10_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL10_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL10_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL10_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL10_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL10_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL10_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL10_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL10_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL10_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL10_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL10_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL10_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL10_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL10_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL10_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL10_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL10_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL10_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL10_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL10_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL10_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL10_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL10_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL10_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL10_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL10_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL10_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL10_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL10_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL10_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL10_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL10_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL10_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL10_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL10_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL10_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL10_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL10_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL10_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL10_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL10_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL10_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL10_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL10_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL10_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL10_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL10_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL10_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL10_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL10_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL10_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL10_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL10_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL10_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL10_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL10_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL10_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL10_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL10_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL10_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL10_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL10_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL10_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL10_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL10_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL10_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL10_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL10_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL10_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL10_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL10_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL10_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL10_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL10_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL10_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL10_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT10: Device OUT Endpoint Interrupt Register 10 */ + #define USBHSCORE_DOEPINT10_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT10 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT10_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT10_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT10_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT10_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT10_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT10_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT10_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT10_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT10_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT10_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT10_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT10_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT10_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT10_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT10_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT10_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT10_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT10_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT10_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT10_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT10_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT10_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT10_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT10_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT10_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT10_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT10_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT10_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT10_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT10_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT10_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS + field.*/ + #define USBHSCORE_DOEPINT10_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT10_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT10_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT10_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT10_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT10_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT10_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD + field.*/ + #define USBHSCORE_DOEPINT10_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT10_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT10_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT10_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT10_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT10_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT10_BACK2BACKSETUP_Pos) /*!< Bit mask of + BACK2BACKSETUP field.*/ + #define USBHSCORE_DOEPINT10_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT10_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT10_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT10_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT10_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT10_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT10_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT10_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT10_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT10_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT10_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT10_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT10_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT10_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT10_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT10_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT10_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT10_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT10_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT10_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT10_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT10_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT10_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT10_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT10_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT10_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT10_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT10_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT10_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT10_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT10_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT10_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT10_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT10_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT10_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT10_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT10_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT10_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT10_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT10_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT10_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT10_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT10_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT10_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT10_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT10_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT10_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT10_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT10_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD + field.*/ + #define USBHSCORE_DOEPINT10_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT10_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT10_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT10_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ10: Device OUT Endpoint Transfer Size Register 10 */ + #define USBHSCORE_DOEPTSIZ10_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ10 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ10_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ10_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ10_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ10_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ10_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ10_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ10_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ10_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ10_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ10_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ10_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ10_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ10_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ10_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ10_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA10: Device OUT Endpoint DMA Address Register 10 */ + #define USBHSCORE_DOEPDMA10_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA10 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA10_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA10_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA10_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL11: Device Control OUT Endpoint Control Register 11 */ + #define USBHSCORE_DOEPCTL11_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL11 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL11_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL11_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL11_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL11_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL11_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL11_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL11_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL11_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL11_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL11_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL11_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL11_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL11_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL11_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL11_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL11_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL11_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL11_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL11_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL11_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL11_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL11_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL11_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL11_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL11_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL11_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL11_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL11_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL11_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL11_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL11_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL11_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL11_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL11_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL11_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL11_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL11_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL11_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL11_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL11_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL11_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL11_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL11_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL11_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL11_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL11_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL11_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL11_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL11_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL11_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL11_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL11_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL11_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL11_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL11_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL11_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL11_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL11_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL11_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL11_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL11_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL11_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL11_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL11_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL11_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL11_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL11_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL11_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL11_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL11_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL11_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL11_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL11_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL11_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL11_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL11_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL11_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL11_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL11_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL11_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL11_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL11_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT11: Device OUT Endpoint Interrupt Register 11 */ + #define USBHSCORE_DOEPINT11_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT11 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT11_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT11_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT11_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT11_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT11_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT11_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT11_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT11_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT11_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT11_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT11_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT11_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT11_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT11_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT11_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT11_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT11_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT11_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT11_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT11_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT11_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT11_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT11_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT11_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT11_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT11_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT11_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT11_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT11_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT11_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT11_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS + field.*/ + #define USBHSCORE_DOEPINT11_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT11_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT11_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT11_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT11_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT11_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT11_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD + field.*/ + #define USBHSCORE_DOEPINT11_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT11_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT11_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT11_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT11_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT11_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT11_BACK2BACKSETUP_Pos) /*!< Bit mask of + BACK2BACKSETUP field.*/ + #define USBHSCORE_DOEPINT11_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT11_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT11_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT11_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT11_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT11_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT11_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT11_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT11_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT11_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT11_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT11_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT11_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT11_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT11_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT11_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT11_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT11_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT11_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT11_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT11_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT11_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT11_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT11_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT11_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT11_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT11_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT11_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT11_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT11_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT11_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT11_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT11_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT11_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT11_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT11_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT11_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT11_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT11_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT11_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT11_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT11_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT11_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT11_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT11_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT11_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT11_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT11_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT11_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD + field.*/ + #define USBHSCORE_DOEPINT11_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT11_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT11_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT11_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ11: Device OUT Endpoint Transfer Size Register 11 */ + #define USBHSCORE_DOEPTSIZ11_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ11 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ11_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ11_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ11_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ11_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ11_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ11_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ11_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ11_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ11_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ11_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ11_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ11_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ11_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ11_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ11_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA11: Device OUT Endpoint DMA Address Register 11 */ + #define USBHSCORE_DOEPDMA11_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA11 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA11_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA11_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA11_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL12: Device Control OUT Endpoint Control Register 12 */ + #define USBHSCORE_DOEPCTL12_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL12 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL12_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL12_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL12_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL12_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL12_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL12_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL12_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL12_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL12_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL12_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL12_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL12_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL12_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL12_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL12_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL12_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL12_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL12_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL12_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL12_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL12_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL12_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL12_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL12_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL12_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL12_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL12_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL12_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL12_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL12_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL12_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL12_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL12_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL12_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL12_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL12_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL12_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL12_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL12_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL12_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL12_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL12_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL12_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL12_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL12_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL12_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL12_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL12_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL12_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL12_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL12_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL12_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL12_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL12_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL12_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL12_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL12_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL12_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL12_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL12_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL12_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL12_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL12_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL12_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL12_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL12_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL12_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL12_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL12_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL12_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL12_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL12_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL12_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL12_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL12_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL12_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL12_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL12_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL12_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL12_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL12_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL12_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT12: Device OUT Endpoint Interrupt Register 12 */ + #define USBHSCORE_DOEPINT12_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT12 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT12_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT12_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT12_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT12_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT12_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT12_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT12_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT12_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT12_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT12_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT12_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT12_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT12_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT12_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT12_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT12_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT12_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT12_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT12_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT12_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT12_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT12_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT12_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS + field.*/ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT12_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD + field.*/ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT12_BACK2BACKSETUP_Pos) /*!< Bit mask of + BACK2BACKSETUP field.*/ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT12_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT12_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT12_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT12_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT12_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT12_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT12_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT12_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT12_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT12_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT12_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT12_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT12_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT12_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT12_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT12_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT12_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT12_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT12_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD + field.*/ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ12: Device OUT Endpoint Transfer Size Register 12 */ + #define USBHSCORE_DOEPTSIZ12_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ12 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ12_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ12_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ12_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ12_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ12_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ12_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ12_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA12: Device OUT Endpoint DMA Address Register 12 */ + #define USBHSCORE_DOEPDMA12_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA12 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA12_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA12_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA12_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL13: Device Control OUT Endpoint Control Register 13 */ + #define USBHSCORE_DOEPCTL13_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL13 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL13_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL13_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL13_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL13_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL13_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL13_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL13_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL13_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL13_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL13_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL13_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL13_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL13_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL13_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL13_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL13_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL13_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL13_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL13_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL13_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL13_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL13_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL13_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL13_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL13_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL13_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL13_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL13_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL13_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL13_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL13_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL13_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL13_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL13_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL13_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL13_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL13_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL13_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL13_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL13_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL13_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL13_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL13_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL13_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL13_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL13_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL13_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL13_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL13_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL13_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL13_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL13_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL13_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL13_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL13_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL13_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL13_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL13_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL13_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL13_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL13_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL13_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL13_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL13_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL13_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL13_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL13_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL13_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL13_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL13_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL13_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL13_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL13_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL13_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL13_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL13_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL13_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL13_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL13_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL13_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL13_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL13_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT13: Device OUT Endpoint Interrupt Register 13 */ + #define USBHSCORE_DOEPINT13_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT13 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT13_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT13_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT13_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT13_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT13_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT13_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT13_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT13_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT13_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT13_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT13_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT13_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT13_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT13_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT13_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT13_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT13_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT13_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT13_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT13_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT13_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT13_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT13_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS + field.*/ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT13_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD + field.*/ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT13_BACK2BACKSETUP_Pos) /*!< Bit mask of + BACK2BACKSETUP field.*/ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT13_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT13_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT13_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT13_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT13_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT13_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT13_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT13_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT13_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT13_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT13_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT13_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT13_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT13_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT13_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT13_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT13_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT13_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT13_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD + field.*/ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ13: Device OUT Endpoint Transfer Size Register 13 */ + #define USBHSCORE_DOEPTSIZ13_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ13 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ13_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ13_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ13_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ13_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ13_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ13_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ13_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA13: Device OUT Endpoint DMA Address Register 13 */ + #define USBHSCORE_DOEPDMA13_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA13 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA13_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA13_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA13_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL14: Device Control OUT Endpoint Control Register 14 */ + #define USBHSCORE_DOEPCTL14_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL14 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL14_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL14_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL14_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL14_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL14_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL14_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL14_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL14_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL14_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL14_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL14_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL14_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL14_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL14_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL14_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL14_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL14_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL14_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL14_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL14_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL14_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL14_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL14_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL14_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL14_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL14_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL14_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL14_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL14_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL14_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL14_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL14_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL14_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL14_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL14_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL14_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL14_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL14_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL14_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL14_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL14_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL14_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL14_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL14_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL14_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL14_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL14_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL14_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL14_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL14_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL14_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL14_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL14_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL14_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL14_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL14_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL14_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL14_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL14_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL14_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL14_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL14_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL14_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL14_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL14_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL14_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL14_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL14_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL14_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL14_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL14_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL14_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL14_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL14_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL14_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL14_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL14_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL14_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL14_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL14_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL14_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL14_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT14: Device OUT Endpoint Interrupt Register 14 */ + #define USBHSCORE_DOEPINT14_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT14 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT14_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT14_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT14_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT14_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT14_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT14_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT14_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT14_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT14_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT14_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT14_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT14_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT14_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT14_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT14_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT14_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT14_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT14_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT14_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT14_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT14_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT14_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT14_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS + field.*/ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT14_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD + field.*/ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT14_BACK2BACKSETUP_Pos) /*!< Bit mask of + BACK2BACKSETUP field.*/ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT14_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT14_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT14_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT14_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT14_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT14_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT14_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT14_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT14_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT14_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT14_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT14_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT14_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT14_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT14_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT14_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT14_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT14_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT14_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD + field.*/ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ14: Device OUT Endpoint Transfer Size Register 14 */ + #define USBHSCORE_DOEPTSIZ14_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ14 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ14_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ14_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ14_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ14_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ14_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ14_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ14_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA14: Device OUT Endpoint DMA Address Register 14 */ + #define USBHSCORE_DOEPDMA14_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA14 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA14_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA14_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA14_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL15: Device Control OUT Endpoint Control Register 15 */ + #define USBHSCORE_DOEPCTL15_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL15 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL15_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL15_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL15_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL15_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL15_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL15_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL15_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL15_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL15_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL15_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL15_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL15_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL15_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL15_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL15_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL15_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL15_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL15_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL15_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL15_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL15_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL15_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL15_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL15_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL15_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL15_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL15_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL15_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL15_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL15_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL15_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL15_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL15_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL15_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL15_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL15_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL15_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL15_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL15_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL15_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL15_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL15_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL15_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL15_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL15_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL15_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL15_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL15_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL15_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL15_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL15_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL15_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL15_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL15_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL15_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL15_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL15_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL15_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL15_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL15_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL15_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL15_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL15_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL15_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL15_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL15_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL15_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL15_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL15_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL15_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL15_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL15_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL15_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL15_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL15_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL15_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL15_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL15_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL15_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL15_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL15_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL15_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT15: Device OUT Endpoint Interrupt Register 15 */ + #define USBHSCORE_DOEPINT15_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT15 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT15_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT15_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT15_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT15_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT15_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT15_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT15_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT15_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT15_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT15_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT15_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT15_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT15_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT15_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT15_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT15_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT15_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT15_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT15_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT15_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT15_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT15_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT15_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS + field.*/ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT15_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD + field.*/ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT15_BACK2BACKSETUP_Pos) /*!< Bit mask of + BACK2BACKSETUP field.*/ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT15_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT15_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT15_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT15_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT15_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT15_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT15_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT15_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT15_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT15_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT15_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT15_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT15_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT15_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT15_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT15_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT15_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT15_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT15_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD + field.*/ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_NOTRCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ15: Device OUT Endpoint Transfer Size Register 15 */ + #define USBHSCORE_DOEPTSIZ15_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ15 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ15_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ15_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ15_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ15_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ15_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ15_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ15_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA15: Device OUT Endpoint DMA Address Register 15 */ + #define USBHSCORE_DOEPDMA15_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA15 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA15_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA15_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA15_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_PCGCCTL: Power and Clock Gating Control Register */ + #define USBHSCORE_PCGCCTL_ResetValue (0x880A0000UL) /*!< Reset value of PCGCCTL register. */ + +/* STOPPCLK @Bit 0 : Stop Pclk (StopPclk) */ + #define USBHSCORE_PCGCCTL_STOPPCLK_Pos (0UL) /*!< Position of STOPPCLK field. */ + #define USBHSCORE_PCGCCTL_STOPPCLK_Msk (0x1UL << USBHSCORE_PCGCCTL_STOPPCLK_Pos) /*!< Bit mask of STOPPCLK field. */ + #define USBHSCORE_PCGCCTL_STOPPCLK_Min (0x0UL) /*!< Min enumerator value of STOPPCLK field. */ + #define USBHSCORE_PCGCCTL_STOPPCLK_Max (0x1UL) /*!< Max enumerator value of STOPPCLK field. */ + #define USBHSCORE_PCGCCTL_STOPPCLK_DISABLED (0x0UL) /*!< Disable Stop Pclk */ + #define USBHSCORE_PCGCCTL_STOPPCLK_ENABLED (0x1UL) /*!< Enable Stop Pclk */ + +/* GATEHCLK @Bit 1 : Gate Hclk (GateHclk) */ + #define USBHSCORE_PCGCCTL_GATEHCLK_Pos (1UL) /*!< Position of GATEHCLK field. */ + #define USBHSCORE_PCGCCTL_GATEHCLK_Msk (0x1UL << USBHSCORE_PCGCCTL_GATEHCLK_Pos) /*!< Bit mask of GATEHCLK field. */ + #define USBHSCORE_PCGCCTL_GATEHCLK_Min (0x0UL) /*!< Min enumerator value of GATEHCLK field. */ + #define USBHSCORE_PCGCCTL_GATEHCLK_Max (0x1UL) /*!< Max enumerator value of GATEHCLK field. */ + #define USBHSCORE_PCGCCTL_GATEHCLK_DISABLED (0x0UL) /*!< Clears this bit when the USB is resumed or a new session starts */ + #define USBHSCORE_PCGCCTL_GATEHCLK_ENABLED (0x1UL) /*!< Sets this bit to gate hclk to modules when the USB is suspended or the + session is not valid*/ + +/* RSTPDWNMODULE @Bit 3 : Reset Power-Down Modules (RstPdwnModule) */ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Pos (3UL) /*!< Position of RSTPDWNMODULE field. */ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Msk (0x1UL << USBHSCORE_PCGCCTL_RSTPDWNMODULE_Pos) /*!< Bit mask of RSTPDWNMODULE + field.*/ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Min (0x0UL) /*!< Min enumerator value of RSTPDWNMODULE field. */ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Max (0x1UL) /*!< Max enumerator value of RSTPDWNMODULE field. */ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_ON (0x0UL) /*!< Power is turned on */ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_OFF (0x1UL) /*!< Power is turned off */ + +/* ENBLL1GATING @Bit 5 : Enable Sleep Clock Gating */ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_Pos (5UL) /*!< Position of ENBLL1GATING field. */ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_Msk (0x1UL << USBHSCORE_PCGCCTL_ENBLL1GATING_Pos) /*!< Bit mask of ENBLL1GATING field.*/ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_Min (0x0UL) /*!< Min enumerator value of ENBLL1GATING field. */ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_Max (0x1UL) /*!< Max enumerator value of ENBLL1GATING field. */ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_DISABLED (0x0UL) /*!< The PHY clock is not gated in Sleep state */ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_ENABLED (0x1UL) /*!< The Core internal clock gating is enabled in Sleep state */ + +/* PHYSLEEP @Bit 6 : PHY In Sleep */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_Pos (6UL) /*!< Position of PHYSLEEP field. */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_Msk (0x1UL << USBHSCORE_PCGCCTL_PHYSLEEP_Pos) /*!< Bit mask of PHYSLEEP field. */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_Min (0x0UL) /*!< Min enumerator value of PHYSLEEP field. */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_Max (0x1UL) /*!< Max enumerator value of PHYSLEEP field. */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_INACTIVE (0x0UL) /*!< Phy not in Sleep state */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_ACTIVE (0x1UL) /*!< Phy in Sleep state */ + +/* L1SUSPENDED @Bit 7 : L1 Deep Sleep */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_Pos (7UL) /*!< Position of L1SUSPENDED field. */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_Msk (0x1UL << USBHSCORE_PCGCCTL_L1SUSPENDED_Pos) /*!< Bit mask of L1SUSPENDED field. */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_Min (0x0UL) /*!< Min enumerator value of L1SUSPENDED field. */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_Max (0x1UL) /*!< Max enumerator value of L1SUSPENDED field. */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_INACTIVE (0x0UL) /*!< Non Deep Sleep */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_ACTIVE (0x1UL) /*!< Deep Sleep */ + +/* RESTOREMODE @Bit 9 : Restore Mode (RestoreMode) */ + #define USBHSCORE_PCGCCTL_RESTOREMODE_Pos (9UL) /*!< Position of RESTOREMODE field. */ + #define USBHSCORE_PCGCCTL_RESTOREMODE_Msk (0x1UL << USBHSCORE_PCGCCTL_RESTOREMODE_Pos) /*!< Bit mask of RESTOREMODE field. */ + #define USBHSCORE_PCGCCTL_RESTOREMODE_Min (0x0UL) /*!< Min enumerator value of RESTOREMODE field. */ + #define USBHSCORE_PCGCCTL_RESTOREMODE_Max (0x1UL) /*!< Max enumerator value of RESTOREMODE field. */ + #define USBHSCORE_PCGCCTL_RESTOREMODE_DISABLED (0x0UL) /*!< In Host mode,this bit indicates Host-initiated Resume and Reset. + In Device mode, this bit indicates Device-initiated Remote Wakeup*/ + #define USBHSCORE_PCGCCTL_RESTOREMODE_ENABLED (0x1UL) /*!< In Host mode,this bit indicates Device-initiated Remote Wakeup. In + Device mode, this bit indicates Host-initiated Resume and Reset*/ + +/* ESSREGRESTORED @Bit 13 : Essential Register Values Restored (EssRegRestored) */ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Pos (13UL) /*!< Position of ESSREGRESTORED field. */ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Msk (0x1UL << USBHSCORE_PCGCCTL_ESSREGRESTORED_Pos) /*!< Bit mask of ESSREGRESTORED + field.*/ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Min (0x0UL) /*!< Min enumerator value of ESSREGRESTORED field. */ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Max (0x1UL) /*!< Max enumerator value of ESSREGRESTORED field. */ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_NOTRESTORED (0x0UL) /*!< Register values of essential registers are not restored */ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_RESTORED (0x1UL) /*!< Register values of essential registers have been restored */ + +/* RESTOREVALUE @Bits 14..31 : Restore Value (RestoreValue) */ + #define USBHSCORE_PCGCCTL_RESTOREVALUE_Pos (14UL) /*!< Position of RESTOREVALUE field. */ + #define USBHSCORE_PCGCCTL_RESTOREVALUE_Msk (0x3FFFFUL << USBHSCORE_PCGCCTL_RESTOREVALUE_Pos) /*!< Bit mask of RESTOREVALUE + field.*/ + + +/* USBHSCORE_GSTARFXDIS: Global STAR Fix Disable Register */ + #define USBHSCORE_GSTARFXDIS_ResetValue (0x00002200UL) /*!< Reset value of GSTARFXDIS register. */ + +/* HOSTIGNORESRMTWKUPDIS @Bit 0 : Disable the STAR fix added for Device controller to go back to low power mode when Host + ignores Remote wakeup */ + + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_Pos (0UL) /*!< Position of HOSTIGNORESRMTWKUPDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_Pos) /*!< Bit mask + of HOSTIGNORESRMTWKUPDIS field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_Min (0x0UL) /*!< Min enumerator value of HOSTIGNORESRMTWKUPDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_Max (0x1UL) /*!< Max enumerator value of HOSTIGNORESRMTWKUPDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_ENABLEFIX (0x0UL) /*!< Device controller goes back into SUSPENDED state + when host ignores Remote Wakeup*/ + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_DISABLEFIX (0x1UL) /*!< Device controller waits indefinitely without + entering SUSPENDED state when host ignores the + Remote Wakeup*/ + +/* RESUMEFRMCHKBUSDIS @Bit 1 : Disable the STAR fix added for Device controller to detect lineK and move to RESUMING state after + the 50us pull-up delay ends */ + + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_Pos (1UL) /*!< Position of RESUMEFRMCHKBUSDIS field. */ + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_Pos) /*!< Bit mask of + RESUMEFRMCHKBUSDIS field.*/ + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_Min (0x0UL) /*!< Min enumerator value of RESUMEFRMCHKBUSDIS field. */ + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_Max (0x1UL) /*!< Max enumerator value of RESUMEFRMCHKBUSDIS field. */ + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_ENABLEFIX (0x0UL) /*!< Device controller detects line K and resumes */ + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_DISABLEFIX (0x1UL) /*!< Device controller does not detect line K and resume */ + +/* IGNORECTLOUTDATA0DIS @Bit 2 : Disable the STAR fix added for Device controller to reject DATA0 for the first Control OUT Data + Phase and Control Status OUT Phase */ + + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_Pos (2UL) /*!< Position of IGNORECTLOUTDATA0DIS field. */ + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_Pos) /*!< Bit mask + of IGNORECTLOUTDATA0DIS field.*/ + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_Min (0x0UL) /*!< Min enumerator value of IGNORECTLOUTDATA0DIS field. */ + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_Max (0x1UL) /*!< Max enumerator value of IGNORECTLOUTDATA0DIS field. */ + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_ENABLEFIX (0x0UL) /*!< Transaction Error reported when host sends DATA0 PID*/ + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_DISABLEFIX (0x1UL) /*!< Transaction Error not reported when host sends DATA0 + PID*/ + +/* SSPLITSTALLNYETERRDIS @Bit 3 : Disable the STAR fix added for Host controller to flag error for SSPLIT STALL/NYET */ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_Pos (3UL) /*!< Position of SSPLITSTALLNYETERRDIS field. */ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_Pos) /*!< Bit mask + of SSPLITSTALLNYETERRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_Min (0x0UL) /*!< Min enumerator value of SSPLITSTALLNYETERRDIS field. */ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_Max (0x1UL) /*!< Max enumerator value of SSPLITSTALLNYETERRDIS field. */ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_ENABLEFIX (0x0UL) /*!< Transaction Error reported when device sends + STALL/NYET for SSPLIT*/ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_DISABLEFIX (0x1UL) /*!< Transaction Error not reported when device sends + STALL/NYET for SSPLIT*/ + +/* ACCEPTISOCSPLITDATA1DIS @Bit 4 : Disable the STAR fix added for Host controller to accept DATA1 PID from device for ISOC + Split transfers */ + + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_Pos (4UL) /*!< Position of ACCEPTISOCSPLITDATA1DIS field. */ + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_Pos) /*!< Bit + mask of ACCEPTISOCSPLITDATA1DIS field.*/ + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_Min (0x0UL) /*!< Min enumerator value of ACCEPTISOCSPLITDATA1DIS field. */ + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_Max (0x1UL) /*!< Max enumerator value of ACCEPTISOCSPLITDATA1DIS field. */ + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_ENABLEFIX (0x0UL) /*!< Transaction Error not reported when device sends + DATA1 PID for ISOC Split*/ + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_DISABLEFIX (0x1UL) /*!< Transaction Error reported when device sends + DATA1 PID for ISOC Split*/ + +/* HANDLEFAULTYCABLEDIS @Bit 5 : Disable the STAR fix added for Host controller to handle Faulty cable scenarios */ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_Pos (5UL) /*!< Position of HANDLEFAULTYCABLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_Pos) /*!< Bit mask + of HANDLEFAULTYCABLEDIS field.*/ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_Min (0x0UL) /*!< Min enumerator value of HANDLEFAULTYCABLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_Max (0x1UL) /*!< Max enumerator value of HANDLEFAULTYCABLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_ENABLEFIX (0x0UL) /*!< Fix for handling faulty cable enabled */ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_DISABLEFIX (0x1UL) /*!< Fix for handling faulty cable disabled */ + +/* LSIPGINCRDIS @Bit 6 : Disable the STAR fix added for Host controller LS mode IPG increment from 2 LS bit times to 3 LS bit + times */ + + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_Pos (6UL) /*!< Position of LSIPGINCRDIS field. */ + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_Pos) /*!< Bit mask of LSIPGINCRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_Min (0x0UL) /*!< Min enumerator value of LSIPGINCRDIS field. */ + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_Max (0x1UL) /*!< Max enumerator value of LSIPGINCRDIS field. */ + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_ENABLEFIX (0x0UL) /*!< Host LS mode IPG is 3 LS bit times */ + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_DISABLEFIX (0x1UL) /*!< Host LS mode IPG is 2 LS bit times */ + +/* FSDISCIDLEDIS @Bit 7 : Disable the STAR fix added for Device controller to transition to IDLE state during FS device + disconnect */ + + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_Pos (7UL) /*!< Position of FSDISCIDLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_Pos) /*!< Bit mask of + FSDISCIDLEDIS field.*/ + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_Min (0x0UL) /*!< Min enumerator value of FSDISCIDLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_Max (0x1UL) /*!< Max enumerator value of FSDISCIDLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_ENABLEFIX (0x0UL) /*!< Device controller transitions to IDLE state during FS device + disconnect*/ + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_DISABLEFIX (0x1UL) /*!< Device controller does not transition to IDLE state during + FS device disconnect*/ + +/* CONCURRENTRMTWKUPUSBRESUMEDIS @Bit 8 : Disable the STAR fix added for Device controller to not start Remote Wakeup signalling + when USB resume has already started */ + + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_Pos (8UL) /*!< Position of CONCURRENTRMTWKUPUSBRESUMEDIS field. */ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_Pos) + /*!< Bit mask of CONCURRENTRMTWKUPUSBRESUMEDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_Min (0x0UL) /*!< Min enumerator value of + CONCURRENTRMTWKUPUSBRESUMEDIS field.*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_Max (0x1UL) /*!< Max enumerator value of + CONCURRENTRMTWKUPUSBRESUMEDIS field.*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_ENABLEFIX (0x0UL) /*!< Device controller does not start remote + wakeup signalling when host resume has already + started*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_DISABLEFIX (0x1UL) /*!< Device controller is allowed to start + remote wakeup signalling when host resume has + already started*/ + +/* LSIPGCHKAFTERNAKSTALLFORINDIS @Bit 10 : Disable the STAR fix added for Host controller to wait for IPG duration to send next + token after receiving NAK/STALL for previous IN token with FS/LS device */ + + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_Pos (10UL) /*!< Position of LSIPGCHKAFTERNAKSTALLFORINDIS field. */ + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_Pos) + /*!< Bit mask of LSIPGCHKAFTERNAKSTALLFORINDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_Min (0x0UL) /*!< Min enumerator value of + LSIPGCHKAFTERNAKSTALLFORINDIS field.*/ + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_Max (0x1UL) /*!< Max enumerator value of + LSIPGCHKAFTERNAKSTALLFORINDIS field.*/ + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_ENABLEFIX (0x0UL) /*!< Host controller checks IPG after NAK/STALL + for IN token*/ + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_DISABLEFIX (0x1UL) /*!< Host controller does not check IPG after + NAK/STALL for IN token*/ + +/* PHYIOPXCVRSELTXVLDCORRDIS @Bit 11 : Disable the STAR fix added for Host controller to increase the gap between + utmi_xcvrselect switching and utmi_txvalid assertion in LS/FS mode */ + + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_Pos (11UL) /*!< Position of PHYIOPXCVRSELTXVLDCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_Pos) /*!< + Bit mask of PHYIOPXCVRSELTXVLDCORRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_Min (0x0UL) /*!< Min enumerator value of PHYIOPXCVRSELTXVLDCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_Max (0x1UL) /*!< Max enumerator value of PHYIOPXCVRSELTXVLDCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_ENABLEFIX (0x0UL) /*!< Host controller asserts utmi_txvalid at least 2 + utmi_clk cycles after utmi_xcvrselect switching*/ + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_DISABLEFIX (0x1UL) /*!< Host controller can assert utmi_txvalid after 1 + utmi_clk cycle of utmi_xcvrselect switching*/ + +/* ULPIXCVRSELSWITCHCORRDIS @Bit 12 : Disable the STAR fix added for Host controller to increase the preamble transceiver select + switch delay to accommodate time taken for ULPI function control write */ + + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_Pos (12UL) /*!< Position of ULPIXCVRSELSWITCHCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_Pos) /*!< + Bit mask of ULPIXCVRSELSWITCHCORRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_Min (0x0UL) /*!< Min enumerator value of ULPIXCVRSELSWITCHCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_Max (0x1UL) /*!< Max enumerator value of ULPIXCVRSELSWITCHCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_ENABLEFIX (0x0UL) /*!< Host controller waits for previous functional + register update to complete before switching the + transceiver select again or asserting txvalid*/ + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_DISABLEFIX (0x1UL) /*!< Host controller does not wait for the previous + functional register update to complete before + switching the transceiver select again or asserting + txvalid*/ + +/* XACTERRDATA0CTRLSTSINDIS @Bit 13 : Disable the STAR fix added for Host controller to report transaction error when DATA0 PID + is received for CTRL STATUS IN transfer in DMA mode */ + + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_Pos (13UL) /*!< Position of XACTERRDATA0CTRLSTSINDIS field. */ + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_Pos) /*!< + Bit mask of XACTERRDATA0CTRLSTSINDIS field.*/ + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_Min (0x0UL) /*!< Min enumerator value of XACTERRDATA0CTRLSTSINDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_Max (0x1UL) /*!< Max enumerator value of XACTERRDATA0CTRLSTSINDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_ENABLEFIX (0x0UL) /*!< Host controller reports transaction error when + DATA0 PID is received for CTRL STATUS IN transfer in + DMA mode*/ + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_DISABLEFIX (0x1UL) /*!< Host controller retries the transfer when DATA0 + PID is received for CTRL STATUS IN transfer in DMA + mode*/ + +/* HOSTUTMITXVLDCORRDIS @Bit 16 : Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface in Host mode. */ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_Pos (16UL) /*!< Position of HOSTUTMITXVLDCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_Pos) /*!< Bit mask + of HOSTUTMITXVLDCORRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_Min (0x0UL) /*!< Min enumerator value of HOSTUTMITXVLDCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_Max (0x1UL) /*!< Max enumerator value of HOSTUTMITXVLDCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_ENABLEFIX (0x0UL) /*!< Opmode, XcvrSel, TermSel are changed by the Host + Controller after TxValid goes LOW (1'b0)*/ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_DISABLEFIX (0x1UL) /*!< Opmode, XcvrSel, TermSel are changed by the Host + Controller without waiting for TxValid to go LOW + (1'b0) during SOF transmission*/ + +/* OPMODEXCVRSELCHIRPENCORRDIS @Bit 17 : Disable the STAR fix added for correcting Opmode and XcvrSel on UTMI Interface when + reset is detected in suspend state. */ + + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_Pos (17UL) /*!< Position of OPMODEXCVRSELCHIRPENCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_Pos) + /*!< Bit mask of OPMODEXCVRSELCHIRPENCORRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_Min (0x0UL) /*!< Min enumerator value of OPMODEXCVRSELCHIRPENCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_Max (0x1UL) /*!< Max enumerator value of OPMODEXCVRSELCHIRPENCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_ENABLEFIX (0x0UL) /*!< Valid Combination of Opmode and XcvrSel is + driven when reset is detected in suspend state*/ + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_DISABLEFIX (0x1UL) /*!< Invalid Combination of Opmode and XcvrSel is + driven when reset is detected in suspend state*/ + +/* TXVALIDDEASSERTIONCORRDIS @Bit 18 : Disable the STAR fix added for correcting Txvalid deassertion on UTMI Interface when soft + disconnect is done. */ + + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_Pos (18UL) /*!< Position of TXVALIDDEASSERTIONCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_Pos) /*!< + Bit mask of TXVALIDDEASSERTIONCORRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_Min (0x0UL) /*!< Min enumerator value of TXVALIDDEASSERTIONCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_Max (0x1UL) /*!< Max enumerator value of TXVALIDDEASSERTIONCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_ENABLEFIX (0x0UL) /*!< Txvalid is deasserted during soft disconnect + after receiving Txready from the PHY*/ + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_DISABLEFIX (0x1UL) /*!< Txvalid is deasserted during soft disconnect + without waiting for Txready from the PHY*/ + +/* HOSTNOXFERAFTERPRTDISFIXDIS @Bit 19 : Disable the STAR fix added for correcting Host behavior when port is disabled. */ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_Pos (19UL) /*!< Position of HOSTNOXFERAFTERPRTDISFIXDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_Pos) + /*!< Bit mask of HOSTNOXFERAFTERPRTDISFIXDIS field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_Min (0x0UL) /*!< Min enumerator value of HOSTNOXFERAFTERPRTDISFIXDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_Max (0x1UL) /*!< Max enumerator value of HOSTNOXFERAFTERPRTDISFIXDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_ENABLEFIX (0x0UL) /*!< Txvalid is not asserted when port is disabled*/ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_DISABLEFIX (0x1UL) /*!< Txvalid can be asserted when port is + disabled*/ + +/* LINESTATESE0FILTERFOREOPDIS @Bit 21 : Disable the STAR fix added for filtering SE0 from the linestate during EOP detection.. + */ + + #define USBHSCORE_GSTARFXDIS_LINESTATESE0FILTERFOREOPDIS_Pos (21UL) /*!< Position of LINESTATESE0FILTERFOREOPDIS field. */ + #define USBHSCORE_GSTARFXDIS_LINESTATESE0FILTERFOREOPDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_LINESTATESE0FILTERFOREOPDIS_Pos) + /*!< Bit mask of LINESTATESE0FILTERFOREOPDIS field.*/ + #define USBHSCORE_GSTARFXDIS_LINESTATESE0FILTERFOREOPDIS_Min (0x0UL) /*!< Min enumerator value of LINESTATESE0FILTERFOREOPDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_LINESTATESE0FILTERFOREOPDIS_Max (0x1UL) /*!< Max enumerator value of LINESTATESE0FILTERFOREOPDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_LINESTATESE0FILTERFOREOPDIS_ENABLEFIX (0x0UL) /*!< Filter for linestate is enabled */ + #define USBHSCORE_GSTARFXDIS_LINESTATESE0FILTERFOREOPDIS_DISABLEFIX (0x1UL) /*!< Filter for linestate is not enabled */ + +/* DMPULLDOWNUPDATEINOTGFORHIBANDPP @Bit 22 : Disable the STAR fix added for utmiotg_dmpulldown update in Hibernation and + Partial power down modes. */ + + #define USBHSCORE_GSTARFXDIS_DMPULLDOWNUPDATEINOTGFORHIBANDPP_Pos (22UL) /*!< Position of DMPULLDOWNUPDATEINOTGFORHIBANDPP + field.*/ + #define USBHSCORE_GSTARFXDIS_DMPULLDOWNUPDATEINOTGFORHIBANDPP_Msk (0x1UL << USBHSCORE_GSTARFXDIS_DMPULLDOWNUPDATEINOTGFORHIBANDPP_Pos) + /*!< Bit mask of DMPULLDOWNUPDATEINOTGFORHIBANDPP + field.*/ + #define USBHSCORE_GSTARFXDIS_DMPULLDOWNUPDATEINOTGFORHIBANDPP_Min (0x0UL) /*!< Min enumerator value of + DMPULLDOWNUPDATEINOTGFORHIBANDPP field.*/ + #define USBHSCORE_GSTARFXDIS_DMPULLDOWNUPDATEINOTGFORHIBANDPP_Max (0x1UL) /*!< Max enumerator value of + DMPULLDOWNUPDATEINOTGFORHIBANDPP field.*/ + #define USBHSCORE_GSTARFXDIS_DMPULLDOWNUPDATEINOTGFORHIBANDPP_ENABLEFIX (0x0UL) /*!< utmiotg_dmpulldown logic for hiberabtion + and partial power down is enabled*/ + #define USBHSCORE_GSTARFXDIS_DMPULLDOWNUPDATEINOTGFORHIBANDPP_DISABLEFIX (0x1UL) /*!< utmiotg_dmpulldown logic for hiberabtion + and partial power down is not enabled*/ + +/* CHIRPDETECTIONUPDTHSTDIS @Bit 23 : Disable the Chirp detection logic change in host mode. */ + #define USBHSCORE_GSTARFXDIS_CHIRPDETECTIONUPDTHSTDIS_Pos (23UL) /*!< Position of CHIRPDETECTIONUPDTHSTDIS field. */ + #define USBHSCORE_GSTARFXDIS_CHIRPDETECTIONUPDTHSTDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_CHIRPDETECTIONUPDTHSTDIS_Pos) /*!< + Bit mask of CHIRPDETECTIONUPDTHSTDIS field.*/ + #define USBHSCORE_GSTARFXDIS_CHIRPDETECTIONUPDTHSTDIS_Min (0x0UL) /*!< Min enumerator value of CHIRPDETECTIONUPDTHSTDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_CHIRPDETECTIONUPDTHSTDIS_Max (0x1UL) /*!< Max enumerator value of CHIRPDETECTIONUPDTHSTDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_CHIRPDETECTIONUPDTHSTDIS_ENABLEFIX (0x0UL) /*!< Chirp detection logic in MAC PRT module depends + on the delayed WAIT_CHIRP state and only valid chirp + K from device is detected*/ + #define USBHSCORE_GSTARFXDIS_CHIRPDETECTIONUPDTHSTDIS_DISABLEFIX (0x1UL) /*!< Chirp detection logic depends on the WAIT_CHIRP + state and controller might detect false chirp K from + device*/ + +/* PROGRAMMABLESE0DURATIONTODETECTEOP @Bit 24 : Disable the STAR fix added for programmable se0 duration to detect EOP in Host + mode . */ + + #define USBHSCORE_GSTARFXDIS_PROGRAMMABLESE0DURATIONTODETECTEOP_Pos (24UL) /*!< Position of PROGRAMMABLESE0DURATIONTODETECTEOP + field.*/ + #define USBHSCORE_GSTARFXDIS_PROGRAMMABLESE0DURATIONTODETECTEOP_Msk (0x1UL << USBHSCORE_GSTARFXDIS_PROGRAMMABLESE0DURATIONTODETECTEOP_Pos) + /*!< Bit mask of PROGRAMMABLESE0DURATIONTODETECTEOP + field.*/ + #define USBHSCORE_GSTARFXDIS_PROGRAMMABLESE0DURATIONTODETECTEOP_Min (0x0UL) /*!< Min enumerator value of + PROGRAMMABLESE0DURATIONTODETECTEOP field.*/ + #define USBHSCORE_GSTARFXDIS_PROGRAMMABLESE0DURATIONTODETECTEOP_Max (0x1UL) /*!< Max enumerator value of + PROGRAMMABLESE0DURATIONTODETECTEOP field.*/ + #define USBHSCORE_GSTARFXDIS_PROGRAMMABLESE0DURATIONTODETECTEOP_ENABLEFIX (0x0UL) /*!< Programmable se0 duration to detect EOP + in Host mode is enabled*/ + #define USBHSCORE_GSTARFXDIS_PROGRAMMABLESE0DURATIONTODETECTEOP_DISABLEFIX (0x1UL) /*!< Programmable se0 duration to detect + EOP in Host mode is disabled*/ + +/* ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT @Bit 25 : Disable the STAR fix added for h2pd_txf_0len_pkt signal which is passing + through a level synchronizer. */ + + #define USBHSCORE_GSTARFXDIS_ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT_Pos (25UL) /*!< Position of + ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT field.*/ + #define USBHSCORE_GSTARFXDIS_ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT_Msk (0x1UL << USBHSCORE_GSTARFXDIS_ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT_Pos) + /*!< Bit mask of + ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT field.*/ + #define USBHSCORE_GSTARFXDIS_ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT_Min (0x0UL) /*!< Min enumerator value of + ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT field.*/ + #define USBHSCORE_GSTARFXDIS_ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT_Max (0x1UL) /*!< Max enumerator value of + ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT field.*/ + #define USBHSCORE_GSTARFXDIS_ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT_ENABLEFIX (0x0UL) /*!< level synchroniser for + h2pd_txf_0len_pkt is enabled and disabled dummy + synchronizer*/ + #define USBHSCORE_GSTARFXDIS_ENABLELEVELSYNCHRONISERFORH2PDTXF0LENPKT_DISABLEFIX (0x1UL) /*!< level synchroniser for + h2pd_txf_0len_pkt is disabled and connected through + dummy synchronizer*/ + +/* EUSB2TERMINATERESUMEONDISCDIS @Bit 26 : Disable fix for Terminating Resume if UTMI HostDisconnect is detected. */ + #define USBHSCORE_GSTARFXDIS_EUSB2TERMINATERESUMEONDISCDIS_Pos (26UL) /*!< Position of EUSB2TERMINATERESUMEONDISCDIS field. */ + #define USBHSCORE_GSTARFXDIS_EUSB2TERMINATERESUMEONDISCDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_EUSB2TERMINATERESUMEONDISCDIS_Pos) + /*!< Bit mask of EUSB2TERMINATERESUMEONDISCDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_EUSB2TERMINATERESUMEONDISCDIS_Min (0x0UL) /*!< Min enumerator value of + EUSB2TERMINATERESUMEONDISCDIS field.*/ + #define USBHSCORE_GSTARFXDIS_EUSB2TERMINATERESUMEONDISCDIS_Max (0x1UL) /*!< Max enumerator value of + EUSB2TERMINATERESUMEONDISCDIS field.*/ + #define USBHSCORE_GSTARFXDIS_EUSB2TERMINATERESUMEONDISCDIS_ENABLEFIX (0x0UL) /*!< Host controller terminates Resume if + HostDisconnect is asserted*/ + #define USBHSCORE_GSTARFXDIS_EUSB2TERMINATERESUMEONDISCDIS_DISABLEFIX (0x1UL) /*!< Host controller does not terminate Resume + if HostDisconnect is asserted*/ + +/* EUSB2FSLSDISCDETECTIONDIS @Bit 27 : Disable fix for FS/LS disconnect detection using UTMI HostDisconnect in MAC PRT. */ + #define USBHSCORE_GSTARFXDIS_EUSB2FSLSDISCDETECTIONDIS_Pos (27UL) /*!< Position of EUSB2FSLSDISCDETECTIONDIS field. */ + #define USBHSCORE_GSTARFXDIS_EUSB2FSLSDISCDETECTIONDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_EUSB2FSLSDISCDETECTIONDIS_Pos) /*!< + Bit mask of EUSB2FSLSDISCDETECTIONDIS field.*/ + #define USBHSCORE_GSTARFXDIS_EUSB2FSLSDISCDETECTIONDIS_Min (0x0UL) /*!< Min enumerator value of EUSB2FSLSDISCDETECTIONDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_EUSB2FSLSDISCDETECTIONDIS_Max (0x1UL) /*!< Max enumerator value of EUSB2FSLSDISCDETECTIONDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_EUSB2FSLSDISCDETECTIONDIS_ENABLEFIX (0x0UL) /*!< Host controller detects FS/LS disconnect using + utmi_hostdisconnect signal*/ + #define USBHSCORE_GSTARFXDIS_EUSB2FSLSDISCDETECTIONDIS_DISABLEFIX (0x1UL) /*!< Host controller detects disconnect by + monitoring 2.5us of SE0 on DP/DM*/ + +/* HOSTFLUSHEXCESSTKNFIXDIS @Bit 29 : Disable fix for recovering the Host controller when sufficient time is not available in + the current uF for an overscheduled ISOC OUT or INTR IN transfer. */ + + #define USBHSCORE_GSTARFXDIS_HOSTFLUSHEXCESSTKNFIXDIS_Pos (29UL) /*!< Position of HOSTFLUSHEXCESSTKNFIXDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTFLUSHEXCESSTKNFIXDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_HOSTFLUSHEXCESSTKNFIXDIS_Pos) /*!< + Bit mask of HOSTFLUSHEXCESSTKNFIXDIS field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTFLUSHEXCESSTKNFIXDIS_Min (0x0UL) /*!< Min enumerator value of HOSTFLUSHEXCESSTKNFIXDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTFLUSHEXCESSTKNFIXDIS_Max (0x1UL) /*!< Max enumerator value of HOSTFLUSHEXCESSTKNFIXDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTFLUSHEXCESSTKNFIXDIS_ENABLEFIX (0x0UL) /*!< Host controller functionality is as expected if + there is an overscheduled ISOC OUT or INTR IN + transfer*/ + #define USBHSCORE_GSTARFXDIS_HOSTFLUSHEXCESSTKNFIXDIS_DISABLEFIX (0x1UL) /*!< Host controller functionality cannot be + determined if there is an overscheduled ISOC OUT or + INTR IN transfer*/ + +/* TITRANSDONETGLDURINGISOCEOPFDISABLE @Bit 30 : Disable the fix added to not toggle ti_trans_done in SEND_EOP state when the + ISOC in tokens responds with zero length packets after end of periodic frame + till next start of frame. The fix is added when operating in descriptor dma + device mode. */ + + #define USBHSCORE_GSTARFXDIS_TITRANSDONETGLDURINGISOCEOPFDISABLE_Pos (30UL) /*!< Position of + TITRANSDONETGLDURINGISOCEOPFDISABLE field.*/ + #define USBHSCORE_GSTARFXDIS_TITRANSDONETGLDURINGISOCEOPFDISABLE_Msk (0x1UL << USBHSCORE_GSTARFXDIS_TITRANSDONETGLDURINGISOCEOPFDISABLE_Pos) + /*!< Bit mask of TITRANSDONETGLDURINGISOCEOPFDISABLE + field.*/ + #define USBHSCORE_GSTARFXDIS_TITRANSDONETGLDURINGISOCEOPFDISABLE_Min (0x0UL) /*!< Min enumerator value of + TITRANSDONETGLDURINGISOCEOPFDISABLE field.*/ + #define USBHSCORE_GSTARFXDIS_TITRANSDONETGLDURINGISOCEOPFDISABLE_Max (0x1UL) /*!< Max enumerator value of + TITRANSDONETGLDURINGISOCEOPFDISABLE field.*/ + #define USBHSCORE_GSTARFXDIS_TITRANSDONETGLDURINGISOCEOPFDISABLE_ENABLEFIX (0x0UL) /*!< ti_transdone is not toggled after eopf + during ISOC IN transfer till next SOF*/ + #define USBHSCORE_GSTARFXDIS_TITRANSDONETGLDURINGISOCEOPFDISABLE_DISABLEFIX (0x1UL) /*!< ti_transdone is toggled after eopf + during ISOC IN transfer till next SOF*/ + +/* CLEARSOFREFCLKTIMERDURINGDISC @Bit 31 : Disable the STAR fix added to clear the SOF refclk timer during disconnect detection. + The STAR fix is added when using both UTMI and eUSB2 PHY. */ + + #define USBHSCORE_GSTARFXDIS_CLEARSOFREFCLKTIMERDURINGDISC_Pos (31UL) /*!< Position of CLEARSOFREFCLKTIMERDURINGDISC field. */ + #define USBHSCORE_GSTARFXDIS_CLEARSOFREFCLKTIMERDURINGDISC_Msk (0x1UL << USBHSCORE_GSTARFXDIS_CLEARSOFREFCLKTIMERDURINGDISC_Pos) + /*!< Bit mask of CLEARSOFREFCLKTIMERDURINGDISC + field.*/ + #define USBHSCORE_GSTARFXDIS_CLEARSOFREFCLKTIMERDURINGDISC_Min (0x0UL) /*!< Min enumerator value of + CLEARSOFREFCLKTIMERDURINGDISC field.*/ + #define USBHSCORE_GSTARFXDIS_CLEARSOFREFCLKTIMERDURINGDISC_Max (0x1UL) /*!< Max enumerator value of + CLEARSOFREFCLKTIMERDURINGDISC field.*/ + #define USBHSCORE_GSTARFXDIS_CLEARSOFREFCLKTIMERDURINGDISC_ENABLEFIX (0x0UL) /*!< SOF refclk timer is cleared immediately + after device disconnect is detected.*/ + #define USBHSCORE_GSTARFXDIS_CLEARSOFREFCLKTIMERDURINGDISC_DISABLEFIX (0x1UL) /*!< SOF refclk timer is not cleared immediately + after device disconnect is detected.*/ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ VDMADESCRIPTOR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ================================================== Struct VDMADESCRIPTOR ================================================== */ +/** + * @brief Job descriptor for vector-based DMA. + */ + typedef struct { /*!< VDMADESCRIPTOR Structure */ + __IOM uint32_t PTR; /*!< (@ 0x00000000) Pointer to data buffer. */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000004) Job configuration. Configuration of attributes and + buffer length.*/ + } NRF_VDMADESCRIPTOR_Type; /*!< Size = 8 (0x008) */ + +/* VDMADESCRIPTOR_PTR: Pointer to data buffer. */ + #define VDMADESCRIPTOR_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Pointer to data buffer. */ + #define VDMADESCRIPTOR_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define VDMADESCRIPTOR_PTR_PTR_Msk (0xFFFFFFFFUL << VDMADESCRIPTOR_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* VDMADESCRIPTOR_CONFIG: Job configuration. Configuration of attributes and buffer length. */ + #define VDMADESCRIPTOR_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* CNT @Bits 0..23 : Maximum number of bytes in data buffer. */ + #define VDMADESCRIPTOR_CONFIG_CNT_Pos (0UL) /*!< Position of CNT field. */ + #define VDMADESCRIPTOR_CONFIG_CNT_Msk (0xFFFFFFUL << VDMADESCRIPTOR_CONFIG_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* ATTRIBUTE @Bits 24..29 : Job attribute. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos (24UL) /*!< Position of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Msk (0x3FUL << VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos) /*!< Bit mask of ATTRIBUTE field.*/ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Min (0x0BUL) /*!< Min enumerator value of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Max (0x0EUL) /*!< Max enumerator value of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarHash (0x0BUL) /*!< Hash attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarPrand (0x0CUL) /*!< Prand attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarIrk (0x0DUL) /*!< Irk attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmAlen (0x0BUL) /*!< Alen attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmMlen (0x0CUL) /*!< Mlen attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmAdata (0x0DUL) /*!< Adata attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmMdata (0x0EUL) /*!< Mdata attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_EcbData (0x0BUL) /*!< EcbData attribute */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ VPR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =================================================== Struct VPR_DEBUGIF ==================================================== */ +/** + * @brief DEBUGIF [VPR_DEBUGIF] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED[4]; + __IOM uint32_t DATA0; /*!< (@ 0x00000010) Abstract Data 0. Read/write data for argument 0 */ + __IOM uint32_t DATA1; /*!< (@ 0x00000014) Abstract Data 1. Read/write data for argument 1 */ + __IM uint32_t RESERVED1[10]; + __IOM uint32_t DMCONTROL; /*!< (@ 0x00000040) Debug Module Control */ + __IM uint32_t DMSTATUS; /*!< (@ 0x00000044) Debug Module Status */ + __IOM uint32_t HARTINFO; /*!< (@ 0x00000048) Hart Information */ + __IOM uint32_t HALTSUM1; /*!< (@ 0x0000004C) Halt Summary 1 */ + __IOM uint32_t HAWINDOWSEL; /*!< (@ 0x00000050) Hart Array Window Select */ + __IOM uint32_t HAWINDOW; /*!< (@ 0x00000054) Hart Array Window */ + __IOM uint32_t ABSTRACTCS; /*!< (@ 0x00000058) Abstract Control and Status */ + __OM uint32_t ABSTRACTCMD; /*!< (@ 0x0000005C) Abstract command */ + __IOM uint32_t ABSTRACTAUTO; /*!< (@ 0x00000060) Abstract Command Autoexec */ + __IOM uint32_t CONFSTRPTR[4]; /*!< (@ 0x00000064) Configuration String Pointer [n] */ + __IOM uint32_t NEXTDM; /*!< (@ 0x00000074) Next Debug Module */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t PROGBUF[16]; /*!< (@ 0x00000080) Program Buffer [n] */ + __IOM uint32_t AUTHDATA; /*!< (@ 0x000000C0) Authentication Data */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t HALTSUM2; /*!< (@ 0x000000D0) Halt Summary 2 */ + __IOM uint32_t HALTSUM3; /*!< (@ 0x000000D4) Halt Summary 3 */ + __IM uint32_t RESERVED4; + __IOM uint32_t SBADDRESS3; /*!< (@ 0x000000DC) System Bus Addres 127:96 */ + __IOM uint32_t SBCS; /*!< (@ 0x000000E0) System Bus Access Control and Status */ + __IOM uint32_t SBADDRESS0; /*!< (@ 0x000000E4) System Bus Addres 31:0 */ + __IOM uint32_t SBADDRESS1; /*!< (@ 0x000000E8) System Bus Addres 63:32 */ + __IOM uint32_t SBADDRESS2; /*!< (@ 0x000000EC) System Bus Addres 95:64 */ + __IOM uint32_t SBDATA0; /*!< (@ 0x000000F0) System Bus Data 31:0 */ + __IOM uint32_t SBDATA1; /*!< (@ 0x000000F4) System Bus Data 63:32 */ + __IOM uint32_t SBDATA2; /*!< (@ 0x000000F8) System Bus Data 95:64 */ + __IOM uint32_t SBDATA3; /*!< (@ 0x000000FC) System Bus Data 127:96 */ + __IOM uint32_t HALTSUM0; /*!< (@ 0x00000100) Halt summary 0 */ +} NRF_VPR_DEBUGIF_Type; /*!< Size = 260 (0x104) */ + +/* VPR_DEBUGIF_DATA0: Abstract Data 0. Read/write data for argument 0 */ + #define VPR_DEBUGIF_DATA0_ResetValue (0x00000000UL) /*!< Reset value of DATA0 register. */ + +/* DATA0 @Bits 0..31 : Abstract Data 0 */ + #define VPR_DEBUGIF_DATA0_DATA0_Pos (0UL) /*!< Position of DATA0 field. */ + #define VPR_DEBUGIF_DATA0_DATA0_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_DATA0_DATA0_Pos) /*!< Bit mask of DATA0 field. */ + + +/* VPR_DEBUGIF_DATA1: Abstract Data 1. Read/write data for argument 1 */ + #define VPR_DEBUGIF_DATA1_ResetValue (0x00000000UL) /*!< Reset value of DATA1 register. */ + +/* DATA1 @Bits 0..31 : Abstract Data 1 */ + #define VPR_DEBUGIF_DATA1_DATA1_Pos (0UL) /*!< Position of DATA1 field. */ + #define VPR_DEBUGIF_DATA1_DATA1_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_DATA1_DATA1_Pos) /*!< Bit mask of DATA1 field. */ + + +/* VPR_DEBUGIF_DMCONTROL: Debug Module Control */ + #define VPR_DEBUGIF_DMCONTROL_ResetValue (0x00000000UL) /*!< Reset value of DMCONTROL register. */ + +/* DMACTIVE @Bit 0 : Reset signal for the debug module. */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos (0UL) /*!< Position of DMACTIVE field. */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos) /*!< Bit mask of DMACTIVE field. */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Min (0x0UL) /*!< Min enumerator value of DMACTIVE field. */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Max (0x1UL) /*!< Max enumerator value of DMACTIVE field. */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Disabled (0x0UL) /*!< Reset the debug module itself */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Enabled (0x1UL) /*!< Normal operation */ + +/* NDMRESET @Bit 1 : Reset signal output from the debug module to the system. */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos (1UL) /*!< Position of NDMRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos) /*!< Bit mask of NDMRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Min (0x0UL) /*!< Min enumerator value of NDMRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Max (0x1UL) /*!< Max enumerator value of NDMRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Inactive (0x0UL) /*!< Reset inactive */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Active (0x1UL) /*!< Reset active */ + +/* CLRRESETHALTREQ @Bit 2 : Clear the halt on reset request. */ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Pos (2UL) /*!< Position of CLRRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Pos) /*!< Bit mask of + CLRRESETHALTREQ field.*/ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of CLRRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of CLRRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_NoOperation (0x0UL) /*!< No operation when written 0. */ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Clear (0x1UL) /*!< Clears the halt on reset request */ + +/* SETRESETHALTREQ @Bit 3 : Set the halt on reset request. */ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Pos (3UL) /*!< Position of SETRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Pos) /*!< Bit mask of + SETRESETHALTREQ field.*/ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of SETRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of SETRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_NoOperation (0x0UL) /*!< No operation when written 0. */ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Clear (0x1UL) /*!< Sets the halt on reset request */ + +/* HARTSELHI @Bits 6..15 : The high 10 bits of hartsel. */ + #define VPR_DEBUGIF_DMCONTROL_HARTSELHI_Pos (6UL) /*!< Position of HARTSELHI field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTSELHI_Msk (0x3FFUL << VPR_DEBUGIF_DMCONTROL_HARTSELHI_Pos) /*!< Bit mask of HARTSELHI + field.*/ + +/* HARTSELLO @Bits 16..25 : The low 10 bits of hartsel. */ + #define VPR_DEBUGIF_DMCONTROL_HARTSELLO_Pos (16UL) /*!< Position of HARTSELLO field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTSELLO_Msk (0x3FFUL << VPR_DEBUGIF_DMCONTROL_HARTSELLO_Pos) /*!< Bit mask of HARTSELLO + field.*/ + +/* HASEL @Bit 26 : Definition of currently selected harts. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Pos (26UL) /*!< Position of HASEL field. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HASEL_Pos) /*!< Bit mask of HASEL field. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Min (0x0UL) /*!< Min enumerator value of HASEL field. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Max (0x1UL) /*!< Max enumerator value of HASEL field. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Single (0x0UL) /*!< Single hart selected. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Multiple (0x1UL) /*!< Multiple harts selected */ + +/* ACKHAVERESET @Bit 28 : Clear the havereset. */ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Pos (28UL) /*!< Position of ACKHAVERESET field. */ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Pos) /*!< Bit mask of ACKHAVERESET + field.*/ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Min (0x0UL) /*!< Min enumerator value of ACKHAVERESET field. */ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Max (0x1UL) /*!< Max enumerator value of ACKHAVERESET field. */ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_NoOperation (0x0UL) /*!< No operation when written 0. */ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Clear (0x1UL) /*!< Clears the havereset for selected harts. */ + +/* HARTRESET @Bit 29 : Reset harts. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Pos (29UL) /*!< Position of HARTRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HARTRESET_Pos) /*!< Bit mask of HARTRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Min (0x0UL) /*!< Min enumerator value of HARTRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Max (0x1UL) /*!< Max enumerator value of HARTRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Deasserted (0x0UL) /*!< Reset de-asserted. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Asserted (0x1UL) /*!< Reset asserted. */ + +/* RESUMEREQ @Bit 30 : Resume currently selected harts. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Pos (30UL) /*!< Position of RESUMEREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Pos) /*!< Bit mask of RESUMEREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Min (0x0UL) /*!< Min enumerator value of RESUMEREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Max (0x1UL) /*!< Max enumerator value of RESUMEREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_NoOperation (0x0UL) /*!< No operation when written 0. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Resumed (0x1UL) /*!< Currently selected harts resumed. */ + +/* HALTREQ @Bit 31 : Halt currently selected harts. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Pos (31UL) /*!< Position of HALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HALTREQ_Pos) /*!< Bit mask of HALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Min (0x0UL) /*!< Min enumerator value of HALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Max (0x1UL) /*!< Max enumerator value of HALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Clear (0x0UL) /*!< Clears halt request bit for all currently selected harts. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Halt (0x1UL) /*!< Currently selected harts halted. */ + + +/* VPR_DEBUGIF_DMSTATUS: Debug Module Status */ + #define VPR_DEBUGIF_DMSTATUS_ResetValue (0x00400082UL) /*!< Reset value of DMSTATUS register. */ + +/* VERSION @Bits 0..3 : Version of the debug module. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_Pos (0UL) /*!< Position of VERSION field. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_Msk (0xFUL << VPR_DEBUGIF_DMSTATUS_VERSION_Pos) /*!< Bit mask of VERSION field. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_Min (0x0UL) /*!< Min enumerator value of VERSION field. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_Max (0xFUL) /*!< Max enumerator value of VERSION field. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_NotPresent (0x0UL) /*!< Debug module not present. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_V011 (0x1UL) /*!< There is a Debug Module and it conforms to version 0.11 of this + specifcation.*/ + #define VPR_DEBUGIF_DMSTATUS_VERSION_V013 (0x2UL) /*!< There is a Debug Module and it conforms to version 0.13 of this + specifcation.*/ + #define VPR_DEBUGIF_DMSTATUS_VERSION_NonConform (0xFUL) /*!< There is a Debug Module but it does not conform to any available + version of the spec.*/ + +/* CONFSTRPTRVALID @Bit 4 : Configuration string. */ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Pos (4UL) /*!< Position of CONFSTRPTRVALID field. */ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Pos) /*!< Bit mask of + CONFSTRPTRVALID field.*/ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Min (0x0UL) /*!< Min enumerator value of CONFSTRPTRVALID field. */ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Max (0x1UL) /*!< Max enumerator value of CONFSTRPTRVALID field. */ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_NotRelevant (0x0UL) /*!< The confstrptr0..confstrptr3 holds information which is + not relevant to the configuration string.*/ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Address (0x1UL) /*!< The confstrptr0..confstrptr3 holds the address of the + configuration string.*/ + +/* HASRESETHALTREQ @Bit 5 : Halt-on-reset support status. */ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Pos (5UL) /*!< Position of HASRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Pos) /*!< Bit mask of + HASRESETHALTREQ field.*/ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of HASRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of HASRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_No (0x0UL) /*!< Halt-on-reset is supported. */ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Yes (0x1UL) /*!< Halt-on-reset is not supported. */ + +/* AUTHBUSY @Bit 6 : Authentication busy status. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Pos (6UL) /*!< Position of AUTHBUSY field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Pos) /*!< Bit mask of AUTHBUSY field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Min (0x0UL) /*!< Min enumerator value of AUTHBUSY field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Max (0x1UL) /*!< Max enumerator value of AUTHBUSY field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_No (0x0UL) /*!< The authentication module is ready. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Yes (0x1UL) /*!< The authentication module is busy. */ + +/* AUTHENTICATED @Bit 7 : Authentication status. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Pos (7UL) /*!< Position of AUTHENTICATED field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Pos) /*!< Bit mask of + AUTHENTICATED field.*/ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Min (0x0UL) /*!< Min enumerator value of AUTHENTICATED field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Max (0x1UL) /*!< Max enumerator value of AUTHENTICATED field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_No (0x0UL) /*!< Authentication required before using the debug module. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Yes (0x1UL) /*!< Authentication passed. */ + +/* ANYHALTED @Bit 8 : Any currently selected harts halted status. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Pos (8UL) /*!< Position of ANYHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYHALTED_Pos) /*!< Bit mask of ANYHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Min (0x0UL) /*!< Min enumerator value of ANYHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Max (0x1UL) /*!< Max enumerator value of ANYHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_No (0x0UL) /*!< None of the currently selected harts halted. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Yes (0x1UL) /*!< Any of the currently selected harts halted. */ + +/* ALLHALTED @Bit 9 : All currently selected harts halted status. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Pos (9UL) /*!< Position of ALLHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLHALTED_Pos) /*!< Bit mask of ALLHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Min (0x0UL) /*!< Min enumerator value of ALLHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Max (0x1UL) /*!< Max enumerator value of ALLHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_No (0x0UL) /*!< Not all of the currently selected harts halted. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Yes (0x1UL) /*!< All of the currently selected harts halted. */ + +/* ANYRUNNING @Bit 10 : Any currently selected harts running status. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Pos (10UL) /*!< Position of ANYRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Pos) /*!< Bit mask of ANYRUNNING field.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Min (0x0UL) /*!< Min enumerator value of ANYRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Max (0x1UL) /*!< Max enumerator value of ANYRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_No (0x0UL) /*!< None of the currently selected harts running. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Yes (0x1UL) /*!< Any of the currently selected harts running. */ + +/* ALLRUNNING @Bit 11 : All currently selected harts running status. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Pos (11UL) /*!< Position of ALLRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Pos) /*!< Bit mask of ALLRUNNING field.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Min (0x0UL) /*!< Min enumerator value of ALLRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Max (0x1UL) /*!< Max enumerator value of ALLRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_No (0x0UL) /*!< Not all of the currently selected harts running. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Yes (0x1UL) /*!< All of the currently selected harts running. */ + +/* ANYUNAVAIL @Bit 12 : Any currently selected harts unavailable status. */ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Pos (12UL) /*!< Position of ANYUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Pos) /*!< Bit mask of ANYUNAVAIL field.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Min (0x0UL) /*!< Min enumerator value of ANYUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Max (0x1UL) /*!< Max enumerator value of ANYUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_No (0x0UL) /*!< None of the currently selected harts unavailable. */ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Yes (0x1UL) /*!< Any of the currently selected harts unavailable. */ + +/* ALLUNAVAIL @Bit 13 : All currently selected harts unavailable status. */ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Pos (13UL) /*!< Position of ALLUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Pos) /*!< Bit mask of ALLUNAVAIL field.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Min (0x0UL) /*!< Min enumerator value of ALLUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Max (0x1UL) /*!< Max enumerator value of ALLUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_No (0x0UL) /*!< Not all of the currently selected harts unavailable. */ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Yes (0x1UL) /*!< All of the currently selected harts unavailable. */ + +/* ANYNONEXISTENT @Bit 14 : Any currently selected harts nonexistent status. */ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Pos (14UL) /*!< Position of ANYNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Pos) /*!< Bit mask of + ANYNONEXISTENT field.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Min (0x0UL) /*!< Min enumerator value of ANYNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Max (0x1UL) /*!< Max enumerator value of ANYNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_No (0x0UL) /*!< None of the currently selected harts nonexistent. */ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Yes (0x1UL) /*!< Any of the currently selected harts nonexistent. */ + +/* ALLNONEXISTENT @Bit 15 : All currently selected harts nonexistent status. */ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Pos (15UL) /*!< Position of ALLNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Pos) /*!< Bit mask of + ALLNONEXISTENT field.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Min (0x0UL) /*!< Min enumerator value of ALLNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Max (0x1UL) /*!< Max enumerator value of ALLNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_No (0x0UL) /*!< Not all of the currently selected harts nonexistent. */ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Yes (0x1UL) /*!< All of the currently selected harts nonexistent. */ + +/* ANYRESUMEACK @Bit 16 : Any currently selected harts acknowledged last resume request. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Pos (16UL) /*!< Position of ANYRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Pos) /*!< Bit mask of ANYRESUMEACK + field.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Min (0x0UL) /*!< Min enumerator value of ANYRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Max (0x1UL) /*!< Max enumerator value of ANYRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_No (0x0UL) /*!< None of the currently selected harts acknowledged last resume + request.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Yes (0x1UL) /*!< Any of the currently selected harts acknowledged last resume + request.*/ + +/* ALLRESUMEACK @Bit 17 : All currently selected harts acknowledged last resume */ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Pos (17UL) /*!< Position of ALLRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Pos) /*!< Bit mask of ALLRESUMEACK + field.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Min (0x0UL) /*!< Min enumerator value of ALLRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Max (0x1UL) /*!< Max enumerator value of ALLRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_No (0x0UL) /*!< Not all of the currently selected harts acknowledged last resume + request.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Yes (0x1UL) /*!< All of the currently selected harts acknowledged last resume + request.*/ + +/* ANYHAVERESET @Bit 18 : Any currently selected harts have been reset and reset is not acknowledged. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Pos (18UL) /*!< Position of ANYHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Pos) /*!< Bit mask of ANYHAVERESET + field.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Min (0x0UL) /*!< Min enumerator value of ANYHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Max (0x1UL) /*!< Max enumerator value of ANYHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_No (0x0UL) /*!< None of the currently selected harts have been reset and reset is + not acknowledget.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Yes (0x1UL) /*!< Any of the currently selected harts have been reset and reset is + not acknowledge.*/ + +/* ALLHAVERESET @Bit 19 : All currently selected harts have been reset and reset is not acknowledge */ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Pos (19UL) /*!< Position of ALLHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Pos) /*!< Bit mask of ALLHAVERESET + field.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Min (0x0UL) /*!< Min enumerator value of ALLHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Max (0x1UL) /*!< Max enumerator value of ALLHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_No (0x0UL) /*!< Not all of the currently selected harts have been reset and reset is + not acknowledge.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Yes (0x1UL) /*!< All of the currently selected harts have been reset and reset is + not acknowledge.*/ + +/* IMPEBREAK @Bit 22 : Implicit ebreak instruction at the non-existent word immediately after the Program Buffer. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Pos (22UL) /*!< Position of IMPEBREAK field. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Pos) /*!< Bit mask of IMPEBREAK field. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Min (0x0UL) /*!< Min enumerator value of IMPEBREAK field. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Max (0x1UL) /*!< Max enumerator value of IMPEBREAK field. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_No (0x0UL) /*!< No implicit ebreak instruction. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Yes (0x1UL) /*!< Implicit ebreak instruction. */ + + +/* VPR_DEBUGIF_HARTINFO: Hart Information */ + #define VPR_DEBUGIF_HARTINFO_ResetValue (0x00000000UL) /*!< Reset value of HARTINFO register. */ + +/* DATAADDR @Bits 0..11 : Data Address */ + #define VPR_DEBUGIF_HARTINFO_DATAADDR_Pos (0UL) /*!< Position of DATAADDR field. */ + #define VPR_DEBUGIF_HARTINFO_DATAADDR_Msk (0xFFFUL << VPR_DEBUGIF_HARTINFO_DATAADDR_Pos) /*!< Bit mask of DATAADDR field. */ + #define VPR_DEBUGIF_HARTINFO_DATAADDR_Min (0x800UL) /*!< Min value of DATAADDR field. */ + #define VPR_DEBUGIF_HARTINFO_DATAADDR_Max (0x7FFUL) /*!< Max size of DATAADDR field. */ + +/* DATASIZE @Bits 12..15 : Data Size */ + #define VPR_DEBUGIF_HARTINFO_DATASIZE_Pos (12UL) /*!< Position of DATASIZE field. */ + #define VPR_DEBUGIF_HARTINFO_DATASIZE_Msk (0xFUL << VPR_DEBUGIF_HARTINFO_DATASIZE_Pos) /*!< Bit mask of DATASIZE field. */ + #define VPR_DEBUGIF_HARTINFO_DATASIZE_Min (0x0UL) /*!< Min value of DATASIZE field. */ + #define VPR_DEBUGIF_HARTINFO_DATASIZE_Max (0xCUL) /*!< Max size of DATASIZE field. */ + +/* DATAACCESS @Bit 16 : Data Access */ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Pos (16UL) /*!< Position of DATAACCESS field. */ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Msk (0x1UL << VPR_DEBUGIF_HARTINFO_DATAACCESS_Pos) /*!< Bit mask of DATAACCESS field.*/ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Min (0x0UL) /*!< Min enumerator value of DATAACCESS field. */ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Max (0x1UL) /*!< Max enumerator value of DATAACCESS field. */ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_No (0x0UL) /*!< The data registers are shadowed in the hart by CSRs. Each CSR is DXLEN + bits in size, and corresponds to a single argument.*/ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Yes (0x1UL) /*!< The data registers are shadowed in the hart's memory map. Each + register takes up 4 bytes in the memory map.*/ + +/* NSCRATCH @Bits 20..23 : Number of dscratch registers */ + #define VPR_DEBUGIF_HARTINFO_NSCRATCH_Pos (20UL) /*!< Position of NSCRATCH field. */ + #define VPR_DEBUGIF_HARTINFO_NSCRATCH_Msk (0xFUL << VPR_DEBUGIF_HARTINFO_NSCRATCH_Pos) /*!< Bit mask of NSCRATCH field. */ + + +/* VPR_DEBUGIF_HALTSUM1: Halt Summary 1 */ + #define VPR_DEBUGIF_HALTSUM1_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM1 register. */ + +/* HALTSUM1 @Bits 0..31 : Halt Summary 1 */ + #define VPR_DEBUGIF_HALTSUM1_HALTSUM1_Pos (0UL) /*!< Position of HALTSUM1 field. */ + #define VPR_DEBUGIF_HALTSUM1_HALTSUM1_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM1_HALTSUM1_Pos) /*!< Bit mask of HALTSUM1 + field.*/ + + +/* VPR_DEBUGIF_HAWINDOWSEL: Hart Array Window Select */ + #define VPR_DEBUGIF_HAWINDOWSEL_ResetValue (0x00000000UL) /*!< Reset value of HAWINDOWSEL register. */ + +/* HAWINDOWSEL @Bits 0..14 : The high bits of this field may be tied to 0, depending on how large the array mask register is. + E.g. on a system with 48 harts only bit 0 of this field may actually be writable. */ + + #define VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Pos (0UL) /*!< Position of HAWINDOWSEL field. */ + #define VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Msk (0x7FFFUL << VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Pos) /*!< Bit mask of + HAWINDOWSEL field.*/ + + +/* VPR_DEBUGIF_HAWINDOW: Hart Array Window */ + #define VPR_DEBUGIF_HAWINDOW_ResetValue (0x00000000UL) /*!< Reset value of HAWINDOW register. */ + +/* MASKDATA @Bits 0..31 : Mask data. */ + #define VPR_DEBUGIF_HAWINDOW_MASKDATA_Pos (0UL) /*!< Position of MASKDATA field. */ + #define VPR_DEBUGIF_HAWINDOW_MASKDATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HAWINDOW_MASKDATA_Pos) /*!< Bit mask of MASKDATA + field.*/ + + +/* VPR_DEBUGIF_ABSTRACTCS: Abstract Control and Status */ + #define VPR_DEBUGIF_ABSTRACTCS_ResetValue (0x01000002UL) /*!< Reset value of ABSTRACTCS register. */ + +/* DATACOUNT @Bits 0..3 : Number of data registers that are implemented as part of the abstract command interface. Valid sizes + are 1..12. */ + + #define VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Pos (0UL) /*!< Position of DATACOUNT field. */ + #define VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Msk (0xFUL << VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Pos) /*!< Bit mask of DATACOUNT + field.*/ + +/* CMDERR @Bits 8..10 : Command error when the abstract command fails. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Pos (8UL) /*!< Position of CMDERR field. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Msk (0x7UL << VPR_DEBUGIF_ABSTRACTCS_CMDERR_Pos) /*!< Bit mask of CMDERR field. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Min (0x0UL) /*!< Min enumerator value of CMDERR field. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Max (0x7UL) /*!< Max enumerator value of CMDERR field. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_NoError (0x0UL) /*!< No error. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Busy (0x1UL) /*!< An abstract command was executing while command, abstractcs, or + abstractauto was written, or when one of the data or progbuf registers + was read or written. This status is only written if cmderr contains 0*/ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_NotSupported (0x2UL) /*!< The requested command is notsupported, regardless of whether + the hart is running or not.*/ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Exception (0x3UL) /*!< An exception occurred while executing the command (e.g. while + executing theProgram Buffer).*/ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_HaltResume (0x4UL) /*!< The abstract command couldn't execute because the hart wasn't in + the required state (running/halted). or unavailable.*/ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Bus (0x5UL) /*!< The abstract command failed due to abus error (e.g. alignment, access + size, or timeout).*/ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Other (0x7UL) /*!< The command failed for another reason. */ + +/* BUSY @Bit 12 : Abstract command execution status. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Pos (12UL) /*!< Position of BUSY field. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Msk (0x1UL << VPR_DEBUGIF_ABSTRACTCS_BUSY_Pos) /*!< Bit mask of BUSY field. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Min (0x0UL) /*!< Min enumerator value of BUSY field. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Max (0x1UL) /*!< Max enumerator value of BUSY field. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_NotBusy (0x0UL) /*!< Not busy. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Busy (0x1UL) /*!< An abstract command is currently being executed. This bit is set as + soon as command is written, and is not cleared until that command has + completed.*/ + +/* PROGBUFSIZE @Bits 24..28 : Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1. */ + #define VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Pos (24UL) /*!< Position of PROGBUFSIZE field. */ + #define VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Msk (0x1FUL << VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Pos) /*!< Bit mask of PROGBUFSIZE + field.*/ + + +/* VPR_DEBUGIF_ABSTRACTCMD: Abstract command */ + #define VPR_DEBUGIF_ABSTRACTCMD_ResetValue (0x00000000UL) /*!< Reset value of ABSTRACTCMD register. */ + +/* CONTROL @Bits 0..23 : This Field is interpreted in a command specific manner, described for each abstract command. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Pos (0UL) /*!< Position of CONTROL field. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Msk (0xFFFFFFUL << VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Pos) /*!< Bit mask of CONTROL + field.*/ + +/* CMDTYPE @Bits 24..31 : The type determines the overall functionality of this abstract command. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Pos (24UL) /*!< Position of CMDTYPE field. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Msk (0xFFUL << VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Pos) /*!< Bit mask of CMDTYPE field. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Min (0x00UL) /*!< Min enumerator value of CMDTYPE field. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Max (0x02UL) /*!< Max enumerator value of CMDTYPE field. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_REGACCESS (0x00UL) /*!< Register Access Command */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_QUICKACCESS (0x01UL) /*!< Quick Access Command */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_MEMACCESS (0x02UL) /*!< Memory Access Command */ + + +/* VPR_DEBUGIF_ABSTRACTAUTO: Abstract Command Autoexec */ + #define VPR_DEBUGIF_ABSTRACTAUTO_ResetValue (0x00000000UL) /*!< Reset value of ABSTRACTAUTO register. */ + +/* AUTOEXECDATA @Bits 0..11 : When a bit in this field is 1, read or write accesses to the corresponding data word cause the + command in command to be executed again. */ + + #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Pos (0UL) /*!< Position of AUTOEXECDATA field. */ + #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Msk (0xFFFUL << VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Pos) /*!< Bit mask of + AUTOEXECDATA field.*/ + +/* AUTOEXECPROGBUF @Bits 16..31 : When a bit in this field is 1, read or write accesses to the corresponding progbuf word cause + the command in command to be executed again. */ + + #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Pos (16UL) /*!< Position of AUTOEXECPROGBUF field. */ + #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Msk (0xFFFFUL << VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Pos) /*!< Bit mask + of AUTOEXECPROGBUF field.*/ + + +/* VPR_DEBUGIF_CONFSTRPTR: Configuration String Pointer [n] */ + #define VPR_DEBUGIF_CONFSTRPTR_MaxCount (4UL) /*!< Max size of CONFSTRPTR[4] array. */ + #define VPR_DEBUGIF_CONFSTRPTR_MaxIndex (3UL) /*!< Max index of CONFSTRPTR[4] array. */ + #define VPR_DEBUGIF_CONFSTRPTR_MinIndex (0UL) /*!< Min index of CONFSTRPTR[4] array. */ + #define VPR_DEBUGIF_CONFSTRPTR_ResetValue (0x00000000UL) /*!< Reset value of CONFSTRPTR[4] register. */ + +/* ADDR @Bits 0..31 : Address */ + #define VPR_DEBUGIF_CONFSTRPTR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ + #define VPR_DEBUGIF_CONFSTRPTR_ADDR_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_CONFSTRPTR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + + +/* VPR_DEBUGIF_NEXTDM: Next Debug Module */ + #define VPR_DEBUGIF_NEXTDM_ResetValue (0x00000000UL) /*!< Reset value of NEXTDM register. */ + +/* ADDR @Bits 0..31 : Address */ + #define VPR_DEBUGIF_NEXTDM_ADDR_Pos (0UL) /*!< Position of ADDR field. */ + #define VPR_DEBUGIF_NEXTDM_ADDR_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_NEXTDM_ADDR_Pos) /*!< Bit mask of ADDR field. */ + + +/* VPR_DEBUGIF_PROGBUF: Program Buffer [n] */ + #define VPR_DEBUGIF_PROGBUF_MaxCount (16UL) /*!< Max size of PROGBUF[16] array. */ + #define VPR_DEBUGIF_PROGBUF_MaxIndex (15UL) /*!< Max index of PROGBUF[16] array. */ + #define VPR_DEBUGIF_PROGBUF_MinIndex (0UL) /*!< Min index of PROGBUF[16] array. */ + #define VPR_DEBUGIF_PROGBUF_ResetValue (0x00000000UL) /*!< Reset value of PROGBUF[16] register. */ + +/* DATA @Bits 0..31 : Data */ + #define VPR_DEBUGIF_PROGBUF_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_PROGBUF_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_PROGBUF_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_AUTHDATA: Authentication Data */ + #define VPR_DEBUGIF_AUTHDATA_ResetValue (0x00000000UL) /*!< Reset value of AUTHDATA register. */ + +/* DATA @Bits 0..31 : Data */ + #define VPR_DEBUGIF_AUTHDATA_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_AUTHDATA_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_AUTHDATA_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_HALTSUM2: Halt Summary 2 */ + #define VPR_DEBUGIF_HALTSUM2_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM2 register. */ + +/* HALTSUM2 @Bits 0..31 : Halt Summary 2 */ + #define VPR_DEBUGIF_HALTSUM2_HALTSUM2_Pos (0UL) /*!< Position of HALTSUM2 field. */ + #define VPR_DEBUGIF_HALTSUM2_HALTSUM2_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM2_HALTSUM2_Pos) /*!< Bit mask of HALTSUM2 + field.*/ + + +/* VPR_DEBUGIF_HALTSUM3: Halt Summary 3 */ + #define VPR_DEBUGIF_HALTSUM3_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM3 register. */ + +/* HALTSUM3 @Bits 0..31 : Halt Summary 3 */ + #define VPR_DEBUGIF_HALTSUM3_HALTSUM3_Pos (0UL) /*!< Position of HALTSUM3 field. */ + #define VPR_DEBUGIF_HALTSUM3_HALTSUM3_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM3_HALTSUM3_Pos) /*!< Bit mask of HALTSUM3 + field.*/ + + +/* VPR_DEBUGIF_SBADDRESS3: System Bus Addres 127:96 */ + #define VPR_DEBUGIF_SBADDRESS3_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS3 register. */ + +/* ADDRESS @Bits 0..31 : Accesses bits 127:96 of the physical address in sbaddress (if the system address bus is that wide). */ + #define VPR_DEBUGIF_SBADDRESS3_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define VPR_DEBUGIF_SBADDRESS3_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS3_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* VPR_DEBUGIF_SBCS: System Bus Access Control and Status */ + #define VPR_DEBUGIF_SBCS_ResetValue (0x20000000UL) /*!< Reset value of SBCS register. */ + +/* SBACCESS8 @Bit 0 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS8_Pos (0UL) /*!< Position of SBACCESS8 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS8_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS8_Pos) /*!< Bit mask of SBACCESS8 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS8_Min (0x1UL) /*!< Min enumerator value of SBACCESS8 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS8_Max (0x1UL) /*!< Max enumerator value of SBACCESS8 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS8_sbaccess8 (0x1UL) /*!< 8-bit system bus accesses are supported. */ + +/* SBACCESS16 @Bit 1 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS16_Pos (1UL) /*!< Position of SBACCESS16 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS16_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS16_Pos) /*!< Bit mask of SBACCESS16 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS16_Min (0x1UL) /*!< Min enumerator value of SBACCESS16 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS16_Max (0x1UL) /*!< Max enumerator value of SBACCESS16 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS16_sbaccess16 (0x1UL) /*!< 16-bit system bus accesses are supported. */ + +/* SBACCESS32 @Bit 2 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS32_Pos (2UL) /*!< Position of SBACCESS32 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS32_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS32_Pos) /*!< Bit mask of SBACCESS32 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS32_Min (0x1UL) /*!< Min enumerator value of SBACCESS32 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS32_Max (0x1UL) /*!< Max enumerator value of SBACCESS32 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS32_sbaccess32 (0x1UL) /*!< 32-bit system bus accesses are supported. */ + +/* SBACCESS64 @Bit 3 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS64_Pos (3UL) /*!< Position of SBACCESS64 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS64_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS64_Pos) /*!< Bit mask of SBACCESS64 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS64_Min (0x1UL) /*!< Min enumerator value of SBACCESS64 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS64_Max (0x1UL) /*!< Max enumerator value of SBACCESS64 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS64_sbaccess64 (0x1UL) /*!< 64-bit system bus accesses are supported. */ + +/* SBACCESS128 @Bit 4 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS128_Pos (4UL) /*!< Position of SBACCESS128 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS128_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS128_Pos) /*!< Bit mask of SBACCESS128 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS128_Min (0x1UL) /*!< Min enumerator value of SBACCESS128 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS128_Max (0x1UL) /*!< Max enumerator value of SBACCESS128 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS128_sbaccess128 (0x1UL) /*!< 128-bit system bus accesses are supported. */ + +/* SBASIZE @Bits 5..11 : Width of system bus addresses in bits. (0 indicates there is no bus access support.) */ + #define VPR_DEBUGIF_SBCS_SBASIZE_Pos (5UL) /*!< Position of SBASIZE field. */ + #define VPR_DEBUGIF_SBCS_SBASIZE_Msk (0x7FUL << VPR_DEBUGIF_SBCS_SBASIZE_Pos) /*!< Bit mask of SBASIZE field. */ + +/* SBERROR @Bits 12..14 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBERROR_Pos (12UL) /*!< Position of SBERROR field. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBERROR_Pos) /*!< Bit mask of SBERROR field. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Min (0x0UL) /*!< Min enumerator value of SBERROR field. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Max (0x7UL) /*!< Max enumerator value of SBERROR field. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Normal (0x0UL) /*!< There was no bus error. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Timeout (0x1UL) /*!< There was a timeout. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Address (0x2UL) /*!< A bad address was accessed. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Alignment (0x3UL) /*!< There was an alignment error. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Size (0x4UL) /*!< An access of unsupported size was requested. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Other (0x7UL) /*!< Other. */ + +/* SBREADONDATA @Bit 15 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBREADONDATA_Pos (15UL) /*!< Position of SBREADONDATA field. */ + #define VPR_DEBUGIF_SBCS_SBREADONDATA_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBREADONDATA_Pos) /*!< Bit mask of SBREADONDATA field. */ + #define VPR_DEBUGIF_SBCS_SBREADONDATA_Min (0x1UL) /*!< Min enumerator value of SBREADONDATA field. */ + #define VPR_DEBUGIF_SBCS_SBREADONDATA_Max (0x1UL) /*!< Max enumerator value of SBREADONDATA field. */ + #define VPR_DEBUGIF_SBCS_SBREADONDATA_sbreadondata (0x1UL) /*!< Every read from sbdata0 automatically triggers a system bus + read at the (possibly autoincremented) address.*/ + +/* SBAUTOINCREMENT @Bit 16 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Pos (16UL) /*!< Position of SBAUTOINCREMENT field. */ + #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Pos) /*!< Bit mask of SBAUTOINCREMENT + field.*/ + #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Min (0x1UL) /*!< Min enumerator value of SBAUTOINCREMENT field. */ + #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Max (0x1UL) /*!< Max enumerator value of SBAUTOINCREMENT field. */ + #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_sbautoincrement (0x1UL) /*!< sbaddress is incremented by the access size (in bytes) + selected in sbaccess after every system bus access.*/ + +/* SBACCESS @Bits 17..19 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS_Pos (17UL) /*!< Position of SBACCESS field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBACCESS_Pos) /*!< Bit mask of SBACCESS field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_Min (0x0UL) /*!< Min enumerator value of SBACCESS field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_Max (0x4UL) /*!< Max enumerator value of SBACCESS field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_size8 (0x0UL) /*!< 8-bit. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_size16 (0x1UL) /*!< 16-bit. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_size32 (0x2UL) /*!< 32-bit. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_size64 (0x3UL) /*!< 64-bit. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_size128 (0x4UL) /*!< 128-bit. */ + +/* SBREADONADDR @Bit 20 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBREADONADDR_Pos (20UL) /*!< Position of SBREADONADDR field. */ + #define VPR_DEBUGIF_SBCS_SBREADONADDR_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBREADONADDR_Pos) /*!< Bit mask of SBREADONADDR field. */ + #define VPR_DEBUGIF_SBCS_SBREADONADDR_Min (0x1UL) /*!< Min enumerator value of SBREADONADDR field. */ + #define VPR_DEBUGIF_SBCS_SBREADONADDR_Max (0x1UL) /*!< Max enumerator value of SBREADONADDR field. */ + #define VPR_DEBUGIF_SBCS_SBREADONADDR_sbreadonaddr (0x1UL) /*!< Every write to sbaddress0 automatically triggers a system bus + read at the new address.*/ + +/* SBBUSY @Bit 21 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBBUSY_Pos (21UL) /*!< Position of SBBUSY field. */ + #define VPR_DEBUGIF_SBCS_SBBUSY_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBBUSY_Pos) /*!< Bit mask of SBBUSY field. */ + #define VPR_DEBUGIF_SBCS_SBBUSY_Min (0x0UL) /*!< Min enumerator value of SBBUSY field. */ + #define VPR_DEBUGIF_SBCS_SBBUSY_Max (0x1UL) /*!< Max enumerator value of SBBUSY field. */ + #define VPR_DEBUGIF_SBCS_SBBUSY_notbusy (0x0UL) /*!< System bus master is not busy. */ + #define VPR_DEBUGIF_SBCS_SBBUSY_busy (0x1UL) /*!< System bus master is busy. */ + +/* SBBUSYERROR @Bit 22 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Pos (22UL) /*!< Position of SBBUSYERROR field. */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBBUSYERROR_Pos) /*!< Bit mask of SBBUSYERROR field. */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Min (0x0UL) /*!< Min enumerator value of SBBUSYERROR field. */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Max (0x1UL) /*!< Max enumerator value of SBBUSYERROR field. */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_noerror (0x0UL) /*!< No error. */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_error (0x1UL) /*!< Debugger access attempted while one in progress. */ + +/* SBVERSION @Bits 29..31 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBVERSION_Pos (29UL) /*!< Position of SBVERSION field. */ + #define VPR_DEBUGIF_SBCS_SBVERSION_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBVERSION_Pos) /*!< Bit mask of SBVERSION field. */ + #define VPR_DEBUGIF_SBCS_SBVERSION_Min (0x0UL) /*!< Min enumerator value of SBVERSION field. */ + #define VPR_DEBUGIF_SBCS_SBVERSION_Max (0x1UL) /*!< Max enumerator value of SBVERSION field. */ + #define VPR_DEBUGIF_SBCS_SBVERSION_version0 (0x0UL) /*!< The System Bus interface conforms to mainline drafts of thia RISC-V + External Debug Support spec older than 1 January, 2018.*/ + #define VPR_DEBUGIF_SBCS_SBVERSION_version1 (0x1UL) /*!< The System Bus interface conforms to RISC-V External Debug Support + version 0.14.0-DRAFT. Other values are reserved for future versions.*/ + + +/* VPR_DEBUGIF_SBADDRESS0: System Bus Addres 31:0 */ + #define VPR_DEBUGIF_SBADDRESS0_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS0 register. */ + +/* ADDRESS @Bits 0..31 : Accesses bits 31:0 of the physical address in sbaddress. */ + #define VPR_DEBUGIF_SBADDRESS0_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define VPR_DEBUGIF_SBADDRESS0_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS0_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* VPR_DEBUGIF_SBADDRESS1: System Bus Addres 63:32 */ + #define VPR_DEBUGIF_SBADDRESS1_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS1 register. */ + +/* ADDRESS @Bits 0..31 : Accesses bits 63:32 of the physical address in sbaddress (if the system address bus is that wide). */ + #define VPR_DEBUGIF_SBADDRESS1_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define VPR_DEBUGIF_SBADDRESS1_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS1_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* VPR_DEBUGIF_SBADDRESS2: System Bus Addres 95:64 */ + #define VPR_DEBUGIF_SBADDRESS2_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS2 register. */ + +/* ADDRESS @Bits 0..31 : Accesses bits 95:64 of the physical address in sbaddress (if the system address bus is that wide). */ + #define VPR_DEBUGIF_SBADDRESS2_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define VPR_DEBUGIF_SBADDRESS2_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS2_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* VPR_DEBUGIF_SBDATA0: System Bus Data 31:0 */ + #define VPR_DEBUGIF_SBDATA0_ResetValue (0x00000000UL) /*!< Reset value of SBDATA0 register. */ + +/* DATA @Bits 0..31 : Accesses bits 31:0 of sbdata */ + #define VPR_DEBUGIF_SBDATA0_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_SBDATA0_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA0_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_SBDATA1: System Bus Data 63:32 */ + #define VPR_DEBUGIF_SBDATA1_ResetValue (0x00000000UL) /*!< Reset value of SBDATA1 register. */ + +/* DATA @Bits 0..31 : Accesses bits 63:32 of sbdata (if the system bus is that wide). */ + #define VPR_DEBUGIF_SBDATA1_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_SBDATA1_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA1_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_SBDATA2: System Bus Data 95:64 */ + #define VPR_DEBUGIF_SBDATA2_ResetValue (0x00000000UL) /*!< Reset value of SBDATA2 register. */ + +/* DATA @Bits 0..31 : Accesses bits 95:64 of sbdata (if the system bus is that wide). */ + #define VPR_DEBUGIF_SBDATA2_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_SBDATA2_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA2_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_SBDATA3: System Bus Data 127:96 */ + #define VPR_DEBUGIF_SBDATA3_ResetValue (0x00000000UL) /*!< Reset value of SBDATA3 register. */ + +/* DATA @Bits 0..31 : Accesses bits 127:96 of sbdata (if the system bus is that wide). */ + #define VPR_DEBUGIF_SBDATA3_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_SBDATA3_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA3_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_HALTSUM0: Halt summary 0 */ + #define VPR_DEBUGIF_HALTSUM0_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM0 register. */ + +/* HALTSUM0 @Bits 0..31 : Halt summary 0 */ + #define VPR_DEBUGIF_HALTSUM0_HALTSUM0_Pos (0UL) /*!< Position of HALTSUM0 field. */ + #define VPR_DEBUGIF_HALTSUM0_HALTSUM0_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM0_HALTSUM0_Pos) /*!< Bit mask of HALTSUM0 + field.*/ + + +/* ======================================================= Struct VPR ======================================================== */ +/** + * @brief VPR peripheral registers + */ + typedef struct { /*!< VPR Structure */ + __OM uint32_t TASKS_TRIGGER[23]; /*!< (@ 0x00000000) VPR task [n] register */ + __IM uint32_t RESERVED[9]; + __IOM uint32_t SUBSCRIBE_TRIGGER[20]; /*!< (@ 0x00000080) Subscribe configuration for task TASKS_TRIGGER[n] */ + __IM uint32_t RESERVED1[12]; + __IOM uint32_t EVENTS_TRIGGERED[23]; /*!< (@ 0x00000100) VPR event [n] register */ + __IM uint32_t RESERVED2[9]; + __IOM uint32_t PUBLISH_TRIGGERED[20]; /*!< (@ 0x00000180) Publish configuration for event EVENTS_TRIGGERED[n] */ + __IM uint32_t RESERVED3[76]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED4[60]; + __IOM NRF_VPR_DEBUGIF_Type DEBUGIF; /*!< (@ 0x00000400) (unspecified) */ + __IM uint32_t RESERVED5[191]; + __IOM uint32_t CPURUN; /*!< (@ 0x00000800) State of the CPU after a core reset */ + __IOM uint32_t VPRSTATUS; /*!< (@ 0x00000804) VPR state information. */ + __IOM uint32_t INITPC; /*!< (@ 0x00000808) Initial value of the PC at CPU start. */ + } NRF_VPR_Type; /*!< Size = 2060 (0x80C) */ + +/* VPR_TASKS_TRIGGER: VPR task [n] register */ + #define VPR_TASKS_TRIGGER_MaxCount (7UL) /*!< Max size of TASKS_TRIGGER[23] array. */ + #define VPR_TASKS_TRIGGER_MaxIndex (22UL) /*!< Max index of TASKS_TRIGGER[23] array. */ + #define VPR_TASKS_TRIGGER_MinIndex (16UL) /*!< Min index of TASKS_TRIGGER[23] array. */ + #define VPR_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[23] register. */ + +/* TASKS_TRIGGER @Bit 0 : VPR task [n] register */ + #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ + #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << VPR_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER + field.*/ + #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field. */ + #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field. */ + #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */ + + +/* VPR_SUBSCRIBE_TRIGGER: Subscribe configuration for task TASKS_TRIGGER[n] */ + #define VPR_SUBSCRIBE_TRIGGER_MaxCount (4UL) /*!< Max size of SUBSCRIBE_TRIGGER[20] array. */ + #define VPR_SUBSCRIBE_TRIGGER_MaxIndex (19UL) /*!< Max index of SUBSCRIBE_TRIGGER[20] array. */ + #define VPR_SUBSCRIBE_TRIGGER_MinIndex (16UL) /*!< Min index of SUBSCRIBE_TRIGGER[20] array. */ + #define VPR_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[20] register. */ + +/* EN @Bit 31 : Subscription enable bit */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << VPR_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* VPR_EVENTS_TRIGGERED: VPR event [n] register */ + #define VPR_EVENTS_TRIGGERED_MaxCount (7UL) /*!< Max size of EVENTS_TRIGGERED[23] array. */ + #define VPR_EVENTS_TRIGGERED_MaxIndex (22UL) /*!< Max index of EVENTS_TRIGGERED[23] array. */ + #define VPR_EVENTS_TRIGGERED_MinIndex (16UL) /*!< Min index of EVENTS_TRIGGERED[23] array. */ + #define VPR_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[23] register. */ + +/* EVENTS_TRIGGERED @Bit 0 : VPR event [n] register */ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of + EVENTS_TRIGGERED field.*/ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TRIGGERED field. */ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TRIGGERED field. */ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated */ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated */ + + +/* VPR_PUBLISH_TRIGGERED: Publish configuration for event EVENTS_TRIGGERED[n] */ + #define VPR_PUBLISH_TRIGGERED_MaxCount (4UL) /*!< Max size of PUBLISH_TRIGGERED[20] array. */ + #define VPR_PUBLISH_TRIGGERED_MaxIndex (19UL) /*!< Max index of PUBLISH_TRIGGERED[20] array. */ + #define VPR_PUBLISH_TRIGGERED_MinIndex (16UL) /*!< Min index of PUBLISH_TRIGGERED[20] array. */ + #define VPR_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[20] register. */ + +/* EN @Bit 31 : Publication enable bit */ + #define VPR_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ + #define VPR_PUBLISH_TRIGGERED_EN_Msk (0x1UL << VPR_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */ + #define VPR_PUBLISH_TRIGGERED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define VPR_PUBLISH_TRIGGERED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define VPR_PUBLISH_TRIGGERED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define VPR_PUBLISH_TRIGGERED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* VPR_INTEN: Enable or disable interrupt */ + #define VPR_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */ + #define VPR_INTEN_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define VPR_INTEN_TRIGGERED16_Msk (0x1UL << VPR_INTEN_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define VPR_INTEN_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define VPR_INTEN_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define VPR_INTEN_TRIGGERED16_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED16_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */ + #define VPR_INTEN_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define VPR_INTEN_TRIGGERED17_Msk (0x1UL << VPR_INTEN_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define VPR_INTEN_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define VPR_INTEN_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define VPR_INTEN_TRIGGERED17_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED17_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */ + #define VPR_INTEN_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define VPR_INTEN_TRIGGERED18_Msk (0x1UL << VPR_INTEN_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define VPR_INTEN_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define VPR_INTEN_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define VPR_INTEN_TRIGGERED18_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED18_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */ + #define VPR_INTEN_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define VPR_INTEN_TRIGGERED19_Msk (0x1UL << VPR_INTEN_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define VPR_INTEN_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define VPR_INTEN_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define VPR_INTEN_TRIGGERED19_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED19_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */ + #define VPR_INTEN_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define VPR_INTEN_TRIGGERED20_Msk (0x1UL << VPR_INTEN_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define VPR_INTEN_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define VPR_INTEN_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define VPR_INTEN_TRIGGERED20_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED20_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */ + #define VPR_INTEN_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define VPR_INTEN_TRIGGERED21_Msk (0x1UL << VPR_INTEN_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define VPR_INTEN_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define VPR_INTEN_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define VPR_INTEN_TRIGGERED21_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED21_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */ + #define VPR_INTEN_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define VPR_INTEN_TRIGGERED22_Msk (0x1UL << VPR_INTEN_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define VPR_INTEN_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define VPR_INTEN_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define VPR_INTEN_TRIGGERED22_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED22_Enabled (0x1UL) /*!< Enable */ + + +/* VPR_INTENSET: Enable interrupt */ + #define VPR_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */ + #define VPR_INTENSET_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define VPR_INTENSET_TRIGGERED16_Msk (0x1UL << VPR_INTENSET_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define VPR_INTENSET_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define VPR_INTENSET_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define VPR_INTENSET_TRIGGERED16_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */ + #define VPR_INTENSET_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define VPR_INTENSET_TRIGGERED17_Msk (0x1UL << VPR_INTENSET_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define VPR_INTENSET_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define VPR_INTENSET_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define VPR_INTENSET_TRIGGERED17_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */ + #define VPR_INTENSET_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define VPR_INTENSET_TRIGGERED18_Msk (0x1UL << VPR_INTENSET_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define VPR_INTENSET_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define VPR_INTENSET_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define VPR_INTENSET_TRIGGERED18_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */ + #define VPR_INTENSET_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define VPR_INTENSET_TRIGGERED19_Msk (0x1UL << VPR_INTENSET_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define VPR_INTENSET_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define VPR_INTENSET_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define VPR_INTENSET_TRIGGERED19_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */ + #define VPR_INTENSET_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define VPR_INTENSET_TRIGGERED20_Msk (0x1UL << VPR_INTENSET_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define VPR_INTENSET_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define VPR_INTENSET_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define VPR_INTENSET_TRIGGERED20_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */ + #define VPR_INTENSET_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define VPR_INTENSET_TRIGGERED21_Msk (0x1UL << VPR_INTENSET_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define VPR_INTENSET_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define VPR_INTENSET_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define VPR_INTENSET_TRIGGERED21_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */ + #define VPR_INTENSET_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define VPR_INTENSET_TRIGGERED22_Msk (0x1UL << VPR_INTENSET_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define VPR_INTENSET_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define VPR_INTENSET_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define VPR_INTENSET_TRIGGERED22_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* VPR_INTENCLR: Disable interrupt */ + #define VPR_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */ + #define VPR_INTENCLR_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define VPR_INTENCLR_TRIGGERED16_Msk (0x1UL << VPR_INTENCLR_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define VPR_INTENCLR_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define VPR_INTENCLR_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define VPR_INTENCLR_TRIGGERED16_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */ + #define VPR_INTENCLR_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define VPR_INTENCLR_TRIGGERED17_Msk (0x1UL << VPR_INTENCLR_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define VPR_INTENCLR_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define VPR_INTENCLR_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define VPR_INTENCLR_TRIGGERED17_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */ + #define VPR_INTENCLR_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define VPR_INTENCLR_TRIGGERED18_Msk (0x1UL << VPR_INTENCLR_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define VPR_INTENCLR_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define VPR_INTENCLR_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define VPR_INTENCLR_TRIGGERED18_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */ + #define VPR_INTENCLR_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define VPR_INTENCLR_TRIGGERED19_Msk (0x1UL << VPR_INTENCLR_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define VPR_INTENCLR_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define VPR_INTENCLR_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define VPR_INTENCLR_TRIGGERED19_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */ + #define VPR_INTENCLR_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define VPR_INTENCLR_TRIGGERED20_Msk (0x1UL << VPR_INTENCLR_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define VPR_INTENCLR_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define VPR_INTENCLR_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define VPR_INTENCLR_TRIGGERED20_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */ + #define VPR_INTENCLR_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define VPR_INTENCLR_TRIGGERED21_Msk (0x1UL << VPR_INTENCLR_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define VPR_INTENCLR_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define VPR_INTENCLR_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define VPR_INTENCLR_TRIGGERED21_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */ + #define VPR_INTENCLR_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define VPR_INTENCLR_TRIGGERED22_Msk (0x1UL << VPR_INTENCLR_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define VPR_INTENCLR_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define VPR_INTENCLR_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define VPR_INTENCLR_TRIGGERED22_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* VPR_INTPEND: Pending interrupts */ + #define VPR_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */ + #define VPR_INTPEND_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define VPR_INTPEND_TRIGGERED16_Msk (0x1UL << VPR_INTPEND_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define VPR_INTPEND_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define VPR_INTPEND_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define VPR_INTPEND_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */ + #define VPR_INTPEND_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define VPR_INTPEND_TRIGGERED17_Msk (0x1UL << VPR_INTPEND_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define VPR_INTPEND_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define VPR_INTPEND_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define VPR_INTPEND_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */ + #define VPR_INTPEND_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define VPR_INTPEND_TRIGGERED18_Msk (0x1UL << VPR_INTPEND_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define VPR_INTPEND_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define VPR_INTPEND_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define VPR_INTPEND_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */ + #define VPR_INTPEND_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define VPR_INTPEND_TRIGGERED19_Msk (0x1UL << VPR_INTPEND_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define VPR_INTPEND_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define VPR_INTPEND_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define VPR_INTPEND_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */ + #define VPR_INTPEND_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define VPR_INTPEND_TRIGGERED20_Msk (0x1UL << VPR_INTPEND_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define VPR_INTPEND_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define VPR_INTPEND_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define VPR_INTPEND_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */ + #define VPR_INTPEND_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define VPR_INTPEND_TRIGGERED21_Msk (0x1UL << VPR_INTPEND_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define VPR_INTPEND_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define VPR_INTPEND_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define VPR_INTPEND_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */ + #define VPR_INTPEND_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define VPR_INTPEND_TRIGGERED22_Msk (0x1UL << VPR_INTPEND_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define VPR_INTPEND_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define VPR_INTPEND_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define VPR_INTPEND_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending */ + + +/* VPR_CPURUN: State of the CPU after a core reset */ + #define VPR_CPURUN_ResetValue (0x00000000UL) /*!< Reset value of CPURUN register. */ + +/* EN @Bit 0 : Controls CPU running state after a core reset. */ + #define VPR_CPURUN_EN_Pos (0UL) /*!< Position of EN field. */ + #define VPR_CPURUN_EN_Msk (0x1UL << VPR_CPURUN_EN_Pos) /*!< Bit mask of EN field. */ + #define VPR_CPURUN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define VPR_CPURUN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define VPR_CPURUN_EN_Stopped (0x0UL) /*!< CPU stopped. If this is the CPU state after a core reset, setting this + bit will change the CPU state to CPU running.*/ + #define VPR_CPURUN_EN_Running (0x1UL) /*!< CPU running. If this is the CPU state after a core reset, clearing + this bit will change the CPU state to CPU stopped after a core reset.*/ + + +/* VPR_VPRSTATUS: VPR state information. */ + #define VPR_VPRSTATUS_ResetValue (0x00000000UL) /*!< Reset value of VPRSTATUS register. */ + +/* CPUSTATUS @Bits 0..3 : (unspecified) */ + #define VPR_VPRSTATUS_CPUSTATUS_Pos (0UL) /*!< Position of CPUSTATUS field. */ + #define VPR_VPRSTATUS_CPUSTATUS_Msk (0xFUL << VPR_VPRSTATUS_CPUSTATUS_Pos) /*!< Bit mask of CPUSTATUS field. */ + #define VPR_VPRSTATUS_CPUSTATUS_Min (0x0UL) /*!< Min enumerator value of CPUSTATUS field. */ + #define VPR_VPRSTATUS_CPUSTATUS_Max (0xEUL) /*!< Max enumerator value of CPUSTATUS field. */ + #define VPR_VPRSTATUS_CPUSTATUS_WAITING (0x0UL) /*!< WAITING (not yet started) */ + #define VPR_VPRSTATUS_CPUSTATUS_RUNNING (0x1UL) /*!< RUNNING */ + #define VPR_VPRSTATUS_CPUSTATUS_SLEEPING (0x2UL) /*!< SLEEPING */ + #define VPR_VPRSTATUS_CPUSTATUS_INTERRUPT (0x3UL) /*!< INTERRUPT (in handler) */ + #define VPR_VPRSTATUS_CPUSTATUS_EXCEPTION_TRAP (0x4UL) /*!< EXCEPTION/TRAP (in handler) */ + #define VPR_VPRSTATUS_CPUSTATUS_ONGOING_RESET (0x5UL) /*!< ONGOING_RESET */ + #define VPR_VPRSTATUS_CPUSTATUS_HALTED (0x6UL) /*!< HALTED */ + #define VPR_VPRSTATUS_CPUSTATUS_ERROR (0xEUL) /*!< ERROR (lockup, needs debugging or reset) */ + +/* RTPENABLED @Bit 4 : Mirrors the ENABLERTPERIPH bit in the NORDIC.VPRNORDICCTRL CSR */ + #define VPR_VPRSTATUS_RTPENABLED_Pos (4UL) /*!< Position of RTPENABLED field. */ + #define VPR_VPRSTATUS_RTPENABLED_Msk (0x1UL << VPR_VPRSTATUS_RTPENABLED_Pos) /*!< Bit mask of RTPENABLED field. */ + #define VPR_VPRSTATUS_RTPENABLED_Min (0x0UL) /*!< Min enumerator value of RTPENABLED field. */ + #define VPR_VPRSTATUS_RTPENABLED_Max (0x1UL) /*!< Max enumerator value of RTPENABLED field. */ + #define VPR_VPRSTATUS_RTPENABLED_Disabled (0x0UL) /*!< Real-time peripherals disabled */ + #define VPR_VPRSTATUS_RTPENABLED_Enabled (0x1UL) /*!< Real-time peripherals enabled */ + +/* RTPSTALL @Bit 5 : Stalled waiting for real-time peripheral blocking CSR access, for example WAIT, OUTB with dirty status */ + #define VPR_VPRSTATUS_RTPSTALL_Pos (5UL) /*!< Position of RTPSTALL field. */ + #define VPR_VPRSTATUS_RTPSTALL_Msk (0x1UL << VPR_VPRSTATUS_RTPSTALL_Pos) /*!< Bit mask of RTPSTALL field. */ + + +/* VPR_INITPC: Initial value of the PC at CPU start. */ + #define VPR_INITPC_ResetValue (0x00000000UL) /*!< Reset value of INITPC register. */ + +/* INITPC @Bits 0..31 : Initial value of the PC at CPU start. */ + #define VPR_INITPC_INITPC_Pos (0UL) /*!< Position of INITPC field. */ + #define VPR_INITPC_INITPC_Msk (0xFFFFFFFFUL << VPR_INITPC_INITPC_Pos) /*!< Bit mask of INITPC field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ VPRCSR ================ */ +/* =========================================================================================================================== */ + +/** + * @brief VPR CSR registers + */ +/** + * @brief [VPRCSR] (unspecified) + */ + +/** + * @brief [VPRCSR] (unspecified) + */ + +/** + * @brief MSTATUS [VPRCSR_MSTATUS] Machine Status + */ + #define VPRCSR_MSTATUS (0x00000300ul) + #define VPRCSR_MSTATUS_ResetValue (0x00001800UL) /*!< Reset value of MSTATUS register. */ + +/* MIE @Bit 3 : global interrupt enable for machine privilege mode */ + #define VPRCSR_MSTATUS_MIE_Pos (3UL) /*!< Position of MIE field. */ + #define VPRCSR_MSTATUS_MIE_Msk (0x1UL << VPRCSR_MSTATUS_MIE_Pos) /*!< Bit mask of MIE field. */ + #define VPRCSR_MSTATUS_MIE_Min (0x0UL) /*!< Min enumerator value of MIE field. */ + #define VPRCSR_MSTATUS_MIE_Max (0x1UL) /*!< Max enumerator value of MIE field. */ + #define VPRCSR_MSTATUS_MIE_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MSTATUS_MIE_Enabled (0x1UL) /*!< (unspecified) */ + +/* MPIE @Bit 7 : Exists to support nested traps. Value of the interrupt-enable bit active prior to the trap for machine + privilege mode */ + + #define VPRCSR_MSTATUS_MPIE_Pos (7UL) /*!< Position of MPIE field. */ + #define VPRCSR_MSTATUS_MPIE_Msk (0x1UL << VPRCSR_MSTATUS_MPIE_Pos) /*!< Bit mask of MPIE field. */ + #define VPRCSR_MSTATUS_MPIE_Min (0x0UL) /*!< Min enumerator value of MPIE field. */ + #define VPRCSR_MSTATUS_MPIE_Max (0x1UL) /*!< Max enumerator value of MPIE field. */ + #define VPRCSR_MSTATUS_MPIE_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MSTATUS_MPIE_Enabled (0x1UL) /*!< (unspecified) */ + +/* MPP @Bits 11..12 : Exists to support nested traps. Value of the privlege mode prior to the trap for machine privilege mode */ + #define VPRCSR_MSTATUS_MPP_Pos (11UL) /*!< Position of MPP field. */ + #define VPRCSR_MSTATUS_MPP_Msk (0x3UL << VPRCSR_MSTATUS_MPP_Pos) /*!< Bit mask of MPP field. */ + + +/** + * @brief MISA [VPRCSR_MISA] Machine ISA + */ + #define VPRCSR_MISA (0x00000301ul) + #define VPRCSR_MISA_ResetValue (0x40001016UL) /*!< Reset value of MISA register. */ + +/* A @Bit 0 : Atomic extension */ + #define VPRCSR_MISA_A_Pos (0UL) /*!< Position of A field. */ + #define VPRCSR_MISA_A_Msk (0x1UL << VPRCSR_MISA_A_Pos) /*!< Bit mask of A field. */ + #define VPRCSR_MISA_A_Min (0x0UL) /*!< Min enumerator value of A field. */ + #define VPRCSR_MISA_A_Max (0x1UL) /*!< Max enumerator value of A field. */ + #define VPRCSR_MISA_A_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_A_Enabled (0x1UL) /*!< (unspecified) */ + +/* B @Bit 1 : Bit-Manipulation extension */ + #define VPRCSR_MISA_B_Pos (1UL) /*!< Position of B field. */ + #define VPRCSR_MISA_B_Msk (0x1UL << VPRCSR_MISA_B_Pos) /*!< Bit mask of B field. */ + #define VPRCSR_MISA_B_Min (0x0UL) /*!< Min enumerator value of B field. */ + #define VPRCSR_MISA_B_Max (0x1UL) /*!< Max enumerator value of B field. */ + #define VPRCSR_MISA_B_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_B_Enabled (0x1UL) /*!< (unspecified) */ + +/* C @Bit 2 : Compressed extension */ + #define VPRCSR_MISA_C_Pos (2UL) /*!< Position of C field. */ + #define VPRCSR_MISA_C_Msk (0x1UL << VPRCSR_MISA_C_Pos) /*!< Bit mask of C field. */ + #define VPRCSR_MISA_C_Min (0x0UL) /*!< Min enumerator value of C field. */ + #define VPRCSR_MISA_C_Max (0x1UL) /*!< Max enumerator value of C field. */ + #define VPRCSR_MISA_C_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_C_Enabled (0x1UL) /*!< (unspecified) */ + +/* E @Bit 4 : RV32E base ISA */ + #define VPRCSR_MISA_E_Pos (4UL) /*!< Position of E field. */ + #define VPRCSR_MISA_E_Msk (0x1UL << VPRCSR_MISA_E_Pos) /*!< Bit mask of E field. */ + #define VPRCSR_MISA_E_Min (0x0UL) /*!< Min enumerator value of E field. */ + #define VPRCSR_MISA_E_Max (0x1UL) /*!< Max enumerator value of E field. */ + #define VPRCSR_MISA_E_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_E_Enabled (0x1UL) /*!< (unspecified) */ + +/* I @Bit 8 : RV32I/64I/128I base ISA */ + #define VPRCSR_MISA_I_Pos (8UL) /*!< Position of I field. */ + #define VPRCSR_MISA_I_Msk (0x1UL << VPRCSR_MISA_I_Pos) /*!< Bit mask of I field. */ + #define VPRCSR_MISA_I_Min (0x0UL) /*!< Min enumerator value of I field. */ + #define VPRCSR_MISA_I_Max (0x1UL) /*!< Max enumerator value of I field. */ + #define VPRCSR_MISA_I_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_I_Enabled (0x1UL) /*!< (unspecified) */ + +/* M @Bit 12 : Integer Multiply/Divide extension */ + #define VPRCSR_MISA_M_Pos (12UL) /*!< Position of M field. */ + #define VPRCSR_MISA_M_Msk (0x1UL << VPRCSR_MISA_M_Pos) /*!< Bit mask of M field. */ + #define VPRCSR_MISA_M_Min (0x0UL) /*!< Min enumerator value of M field. */ + #define VPRCSR_MISA_M_Max (0x1UL) /*!< Max enumerator value of M field. */ + #define VPRCSR_MISA_M_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_M_Enabled (0x1UL) /*!< (unspecified) */ + +/* N @Bit 13 : User-level interrupts supported */ + #define VPRCSR_MISA_N_Pos (13UL) /*!< Position of N field. */ + #define VPRCSR_MISA_N_Msk (0x1UL << VPRCSR_MISA_N_Pos) /*!< Bit mask of N field. */ + #define VPRCSR_MISA_N_Min (0x0UL) /*!< Min enumerator value of N field. */ + #define VPRCSR_MISA_N_Max (0x1UL) /*!< Max enumerator value of N field. */ + #define VPRCSR_MISA_N_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_N_Enabled (0x1UL) /*!< (unspecified) */ + +/* MXL @Bits 30..31 : Machine XLEN */ + #define VPRCSR_MISA_MXL_Pos (30UL) /*!< Position of MXL field. */ + #define VPRCSR_MISA_MXL_Msk (0x3UL << VPRCSR_MISA_MXL_Pos) /*!< Bit mask of MXL field. */ + #define VPRCSR_MISA_MXL_Min (0x1UL) /*!< Min enumerator value of MXL field. */ + #define VPRCSR_MISA_MXL_Max (0x3UL) /*!< Max enumerator value of MXL field. */ + #define VPRCSR_MISA_MXL_XLEN32 (0x1UL) /*!< XLEN is 32 bits */ + #define VPRCSR_MISA_MXL_XLEN64 (0x2UL) /*!< XLEN is 64 bits */ + #define VPRCSR_MISA_MXL_XLEN128 (0x3UL) /*!< XLEN is 128 bits */ + + +/** + * @brief MTVEC [VPRCSR_MTVEC] Machine Trap-Vector + */ + #define VPRCSR_MTVEC (0x00000305ul) + #define VPRCSR_MTVEC_ResetValue (0x00000003UL) /*!< Reset value of MTVEC register. */ + +/* MODE @Bits 0..1 : Mode */ + #define VPRCSR_MTVEC_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define VPRCSR_MTVEC_MODE_Msk (0x3UL << VPRCSR_MTVEC_MODE_Pos) /*!< Bit mask of MODE field. */ + #define VPRCSR_MTVEC_MODE_Min (0x3UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_MTVEC_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_MTVEC_MODE_CLIC (0x3UL) /*!< Core Local Interrupt Controller (CLIC) interrupt handling mode */ + +/* BASE @Bits 2..31 : Vector base address */ + #define VPRCSR_MTVEC_BASE_Pos (2UL) /*!< Position of BASE field. */ + #define VPRCSR_MTVEC_BASE_Msk (0x3FFFFFFFUL << VPRCSR_MTVEC_BASE_Pos) /*!< Bit mask of BASE field. */ + + +/** + * @brief MTVT [VPRCSR_MTVT] Machine Trap Vector Table + */ + #define VPRCSR_MTVT (0x00000307ul) + #define VPRCSR_MTVT_ResetValue (0x00000000UL) /*!< Reset value of MTVT register. */ + +/* VAL @Bits 6..31 : Machine Trap Vector Table base address value for CLIC vectored interrupts */ + #define VPRCSR_MTVT_VAL_Pos (6UL) /*!< Position of VAL field. */ + #define VPRCSR_MTVT_VAL_Msk (0x3FFFFFFUL << VPRCSR_MTVT_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MCOUNTINHIBIT [VPRCSR_MCOUNTINHIBIT] Machine Counter-Inhibit + */ + #define VPRCSR_MCOUNTINHIBIT (0x00000320ul) + #define VPRCSR_MCOUNTINHIBIT_ResetValue (0x00000005UL) /*!< Reset value of MCOUNTINHIBIT register. */ + +/* CY @Bit 0 : (unspecified) */ + #define VPRCSR_MCOUNTINHIBIT_CY_Pos (0UL) /*!< Position of CY field. */ + #define VPRCSR_MCOUNTINHIBIT_CY_Msk (0x1UL << VPRCSR_MCOUNTINHIBIT_CY_Pos) /*!< Bit mask of CY field. */ + #define VPRCSR_MCOUNTINHIBIT_CY_Min (0x0UL) /*!< Min enumerator value of CY field. */ + #define VPRCSR_MCOUNTINHIBIT_CY_Max (0x1UL) /*!< Max enumerator value of CY field. */ + #define VPRCSR_MCOUNTINHIBIT_CY_INCREMENT (0x0UL) /*!< MCYCLE increments as usual */ + #define VPRCSR_MCOUNTINHIBIT_CY_INHIBIT (0x1UL) /*!< MCYCLE doesn't increment */ + +/* IR @Bit 2 : (unspecified) */ + #define VPRCSR_MCOUNTINHIBIT_IR_Pos (2UL) /*!< Position of IR field. */ + #define VPRCSR_MCOUNTINHIBIT_IR_Msk (0x1UL << VPRCSR_MCOUNTINHIBIT_IR_Pos) /*!< Bit mask of IR field. */ + #define VPRCSR_MCOUNTINHIBIT_IR_Min (0x0UL) /*!< Min enumerator value of IR field. */ + #define VPRCSR_MCOUNTINHIBIT_IR_Max (0x1UL) /*!< Max enumerator value of IR field. */ + #define VPRCSR_MCOUNTINHIBIT_IR_INCREMENT (0x0UL) /*!< MINSTRET increments as usual */ + #define VPRCSR_MCOUNTINHIBIT_IR_INHIBIT (0x1UL) /*!< MINSTRET doesn't increment */ + + +/** + * @brief MSCRATCH [VPRCSR_MSCRATCH] Machine Scratch + */ + #define VPRCSR_MSCRATCH (0x00000340ul) + #define VPRCSR_MSCRATCH_ResetValue (0x00000000UL) /*!< Reset value of MSCRATCH register. */ + +/* VAL @Bits 0..31 : Machine Scratch value */ + #define VPRCSR_MSCRATCH_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MSCRATCH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MSCRATCH_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MEPC [VPRCSR_MEPC] Machine Exception Program Counter + */ + #define VPRCSR_MEPC (0x00000341ul) + #define VPRCSR_MEPC_ResetValue (0x00000000UL) /*!< Reset value of MEPC register. */ + +/* VAL @Bits 0..31 : Machine Exception Program Counter value */ + #define VPRCSR_MEPC_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MEPC_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MEPC_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MCAUSE [VPRCSR_MCAUSE] Machine Cause + */ + #define VPRCSR_MCAUSE (0x00000342ul) + #define VPRCSR_MCAUSE_ResetValue (0x30000000UL) /*!< Reset value of MCAUSE register. */ + +/* EXCEPTIONCODE @Bits 0..11 : Exception code */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_Pos (0UL) /*!< Position of EXCEPTIONCODE field. */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_Msk (0xFFFUL << VPRCSR_MCAUSE_EXCEPTIONCODE_Pos) /*!< Bit mask of EXCEPTIONCODE field. */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_Min (0x000UL) /*!< Min enumerator value of EXCEPTIONCODE field. */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_Max (0x01FUL) /*!< Max enumerator value of EXCEPTIONCODE field. */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_INSTADDRMISALIGN (0x000UL) /*!< Instruction Address Misaligned */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_INSTACCESSFAULT (0x001UL) /*!< Instruction Access Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_ILLEGALINST (0x002UL) /*!< Illegal Instruction */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_BKPT (0x003UL) /*!< Breakpoint */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADADDRMISALIGN (0x004UL) /*!< Load Address Misaligned */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADACCESSFAULT (0x005UL) /*!< Load Access Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_STOREADDRMISALIGN (0x006UL) /*!< Store/AMO Address Misaligned */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_STOREACCESSFAULT (0x007UL) /*!< Store/AMO Access Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_ECALLMMODE (0x00BUL) /*!< Environment Call M-Mode */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_MISALIGNSTACKING (0x018UL) /*!< Misaligned Stacking */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_BUSFAULTSTACKING (0x019UL) /*!< Bus Fault on Stacking */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_INTVECTORFAULT (0x01AUL) /*!< Interrupt Vector Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_MISALIGNUNSTACKING (0x01BUL) /*!< Misaligned Unstacking */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_BUSFAULTUNSTACKING (0x01CUL) /*!< Bus Fault on Unstacking */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_STORETIMEOUTFAULT (0x01DUL) /*!< Store Timeout Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADTIMEOUTFAULT (0x01EUL) /*!< Load Timeout Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_STACKINGEXCFAULT (0x01FUL) /*!< Fault on Exception Stacking */ + +/* MPIL @Bits 16..23 : Previous interrupt level */ + #define VPRCSR_MCAUSE_MPIL_Pos (16UL) /*!< Position of MPIL field. */ + #define VPRCSR_MCAUSE_MPIL_Msk (0xFFUL << VPRCSR_MCAUSE_MPIL_Pos) /*!< Bit mask of MPIL field. */ + +/* MPIE @Bit 27 : Previous interrupt enable, same as MSTATUS.MPIE */ + #define VPRCSR_MCAUSE_MPIE_Pos (27UL) /*!< Position of MPIE field. */ + #define VPRCSR_MCAUSE_MPIE_Msk (0x1UL << VPRCSR_MCAUSE_MPIE_Pos) /*!< Bit mask of MPIE field. */ + +/* MPP @Bits 28..29 : Previous privilege mode, same as MSTATUS.MPP */ + #define VPRCSR_MCAUSE_MPP_Pos (28UL) /*!< Position of MPP field. */ + #define VPRCSR_MCAUSE_MPP_Msk (0x3UL << VPRCSR_MCAUSE_MPP_Pos) /*!< Bit mask of MPP field. */ + +/* MINHV @Bit 30 : In hardware vectoring */ + #define VPRCSR_MCAUSE_MINHV_Pos (30UL) /*!< Position of MINHV field. */ + #define VPRCSR_MCAUSE_MINHV_Msk (0x1UL << VPRCSR_MCAUSE_MINHV_Pos) /*!< Bit mask of MINHV field. */ + +/* INTERRUPT @Bit 31 : Interrupt bit */ + #define VPRCSR_MCAUSE_INTERRUPT_Pos (31UL) /*!< Position of INTERRUPT field. */ + #define VPRCSR_MCAUSE_INTERRUPT_Msk (0x1UL << VPRCSR_MCAUSE_INTERRUPT_Pos) /*!< Bit mask of INTERRUPT field. */ + #define VPRCSR_MCAUSE_INTERRUPT_Min (0x0UL) /*!< Min enumerator value of INTERRUPT field. */ + #define VPRCSR_MCAUSE_INTERRUPT_Max (0x1UL) /*!< Max enumerator value of INTERRUPT field. */ + #define VPRCSR_MCAUSE_INTERRUPT_EXCEPTION (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MCAUSE_INTERRUPT_INTERRUPT (0x1UL) /*!< (unspecified) */ + + +/** + * @brief MTVAL [VPRCSR_MTVAL] Machine Trap Value + */ + #define VPRCSR_MTVAL (0x00000343ul) + #define VPRCSR_MTVAL_ResetValue (0x00000000UL) /*!< Reset value of MTVAL register. */ + +/* VAL @Bits 0..31 : Machine Trap Value */ + #define VPRCSR_MTVAL_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MTVAL_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MTVAL_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MINTSTATUS [VPRCSR_MINTSTATUS] M-mode Interrupt Status + */ + #define VPRCSR_MINTSTATUS (0x00000346ul) + #define VPRCSR_MINTSTATUS_ResetValue (0x00000000UL) /*!< Reset value of MINTSTATUS register. */ + +/* MIL @Bits 24..31 : M-Mode interrupt level */ + #define VPRCSR_MINTSTATUS_MIL_Pos (24UL) /*!< Position of MIL field. */ + #define VPRCSR_MINTSTATUS_MIL_Msk (0xFFUL << VPRCSR_MINTSTATUS_MIL_Pos) /*!< Bit mask of MIL field. */ + + +/** + * @brief MINTTHRESH [VPRCSR_MINTTHRESH] M-mode Interrupt-level Threshold + */ + #define VPRCSR_MINTTHRESH (0x00000347ul) + #define VPRCSR_MINTTHRESH_ResetValue (0x0000001FUL) /*!< Reset value of MINTTHRESH register. */ + +/* TH @Bits 0..7 : M-Mode Interrupt-level Threshold */ + #define VPRCSR_MINTTHRESH_TH_Pos (0UL) /*!< Position of TH field. */ + #define VPRCSR_MINTTHRESH_TH_Msk (0xFFUL << VPRCSR_MINTTHRESH_TH_Pos) /*!< Bit mask of TH field. */ + #define VPRCSR_MINTTHRESH_TH_Min (0x00UL) /*!< Min enumerator value of TH field. */ + #define VPRCSR_MINTTHRESH_TH_Max (0xFFUL) /*!< Max enumerator value of TH field. */ + #define VPRCSR_MINTTHRESH_TH_DISABLED (0x00UL) /*!< Threshold disabled */ + #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL0 (0x3FUL) /*!< Threshold level 0 */ + #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL1 (0x7FUL) /*!< Threshold level 1 */ + #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL2 (0xBFUL) /*!< Threshold level 2 */ + #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL3 (0xFFUL) /*!< Threshold level 3 */ + + +/** + * @brief MCLICBASE [VPRCSR_MCLICBASE] Machine CLIC Base + */ + #define VPRCSR_MCLICBASE (0x00000350ul) + #define VPRCSR_MCLICBASE_ResetValue (0xF0000000UL) /*!< Reset value of MCLICBASE register. */ + +/* VAL @Bits 0..31 : CLIC base address value */ + #define VPRCSR_MCLICBASE_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MCLICBASE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCLICBASE_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief TSELECT [VPRCSR_TSELECT] Trigger Select + */ + #define VPRCSR_TSELECT (0x000007A0ul) + #define VPRCSR_TSELECT_ResetValue (0x00000000UL) /*!< Reset value of TSELECT register. */ + +/* VAL @Bits 0..31 : Trigger Select value */ + #define VPRCSR_TSELECT_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_TSELECT_VAL_Msk (0xFFFFFFFFUL << VPRCSR_TSELECT_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief TDATA1 [VPRCSR_TDATA1] Trigger Data 1 + */ + #define VPRCSR_TDATA1 (0x000007A1ul) + #define VPRCSR_TDATA1_ResetValue (0x00000000UL) /*!< Reset value of TDATA1 register. */ + +/* DATA @Bits 0..26 : Trigger Specific Data */ + #define VPRCSR_TDATA1_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPRCSR_TDATA1_DATA_Msk (0x7FFFFFFUL << VPRCSR_TDATA1_DATA_Pos) /*!< Bit mask of DATA field. */ + +/* DMODE @Bit 27 : Debug Mode */ + #define VPRCSR_TDATA1_DMODE_Pos (27UL) /*!< Position of DMODE field. */ + #define VPRCSR_TDATA1_DMODE_Msk (0x1UL << VPRCSR_TDATA1_DMODE_Pos) /*!< Bit mask of DMODE field. */ + #define VPRCSR_TDATA1_DMODE_Min (0x0UL) /*!< Min enumerator value of DMODE field. */ + #define VPRCSR_TDATA1_DMODE_Max (0x1UL) /*!< Max enumerator value of DMODE field. */ + #define VPRCSR_TDATA1_DMODE_BOTH (0x0UL) /*!< Both Debug and M-mode can write the tdata registers at the selected + tselect.*/ + #define VPRCSR_TDATA1_DMODE_ONLYDEBUG (0x1UL) /*!< Only Debug Mode can write the tdata registers at the selected tselect. + Writes from other modes are ignored.*/ + +/* TYPE @Bits 28..31 : Type */ + #define VPRCSR_TDATA1_TYPE_Pos (28UL) /*!< Position of TYPE field. */ + #define VPRCSR_TDATA1_TYPE_Msk (0xFUL << VPRCSR_TDATA1_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define VPRCSR_TDATA1_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define VPRCSR_TDATA1_TYPE_Max (0xFUL) /*!< Max enumerator value of TYPE field. */ + #define VPRCSR_TDATA1_TYPE_NOTRIGGER (0x0UL) /*!< There is no trigger at this tselect */ + #define VPRCSR_TDATA1_TYPE_MATCH (0x2UL) /*!< The trigger is an address match trigger. The remaining bits in this + register act as described in mcontrol*/ + #define VPRCSR_TDATA1_TYPE_REMAP (0xFUL) /*!< This trigger is a remapping trigger. The remaining bits in this + register behave as described in remapping functionality*/ + + +/** + * @brief TDATA2 [VPRCSR_TDATA2] Trigger Data 2 + */ + #define VPRCSR_TDATA2 (0x000007A2ul) + #define VPRCSR_TDATA2_ResetValue (0x00000000UL) /*!< Reset value of TDATA2 register. */ + +/* DATA @Bits 0..31 : Trigger Specific Data */ + #define VPRCSR_TDATA2_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPRCSR_TDATA2_DATA_Msk (0xFFFFFFFFUL << VPRCSR_TDATA2_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/** + * @brief TDATA3 [VPRCSR_TDATA3] Trigger Data 3 + */ + #define VPRCSR_TDATA3 (0x000007A3ul) + #define VPRCSR_TDATA3_ResetValue (0x00000000UL) /*!< Reset value of TDATA3 register. */ + +/* DATA @Bits 0..31 : Trigger Specific Data */ + #define VPRCSR_TDATA3_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPRCSR_TDATA3_DATA_Msk (0xFFFFFFFFUL << VPRCSR_TDATA3_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/** + * @brief TINFO [VPRCSR_TINFO] Trigger Info + */ + #define VPRCSR_TINFO (0x000007A4ul) + #define VPRCSR_TINFO_ResetValue (0x00000000UL) /*!< Reset value of TINFO register. */ + +/* INFO @Bits 0..15 : Trigger Info value */ + #define VPRCSR_TINFO_INFO_Pos (0UL) /*!< Position of INFO field. */ + #define VPRCSR_TINFO_INFO_Msk (0xFFFFUL << VPRCSR_TINFO_INFO_Pos) /*!< Bit mask of INFO field. */ + + +/** + * @brief TCONTROL [VPRCSR_TCONTROL] Trigger Control + */ + #define VPRCSR_TCONTROL (0x000007A5ul) + #define VPRCSR_TCONTROL_ResetValue (0x00000000UL) /*!< Reset value of TCONTROL register. */ + +/* MTE @Bit 3 : Mode Trigger Enable */ + #define VPRCSR_TCONTROL_MTE_Pos (3UL) /*!< Position of MTE field. */ + #define VPRCSR_TCONTROL_MTE_Msk (0x1UL << VPRCSR_TCONTROL_MTE_Pos) /*!< Bit mask of MTE field. */ + #define VPRCSR_TCONTROL_MTE_Min (0x0UL) /*!< Min enumerator value of MTE field. */ + #define VPRCSR_TCONTROL_MTE_Max (0x1UL) /*!< Max enumerator value of MTE field. */ + #define VPRCSR_TCONTROL_MTE_DONTMATCH (0x0UL) /*!< Triggers with action=0 do not match/fire while the hart is in M-mode */ + #define VPRCSR_TCONTROL_MTE_MATCH (0x1UL) /*!< Triggers do match/fire while the hart is in M-mode. When a trap into + M-mode is taken, mte is set to 0. When mret is executed, mte is set to + the value of mpte*/ + +/* MPTE @Bit 7 : Mode Previous Trigger Enable */ + #define VPRCSR_TCONTROL_MPTE_Pos (7UL) /*!< Position of MPTE field. */ + #define VPRCSR_TCONTROL_MPTE_Msk (0x1UL << VPRCSR_TCONTROL_MPTE_Pos) /*!< Bit mask of MPTE field. */ + + +/** + * @brief DCSR [VPRCSR_DCSR] Debug Control and Status + */ + #define VPRCSR_DCSR (0x000007B0ul) + #define VPRCSR_DCSR_ResetValue (0x40000003UL) /*!< Reset value of DCSR register. */ + +/* PRV @Bits 0..1 : Privilege level */ + #define VPRCSR_DCSR_PRV_Pos (0UL) /*!< Position of PRV field. */ + #define VPRCSR_DCSR_PRV_Msk (0x3UL << VPRCSR_DCSR_PRV_Pos) /*!< Bit mask of PRV field. */ + #define VPRCSR_DCSR_PRV_Min (0x3UL) /*!< Min enumerator value of PRV field. */ + #define VPRCSR_DCSR_PRV_Max (0x3UL) /*!< Max enumerator value of PRV field. */ + #define VPRCSR_DCSR_PRV_MACHINE (0x3UL) /*!< (unspecified) */ + +/* STEP @Bit 2 : Step */ + #define VPRCSR_DCSR_STEP_Pos (2UL) /*!< Position of STEP field. */ + #define VPRCSR_DCSR_STEP_Msk (0x1UL << VPRCSR_DCSR_STEP_Pos) /*!< Bit mask of STEP field. */ + +/* CAUSE @Bits 6..8 : Debug Mode enter cause */ + #define VPRCSR_DCSR_CAUSE_Pos (6UL) /*!< Position of CAUSE field. */ + #define VPRCSR_DCSR_CAUSE_Msk (0x7UL << VPRCSR_DCSR_CAUSE_Pos) /*!< Bit mask of CAUSE field. */ + #define VPRCSR_DCSR_CAUSE_Min (0x1UL) /*!< Min enumerator value of CAUSE field. */ + #define VPRCSR_DCSR_CAUSE_Max (0x5UL) /*!< Max enumerator value of CAUSE field. */ + #define VPRCSR_DCSR_CAUSE_EBREAK (0x1UL) /*!< An ebreak instruction was executed. (priority 3) */ + #define VPRCSR_DCSR_CAUSE_TRIGGER (0x2UL) /*!< The Trigger Module caused a breakpoint exception. (priority 4, + highest)*/ + #define VPRCSR_DCSR_CAUSE_HALTREQ (0x3UL) /*!< The debugger requested entry to Debug Mode using haltreq. (priority + 1)*/ + #define VPRCSR_DCSR_CAUSE_STEP (0x4UL) /*!< The hart single stepped because step was set. (priority 0, lowest) */ + #define VPRCSR_DCSR_CAUSE_RESETHALTREQ (0x5UL) /*!< The hart halted directly out of reset due to resethaltreq. It is also + acceptable to report 3 when this happens. (priority 2)*/ + +/* STEPIE @Bit 11 : Step Interrupt Enable */ + #define VPRCSR_DCSR_STEPIE_Pos (11UL) /*!< Position of STEPIE field. */ + #define VPRCSR_DCSR_STEPIE_Msk (0x1UL << VPRCSR_DCSR_STEPIE_Pos) /*!< Bit mask of STEPIE field. */ + #define VPRCSR_DCSR_STEPIE_Min (0x0UL) /*!< Min enumerator value of STEPIE field. */ + #define VPRCSR_DCSR_STEPIE_Max (0x1UL) /*!< Max enumerator value of STEPIE field. */ + #define VPRCSR_DCSR_STEPIE_Disabled (0x0UL) /*!< Interrupts are disabled during single stepping */ + #define VPRCSR_DCSR_STEPIE_Enabled (0x1UL) /*!< Interrupts are enabled during single stepping. Implementations may + hard wire this bit to 0. In that case interrupt behavior can be + emulated by the debugger.*/ + +/* EBREAKM @Bit 15 : M-mode ebreak */ + #define VPRCSR_DCSR_EBREAKM_Pos (15UL) /*!< Position of EBREAKM field. */ + #define VPRCSR_DCSR_EBREAKM_Msk (0x1UL << VPRCSR_DCSR_EBREAKM_Pos) /*!< Bit mask of EBREAKM field. */ + #define VPRCSR_DCSR_EBREAKM_Min (0x0UL) /*!< Min enumerator value of EBREAKM field. */ + #define VPRCSR_DCSR_EBREAKM_Max (0x1UL) /*!< Max enumerator value of EBREAKM field. */ + #define VPRCSR_DCSR_EBREAKM_SPEC (0x0UL) /*!< ebreak instructions in M-mode behave as described in the Privileged + Spe*/ + #define VPRCSR_DCSR_EBREAKM_ENTERDBG (0x1UL) /*!< ebreak instructions in M-mode enter Debug Mode */ + +/* XDEBUGVER @Bits 28..31 : External Debug version */ + #define VPRCSR_DCSR_XDEBUGVER_Pos (28UL) /*!< Position of XDEBUGVER field. */ + #define VPRCSR_DCSR_XDEBUGVER_Msk (0xFUL << VPRCSR_DCSR_XDEBUGVER_Pos) /*!< Bit mask of XDEBUGVER field. */ + #define VPRCSR_DCSR_XDEBUGVER_Min (0x4UL) /*!< Min enumerator value of XDEBUGVER field. */ + #define VPRCSR_DCSR_XDEBUGVER_Max (0x4UL) /*!< Max enumerator value of XDEBUGVER field. */ + #define VPRCSR_DCSR_XDEBUGVER_STDDBG (0x4UL) /*!< External debug support exists as it is described in this document */ + + +/** + * @brief DPC [VPRCSR_DPC] Debug PC + */ + #define VPRCSR_DPC (0x000007B1ul) + #define VPRCSR_DPC_ResetValue (0x00000000UL) /*!< Reset value of DPC register. */ + +/* VAL @Bits 0..31 : Debug PC value */ + #define VPRCSR_DPC_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_DPC_VAL_Msk (0xFFFFFFFFUL << VPRCSR_DPC_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MCYCLE [VPRCSR_MCYCLE] Machine Cycle Counter + */ + #define VPRCSR_MCYCLE (0x00000B00ul) + #define VPRCSR_MCYCLE_ResetValue (0x00000000UL) /*!< Reset value of MCYCLE register. */ + +/* VAL @Bits 0..31 : Machine Cycle Counter value */ + #define VPRCSR_MCYCLE_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MCYCLE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCYCLE_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MINSTRET [VPRCSR_MINSTRET] Machine Instruction Counter + */ + #define VPRCSR_MINSTRET (0x00000B02ul) + #define VPRCSR_MINSTRET_ResetValue (0x00000000UL) /*!< Reset value of MINSTRET register. */ + +/* VAL @Bits 0..31 : Machine Instruction Counter value */ + #define VPRCSR_MINSTRET_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MINSTRET_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MINSTRET_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MCYCLEH [VPRCSR_MCYCLEH] Machine Cycle Counter (Upper part) + */ + #define VPRCSR_MCYCLEH (0x00000B80ul) + #define VPRCSR_MCYCLEH_ResetValue (0x00000000UL) /*!< Reset value of MCYCLEH register. */ + +/* VAL @Bits 0..31 : Machine Cycle Counter value */ + #define VPRCSR_MCYCLEH_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MCYCLEH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCYCLEH_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MINSTRETH [VPRCSR_MINSTRETH] Machine Instruction Counter (Upper part) + */ + #define VPRCSR_MINSTRETH (0x00000B82ul) + #define VPRCSR_MINSTRETH_ResetValue (0x00000000UL) /*!< Reset value of MINSTRETH register. */ + +/* VAL @Bits 0..31 : Machine Instruction Counter (Upper part) value */ + #define VPRCSR_MINSTRETH_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MINSTRETH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MINSTRETH_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief UCYCLE [VPRCSR_UCYCLE] User Cycle Counter + */ + #define VPRCSR_UCYCLE (0x00000C00ul) + #define VPRCSR_UCYCLE_ResetValue (0x00000000UL) /*!< Reset value of UCYCLE register. */ + +/* VAL @Bits 0..31 : User Cycle Counter value */ + #define VPRCSR_UCYCLE_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_UCYCLE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UCYCLE_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief UINSTRET [VPRCSR_UINSTRET] User Instruction Counter + */ + #define VPRCSR_UINSTRET (0x00000C02ul) + #define VPRCSR_UINSTRET_ResetValue (0x00000000UL) /*!< Reset value of UINSTRET register. */ + +/* VAL @Bits 0..31 : User Instruction Counter value */ + #define VPRCSR_UINSTRET_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_UINSTRET_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UINSTRET_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief UCYCLEH [VPRCSR_UCYCLEH] User Cycle Counter (Upper part) + */ + #define VPRCSR_UCYCLEH (0x00000C80ul) + #define VPRCSR_UCYCLEH_ResetValue (0x00000000UL) /*!< Reset value of UCYCLEH register. */ + +/* VAL @Bits 0..31 : User Cycle Counter value */ + #define VPRCSR_UCYCLEH_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_UCYCLEH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UCYCLEH_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief UINSTRETH [VPRCSR_UINSTRETH] User Instruction Counter (Upper part) + */ + #define VPRCSR_UINSTRETH (0x00000C82ul) + #define VPRCSR_UINSTRETH_ResetValue (0x00000000UL) /*!< Reset value of UINSTRETH register. */ + +/* VAL @Bits 0..31 : User Instruction Counter (Upper part) value */ + #define VPRCSR_UINSTRETH_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_UINSTRETH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UINSTRETH_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MVENDORID [VPRCSR_MVENDORID] Machine Vendor ID + */ + #define VPRCSR_MVENDORID (0x00000F11ul) + #define VPRCSR_MVENDORID_ResetValue (0x00000144UL) /*!< Reset value of MVENDORID register. */ + +/* OFFSET @Bits 0..6 : MVENDORID encodes the final byte in the Offset field, discarding the parity bit */ + #define VPRCSR_MVENDORID_OFFSET_Pos (0UL) /*!< Position of OFFSET field. */ + #define VPRCSR_MVENDORID_OFFSET_Msk (0x7FUL << VPRCSR_MVENDORID_OFFSET_Pos) /*!< Bit mask of OFFSET field. */ + +/* BANK @Bits 7..31 : MVENDORID encodes the number of one-byte continuation codes in the Bank field */ + #define VPRCSR_MVENDORID_BANK_Pos (7UL) /*!< Position of BANK field. */ + #define VPRCSR_MVENDORID_BANK_Msk (0x1FFFFFFUL << VPRCSR_MVENDORID_BANK_Pos) /*!< Bit mask of BANK field. */ + + +/** + * @brief MARCHID [VPRCSR_MARCHID] Machine Architecture ID + */ + #define VPRCSR_MARCHID (0x00000F12ul) + #define VPRCSR_MARCHID_ResetValue (0x8000006EUL) /*!< Reset value of MARCHID register. */ + +/* MULDIV @Bits 0..1 : Indicates the MULDIV parameter option */ + #define VPRCSR_MARCHID_MULDIV_Pos (0UL) /*!< Position of MULDIV field. */ + #define VPRCSR_MARCHID_MULDIV_Msk (0x3UL << VPRCSR_MARCHID_MULDIV_Pos) /*!< Bit mask of MULDIV field. */ + +/* HIBERNATE @Bit 2 : Indicates the POWEROFFSLEEP parameter option */ + #define VPRCSR_MARCHID_HIBERNATE_Pos (2UL) /*!< Position of HIBERNATE field. */ + #define VPRCSR_MARCHID_HIBERNATE_Msk (0x1UL << VPRCSR_MARCHID_HIBERNATE_Pos) /*!< Bit mask of HIBERNATE field. */ + +/* DBG @Bit 3 : Indicates the DBG parameter option */ + #define VPRCSR_MARCHID_DBG_Pos (3UL) /*!< Position of DBG field. */ + #define VPRCSR_MARCHID_DBG_Msk (0x1UL << VPRCSR_MARCHID_DBG_Pos) /*!< Bit mask of DBG field. */ + +/* REMAP @Bit 4 : Indicates the REMAP parameter option */ + #define VPRCSR_MARCHID_REMAP_Pos (4UL) /*!< Position of REMAP field. */ + #define VPRCSR_MARCHID_REMAP_Msk (0x1UL << VPRCSR_MARCHID_REMAP_Pos) /*!< Bit mask of REMAP field. */ + +/* BUSWIDTH @Bit 5 : Indicates the BUS_WIDTH parameter option */ + #define VPRCSR_MARCHID_BUSWIDTH_Pos (5UL) /*!< Position of BUSWIDTH field. */ + #define VPRCSR_MARCHID_BUSWIDTH_Msk (0x1UL << VPRCSR_MARCHID_BUSWIDTH_Pos) /*!< Bit mask of BUSWIDTH field. */ + +/* BKPT @Bits 6..9 : Indicates the BKPT parameter option */ + #define VPRCSR_MARCHID_BKPT_Pos (6UL) /*!< Position of BKPT field. */ + #define VPRCSR_MARCHID_BKPT_Msk (0xFUL << VPRCSR_MARCHID_BKPT_Pos) /*!< Bit mask of BKPT field. */ + +/* CACHE @Bit 10 : Indicates that the CACHE is present */ + #define VPRCSR_MARCHID_CACHE_Pos (10UL) /*!< Position of CACHE field. */ + #define VPRCSR_MARCHID_CACHE_Msk (0x1UL << VPRCSR_MARCHID_CACHE_Pos) /*!< Bit mask of CACHE field. */ + +/* CACHEEXTRATAGBUF @Bits 11..13 : Indicates the number of extra TAG buffers in CACHE */ + #define VPRCSR_MARCHID_CACHEEXTRATAGBUF_Pos (11UL) /*!< Position of CACHEEXTRATAGBUF field. */ + #define VPRCSR_MARCHID_CACHEEXTRATAGBUF_Msk (0x7UL << VPRCSR_MARCHID_CACHEEXTRATAGBUF_Pos) /*!< Bit mask of CACHEEXTRATAGBUF + field.*/ + +/* RETAINED @Bit 16 : Indicates the RETAINED parameter option */ + #define VPRCSR_MARCHID_RETAINED_Pos (16UL) /*!< Position of RETAINED field. */ + #define VPRCSR_MARCHID_RETAINED_Msk (0x1UL << VPRCSR_MARCHID_RETAINED_Pos) /*!< Bit mask of RETAINED field. */ + +/* IMPLEM @Bit 31 : Indicates a non-open implementation */ + #define VPRCSR_MARCHID_IMPLEM_Pos (31UL) /*!< Position of IMPLEM field. */ + #define VPRCSR_MARCHID_IMPLEM_Msk (0x1UL << VPRCSR_MARCHID_IMPLEM_Pos) /*!< Bit mask of IMPLEM field. */ + + +/** + * @brief MIMPID [VPRCSR_MIMPID] Machine Implementation ID + */ + #define VPRCSR_MIMPID (0x00000F13ul) + #define VPRCSR_MIMPID_ResetValue (0x00010300UL) /*!< Reset value of MIMPID register. */ + +/* PATCHREV @Bits 0..7 : Indicates the number of the patch revision */ + #define VPRCSR_MIMPID_PATCHREV_Pos (0UL) /*!< Position of PATCHREV field. */ + #define VPRCSR_MIMPID_PATCHREV_Msk (0xFFUL << VPRCSR_MIMPID_PATCHREV_Pos) /*!< Bit mask of PATCHREV field. */ + +/* MINORREV @Bits 8..15 : Indicates the number of the minor revision */ + #define VPRCSR_MIMPID_MINORREV_Pos (8UL) /*!< Position of MINORREV field. */ + #define VPRCSR_MIMPID_MINORREV_Msk (0xFFUL << VPRCSR_MIMPID_MINORREV_Pos) /*!< Bit mask of MINORREV field. */ + +/* MAJORREV @Bits 16..23 : Indicates the number of the major revison */ + #define VPRCSR_MIMPID_MAJORREV_Pos (16UL) /*!< Position of MAJORREV field. */ + #define VPRCSR_MIMPID_MAJORREV_Msk (0xFFUL << VPRCSR_MIMPID_MAJORREV_Pos) /*!< Bit mask of MAJORREV field. */ + + +/** + * @brief MHARTID [VPRCSR_MHARTID] Machine Hart ID + */ + #define VPRCSR_MHARTID (0x00000F14ul) + #define VPRCSR_MHARTID_ResetValue (0x0000000EUL) /*!< Reset value of MHARTID register. */ + +/* HARTNUM @Bits 0..31 : Machine Hart ID value */ + #define VPRCSR_MHARTID_HARTNUM_Pos (0UL) /*!< Position of HARTNUM field. */ + #define VPRCSR_MHARTID_HARTNUM_Msk (0xFFFFFFFFUL << VPRCSR_MHARTID_HARTNUM_Pos) /*!< Bit mask of HARTNUM field. */ + + +/** + * @brief NORDIC [VPRCSR_NORDIC] (unspecified) + */ + +/** + * @brief VPRNORDICCTRL [VPRCSR_NORDIC_VPRNORDICCTRL] Nordic Core Control + */ + #define VPRCSR_NORDIC_VPRNORDICCTRL (0x000007C0ul) + #define VPRCSR_NORDIC_VPRNORDICCTRL_ResetValue (0x00000000UL) /*!< Reset value of VPRNORDICCTRL register. */ + +/* ENABLERTPERIPH @Bit 0 : Control bit to enable Real-Time Peripherals */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Pos (0UL) /*!< Position of ENABLERTPERIPH field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Pos) /*!< Bit mask + of ENABLERTPERIPH field.*/ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Min (0x0UL) /*!< Min enumerator value of ENABLERTPERIPH field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Max (0x1UL) /*!< Max enumerator value of ENABLERTPERIPH field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Enabled (0x1UL) /*!< (unspecified) */ + +/* ENABLEREMAP @Bit 3 : Enable remap feature */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Pos (3UL) /*!< Position of ENABLEREMAP field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Pos) /*!< Bit mask of + ENABLEREMAP field.*/ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Min (0x0UL) /*!< Min enumerator value of ENABLEREMAP field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Max (0x1UL) /*!< Max enumerator value of ENABLEREMAP field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Enabled (0x1UL) /*!< (unspecified) */ + +/* CNTIRQENABLE @Bit 6 : Enables the generation of IRQ number COUNTER_IRQ_NUM */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Pos (6UL) /*!< Position of CNTIRQENABLE field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Pos) /*!< Bit mask of + CNTIRQENABLE field.*/ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Min (0x0UL) /*!< Min enumerator value of CNTIRQENABLE field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Max (0x1UL) /*!< Max enumerator value of CNTIRQENABLE field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Enabled (0x1UL) /*!< (unspecified) */ + +/* VPRBUSPRI @Bit 7 : Arbitration priority on bus */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Pos (7UL) /*!< Position of VPRBUSPRI field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Pos) /*!< Bit mask of + VPRBUSPRI field.*/ + #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Min (0x0UL) /*!< Min enumerator value of VPRBUSPRI field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Max (0x1UL) /*!< Max enumerator value of VPRBUSPRI field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_LowPriority (0x0UL) /*!< Low priority for VPR RAM transactions on bus */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_HighPriority (0x1UL) /*!< High priority for VPR RAM transactions on bus */ + +/* NORDICKEY @Bits 16..31 : Used in order to protect the write to this register */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Pos (16UL) /*!< Position of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Msk (0xFFFFUL << VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Pos) /*!< Bit mask of + NORDICKEY field.*/ + #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Min (0x507DUL) /*!< Min enumerator value of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Max (0x507DUL) /*!< Max enumerator value of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Enabled (0x507DUL) /*!< Write enabled */ + + +/** + * @brief VPRNORDICSLEEPCTRL [VPRCSR_NORDIC_VPRNORDICSLEEPCTRL] Nordic Sleep Control + */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL (0x000007C1ul) + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_ResetValue (0x00000002UL) /*!< Reset value of VPRNORDICSLEEPCTRL register. */ + +/* SLEEPSTATE @Bits 0..3 : Sleep State */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Msk (0xFUL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Pos) /*!< Bit + mask of SLEEPSTATE field.*/ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Min (0x0UL) /*!< Min enumerator value of SLEEPSTATE field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Max (0xFUL) /*!< Max enumerator value of SLEEPSTATE field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_WAIT (0x0UL) /*!< Sleep is not turning off the clock */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_RESET (0x2UL) /*!< Sleep state default reset value. Going to sleep with + sleep state = RESET has the same effect as going to + sleep with sleep state = WAIT*/ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_SLEEP (0x5UL) /*!< Sleep is turning the clock off */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_DEEPSLEEP (0x7UL) /*!< Sleep is turning the clock off and power is turned + off*/ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_HIBERNATE (0xFUL) /*!< sleep is turning the clock off and all the + registers are saved automatically, restart by a + reset*/ + +/* RETURNTOSLEEP @Bit 16 : Return to Sleep */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Pos (16UL) /*!< Position of RETURNTOSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Pos) /*!< + Bit mask of RETURNTOSLEEP field.*/ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Min (0x0UL) /*!< Min enumerator value of RETURNTOSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Max (0x1UL) /*!< Max enumerator value of RETURNTOSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Enabled (0x1UL) /*!< (unspecified) */ + +/* STACKONSLEEP @Bit 17 : Stack on Sleep */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Pos (17UL) /*!< Position of STACKONSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Pos) /*!< + Bit mask of STACKONSLEEP field.*/ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Min (0x0UL) /*!< Min enumerator value of STACKONSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Max (0x1UL) /*!< Max enumerator value of STACKONSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Enabled (0x1UL) /*!< (unspecified) */ + + +/** + * @brief VPRNORDICFEATURESDISABLE [VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE] (unspecified) + */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE (0x000007C2ul) + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_ResetValue (0x00000002UL) /*!< Reset value of VPRNORDICFEATURESDISABLE + register.*/ + +/* DISABLECLICROUNDROBIN @Bit 3 : Disable CLIC Round Robin */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Pos (3UL) /*!< Position of DISABLECLICROUNDROBIN field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Pos) + /*!< Bit mask of DISABLECLICROUNDROBIN field.*/ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Min (0x0UL) /*!< Min enumerator value of + DISABLECLICROUNDROBIN field.*/ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Max (0x1UL) /*!< Max enumerator value of + DISABLECLICROUNDROBIN field.*/ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Enabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Disabled (0x1UL) /*!< (unspecified) */ + +/* UNRECOVRETURN @Bit 4 : Unrecoverable Return */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Pos (4UL) /*!< Position of UNRECOVRETURN field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Pos) + /*!< Bit mask of UNRECOVRETURN field.*/ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Min (0x0UL) /*!< Min enumerator value of UNRECOVRETURN field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Max (0x1UL) /*!< Max enumerator value of UNRECOVRETURN field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Enabled (0x1UL) /*!< (unspecified) */ + +/* NORDICKEY @Bits 16..31 : Used in order to protect the write to this register */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Pos (16UL) /*!< Position of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Msk (0xFFFFUL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Pos) + /*!< Bit mask of NORDICKEY field.*/ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Min (0x507DUL) /*!< Min enumerator value of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Max (0x507DUL) /*!< Max enumerator value of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Enabled (0x507DUL) /*!< Write enabled */ + + +/** + * @brief VIOPINS [VPRCSR_NORDIC_VIOPINS] VPR pins used for Real Time Peripherals VIO + */ + #define VPRCSR_NORDIC_VIOPINS (0x000007C3ul) + #define VPRCSR_NORDIC_VIOPINS_ResetValue (0x000007FFUL) /*!< Reset value of VIOPINS register. */ + +/* VAL @Bits 0..31 : VPR pins used for Real Time Peripherals VIO */ + #define VPRCSR_NORDIC_VIOPINS_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_VIOPINS_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_VIOPINS_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief EXTPARAMS [VPRCSR_NORDIC_EXTPARAMS] Reads values of external configuration parameters + */ + #define VPRCSR_NORDIC_EXTPARAMS (0x000007C4ul) + #define VPRCSR_NORDIC_EXTPARAMS_ResetValue (0x0000000EUL) /*!< Reset value of EXTPARAMS register. */ + +/* MULDIV @Bits 0..1 : value of MULDIV */ + #define VPRCSR_NORDIC_EXTPARAMS_MULDIV_Pos (0UL) /*!< Position of MULDIV field. */ + #define VPRCSR_NORDIC_EXTPARAMS_MULDIV_Msk (0x3UL << VPRCSR_NORDIC_EXTPARAMS_MULDIV_Pos) /*!< Bit mask of MULDIV field. */ + +/* DBG @Bit 2 : value of DBG */ + #define VPRCSR_NORDIC_EXTPARAMS_DBG_Pos (2UL) /*!< Position of DBG field. */ + #define VPRCSR_NORDIC_EXTPARAMS_DBG_Msk (0x1UL << VPRCSR_NORDIC_EXTPARAMS_DBG_Pos) /*!< Bit mask of DBG field. */ + +/* BKPT @Bits 3..6 : value of BKPT */ + #define VPRCSR_NORDIC_EXTPARAMS_BKPT_Pos (3UL) /*!< Position of BKPT field. */ + #define VPRCSR_NORDIC_EXTPARAMS_BKPT_Msk (0xFUL << VPRCSR_NORDIC_EXTPARAMS_BKPT_Pos) /*!< Bit mask of BKPT field. */ + +/* REMAP @Bit 7 : value of REMAP */ + #define VPRCSR_NORDIC_EXTPARAMS_REMAP_Pos (7UL) /*!< Position of REMAP field. */ + #define VPRCSR_NORDIC_EXTPARAMS_REMAP_Msk (0x1UL << VPRCSR_NORDIC_EXTPARAMS_REMAP_Pos) /*!< Bit mask of REMAP field. */ + + +/** + * @brief CACHE [VPRCSR_NORDIC_CACHE] (unspecified) + */ + +/** + * @brief AXCACHE [VPRCSR_NORDIC_CACHE_AXCACHE] Memory type encoding + */ + #define VPRCSR_NORDIC_CACHE_AXCACHE (0x000007C5ul) + #define VPRCSR_NORDIC_CACHE_AXCACHE_ResetValue (0x00000EEEUL) /*!< Reset value of AXCACHE register. */ + +/* AWCACHE @Bits 0..3 : Memory type for data stores */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_Pos (0UL) /*!< Position of AWCACHE field. */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_Msk (0xFUL << VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_Pos) /*!< Bit mask of AWCACHE + field.*/ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_Min (0x0UL) /*!< Min enumerator value of AWCACHE field. */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_Max (0xFUL) /*!< Max enumerator value of AWCACHE field. */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_DEVNONBUFF (0x0UL) /*!< Device Non-Bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_DEVBUFF (0x1UL) /*!< Device Bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_NNONCACHENONBUFF (0x2UL) /*!< Normal Non-cacheable Non-bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_NNONCACHEBUFF (0x3UL) /*!< Normal Non-cacheable Bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITETHNALLOC (0x6UL) /*!< Write-through No-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITETHRALLOC (0x6UL) /*!< Write-through Read-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITETHWALLOC (0xEUL) /*!< Write-through Write-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITETHRWALLOC (0xEUL) /*!< Write-through Read and Write-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITEBACKNALLOC (0x7UL) /*!< Write-back No-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITEBACKRALLOC (0x7UL) /*!< Write-back Read-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITEBACKWALLOC (0xFUL) /*!< Write-back Write-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITEBACKRWALLOC (0xFUL) /*!< Write-back Read and Write-allocate */ + +/* IARCACHE @Bits 4..7 : Memory type for instruction loads */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_Pos (4UL) /*!< Position of IARCACHE field. */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_Msk (0xFUL << VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_Pos) /*!< Bit mask of IARCACHE + field.*/ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_Min (0x0UL) /*!< Min enumerator value of IARCACHE field. */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_Max (0xFUL) /*!< Max enumerator value of IARCACHE field. */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_DEVNONBUFF (0x0UL) /*!< Device Non-Bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_DEVBUFF (0x1UL) /*!< Device Bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_NNONCACHENONBUFF (0x2UL) /*!< Normal Non-cacheable Non-bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_NNONCACHEBUFF (0x3UL) /*!< Normal Non-cacheable Bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITETHNALLOC (0xAUL) /*!< Write-through No-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITETHRALLOC (0xEUL) /*!< Write-through Read-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITETHWALLOC (0xAUL) /*!< Write-through Write-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITETHRWALLOC (0xEUL) /*!< Write-through Read and Write-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITEBACKNALLOC (0xBUL) /*!< Write-back No-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITEBACKRALLOC (0xFUL) /*!< Write-back Read-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITEBACKWALLOC (0xBUL) /*!< Write-back Write-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITEBACKRWALLOC (0xFUL) /*!< Write-back Read and Write-allocate */ + +/* DARCACHE @Bits 8..11 : Memory type for data loads */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_Pos (8UL) /*!< Position of DARCACHE field. */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_Msk (0xFUL << VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_Pos) /*!< Bit mask of DARCACHE + field.*/ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_Min (0x0UL) /*!< Min enumerator value of DARCACHE field. */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_Max (0xFUL) /*!< Max enumerator value of DARCACHE field. */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_DEVNONBUFF (0x0UL) /*!< Device Non-Bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_DEVBUFF (0x1UL) /*!< Device Bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_NNONCACHENONBUFF (0x2UL) /*!< Normal Non-cacheable Non-bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_NNONCACHEBUFF (0x3UL) /*!< Normal Non-cacheable Bufferable */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITETHNALLOC (0xAUL) /*!< Write-through No-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITETHRALLOC (0xEUL) /*!< Write-through Read-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITETHWALLOC (0xAUL) /*!< Write-through Write-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITETHRWALLOC (0xEUL) /*!< Write-through Read and Write-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITEBACKNALLOC (0xBUL) /*!< Write-back No-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITEBACKRALLOC (0xFUL) /*!< Write-back Read-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITEBACKWALLOC (0xBUL) /*!< Write-back Write-allocate */ + #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITEBACKRWALLOC (0xFUL) /*!< Write-back Read and Write-allocate */ + + +/** + * @brief CTRL [VPRCSR_NORDIC_CACHE_CTRL] Cache control + */ + #define VPRCSR_NORDIC_CACHE_CTRL (0x000007C8ul) + #define VPRCSR_NORDIC_CACHE_CTRL_ResetValue (0x00000000UL) /*!< Reset value of CTRL register. */ + +/* ENABLE @Bit 0 : Enable cache */ + #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Msk (0x1UL << VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Disabled (0x0UL) /*!< Cache disabled */ + #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Enabled (0x1UL) /*!< Cache enabled */ + +/* CACHECLR @Bit 16 : Cache clear */ + #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Pos (16UL) /*!< Position of CACHECLR field. */ + #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Msk (0x1UL << VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Pos) /*!< Bit mask of CACHECLR + field.*/ + #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Min (0x0UL) /*!< Min enumerator value of CACHECLR field. */ + #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Max (0x1UL) /*!< Max enumerator value of CACHECLR field. */ + #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_NoOperation (0x0UL) /*!< No Operation */ + #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Clear (0x1UL) /*!< Cache clear */ + + +/** + * @brief CFG [VPRCSR_NORDIC_CACHE_CFG] Cache configuration + */ + #define VPRCSR_NORDIC_CACHE_CFG (0x000007C9ul) + #define VPRCSR_NORDIC_CACHE_CFG_ResetValue (0x00000000UL) /*!< Reset value of CFG register. */ + +/* CACHESIZE @Bits 0..3 : Cache size is 2^CACHESIZE or (1 << CACHESIZE) KB, with a maximum size of 32KB (CACHESIZE = 5) */ + #define VPRCSR_NORDIC_CACHE_CFG_CACHESIZE_Pos (0UL) /*!< Position of CACHESIZE field. */ + #define VPRCSR_NORDIC_CACHE_CFG_CACHESIZE_Msk (0xFUL << VPRCSR_NORDIC_CACHE_CFG_CACHESIZE_Pos) /*!< Bit mask of CACHESIZE + field.*/ + #define VPRCSR_NORDIC_CACHE_CFG_CACHESIZE_Min (0x0UL) /*!< Min value of CACHESIZE field. */ + #define VPRCSR_NORDIC_CACHE_CFG_CACHESIZE_Max (0xFUL) /*!< Max size of CACHESIZE field. */ + +/* CACHELINESIZE @Bit 8 : Cache line size */ + #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_Pos (8UL) /*!< Position of CACHELINESIZE field. */ + #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_Msk (0x1UL << VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_Pos) /*!< Bit mask of + CACHELINESIZE field.*/ + #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_Min (0x0UL) /*!< Min enumerator value of CACHELINESIZE field. */ + #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_Max (0x1UL) /*!< Max enumerator value of CACHELINESIZE field. */ + #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_CachelineSize32B (0x0UL) /*!< Cache line size is 32 bytes (4 data units) */ + #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_CachelineSize64B (0x1UL) /*!< Cache line size is 64 bytes (8 data units) */ + + +/** + * @brief DATATAGADDR [VPRCSR_NORDIC_CACHE_DATATAGADDR] Cache tag base address + */ + #define VPRCSR_NORDIC_CACHE_DATATAGADDR (0x000007CAul) + #define VPRCSR_NORDIC_CACHE_DATATAGADDR_ResetValue (0x00000000UL) /*!< Reset value of DATATAGADDR register. */ + +/* VAL @Bits 0..31 : Cache tag base address value */ + #define VPRCSR_NORDIC_CACHE_DATATAGADDR_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CACHE_DATATAGADDR_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CACHE_DATATAGADDR_VAL_Pos) /*!< Bit mask of VAL + field.*/ + #define VPRCSR_NORDIC_CACHE_DATATAGADDR_VAL_Min (0x00000000UL) /*!< Min value of VAL field. */ + #define VPRCSR_NORDIC_CACHE_DATATAGADDR_VAL_Max (0xFFFFFFFCUL) /*!< Max size of VAL field. */ + + +/** + * @brief DATABASEADDR [VPRCSR_NORDIC_CACHE_DATABASEADDR] Cache data base address + */ + #define VPRCSR_NORDIC_CACHE_DATABASEADDR (0x000007CBul) + #define VPRCSR_NORDIC_CACHE_DATABASEADDR_ResetValue (0x00000000UL) /*!< Reset value of DATABASEADDR register. */ + +/* VAL @Bits 0..31 : Cache data base address value */ + #define VPRCSR_NORDIC_CACHE_DATABASEADDR_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CACHE_DATABASEADDR_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CACHE_DATABASEADDR_VAL_Pos) /*!< Bit mask of + VAL field.*/ + #define VPRCSR_NORDIC_CACHE_DATABASEADDR_VAL_Min (0x00000000UL) /*!< Min value of VAL field. */ + #define VPRCSR_NORDIC_CACHE_DATABASEADDR_VAL_Max (0xFFFFFFFCUL) /*!< Max size of VAL field. */ + + +/** + * @brief RTPERIPHCTRL [VPRCSR_NORDIC_RTPERIPHCTRL] RT peripheral control + */ + #define VPRCSR_NORDIC_RTPERIPHCTRL (0x000007CCul) + #define VPRCSR_NORDIC_RTPERIPHCTRL_ResetValue (0x00000000UL) /*!< Reset value of RTPERIPHCTRL register. */ + +/* CLOCKPOLARITY @Bit 0 : Clock polarity */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Pos (0UL) /*!< Position of CLOCKPOLARITY field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Pos) /*!< Bit mask of + CLOCKPOLARITY field.*/ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Min (0x0UL) /*!< Min enumerator value of CLOCKPOLARITY field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Max (0x1UL) /*!< Max enumerator value of CLOCKPOLARITY field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Low (0x0UL) /*!< Clock polarity is low */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_High (0x1UL) /*!< Clock polarity is High */ + +/* STOPCOUNTERS @Bit 4 : Stop counters CNT0 and CNT1 on OUTB under-run, or on INB Overflow if OUTMODE2 and INMODE2 */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Pos (4UL) /*!< Position of STOPCOUNTERS field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Pos) /*!< Bit mask of + STOPCOUNTERS field.*/ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Min (0x0UL) /*!< Min enumerator value of STOPCOUNTERS field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Max (0x1UL) /*!< Max enumerator value of STOPCOUNTERS field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_NoStop (0x0UL) /*!< Counters do not stop on OUTB under-run */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Stop (0x1UL) /*!< Counters stop on OUTB under-run */ + +/* INSEL @Bit 8 : Input pin selection */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Pos (8UL) /*!< Position of INSEL field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Pos) /*!< Bit mask of INSEL field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Min (0x0UL) /*!< Min enumerator value of INSEL field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Max (0x1UL) /*!< Max enumerator value of INSEL field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_SamePin (0x0UL) /*!< Sample on same OUT pin */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_SeparatePin (0x1UL) /*!< Sample on separate pin */ + +/* EVPINSEL @Bits 12..15 : Event pin select */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVPINSEL_Pos (12UL) /*!< Position of EVPINSEL field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVPINSEL_Msk (0xFUL << VPRCSR_NORDIC_RTPERIPHCTRL_EVPINSEL_Pos) /*!< Bit mask of EVPINSEL + field.*/ + +/* EVEDGE @Bits 16..17 : Event pin edge */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVEDGE_Pos (16UL) /*!< Position of EVEDGE field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVEDGE_Msk (0x3UL << VPRCSR_NORDIC_RTPERIPHCTRL_EVEDGE_Pos) /*!< Bit mask of EVEDGE field.*/ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVEDGE_Min (0x0UL) /*!< Min enumerator value of EVEDGE field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVEDGE_Max (0x2UL) /*!< Max enumerator value of EVEDGE field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVEDGE_AnyEdge (0x0UL) /*!< Any edge */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVEDGE_RisingEdge (0x1UL) /*!< Rising edge */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVEDGE_FallingEdge (0x2UL) /*!< Falling edge */ + +/* EVSAMPLE @Bit 20 : Event pin sampling */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVSAMPLE_Pos (20UL) /*!< Position of EVSAMPLE field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVSAMPLE_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHCTRL_EVSAMPLE_Pos) /*!< Bit mask of EVSAMPLE + field.*/ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVSAMPLE_Min (0x0UL) /*!< Min enumerator value of EVSAMPLE field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVSAMPLE_Max (0x1UL) /*!< Max enumerator value of EVSAMPLE field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVSAMPLE_Continuous (0x0UL) /*!< Sample continuously */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_EVSAMPLE_Event (0x1UL) /*!< Sample on CNT1 event */ + + +/** + * @brief RTPERIPHSTATUS [VPRCSR_NORDIC_RTPERIPHSTATUS] Real-Time Peripheral Status + */ + #define VPRCSR_NORDIC_RTPERIPHSTATUS (0x000007CDul) + #define VPRCSR_NORDIC_RTPERIPHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of RTPERIPHSTATUS register. */ + +/* OUTBUNDERRUN @Bit 0 : Set if OUTB value is not written in time for the next shift out event, which means OUT data is not + valid. Can only be cleared by SW by writing a 1 to the bit. */ + + #define VPRCSR_NORDIC_RTPERIPHSTATUS_OUTBUNDERRUN_Pos (0UL) /*!< Position of OUTBUNDERRUN field. */ + #define VPRCSR_NORDIC_RTPERIPHSTATUS_OUTBUNDERRUN_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHSTATUS_OUTBUNDERRUN_Pos) /*!< Bit mask + of OUTBUNDERRUN field.*/ + +/* INBOVERRUN @Bit 1 : Set if INB value is not read in time for the next shift in event, which means IN data is lost. Can only + be cleared by SW by writing a 1 to the bit. */ + + #define VPRCSR_NORDIC_RTPERIPHSTATUS_INBOVERRUN_Pos (1UL) /*!< Position of INBOVERRUN field. */ + #define VPRCSR_NORDIC_RTPERIPHSTATUS_INBOVERRUN_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHSTATUS_INBOVERRUN_Pos) /*!< Bit mask of + INBOVERRUN field.*/ + + +/** + * @brief CNTMODE0 [VPRCSR_NORDIC_CNTMODE0] CNT0 Mode + */ + #define VPRCSR_NORDIC_CNTMODE0 (0x000007D0ul) + #define VPRCSR_NORDIC_CNTMODE0_ResetValue (0x00000000UL) /*!< Reset value of CNTMODE0 register. */ + +/* CNTMODE0 @Bits 0..2 : CNT0 Mode */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Pos (0UL) /*!< Position of CNTMODE0 field. */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Msk (0x7UL << VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Pos) /*!< Bit mask of CNTMODE0 field. */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Min (0x0UL) /*!< Min enumerator value of CNTMODE0 field. */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Max (0x5UL) /*!< Max enumerator value of CNTMODE0 field. */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_STOP (0x0UL) /*!< CNT0 stops at 0 */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_WRAP (0x1UL) /*!< When CNT0 reaches 0 it will continue counting from 0xFFFF */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_RELOAD (0x2UL) /*!< When CNT0 reaches 0 it will continue counting from the value in + CNTTOP*/ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_TRIGCOMB (0x3UL) /*!< When CNT0 reaches 0 it is reloaded from CNTTOP and stops. + Counting will restart when a VIO event happens*/ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_TRIGWRAP (0x5UL) /*!< When the counter reaches 0 it wraps to MAX and stops. Counting + will restart when a VIO event happens*/ + + +/** + * @brief CNTMODE1 [VPRCSR_NORDIC_CNTMODE1] CNT1 Mode + */ + #define VPRCSR_NORDIC_CNTMODE1 (0x000007D1ul) + #define VPRCSR_NORDIC_CNTMODE1_ResetValue (0x00000000UL) /*!< Reset value of CNTMODE1 register. */ + +/* CNTMODE1 @Bits 0..2 : CNT1 Mode */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Pos (0UL) /*!< Position of CNTMODE1 field. */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Msk (0x7UL << VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Pos) /*!< Bit mask of CNTMODE1 field. */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Min (0x0UL) /*!< Min enumerator value of CNTMODE1 field. */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Max (0x5UL) /*!< Max enumerator value of CNTMODE1 field. */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_STOP (0x0UL) /*!< CNT1 stops at 0 */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_WRAP (0x1UL) /*!< When CNT1 reaches 0 it will continue counting from 0xFFFF */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_RELOAD (0x2UL) /*!< When CNT1 reches 0 it will continue counting from the value in + CNTTOP*/ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_TRIGCOMB (0x3UL) /*!< In combine mode mode CNT1 acts as an extension of CNT0 (16 most + significant bits of the 32-bit CNT)*/ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_TRIGRELOAD (0x4UL) /*!< When CNT1 reaches 0 it is reloaded from CNTTOP and stops. + Counting will restart when a VIO event happens*/ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_TRIGWRAP (0x5UL) /*!< When CNT1 reaches 0 it wraps to MAX and stops. Counting will + restart when a VIO event happens*/ + + +/** + * @brief CNT [VPRCSR_NORDIC_CNT] 32-bit Counter + */ + #define VPRCSR_NORDIC_CNT (0x000007D2ul) + #define VPRCSR_NORDIC_CNT_ResetValue (0x00000000UL) /*!< Reset value of CNT register. */ + +/* CNT0 @Bits 0..15 : 16-bit Counter 0 */ + #define VPRCSR_NORDIC_CNT_CNT0_Pos (0UL) /*!< Position of CNT0 field. */ + #define VPRCSR_NORDIC_CNT_CNT0_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT_CNT0_Pos) /*!< Bit mask of CNT0 field. */ + +/* CNT1 @Bits 16..31 : 16-bit Counter 1 */ + #define VPRCSR_NORDIC_CNT_CNT1_Pos (16UL) /*!< Position of CNT1 field. */ + #define VPRCSR_NORDIC_CNT_CNT1_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT_CNT1_Pos) /*!< Bit mask of CNT1 field. */ + + +/** + * @brief CNTTOP [VPRCSR_NORDIC_CNTTOP] Counter Top + */ + #define VPRCSR_NORDIC_CNTTOP (0x000007D3ul) + #define VPRCSR_NORDIC_CNTTOP_ResetValue (0x00000000UL) /*!< Reset value of CNTTOP register. */ + +/* CNT0RELOAD @Bits 0..15 : Reload value for CNT0 */ + #define VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Pos (0UL) /*!< Position of CNT0RELOAD field. */ + #define VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Msk (0xFFFFUL << VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Pos) /*!< Bit mask of CNT0RELOAD + field.*/ + +/* CNT1RELOAD @Bits 16..31 : Reload value for CNT1 */ + #define VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Pos (16UL) /*!< Position of CNT1RELOAD field. */ + #define VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Msk (0xFFFFUL << VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Pos) /*!< Bit mask of CNT1RELOAD + field.*/ + + +/** + * @brief CNTADD [VPRCSR_NORDIC_CNTADD] CNT Add + */ + #define VPRCSR_NORDIC_CNTADD (0x000007D4ul) + #define VPRCSR_NORDIC_CNTADD_ResetValue (0x00000000UL) /*!< Reset value of CNTADD register. */ + +/* VAL @Bits 0..31 : Value added to CNT */ + #define VPRCSR_NORDIC_CNTADD_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CNTADD_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief CNT0 [VPRCSR_NORDIC_CNT0] 16 bit Counter 0 + */ + #define VPRCSR_NORDIC_CNT0 (0x000007D5ul) + #define VPRCSR_NORDIC_CNT0_ResetValue (0x00000000UL) /*!< Reset value of CNT0 register. */ + +/* VAL @Bits 0..15 : CNT0 value */ + #define VPRCSR_NORDIC_CNT0_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CNT0_VAL_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT0_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief CNTADD0 [VPRCSR_NORDIC_CNTADD0] CNT0 Add + */ + #define VPRCSR_NORDIC_CNTADD0 (0x000007D6ul) + #define VPRCSR_NORDIC_CNTADD0_ResetValue (0x00000000UL) /*!< Reset value of CNTADD0 register. */ + +/* VAL @Bits 0..31 : Value added to CNT0 */ + #define VPRCSR_NORDIC_CNTADD0_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CNTADD0_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD0_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief CNT1 [VPRCSR_NORDIC_CNT1] 16-bit Counter 1 + */ + #define VPRCSR_NORDIC_CNT1 (0x000007D7ul) + #define VPRCSR_NORDIC_CNT1_ResetValue (0x00000000UL) /*!< Reset value of CNT1 register. */ + +/* VAL @Bits 0..15 : CNT1 value */ + #define VPRCSR_NORDIC_CNT1_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CNT1_VAL_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT1_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief CNTADD1 [VPRCSR_NORDIC_CNTADD1] CNT1 Add + */ + #define VPRCSR_NORDIC_CNTADD1 (0x000007D8ul) + #define VPRCSR_NORDIC_CNTADD1_ResetValue (0x00000000UL) /*!< Reset value of CNTADD1 register. */ + +/* VAL @Bits 0..31 : Value added to CNT1 */ + #define VPRCSR_NORDIC_CNTADD1_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CNTADD1_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD1_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief WAIT0 [VPRCSR_NORDIC_WAIT0] Wait 0 + */ + #define VPRCSR_NORDIC_WAIT0 (0x000007DAul) + #define VPRCSR_NORDIC_WAIT0_ResetValue (0x00000000UL) /*!< Reset value of WAIT0 register. */ + +/* DATA @Bits 0..15 : Value to write to CNT0 */ + #define VPRCSR_NORDIC_WAIT0_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPRCSR_NORDIC_WAIT0_DATA_Msk (0xFFFFUL << VPRCSR_NORDIC_WAIT0_DATA_Pos) /*!< Bit mask of DATA field. */ + +/* WRITEDATA @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Pos (16UL) /*!< Position of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Msk (0x1UL << VPRCSR_NORDIC_WAIT0_WRITEDATA_Pos) /*!< Bit mask of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Min (0x0UL) /*!< Min enumerator value of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Max (0x1UL) /*!< Max enumerator value of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_WAIT (0x0UL) /*!< Wait until CNT0 reaches 0 */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_WRITE (0x1UL) /*!< Write DATA to CNT0 and then wait until CNT0 reaches 0 */ + + +/** + * @brief WAIT1 [VPRCSR_NORDIC_WAIT1] Wait 1 + */ + #define VPRCSR_NORDIC_WAIT1 (0x000007DBul) + #define VPRCSR_NORDIC_WAIT1_ResetValue (0x00000000UL) /*!< Reset value of WAIT1 register. */ + +/* DATA @Bits 0..15 : Value to write to CNT1 */ + #define VPRCSR_NORDIC_WAIT1_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPRCSR_NORDIC_WAIT1_DATA_Msk (0xFFFFUL << VPRCSR_NORDIC_WAIT1_DATA_Pos) /*!< Bit mask of DATA field. */ + +/* WRITEDATA @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Pos (16UL) /*!< Position of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Msk (0x1UL << VPRCSR_NORDIC_WAIT1_WRITEDATA_Pos) /*!< Bit mask of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Min (0x0UL) /*!< Min enumerator value of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Max (0x1UL) /*!< Max enumerator value of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_WAIT (0x0UL) /*!< Wait until CNT1 reaches 0 */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_WRITE (0x1UL) /*!< Write DATA to CNT1 and then wait until CNT1 reaches 0 */ + + +/** + * @brief WAIT [VPRCSR_NORDIC_WAIT] Wait + */ + #define VPRCSR_NORDIC_WAIT (0x000007DCul) + #define VPRCSR_NORDIC_WAIT_ResetValue (0x00000000UL) /*!< Reset value of WAIT register. */ + +/* VAL @Bits 0..31 : (unspecified) */ + #define VPRCSR_NORDIC_WAIT_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_WAIT_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_WAIT_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief TASKS [VPRCSR_NORDIC_TASKS] DPPI Tasks + */ + #define VPRCSR_NORDIC_TASKS (0x000007E0ul) + #define VPRCSR_NORDIC_TASKS_ResetValue (0x00000000UL) /*!< Reset value of TASKS register. */ + +/* TASKS0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Pos (0UL) /*!< Position of TASKS0 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS0_Pos) /*!< Bit mask of TASKS0 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Min (0x0UL) /*!< Min enumerator value of TASKS0 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Max (0x1UL) /*!< Max enumerator value of TASKS0 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Disabled (0x0UL) /*!< TASKS[0] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Enabled (0x1UL) /*!< TASKS[0] enabled */ + +/* TASKS1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Pos (1UL) /*!< Position of TASKS1 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS1_Pos) /*!< Bit mask of TASKS1 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Min (0x0UL) /*!< Min enumerator value of TASKS1 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Max (0x1UL) /*!< Max enumerator value of TASKS1 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Disabled (0x0UL) /*!< TASKS[1] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Enabled (0x1UL) /*!< TASKS[1] enabled */ + +/* TASKS2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Pos (2UL) /*!< Position of TASKS2 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS2_Pos) /*!< Bit mask of TASKS2 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Min (0x0UL) /*!< Min enumerator value of TASKS2 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Max (0x1UL) /*!< Max enumerator value of TASKS2 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Disabled (0x0UL) /*!< TASKS[2] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Enabled (0x1UL) /*!< TASKS[2] enabled */ + +/* TASKS3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Pos (3UL) /*!< Position of TASKS3 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS3_Pos) /*!< Bit mask of TASKS3 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Min (0x0UL) /*!< Min enumerator value of TASKS3 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Max (0x1UL) /*!< Max enumerator value of TASKS3 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Disabled (0x0UL) /*!< TASKS[3] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Enabled (0x1UL) /*!< TASKS[3] enabled */ + +/* TASKS4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Pos (4UL) /*!< Position of TASKS4 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS4_Pos) /*!< Bit mask of TASKS4 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Min (0x0UL) /*!< Min enumerator value of TASKS4 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Max (0x1UL) /*!< Max enumerator value of TASKS4 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Disabled (0x0UL) /*!< TASKS[4] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Enabled (0x1UL) /*!< TASKS[4] enabled */ + +/* TASKS5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Pos (5UL) /*!< Position of TASKS5 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS5_Pos) /*!< Bit mask of TASKS5 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Min (0x0UL) /*!< Min enumerator value of TASKS5 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Max (0x1UL) /*!< Max enumerator value of TASKS5 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Disabled (0x0UL) /*!< TASKS[5] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Enabled (0x1UL) /*!< TASKS[5] enabled */ + +/* TASKS6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Pos (6UL) /*!< Position of TASKS6 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS6_Pos) /*!< Bit mask of TASKS6 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Min (0x0UL) /*!< Min enumerator value of TASKS6 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Max (0x1UL) /*!< Max enumerator value of TASKS6 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Disabled (0x0UL) /*!< TASKS[6] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Enabled (0x1UL) /*!< TASKS[6] enabled */ + +/* TASKS7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Pos (7UL) /*!< Position of TASKS7 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS7_Pos) /*!< Bit mask of TASKS7 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Min (0x0UL) /*!< Min enumerator value of TASKS7 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Max (0x1UL) /*!< Max enumerator value of TASKS7 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Disabled (0x0UL) /*!< TASKS[7] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Enabled (0x1UL) /*!< TASKS[7] enabled */ + +/* TASKS8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Pos (8UL) /*!< Position of TASKS8 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS8_Pos) /*!< Bit mask of TASKS8 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Min (0x0UL) /*!< Min enumerator value of TASKS8 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Max (0x1UL) /*!< Max enumerator value of TASKS8 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Disabled (0x0UL) /*!< TASKS[8] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Enabled (0x1UL) /*!< TASKS[8] enabled */ + +/* TASKS9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Pos (9UL) /*!< Position of TASKS9 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS9_Pos) /*!< Bit mask of TASKS9 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Min (0x0UL) /*!< Min enumerator value of TASKS9 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Max (0x1UL) /*!< Max enumerator value of TASKS9 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Disabled (0x0UL) /*!< TASKS[9] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Enabled (0x1UL) /*!< TASKS[9] enabled */ + +/* TASKS10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Pos (10UL) /*!< Position of TASKS10 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS10_Pos) /*!< Bit mask of TASKS10 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Min (0x0UL) /*!< Min enumerator value of TASKS10 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Max (0x1UL) /*!< Max enumerator value of TASKS10 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Disabled (0x0UL) /*!< TASKS[10] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Enabled (0x1UL) /*!< TASKS[10] enabled */ + +/* TASKS11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Pos (11UL) /*!< Position of TASKS11 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS11_Pos) /*!< Bit mask of TASKS11 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Min (0x0UL) /*!< Min enumerator value of TASKS11 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Max (0x1UL) /*!< Max enumerator value of TASKS11 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Disabled (0x0UL) /*!< TASKS[11] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Enabled (0x1UL) /*!< TASKS[11] enabled */ + +/* TASKS12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Pos (12UL) /*!< Position of TASKS12 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS12_Pos) /*!< Bit mask of TASKS12 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Min (0x0UL) /*!< Min enumerator value of TASKS12 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Max (0x1UL) /*!< Max enumerator value of TASKS12 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Disabled (0x0UL) /*!< TASKS[12] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Enabled (0x1UL) /*!< TASKS[12] enabled */ + +/* TASKS13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Pos (13UL) /*!< Position of TASKS13 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS13_Pos) /*!< Bit mask of TASKS13 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Min (0x0UL) /*!< Min enumerator value of TASKS13 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Max (0x1UL) /*!< Max enumerator value of TASKS13 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Disabled (0x0UL) /*!< TASKS[13] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Enabled (0x1UL) /*!< TASKS[13] enabled */ + +/* TASKS14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Pos (14UL) /*!< Position of TASKS14 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS14_Pos) /*!< Bit mask of TASKS14 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Min (0x0UL) /*!< Min enumerator value of TASKS14 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Max (0x1UL) /*!< Max enumerator value of TASKS14 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Disabled (0x0UL) /*!< TASKS[14] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Enabled (0x1UL) /*!< TASKS[14] enabled */ + +/* TASKS15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Pos (15UL) /*!< Position of TASKS15 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS15_Pos) /*!< Bit mask of TASKS15 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Min (0x0UL) /*!< Min enumerator value of TASKS15 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Max (0x1UL) /*!< Max enumerator value of TASKS15 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Disabled (0x0UL) /*!< TASKS[15] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Enabled (0x1UL) /*!< TASKS[15] enabled */ + +/* TASKS16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Pos (16UL) /*!< Position of TASKS16 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS16_Pos) /*!< Bit mask of TASKS16 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Min (0x0UL) /*!< Min enumerator value of TASKS16 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Max (0x1UL) /*!< Max enumerator value of TASKS16 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Disabled (0x0UL) /*!< TASKS[16] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Enabled (0x1UL) /*!< TASKS[16] enabled */ + +/* TASKS17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Pos (17UL) /*!< Position of TASKS17 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS17_Pos) /*!< Bit mask of TASKS17 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Min (0x0UL) /*!< Min enumerator value of TASKS17 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Max (0x1UL) /*!< Max enumerator value of TASKS17 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Disabled (0x0UL) /*!< TASKS[17] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Enabled (0x1UL) /*!< TASKS[17] enabled */ + +/* TASKS18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Pos (18UL) /*!< Position of TASKS18 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS18_Pos) /*!< Bit mask of TASKS18 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Min (0x0UL) /*!< Min enumerator value of TASKS18 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Max (0x1UL) /*!< Max enumerator value of TASKS18 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Disabled (0x0UL) /*!< TASKS[18] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Enabled (0x1UL) /*!< TASKS[18] enabled */ + +/* TASKS19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Pos (19UL) /*!< Position of TASKS19 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS19_Pos) /*!< Bit mask of TASKS19 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Min (0x0UL) /*!< Min enumerator value of TASKS19 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Max (0x1UL) /*!< Max enumerator value of TASKS19 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Disabled (0x0UL) /*!< TASKS[19] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Enabled (0x1UL) /*!< TASKS[19] enabled */ + +/* TASKS20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Pos (20UL) /*!< Position of TASKS20 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS20_Pos) /*!< Bit mask of TASKS20 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Min (0x0UL) /*!< Min enumerator value of TASKS20 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Max (0x1UL) /*!< Max enumerator value of TASKS20 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Disabled (0x0UL) /*!< TASKS[20] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Enabled (0x1UL) /*!< TASKS[20] enabled */ + +/* TASKS21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Pos (21UL) /*!< Position of TASKS21 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS21_Pos) /*!< Bit mask of TASKS21 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Min (0x0UL) /*!< Min enumerator value of TASKS21 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Max (0x1UL) /*!< Max enumerator value of TASKS21 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Disabled (0x0UL) /*!< TASKS[21] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Enabled (0x1UL) /*!< TASKS[21] enabled */ + +/* TASKS22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Pos (22UL) /*!< Position of TASKS22 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS22_Pos) /*!< Bit mask of TASKS22 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Min (0x0UL) /*!< Min enumerator value of TASKS22 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Max (0x1UL) /*!< Max enumerator value of TASKS22 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Disabled (0x0UL) /*!< TASKS[22] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Enabled (0x1UL) /*!< TASKS[22] enabled */ + +/* TASKS23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Pos (23UL) /*!< Position of TASKS23 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS23_Pos) /*!< Bit mask of TASKS23 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Min (0x0UL) /*!< Min enumerator value of TASKS23 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Max (0x1UL) /*!< Max enumerator value of TASKS23 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Disabled (0x0UL) /*!< TASKS[23] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Enabled (0x1UL) /*!< TASKS[23] enabled */ + +/* TASKS24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Pos (24UL) /*!< Position of TASKS24 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS24_Pos) /*!< Bit mask of TASKS24 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Min (0x0UL) /*!< Min enumerator value of TASKS24 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Max (0x1UL) /*!< Max enumerator value of TASKS24 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Disabled (0x0UL) /*!< TASKS[24] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Enabled (0x1UL) /*!< TASKS[24] enabled */ + +/* TASKS25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Pos (25UL) /*!< Position of TASKS25 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS25_Pos) /*!< Bit mask of TASKS25 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Min (0x0UL) /*!< Min enumerator value of TASKS25 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Max (0x1UL) /*!< Max enumerator value of TASKS25 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Disabled (0x0UL) /*!< TASKS[25] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Enabled (0x1UL) /*!< TASKS[25] enabled */ + +/* TASKS26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Pos (26UL) /*!< Position of TASKS26 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS26_Pos) /*!< Bit mask of TASKS26 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Min (0x0UL) /*!< Min enumerator value of TASKS26 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Max (0x1UL) /*!< Max enumerator value of TASKS26 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Disabled (0x0UL) /*!< TASKS[26] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Enabled (0x1UL) /*!< TASKS[26] enabled */ + +/* TASKS27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Pos (27UL) /*!< Position of TASKS27 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS27_Pos) /*!< Bit mask of TASKS27 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Min (0x0UL) /*!< Min enumerator value of TASKS27 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Max (0x1UL) /*!< Max enumerator value of TASKS27 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Disabled (0x0UL) /*!< TASKS[27] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Enabled (0x1UL) /*!< TASKS[27] enabled */ + +/* TASKS28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Pos (28UL) /*!< Position of TASKS28 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS28_Pos) /*!< Bit mask of TASKS28 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Min (0x0UL) /*!< Min enumerator value of TASKS28 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Max (0x1UL) /*!< Max enumerator value of TASKS28 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Disabled (0x0UL) /*!< TASKS[28] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Enabled (0x1UL) /*!< TASKS[28] enabled */ + +/* TASKS29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Pos (29UL) /*!< Position of TASKS29 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS29_Pos) /*!< Bit mask of TASKS29 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Min (0x0UL) /*!< Min enumerator value of TASKS29 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Max (0x1UL) /*!< Max enumerator value of TASKS29 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Disabled (0x0UL) /*!< TASKS[29] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Enabled (0x1UL) /*!< TASKS[29] enabled */ + +/* TASKS30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Pos (30UL) /*!< Position of TASKS30 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS30_Pos) /*!< Bit mask of TASKS30 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Min (0x0UL) /*!< Min enumerator value of TASKS30 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Max (0x1UL) /*!< Max enumerator value of TASKS30 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Disabled (0x0UL) /*!< TASKS[30] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Enabled (0x1UL) /*!< TASKS[30] enabled */ + +/* TASKS31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Pos (31UL) /*!< Position of TASKS31 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS31_Pos) /*!< Bit mask of TASKS31 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Min (0x0UL) /*!< Min enumerator value of TASKS31 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Max (0x1UL) /*!< Max enumerator value of TASKS31 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Disabled (0x0UL) /*!< TASKS[31] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Enabled (0x1UL) /*!< TASKS[31] enabled */ + + +/** + * @brief SUBSCRIBE [VPRCSR_NORDIC_SUBSCRIBE] Enable Task Subscription + */ + #define VPRCSR_NORDIC_SUBSCRIBE (0x000007E1ul) + #define VPRCSR_NORDIC_SUBSCRIBE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE register. */ + +/* SUBSCRIBE16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos (16UL) /*!< Position of SUBSCRIBE16 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos) /*!< Bit mask of + SUBSCRIBE16 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE16 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE16 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Disabled (0x0UL) /*!< Subscribe disabled for TASK[16] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Enabled (0x1UL) /*!< Subscribe enabled for TASK[16] */ + +/* SUBSCRIBE17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos (17UL) /*!< Position of SUBSCRIBE17 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos) /*!< Bit mask of + SUBSCRIBE17 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE17 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE17 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Disabled (0x0UL) /*!< Subscribe disabled for TASK[17] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Enabled (0x1UL) /*!< Subscribe enabled for TASK[17] */ + +/* SUBSCRIBE18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos (18UL) /*!< Position of SUBSCRIBE18 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos) /*!< Bit mask of + SUBSCRIBE18 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE18 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE18 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Disabled (0x0UL) /*!< Subscribe disabled for TASK[18] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Enabled (0x1UL) /*!< Subscribe enabled for TASK[18] */ + +/* SUBSCRIBE19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos (19UL) /*!< Position of SUBSCRIBE19 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos) /*!< Bit mask of + SUBSCRIBE19 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE19 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE19 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Disabled (0x0UL) /*!< Subscribe disabled for TASK[19] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Enabled (0x1UL) /*!< Subscribe enabled for TASK[19] */ + + +/** + * @brief EVENTS [VPRCSR_NORDIC_EVENTS] DPPI Events + */ + #define VPRCSR_NORDIC_EVENTS (0x000007E2ul) + #define VPRCSR_NORDIC_EVENTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS register. */ + +/* EVENTS0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Pos (0UL) /*!< Position of EVENTS0 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS0_Pos) /*!< Bit mask of EVENTS0 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Min (0x0UL) /*!< Min enumerator value of EVENTS0 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Max (0x1UL) /*!< Max enumerator value of EVENTS0 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Disabled (0x0UL) /*!< EVENTS[0] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Enabled (0x1UL) /*!< EVENTS[0] enabled */ + +/* EVENTS1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Pos (1UL) /*!< Position of EVENTS1 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS1_Pos) /*!< Bit mask of EVENTS1 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Min (0x0UL) /*!< Min enumerator value of EVENTS1 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Max (0x1UL) /*!< Max enumerator value of EVENTS1 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Disabled (0x0UL) /*!< EVENTS[1] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Enabled (0x1UL) /*!< EVENTS[1] enabled */ + +/* EVENTS2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Pos (2UL) /*!< Position of EVENTS2 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS2_Pos) /*!< Bit mask of EVENTS2 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Min (0x0UL) /*!< Min enumerator value of EVENTS2 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Max (0x1UL) /*!< Max enumerator value of EVENTS2 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Disabled (0x0UL) /*!< EVENTS[2] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Enabled (0x1UL) /*!< EVENTS[2] enabled */ + +/* EVENTS3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Pos (3UL) /*!< Position of EVENTS3 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS3_Pos) /*!< Bit mask of EVENTS3 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Min (0x0UL) /*!< Min enumerator value of EVENTS3 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Max (0x1UL) /*!< Max enumerator value of EVENTS3 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Disabled (0x0UL) /*!< EVENTS[3] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Enabled (0x1UL) /*!< EVENTS[3] enabled */ + +/* EVENTS4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Pos (4UL) /*!< Position of EVENTS4 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS4_Pos) /*!< Bit mask of EVENTS4 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Min (0x0UL) /*!< Min enumerator value of EVENTS4 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Max (0x1UL) /*!< Max enumerator value of EVENTS4 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Disabled (0x0UL) /*!< EVENTS[4] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Enabled (0x1UL) /*!< EVENTS[4] enabled */ + +/* EVENTS5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Pos (5UL) /*!< Position of EVENTS5 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS5_Pos) /*!< Bit mask of EVENTS5 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Min (0x0UL) /*!< Min enumerator value of EVENTS5 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Max (0x1UL) /*!< Max enumerator value of EVENTS5 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Disabled (0x0UL) /*!< EVENTS[5] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Enabled (0x1UL) /*!< EVENTS[5] enabled */ + +/* EVENTS6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Pos (6UL) /*!< Position of EVENTS6 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS6_Pos) /*!< Bit mask of EVENTS6 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Min (0x0UL) /*!< Min enumerator value of EVENTS6 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Max (0x1UL) /*!< Max enumerator value of EVENTS6 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Disabled (0x0UL) /*!< EVENTS[6] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Enabled (0x1UL) /*!< EVENTS[6] enabled */ + +/* EVENTS7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Pos (7UL) /*!< Position of EVENTS7 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS7_Pos) /*!< Bit mask of EVENTS7 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Min (0x0UL) /*!< Min enumerator value of EVENTS7 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Max (0x1UL) /*!< Max enumerator value of EVENTS7 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Disabled (0x0UL) /*!< EVENTS[7] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Enabled (0x1UL) /*!< EVENTS[7] enabled */ + +/* EVENTS8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Pos (8UL) /*!< Position of EVENTS8 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS8_Pos) /*!< Bit mask of EVENTS8 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Min (0x0UL) /*!< Min enumerator value of EVENTS8 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Max (0x1UL) /*!< Max enumerator value of EVENTS8 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Disabled (0x0UL) /*!< EVENTS[8] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Enabled (0x1UL) /*!< EVENTS[8] enabled */ + +/* EVENTS9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Pos (9UL) /*!< Position of EVENTS9 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS9_Pos) /*!< Bit mask of EVENTS9 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Min (0x0UL) /*!< Min enumerator value of EVENTS9 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Max (0x1UL) /*!< Max enumerator value of EVENTS9 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Disabled (0x0UL) /*!< EVENTS[9] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Enabled (0x1UL) /*!< EVENTS[9] enabled */ + +/* EVENTS10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Pos (10UL) /*!< Position of EVENTS10 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS10_Pos) /*!< Bit mask of EVENTS10 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Min (0x0UL) /*!< Min enumerator value of EVENTS10 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Max (0x1UL) /*!< Max enumerator value of EVENTS10 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Disabled (0x0UL) /*!< EVENTS[10] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Enabled (0x1UL) /*!< EVENTS[10] enabled */ + +/* EVENTS11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Pos (11UL) /*!< Position of EVENTS11 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS11_Pos) /*!< Bit mask of EVENTS11 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Min (0x0UL) /*!< Min enumerator value of EVENTS11 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Max (0x1UL) /*!< Max enumerator value of EVENTS11 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Disabled (0x0UL) /*!< EVENTS[11] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Enabled (0x1UL) /*!< EVENTS[11] enabled */ + +/* EVENTS12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Pos (12UL) /*!< Position of EVENTS12 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS12_Pos) /*!< Bit mask of EVENTS12 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Min (0x0UL) /*!< Min enumerator value of EVENTS12 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Max (0x1UL) /*!< Max enumerator value of EVENTS12 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Disabled (0x0UL) /*!< EVENTS[12] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Enabled (0x1UL) /*!< EVENTS[12] enabled */ + +/* EVENTS13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Pos (13UL) /*!< Position of EVENTS13 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS13_Pos) /*!< Bit mask of EVENTS13 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Min (0x0UL) /*!< Min enumerator value of EVENTS13 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Max (0x1UL) /*!< Max enumerator value of EVENTS13 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Disabled (0x0UL) /*!< EVENTS[13] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Enabled (0x1UL) /*!< EVENTS[13] enabled */ + +/* EVENTS14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Pos (14UL) /*!< Position of EVENTS14 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS14_Pos) /*!< Bit mask of EVENTS14 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Min (0x0UL) /*!< Min enumerator value of EVENTS14 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Max (0x1UL) /*!< Max enumerator value of EVENTS14 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Disabled (0x0UL) /*!< EVENTS[14] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Enabled (0x1UL) /*!< EVENTS[14] enabled */ + +/* EVENTS15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Pos (15UL) /*!< Position of EVENTS15 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS15_Pos) /*!< Bit mask of EVENTS15 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Min (0x0UL) /*!< Min enumerator value of EVENTS15 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Max (0x1UL) /*!< Max enumerator value of EVENTS15 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Disabled (0x0UL) /*!< EVENTS[15] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Enabled (0x1UL) /*!< EVENTS[15] enabled */ + +/* EVENTS16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Pos (16UL) /*!< Position of EVENTS16 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS16_Pos) /*!< Bit mask of EVENTS16 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Min (0x0UL) /*!< Min enumerator value of EVENTS16 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Max (0x1UL) /*!< Max enumerator value of EVENTS16 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Disabled (0x0UL) /*!< EVENTS[16] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Enabled (0x1UL) /*!< EVENTS[16] enabled */ + +/* EVENTS17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Pos (17UL) /*!< Position of EVENTS17 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS17_Pos) /*!< Bit mask of EVENTS17 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Min (0x0UL) /*!< Min enumerator value of EVENTS17 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Max (0x1UL) /*!< Max enumerator value of EVENTS17 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Disabled (0x0UL) /*!< EVENTS[17] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Enabled (0x1UL) /*!< EVENTS[17] enabled */ + +/* EVENTS18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Pos (18UL) /*!< Position of EVENTS18 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS18_Pos) /*!< Bit mask of EVENTS18 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Min (0x0UL) /*!< Min enumerator value of EVENTS18 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Max (0x1UL) /*!< Max enumerator value of EVENTS18 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Disabled (0x0UL) /*!< EVENTS[18] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Enabled (0x1UL) /*!< EVENTS[18] enabled */ + +/* EVENTS19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Pos (19UL) /*!< Position of EVENTS19 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS19_Pos) /*!< Bit mask of EVENTS19 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Min (0x0UL) /*!< Min enumerator value of EVENTS19 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Max (0x1UL) /*!< Max enumerator value of EVENTS19 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Disabled (0x0UL) /*!< EVENTS[19] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Enabled (0x1UL) /*!< EVENTS[19] enabled */ + +/* EVENTS20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Pos (20UL) /*!< Position of EVENTS20 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS20_Pos) /*!< Bit mask of EVENTS20 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Min (0x0UL) /*!< Min enumerator value of EVENTS20 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Max (0x1UL) /*!< Max enumerator value of EVENTS20 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Disabled (0x0UL) /*!< EVENTS[20] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Enabled (0x1UL) /*!< EVENTS[20] enabled */ + +/* EVENTS21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Pos (21UL) /*!< Position of EVENTS21 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS21_Pos) /*!< Bit mask of EVENTS21 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Min (0x0UL) /*!< Min enumerator value of EVENTS21 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Max (0x1UL) /*!< Max enumerator value of EVENTS21 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Disabled (0x0UL) /*!< EVENTS[21] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Enabled (0x1UL) /*!< EVENTS[21] enabled */ + +/* EVENTS22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Pos (22UL) /*!< Position of EVENTS22 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS22_Pos) /*!< Bit mask of EVENTS22 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Min (0x0UL) /*!< Min enumerator value of EVENTS22 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Max (0x1UL) /*!< Max enumerator value of EVENTS22 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Disabled (0x0UL) /*!< EVENTS[22] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Enabled (0x1UL) /*!< EVENTS[22] enabled */ + +/* EVENTS23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Pos (23UL) /*!< Position of EVENTS23 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS23_Pos) /*!< Bit mask of EVENTS23 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Min (0x0UL) /*!< Min enumerator value of EVENTS23 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Max (0x1UL) /*!< Max enumerator value of EVENTS23 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Disabled (0x0UL) /*!< EVENTS[23] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Enabled (0x1UL) /*!< EVENTS[23] enabled */ + +/* EVENTS24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Pos (24UL) /*!< Position of EVENTS24 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS24_Pos) /*!< Bit mask of EVENTS24 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Min (0x0UL) /*!< Min enumerator value of EVENTS24 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Max (0x1UL) /*!< Max enumerator value of EVENTS24 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Disabled (0x0UL) /*!< EVENTS[24] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Enabled (0x1UL) /*!< EVENTS[24] enabled */ + +/* EVENTS25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Pos (25UL) /*!< Position of EVENTS25 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS25_Pos) /*!< Bit mask of EVENTS25 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Min (0x0UL) /*!< Min enumerator value of EVENTS25 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Max (0x1UL) /*!< Max enumerator value of EVENTS25 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Disabled (0x0UL) /*!< EVENTS[25] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Enabled (0x1UL) /*!< EVENTS[25] enabled */ + +/* EVENTS26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Pos (26UL) /*!< Position of EVENTS26 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS26_Pos) /*!< Bit mask of EVENTS26 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Min (0x0UL) /*!< Min enumerator value of EVENTS26 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Max (0x1UL) /*!< Max enumerator value of EVENTS26 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Disabled (0x0UL) /*!< EVENTS[26] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Enabled (0x1UL) /*!< EVENTS[26] enabled */ + +/* EVENTS27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Pos (27UL) /*!< Position of EVENTS27 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS27_Pos) /*!< Bit mask of EVENTS27 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Min (0x0UL) /*!< Min enumerator value of EVENTS27 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Max (0x1UL) /*!< Max enumerator value of EVENTS27 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Disabled (0x0UL) /*!< EVENTS[27] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Enabled (0x1UL) /*!< EVENTS[27] enabled */ + +/* EVENTS28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Pos (28UL) /*!< Position of EVENTS28 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS28_Pos) /*!< Bit mask of EVENTS28 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Min (0x0UL) /*!< Min enumerator value of EVENTS28 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Max (0x1UL) /*!< Max enumerator value of EVENTS28 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Disabled (0x0UL) /*!< EVENTS[28] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Enabled (0x1UL) /*!< EVENTS[28] enabled */ + +/* EVENTS29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Pos (29UL) /*!< Position of EVENTS29 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS29_Pos) /*!< Bit mask of EVENTS29 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Min (0x0UL) /*!< Min enumerator value of EVENTS29 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Max (0x1UL) /*!< Max enumerator value of EVENTS29 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Disabled (0x0UL) /*!< EVENTS[29] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Enabled (0x1UL) /*!< EVENTS[29] enabled */ + +/* EVENTS30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Pos (30UL) /*!< Position of EVENTS30 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS30_Pos) /*!< Bit mask of EVENTS30 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Min (0x0UL) /*!< Min enumerator value of EVENTS30 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Max (0x1UL) /*!< Max enumerator value of EVENTS30 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Disabled (0x0UL) /*!< EVENTS[30] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Enabled (0x1UL) /*!< EVENTS[30] enabled */ + +/* EVENTS31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Pos (31UL) /*!< Position of EVENTS31 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS31_Pos) /*!< Bit mask of EVENTS31 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Min (0x0UL) /*!< Min enumerator value of EVENTS31 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Max (0x1UL) /*!< Max enumerator value of EVENTS31 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Disabled (0x0UL) /*!< EVENTS[31] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Enabled (0x1UL) /*!< EVENTS[31] enabled */ + + +/** + * @brief PUBLISH [VPRCSR_NORDIC_PUBLISH] Enable Event Publication + */ + #define VPRCSR_NORDIC_PUBLISH (0x000007E3ul) + #define VPRCSR_NORDIC_PUBLISH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH register. */ + +/* PUBLISH16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos (16UL) /*!< Position of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos) /*!< Bit mask of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Min (0x0UL) /*!< Min enumerator value of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Max (0x1UL) /*!< Max enumerator value of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Disabled (0x0UL) /*!< Publish disabled for EVENTS[16] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Enabled (0x1UL) /*!< Publish enabled for EVENTS[16] */ + +/* PUBLISH17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos (17UL) /*!< Position of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos) /*!< Bit mask of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Min (0x0UL) /*!< Min enumerator value of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Max (0x1UL) /*!< Max enumerator value of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Disabled (0x0UL) /*!< Publish disabled for EVENTS[17] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Enabled (0x1UL) /*!< Publish enabled for EVENTS[17] */ + +/* PUBLISH18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos (18UL) /*!< Position of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos) /*!< Bit mask of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Min (0x0UL) /*!< Min enumerator value of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Max (0x1UL) /*!< Max enumerator value of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Disabled (0x0UL) /*!< Publish disabled for EVENTS[18] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Enabled (0x1UL) /*!< Publish enabled for EVENTS[18] */ + +/* PUBLISH19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos (19UL) /*!< Position of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos) /*!< Bit mask of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Min (0x0UL) /*!< Min enumerator value of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Max (0x1UL) /*!< Max enumerator value of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Disabled (0x0UL) /*!< Publish disabled for EVENTS[19] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Enabled (0x1UL) /*!< Publish enabled for EVENTS[19] */ + + +/** + * @brief INTEN [VPRCSR_NORDIC_INTEN] DPPI Event Interrupt Enable + */ + #define VPRCSR_NORDIC_INTEN (0x000007E4ul) + #define VPRCSR_NORDIC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* INTEN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Pos (0UL) /*!< Position of INTEN0 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN0_Pos) /*!< Bit mask of INTEN0 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Min (0x0UL) /*!< Min enumerator value of INTEN0 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Max (0x1UL) /*!< Max enumerator value of INTEN0 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[0] */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[0] */ + +/* INTEN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Pos (1UL) /*!< Position of INTEN1 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN1_Pos) /*!< Bit mask of INTEN1 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Min (0x0UL) /*!< Min enumerator value of INTEN1 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Max (0x1UL) /*!< Max enumerator value of INTEN1 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[1] */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[1] */ + +/* INTEN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Pos (2UL) /*!< Position of INTEN2 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN2_Pos) /*!< Bit mask of INTEN2 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Min (0x0UL) /*!< Min enumerator value of INTEN2 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Max (0x1UL) /*!< Max enumerator value of INTEN2 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[2] */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[2] */ + +/* INTEN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Pos (3UL) /*!< Position of INTEN3 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN3_Pos) /*!< Bit mask of INTEN3 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Min (0x0UL) /*!< Min enumerator value of INTEN3 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Max (0x1UL) /*!< Max enumerator value of INTEN3 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[3] */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[3] */ + +/* INTEN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Pos (4UL) /*!< Position of INTEN4 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN4_Pos) /*!< Bit mask of INTEN4 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Min (0x0UL) /*!< Min enumerator value of INTEN4 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Max (0x1UL) /*!< Max enumerator value of INTEN4 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[4] */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[4] */ + +/* INTEN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Pos (5UL) /*!< Position of INTEN5 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN5_Pos) /*!< Bit mask of INTEN5 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Min (0x0UL) /*!< Min enumerator value of INTEN5 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Max (0x1UL) /*!< Max enumerator value of INTEN5 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[5] */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[5] */ + +/* INTEN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Pos (6UL) /*!< Position of INTEN6 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN6_Pos) /*!< Bit mask of INTEN6 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Min (0x0UL) /*!< Min enumerator value of INTEN6 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Max (0x1UL) /*!< Max enumerator value of INTEN6 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[6] */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[6] */ + +/* INTEN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Pos (7UL) /*!< Position of INTEN7 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN7_Pos) /*!< Bit mask of INTEN7 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Min (0x0UL) /*!< Min enumerator value of INTEN7 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Max (0x1UL) /*!< Max enumerator value of INTEN7 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[7] */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[7] */ + +/* INTEN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Pos (8UL) /*!< Position of INTEN8 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN8_Pos) /*!< Bit mask of INTEN8 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Min (0x0UL) /*!< Min enumerator value of INTEN8 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Max (0x1UL) /*!< Max enumerator value of INTEN8 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[8] */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[8] */ + +/* INTEN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Pos (9UL) /*!< Position of INTEN9 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN9_Pos) /*!< Bit mask of INTEN9 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Min (0x0UL) /*!< Min enumerator value of INTEN9 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Max (0x1UL) /*!< Max enumerator value of INTEN9 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[9] */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[9] */ + +/* INTEN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Pos (10UL) /*!< Position of INTEN10 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN10_Pos) /*!< Bit mask of INTEN10 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Min (0x0UL) /*!< Min enumerator value of INTEN10 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Max (0x1UL) /*!< Max enumerator value of INTEN10 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[10] */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[10] */ + +/* INTEN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Pos (11UL) /*!< Position of INTEN11 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN11_Pos) /*!< Bit mask of INTEN11 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Min (0x0UL) /*!< Min enumerator value of INTEN11 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Max (0x1UL) /*!< Max enumerator value of INTEN11 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[11] */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[11] */ + +/* INTEN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Pos (12UL) /*!< Position of INTEN12 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN12_Pos) /*!< Bit mask of INTEN12 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Min (0x0UL) /*!< Min enumerator value of INTEN12 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Max (0x1UL) /*!< Max enumerator value of INTEN12 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[12] */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[12] */ + +/* INTEN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Pos (13UL) /*!< Position of INTEN13 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN13_Pos) /*!< Bit mask of INTEN13 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Min (0x0UL) /*!< Min enumerator value of INTEN13 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Max (0x1UL) /*!< Max enumerator value of INTEN13 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[13] */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[13] */ + +/* INTEN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Pos (14UL) /*!< Position of INTEN14 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN14_Pos) /*!< Bit mask of INTEN14 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Min (0x0UL) /*!< Min enumerator value of INTEN14 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Max (0x1UL) /*!< Max enumerator value of INTEN14 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[14] */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[14] */ + +/* INTEN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Pos (15UL) /*!< Position of INTEN15 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN15_Pos) /*!< Bit mask of INTEN15 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Min (0x0UL) /*!< Min enumerator value of INTEN15 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Max (0x1UL) /*!< Max enumerator value of INTEN15 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[15] */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[15] */ + +/* INTEN16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Pos (16UL) /*!< Position of INTEN16 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN16_Pos) /*!< Bit mask of INTEN16 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Min (0x0UL) /*!< Min enumerator value of INTEN16 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Max (0x1UL) /*!< Max enumerator value of INTEN16 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[16] */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[16] */ + +/* INTEN17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Pos (17UL) /*!< Position of INTEN17 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN17_Pos) /*!< Bit mask of INTEN17 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Min (0x0UL) /*!< Min enumerator value of INTEN17 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Max (0x1UL) /*!< Max enumerator value of INTEN17 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[17] */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[17] */ + +/* INTEN18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Pos (18UL) /*!< Position of INTEN18 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN18_Pos) /*!< Bit mask of INTEN18 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Min (0x0UL) /*!< Min enumerator value of INTEN18 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Max (0x1UL) /*!< Max enumerator value of INTEN18 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[18] */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[18] */ + +/* INTEN19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Pos (19UL) /*!< Position of INTEN19 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN19_Pos) /*!< Bit mask of INTEN19 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Min (0x0UL) /*!< Min enumerator value of INTEN19 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Max (0x1UL) /*!< Max enumerator value of INTEN19 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[19] */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[19] */ + +/* INTEN20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Pos (20UL) /*!< Position of INTEN20 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN20_Pos) /*!< Bit mask of INTEN20 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Min (0x0UL) /*!< Min enumerator value of INTEN20 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Max (0x1UL) /*!< Max enumerator value of INTEN20 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[20] */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[20] */ + +/* INTEN21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Pos (21UL) /*!< Position of INTEN21 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN21_Pos) /*!< Bit mask of INTEN21 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Min (0x0UL) /*!< Min enumerator value of INTEN21 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Max (0x1UL) /*!< Max enumerator value of INTEN21 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[21] */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[21] */ + +/* INTEN22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Pos (22UL) /*!< Position of INTEN22 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN22_Pos) /*!< Bit mask of INTEN22 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Min (0x0UL) /*!< Min enumerator value of INTEN22 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Max (0x1UL) /*!< Max enumerator value of INTEN22 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[22] */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[22] */ + +/* INTEN23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Pos (23UL) /*!< Position of INTEN23 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN23_Pos) /*!< Bit mask of INTEN23 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Min (0x0UL) /*!< Min enumerator value of INTEN23 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Max (0x1UL) /*!< Max enumerator value of INTEN23 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[23] */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[23] */ + +/* INTEN24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Pos (24UL) /*!< Position of INTEN24 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN24_Pos) /*!< Bit mask of INTEN24 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Min (0x0UL) /*!< Min enumerator value of INTEN24 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Max (0x1UL) /*!< Max enumerator value of INTEN24 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[24] */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[24] */ + +/* INTEN25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Pos (25UL) /*!< Position of INTEN25 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN25_Pos) /*!< Bit mask of INTEN25 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Min (0x0UL) /*!< Min enumerator value of INTEN25 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Max (0x1UL) /*!< Max enumerator value of INTEN25 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[25] */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[25] */ + +/* INTEN26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Pos (26UL) /*!< Position of INTEN26 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN26_Pos) /*!< Bit mask of INTEN26 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Min (0x0UL) /*!< Min enumerator value of INTEN26 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Max (0x1UL) /*!< Max enumerator value of INTEN26 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[26] */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[26] */ + +/* INTEN27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Pos (27UL) /*!< Position of INTEN27 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN27_Pos) /*!< Bit mask of INTEN27 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Min (0x0UL) /*!< Min enumerator value of INTEN27 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Max (0x1UL) /*!< Max enumerator value of INTEN27 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[27] */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[27] */ + +/* INTEN28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Pos (28UL) /*!< Position of INTEN28 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN28_Pos) /*!< Bit mask of INTEN28 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Min (0x0UL) /*!< Min enumerator value of INTEN28 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Max (0x1UL) /*!< Max enumerator value of INTEN28 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[28] */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[28] */ + +/* INTEN29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Pos (29UL) /*!< Position of INTEN29 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN29_Pos) /*!< Bit mask of INTEN29 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Min (0x0UL) /*!< Min enumerator value of INTEN29 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Max (0x1UL) /*!< Max enumerator value of INTEN29 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[29] */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[29] */ + +/* INTEN30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Pos (30UL) /*!< Position of INTEN30 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN30_Pos) /*!< Bit mask of INTEN30 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Min (0x0UL) /*!< Min enumerator value of INTEN30 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Max (0x1UL) /*!< Max enumerator value of INTEN30 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[30] */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[30] */ + +/* INTEN31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Pos (31UL) /*!< Position of INTEN31 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN31_Pos) /*!< Bit mask of INTEN31 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Min (0x0UL) /*!< Min enumerator value of INTEN31 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Max (0x1UL) /*!< Max enumerator value of INTEN31 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[31] */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[31] */ + + +/** + * @brief EVENTSB [VPRCSR_NORDIC_EVENTSB] Buffered DPPI Events + */ + #define VPRCSR_NORDIC_EVENTSB (0x000007E5ul) + #define VPRCSR_NORDIC_EVENTSB_ResetValue (0x00000000UL) /*!< Reset value of EVENTSB register. */ + +/* EVENTSB0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Pos (0UL) /*!< Position of EVENTSB0 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB0_Pos) /*!< Bit mask of EVENTSB0 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Min (0x0UL) /*!< Min enumerator value of EVENTSB0 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Max (0x1UL) /*!< Max enumerator value of EVENTSB0 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Disabled (0x0UL) /*!< EVENTSB[0] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Enabled (0x1UL) /*!< EVENTSB[0] enabled */ + +/* EVENTSB1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Pos (1UL) /*!< Position of EVENTSB1 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB1_Pos) /*!< Bit mask of EVENTSB1 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Min (0x0UL) /*!< Min enumerator value of EVENTSB1 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Max (0x1UL) /*!< Max enumerator value of EVENTSB1 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Disabled (0x0UL) /*!< EVENTSB[1] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Enabled (0x1UL) /*!< EVENTSB[1] enabled */ + +/* EVENTSB2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Pos (2UL) /*!< Position of EVENTSB2 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB2_Pos) /*!< Bit mask of EVENTSB2 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Min (0x0UL) /*!< Min enumerator value of EVENTSB2 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Max (0x1UL) /*!< Max enumerator value of EVENTSB2 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Disabled (0x0UL) /*!< EVENTSB[2] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Enabled (0x1UL) /*!< EVENTSB[2] enabled */ + +/* EVENTSB3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Pos (3UL) /*!< Position of EVENTSB3 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB3_Pos) /*!< Bit mask of EVENTSB3 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Min (0x0UL) /*!< Min enumerator value of EVENTSB3 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Max (0x1UL) /*!< Max enumerator value of EVENTSB3 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Disabled (0x0UL) /*!< EVENTSB[3] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Enabled (0x1UL) /*!< EVENTSB[3] enabled */ + +/* EVENTSB4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Pos (4UL) /*!< Position of EVENTSB4 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB4_Pos) /*!< Bit mask of EVENTSB4 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Min (0x0UL) /*!< Min enumerator value of EVENTSB4 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Max (0x1UL) /*!< Max enumerator value of EVENTSB4 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Disabled (0x0UL) /*!< EVENTSB[4] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Enabled (0x1UL) /*!< EVENTSB[4] enabled */ + +/* EVENTSB5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Pos (5UL) /*!< Position of EVENTSB5 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB5_Pos) /*!< Bit mask of EVENTSB5 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Min (0x0UL) /*!< Min enumerator value of EVENTSB5 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Max (0x1UL) /*!< Max enumerator value of EVENTSB5 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Disabled (0x0UL) /*!< EVENTSB[5] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Enabled (0x1UL) /*!< EVENTSB[5] enabled */ + +/* EVENTSB6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Pos (6UL) /*!< Position of EVENTSB6 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB6_Pos) /*!< Bit mask of EVENTSB6 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Min (0x0UL) /*!< Min enumerator value of EVENTSB6 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Max (0x1UL) /*!< Max enumerator value of EVENTSB6 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Disabled (0x0UL) /*!< EVENTSB[6] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Enabled (0x1UL) /*!< EVENTSB[6] enabled */ + +/* EVENTSB7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Pos (7UL) /*!< Position of EVENTSB7 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB7_Pos) /*!< Bit mask of EVENTSB7 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Min (0x0UL) /*!< Min enumerator value of EVENTSB7 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Max (0x1UL) /*!< Max enumerator value of EVENTSB7 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Disabled (0x0UL) /*!< EVENTSB[7] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Enabled (0x1UL) /*!< EVENTSB[7] enabled */ + +/* EVENTSB8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Pos (8UL) /*!< Position of EVENTSB8 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB8_Pos) /*!< Bit mask of EVENTSB8 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Min (0x0UL) /*!< Min enumerator value of EVENTSB8 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Max (0x1UL) /*!< Max enumerator value of EVENTSB8 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Disabled (0x0UL) /*!< EVENTSB[8] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Enabled (0x1UL) /*!< EVENTSB[8] enabled */ + +/* EVENTSB9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Pos (9UL) /*!< Position of EVENTSB9 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB9_Pos) /*!< Bit mask of EVENTSB9 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Min (0x0UL) /*!< Min enumerator value of EVENTSB9 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Max (0x1UL) /*!< Max enumerator value of EVENTSB9 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Disabled (0x0UL) /*!< EVENTSB[9] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Enabled (0x1UL) /*!< EVENTSB[9] enabled */ + +/* EVENTSB10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Pos (10UL) /*!< Position of EVENTSB10 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB10_Pos) /*!< Bit mask of EVENTSB10 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Min (0x0UL) /*!< Min enumerator value of EVENTSB10 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Max (0x1UL) /*!< Max enumerator value of EVENTSB10 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Disabled (0x0UL) /*!< EVENTSB[10] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Enabled (0x1UL) /*!< EVENTSB[10] enabled */ + +/* EVENTSB11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Pos (11UL) /*!< Position of EVENTSB11 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB11_Pos) /*!< Bit mask of EVENTSB11 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Min (0x0UL) /*!< Min enumerator value of EVENTSB11 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Max (0x1UL) /*!< Max enumerator value of EVENTSB11 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Disabled (0x0UL) /*!< EVENTSB[11] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Enabled (0x1UL) /*!< EVENTSB[11] enabled */ + +/* EVENTSB12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Pos (12UL) /*!< Position of EVENTSB12 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB12_Pos) /*!< Bit mask of EVENTSB12 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Min (0x0UL) /*!< Min enumerator value of EVENTSB12 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Max (0x1UL) /*!< Max enumerator value of EVENTSB12 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Disabled (0x0UL) /*!< EVENTSB[12] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Enabled (0x1UL) /*!< EVENTSB[12] enabled */ + +/* EVENTSB13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Pos (13UL) /*!< Position of EVENTSB13 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB13_Pos) /*!< Bit mask of EVENTSB13 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Min (0x0UL) /*!< Min enumerator value of EVENTSB13 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Max (0x1UL) /*!< Max enumerator value of EVENTSB13 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Disabled (0x0UL) /*!< EVENTSB[13] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Enabled (0x1UL) /*!< EVENTSB[13] enabled */ + +/* EVENTSB14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Pos (14UL) /*!< Position of EVENTSB14 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB14_Pos) /*!< Bit mask of EVENTSB14 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Min (0x0UL) /*!< Min enumerator value of EVENTSB14 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Max (0x1UL) /*!< Max enumerator value of EVENTSB14 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Disabled (0x0UL) /*!< EVENTSB[14] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Enabled (0x1UL) /*!< EVENTSB[14] enabled */ + +/* EVENTSB15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Pos (15UL) /*!< Position of EVENTSB15 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB15_Pos) /*!< Bit mask of EVENTSB15 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Min (0x0UL) /*!< Min enumerator value of EVENTSB15 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Max (0x1UL) /*!< Max enumerator value of EVENTSB15 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Disabled (0x0UL) /*!< EVENTSB[15] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Enabled (0x1UL) /*!< EVENTSB[15] enabled */ + +/* EVENTSB16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Pos (16UL) /*!< Position of EVENTSB16 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB16_Pos) /*!< Bit mask of EVENTSB16 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Min (0x0UL) /*!< Min enumerator value of EVENTSB16 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Max (0x1UL) /*!< Max enumerator value of EVENTSB16 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Disabled (0x0UL) /*!< EVENTSB[16] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Enabled (0x1UL) /*!< EVENTSB[16] enabled */ + +/* EVENTSB17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Pos (17UL) /*!< Position of EVENTSB17 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB17_Pos) /*!< Bit mask of EVENTSB17 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Min (0x0UL) /*!< Min enumerator value of EVENTSB17 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Max (0x1UL) /*!< Max enumerator value of EVENTSB17 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Disabled (0x0UL) /*!< EVENTSB[17] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Enabled (0x1UL) /*!< EVENTSB[17] enabled */ + +/* EVENTSB18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Pos (18UL) /*!< Position of EVENTSB18 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB18_Pos) /*!< Bit mask of EVENTSB18 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Min (0x0UL) /*!< Min enumerator value of EVENTSB18 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Max (0x1UL) /*!< Max enumerator value of EVENTSB18 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Disabled (0x0UL) /*!< EVENTSB[18] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Enabled (0x1UL) /*!< EVENTSB[18] enabled */ + +/* EVENTSB19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Pos (19UL) /*!< Position of EVENTSB19 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB19_Pos) /*!< Bit mask of EVENTSB19 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Min (0x0UL) /*!< Min enumerator value of EVENTSB19 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Max (0x1UL) /*!< Max enumerator value of EVENTSB19 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Disabled (0x0UL) /*!< EVENTSB[19] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Enabled (0x1UL) /*!< EVENTSB[19] enabled */ + +/* EVENTSB20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Pos (20UL) /*!< Position of EVENTSB20 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB20_Pos) /*!< Bit mask of EVENTSB20 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Min (0x0UL) /*!< Min enumerator value of EVENTSB20 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Max (0x1UL) /*!< Max enumerator value of EVENTSB20 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Disabled (0x0UL) /*!< EVENTSB[20] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Enabled (0x1UL) /*!< EVENTSB[20] enabled */ + +/* EVENTSB21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Pos (21UL) /*!< Position of EVENTSB21 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB21_Pos) /*!< Bit mask of EVENTSB21 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Min (0x0UL) /*!< Min enumerator value of EVENTSB21 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Max (0x1UL) /*!< Max enumerator value of EVENTSB21 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Disabled (0x0UL) /*!< EVENTSB[21] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Enabled (0x1UL) /*!< EVENTSB[21] enabled */ + +/* EVENTSB22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Pos (22UL) /*!< Position of EVENTSB22 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB22_Pos) /*!< Bit mask of EVENTSB22 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Min (0x0UL) /*!< Min enumerator value of EVENTSB22 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Max (0x1UL) /*!< Max enumerator value of EVENTSB22 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Disabled (0x0UL) /*!< EVENTSB[22] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Enabled (0x1UL) /*!< EVENTSB[22] enabled */ + +/* EVENTSB23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Pos (23UL) /*!< Position of EVENTSB23 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB23_Pos) /*!< Bit mask of EVENTSB23 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Min (0x0UL) /*!< Min enumerator value of EVENTSB23 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Max (0x1UL) /*!< Max enumerator value of EVENTSB23 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Disabled (0x0UL) /*!< EVENTSB[23] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Enabled (0x1UL) /*!< EVENTSB[23] enabled */ + +/* EVENTSB24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Pos (24UL) /*!< Position of EVENTSB24 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB24_Pos) /*!< Bit mask of EVENTSB24 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Min (0x0UL) /*!< Min enumerator value of EVENTSB24 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Max (0x1UL) /*!< Max enumerator value of EVENTSB24 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Disabled (0x0UL) /*!< EVENTSB[24] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Enabled (0x1UL) /*!< EVENTSB[24] enabled */ + +/* EVENTSB25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Pos (25UL) /*!< Position of EVENTSB25 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB25_Pos) /*!< Bit mask of EVENTSB25 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Min (0x0UL) /*!< Min enumerator value of EVENTSB25 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Max (0x1UL) /*!< Max enumerator value of EVENTSB25 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Disabled (0x0UL) /*!< EVENTSB[25] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Enabled (0x1UL) /*!< EVENTSB[25] enabled */ + +/* EVENTSB26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Pos (26UL) /*!< Position of EVENTSB26 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB26_Pos) /*!< Bit mask of EVENTSB26 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Min (0x0UL) /*!< Min enumerator value of EVENTSB26 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Max (0x1UL) /*!< Max enumerator value of EVENTSB26 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Disabled (0x0UL) /*!< EVENTSB[26] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Enabled (0x1UL) /*!< EVENTSB[26] enabled */ + +/* EVENTSB27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Pos (27UL) /*!< Position of EVENTSB27 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB27_Pos) /*!< Bit mask of EVENTSB27 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Min (0x0UL) /*!< Min enumerator value of EVENTSB27 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Max (0x1UL) /*!< Max enumerator value of EVENTSB27 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Disabled (0x0UL) /*!< EVENTSB[27] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Enabled (0x1UL) /*!< EVENTSB[27] enabled */ + +/* EVENTSB28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Pos (28UL) /*!< Position of EVENTSB28 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB28_Pos) /*!< Bit mask of EVENTSB28 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Min (0x0UL) /*!< Min enumerator value of EVENTSB28 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Max (0x1UL) /*!< Max enumerator value of EVENTSB28 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Disabled (0x0UL) /*!< EVENTSB[28] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Enabled (0x1UL) /*!< EVENTSB[28] enabled */ + +/* EVENTSB29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Pos (29UL) /*!< Position of EVENTSB29 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB29_Pos) /*!< Bit mask of EVENTSB29 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Min (0x0UL) /*!< Min enumerator value of EVENTSB29 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Max (0x1UL) /*!< Max enumerator value of EVENTSB29 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Disabled (0x0UL) /*!< EVENTSB[29] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Enabled (0x1UL) /*!< EVENTSB[29] enabled */ + +/* EVENTSB30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Pos (30UL) /*!< Position of EVENTSB30 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB30_Pos) /*!< Bit mask of EVENTSB30 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Min (0x0UL) /*!< Min enumerator value of EVENTSB30 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Max (0x1UL) /*!< Max enumerator value of EVENTSB30 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Disabled (0x0UL) /*!< EVENTSB[30] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Enabled (0x1UL) /*!< EVENTSB[30] enabled */ + +/* EVENTSB31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Pos (31UL) /*!< Position of EVENTSB31 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB31_Pos) /*!< Bit mask of EVENTSB31 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Min (0x0UL) /*!< Min enumerator value of EVENTSB31 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Max (0x1UL) /*!< Max enumerator value of EVENTSB31 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Disabled (0x0UL) /*!< EVENTSB[31] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Enabled (0x1UL) /*!< EVENTSB[31] enabled */ + + +/** + * @brief EVENTSBS [VPRCSR_NORDIC_EVENTSBS] EVENTSB Dirty Status + */ + #define VPRCSR_NORDIC_EVENTSBS (0x000007E6ul) + #define VPRCSR_NORDIC_EVENTSBS_ResetValue (0x00000000UL) /*!< Reset value of EVENTSBS register. */ + +/* EVENTSB @Bits 0..31 : Write to EVENTSB (if not dirty) */ + #define VPRCSR_NORDIC_EVENTSBS_EVENTSB_Pos (0UL) /*!< Position of EVENTSB field. */ + #define VPRCSR_NORDIC_EVENTSBS_EVENTSB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_EVENTSBS_EVENTSB_Pos) /*!< Bit mask of EVENTSB + field.*/ + +/* DIRTYBIT @Bit 0 : Read EVENTSB Dirty status */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Pos (0UL) /*!< Position of DIRTYBIT field. */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field. */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty */ + + +/** + * @brief OUT [VPRCSR_NORDIC_OUT] GPIO Output value. Real Time Peripherals VIO. + */ + #define VPRCSR_NORDIC_OUT (0x00000BC0ul) + #define VPRCSR_NORDIC_OUT_ResetValue (0x00000000UL) /*!< Reset value of OUT register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_OUT_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_OUT_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUT_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUT_PIN0_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN0_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_OUT_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_OUT_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUT_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUT_PIN1_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN1_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_OUT_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_OUT_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUT_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUT_PIN2_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN2_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_OUT_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_OUT_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUT_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUT_PIN3_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN3_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_OUT_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_OUT_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUT_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUT_PIN4_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN4_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_OUT_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_OUT_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUT_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUT_PIN5_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN5_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_OUT_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_OUT_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUT_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUT_PIN6_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN6_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_OUT_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_OUT_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUT_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUT_PIN7_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN7_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_OUT_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_OUT_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUT_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUT_PIN8_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN8_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_OUT_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_OUT_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUT_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUT_PIN9_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN9_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_OUT_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_OUT_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUT_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUT_PIN10_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN10_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_OUT_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_OUT_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUT_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUT_PIN11_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN11_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_OUT_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_OUT_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUT_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUT_PIN12_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN12_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_OUT_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_OUT_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUT_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUT_PIN13_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN13_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_OUT_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_OUT_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUT_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUT_PIN14_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN14_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_OUT_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_OUT_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUT_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUT_PIN15_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN15_HIGH (0x1UL) /*!< Pin driver is high */ + + +/** + * @brief DIR [VPRCSR_NORDIC_DIR] GPIO pin Direction. Real Time Peripherals VIO. + */ + #define VPRCSR_NORDIC_DIR (0x00000BC1ul) + #define VPRCSR_NORDIC_DIR_ResetValue (0x00000000UL) /*!< Reset value of DIR register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_DIR_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_DIR_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIR_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIR_PIN0_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN0_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_DIR_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_DIR_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIR_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIR_PIN1_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN1_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_DIR_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_DIR_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIR_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIR_PIN2_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN2_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_DIR_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_DIR_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIR_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIR_PIN3_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN3_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_DIR_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_DIR_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIR_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIR_PIN4_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN4_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_DIR_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_DIR_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIR_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIR_PIN5_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN5_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_DIR_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_DIR_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIR_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIR_PIN6_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN6_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_DIR_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_DIR_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIR_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIR_PIN7_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN7_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_DIR_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_DIR_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIR_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIR_PIN8_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN8_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_DIR_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_DIR_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIR_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIR_PIN9_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN9_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_DIR_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_DIR_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIR_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIR_PIN10_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN10_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_DIR_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_DIR_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIR_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIR_PIN11_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN11_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_DIR_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_DIR_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIR_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIR_PIN12_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN12_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_DIR_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_DIR_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIR_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIR_PIN13_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN13_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_DIR_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_DIR_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIR_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIR_PIN14_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN14_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_DIR_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_DIR_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIR_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIR_PIN15_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN15_OUTPUT (0x1UL) /*!< Pin is set as output */ + + +/** + * @brief IN [VPRCSR_NORDIC_IN] GPIO Input. Real Time Peripherals VIO. + */ + #define VPRCSR_NORDIC_IN (0x00000BC2ul) + #define VPRCSR_NORDIC_IN_ResetValue (0x00000000UL) /*!< Reset value of IN register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_IN_PIN0_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_IN_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_IN_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_IN_PIN0_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN0_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_IN_PIN1_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_IN_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_IN_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_IN_PIN1_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN1_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_IN_PIN2_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_IN_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_IN_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_IN_PIN2_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN2_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_IN_PIN3_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_IN_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_IN_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_IN_PIN3_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN3_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_IN_PIN4_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_IN_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_IN_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_IN_PIN4_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN4_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_IN_PIN5_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_IN_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_IN_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_IN_PIN5_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN5_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_IN_PIN6_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_IN_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_IN_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_IN_PIN6_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN6_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_IN_PIN7_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_IN_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_IN_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_IN_PIN7_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN7_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_IN_PIN8_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_IN_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_IN_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_IN_PIN8_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN8_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_IN_PIN9_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_IN_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_IN_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_IN_PIN9_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN9_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_IN_PIN10_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_IN_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_IN_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_IN_PIN10_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN10_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_IN_PIN11_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_IN_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_IN_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_IN_PIN11_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN11_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_IN_PIN12_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_IN_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_IN_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_IN_PIN12_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN12_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_IN_PIN13_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_IN_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_IN_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_IN_PIN13_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN13_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_IN_PIN14_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_IN_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_IN_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_IN_PIN14_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN14_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_IN_PIN15_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_IN_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_IN_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_IN_PIN15_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN15_HIGH (0x1UL) /*!< Pin is High */ + + +/** + * @brief INMODE [VPRCSR_NORDIC_INMODE] Input Mode + */ + #define VPRCSR_NORDIC_INMODE (0x00000BC3ul) + #define VPRCSR_NORDIC_INMODE_ResetValue (0x00000000UL) /*!< Reset value of INMODE register. */ + +/* MODE @Bits 0..1 : Input Mode */ + #define VPRCSR_NORDIC_INMODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_INMODE_MODE_Msk (0x3UL << VPRCSR_NORDIC_INMODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define VPRCSR_NORDIC_INMODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_INMODE_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_INMODE_MODE_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping) */ + #define VPRCSR_NORDIC_INMODE_MODE_EVENT (0x1UL) /*!< Sampling on Counter1 event */ + #define VPRCSR_NORDIC_INMODE_MODE_SHIFT (0x2UL) /*!< Sampling and shifting on Counter1 event synchronized with OUT */ + #define VPRCSR_NORDIC_INMODE_MODE_SHIFTA (0x3UL) /*!< Sampling and shifting on Counter1 event, independent of OUT */ + + +/** + * @brief OUTB [VPRCSR_NORDIC_OUTB] Buffered GPIO Output + */ + #define VPRCSR_NORDIC_OUTB (0x00000BC4ul) + #define VPRCSR_NORDIC_OUTB_ResetValue (0x00000000UL) /*!< Reset value of OUTB register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_OUTB_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_OUTB_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTB_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTB_PIN0_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN0_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_OUTB_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_OUTB_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTB_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTB_PIN1_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN1_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_OUTB_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_OUTB_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTB_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTB_PIN2_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN2_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_OUTB_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_OUTB_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTB_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTB_PIN3_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN3_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_OUTB_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_OUTB_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTB_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTB_PIN4_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN4_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_OUTB_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_OUTB_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTB_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTB_PIN5_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN5_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_OUTB_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_OUTB_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTB_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTB_PIN6_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN6_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_OUTB_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_OUTB_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTB_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTB_PIN7_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN7_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_OUTB_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_OUTB_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTB_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTB_PIN8_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN8_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_OUTB_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_OUTB_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTB_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTB_PIN9_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN9_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_OUTB_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_OUTB_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTB_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTB_PIN10_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN10_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_OUTB_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_OUTB_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTB_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTB_PIN11_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN11_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_OUTB_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_OUTB_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTB_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTB_PIN12_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN12_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_OUTB_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_OUTB_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTB_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTB_PIN13_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN13_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_OUTB_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_OUTB_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTB_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTB_PIN14_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN14_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_OUTB_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_OUTB_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTB_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTB_PIN15_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN15_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define VPRCSR_NORDIC_OUTB_PIN16_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define VPRCSR_NORDIC_OUTB_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define VPRCSR_NORDIC_OUTB_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define VPRCSR_NORDIC_OUTB_PIN16_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN16_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define VPRCSR_NORDIC_OUTB_PIN17_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define VPRCSR_NORDIC_OUTB_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define VPRCSR_NORDIC_OUTB_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define VPRCSR_NORDIC_OUTB_PIN17_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN17_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define VPRCSR_NORDIC_OUTB_PIN18_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define VPRCSR_NORDIC_OUTB_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define VPRCSR_NORDIC_OUTB_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define VPRCSR_NORDIC_OUTB_PIN18_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN18_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define VPRCSR_NORDIC_OUTB_PIN19_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define VPRCSR_NORDIC_OUTB_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define VPRCSR_NORDIC_OUTB_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define VPRCSR_NORDIC_OUTB_PIN19_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN19_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define VPRCSR_NORDIC_OUTB_PIN20_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define VPRCSR_NORDIC_OUTB_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define VPRCSR_NORDIC_OUTB_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define VPRCSR_NORDIC_OUTB_PIN20_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN20_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define VPRCSR_NORDIC_OUTB_PIN21_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define VPRCSR_NORDIC_OUTB_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define VPRCSR_NORDIC_OUTB_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define VPRCSR_NORDIC_OUTB_PIN21_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN21_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define VPRCSR_NORDIC_OUTB_PIN22_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define VPRCSR_NORDIC_OUTB_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define VPRCSR_NORDIC_OUTB_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define VPRCSR_NORDIC_OUTB_PIN22_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN22_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define VPRCSR_NORDIC_OUTB_PIN23_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define VPRCSR_NORDIC_OUTB_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define VPRCSR_NORDIC_OUTB_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define VPRCSR_NORDIC_OUTB_PIN23_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN23_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define VPRCSR_NORDIC_OUTB_PIN24_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define VPRCSR_NORDIC_OUTB_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define VPRCSR_NORDIC_OUTB_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define VPRCSR_NORDIC_OUTB_PIN24_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN24_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define VPRCSR_NORDIC_OUTB_PIN25_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define VPRCSR_NORDIC_OUTB_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define VPRCSR_NORDIC_OUTB_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define VPRCSR_NORDIC_OUTB_PIN25_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN25_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define VPRCSR_NORDIC_OUTB_PIN26_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define VPRCSR_NORDIC_OUTB_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define VPRCSR_NORDIC_OUTB_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define VPRCSR_NORDIC_OUTB_PIN26_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN26_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define VPRCSR_NORDIC_OUTB_PIN27_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define VPRCSR_NORDIC_OUTB_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define VPRCSR_NORDIC_OUTB_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define VPRCSR_NORDIC_OUTB_PIN27_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN27_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define VPRCSR_NORDIC_OUTB_PIN28_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define VPRCSR_NORDIC_OUTB_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define VPRCSR_NORDIC_OUTB_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define VPRCSR_NORDIC_OUTB_PIN28_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN28_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define VPRCSR_NORDIC_OUTB_PIN29_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define VPRCSR_NORDIC_OUTB_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define VPRCSR_NORDIC_OUTB_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define VPRCSR_NORDIC_OUTB_PIN29_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN29_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define VPRCSR_NORDIC_OUTB_PIN30_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define VPRCSR_NORDIC_OUTB_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define VPRCSR_NORDIC_OUTB_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define VPRCSR_NORDIC_OUTB_PIN30_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN30_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define VPRCSR_NORDIC_OUTB_PIN31_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define VPRCSR_NORDIC_OUTB_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define VPRCSR_NORDIC_OUTB_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define VPRCSR_NORDIC_OUTB_PIN31_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN31_HIGH (0x1UL) /*!< Pin driver is high */ + + +/** + * @brief DIRB [VPRCSR_NORDIC_DIRB] Buffered GPIO pin Direction + */ + #define VPRCSR_NORDIC_DIRB (0x00000BC5ul) + #define VPRCSR_NORDIC_DIRB_ResetValue (0x00000000UL) /*!< Reset value of DIRB register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_DIRB_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_DIRB_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRB_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRB_PIN0_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN0_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_DIRB_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_DIRB_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRB_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRB_PIN1_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN1_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_DIRB_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_DIRB_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRB_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRB_PIN2_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN2_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_DIRB_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_DIRB_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRB_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRB_PIN3_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN3_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_DIRB_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_DIRB_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRB_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRB_PIN4_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN4_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_DIRB_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_DIRB_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRB_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRB_PIN5_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN5_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_DIRB_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_DIRB_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRB_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRB_PIN6_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN6_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_DIRB_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_DIRB_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRB_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRB_PIN7_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN7_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_DIRB_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_DIRB_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRB_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRB_PIN8_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN8_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_DIRB_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_DIRB_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRB_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRB_PIN9_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN9_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_DIRB_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_DIRB_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRB_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRB_PIN10_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN10_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_DIRB_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_DIRB_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRB_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRB_PIN11_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN11_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_DIRB_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_DIRB_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRB_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRB_PIN12_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN12_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_DIRB_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_DIRB_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRB_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRB_PIN13_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN13_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_DIRB_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_DIRB_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRB_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRB_PIN14_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN14_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_DIRB_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_DIRB_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRB_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRB_PIN15_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN15_OUTPUT (0x1UL) /*!< Pin is set as output */ + + +/** + * @brief DIROUT [VPRCSR_NORDIC_DIROUT] DIR and OUT concatenation + */ + #define VPRCSR_NORDIC_DIROUT (0x00000BC6ul) + #define VPRCSR_NORDIC_DIROUT_ResetValue (0x00000000UL) /*!< Reset value of DIROUT register. */ + +/* OUT @Bits 0..15 : GPIO Output */ + #define VPRCSR_NORDIC_DIROUT_OUT_Pos (0UL) /*!< Position of OUT field. */ + #define VPRCSR_NORDIC_DIROUT_OUT_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUT_OUT_Pos) /*!< Bit mask of OUT field. */ + +/* DIR @Bits 16..31 : GPIO pin Direction */ + #define VPRCSR_NORDIC_DIROUT_DIR_Pos (16UL) /*!< Position of DIR field. */ + #define VPRCSR_NORDIC_DIROUT_DIR_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUT_DIR_Pos) /*!< Bit mask of DIR field. */ + + +/** + * @brief DIROUTB [VPRCSR_NORDIC_DIROUTB] Concatenation of DIRB and OUTB + */ + #define VPRCSR_NORDIC_DIROUTB (0x00000BC7ul) + #define VPRCSR_NORDIC_DIROUTB_ResetValue (0x00000000UL) /*!< Reset value of DIROUTB register. */ + +/* OUTB @Bits 0..15 : Buffered GPIO Output */ + #define VPRCSR_NORDIC_DIROUTB_OUTB_Pos (0UL) /*!< Position of OUTB field. */ + #define VPRCSR_NORDIC_DIROUTB_OUTB_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUTB_OUTB_Pos) /*!< Bit mask of OUTB field. */ + +/* DIRB @Bits 16..31 : Buffered GPIO pin Direction */ + #define VPRCSR_NORDIC_DIROUTB_DIRB_Pos (16UL) /*!< Position of DIRB field. */ + #define VPRCSR_NORDIC_DIROUTB_DIRB_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUTB_DIRB_Pos) /*!< Bit mask of DIRB field. */ + + +/** + * @brief OUTBRB [VPRCSR_NORDIC_OUTBRB] Byte reversed register OUTB + */ + #define VPRCSR_NORDIC_OUTBRB (0x00000BC8ul) + #define VPRCSR_NORDIC_OUTBRB_ResetValue (0x00000000UL) /*!< Reset value of OUTBRB register. */ + +/* VAL @Bits 0..31 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBRB_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_OUTBRB_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBRB_VAL_Pos) /*!< Bit mask of VAL field. */ + #define VPRCSR_NORDIC_OUTBRB_VAL_Min (0x00000000UL) /*!< Min value of VAL field. */ + #define VPRCSR_NORDIC_OUTBRB_VAL_Max (0xFFFFFFFFUL) /*!< Max size of VAL field. */ + + +/** + * @brief OUTBRW [VPRCSR_NORDIC_OUTBRW] Word reversed register OUTB + */ + #define VPRCSR_NORDIC_OUTBRW (0x00000BC9ul) + #define VPRCSR_NORDIC_OUTBRW_ResetValue (0x00000000UL) /*!< Reset value of OUTBRW register. */ + +/* VAL @Bits 0..31 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBRW_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_OUTBRW_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBRW_VAL_Pos) /*!< Bit mask of VAL field. */ + #define VPRCSR_NORDIC_OUTBRW_VAL_Min (0x00000000UL) /*!< Min value of VAL field. */ + #define VPRCSR_NORDIC_OUTBRW_VAL_Max (0xFFFFFFFFUL) /*!< Max size of VAL field. */ + + +/** + * @brief INBRB [VPRCSR_NORDIC_INBRB] Byte reversed register INB + */ + #define VPRCSR_NORDIC_INBRB (0x00000BCAul) + #define VPRCSR_NORDIC_INBRB_ResetValue (0x00000000UL) /*!< Reset value of INBRB register. */ + +/* VAL @Bits 0..31 : (unspecified) */ + #define VPRCSR_NORDIC_INBRB_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_INBRB_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_INBRB_VAL_Pos) /*!< Bit mask of VAL field. */ + #define VPRCSR_NORDIC_INBRB_VAL_Min (0x00000000UL) /*!< Min value of VAL field. */ + #define VPRCSR_NORDIC_INBRB_VAL_Max (0xFFFFFFFFUL) /*!< Max size of VAL field. */ + + +/** + * @brief SHIFTCTRLB [VPRCSR_NORDIC_SHIFTCTRLB] Buffered IO shift control + */ + #define VPRCSR_NORDIC_SHIFTCTRLB (0x00000BCBul) + #define VPRCSR_NORDIC_SHIFTCTRLB_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCTRLB register. */ + +/* Field group SHIFTCNTB : (unspecified) */ +/* VALUE @Bits 0..5 : Alias to SHIFTCNTB.VALUE register */ + #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Pos) /*!< Bit mask + of VALUE field.*/ + #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Min (0x00UL) /*!< Min value of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Max (0x20UL) /*!< Max size of VALUE field. */ + +/* End field group SHIFTCNTB. */ + +/* Field group OUTMODEB : (unspecified) */ +/* MODE @Bits 8..10 : Alias to OUTMODEB.MODE register */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Pos (8UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Msk (0x7UL << VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Pos) /*!< Bit mask of + MODE field.*/ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Max (0x4UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_NoShifting (0x0UL) /*!< No shifting */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_OutBBuf (0x2UL) /*!< Only OUTB used for buffering */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_OutBBufToggleClk (0x4UL) /*!< Only OUTB used for buffering, auto-toggle clock + line*/ + +/* FRAMEWIDTH @Bits 12..16 : Alias to OUTMODEB.FRAMEWIDTH register */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Pos (12UL) /*!< Position of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Msk (0x1FUL << VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Pos) /*!< + Bit mask of FRAMEWIDTH field.*/ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Min (0x00UL) /*!< Min value of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Max (0x10UL) /*!< Max size of FRAMEWIDTH field. */ + +/* SEL @Bits 24..27 : Alias to OUTMODEB.SEL register */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_SEL_Pos (24UL) /*!< Position of SEL field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_SEL_Msk (0xFUL << VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_SEL_Pos) /*!< Bit mask of SEL + field.*/ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_SEL_Min (0x0UL) /*!< Min value of SEL field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_SEL_Max (0xFUL) /*!< Max size of SEL field. */ + +/* End field group OUTMODEB. */ + +/* Field group INMODEB : (unspecified) */ +/* MODE @Bits 20..21 : Alias to INMODEB.MODE register */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Pos (20UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Msk (0x3UL << VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Pos) /*!< Bit mask of MODE + field.*/ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping) */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_EVENT (0x1UL) /*!< Sampling on Counter1 event */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_SHIFT (0x2UL) /*!< Sampling and shifting on Counter1 event */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_SHIFTA (0x3UL) /*!< Sampling and shifting on Counter1 event, independent from + output*/ + +/* End field group INMODEB. */ + + +/** + * @brief SHIFTCNTIN [VPRCSR_NORDIC_SHIFTCNTIN] Number of frames to be shifted from INB before new data is required + */ + #define VPRCSR_NORDIC_SHIFTCNTIN (0x00000BCDul) + #define VPRCSR_NORDIC_SHIFTCNTIN_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCNTIN register. */ + +/* VALUE @Bits 0..5 : Value */ + #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Min (0x00UL) /*!< Min value of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Max (0x3FUL) /*!< Max size of VALUE field. */ + + +/** + * @brief SHIFTCNTOUT [VPRCSR_NORDIC_SHIFTCNTOUT] Number of frames to be shifted to OUTB before new data is required + */ + #define VPRCSR_NORDIC_SHIFTCNTOUT (0x00000BCEul) + #define VPRCSR_NORDIC_SHIFTCNTOUT_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCNTOUT register. */ + +/* VALUE @Bits 0..5 : Value */ + #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Min (0x00UL) /*!< Min value of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Max (0x3FUL) /*!< Max size of VALUE field. */ + + +/** + * @brief SHIFTCNTB [VPRCSR_NORDIC_SHIFTCNTB] Buffered SHIFTCNTOUT and SHIFTCNTIN register + */ + #define VPRCSR_NORDIC_SHIFTCNTB (0x00000BCFul) + #define VPRCSR_NORDIC_SHIFTCNTB_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCNTB register. */ + +/* VALUE @Bits 0..5 : Value */ + #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCNTB_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Min (0x00UL) /*!< Min value of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Max (0x3FUL) /*!< Max size of VALUE field. */ + + +/** + * @brief OUTTGL [VPRCSR_NORDIC_OUTTGL] GPIO Output Toggle + */ + #define VPRCSR_NORDIC_OUTTGL (0x00000BD0ul) + #define VPRCSR_NORDIC_OUTTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTTGL register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief DIRTGL [VPRCSR_NORDIC_DIRTGL] GPIO pin Direction Toggle + */ + #define VPRCSR_NORDIC_DIRTGL (0x00000BD1ul) + #define VPRCSR_NORDIC_DIRTGL_ResetValue (0x00000000UL) /*!< Reset value of DIRTGL register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief OUTBTGL [VPRCSR_NORDIC_OUTBTGL] Buffered GPIO Output Toggle + */ + #define VPRCSR_NORDIC_OUTBTGL (0x00000BD2ul) + #define VPRCSR_NORDIC_OUTBTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTBTGL register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief DIRBTGL [VPRCSR_NORDIC_DIRBTGL] Buffered GPIO pin Direction Toggle + */ + #define VPRCSR_NORDIC_DIRBTGL (0x00000BD3ul) + #define VPRCSR_NORDIC_DIRBTGL_ResetValue (0x00000000UL) /*!< Reset value of DIRBTGL register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief DIROUTTGL [VPRCSR_NORDIC_DIROUTTGL] DIROUT Toggle + */ + #define VPRCSR_NORDIC_DIROUTTGL (0x00000BD4ul) + #define VPRCSR_NORDIC_DIROUTTGL_ResetValue (0x00000000UL) /*!< Reset value of DIROUTTGL register. */ + +/* OUT0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Pos (0UL) /*!< Position of OUT0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT0_Pos) /*!< Bit mask of OUT0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Min (0x0UL) /*!< Min enumerator value of OUT0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Max (0x1UL) /*!< Max enumerator value of OUT0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Pos (1UL) /*!< Position of OUT1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT1_Pos) /*!< Bit mask of OUT1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Min (0x0UL) /*!< Min enumerator value of OUT1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Max (0x1UL) /*!< Max enumerator value of OUT1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Pos (2UL) /*!< Position of OUT2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT2_Pos) /*!< Bit mask of OUT2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Min (0x0UL) /*!< Min enumerator value of OUT2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Max (0x1UL) /*!< Max enumerator value of OUT2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Pos (3UL) /*!< Position of OUT3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT3_Pos) /*!< Bit mask of OUT3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Min (0x0UL) /*!< Min enumerator value of OUT3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Max (0x1UL) /*!< Max enumerator value of OUT3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Pos (4UL) /*!< Position of OUT4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT4_Pos) /*!< Bit mask of OUT4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Min (0x0UL) /*!< Min enumerator value of OUT4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Max (0x1UL) /*!< Max enumerator value of OUT4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Pos (5UL) /*!< Position of OUT5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT5_Pos) /*!< Bit mask of OUT5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Min (0x0UL) /*!< Min enumerator value of OUT5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Max (0x1UL) /*!< Max enumerator value of OUT5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Pos (6UL) /*!< Position of OUT6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT6_Pos) /*!< Bit mask of OUT6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Min (0x0UL) /*!< Min enumerator value of OUT6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Max (0x1UL) /*!< Max enumerator value of OUT6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Pos (7UL) /*!< Position of OUT7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT7_Pos) /*!< Bit mask of OUT7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Min (0x0UL) /*!< Min enumerator value of OUT7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Max (0x1UL) /*!< Max enumerator value of OUT7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Pos (8UL) /*!< Position of OUT8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT8_Pos) /*!< Bit mask of OUT8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Min (0x0UL) /*!< Min enumerator value of OUT8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Max (0x1UL) /*!< Max enumerator value of OUT8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Pos (9UL) /*!< Position of OUT9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT9_Pos) /*!< Bit mask of OUT9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Min (0x0UL) /*!< Min enumerator value of OUT9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Max (0x1UL) /*!< Max enumerator value of OUT9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Pos (10UL) /*!< Position of OUT10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT10_Pos) /*!< Bit mask of OUT10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Min (0x0UL) /*!< Min enumerator value of OUT10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Max (0x1UL) /*!< Max enumerator value of OUT10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Pos (11UL) /*!< Position of OUT11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT11_Pos) /*!< Bit mask of OUT11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Min (0x0UL) /*!< Min enumerator value of OUT11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Max (0x1UL) /*!< Max enumerator value of OUT11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Pos (12UL) /*!< Position of OUT12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT12_Pos) /*!< Bit mask of OUT12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Min (0x0UL) /*!< Min enumerator value of OUT12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Max (0x1UL) /*!< Max enumerator value of OUT12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Pos (13UL) /*!< Position of OUT13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT13_Pos) /*!< Bit mask of OUT13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Min (0x0UL) /*!< Min enumerator value of OUT13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Max (0x1UL) /*!< Max enumerator value of OUT13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Pos (14UL) /*!< Position of OUT14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT14_Pos) /*!< Bit mask of OUT14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Min (0x0UL) /*!< Min enumerator value of OUT14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Max (0x1UL) /*!< Max enumerator value of OUT14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Pos (15UL) /*!< Position of OUT15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT15_Pos) /*!< Bit mask of OUT15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Min (0x0UL) /*!< Min enumerator value of OUT15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Max (0x1UL) /*!< Max enumerator value of OUT15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR0 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Pos (16UL) /*!< Position of DIR0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR0_Pos) /*!< Bit mask of DIR0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Min (0x0UL) /*!< Min enumerator value of DIR0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Max (0x1UL) /*!< Max enumerator value of DIR0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR1 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Pos (17UL) /*!< Position of DIR1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR1_Pos) /*!< Bit mask of DIR1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Min (0x0UL) /*!< Min enumerator value of DIR1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Max (0x1UL) /*!< Max enumerator value of DIR1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR2 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Pos (18UL) /*!< Position of DIR2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR2_Pos) /*!< Bit mask of DIR2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Min (0x0UL) /*!< Min enumerator value of DIR2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Max (0x1UL) /*!< Max enumerator value of DIR2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR3 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Pos (19UL) /*!< Position of DIR3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR3_Pos) /*!< Bit mask of DIR3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Min (0x0UL) /*!< Min enumerator value of DIR3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Max (0x1UL) /*!< Max enumerator value of DIR3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR4 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Pos (20UL) /*!< Position of DIR4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR4_Pos) /*!< Bit mask of DIR4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Min (0x0UL) /*!< Min enumerator value of DIR4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Max (0x1UL) /*!< Max enumerator value of DIR4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR5 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Pos (21UL) /*!< Position of DIR5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR5_Pos) /*!< Bit mask of DIR5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Min (0x0UL) /*!< Min enumerator value of DIR5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Max (0x1UL) /*!< Max enumerator value of DIR5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR6 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Pos (22UL) /*!< Position of DIR6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR6_Pos) /*!< Bit mask of DIR6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Min (0x0UL) /*!< Min enumerator value of DIR6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Max (0x1UL) /*!< Max enumerator value of DIR6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR7 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Pos (23UL) /*!< Position of DIR7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR7_Pos) /*!< Bit mask of DIR7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Min (0x0UL) /*!< Min enumerator value of DIR7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Max (0x1UL) /*!< Max enumerator value of DIR7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR8 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Pos (24UL) /*!< Position of DIR8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR8_Pos) /*!< Bit mask of DIR8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Min (0x0UL) /*!< Min enumerator value of DIR8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Max (0x1UL) /*!< Max enumerator value of DIR8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR9 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Pos (25UL) /*!< Position of DIR9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR9_Pos) /*!< Bit mask of DIR9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Min (0x0UL) /*!< Min enumerator value of DIR9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Max (0x1UL) /*!< Max enumerator value of DIR9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR10 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Pos (26UL) /*!< Position of DIR10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR10_Pos) /*!< Bit mask of DIR10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Min (0x0UL) /*!< Min enumerator value of DIR10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Max (0x1UL) /*!< Max enumerator value of DIR10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR11 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Pos (27UL) /*!< Position of DIR11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR11_Pos) /*!< Bit mask of DIR11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Min (0x0UL) /*!< Min enumerator value of DIR11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Max (0x1UL) /*!< Max enumerator value of DIR11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR12 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Pos (28UL) /*!< Position of DIR12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR12_Pos) /*!< Bit mask of DIR12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Min (0x0UL) /*!< Min enumerator value of DIR12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Max (0x1UL) /*!< Max enumerator value of DIR12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR13 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Pos (29UL) /*!< Position of DIR13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR13_Pos) /*!< Bit mask of DIR13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Min (0x0UL) /*!< Min enumerator value of DIR13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Max (0x1UL) /*!< Max enumerator value of DIR13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR14 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Pos (30UL) /*!< Position of DIR14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR14_Pos) /*!< Bit mask of DIR14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Min (0x0UL) /*!< Min enumerator value of DIR14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Max (0x1UL) /*!< Max enumerator value of DIR14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR15 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Pos (31UL) /*!< Position of DIR15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR15_Pos) /*!< Bit mask of DIR15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Min (0x0UL) /*!< Min enumerator value of DIR15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Max (0x1UL) /*!< Max enumerator value of DIR15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief DIROUTBTGL [VPRCSR_NORDIC_DIROUTBTGL] DIROUTB Toggle + */ + #define VPRCSR_NORDIC_DIROUTBTGL (0x00000BD5ul) + #define VPRCSR_NORDIC_DIROUTBTGL_ResetValue (0x00000000UL) /*!< Reset value of DIROUTBTGL register. */ + +/* OUTB0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Pos (0UL) /*!< Position of OUTB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Pos) /*!< Bit mask of OUTB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Min (0x0UL) /*!< Min enumerator value of OUTB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Max (0x1UL) /*!< Max enumerator value of OUTB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Pos (1UL) /*!< Position of OUTB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Pos) /*!< Bit mask of OUTB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Min (0x0UL) /*!< Min enumerator value of OUTB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Max (0x1UL) /*!< Max enumerator value of OUTB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Pos (2UL) /*!< Position of OUTB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Pos) /*!< Bit mask of OUTB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Min (0x0UL) /*!< Min enumerator value of OUTB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Max (0x1UL) /*!< Max enumerator value of OUTB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Pos (3UL) /*!< Position of OUTB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Pos) /*!< Bit mask of OUTB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Min (0x0UL) /*!< Min enumerator value of OUTB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Max (0x1UL) /*!< Max enumerator value of OUTB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Pos (4UL) /*!< Position of OUTB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Pos) /*!< Bit mask of OUTB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Min (0x0UL) /*!< Min enumerator value of OUTB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Max (0x1UL) /*!< Max enumerator value of OUTB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Pos (5UL) /*!< Position of OUTB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Pos) /*!< Bit mask of OUTB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Min (0x0UL) /*!< Min enumerator value of OUTB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Max (0x1UL) /*!< Max enumerator value of OUTB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Pos (6UL) /*!< Position of OUTB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Pos) /*!< Bit mask of OUTB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Min (0x0UL) /*!< Min enumerator value of OUTB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Max (0x1UL) /*!< Max enumerator value of OUTB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Pos (7UL) /*!< Position of OUTB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Pos) /*!< Bit mask of OUTB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Min (0x0UL) /*!< Min enumerator value of OUTB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Max (0x1UL) /*!< Max enumerator value of OUTB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Pos (8UL) /*!< Position of OUTB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Pos) /*!< Bit mask of OUTB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Min (0x0UL) /*!< Min enumerator value of OUTB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Max (0x1UL) /*!< Max enumerator value of OUTB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Pos (9UL) /*!< Position of OUTB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Pos) /*!< Bit mask of OUTB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Min (0x0UL) /*!< Min enumerator value of OUTB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Max (0x1UL) /*!< Max enumerator value of OUTB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Pos (10UL) /*!< Position of OUTB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Pos) /*!< Bit mask of OUTB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Min (0x0UL) /*!< Min enumerator value of OUTB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Max (0x1UL) /*!< Max enumerator value of OUTB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Pos (11UL) /*!< Position of OUTB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Pos) /*!< Bit mask of OUTB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Min (0x0UL) /*!< Min enumerator value of OUTB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Max (0x1UL) /*!< Max enumerator value of OUTB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Pos (12UL) /*!< Position of OUTB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Pos) /*!< Bit mask of OUTB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Min (0x0UL) /*!< Min enumerator value of OUTB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Max (0x1UL) /*!< Max enumerator value of OUTB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Pos (13UL) /*!< Position of OUTB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Pos) /*!< Bit mask of OUTB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Min (0x0UL) /*!< Min enumerator value of OUTB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Max (0x1UL) /*!< Max enumerator value of OUTB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Pos (14UL) /*!< Position of OUTB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Pos) /*!< Bit mask of OUTB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Min (0x0UL) /*!< Min enumerator value of OUTB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Max (0x1UL) /*!< Max enumerator value of OUTB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Pos (15UL) /*!< Position of OUTB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Pos) /*!< Bit mask of OUTB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Min (0x0UL) /*!< Min enumerator value of OUTB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Max (0x1UL) /*!< Max enumerator value of OUTB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB0 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Pos (16UL) /*!< Position of DIRB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Pos) /*!< Bit mask of DIRB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Min (0x0UL) /*!< Min enumerator value of DIRB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Max (0x1UL) /*!< Max enumerator value of DIRB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB1 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Pos (17UL) /*!< Position of DIRB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Pos) /*!< Bit mask of DIRB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Min (0x0UL) /*!< Min enumerator value of DIRB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Max (0x1UL) /*!< Max enumerator value of DIRB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB2 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Pos (18UL) /*!< Position of DIRB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Pos) /*!< Bit mask of DIRB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Min (0x0UL) /*!< Min enumerator value of DIRB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Max (0x1UL) /*!< Max enumerator value of DIRB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB3 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Pos (19UL) /*!< Position of DIRB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Pos) /*!< Bit mask of DIRB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Min (0x0UL) /*!< Min enumerator value of DIRB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Max (0x1UL) /*!< Max enumerator value of DIRB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB4 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Pos (20UL) /*!< Position of DIRB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Pos) /*!< Bit mask of DIRB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Min (0x0UL) /*!< Min enumerator value of DIRB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Max (0x1UL) /*!< Max enumerator value of DIRB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB5 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Pos (21UL) /*!< Position of DIRB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Pos) /*!< Bit mask of DIRB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Min (0x0UL) /*!< Min enumerator value of DIRB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Max (0x1UL) /*!< Max enumerator value of DIRB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB6 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Pos (22UL) /*!< Position of DIRB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Pos) /*!< Bit mask of DIRB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Min (0x0UL) /*!< Min enumerator value of DIRB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Max (0x1UL) /*!< Max enumerator value of DIRB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB7 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Pos (23UL) /*!< Position of DIRB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Pos) /*!< Bit mask of DIRB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Min (0x0UL) /*!< Min enumerator value of DIRB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Max (0x1UL) /*!< Max enumerator value of DIRB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB8 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Pos (24UL) /*!< Position of DIRB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Pos) /*!< Bit mask of DIRB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Min (0x0UL) /*!< Min enumerator value of DIRB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Max (0x1UL) /*!< Max enumerator value of DIRB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB9 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Pos (25UL) /*!< Position of DIRB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Pos) /*!< Bit mask of DIRB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Min (0x0UL) /*!< Min enumerator value of DIRB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Max (0x1UL) /*!< Max enumerator value of DIRB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB10 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Pos (26UL) /*!< Position of DIRB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Pos) /*!< Bit mask of DIRB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Min (0x0UL) /*!< Min enumerator value of DIRB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Max (0x1UL) /*!< Max enumerator value of DIRB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB11 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Pos (27UL) /*!< Position of DIRB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Pos) /*!< Bit mask of DIRB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Min (0x0UL) /*!< Min enumerator value of DIRB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Max (0x1UL) /*!< Max enumerator value of DIRB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB12 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Pos (28UL) /*!< Position of DIRB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Pos) /*!< Bit mask of DIRB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Min (0x0UL) /*!< Min enumerator value of DIRB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Max (0x1UL) /*!< Max enumerator value of DIRB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB13 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Pos (29UL) /*!< Position of DIRB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Pos) /*!< Bit mask of DIRB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Min (0x0UL) /*!< Min enumerator value of DIRB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Max (0x1UL) /*!< Max enumerator value of DIRB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB14 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Pos (30UL) /*!< Position of DIRB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Pos) /*!< Bit mask of DIRB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Min (0x0UL) /*!< Min enumerator value of DIRB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Max (0x1UL) /*!< Max enumerator value of DIRB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB15 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Pos (31UL) /*!< Position of DIRB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Pos) /*!< Bit mask of DIRB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Min (0x0UL) /*!< Min enumerator value of DIRB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Max (0x1UL) /*!< Max enumerator value of DIRB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief OUTUBTGL [VPRCSR_NORDIC_OUTUBTGL] Buffered GPIO Unshifted Output Toggle + */ + #define VPRCSR_NORDIC_OUTUBTGL (0x00000BD6ul) + #define VPRCSR_NORDIC_OUTUBTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTUBTGL register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTUBTGL_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTUBTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief OUTBS [VPRCSR_NORDIC_OUTBS] Buffered GPIO Output Dirty Status + */ + #define VPRCSR_NORDIC_OUTBS (0x00000BD8ul) + #define VPRCSR_NORDIC_OUTBS_ResetValue (0x00000000UL) /*!< Reset value of OUTBS register. */ + +/* OUTB @Bits 0..31 : Write to OUTB (if not dirty) */ + #define VPRCSR_NORDIC_OUTBS_OUTB_Pos (0UL) /*!< Position of OUTB field. */ + #define VPRCSR_NORDIC_OUTBS_OUTB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBS_OUTB_Pos) /*!< Bit mask of OUTB field. */ + +/* DIRTYBIT @Bit 0 : Read Buffer Dirty status */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Pos (0UL) /*!< Position of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_OUTBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty */ + + +/** + * @brief DIRBS [VPRCSR_NORDIC_DIRBS] Buffered GPIO pin Direction Dirty Status + */ + #define VPRCSR_NORDIC_DIRBS (0x00000BD9ul) + #define VPRCSR_NORDIC_DIRBS_ResetValue (0x00000000UL) /*!< Reset value of DIRBS register. */ + +/* DIRB @Bits 0..31 : Write to DIRB (if not dirty) */ + #define VPRCSR_NORDIC_DIRBS_DIRB_Pos (0UL) /*!< Position of DIRB field. */ + #define VPRCSR_NORDIC_DIRBS_DIRB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_DIRBS_DIRB_Pos) /*!< Bit mask of DIRB field. */ + +/* DIRTYBIT @Bit 0 : Read Buffer Dirty status */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Pos (0UL) /*!< Position of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_DIRBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty */ + + +/** + * @brief DIROUTBS [VPRCSR_NORDIC_DIROUTBS] Combination of DIRB and OUTB Dirty Status + */ + #define VPRCSR_NORDIC_DIROUTBS (0x00000BDAul) + #define VPRCSR_NORDIC_DIROUTBS_ResetValue (0x00000000UL) /*!< Reset value of DIROUTBS register. */ + +/* DIROUTB @Bits 0..31 : Write to DIROUTB (if not dirty) */ + #define VPRCSR_NORDIC_DIROUTBS_DIROUTB_Pos (0UL) /*!< Position of DIROUTB field. */ + #define VPRCSR_NORDIC_DIROUTBS_DIROUTB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_DIROUTBS_DIROUTB_Pos) /*!< Bit mask of DIROUTB + field.*/ + +/* DIRTYBIT @Bit 0 : Read Combination (OR) of DIRB and OUTB Dirty status */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Pos (0UL) /*!< Position of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty */ + + +/** + * @brief OUTUBS [VPRCSR_NORDIC_OUTUBS] Buffered GPIO Unshifted Output Dirty Status + */ + #define VPRCSR_NORDIC_OUTUBS (0x00000BDBul) + #define VPRCSR_NORDIC_OUTUBS_ResetValue (0x00000000UL) /*!< Reset value of OUTUBS register. */ + +/* OUTUB @Bits 0..31 : Write to OUTUB (if not dirty) */ + #define VPRCSR_NORDIC_OUTUBS_OUTUB_Pos (0UL) /*!< Position of OUTUB field. */ + #define VPRCSR_NORDIC_OUTUBS_OUTUB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTUBS_OUTUB_Pos) /*!< Bit mask of OUTUB field. */ + +/* DIRTYBIT @Bit 0 : Read Buffer Dirty status */ + #define VPRCSR_NORDIC_OUTUBS_DIRTYBIT_Pos (0UL) /*!< Position of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTUBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_OUTUBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTUBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTUBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTUBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean */ + #define VPRCSR_NORDIC_OUTUBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty */ + + +/** + * @brief OUTBD [VPRCSR_NORDIC_OUTBD] Concatenation of Buffered GPIO Output and GPIO Output + */ + #define VPRCSR_NORDIC_OUTBD (0x00000BE0ul) + #define VPRCSR_NORDIC_OUTBD_ResetValue (0x00000000UL) /*!< Reset value of OUTBD register. */ + +/* OUT @Bits 0..15 : GPIO Output */ + #define VPRCSR_NORDIC_OUTBD_OUT_Pos (0UL) /*!< Position of OUT field. */ + #define VPRCSR_NORDIC_OUTBD_OUT_Msk (0xFFFFUL << VPRCSR_NORDIC_OUTBD_OUT_Pos) /*!< Bit mask of OUT field. */ + +/* OUTB @Bits 16..31 : Buffered GPIO Output */ + #define VPRCSR_NORDIC_OUTBD_OUTB_Pos (16UL) /*!< Position of OUTB field. */ + #define VPRCSR_NORDIC_OUTBD_OUTB_Msk (0xFFFFUL << VPRCSR_NORDIC_OUTBD_OUTB_Pos) /*!< Bit mask of OUTB field. */ + + +/** + * @brief OUTBDTGL [VPRCSR_NORDIC_OUTBDTGL] OUTBD Toggle + */ + #define VPRCSR_NORDIC_OUTBDTGL (0x00000BE1ul) + #define VPRCSR_NORDIC_OUTBDTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTBDTGL register. */ + +/* OUT0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Pos (0UL) /*!< Position of OUT0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT0_Pos) /*!< Bit mask of OUT0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Min (0x0UL) /*!< Min enumerator value of OUT0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Max (0x1UL) /*!< Max enumerator value of OUT0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Pos (1UL) /*!< Position of OUT1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT1_Pos) /*!< Bit mask of OUT1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Min (0x0UL) /*!< Min enumerator value of OUT1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Max (0x1UL) /*!< Max enumerator value of OUT1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Pos (2UL) /*!< Position of OUT2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT2_Pos) /*!< Bit mask of OUT2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Min (0x0UL) /*!< Min enumerator value of OUT2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Max (0x1UL) /*!< Max enumerator value of OUT2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Pos (3UL) /*!< Position of OUT3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT3_Pos) /*!< Bit mask of OUT3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Min (0x0UL) /*!< Min enumerator value of OUT3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Max (0x1UL) /*!< Max enumerator value of OUT3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Pos (4UL) /*!< Position of OUT4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT4_Pos) /*!< Bit mask of OUT4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Min (0x0UL) /*!< Min enumerator value of OUT4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Max (0x1UL) /*!< Max enumerator value of OUT4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Pos (5UL) /*!< Position of OUT5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT5_Pos) /*!< Bit mask of OUT5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Min (0x0UL) /*!< Min enumerator value of OUT5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Max (0x1UL) /*!< Max enumerator value of OUT5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Pos (6UL) /*!< Position of OUT6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT6_Pos) /*!< Bit mask of OUT6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Min (0x0UL) /*!< Min enumerator value of OUT6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Max (0x1UL) /*!< Max enumerator value of OUT6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Pos (7UL) /*!< Position of OUT7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT7_Pos) /*!< Bit mask of OUT7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Min (0x0UL) /*!< Min enumerator value of OUT7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Max (0x1UL) /*!< Max enumerator value of OUT7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Pos (8UL) /*!< Position of OUT8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT8_Pos) /*!< Bit mask of OUT8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Min (0x0UL) /*!< Min enumerator value of OUT8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Max (0x1UL) /*!< Max enumerator value of OUT8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Pos (9UL) /*!< Position of OUT9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT9_Pos) /*!< Bit mask of OUT9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Min (0x0UL) /*!< Min enumerator value of OUT9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Max (0x1UL) /*!< Max enumerator value of OUT9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Pos (10UL) /*!< Position of OUT10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT10_Pos) /*!< Bit mask of OUT10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Min (0x0UL) /*!< Min enumerator value of OUT10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Max (0x1UL) /*!< Max enumerator value of OUT10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Pos (11UL) /*!< Position of OUT11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT11_Pos) /*!< Bit mask of OUT11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Min (0x0UL) /*!< Min enumerator value of OUT11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Max (0x1UL) /*!< Max enumerator value of OUT11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Pos (12UL) /*!< Position of OUT12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT12_Pos) /*!< Bit mask of OUT12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Min (0x0UL) /*!< Min enumerator value of OUT12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Max (0x1UL) /*!< Max enumerator value of OUT12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Pos (13UL) /*!< Position of OUT13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT13_Pos) /*!< Bit mask of OUT13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Min (0x0UL) /*!< Min enumerator value of OUT13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Max (0x1UL) /*!< Max enumerator value of OUT13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Pos (14UL) /*!< Position of OUT14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT14_Pos) /*!< Bit mask of OUT14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Min (0x0UL) /*!< Min enumerator value of OUT14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Max (0x1UL) /*!< Max enumerator value of OUT14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Pos (15UL) /*!< Position of OUT15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT15_Pos) /*!< Bit mask of OUT15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Min (0x0UL) /*!< Min enumerator value of OUT15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Max (0x1UL) /*!< Max enumerator value of OUT15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB0 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Pos (16UL) /*!< Position of OUTB0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB0_Pos) /*!< Bit mask of OUTB0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Min (0x0UL) /*!< Min enumerator value of OUTB0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Max (0x1UL) /*!< Max enumerator value of OUTB0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB1 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Pos (17UL) /*!< Position of OUTB1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB1_Pos) /*!< Bit mask of OUTB1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Min (0x0UL) /*!< Min enumerator value of OUTB1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Max (0x1UL) /*!< Max enumerator value of OUTB1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB2 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Pos (18UL) /*!< Position of OUTB2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB2_Pos) /*!< Bit mask of OUTB2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Min (0x0UL) /*!< Min enumerator value of OUTB2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Max (0x1UL) /*!< Max enumerator value of OUTB2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB3 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Pos (19UL) /*!< Position of OUTB3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB3_Pos) /*!< Bit mask of OUTB3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Min (0x0UL) /*!< Min enumerator value of OUTB3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Max (0x1UL) /*!< Max enumerator value of OUTB3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB4 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Pos (20UL) /*!< Position of OUTB4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB4_Pos) /*!< Bit mask of OUTB4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Min (0x0UL) /*!< Min enumerator value of OUTB4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Max (0x1UL) /*!< Max enumerator value of OUTB4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB5 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Pos (21UL) /*!< Position of OUTB5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB5_Pos) /*!< Bit mask of OUTB5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Min (0x0UL) /*!< Min enumerator value of OUTB5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Max (0x1UL) /*!< Max enumerator value of OUTB5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB6 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Pos (22UL) /*!< Position of OUTB6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB6_Pos) /*!< Bit mask of OUTB6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Min (0x0UL) /*!< Min enumerator value of OUTB6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Max (0x1UL) /*!< Max enumerator value of OUTB6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB7 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Pos (23UL) /*!< Position of OUTB7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB7_Pos) /*!< Bit mask of OUTB7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Min (0x0UL) /*!< Min enumerator value of OUTB7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Max (0x1UL) /*!< Max enumerator value of OUTB7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB8 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Pos (24UL) /*!< Position of OUTB8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB8_Pos) /*!< Bit mask of OUTB8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Min (0x0UL) /*!< Min enumerator value of OUTB8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Max (0x1UL) /*!< Max enumerator value of OUTB8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB9 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Pos (25UL) /*!< Position of OUTB9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB9_Pos) /*!< Bit mask of OUTB9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Min (0x0UL) /*!< Min enumerator value of OUTB9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Max (0x1UL) /*!< Max enumerator value of OUTB9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB10 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Pos (26UL) /*!< Position of OUTB10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB10_Pos) /*!< Bit mask of OUTB10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Min (0x0UL) /*!< Min enumerator value of OUTB10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Max (0x1UL) /*!< Max enumerator value of OUTB10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB11 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Pos (27UL) /*!< Position of OUTB11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB11_Pos) /*!< Bit mask of OUTB11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Min (0x0UL) /*!< Min enumerator value of OUTB11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Max (0x1UL) /*!< Max enumerator value of OUTB11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB12 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Pos (28UL) /*!< Position of OUTB12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB12_Pos) /*!< Bit mask of OUTB12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Min (0x0UL) /*!< Min enumerator value of OUTB12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Max (0x1UL) /*!< Max enumerator value of OUTB12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB13 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Pos (29UL) /*!< Position of OUTB13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB13_Pos) /*!< Bit mask of OUTB13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Min (0x0UL) /*!< Min enumerator value of OUTB13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Max (0x1UL) /*!< Max enumerator value of OUTB13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB14 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Pos (30UL) /*!< Position of OUTB14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB14_Pos) /*!< Bit mask of OUTB14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Min (0x0UL) /*!< Min enumerator value of OUTB14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Max (0x1UL) /*!< Max enumerator value of OUTB14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB15 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Pos (31UL) /*!< Position of OUTB15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB15_Pos) /*!< Bit mask of OUTB15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Min (0x0UL) /*!< Min enumerator value of OUTB15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Max (0x1UL) /*!< Max enumerator value of OUTB15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief OUTBDS [VPRCSR_NORDIC_OUTBDS] OUTBD Dirty Status + */ + #define VPRCSR_NORDIC_OUTBDS (0x00000BE2ul) + #define VPRCSR_NORDIC_OUTBDS_ResetValue (0x00000000UL) /*!< Reset value of OUTBDS register. */ + +/* OUTBD @Bits 0..31 : Write to OUTBD register (if not dirty) */ + #define VPRCSR_NORDIC_OUTBDS_OUTBD_Pos (0UL) /*!< Position of OUTBD field. */ + #define VPRCSR_NORDIC_OUTBDS_OUTBD_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBDS_OUTBD_Pos) /*!< Bit mask of OUTBD field. */ + +/* DIRTYBIT @Bit 0 : Read OUTB and OUT parallel write Dirty status */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Pos (0UL) /*!< Position of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty */ + + +/** + * @brief OUTMODE [VPRCSR_NORDIC_OUTMODE] Serial output mode + */ + #define VPRCSR_NORDIC_OUTMODE (0x00000BE3ul) + #define VPRCSR_NORDIC_OUTMODE_ResetValue (0x00000000UL) /*!< Reset value of OUTMODE register. */ + +/* MODE @Bits 0..2 : Mode */ + #define VPRCSR_NORDIC_OUTMODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_OUTMODE_MODE_Msk (0x7UL << VPRCSR_NORDIC_OUTMODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define VPRCSR_NORDIC_OUTMODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_OUTMODE_MODE_Max (0x4UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_OUTMODE_MODE_NoShifting (0x0UL) /*!< No shifting */ + #define VPRCSR_NORDIC_OUTMODE_MODE_OutBBuf (0x2UL) /*!< Only OUTB used for buffering */ + #define VPRCSR_NORDIC_OUTMODE_MODE_OutBBufToggleClk (0x4UL) /*!< Only OUTB used for buffering, auto-toggle clock line */ + +/* SHIFTMODE @Bit 0 : Shift mode */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Pos (0UL) /*!< Position of SHIFTMODE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Msk (0x1UL << VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Pos) /*!< Bit mask of SHIFTMODE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Min (0x0UL) /*!< Min enumerator value of SHIFTMODE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Max (0x1UL) /*!< Max enumerator value of SHIFTMODE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Disabled (0x0UL) /*!< Shift mode is disabled */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Enabled (0x1UL) /*!< Shift mode is enabled */ + +/* FRAMEWIDTH @Bits 16..20 : Output frame width MODE=0x1: BITS=2^FRAMEWIDTH. Legal FRAMEWIDTH values: 0, 1, 2, 3, 4 MODE=0x2: + BITS=FRAMEWIDTH. Legal values: 1, 2, 3, 4, 5, 6, 7, 8, 16 (9-15 are not legal) MODE=0x4: + BITS=FRAMEWIDTH. Legal values: 1, 2, 3, 4, 5, 6, 7, 8 */ + + #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Pos (16UL) /*!< Position of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Msk (0x1FUL << VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Pos) /*!< Bit mask of FRAMEWIDTH + field.*/ + #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Min (0x00UL) /*!< Min value of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Max (0x10UL) /*!< Max size of FRAMEWIDTH field. */ + +/* SHIFSIZE @Bits 16..19 : Shift size. Only applies if Shift mode is enabled */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Pos (16UL) /*!< Position of SHIFSIZE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Msk (0xFUL << VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Pos) /*!< Bit mask of SHIFSIZE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Min (0x0UL) /*!< Min enumerator value of SHIFSIZE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Max (0x4UL) /*!< Max enumerator value of SHIFSIZE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT1 (0x0UL) /*!< Shift OUT by 1 bit */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT2 (0x1UL) /*!< Shift OUT by 2 bits */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT4 (0x2UL) /*!< Shift OUT by 4 bits */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT8 (0x3UL) /*!< Shift OUT by 8 bits */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT16 (0x4UL) /*!< Shift OUT by 16 bits */ + +/* SEL @Bits 24..27 : Start index of VIO used for shifting from OUTB and to INB. For OUTB, the number of left shifts is given by + (MODE is OUTMODE.MODE): if (MODE < 2) then SHIFTS = 0; else if ((MODE==4) & (SEL==0)) then SHIFTS = 1; + else SHIFTS = SEL; For INB, the number of left shifts is given by (MODE is INMODE.MODE): if (MODE < 2) + then SHIFTS = 0; else if ((MODE==2) & (INSEL==1) & (FRAMEWIDTH==1)) then SHIFTS = 2; else if (SEL==0) then + SHIFTS = 1; else SHIFTS = SEL; */ + + #define VPRCSR_NORDIC_OUTMODE_SEL_Pos (24UL) /*!< Position of SEL field. */ + #define VPRCSR_NORDIC_OUTMODE_SEL_Msk (0xFUL << VPRCSR_NORDIC_OUTMODE_SEL_Pos) /*!< Bit mask of SEL field. */ + #define VPRCSR_NORDIC_OUTMODE_SEL_Min (0x0UL) /*!< Min value of SEL field. */ + #define VPRCSR_NORDIC_OUTMODE_SEL_Max (0xFUL) /*!< Max size of SEL field. */ + + +/** + * @brief OUTMODEB [VPRCSR_NORDIC_OUTMODEB] Buffered OUTMODE register + */ + #define VPRCSR_NORDIC_OUTMODEB (0x00000BE4ul) + #define VPRCSR_NORDIC_OUTMODEB_ResetValue (0x00000000UL) /*!< Reset value of OUTMODEB register. */ + +/* MODE @Bits 0..2 : Mode */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_Msk (0x7UL << VPRCSR_NORDIC_OUTMODEB_MODE_Pos) /*!< Bit mask of MODE field. */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_Max (0x4UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_NoShifting (0x0UL) /*!< No shifting */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_OutBBuf (0x2UL) /*!< Only OUTB used for buffering */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_OutBBufToggleClk (0x4UL) /*!< Only OUTB used for buffering, auto-toggle clock line */ + +/* FRAMEWIDTH @Bits 16..20 : Frame width in bits */ + #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Pos (16UL) /*!< Position of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Msk (0x1FUL << VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Pos) /*!< Bit mask of FRAMEWIDTH + field.*/ + #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Min (0x00UL) /*!< Min value of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Max (0x10UL) /*!< Max size of FRAMEWIDTH field. */ + +/* SEL @Bits 24..27 : Start index of VIO used for shifting from OUTB and to INB. For OUTB, the number of left shifts is given by + (MODE is OUTMODE.MODE): if (MODE < 2) then SHIFTS = 0; else if ((MODE==4) & (SEL==0)) then SHIFTS = 1; + else SHIFTS = SEL; For INB, the number of left shifts is given by (MODE is INMODE.MODE): if (MODE < 2) + then SHIFTS = 0; else if ((MODE==2) & (INSEL==1) & (FRAMEWIDTH==1)) then SHIFTS = 2; else if (SEL==0) then + SHIFTS = 1; else SHIFTS = SEL; */ + + #define VPRCSR_NORDIC_OUTMODEB_SEL_Pos (24UL) /*!< Position of SEL field. */ + #define VPRCSR_NORDIC_OUTMODEB_SEL_Msk (0xFUL << VPRCSR_NORDIC_OUTMODEB_SEL_Pos) /*!< Bit mask of SEL field. */ + #define VPRCSR_NORDIC_OUTMODEB_SEL_Min (0x0UL) /*!< Min value of SEL field. */ + #define VPRCSR_NORDIC_OUTMODEB_SEL_Max (0xFUL) /*!< Max size of SEL field. */ + + +/** + * @brief INMODEB [VPRCSR_NORDIC_INMODEB] Buffered INMODE register + */ + #define VPRCSR_NORDIC_INMODEB (0x00000BE5ul) + #define VPRCSR_NORDIC_INMODEB_ResetValue (0x00000000UL) /*!< Reset value of INMODEB register. */ + +/* MODE @Bits 0..1 : Input Mode */ + #define VPRCSR_NORDIC_INMODEB_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_INMODEB_MODE_Msk (0x3UL << VPRCSR_NORDIC_INMODEB_MODE_Pos) /*!< Bit mask of MODE field. */ + #define VPRCSR_NORDIC_INMODEB_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_INMODEB_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_INMODEB_MODE_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping) */ + #define VPRCSR_NORDIC_INMODEB_MODE_EVENT (0x1UL) /*!< Sampling on Counter1 event */ + #define VPRCSR_NORDIC_INMODEB_MODE_SHIFT (0x2UL) /*!< Sampling and shifting on Counter1 event */ + #define VPRCSR_NORDIC_INMODEB_MODE_SHIFTA (0x3UL) /*!< Sampling and shifting on Counter1 event, independent from output */ + + +/** + * @brief INB [VPRCSR_NORDIC_INB] Buffered GPIO input + */ + #define VPRCSR_NORDIC_INB (0x00000BE6ul) + #define VPRCSR_NORDIC_INB_ResetValue (0x00000000UL) /*!< Reset value of INB register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_INB_PIN0_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_INB_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_INB_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_INB_PIN0_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN0_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_INB_PIN1_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_INB_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_INB_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_INB_PIN1_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN1_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_INB_PIN2_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_INB_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_INB_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_INB_PIN2_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN2_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_INB_PIN3_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_INB_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_INB_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_INB_PIN3_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN3_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_INB_PIN4_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_INB_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_INB_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_INB_PIN4_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN4_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_INB_PIN5_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_INB_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_INB_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_INB_PIN5_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN5_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_INB_PIN6_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_INB_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_INB_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_INB_PIN6_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN6_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_INB_PIN7_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_INB_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_INB_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_INB_PIN7_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN7_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_INB_PIN8_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_INB_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_INB_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_INB_PIN8_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN8_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_INB_PIN9_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_INB_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_INB_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_INB_PIN9_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN9_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_INB_PIN10_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_INB_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_INB_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_INB_PIN10_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN10_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_INB_PIN11_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_INB_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_INB_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_INB_PIN11_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN11_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_INB_PIN12_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_INB_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_INB_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_INB_PIN12_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN12_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_INB_PIN13_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_INB_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_INB_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_INB_PIN13_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN13_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_INB_PIN14_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_INB_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_INB_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_INB_PIN14_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN14_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_INB_PIN15_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_INB_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_INB_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_INB_PIN15_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN15_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define VPRCSR_NORDIC_INB_PIN16_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define VPRCSR_NORDIC_INB_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define VPRCSR_NORDIC_INB_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define VPRCSR_NORDIC_INB_PIN16_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN16_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define VPRCSR_NORDIC_INB_PIN17_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define VPRCSR_NORDIC_INB_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define VPRCSR_NORDIC_INB_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define VPRCSR_NORDIC_INB_PIN17_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN17_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define VPRCSR_NORDIC_INB_PIN18_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define VPRCSR_NORDIC_INB_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define VPRCSR_NORDIC_INB_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define VPRCSR_NORDIC_INB_PIN18_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN18_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define VPRCSR_NORDIC_INB_PIN19_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define VPRCSR_NORDIC_INB_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define VPRCSR_NORDIC_INB_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define VPRCSR_NORDIC_INB_PIN19_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN19_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define VPRCSR_NORDIC_INB_PIN20_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define VPRCSR_NORDIC_INB_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define VPRCSR_NORDIC_INB_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define VPRCSR_NORDIC_INB_PIN20_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN20_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define VPRCSR_NORDIC_INB_PIN21_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define VPRCSR_NORDIC_INB_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define VPRCSR_NORDIC_INB_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define VPRCSR_NORDIC_INB_PIN21_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN21_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define VPRCSR_NORDIC_INB_PIN22_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define VPRCSR_NORDIC_INB_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define VPRCSR_NORDIC_INB_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define VPRCSR_NORDIC_INB_PIN22_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN22_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define VPRCSR_NORDIC_INB_PIN23_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define VPRCSR_NORDIC_INB_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define VPRCSR_NORDIC_INB_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define VPRCSR_NORDIC_INB_PIN23_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN23_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define VPRCSR_NORDIC_INB_PIN24_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define VPRCSR_NORDIC_INB_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define VPRCSR_NORDIC_INB_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define VPRCSR_NORDIC_INB_PIN24_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN24_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define VPRCSR_NORDIC_INB_PIN25_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define VPRCSR_NORDIC_INB_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define VPRCSR_NORDIC_INB_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define VPRCSR_NORDIC_INB_PIN25_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN25_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define VPRCSR_NORDIC_INB_PIN26_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define VPRCSR_NORDIC_INB_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define VPRCSR_NORDIC_INB_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define VPRCSR_NORDIC_INB_PIN26_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN26_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define VPRCSR_NORDIC_INB_PIN27_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define VPRCSR_NORDIC_INB_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define VPRCSR_NORDIC_INB_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define VPRCSR_NORDIC_INB_PIN27_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN27_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define VPRCSR_NORDIC_INB_PIN28_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define VPRCSR_NORDIC_INB_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define VPRCSR_NORDIC_INB_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define VPRCSR_NORDIC_INB_PIN28_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN28_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define VPRCSR_NORDIC_INB_PIN29_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define VPRCSR_NORDIC_INB_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define VPRCSR_NORDIC_INB_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define VPRCSR_NORDIC_INB_PIN29_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN29_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define VPRCSR_NORDIC_INB_PIN30_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define VPRCSR_NORDIC_INB_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define VPRCSR_NORDIC_INB_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define VPRCSR_NORDIC_INB_PIN30_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN30_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define VPRCSR_NORDIC_INB_PIN31_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define VPRCSR_NORDIC_INB_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define VPRCSR_NORDIC_INB_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define VPRCSR_NORDIC_INB_PIN31_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN31_HIGH (0x1UL) /*!< Pin is High */ + + +/** + * @brief OUTUB [VPRCSR_NORDIC_OUTUB] Buffered write to Unshifted parts of OUT + */ + #define VPRCSR_NORDIC_OUTUB (0x00000BE7ul) + #define VPRCSR_NORDIC_OUTUB_ResetValue (0x00000000UL) /*!< Reset value of OUTUB register. */ + +/* OUT @Bits 0..15 : Written to OUT MSBs that are not driven by OUTB shifting. */ + #define VPRCSR_NORDIC_OUTUB_OUT_Pos (0UL) /*!< Position of OUT field. */ + #define VPRCSR_NORDIC_OUTUB_OUT_Msk (0xFFFFUL << VPRCSR_NORDIC_OUTUB_OUT_Pos) /*!< Bit mask of OUT field. */ + + +/** + * @brief SHIFTCNTCOMP [VPRCSR_NORDIC_SHIFTCNTCOMP] SHIFTCNTIN/OUT compare values + */ + #define VPRCSR_NORDIC_SHIFTCNTCOMP (0x00000BE8ul) + #define VPRCSR_NORDIC_SHIFTCNTCOMP_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCNTCOMP register. */ + +/* OUTCOMPVAL @Bits 0..5 : Compare value for SHIFTCNTOUT */ + #define VPRCSR_NORDIC_SHIFTCNTCOMP_OUTCOMPVAL_Pos (0UL) /*!< Position of OUTCOMPVAL field. */ + #define VPRCSR_NORDIC_SHIFTCNTCOMP_OUTCOMPVAL_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCNTCOMP_OUTCOMPVAL_Pos) /*!< Bit mask of + OUTCOMPVAL field.*/ + +/* INCOMPVAL @Bits 8..13 : Compare value for SHIFTCNTIN */ + #define VPRCSR_NORDIC_SHIFTCNTCOMP_INCOMPVAL_Pos (8UL) /*!< Position of INCOMPVAL field. */ + #define VPRCSR_NORDIC_SHIFTCNTCOMP_INCOMPVAL_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCNTCOMP_INCOMPVAL_Pos) /*!< Bit mask of + INCOMPVAL field.*/ + + +/** + * @brief WAITEVENT [VPRCSR_NORDIC_WAITEVENT] Wait for internal event + */ + #define VPRCSR_NORDIC_WAITEVENT (0x00000BE9ul) + #define VPRCSR_NORDIC_WAITEVENT_ResetValue (0x00000000UL) /*!< Reset value of WAITEVENT register. */ + +/* IEVENTCNT0 @Bit 0 : CNT0's event */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTCNT0_Pos (0UL) /*!< Position of IEVENTCNT0 field. */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTCNT0_Msk (0x1UL << VPRCSR_NORDIC_WAITEVENT_IEVENTCNT0_Pos) /*!< Bit mask of IEVENTCNT0 + field.*/ + +/* IEVENTCNT1 @Bit 1 : CNT1's event */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTCNT1_Pos (1UL) /*!< Position of IEVENTCNT1 field. */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTCNT1_Msk (0x1UL << VPRCSR_NORDIC_WAITEVENT_IEVENTCNT1_Pos) /*!< Bit mask of IEVENTCNT1 + field.*/ + +/* IEVENTVIO @Bit 2 : Event generated by a specific VIO pin */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTVIO_Pos (2UL) /*!< Position of IEVENTVIO field. */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTVIO_Msk (0x1UL << VPRCSR_NORDIC_WAITEVENT_IEVENTVIO_Pos) /*!< Bit mask of IEVENTVIO + field.*/ + +/* IEVENTVIOANY @Bit 3 : Event generated by a change in any VIO pin */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTVIOANY_Pos (3UL) /*!< Position of IEVENTVIOANY field. */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTVIOANY_Msk (0x1UL << VPRCSR_NORDIC_WAITEVENT_IEVENTVIOANY_Pos) /*!< Bit mask of + IEVENTVIOANY field.*/ + +/* IEVENTVTASKSANY @Bit 4 : Event when any TASK is triggered */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTVTASKSANY_Pos (4UL) /*!< Position of IEVENTVTASKSANY field. */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTVTASKSANY_Msk (0x1UL << VPRCSR_NORDIC_WAITEVENT_IEVENTVTASKSANY_Pos) /*!< Bit mask of + IEVENTVTASKSANY field.*/ + +/* IEVENTSHIFTCNTOUT @Bit 5 : Event for SHIFTCNTOUT when reaching a compare value defined in SHIFTCNTCOMP */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTSHIFTCNTOUT_Pos (5UL) /*!< Position of IEVENTSHIFTCNTOUT field. */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTSHIFTCNTOUT_Msk (0x1UL << VPRCSR_NORDIC_WAITEVENT_IEVENTSHIFTCNTOUT_Pos) /*!< Bit mask + of IEVENTSHIFTCNTOUT field.*/ + +/* IEVENTSHIFTCNTIN @Bit 6 : Event for SHIFTCNTIN when reaching a compare value defined in SHIFTCNTCOMP */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTSHIFTCNTIN_Pos (6UL) /*!< Position of IEVENTSHIFTCNTIN field. */ + #define VPRCSR_NORDIC_WAITEVENT_IEVENTSHIFTCNTIN_Msk (0x1UL << VPRCSR_NORDIC_WAITEVENT_IEVENTSHIFTCNTIN_Pos) /*!< Bit mask of + IEVENTSHIFTCNTIN field.*/ + + +/** + * @brief WAITINPUT [VPRCSR_NORDIC_WAITINPUT] Wait input + */ + #define VPRCSR_NORDIC_WAITINPUT (0x00000BEAul) + #define VPRCSR_NORDIC_WAITINPUT_ResetValue (0x00000000UL) /*!< Reset value of WAITINPUT register. */ + +/* VTASKSVIO @Bits 0..31 : VTASKS or VIO pins */ + #define VPRCSR_NORDIC_WAITINPUT_VTASKSVIO_Pos (0UL) /*!< Position of VTASKSVIO field. */ + #define VPRCSR_NORDIC_WAITINPUT_VTASKSVIO_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_WAITINPUT_VTASKSVIO_Pos) /*!< Bit mask of + VTASKSVIO field.*/ + + +/** + * @brief RTPINTEN [VPRCSR_NORDIC_RTPINTEN] Interrupt enable + */ + #define VPRCSR_NORDIC_RTPINTEN (0x00000BEBul) + #define VPRCSR_NORDIC_RTPINTEN_ResetValue (0x00000000UL) /*!< Reset value of RTPINTEN register. */ + +/* CNT0 @Bit 0 : Interrupt enable for IEVENTCNT0, alias of VPRNORDICCTRL.CNTIRQENABLE */ + #define VPRCSR_NORDIC_RTPINTEN_CNT0_Pos (0UL) /*!< Position of CNT0 field. */ + #define VPRCSR_NORDIC_RTPINTEN_CNT0_Msk (0x1UL << VPRCSR_NORDIC_RTPINTEN_CNT0_Pos) /*!< Bit mask of CNT0 field. */ + +/* CNT1 @Bit 1 : Interrupt enable for IEVENTCNT1 */ + #define VPRCSR_NORDIC_RTPINTEN_CNT1_Pos (1UL) /*!< Position of CNT1 field. */ + #define VPRCSR_NORDIC_RTPINTEN_CNT1_Msk (0x1UL << VPRCSR_NORDIC_RTPINTEN_CNT1_Pos) /*!< Bit mask of CNT1 field. */ + +/* VIO @Bit 2 : Interrupt enable for IEVENTVIO */ + #define VPRCSR_NORDIC_RTPINTEN_VIO_Pos (2UL) /*!< Position of VIO field. */ + #define VPRCSR_NORDIC_RTPINTEN_VIO_Msk (0x1UL << VPRCSR_NORDIC_RTPINTEN_VIO_Pos) /*!< Bit mask of VIO field. */ + +/* VIOANY @Bit 3 : Interrupt enable for IEVENTVIOANY */ + #define VPRCSR_NORDIC_RTPINTEN_VIOANY_Pos (3UL) /*!< Position of VIOANY field. */ + #define VPRCSR_NORDIC_RTPINTEN_VIOANY_Msk (0x1UL << VPRCSR_NORDIC_RTPINTEN_VIOANY_Pos) /*!< Bit mask of VIOANY field. */ + +/* VTASKSANY @Bit 4 : Interrupt enable for IEVENTVTASKSANY */ + #define VPRCSR_NORDIC_RTPINTEN_VTASKSANY_Pos (4UL) /*!< Position of VTASKSANY field. */ + #define VPRCSR_NORDIC_RTPINTEN_VTASKSANY_Msk (0x1UL << VPRCSR_NORDIC_RTPINTEN_VTASKSANY_Pos) /*!< Bit mask of VTASKSANY + field.*/ + +/* SHIFTCNTOUT @Bit 5 : Interrupt enable for IEVENTSHIFTCNTOUT */ + #define VPRCSR_NORDIC_RTPINTEN_SHIFTCNTOUT_Pos (5UL) /*!< Position of SHIFTCNTOUT field. */ + #define VPRCSR_NORDIC_RTPINTEN_SHIFTCNTOUT_Msk (0x1UL << VPRCSR_NORDIC_RTPINTEN_SHIFTCNTOUT_Pos) /*!< Bit mask of SHIFTCNTOUT + field.*/ + +/* SHIFTCNTIN @Bit 6 : Interrupt enable for IEVENTSHIFTCNTIN */ + #define VPRCSR_NORDIC_RTPINTEN_SHIFTCNTIN_Pos (6UL) /*!< Position of SHIFTCNTIN field. */ + #define VPRCSR_NORDIC_RTPINTEN_SHIFTCNTIN_Msk (0x1UL << VPRCSR_NORDIC_RTPINTEN_SHIFTCNTIN_Pos) /*!< Bit mask of SHIFTCNTIN + field.*/ + + +/** + * @brief OUTUBTRIG [VPRCSR_NORDIC_OUTUBTRIG] OUTUB trigger select + */ + #define VPRCSR_NORDIC_OUTUBTRIG (0x00000BECul) + #define VPRCSR_NORDIC_OUTUBTRIG_ResetValue (0x00000000UL) /*!< Reset value of OUTUBTRIG register. */ + +/* SEL @Bits 0..2 : OUTUBTRIG select */ + #define VPRCSR_NORDIC_OUTUBTRIG_SEL_Pos (0UL) /*!< Position of SEL field. */ + #define VPRCSR_NORDIC_OUTUBTRIG_SEL_Msk (0x7UL << VPRCSR_NORDIC_OUTUBTRIG_SEL_Pos) /*!< Bit mask of SEL field. */ + #define VPRCSR_NORDIC_OUTUBTRIG_SEL_Min (0x0UL) /*!< Min enumerator value of SEL field. */ + #define VPRCSR_NORDIC_OUTUBTRIG_SEL_Max (0x6UL) /*!< Max enumerator value of SEL field. */ + #define VPRCSR_NORDIC_OUTUBTRIG_SEL_IEVENTSHIFTCNTIN (0x6UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTRIG_SEL_IEVENTSHIFTCNTOUT (0x5UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTRIG_SEL_IEVENTVTASKSANY (0x4UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTRIG_SEL_IEVENTVIOANY (0x3UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTRIG_SEL_IEVENTVIO (0x2UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTRIG_SEL_IEVENTCNT1 (0x1UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_OUTUBTRIG_SEL_IEVENTCNT0 (0x0UL) /*!< (unspecified) */ + + + + +/* =========================================================================================================================== */ +/* ================ VREGUSB ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ===================================================== Struct VREGUSB ====================================================== */ +/** + * @brief VREGUSB peripheral + */ + typedef struct { /*!< VREGUSB Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Enable and start VREGUSB so that it can detect VBUS */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop and disable VREGUSB */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_VBUSDETECTED; /*!< (@ 0x00000104) VBUS detected */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_VBUSREMOVED; /*!< (@ 0x00000110) VBUS removed */ + __IM uint32_t RESERVED2[123]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + } NRF_VREGUSB_Type; /*!< Size = 784 (0x310) */ + +/* VREGUSB_TASKS_START: Enable and start VREGUSB so that it can detect VBUS */ + #define VREGUSB_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Enable and start VREGUSB so that it can detect VBUS */ + #define VREGUSB_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define VREGUSB_TASKS_START_TASKS_START_Msk (0x1UL << VREGUSB_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START + field.*/ + #define VREGUSB_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define VREGUSB_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define VREGUSB_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* VREGUSB_TASKS_STOP: Stop and disable VREGUSB */ + #define VREGUSB_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop and disable VREGUSB */ + #define VREGUSB_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define VREGUSB_TASKS_STOP_TASKS_STOP_Msk (0x1UL << VREGUSB_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define VREGUSB_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define VREGUSB_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define VREGUSB_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* VREGUSB_EVENTS_VBUSDETECTED: VBUS detected */ + #define VREGUSB_EVENTS_VBUSDETECTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_VBUSDETECTED register. */ + +/* EVENTS_VBUSDETECTED @Bit 0 : VBUS detected */ + #define VREGUSB_EVENTS_VBUSDETECTED_EVENTS_VBUSDETECTED_Pos (0UL) /*!< Position of EVENTS_VBUSDETECTED field. */ + #define VREGUSB_EVENTS_VBUSDETECTED_EVENTS_VBUSDETECTED_Msk (0x1UL << VREGUSB_EVENTS_VBUSDETECTED_EVENTS_VBUSDETECTED_Pos) + /*!< Bit mask of EVENTS_VBUSDETECTED field.*/ + #define VREGUSB_EVENTS_VBUSDETECTED_EVENTS_VBUSDETECTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_VBUSDETECTED field. */ + #define VREGUSB_EVENTS_VBUSDETECTED_EVENTS_VBUSDETECTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_VBUSDETECTED field. */ + #define VREGUSB_EVENTS_VBUSDETECTED_EVENTS_VBUSDETECTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define VREGUSB_EVENTS_VBUSDETECTED_EVENTS_VBUSDETECTED_Generated (0x1UL) /*!< Event generated */ + + +/* VREGUSB_EVENTS_VBUSREMOVED: VBUS removed */ + #define VREGUSB_EVENTS_VBUSREMOVED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_VBUSREMOVED register. */ + +/* EVENTS_VBUSREMOVED @Bit 0 : VBUS removed */ + #define VREGUSB_EVENTS_VBUSREMOVED_EVENTS_VBUSREMOVED_Pos (0UL) /*!< Position of EVENTS_VBUSREMOVED field. */ + #define VREGUSB_EVENTS_VBUSREMOVED_EVENTS_VBUSREMOVED_Msk (0x1UL << VREGUSB_EVENTS_VBUSREMOVED_EVENTS_VBUSREMOVED_Pos) /*!< + Bit mask of EVENTS_VBUSREMOVED field.*/ + #define VREGUSB_EVENTS_VBUSREMOVED_EVENTS_VBUSREMOVED_Min (0x0UL) /*!< Min enumerator value of EVENTS_VBUSREMOVED field. */ + #define VREGUSB_EVENTS_VBUSREMOVED_EVENTS_VBUSREMOVED_Max (0x1UL) /*!< Max enumerator value of EVENTS_VBUSREMOVED field. */ + #define VREGUSB_EVENTS_VBUSREMOVED_EVENTS_VBUSREMOVED_NotGenerated (0x0UL) /*!< Event not generated */ + #define VREGUSB_EVENTS_VBUSREMOVED_EVENTS_VBUSREMOVED_Generated (0x1UL) /*!< Event generated */ + + +/* VREGUSB_INTEN: Enable or disable interrupt */ + #define VREGUSB_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* VBUSDETECTED @Bit 1 : Enable or disable interrupt for event VBUSDETECTED */ + #define VREGUSB_INTEN_VBUSDETECTED_Pos (1UL) /*!< Position of VBUSDETECTED field. */ + #define VREGUSB_INTEN_VBUSDETECTED_Msk (0x1UL << VREGUSB_INTEN_VBUSDETECTED_Pos) /*!< Bit mask of VBUSDETECTED field. */ + #define VREGUSB_INTEN_VBUSDETECTED_Min (0x0UL) /*!< Min enumerator value of VBUSDETECTED field. */ + #define VREGUSB_INTEN_VBUSDETECTED_Max (0x1UL) /*!< Max enumerator value of VBUSDETECTED field. */ + #define VREGUSB_INTEN_VBUSDETECTED_Disabled (0x0UL) /*!< Disable */ + #define VREGUSB_INTEN_VBUSDETECTED_Enabled (0x1UL) /*!< Enable */ + +/* VBUSREMOVED @Bit 4 : Enable or disable interrupt for event VBUSREMOVED */ + #define VREGUSB_INTEN_VBUSREMOVED_Pos (4UL) /*!< Position of VBUSREMOVED field. */ + #define VREGUSB_INTEN_VBUSREMOVED_Msk (0x1UL << VREGUSB_INTEN_VBUSREMOVED_Pos) /*!< Bit mask of VBUSREMOVED field. */ + #define VREGUSB_INTEN_VBUSREMOVED_Min (0x0UL) /*!< Min enumerator value of VBUSREMOVED field. */ + #define VREGUSB_INTEN_VBUSREMOVED_Max (0x1UL) /*!< Max enumerator value of VBUSREMOVED field. */ + #define VREGUSB_INTEN_VBUSREMOVED_Disabled (0x0UL) /*!< Disable */ + #define VREGUSB_INTEN_VBUSREMOVED_Enabled (0x1UL) /*!< Enable */ + + +/* VREGUSB_INTENSET: Enable interrupt */ + #define VREGUSB_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* VBUSDETECTED @Bit 1 : Write '1' to enable interrupt for event VBUSDETECTED */ + #define VREGUSB_INTENSET_VBUSDETECTED_Pos (1UL) /*!< Position of VBUSDETECTED field. */ + #define VREGUSB_INTENSET_VBUSDETECTED_Msk (0x1UL << VREGUSB_INTENSET_VBUSDETECTED_Pos) /*!< Bit mask of VBUSDETECTED field. */ + #define VREGUSB_INTENSET_VBUSDETECTED_Min (0x0UL) /*!< Min enumerator value of VBUSDETECTED field. */ + #define VREGUSB_INTENSET_VBUSDETECTED_Max (0x1UL) /*!< Max enumerator value of VBUSDETECTED field. */ + #define VREGUSB_INTENSET_VBUSDETECTED_Set (0x1UL) /*!< Enable */ + #define VREGUSB_INTENSET_VBUSDETECTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define VREGUSB_INTENSET_VBUSDETECTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* VBUSREMOVED @Bit 4 : Write '1' to enable interrupt for event VBUSREMOVED */ + #define VREGUSB_INTENSET_VBUSREMOVED_Pos (4UL) /*!< Position of VBUSREMOVED field. */ + #define VREGUSB_INTENSET_VBUSREMOVED_Msk (0x1UL << VREGUSB_INTENSET_VBUSREMOVED_Pos) /*!< Bit mask of VBUSREMOVED field. */ + #define VREGUSB_INTENSET_VBUSREMOVED_Min (0x0UL) /*!< Min enumerator value of VBUSREMOVED field. */ + #define VREGUSB_INTENSET_VBUSREMOVED_Max (0x1UL) /*!< Max enumerator value of VBUSREMOVED field. */ + #define VREGUSB_INTENSET_VBUSREMOVED_Set (0x1UL) /*!< Enable */ + #define VREGUSB_INTENSET_VBUSREMOVED_Disabled (0x0UL) /*!< Read: Disabled */ + #define VREGUSB_INTENSET_VBUSREMOVED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* VREGUSB_INTENCLR: Disable interrupt */ + #define VREGUSB_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* VBUSDETECTED @Bit 1 : Write '1' to disable interrupt for event VBUSDETECTED */ + #define VREGUSB_INTENCLR_VBUSDETECTED_Pos (1UL) /*!< Position of VBUSDETECTED field. */ + #define VREGUSB_INTENCLR_VBUSDETECTED_Msk (0x1UL << VREGUSB_INTENCLR_VBUSDETECTED_Pos) /*!< Bit mask of VBUSDETECTED field. */ + #define VREGUSB_INTENCLR_VBUSDETECTED_Min (0x0UL) /*!< Min enumerator value of VBUSDETECTED field. */ + #define VREGUSB_INTENCLR_VBUSDETECTED_Max (0x1UL) /*!< Max enumerator value of VBUSDETECTED field. */ + #define VREGUSB_INTENCLR_VBUSDETECTED_Clear (0x1UL) /*!< Disable */ + #define VREGUSB_INTENCLR_VBUSDETECTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define VREGUSB_INTENCLR_VBUSDETECTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* VBUSREMOVED @Bit 4 : Write '1' to disable interrupt for event VBUSREMOVED */ + #define VREGUSB_INTENCLR_VBUSREMOVED_Pos (4UL) /*!< Position of VBUSREMOVED field. */ + #define VREGUSB_INTENCLR_VBUSREMOVED_Msk (0x1UL << VREGUSB_INTENCLR_VBUSREMOVED_Pos) /*!< Bit mask of VBUSREMOVED field. */ + #define VREGUSB_INTENCLR_VBUSREMOVED_Min (0x0UL) /*!< Min enumerator value of VBUSREMOVED field. */ + #define VREGUSB_INTENCLR_VBUSREMOVED_Max (0x1UL) /*!< Max enumerator value of VBUSREMOVED field. */ + #define VREGUSB_INTENCLR_VBUSREMOVED_Clear (0x1UL) /*!< Disable */ + #define VREGUSB_INTENCLR_VBUSREMOVED_Disabled (0x0UL) /*!< Read: Disabled */ + #define VREGUSB_INTENCLR_VBUSREMOVED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* VREGUSB_INTPEND: Pending interrupts */ + #define VREGUSB_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* VBUSDETECTED @Bit 1 : Read pending status of interrupt for event VBUSDETECTED */ + #define VREGUSB_INTPEND_VBUSDETECTED_Pos (1UL) /*!< Position of VBUSDETECTED field. */ + #define VREGUSB_INTPEND_VBUSDETECTED_Msk (0x1UL << VREGUSB_INTPEND_VBUSDETECTED_Pos) /*!< Bit mask of VBUSDETECTED field. */ + #define VREGUSB_INTPEND_VBUSDETECTED_Min (0x0UL) /*!< Min enumerator value of VBUSDETECTED field. */ + #define VREGUSB_INTPEND_VBUSDETECTED_Max (0x1UL) /*!< Max enumerator value of VBUSDETECTED field. */ + #define VREGUSB_INTPEND_VBUSDETECTED_NotPending (0x0UL) /*!< Read: Not pending */ + #define VREGUSB_INTPEND_VBUSDETECTED_Pending (0x1UL) /*!< Read: Pending */ + +/* VBUSREMOVED @Bit 4 : Read pending status of interrupt for event VBUSREMOVED */ + #define VREGUSB_INTPEND_VBUSREMOVED_Pos (4UL) /*!< Position of VBUSREMOVED field. */ + #define VREGUSB_INTPEND_VBUSREMOVED_Msk (0x1UL << VREGUSB_INTPEND_VBUSREMOVED_Pos) /*!< Bit mask of VBUSREMOVED field. */ + #define VREGUSB_INTPEND_VBUSREMOVED_Min (0x0UL) /*!< Min enumerator value of VBUSREMOVED field. */ + #define VREGUSB_INTPEND_VBUSREMOVED_Max (0x1UL) /*!< Max enumerator value of VBUSREMOVED field. */ + #define VREGUSB_INTPEND_VBUSREMOVED_NotPending (0x0UL) /*!< Read: Not pending */ + #define VREGUSB_INTPEND_VBUSREMOVED_Pending (0x1UL) /*!< Read: Pending */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct WDT ======================================================== */ +/** + * @brief Watchdog Timer + */ + typedef struct { /*!< WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start WDT */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop WDT */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Watchdog stopped */ + __IM uint32_t RESERVED2[30]; + __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED3[95]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[6]; + __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ + __IM uint32_t RESERVED5[53]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED6[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED7[4]; + __OM uint32_t TSEN; /*!< (@ 0x00000520) Task stop enable */ + __IM uint32_t RESERVED8[55]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Reload request n */ + } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + +/* WDT_TASKS_START: Start WDT */ + #define WDT_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start WDT */ + #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define WDT_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define WDT_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define WDT_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* WDT_TASKS_STOP: Stop WDT */ + #define WDT_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop WDT */ + #define WDT_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define WDT_TASKS_STOP_TASKS_STOP_Msk (0x1UL << WDT_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define WDT_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define WDT_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define WDT_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* WDT_SUBSCRIBE_START: Subscribe configuration for task START */ + #define WDT_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define WDT_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define WDT_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define WDT_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define WDT_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define WDT_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define WDT_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* WDT_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define WDT_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define WDT_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define WDT_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define WDT_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define WDT_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define WDT_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define WDT_SUBSCRIBE_STOP_EN_Msk (0x1UL << WDT_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define WDT_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define WDT_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define WDT_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define WDT_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* WDT_EVENTS_TIMEOUT: Watchdog timeout */ + #define WDT_EVENTS_TIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TIMEOUT register. */ + +/* EVENTS_TIMEOUT @Bit 0 : Watchdog timeout */ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT + field.*/ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of EVENTS_TIMEOUT field. */ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of EVENTS_TIMEOUT field. */ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0x0UL) /*!< Event not generated */ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (0x1UL) /*!< Event generated */ + + +/* WDT_EVENTS_STOPPED: Watchdog stopped */ + #define WDT_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : Watchdog stopped */ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED + field.*/ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* WDT_PUBLISH_TIMEOUT: Publish configuration for event TIMEOUT */ + #define WDT_PUBLISH_TIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TIMEOUT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TIMEOUT will publish to */ + #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define WDT_PUBLISH_TIMEOUT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define WDT_PUBLISH_TIMEOUT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */ + #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */ + #define WDT_PUBLISH_TIMEOUT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define WDT_PUBLISH_TIMEOUT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define WDT_PUBLISH_TIMEOUT_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* WDT_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define WDT_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define WDT_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define WDT_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << WDT_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define WDT_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define WDT_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define WDT_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define WDT_PUBLISH_STOPPED_EN_Msk (0x1UL << WDT_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define WDT_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define WDT_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define WDT_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define WDT_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* WDT_INTENSET: Enable interrupt */ + #define WDT_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* TIMEOUT @Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ + #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ + #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define WDT_INTENSET_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define WDT_INTENSET_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define WDT_INTENSET_TIMEOUT_Set (0x1UL) /*!< Enable */ + #define WDT_INTENSET_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_INTENSET_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define WDT_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define WDT_INTENSET_STOPPED_Msk (0x1UL << WDT_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define WDT_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define WDT_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define WDT_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define WDT_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* WDT_INTENCLR: Disable interrupt */ + #define WDT_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* TIMEOUT @Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ + #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ + #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define WDT_INTENCLR_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define WDT_INTENCLR_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define WDT_INTENCLR_TIMEOUT_Clear (0x1UL) /*!< Disable */ + #define WDT_INTENCLR_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_INTENCLR_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define WDT_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define WDT_INTENCLR_STOPPED_Msk (0x1UL << WDT_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define WDT_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define WDT_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define WDT_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define WDT_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* WDT_NMIENSET: Enable interrupt */ + #define WDT_NMIENSET_ResetValue (0x00000000UL) /*!< Reset value of NMIENSET register. */ + +/* TIMEOUT @Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ + #define WDT_NMIENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ + #define WDT_NMIENSET_TIMEOUT_Msk (0x1UL << WDT_NMIENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define WDT_NMIENSET_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define WDT_NMIENSET_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define WDT_NMIENSET_TIMEOUT_Set (0x1UL) /*!< Enable */ + #define WDT_NMIENSET_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_NMIENSET_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define WDT_NMIENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define WDT_NMIENSET_STOPPED_Msk (0x1UL << WDT_NMIENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define WDT_NMIENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define WDT_NMIENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define WDT_NMIENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define WDT_NMIENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_NMIENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* WDT_NMIENCLR: Disable interrupt */ + #define WDT_NMIENCLR_ResetValue (0x00000000UL) /*!< Reset value of NMIENCLR register. */ + +/* TIMEOUT @Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ + #define WDT_NMIENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ + #define WDT_NMIENCLR_TIMEOUT_Msk (0x1UL << WDT_NMIENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define WDT_NMIENCLR_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define WDT_NMIENCLR_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define WDT_NMIENCLR_TIMEOUT_Clear (0x1UL) /*!< Disable */ + #define WDT_NMIENCLR_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_NMIENCLR_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define WDT_NMIENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define WDT_NMIENCLR_STOPPED_Msk (0x1UL << WDT_NMIENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define WDT_NMIENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define WDT_NMIENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define WDT_NMIENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define WDT_NMIENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_NMIENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* WDT_RUNSTATUS: Run status */ + #define WDT_RUNSTATUS_ResetValue (0x00000000UL) /*!< Reset value of RUNSTATUS register. */ + +/* RUNSTATUSWDT @Bit 0 : Indicates whether or not WDT is running */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_Min (0x0UL) /*!< Min enumerator value of RUNSTATUSWDT field. */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_Max (0x1UL) /*!< Max enumerator value of RUNSTATUSWDT field. */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0x0UL) /*!< Watchdog is not running */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (0x1UL) /*!< Watchdog is running */ + + +/* WDT_REQSTATUS: Request status */ + #define WDT_REQSTATUS_ResetValue (0x00000001UL) /*!< Reset value of REQSTATUS register. */ + +/* RR0 @Bit 0 : Request status for RR[0] register */ + #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ + #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ + #define WDT_REQSTATUS_RR0_Min (0x0UL) /*!< Min enumerator value of RR0 field. */ + #define WDT_REQSTATUS_RR0_Max (0x1UL) /*!< Max enumerator value of RR0 field. */ + #define WDT_REQSTATUS_RR0_DisabledOrRequested (0x0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (0x1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* RR1 @Bit 1 : Request status for RR[1] register */ + #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ + #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ + #define WDT_REQSTATUS_RR1_Min (0x0UL) /*!< Min enumerator value of RR1 field. */ + #define WDT_REQSTATUS_RR1_Max (0x1UL) /*!< Max enumerator value of RR1 field. */ + #define WDT_REQSTATUS_RR1_DisabledOrRequested (0x0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (0x1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* RR2 @Bit 2 : Request status for RR[2] register */ + #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ + #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ + #define WDT_REQSTATUS_RR2_Min (0x0UL) /*!< Min enumerator value of RR2 field. */ + #define WDT_REQSTATUS_RR2_Max (0x1UL) /*!< Max enumerator value of RR2 field. */ + #define WDT_REQSTATUS_RR2_DisabledOrRequested (0x0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (0x1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* RR3 @Bit 3 : Request status for RR[3] register */ + #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ + #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ + #define WDT_REQSTATUS_RR3_Min (0x0UL) /*!< Min enumerator value of RR3 field. */ + #define WDT_REQSTATUS_RR3_Max (0x1UL) /*!< Max enumerator value of RR3 field. */ + #define WDT_REQSTATUS_RR3_DisabledOrRequested (0x0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (0x1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* RR4 @Bit 4 : Request status for RR[4] register */ + #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ + #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ + #define WDT_REQSTATUS_RR4_Min (0x0UL) /*!< Min enumerator value of RR4 field. */ + #define WDT_REQSTATUS_RR4_Max (0x1UL) /*!< Max enumerator value of RR4 field. */ + #define WDT_REQSTATUS_RR4_DisabledOrRequested (0x0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (0x1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* RR5 @Bit 5 : Request status for RR[5] register */ + #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ + #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ + #define WDT_REQSTATUS_RR5_Min (0x0UL) /*!< Min enumerator value of RR5 field. */ + #define WDT_REQSTATUS_RR5_Max (0x1UL) /*!< Max enumerator value of RR5 field. */ + #define WDT_REQSTATUS_RR5_DisabledOrRequested (0x0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (0x1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* RR6 @Bit 6 : Request status for RR[6] register */ + #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ + #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ + #define WDT_REQSTATUS_RR6_Min (0x0UL) /*!< Min enumerator value of RR6 field. */ + #define WDT_REQSTATUS_RR6_Max (0x1UL) /*!< Max enumerator value of RR6 field. */ + #define WDT_REQSTATUS_RR6_DisabledOrRequested (0x0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (0x1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* RR7 @Bit 7 : Request status for RR[7] register */ + #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ + #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ + #define WDT_REQSTATUS_RR7_Min (0x0UL) /*!< Min enumerator value of RR7 field. */ + #define WDT_REQSTATUS_RR7_Max (0x1UL) /*!< Max enumerator value of RR7 field. */ + #define WDT_REQSTATUS_RR7_DisabledOrRequested (0x0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (0x1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + + +/* WDT_CRV: Counter reload value */ + #define WDT_CRV_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CRV register. */ + +/* CRV @Bits 0..31 : Counter reload value in number of cycles of the 32.768 kHz clock */ + #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ + #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + #define WDT_CRV_CRV_Min (0x0000000FUL) /*!< Min value of CRV field. */ + #define WDT_CRV_CRV_Max (0xFFFFFFFFUL) /*!< Max size of CRV field. */ + + +/* WDT_RREN: Enable register for reload request registers */ + #define WDT_RREN_ResetValue (0x00000001UL) /*!< Reset value of RREN register. */ + +/* RR0 @Bit 0 : Enable or disable RR[0] register */ + #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ + #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ + #define WDT_RREN_RR0_Min (0x0UL) /*!< Min enumerator value of RR0 field. */ + #define WDT_RREN_RR0_Max (0x1UL) /*!< Max enumerator value of RR0 field. */ + #define WDT_RREN_RR0_Disabled (0x0UL) /*!< Disable RR[0] register */ + #define WDT_RREN_RR0_Enabled (0x1UL) /*!< Enable RR[0] register */ + +/* RR1 @Bit 1 : Enable or disable RR[1] register */ + #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ + #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ + #define WDT_RREN_RR1_Min (0x0UL) /*!< Min enumerator value of RR1 field. */ + #define WDT_RREN_RR1_Max (0x1UL) /*!< Max enumerator value of RR1 field. */ + #define WDT_RREN_RR1_Disabled (0x0UL) /*!< Disable RR[1] register */ + #define WDT_RREN_RR1_Enabled (0x1UL) /*!< Enable RR[1] register */ + +/* RR2 @Bit 2 : Enable or disable RR[2] register */ + #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ + #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ + #define WDT_RREN_RR2_Min (0x0UL) /*!< Min enumerator value of RR2 field. */ + #define WDT_RREN_RR2_Max (0x1UL) /*!< Max enumerator value of RR2 field. */ + #define WDT_RREN_RR2_Disabled (0x0UL) /*!< Disable RR[2] register */ + #define WDT_RREN_RR2_Enabled (0x1UL) /*!< Enable RR[2] register */ + +/* RR3 @Bit 3 : Enable or disable RR[3] register */ + #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ + #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ + #define WDT_RREN_RR3_Min (0x0UL) /*!< Min enumerator value of RR3 field. */ + #define WDT_RREN_RR3_Max (0x1UL) /*!< Max enumerator value of RR3 field. */ + #define WDT_RREN_RR3_Disabled (0x0UL) /*!< Disable RR[3] register */ + #define WDT_RREN_RR3_Enabled (0x1UL) /*!< Enable RR[3] register */ + +/* RR4 @Bit 4 : Enable or disable RR[4] register */ + #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ + #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ + #define WDT_RREN_RR4_Min (0x0UL) /*!< Min enumerator value of RR4 field. */ + #define WDT_RREN_RR4_Max (0x1UL) /*!< Max enumerator value of RR4 field. */ + #define WDT_RREN_RR4_Disabled (0x0UL) /*!< Disable RR[4] register */ + #define WDT_RREN_RR4_Enabled (0x1UL) /*!< Enable RR[4] register */ + +/* RR5 @Bit 5 : Enable or disable RR[5] register */ + #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ + #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ + #define WDT_RREN_RR5_Min (0x0UL) /*!< Min enumerator value of RR5 field. */ + #define WDT_RREN_RR5_Max (0x1UL) /*!< Max enumerator value of RR5 field. */ + #define WDT_RREN_RR5_Disabled (0x0UL) /*!< Disable RR[5] register */ + #define WDT_RREN_RR5_Enabled (0x1UL) /*!< Enable RR[5] register */ + +/* RR6 @Bit 6 : Enable or disable RR[6] register */ + #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ + #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ + #define WDT_RREN_RR6_Min (0x0UL) /*!< Min enumerator value of RR6 field. */ + #define WDT_RREN_RR6_Max (0x1UL) /*!< Max enumerator value of RR6 field. */ + #define WDT_RREN_RR6_Disabled (0x0UL) /*!< Disable RR[6] register */ + #define WDT_RREN_RR6_Enabled (0x1UL) /*!< Enable RR[6] register */ + +/* RR7 @Bit 7 : Enable or disable RR[7] register */ + #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ + #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ + #define WDT_RREN_RR7_Min (0x0UL) /*!< Min enumerator value of RR7 field. */ + #define WDT_RREN_RR7_Max (0x1UL) /*!< Max enumerator value of RR7 field. */ + #define WDT_RREN_RR7_Disabled (0x0UL) /*!< Disable RR[7] register */ + #define WDT_RREN_RR7_Enabled (0x1UL) /*!< Enable RR[7] register */ + + +/* WDT_CONFIG: Configuration register */ + #define WDT_CONFIG_ResetValue (0x00000001UL) /*!< Reset value of CONFIG register. */ + +/* SLEEP @Bit 0 : Configure WDT to either be paused, or kept running, while the CPU is sleeping */ + #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ + #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ + #define WDT_CONFIG_SLEEP_Min (0x0UL) /*!< Min enumerator value of SLEEP field. */ + #define WDT_CONFIG_SLEEP_Max (0x1UL) /*!< Max enumerator value of SLEEP field. */ + #define WDT_CONFIG_SLEEP_Pause (0x0UL) /*!< Pause WDT while the CPU is sleeping */ + #define WDT_CONFIG_SLEEP_Run (0x1UL) /*!< Keep WDT running while the CPU is sleeping */ + +/* HALT @Bit 3 : Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger */ + #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ + #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ + #define WDT_CONFIG_HALT_Min (0x0UL) /*!< Min enumerator value of HALT field. */ + #define WDT_CONFIG_HALT_Max (0x1UL) /*!< Max enumerator value of HALT field. */ + #define WDT_CONFIG_HALT_Pause (0x0UL) /*!< Pause WDT while the CPU is halted by the debugger */ + #define WDT_CONFIG_HALT_Run (0x1UL) /*!< Keep WDT running while the CPU is halted by the debugger */ + +/* STOPEN @Bit 6 : Allow stopping WDT */ + #define WDT_CONFIG_STOPEN_Pos (6UL) /*!< Position of STOPEN field. */ + #define WDT_CONFIG_STOPEN_Msk (0x1UL << WDT_CONFIG_STOPEN_Pos) /*!< Bit mask of STOPEN field. */ + #define WDT_CONFIG_STOPEN_Min (0x0UL) /*!< Min enumerator value of STOPEN field. */ + #define WDT_CONFIG_STOPEN_Max (0x1UL) /*!< Max enumerator value of STOPEN field. */ + #define WDT_CONFIG_STOPEN_Disable (0x0UL) /*!< Do not allow stopping WDT */ + #define WDT_CONFIG_STOPEN_Enable (0x1UL) /*!< Allow stopping WDT */ + + +/* WDT_TSEN: Task stop enable */ + #define WDT_TSEN_ResetValue (0x00000000UL) /*!< Reset value of TSEN register. */ + +/* TSEN @Bits 0..31 : Allow stopping WDT */ + #define WDT_TSEN_TSEN_Pos (0UL) /*!< Position of TSEN field. */ + #define WDT_TSEN_TSEN_Msk (0xFFFFFFFFUL << WDT_TSEN_TSEN_Pos) /*!< Bit mask of TSEN field. */ + #define WDT_TSEN_TSEN_Min (0x6E524635UL) /*!< Min enumerator value of TSEN field. */ + #define WDT_TSEN_TSEN_Max (0x6E524635UL) /*!< Max enumerator value of TSEN field. */ + #define WDT_TSEN_TSEN_Enable (0x6E524635UL) /*!< Value to allow stopping WDT */ + + +/* WDT_RR: Reload request n */ + #define WDT_RR_MaxCount (8UL) /*!< Max size of RR[8] array. */ + #define WDT_RR_MaxIndex (7UL) /*!< Max index of RR[8] array. */ + #define WDT_RR_MinIndex (0UL) /*!< Min index of RR[8] array. */ + #define WDT_RR_ResetValue (0x00000000UL) /*!< Reset value of RR[8] register. */ + +/* RR @Bits 0..31 : Reload request register */ + #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ + #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ + #define WDT_RR_RR_Min (0x6E524635UL) /*!< Min enumerator value of RR field. */ + #define WDT_RR_RR_Max (0x6E524635UL) /*!< Max enumerator value of RR field. */ + #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* ========================================== End of section using anonymous unions ========================================== */ + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif +#endif /* NRF54LM20A_TYPES_H */ + diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_version.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_version.h new file mode 100644 index 0000000..4202cbc --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_version.h @@ -0,0 +1,52 @@ +/* + +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF54LM20A_VERSION_H +#define NRF54LM20A_VERSION_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#define MDK_SOURCE_VERSION_MAJOR 0 /*!< Major version of the datasheet. */ +#define MDK_SOURCE_VERSION_MINOR 7 /*!< Minor version of the datasheet. */ +#define MDK_SOURCE_VERSION_MICRO 1 /*!< Micro version of the datasheet. */ + + +#ifdef __cplusplus +} +#endif +#endif /* NRF54LM20A_VERSION_H */ + diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_xxaa_application_memory.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_xxaa_application_memory.h new file mode 100644 index 0000000..19ec8a6 --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_xxaa_application_memory.h @@ -0,0 +1,77 @@ +/* +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 16384 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 16384 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x001FD000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x00FFD000 +#define NRF_MEMORY_UICR_SIZE 0x00001000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00040000 + +/* Device memory RAM2: */ +#define NRF_MEMORY_RAM2_BASE 0x20040000 +#define NRF_MEMORY_RAM2_SIZE 0x00040000 + +/* Device memory PeripheralsAPBS: */ +#define NRF_MEMORY_PERIPHERALSAPBS_BASE 0x52000000 +#define NRF_MEMORY_PERIPHERALSAPBS_SIZE 0x00200000 + +/* Device memory PeripheralsAPBNS: */ +#define NRF_MEMORY_PERIPHERALSAPBNS_BASE 0x42000000 +#define NRF_MEMORY_PERIPHERALSAPBNS_SIZE 0x00200000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x52840000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00003000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_xxaa_flpr_memory.h b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_xxaa_flpr_memory.h new file mode 100644 index 0000000..4d28bf8 --- /dev/null +++ b/cores/nRF5/nordic/nrfx/mdk/nrf54lm20a_xxaa_flpr_memory.h @@ -0,0 +1,73 @@ +/* +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 16384 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 16384 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x00000000 +#define NRF_MEMORY_FLASH_SIZE 0x001FD000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x20000000 +#define NRF_MEMORY_RAM_SIZE 0x00040000 + +/* Device memory RAM2: */ +#define NRF_MEMORY_RAM2_BASE 0x20040000 +#define NRF_MEMORY_RAM2_SIZE 0x00040000 + +/* Device memory PeripheralsAPBS: */ +#define NRF_MEMORY_PERIPHERALSAPBS_BASE 0x54000000 +#define NRF_MEMORY_PERIPHERALSAPBS_SIZE 0x00200000 + +/* Device memory PeripheralsAPBNS: */ +#define NRF_MEMORY_PERIPHERALSAPBNS_BASE 0x44000000 +#define NRF_MEMORY_PERIPHERALSAPBNS_SIZE 0x00200000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x54840000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00003000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf_erratas.h b/cores/nRF5/nordic/nrfx/mdk/nrf_erratas.h index eeb4b4e..156ed50 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf_erratas.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf_erratas.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -45,8 +45,8 @@ NRF_MDK_VERSION_ASSERT_AT_LEAST(8,34,0); #include "nrf51_erratas.h" #include "nrf52_erratas.h" #include "nrf53_erratas.h" -#include "nrf54l_erratas.h" #include "nrf54h_erratas.h" +#include "nrf54l_erratas.h" #include "nrf91_erratas.h" /*lint --flb "Leave library region" */ diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf_mem.h b/cores/nRF5/nordic/nrfx/mdk/nrf_mem.h index 01100b9..6ecbad0 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf_mem.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf_mem.h @@ -1,5 +1,5 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -74,12 +74,24 @@ POSSIBILITY OF SUCH DAMAGE. #if defined(NRF_NETWORK) #include "nrf5340_xxaa_network_memory.h" #endif -#elif defined(NRF54LV10A_ENGA_XXAA) +#elif defined(NRF54H20_XXAA) + #if defined(NRF_SECURE) + #include "nrf54h20_xxaa_secure_memory.h" + #endif #if defined(NRF_APPLICATION) - #include "nrf54lv10a_enga_xxaa_application_memory.h" + #include "nrf54h20_xxaa_application_memory.h" + #endif + #if defined(NRF_RADIOCORE) + #include "nrf54h20_xxaa_radiocore_memory.h" + #endif + #if defined(NRF_SYSCTRL) + #include "nrf54h20_xxaa_sysctrl_memory.h" + #endif + #if defined(NRF_PPR) + #include "nrf54h20_xxaa_ppr_memory.h" #endif #if defined(NRF_FLPR) - #include "nrf54lv10a_enga_xxaa_flpr_memory.h" + #include "nrf54h20_xxaa_flpr_memory.h" #endif #elif defined(NRF54L05_XXAA) #if defined(NRF_APPLICATION) @@ -102,27 +114,37 @@ POSSIBILITY OF SUCH DAMAGE. #if defined(NRF_FLPR) #include "nrf54l15_xxaa_flpr_memory.h" #endif -#elif defined(NRF54LM20A_ENGA_XXAA) +#elif defined(NRF54LC10A_XXAA) #if defined(NRF_APPLICATION) - #include "nrf54lm20a_enga_xxaa_application_memory.h" + #include "nrf54lc10a_xxaa_application_memory.h" #endif #if defined(NRF_FLPR) - #include "nrf54lm20a_enga_xxaa_flpr_memory.h" + #include "nrf54lc10a_xxaa_flpr_memory.h" #endif -#elif defined(NRF54LS05B_ENGA_XXAA) - #include "nrf54ls05b_enga_xxaa_application_memory.h" -#elif defined(NRF54H20_XXAA) +#elif defined(NRF54LM20A_XXAA) #if defined(NRF_APPLICATION) - #include "nrf54h20_xxaa_application_memory.h" + #include "nrf54lm20a_xxaa_application_memory.h" #endif - #if defined(NRF_RADIOCORE) - #include "nrf54h20_xxaa_radiocore_memory.h" + #if defined(NRF_FLPR) + #include "nrf54lm20a_xxaa_flpr_memory.h" #endif - #if defined(NRF_PPR) - #include "nrf54h20_xxaa_ppr_memory.h" +#elif defined(NRF54LM20B_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf54lm20b_xxaa_application_memory.h" #endif #if defined(NRF_FLPR) - #include "nrf54h20_xxaa_flpr_memory.h" + #include "nrf54lm20b_xxaa_flpr_memory.h" + #endif +#elif defined(NRF54LS05A_XXAA) + #include "nrf54ls05a_xxaa_application_memory.h" +#elif defined(NRF54LS05B_XXAA) + #include "nrf54ls05b_xxaa_application_memory.h" +#elif defined(NRF54LV10A_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf54lv10a_xxaa_application_memory.h" + #endif + #if defined(NRF_FLPR) + #include "nrf54lv10a_xxaa_flpr_memory.h" #endif #elif defined(NRF7120_ENGA_XXAA) #if defined(NRF_APPLICATION) @@ -141,6 +163,16 @@ POSSIBILITY OF SUCH DAMAGE. #include "nrf9120_xxaa_memory.h" #elif defined(NRF9160_XXAA) #include "nrf9160_xxaa_memory.h" +#elif defined(NRF9220_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf9220_xxaa_application_memory.h" + #endif + #if defined(NRF_PPR) + #include "nrf9220_xxaa_ppr_memory.h" + #endif + #if defined(NRF_FLPR) + #include "nrf9220_xxaa_flpr_memory.h" + #endif #elif defined(NRF9230_ENGB_XXAA) #if defined(NRF_APPLICATION) #include "nrf9230_engb_xxaa_application_memory.h" diff --git a/cores/nRF5/nordic/nrfx/mdk/nrf_peripherals.h b/cores/nRF5/nordic/nrfx/mdk/nrf_peripherals.h index 8478789..3cff758 100644 --- a/cores/nRF5/nordic/nrfx/mdk/nrf_peripherals.h +++ b/cores/nRF5/nordic/nrfx/mdk/nrf_peripherals.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -35,6 +35,10 @@ POSSIBILITY OF SUCH DAMAGE. #ifndef NRF_PERIPHERALS_H__ #define NRF_PERIPHERALS_H__ +#ifdef __ZEPHYR__ +#include +#endif + /*lint ++flb "Enter library region */ #if defined(NRF51) @@ -66,8 +70,8 @@ POSSIBILITY OF SUCH DAMAGE. #elif defined (NRF54L05_XXAA) #include "nrf54l05_peripherals.h" -#elif defined (NRF54LV10A_ENGA_XXAA) - #include "nrf54lv10a_enga_peripherals.h" +#elif defined (NRF54LV10A_XXAA) + #include "nrf54lv10a_peripherals.h" #elif defined (NRF54L10_XXAA) #include "nrf54l10_peripherals.h" @@ -75,11 +79,14 @@ POSSIBILITY OF SUCH DAMAGE. #elif defined (NRF54L15_XXAA) #include "nrf54l15_peripherals.h" -#elif defined (NRF54LM20A_ENGA_XXAA) - #include "nrf54lm20a_enga_peripherals.h" +#elif defined (NRF54LM20A_XXAA) + #include "nrf54lm20a_peripherals.h" + +#elif defined (NRF54LM20B_XXAA) + #include "nrf54lm20b_peripherals.h" -#elif defined (NRF54LS05B_ENGA_XXAA) - #include "nrf54ls05b_enga_peripherals.h" +#elif defined (NRF54LS05B_XXAA) + #include "nrf54ls05b_peripherals.h" #elif defined (NRF7120_ENGA_XXAA) #include "nrf7120_enga_peripherals.h" @@ -92,6 +99,15 @@ POSSIBILITY OF SUCH DAMAGE. #elif defined (NRF9230_ENGB_XXAA) #include "nrf9230_engb_peripherals.h" +#elif defined (NRF54LC10A_XXAA) + #include "nrf54lc10a_peripherals.h" + +#elif defined (NRF54LS05A_XXAA) + #include "nrf54ls05a_peripherals.h" + +#elif defined (NRF9220_XXAA) + #include "nrf9220_peripherals.h" + #else #error "Device must be defined. See nrf_peripherals.h." #endif diff --git a/cores/nRF5/nordic/nrfx/mdk/system_config_sau.h b/cores/nRF5/nordic/nrfx/mdk/system_config_sau.h index 52106d9..e6983cc 100644 --- a/cores/nRF5/nordic/nrfx/mdk/system_config_sau.h +++ b/cores/nRF5/nordic/nrfx/mdk/system_config_sau.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause diff --git a/cores/nRF5/nordic/nrfx/mdk/system_nrf.h b/cores/nRF5/nordic/nrfx/mdk/system_nrf.h index 849c5ad..c862f21 100644 --- a/cores/nRF5/nordic/nrfx/mdk/system_nrf.h +++ b/cores/nRF5/nordic/nrfx/mdk/system_nrf.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2025 ARM Limited. All rights reserved. +Copyright (c) 2009-2026 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/cores/nRF5/nordic/nrfx/mdk/system_nrf54l.c b/cores/nRF5/nordic/nrfx/mdk/system_nrf54l.c index a664511..312c74c 100644 --- a/cores/nRF5/nordic/nrfx/mdk/system_nrf54l.c +++ b/cores/nRF5/nordic/nrfx/mdk/system_nrf54l.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2025 ARM Limited. All rights reserved. +Copyright (c) 2009-2026 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -37,7 +37,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #define __SYSTEM_CLOCK_DEFAULT (64000000ul) /* Trace configuration */ -#if (defined(NRF54L05_XXAA) || defined(NRF54L10_XXAA) || defined(NRF54L15_XXAA) || defined(NRF54LM20A_ENGA_XXAA)) +#if (defined(NRF54L05_XXAA) || defined(NRF54L10_XXAA) || defined(NRF54L15_XXAA) || defined(NRF54LM20A_XXAA) || defined(NRF54LM20B_XXAA)) #define TRACE_PORT NRF_P2_S #define TRACE_TRACECLK_PIN (6ul) #define TRACE_TRACEDATA0_PIN (7ul) @@ -47,7 +47,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #define TRACE_PIN_CONFIG ((GPIO_PIN_CNF_DRIVE0_E0 << GPIO_PIN_CNF_DRIVE0_Pos) \ | (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_Pos) \ | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos)) -#elif defined(NRF54LV10A_ENGA_XXAA) +#elif defined(NRF54LV10A_XXAA) #define TRACE_PORT NRF_P1_S #define TRACE_TRACECLK_PIN (10ul) #define TRACE_TRACEDATA0_PIN (11ul) @@ -79,7 +79,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT; #elif defined ( __ICCARM__ ) __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; -#endif +#endif void SystemCoreClockUpdate(void) { @@ -110,7 +110,7 @@ void SystemInit(void) #endif #if !defined(NRF_TRUSTZONE_NONSECURE) && defined(__ARM_FEATURE_CMSE) - #if defined (NRF54LM20A_ENGA_XXAA) || defined (NRF54LV10A_ENGA_XXAA) + #if defined (NRF54LM20A_XXAA) || defined (NRF54LM20B_XXAA) || defined (NRF54LV10A_XXAA) /* Dummy-read KMU to starts its boot preparations. This operation should be at the beginning of SystemInit to allow KMU to run to completion during the function call */ NRF_KMU->STATUS; @@ -120,7 +120,7 @@ void SystemInit(void) /* Workaround for Errata 37 */ if (nrf54l_errata_37()) { - *((volatile uint32_t *)0x5005340C) = 1ul; + *((volatile uint32_t *)(((uint32_t)NRF_TAD) + 0x40C)) = 1ul; } #endif @@ -133,16 +133,16 @@ void SystemInit(void) SCB->NSACR |= (3UL << 10ul); #endif - #ifndef NRF_SKIP_SAU_CONFIGURATION + #ifndef NRF_SKIP_SAU_CONFIGURATION configure_default_sau(); - #endif + #endif #if !defined (NRF_DISABLE_FICR_TRIMCNF) /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim until one ADDR is not initialized. */ uint32_t index = 0ul; - #if defined (NRF54LS05B_ENGA_XXAA) + #if defined (NRF54LS05A_XXAA) || defined (NRF54LS05B_XXAA) for (index = 0ul; index < FICR_TRIMCNF_MaxCount && NRF_FICR->TRIMCNF[index].ADDR != 0xFFFFFFFFul && NRF_FICR->TRIMCNF[index].ADDR != 0x00000000ul; index++) { #if defined ( __ICCARM__ ) @@ -160,7 +160,7 @@ void SystemInit(void) #endif * ((volatile uint32_t*)NRF_FICR_NS->TRIMCNF[index].ADDR) = NRF_FICR_NS->TRIMCNF[index].DATA; - #endif //NRF54LS05B_ENGA_XXAA + #endif //NRF54LS05A_XXAA || NRF54LS05B_XXAA #if defined ( __ICCARM__ ) #pragma diag_default=Pa082 @@ -210,7 +210,8 @@ void SystemInit(void) #ifndef NRF_DISABLE_RRAM_POWER_OFF /* Allow RRAMC to go into poweroff mode during System on idle for lower power consumption at a penalty of 9us extra RRAM ready time */ - NRF_RRAMC->POWER.LOWPOWERCONFIG = (RRAMC_POWER_LOWPOWERCONFIG_MODE_PowerOff << RRAMC_POWER_LOWPOWERCONFIG_MODE_Pos); + NRF_RRAMC->POWER.LOWPOWERCONFIG &= ~RRAMC_POWER_LOWPOWERCONFIG_MODE_Msk; + NRF_RRAMC->POWER.LOWPOWERCONFIG |= (RRAMC_POWER_LOWPOWERCONFIG_MODE_PowerOff << RRAMC_POWER_LOWPOWERCONFIG_MODE_Pos); #endif #if defined (DEVELOP_IN_NRF54L15) && defined(NRF54L10_XXAA) @@ -230,7 +231,7 @@ void SystemInit(void) /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit * operations are not used in your code. */ - + /* Allow Non-Secure code to run FPU instructions. * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */ SCB->NSACR |= (3UL << 10ul); @@ -248,7 +249,7 @@ void SystemInit(void) #endif #if !defined(NRF_TRUSTZONE_NONSECURE) && defined(__ARM_FEATURE_CMSE) - #if !defined (NRF54LV10A_ENGA_XXAA) + #if !defined (NRF54LV10A_XXAA) #if defined(NRF_CONFIG_NFCT_PINS_AS_GPIOS) NRF_NFCT_S->PADCONFIG = (NFCT_PADCONFIG_ENABLE_Disabled << NFCT_PADCONFIG_ENABLE_Pos); #endif @@ -315,7 +316,7 @@ void SystemInit(void) #endif #if !defined(NRF_TRUSTZONE_NONSECURE) && defined(__ARM_FEATURE_CMSE) && !defined (NRF_SKIP_KMU_WAIT_FOR_READY) - #if defined (NRF54LM20A_ENGA_XXAA) || defined (NRF54LV10A_ENGA_XXAA) + #if defined (NRF54LM20A_XXAA) || defined (NRF54LM20B_XXAA) || defined (NRF54LC10A_XXAA) || defined (NRF54LV10A_XXAA) /* KMU is ready by now, but to be sure allow it to run to completion */ while(NRF_KMU->STATUS == KMU_STATUS_STATUS_Busy) { diff --git a/cores/nRF5/nordic/nrfx/mdk/system_nrf54l.h b/cores/nRF5/nordic/nrfx/mdk/system_nrf54l.h index 10adc79..82cefbd 100644 --- a/cores/nRF5/nordic/nrfx/mdk/system_nrf54l.h +++ b/cores/nRF5/nordic/nrfx/mdk/system_nrf54l.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2025 ARM Limited. All rights reserved. +Copyright (c) 2009-2026 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/cores/nRF5/nordic/nrfx/mdk/system_nrf54l_approtect.h b/cores/nRF5/nordic/nrfx/mdk/system_nrf54l_approtect.h index aa139c7..f50b53a 100644 --- a/cores/nRF5/nordic/nrfx/mdk/system_nrf54l_approtect.h +++ b/cores/nRF5/nordic/nrfx/mdk/system_nrf54l_approtect.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2026, Nordic Semiconductor ASA All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -152,7 +152,7 @@ static inline void nrf54l_handle_secureapprotect_signal(volatile uint32_t * sign ENABLE_SECURE_APPROTECT and ENABLE_SECURE_APPROTECT_USER_HANDLING. */ static inline void nrf54l_handle_approtect(void) { -#if defined (NRF54LS05B_ENGA_XXAA) +#if defined (NRF54LS05A_XXAA) || defined (NRF54LS05B_XXAA) nrf54l_handle_approtect_signal(&NRF_TAMPC->PROTECT.DOMAIN[0].DBGEN.CTRL); nrf54l_handle_approtect_signal(&NRF_TAMPC->PROTECT.DOMAIN[0].NIDEN.CTRL); #else diff --git a/cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_enga_application.h b/cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_application.h similarity index 98% rename from cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_enga_application.h rename to cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_application.h index 8aec57b..75baba7 100644 --- a/cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_enga_application.h +++ b/cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_application.h @@ -31,8 +31,8 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef NRFX_IRQS_NRF54LM20A_ENGA_APPLICATION_H__ -#define NRFX_IRQS_NRF54LM20A_ENGA_APPLICATION_H__ +#ifndef NRFX_IRQS_NRF54LM20A_APPLICATION_H__ +#define NRFX_IRQS_NRF54LM20A_APPLICATION_H__ #include "drivers/nrfx_utils.h" @@ -255,4 +255,4 @@ extern "C" { } #endif -#endif // NRFX_IRQS_NRF54LM20A_ENGA_APPLICATION_H___ +#endif // NRFX_IRQS_NRF54LM20A_APPLICATION_H___ diff --git a/cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_enga_flpr.h b/cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_flpr.h similarity index 98% rename from cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_enga_flpr.h rename to cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_flpr.h index e0d863b..f9c31c6 100644 --- a/cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_enga_flpr.h +++ b/cores/nRF5/nordic/nrfx/soc/irqs/nrfx_irqs_nrf54lm20a_flpr.h @@ -31,8 +31,8 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef NRFX_IRQS_NRF54LM20A_ENGA_FLPR_H__ -#define NRFX_IRQS_NRF54LM20A_ENGA_FLPR_H__ +#ifndef NRFX_IRQS_NRF54LM20A_FLPR_H__ +#define NRFX_IRQS_NRF54LM20A_FLPR_H__ #include "drivers/nrfx_utils.h" @@ -343,4 +343,4 @@ extern "C" { } #endif -#endif // NRFX_IRQS_NRF54LM20A_ENGA_FLPR_H___ +#endif // NRFX_IRQS_NRF54LM20A_FLPR_H___