profilingv2gpu.md

Streaming output truncated to the last 5000 lines.
    L2 Cache Throughput               %        14.28
    SM Active Cycles              cycle 2,477,795.25
    Compute (SM) Throughput           %        49.37
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                 32,768
    Registers Per Thread             register/thread              64
    Shared Memory Configuration Size           Kbyte           65.54
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block           11.54
    # SMs                                         SM              40
    Threads                                   thread       8,388,608
    Uses Green Context                                             0
    Waves Per SM                                              204.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block            5
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        97.26
    Achieved Active Warps Per SM           warp        31.12
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       58,716
    Total DRAM Elapsed Cycles        cycle  169,462,784
    Average L1 Active Cycles         cycle 2,477,795.25
    Total L1 Elapsed Cycles          cycle   99,289,824
    Average L2 Active Cycles         cycle 3,331,383.97
    Total L2 Elapsed Cycles          cycle  115,957,472
    Average SM Active Cycles         cycle 2,477,795.25
    Total SM Elapsed Cycles          cycle   99,289,824
    Average SMSP Active Cycles       cycle 2,477,684.92
    Total SMSP Elapsed Cycles        cycle  397,159,296
    -------------------------- ----------- ------------

  upsample2x_backward_sum4_nhwc_f4(const float *, float *, int, int, int, int, int) (8, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.87
    SM Frequency                    Mhz       575.13
    Elapsed Cycles                cycle        3,629
    Memory Throughput                 %         7.54
    DRAM Throughput                   %         7.54
    Duration                         us         6.30
    L1/TEX Cache Throughput           %        27.25
    L2 Cache Throughput               %         3.73
    SM Active Cycles              cycle       375.73
    Compute (SM) Throughput           %         1.23
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      8
    Registers Per Thread             register/thread              24
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           2,048
    Uses Green Context                                             0
    Waves Per SM                                                0.05
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 80%                                                                                             
          The grid for this launch is configured to execute only 8 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.83
    Achieved Active Warps Per SM           warp         7.95
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.17%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.8%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     2,316.50
    Total DRAM Elapsed Cycles        cycle      245,760
    Average L1 Active Cycles         cycle       375.73
    Total L1 Elapsed Cycles          cycle      144,384
    Average L2 Active Cycles         cycle       857.16
    Total L2 Elapsed Cycles          cycle      169,504
    Average SM Active Cycles         cycle       375.73
    Total SM Elapsed Cycles          cycle      144,384
    Average SMSP Active Cycles       cycle       372.04
    Total SMSP Elapsed Cycles        cycle      577,536
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.357%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 80.29% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.312%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 80.64% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.357%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 80.29% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.059%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 31.26% above the average, while the minimum instance value is 17.28% below the      
          average.                                                                                                      

  relu_backward_f4(const float *, float *, const float *, int) (8, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.82
    SM Frequency                    Mhz       580.23
    Elapsed Cycles                cycle        3,083
    Memory Throughput                 %         4.65
    DRAM Throughput                   %         4.65
    Duration                         us         5.31
    L1/TEX Cache Throughput           %        20.04
    L2 Cache Throughput               %         2.82
    SM Active Cycles              cycle       255.55
    Compute (SM) Throughput           %         0.54
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      8
    Registers Per Thread             register/thread              18
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           2,048
    Uses Green Context                                             0
    Waves Per SM                                                0.05
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 80%                                                                                             
          The grid for this launch is configured to execute only 8 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.46
    Achieved Active Warps Per SM           warp         7.83
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.54%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.5%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        1,190
    Total DRAM Elapsed Cycles        cycle      204,800
    Average L1 Active Cycles         cycle       255.55
    Total L1 Elapsed Cycles          cycle      123,816
    Average L2 Active Cycles         cycle       706.25
    Total L2 Elapsed Cycles          cycle      144,192
    Average SM Active Cycles         cycle       255.55
    Total SM Elapsed Cycles          cycle      123,816
    Average SMSP Active Cycles       cycle       248.82
    Total SMSP Elapsed Cycles        cycle      495,264
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 6.653%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 80.58% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.475%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 80.55% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.653%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 80.58% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.25%                                                                                           
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 33.50% above the average, while the minimum instance value is 18.30% below the      
          average.                                                                                                      

  conv2d_dinput_tiled_gmem_k3(const float *, float *, const float *, int, int, int, int) (1, 1, 128)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.02
    SM Frequency                    Mhz       584.96
    Elapsed Cycles                cycle      199,155
    Memory Throughput                 %        39.10
    DRAM Throughput                   %         1.21
    Duration                         us       340.45
    L1/TEX Cache Throughput           %        69.69
    L2 Cache Throughput               %         0.88
    SM Active Cycles              cycle   177,051.23
    Compute (SM) Throughput           %        39.10
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        78.12
    Achieved Active Warps Per SM           warp        25.00
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 21.88%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (78.1%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       20,632
    Total DRAM Elapsed Cycles        cycle   13,680,640
    Average L1 Active Cycles         cycle   177,051.23
    Total L1 Elapsed Cycles          cycle    7,975,616
    Average L2 Active Cycles         cycle    71,993.28
    Total L2 Elapsed Cycles          cycle    9,313,696
    Average SM Active Cycles         cycle   177,051.23
    Total SM Elapsed Cycles          cycle    7,975,616
    Average SMSP Active Cycles       cycle   177,625.20
    Total SMSP Elapsed Cycles        cycle   31,902,464
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.296%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 10.47% above the average, while the minimum instance value is 5.20% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.229%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 10.36% above the average, while the minimum instance value is 4.55% below the       
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.296%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 10.47% above the average, while the minimum instance value is 5.20% below the       
          average.                                                                                                      

  conv2d_dweight_dbias_tiled_k3(const float *, const float *, float *, float *, int, int, int, int) (1, 1, 16384)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       584.98
    Elapsed Cycles                cycle      835,053
    Memory Throughput                 %        68.52
    DRAM Throughput                   %         0.33
    Duration                         ms         1.43
    L1/TEX Cache Throughput           %        87.44
    L2 Cache Throughput               %         2.99
    SM Active Cycles              cycle   832,688.45
    Compute (SM) Throughput           %        68.52
    ----------------------- ----------- ------------

    INF   Compute and Memory are well-balanced: To reduce runtime, both computation and memory traffic must be reduced. 
          Check both the Compute Workload Analysis and Memory Workload Analysis sections.                               

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                 16,384
    Registers Per Thread             register/thread              64
    Shared Memory Configuration Size           Kbyte           65.54
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block           11.54
    # SMs                                         SM              40
    Threads                                   thread       4,194,304
    Uses Green Context                                             0
    Waves Per SM                                              102.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block            5
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        96.78
    Achieved Active Warps Per SM           warp        30.97
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    23,422.50
    Total DRAM Elapsed Cycles        cycle   57,065,472
    Average L1 Active Cycles         cycle   832,688.45
    Total L1 Elapsed Cycles          cycle   33,426,928
    Average L2 Active Cycles         cycle   476,887.16
    Total L2 Elapsed Cycles          cycle   39,054,432
    Average SM Active Cycles         cycle   832,688.45
    Total SM Elapsed Cycles          cycle   33,426,928
    Average SMSP Active Cycles       cycle   832,632.93
    Total SMSP Elapsed Cycles        cycle  133,707,712
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 10.45%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 26.74% above the average, while the minimum instance value is 2.91% below the       
          average.                                                                                                      

  maxpool2x2_backward_scatter_noatomic(const float *, float *, const int *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.76
    SM Frequency                    Mhz       575.44
    Elapsed Cycles                cycle        2,911
    Memory Throughput                 %        14.36
    DRAM Throughput                   %        14.36
    Duration                         us         5.06
    L1/TEX Cache Throughput           %        13.86
    L2 Cache Throughput               %         4.64
    SM Active Cycles              cycle       841.20
    Compute (SM) Throughput           %         1.80
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.91
    Achieved Active Warps Per SM           warp         7.97
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.09%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     3,454.50
    Total DRAM Elapsed Cycles        cycle      192,512
    Average L1 Active Cycles         cycle       841.20
    Total L1 Elapsed Cycles          cycle      113,944
    Average L2 Active Cycles         cycle     1,111.25
    Total L2 Elapsed Cycles          cycle      136,224
    Average SM Active Cycles         cycle       841.20
    Total SM Elapsed Cycles          cycle      113,944
    Average SMSP Active Cycles       cycle       811.53
    Total SMSP Elapsed Cycles        cycle      455,776
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 6.865%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 23.25% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.882%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 24.16% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.865%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 23.25% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.153%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 23.57% above the average, while the minimum instance value is 16.58% below the      
          average.                                                                                                      

  relu_backward_f4(const float *, float *, const float *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.73
    SM Frequency                    Mhz       578.51
    Elapsed Cycles                cycle        3,466
    Memory Throughput                 %        16.11
    DRAM Throughput                   %        16.11
    Duration                         us         5.98
    L1/TEX Cache Throughput           %        16.05
    L2 Cache Throughput               %         8.35
    SM Active Cycles              cycle     1,275.72
    Compute (SM) Throughput           %         2.02
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              18
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        23.68
    Achieved Active Warps Per SM           warp         7.58
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 76.32%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (23.7%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        4,557
    Total DRAM Elapsed Cycles        cycle      226,304
    Average L1 Active Cycles         cycle     1,275.72
    Total L1 Elapsed Cycles          cycle      133,024
    Average L2 Active Cycles         cycle     1,535.62
    Total L2 Elapsed Cycles          cycle      162,368
    Average SM Active Cycles         cycle     1,275.72
    Total SM Elapsed Cycles          cycle      133,024
    Average SMSP Active Cycles       cycle     1,152.72
    Total SMSP Elapsed Cycles        cycle      532,096
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.472%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 24.69% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.213%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 26.58% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.472%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 24.69% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.688%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 18.79% above the average, while the minimum instance value is 11.89% below the      
          average.                                                                                                      

  conv2d_dinput_tiled_gmem_k3(const float *, float *, const float *, int, int, int, int) (1, 1, 256)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       584.98
    Elapsed Cycles                cycle      980,706
    Memory Throughput                 %        42.58
    DRAM Throughput                   %         0.65
    Duration                         ms         1.68
    L1/TEX Cache Throughput           %        85.16
    L2 Cache Throughput               %         7.38
    SM Active Cycles              cycle   885,620.78
    Compute (SM) Throughput           %        30.14
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        86.16
    Achieved Active Warps Per SM           warp        27.57
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 13.84%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (86.2%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    54,447.50
    Total DRAM Elapsed Cycles        cycle   66,883,584
    Average L1 Active Cycles         cycle   885,620.78
    Total L1 Elapsed Cycles          cycle   39,182,048
    Average L2 Active Cycles         cycle 1,024,297.81
    Total L2 Elapsed Cycles          cycle   45,867,040
    Average SM Active Cycles         cycle   885,620.78
    Total SM Elapsed Cycles          cycle   39,182,048
    Average SMSP Active Cycles       cycle   886,909.69
    Total SMSP Elapsed Cycles        cycle  156,728,192
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.444%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 9.34% above the average, while the minimum instance value is 6.26% below the average.       
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.408%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 9.29% above the average, while the minimum instance value is 6.55% below the        
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.444%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 9.34% above the average, while the minimum instance value is 6.26% below the        
          average.                                                                                                      

  conv2d_dweight_dbias_tiled_k3(const float *, const float *, float *, float *, int, int, int, int) (1, 1, 32768)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       584.99
    Elapsed Cycles                cycle    2,475,419
    Memory Throughput                 %        49.48
    DRAM Throughput                   %         0.27
    Duration                         ms         4.23
    L1/TEX Cache Throughput           %        93.77
    L2 Cache Throughput               %        14.35
    SM Active Cycles              cycle 2,470,470.95
    Compute (SM) Throughput           %        49.48
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                 32,768
    Registers Per Thread             register/thread              64
    Shared Memory Configuration Size           Kbyte           65.54
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block           11.54
    # SMs                                         SM              40
    Threads                                   thread       8,388,608
    Uses Green Context                                             0
    Waves Per SM                                              204.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block            5
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        97.39
    Achieved Active Warps Per SM           warp        31.17
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       56,206
    Total DRAM Elapsed Cycles        cycle  169,222,144
    Average L1 Active Cycles         cycle 2,470,470.95
    Total L1 Elapsed Cycles          cycle   99,073,456
    Average L2 Active Cycles         cycle 3,403,349.47
    Total L2 Elapsed Cycles          cycle  115,772,544
    Average SM Active Cycles         cycle 2,470,470.95
    Total SM Elapsed Cycles          cycle   99,073,456
    Average SMSP Active Cycles       cycle 2,471,131.43
    Total SMSP Elapsed Cycles        cycle  396,293,824
    -------------------------- ----------- ------------

  maxpool2x2_backward_scatter_noatomic(const float *, float *, const int *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.62
    SM Frequency                    Mhz       580.12
    Elapsed Cycles                cycle        5,536
    Memory Throughput                 %        60.01
    DRAM Throughput                   %        60.01
    Duration                         us         9.54
    L1/TEX Cache Throughput           %        33.59
    L2 Cache Throughput               %        16.15
    SM Active Cycles              cycle     3,105.62
    Compute (SM) Throughput           %         7.98
    ----------------------- ----------- ------------

    OPT   Memory is more heavily utilized than Compute: Look at the Memory Workload Analysis section to identify the    
          DRAM bottleneck. Check memory replay (coalescing) metrics to make sure you're efficiently utilizing the       
          bytes transferred. Also consider whether it is possible to do more work per memory access (kernel fusion) or  
          whether there are values you can (re)compute.                                                                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 50%                                                                                             
          A wave of thread blocks is defined as the maximum number of blocks that can be executed in parallel on the    
          target GPU. The number of blocks in a wave depends on the number of multiprocessors and the theoretical       
          occupancy of the kernel. This kernel launch results in 1 full waves and a partial wave of 96 thread blocks.   
          Under the assumption of a uniform execution duration of all thread blocks, the partial wave may account for   
          up to 50.0% of the total kernel runtime with a lower occupancy of 23.6%. Try launching a grid with no         
          partial wave. The overall impact of this tail effect also lessens with the number of full waves executed for  
          a grid. See the Hardware Model                                                                                
          (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model) description for more      
          details on launch configurations.                                                                             

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        76.45
    Achieved Active Warps Per SM           warp        24.46
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 23.55%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (76.4%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    26,421.50
    Total DRAM Elapsed Cycles        cycle      352,256
    Average L1 Active Cycles         cycle     3,105.62
    Total L1 Elapsed Cycles          cycle      205,280
    Average L2 Active Cycles         cycle     4,705.75
    Total L2 Elapsed Cycles          cycle      258,976
    Average SM Active Cycles         cycle     3,105.62
    Total SM Elapsed Cycles          cycle      205,280
    Average SMSP Active Cycles       cycle     3,161.49
    Total SMSP Elapsed Cycles        cycle      821,120
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.207%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 8.60% above the average, while the minimum instance value is 27.33% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.67%                                                                                           
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 9.20% above the average, while the minimum instance value is 21.75% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.207%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 8.60% above the average, while the minimum instance value is 27.33% below the       
          average.                                                                                                      

  relu_backward_f4(const float *, float *, const float *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.57
    SM Frequency                    Mhz       581.34
    Elapsed Cycles                cycle        7,873
    Memory Throughput                 %        64.94
    DRAM Throughput                   %        64.94
    Duration                         us        13.54
    L1/TEX Cache Throughput           %        31.85
    L2 Cache Throughput               %        27.17
    SM Active Cycles              cycle     5,144.25
    Compute (SM) Throughput           %         6.87
    ----------------------- ----------- ------------

    OPT   Memory is more heavily utilized than Compute: Look at the Memory Workload Analysis section to identify the    
          DRAM bottleneck. Check memory replay (coalescing) metrics to make sure you're efficiently utilizing the       
          bytes transferred. Also consider whether it is possible to do more work per memory access (kernel fusion) or  
          whether there are values you can (re)compute.                                                                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              18
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 50%                                                                                             
          A wave of thread blocks is defined as the maximum number of blocks that can be executed in parallel on the    
          target GPU. The number of blocks in a wave depends on the number of multiprocessors and the theoretical       
          occupancy of the kernel. This kernel launch results in 1 full waves and a partial wave of 96 thread blocks.   
          Under the assumption of a uniform execution duration of all thread blocks, the partial wave may account for   
          up to 50.0% of the total kernel runtime with a lower occupancy of 22.0%. Try launching a grid with no         
          partial wave. The overall impact of this tail effect also lessens with the number of full waves executed for  
          a grid. See the Hardware Model                                                                                
          (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model) description for more      
          details on launch configurations.                                                                             

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        78.04
    Achieved Active Warps Per SM           warp        24.97
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 21.96%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (78.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    40,147.50
    Total DRAM Elapsed Cycles        cycle      494,592
    Average L1 Active Cycles         cycle     5,144.25
    Total L1 Elapsed Cycles          cycle      293,024
    Average L2 Active Cycles         cycle     7,201.81
    Total L2 Elapsed Cycles          cycle      368,288
    Average SM Active Cycles         cycle     5,144.25
    Total SM Elapsed Cycles          cycle      293,024
    Average SMSP Active Cycles       cycle     5,129.19
    Total SMSP Elapsed Cycles        cycle    1,172,096
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.426%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 7.73% above the average, while the minimum instance value is 13.09% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.332%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 7.62% above the average, while the minimum instance value is 13.57% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.426%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 7.73% above the average, while the minimum instance value is 13.09% below the       
          average.                                                                                                      

  conv2d_dinput_tiled_cmem_k3(const float *, float *, int, int, int, int) (2, 2, 3)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       584.94
    Elapsed Cycles                cycle      392,516
    Memory Throughput                 %         9.09
    DRAM Throughput                   %         1.00
    Duration                         us       671.04
    L1/TEX Cache Throughput           %        30.79
    L2 Cache Throughput               %         0.90
    SM Active Cycles              cycle   116,344.65
    Compute (SM) Throughput           %         4.21
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     12
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread           3,072
    Uses Green Context                                             0
    Waves Per SM                                                0.07
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 70%                                                                                             
          The grid for this launch is configured to execute only 12 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.93
    Achieved Active Warps Per SM           warp         7.98
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.07%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       33,688
    Total DRAM Elapsed Cycles        cycle   26,865,664
    Average L1 Active Cycles         cycle   116,344.65
    Total L1 Elapsed Cycles          cycle   15,772,160
    Average L2 Active Cycles         cycle   125,513.75
    Total L2 Elapsed Cycles          cycle   18,357,952
    Average SM Active Cycles         cycle   116,344.65
    Total SM Elapsed Cycles          cycle   15,772,160
    Average SMSP Active Cycles       cycle   116,262.72
    Total SMSP Elapsed Cycles        cycle   63,088,640
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 20.72%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 70.22% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.73%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 70.29% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.72%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 70.22% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  conv2d_dweight_dbias_tiled_k3(const float *, const float *, float *, float *, int, int, int, int) (2, 2, 768)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       584.95
    Elapsed Cycles                cycle      209,822
    Memory Throughput                 %        54.74
    DRAM Throughput                   %         1.90
    Duration                         us       358.69
    L1/TEX Cache Throughput           %        87.23
    L2 Cache Throughput               %        10.41
    SM Active Cycles              cycle   205,273.02
    Compute (SM) Throughput           %        54.74
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  3,072
    Registers Per Thread             register/thread              64
    Shared Memory Configuration Size           Kbyte           65.54
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block           11.54
    # SMs                                         SM              40
    Threads                                   thread         786,432
    Uses Green Context                                             0
    Waves Per SM                                               19.20
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block            5
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        96.38
    Achieved Active Warps Per SM           warp        30.84
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    34,013.50
    Total DRAM Elapsed Cycles        cycle   14,310,400
    Average L1 Active Cycles         cycle   205,273.02
    Total L1 Elapsed Cycles          cycle    8,396,032
    Average L2 Active Cycles         cycle   189,026.59
    Total L2 Elapsed Cycles          cycle    9,811,840
    Average SM Active Cycles         cycle   205,273.02
    Total SM Elapsed Cycles          cycle    8,396,032
    Average SMSP Active Cycles       cycle   205,802.33
    Total SMSP Elapsed Cycles        cycle   33,584,128
    -------------------------- ----------- ------------

  conv2d_fwd_tiled_cmem_k3(const float *, float *, const float *, int, int, int, int) (2, 2, 256)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.91
    SM Frequency                    Mhz       584.92
    Elapsed Cycles                cycle       60,423
    Memory Throughput                 %        40.77
    DRAM Throughput                   %        11.00
    Duration                         us       103.30
    L1/TEX Cache Throughput           %        81.60
    L2 Cache Throughput               %        19.08
    SM Active Cycles              cycle    56,511.97
    Compute (SM) Throughput           %        31.07
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        90.49
    Achieved Active Warps Per SM           warp        28.96
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       55,760
    Total DRAM Elapsed Cycles        cycle    4,054,016
    Average L1 Active Cycles         cycle    56,511.97
    Total L1 Elapsed Cycles          cycle    2,390,936
    Average L2 Active Cycles         cycle    71,050.69
    Total L2 Elapsed Cycles          cycle    2,824,480
    Average SM Active Cycles         cycle    56,511.97
    Total SM Elapsed Cycles          cycle    2,390,936
    Average SMSP Active Cycles       cycle    56,370.76
    Total SMSP Elapsed Cycles        cycle    9,563,744
    -------------------------- ----------- ------------

  relu_forward_f4(const float *, float *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.57
    SM Frequency                    Mhz       578.08
    Elapsed Cycles                cycle        5,444
    Memory Throughput                 %        49.93
    DRAM Throughput                   %        49.93
    Duration                         us         9.41
    L1/TEX Cache Throughput           %        36.67
    L2 Cache Throughput               %        26.34
    SM Active Cycles              cycle     3,091.15
    Compute (SM) Throughput           %         8.40
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 50%                                                                                             
          A wave of thread blocks is defined as the maximum number of blocks that can be executed in parallel on the    
          target GPU. The number of blocks in a wave depends on the number of multiprocessors and the theoretical       
          occupancy of the kernel. This kernel launch results in 1 full waves and a partial wave of 96 thread blocks.   
          Under the assumption of a uniform execution duration of all thread blocks, the partial wave may account for   
          up to 50.0% of the total kernel runtime with a lower occupancy of 25.0%. Try launching a grid with no         
          partial wave. The overall impact of this tail effect also lessens with the number of full waves executed for  
          a grid. See the Hardware Model                                                                                
          (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model) description for more      
          details on launch configurations.                                                                             

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        75.03
    Achieved Active Warps Per SM           warp        24.01
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 24.97%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (75.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    21,475.50
    Total DRAM Elapsed Cycles        cycle      344,064
    Average L1 Active Cycles         cycle     3,091.15
    Total L1 Elapsed Cycles          cycle      202,848
    Average L2 Active Cycles         cycle     4,169.62
    Total L2 Elapsed Cycles          cycle      255,424
    Average SM Active Cycles         cycle     3,091.15
    Total SM Elapsed Cycles          cycle      202,848
    Average SMSP Active Cycles       cycle     2,955.59
    Total SMSP Elapsed Cycles        cycle      811,392
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 7.408%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 12.71% above the average, while the minimum instance value is 16.19% below the average.     

  maxpool2x2_forward_nhwc_f4(const float *, float *, int *, int, int, int, int, int) (64, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.81
    SM Frequency                    Mhz       578.69
    Elapsed Cycles                cycle        5,875
    Memory Throughput                 %        39.55
    DRAM Throughput                   %        39.55
    Duration                         us        10.14
    L1/TEX Cache Throughput           %        23.25
    L2 Cache Throughput               %        18.67
    SM Active Cycles              cycle     3,523.32
    Compute (SM) Throughput           %        12.00
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.4 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     64
    Registers Per Thread             register/thread              30
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          16,384
    Uses Green Context                                             0
    Waves Per SM                                                0.40
    -------------------------------- --------------- ---------------

    OPT   If you execute __syncthreads() to synchronize the threads of a block, it is recommended to have more than the 
          achieved 1 blocks per multiprocessor. This way, blocks that aren't waiting for __syncthreads() can keep the   
          hardware busy.                                                                                                

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            8
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        37.06
    Achieved Active Warps Per SM           warp        11.86
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 62.94%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (37.1%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       19,289
    Total DRAM Elapsed Cycles        cycle      390,144
    Average L1 Active Cycles         cycle     3,523.32
    Total L1 Elapsed Cycles          cycle      230,456
    Average L2 Active Cycles         cycle     4,312.94
    Total L2 Elapsed Cycles          cycle      275,200
    Average SM Active Cycles         cycle     3,523.32
    Total SM Elapsed Cycles          cycle      230,456
    Average SMSP Active Cycles       cycle     3,419.50
    Total SMSP Elapsed Cycles        cycle      921,824
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.563%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 14.00% above the average, while the minimum instance value is 22.86% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.12%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 17.04% above the average, while the minimum instance value is 37.56% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.563%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 14.00% above the average, while the minimum instance value is 22.86% below the      
          average.                                                                                                      

  conv2d_fwd_tiled_gmem_k3(const float *, float *, const float *, const float *, int, int, int, int) (1, 1, 128)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.01
    SM Frequency                    Mhz       584.98
    Elapsed Cycles                cycle    1,078,717
    Memory Throughput                 %        38.36
    DRAM Throughput                   %         0.55
    Duration                         ms         1.84
    L1/TEX Cache Throughput           %        76.72
    L2 Cache Throughput               %         7.36
    SM Active Cycles              cycle   920,696.15
    Compute (SM) Throughput           %        27.17
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        72.09
    Achieved Active Warps Per SM           warp        23.07
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 27.91%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (72.1%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       51,303
    Total DRAM Elapsed Cycles        cycle   73,958,400
    Average L1 Active Cycles         cycle   920,696.15
    Total L1 Elapsed Cycles          cycle   43,440,712
    Average L2 Active Cycles         cycle 1,226,562.59
    Total L2 Elapsed Cycles          cycle   50,450,880
    Average SM Active Cycles         cycle   920,696.15
    Total SM Elapsed Cycles          cycle   43,440,712
    Average SMSP Active Cycles       cycle   920,262.06
    Total SMSP Elapsed Cycles        cycle  173,762,848
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 12.59%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 14.85% above the average, while the minimum instance value is 5.43% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.6%                                                                                           
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 14.87% above the average, while the minimum instance value is 5.62% below the       
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.59%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 14.85% above the average, while the minimum instance value is 5.43% below the       
          average.                                                                                                      

  relu_forward_f4(const float *, float *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.98
    SM Frequency                    Mhz       576.45
    Elapsed Cycles                cycle        3,028
    Memory Throughput                 %         8.79
    DRAM Throughput                   %         8.79
    Duration                         us         5.25
    L1/TEX Cache Throughput           %        12.05
    L2 Cache Throughput               %         6.72
    SM Active Cycles              cycle       989.10
    Compute (SM) Throughput           %         1.90
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        23.68
    Achieved Active Warps Per SM           warp         7.58
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 76.32%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (23.7%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        2,294
    Total DRAM Elapsed Cycles        cycle      208,896
    Average L1 Active Cycles         cycle       989.10
    Total L1 Elapsed Cycles          cycle      121,440
    Average L2 Active Cycles         cycle     1,150.25
    Total L2 Elapsed Cycles          cycle      141,792
    Average SM Active Cycles         cycle       989.10
    Total SM Elapsed Cycles          cycle      121,440
    Average SMSP Active Cycles       cycle       992.57
    Total SMSP Elapsed Cycles        cycle      485,760
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 7.867%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 24.15% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.196%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 28.13% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 7.867%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 24.15% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.013%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Additionally, other L2 Slices have a much lower number of active cycles than the average number of active     
          cycles. Maximum instance value is 23.16% above the average, while the minimum instance value is 24.36% below  
          the average.                                                                                                  

  maxpool2x2_forward_nhwc_f4(const float *, float *, int *, int, int, int, int, int) (8, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.77
    SM Frequency                    Mhz       580.26
    Elapsed Cycles                cycle        4,125
    Memory Throughput                 %         7.41
    DRAM Throughput                   %         7.41
    Duration                         us         7.10
    L1/TEX Cache Throughput           %        22.53
    L2 Cache Throughput               %         4.04
    SM Active Cycles              cycle       454.45
    Compute (SM) Throughput           %         2.16
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      8
    Registers Per Thread             register/thread              30
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           2,048
    Uses Green Context                                             0
    Waves Per SM                                                0.05
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 80%                                                                                             
          The grid for this launch is configured to execute only 8 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            8
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.91
    Achieved Active Warps Per SM           warp         7.97
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.09%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     2,513.50
    Total DRAM Elapsed Cycles        cycle      271,360
    Average L1 Active Cycles         cycle       454.45
    Total L1 Elapsed Cycles          cycle      160,088
    Average L2 Active Cycles         cycle     1,111.91
    Total L2 Elapsed Cycles          cycle      192,896
    Average SM Active Cycles         cycle       454.45
    Total SM Elapsed Cycles          cycle      160,088
    Average SMSP Active Cycles       cycle       448.77
    Total SMSP Elapsed Cycles        cycle      640,352
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.137%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 80.47% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.017%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 80.41% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.137%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 80.47% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  conv2d_fwd_tiled_gmem_k3(const float *, float *, const float *, const float *, int, int, int, int) (1, 1, 128)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       584.94
    Elapsed Cycles                cycle      199,880
    Memory Throughput                 %        39.00
    DRAM Throughput                   %         1.22
    Duration                         us       341.70
    L1/TEX Cache Throughput           %        69.51
    L2 Cache Throughput               %         0.75
    SM Active Cycles              cycle   175,980.02
    Compute (SM) Throughput           %        39.00
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        78.04
    Achieved Active Warps Per SM           warp        24.97
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 21.96%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (78.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    20,875.50
    Total DRAM Elapsed Cycles        cycle   13,660,160
    Average L1 Active Cycles         cycle   175,980.02
    Total L1 Elapsed Cycles          cycle    7,997,672
    Average L2 Active Cycles         cycle    77,589.47
    Total L2 Elapsed Cycles          cycle    9,347,488
    Average SM Active Cycles         cycle   175,980.02
    Total SM Elapsed Cycles          cycle    7,997,672
    Average SMSP Active Cycles       cycle   176,130.77
    Total SMSP Elapsed Cycles        cycle   31,990,688
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 10.44%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 11.86% above the average, while the minimum instance value is 5.75% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.37%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 11.78% above the average, while the minimum instance value is 6.22% below the       
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.44%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 11.86% above the average, while the minimum instance value is 5.75% below the       
          average.                                                                                                      

  relu_forward_f4(const float *, float *, int) (8, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.82
    SM Frequency                    Mhz       572.88
    Elapsed Cycles                cycle        2,860
    Memory Throughput                 %         2.59
    DRAM Throughput                   %         2.59
    Duration                         us         4.99
    L1/TEX Cache Throughput           %        14.80
    L2 Cache Throughput               %         2.19
    SM Active Cycles              cycle       221.57
    Compute (SM) Throughput           %         0.51
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      8
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           2,048
    Uses Green Context                                             0
    Waves Per SM                                                0.05
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 80%                                                                                             
          The grid for this launch is configured to execute only 8 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.71
    Achieved Active Warps Per SM           warp         7.91
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.29%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.7%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle          624
    Total DRAM Elapsed Cycles        cycle      192,512
    Average L1 Active Cycles         cycle       221.57
    Total L1 Elapsed Cycles          cycle      112,816
    Average L2 Active Cycles         cycle       518.75
    Total L2 Elapsed Cycles          cycle      133,664
    Average SM Active Cycles         cycle       221.57
    Total SM Elapsed Cycles          cycle      112,816
    Average SMSP Active Cycles       cycle       218.87
    Total SMSP Elapsed Cycles        cycle      451,264
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 6.31%                                                                                           
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 80.32% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.246%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 80.49% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.31%                                                                                           
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 80.32% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.261%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 42.36% above the average, while the minimum instance value is 22.12% below the      
          average.                                                                                                      

  upsample2x_forward_nhwc_f4(const float *, float *, int, int, int, int, int) (8, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.91
    SM Frequency                    Mhz       580.92
    Elapsed Cycles                cycle        3,497
    Memory Throughput                 %         4.05
    DRAM Throughput                   %         2.16
    Duration                         us         6.02
    L1/TEX Cache Throughput           %        32.89
    L2 Cache Throughput               %         4.05
    SM Active Cycles              cycle       336.25
    Compute (SM) Throughput           %         1.12
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      8
    Registers Per Thread             register/thread              18
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           2,048
    Uses Green Context                                             0
    Waves Per SM                                                0.05
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 80%                                                                                             
          The grid for this launch is configured to execute only 8 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        23.18
    Achieved Active Warps Per SM           warp         7.42
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 76.82%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (23.2%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       639.50
    Total DRAM Elapsed Cycles        cycle      236,544
    Average L1 Active Cycles         cycle       336.25
    Total L1 Elapsed Cycles          cycle      138,112
    Average L2 Active Cycles         cycle       968.06
    Total L2 Elapsed Cycles          cycle      163,104
    Average SM Active Cycles         cycle       336.25
    Total SM Elapsed Cycles          cycle      138,112
    Average SMSP Active Cycles       cycle       320.40
    Total SMSP Elapsed Cycles        cycle      552,448
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 7.854%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 80.65% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 7.543%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 81.29% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 7.854%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 80.65% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.231%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 27.54% above the average, while the minimum instance value is 23.66% below the      
          average.                                                                                                      

  conv2d_fwd_tiled_gmem_k3(const float *, float *, const float *, const float *, int, int, int, int) (1, 1, 256)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.98
    SM Frequency                    Mhz       584.97
    Elapsed Cycles                cycle      980,866
    Memory Throughput                 %        42.56
    DRAM Throughput                   %         0.65
    Duration                         ms         1.68
    L1/TEX Cache Throughput           %        85.12
    L2 Cache Throughput               %         7.59
    SM Active Cycles              cycle   890,083.75
    Compute (SM) Throughput           %        30.13
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        85.81
    Achieved Active Warps Per SM           warp        27.46
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 14.19%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (85.8%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       54,677
    Total DRAM Elapsed Cycles        cycle   66,805,760
    Average L1 Active Cycles         cycle   890,083.75
    Total L1 Elapsed Cycles          cycle   39,211,400
    Average L2 Active Cycles         cycle 1,044,028.50
    Total L2 Elapsed Cycles          cycle   45,874,432
    Average SM Active Cycles         cycle   890,083.75
    Total SM Elapsed Cycles          cycle   39,211,400
    Average SMSP Active Cycles       cycle   888,159.42
    Total SMSP Elapsed Cycles        cycle  156,845,600
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.233%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 9.07% above the average, while the minimum instance value is 6.29% below the average.       
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.185%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 9.03% above the average, while the minimum instance value is 5.95% below the        
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.233%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 9.07% above the average, while the minimum instance value is 6.29% below the        
          average.                                                                                                      

  relu_forward_f4(const float *, float *, int) (64, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.04
    SM Frequency                    Mhz       574.90
    Elapsed Cycles                cycle        3,404
    Memory Throughput                 %        15.30
    DRAM Throughput                   %        15.30
    Duration                         us         5.92
    L1/TEX Cache Throughput           %        16.08
    L2 Cache Throughput               %        11.23
    SM Active Cycles              cycle     1,457.67
    Compute (SM) Throughput           %         3.34
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.4 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     64
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          16,384
    Uses Green Context                                             0
    Waves Per SM                                                0.40
    -------------------------------- --------------- ---------------

    OPT   If you execute __syncthreads() to synchronize the threads of a block, it is recommended to have more than the 
          achieved 1 blocks per multiprocessor. This way, blocks that aren't waiting for __syncthreads() can keep the   
          hardware busy.                                                                                                

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        37.99
    Achieved Active Warps Per SM           warp        12.16
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 62.01%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (38.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        4,563
    Total DRAM Elapsed Cycles        cycle      238,592
    Average L1 Active Cycles         cycle     1,457.67
    Total L1 Elapsed Cycles          cycle      137,216
    Average L2 Active Cycles         cycle     1,697.31
    Total L2 Elapsed Cycles          cycle      159,296
    Average SM Active Cycles         cycle     1,457.67
    Total SM Elapsed Cycles          cycle      137,216
    Average SMSP Active Cycles       cycle     1,404.94
    Total SMSP Elapsed Cycles        cycle      548,864
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.461%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 16.02% above the average, while the minimum instance value is 8.15% below the       
          average.                                                                                                      

  upsample2x_forward_nhwc_f4(const float *, float *, int, int, int, int, int) (64, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.95
    SM Frequency                    Mhz       579.43
    Elapsed Cycles                cycle        5,086
    Memory Throughput                 %        18.32
    DRAM Throughput                   %        18.32
    Duration                         us         8.77
    L1/TEX Cache Throughput           %        34.21
    L2 Cache Throughput               %        17.99
    SM Active Cycles              cycle     2,481.50
    Compute (SM) Throughput           %         6.17
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.4 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     64
    Registers Per Thread             register/thread              18
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          16,384
    Uses Green Context                                             0
    Waves Per SM                                                0.40
    -------------------------------- --------------- ---------------

    OPT   If you execute __syncthreads() to synchronize the threads of a block, it is recommended to have more than the 
          achieved 1 blocks per multiprocessor. This way, blocks that aren't waiting for __syncthreads() can keep the   
          hardware busy.                                                                                                

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        34.01
    Achieved Active Warps Per SM           warp        10.88
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 65.99%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (34.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        7,950
    Total DRAM Elapsed Cycles        cycle      347,136
    Average L1 Active Cycles         cycle     2,481.50
    Total L1 Elapsed Cycles          cycle      200,336
    Average L2 Active Cycles         cycle     3,490.06
    Total L2 Elapsed Cycles          cycle      238,080
    Average SM Active Cycles         cycle     2,481.50
    Total SM Elapsed Cycles          cycle      200,336
    Average SMSP Active Cycles       cycle     2,361.41
    Total SMSP Elapsed Cycles        cycle      801,344
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 12.59%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 25.41% above the average, while the minimum instance value is 33.10% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.75%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 27.05% above the average, while the minimum instance value is 39.99% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.59%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 25.41% above the average, while the minimum instance value is 33.10% below the      
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.188%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 11.06% above the average, while the minimum instance value is 7.08% below the       
          average.                                                                                                      

  conv2d_fwd_tiled_cmem_k3(const float *, float *, const float *, int, int, int, int) (2, 2, 3)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       584.93
    Elapsed Cycles                cycle      387,383
    Memory Throughput                 %         9.29
    DRAM Throughput                   %         1.03
    Duration                         us       662.27
    L1/TEX Cache Throughput           %        31.65
    L2 Cache Throughput               %         0.94
    SM Active Cycles              cycle   113,229.05
    Compute (SM) Throughput           %         4.30
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     12
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread           3,072
    Uses Green Context                                             0
    Waves Per SM                                                0.07
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 70%                                                                                             
          The grid for this launch is configured to execute only 12 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        25.00
    Achieved Active Warps Per SM           warp         8.00
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75%                                                                                       
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (25.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       33,999
    Total DRAM Elapsed Cycles        cycle   26,418,176
    Average L1 Active Cycles         cycle   113,229.05
    Total L1 Elapsed Cycles          cycle   15,437,656
    Average L2 Active Cycles         cycle   134,522.88
    Total L2 Elapsed Cycles          cycle   18,117,728
    Average SM Active Cycles         cycle   113,229.05
    Total SM Elapsed Cycles          cycle   15,437,656
    Average SMSP Active Cycles       cycle   113,458.14
    Total SMSP Elapsed Cycles        cycle   61,750,624
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 20.69%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 70.54% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.71%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 70.45% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.69%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 70.54% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  mse_loss_reduce_f4(const float *, const float *, float *, int) (3, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.83
    SM Frequency                    Mhz       580.08
    Elapsed Cycles                cycle        3,676
    Memory Throughput                 %         1.82
    DRAM Throughput                   %         1.82
    Duration                         us         6.34
    L1/TEX Cache Throughput           %        13.59
    L2 Cache Throughput               %         1.25
    SM Active Cycles              cycle       141.25
    Compute (SM) Throughput           %         0.45
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.0 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      3
    Registers Per Thread             register/thread              54
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block             128
    # SMs                                         SM              40
    Threads                                   thread             768
    Uses Green Context                                             0
    Waves Per SM                                                0.02
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 92.5%                                                                                           
          The grid for this launch is configured to execute only 3 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block          128
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        23.43
    Achieved Active Warps Per SM           warp         7.50
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 76.57%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (23.4%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle          558
    Total DRAM Elapsed Cycles        cycle      244,736
    Average L1 Active Cycles         cycle       141.25
    Total L1 Elapsed Cycles          cycle      142,744
    Average L2 Active Cycles         cycle       419.38
    Total L2 Elapsed Cycles          cycle      171,680
    Average SM Active Cycles         cycle       141.25
    Total SM Elapsed Cycles          cycle      142,744
    Average SMSP Active Cycles       cycle       134.24
    Total SMSP Elapsed Cycles        cycle      570,976
    -------------------------- ----------- ------------

  mse_loss_backward_f4(const float *, const float *, float *, int) (3, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.90
    SM Frequency                    Mhz       580.75
    Elapsed Cycles                cycle        3,234
    Memory Throughput                 %         1.99
    DRAM Throughput                   %         1.99
    Duration                         us         5.57
    L1/TEX Cache Throughput           %        17.05
    L2 Cache Throughput               %         1.61
    SM Active Cycles              cycle       112.62
    Compute (SM) Throughput           %         0.37
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.0 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      3
    Registers Per Thread             register/thread              44
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread             768
    Uses Green Context                                             0
    Waves Per SM                                                0.02
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 92.5%                                                                                           
          The grid for this launch is configured to execute only 3 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            5
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.48
    Achieved Active Warps Per SM           warp         7.83
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.52%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.5%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle          543
    Total DRAM Elapsed Cycles        cycle      218,112
    Average L1 Active Cycles         cycle       112.62
    Total L1 Elapsed Cycles          cycle      127,960
    Average L2 Active Cycles         cycle       460.03
    Total L2 Elapsed Cycles          cycle      151,104
    Average SM Active Cycles         cycle       112.62
    Total SM Elapsed Cycles          cycle      127,960
    Average SMSP Active Cycles       cycle       109.48
    Total SMSP Elapsed Cycles        cycle      511,840
    -------------------------- ----------- ------------

  conv2d_dinput_tiled_cmem_k3(const float *, float *, int, int, int, int) (2, 2, 256)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.92
    SM Frequency                    Mhz       585.07
    Elapsed Cycles                cycle       59,838
    Memory Throughput                 %        40.68
    DRAM Throughput                   %        11.01
    Duration                         us       102.27
    L1/TEX Cache Throughput           %        81.34
    L2 Cache Throughput               %        19.14
    SM Active Cycles              cycle    56,216.05
    Compute (SM) Throughput           %        31.03
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        90.26
    Achieved Active Warps Per SM           warp        28.88
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       55,419
    Total DRAM Elapsed Cycles        cycle    4,026,368
    Average L1 Active Cycles         cycle    56,216.05
    Total L1 Elapsed Cycles          cycle    2,373,584
    Average L2 Active Cycles         cycle    70,072.53
    Total L2 Elapsed Cycles          cycle    2,797,184
    Average SM Active Cycles         cycle    56,216.05
    Total SM Elapsed Cycles          cycle    2,373,584
    Average SMSP Active Cycles       cycle    55,989.15
    Total SMSP Elapsed Cycles        cycle    9,494,336
    -------------------------- ----------- ------------

  conv2d_dweight_dbias_tiled_k3(const float *, const float *, float *, float *, int, int, int, int) (2, 2, 768)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       584.93
    Elapsed Cycles                cycle      211,387
    Memory Throughput                 %        54.34
    DRAM Throughput                   %         1.87
    Duration                         us       361.38
    L1/TEX Cache Throughput           %        87.73
    L2 Cache Throughput               %        12.02
    SM Active Cycles              cycle   207,382.85
    Compute (SM) Throughput           %        54.34
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  3,072
    Registers Per Thread             register/thread              64
    Shared Memory Configuration Size           Kbyte           65.54
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block           11.54
    # SMs                                         SM              40
    Threads                                   thread         786,432
    Uses Green Context                                             0
    Waves Per SM                                               19.20
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block            5
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        96.23
    Achieved Active Warps Per SM           warp        30.79
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    33,867.50
    Total DRAM Elapsed Cycles        cycle   14,462,976
    Average L1 Active Cycles         cycle   207,382.85
    Total L1 Elapsed Cycles          cycle    8,458,088
    Average L2 Active Cycles         cycle   200,629.12
    Total L2 Elapsed Cycles          cycle    9,885,440
    Average SM Active Cycles         cycle   207,382.85
    Total SM Elapsed Cycles          cycle    8,458,088
    Average SMSP Active Cycles       cycle   207,195.67
    Total SMSP Elapsed Cycles        cycle   33,832,352
    -------------------------- ----------- ------------

  upsample2x_backward_sum4_nhwc_f4(const float *, float *, int, int, int, int, int) (64, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.95
    SM Frequency                    Mhz       578.69
    Elapsed Cycles                cycle        5,392
    Memory Throughput                 %        39.76
    DRAM Throughput                   %        39.76
    Duration                         us         9.31
    L1/TEX Cache Throughput           %        25.48
    L2 Cache Throughput               %        16.85
    SM Active Cycles              cycle     3,214.78
    Compute (SM) Throughput           %         6.50
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.4 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     64
    Registers Per Thread             register/thread              24
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          16,384
    Uses Green Context                                             0
    Waves Per SM                                                0.40
    -------------------------------- --------------- ---------------

    OPT   If you execute __syncthreads() to synchronize the threads of a block, it is recommended to have more than the 
          achieved 1 blocks per multiprocessor. This way, blocks that aren't waiting for __syncthreads() can keep the   
          hardware busy.                                                                                                

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        36.21
    Achieved Active Warps Per SM           warp        11.59
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 63.79%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (36.2%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       18,323
    Total DRAM Elapsed Cycles        cycle      368,640
    Average L1 Active Cycles         cycle     3,214.78
    Total L1 Elapsed Cycles          cycle      215,368
    Average L2 Active Cycles         cycle     3,805.59
    Total L2 Elapsed Cycles          cycle      252,512
    Average SM Active Cycles         cycle     3,214.78
    Total SM Elapsed Cycles          cycle      215,368
    Average SMSP Active Cycles       cycle     3,126.51
    Total SMSP Elapsed Cycles        cycle      861,472
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.412%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 14.09% above the average, while the minimum instance value is 29.70% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.027%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 15.55% above the average, while the minimum instance value is 28.90% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.412%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 14.09% above the average, while the minimum instance value is 29.70% below the      
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.265%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 10.92% above the average, while the minimum instance value is 5.30% below the       
          average.                                                                                                      

  relu_backward_f4(const float *, float *, const float *, int) (64, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.75
    SM Frequency                    Mhz       575.84
    Elapsed Cycles                cycle        4,113
    Memory Throughput                 %        27.24
    DRAM Throughput                   %        27.24
    Duration                         us         7.14
    L1/TEX Cache Throughput           %        20.85
    L2 Cache Throughput               %        13.66
    SM Active Cycles              cycle     1,964.62
    Compute (SM) Throughput           %         3.38
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.4 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     64
    Registers Per Thread             register/thread              18
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          16,384
    Uses Green Context                                             0
    Waves Per SM                                                0.40
    -------------------------------- --------------- ---------------

    OPT   If you execute __syncthreads() to synchronize the threads of a block, it is recommended to have more than the 
          achieved 1 blocks per multiprocessor. This way, blocks that aren't waiting for __syncthreads() can keep the   
          hardware busy.                                                                                                

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        38.47
    Achieved Active Warps Per SM           warp        12.31
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 61.53%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (38.5%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        9,240
    Total DRAM Elapsed Cycles        cycle      271,360
    Average L1 Active Cycles         cycle     1,964.62
    Total L1 Elapsed Cycles          cycle      158,440
    Average L2 Active Cycles         cycle     2,389.53
    Total L2 Elapsed Cycles          cycle      192,448
    Average SM Active Cycles         cycle     1,964.62
    Total SM Elapsed Cycles          cycle      158,440
    Average SMSP Active Cycles       cycle     1,906.67
    Total SMSP Elapsed Cycles        cycle      633,760
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.745%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 11.58% above the average, while the minimum instance value is 23.80% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.905%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 14.35% above the average, while the minimum instance value is 35.65% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.745%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 11.58% above the average, while the minimum instance value is 23.80% below the      
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.482%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 13.80% above the average, while the minimum instance value is 9.90% below the       
          average.                                                                                                      

  conv2d_dinput_tiled_gmem_k3(const float *, float *, const float *, int, int, int, int) (1, 1, 128)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.01
    SM Frequency                    Mhz       584.98
    Elapsed Cycles                cycle    1,063,279
    Memory Throughput                 %        39.04
    DRAM Throughput                   %         0.56
    Duration                         ms         1.82
    L1/TEX Cache Throughput           %        78.08
    L2 Cache Throughput               %         5.90
    SM Active Cycles              cycle   908,675.45
    Compute (SM) Throughput           %        27.69
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        72.32
    Achieved Active Warps Per SM           warp        23.14
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 27.68%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (72.3%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       50,871
    Total DRAM Elapsed Cycles        cycle   72,884,224
    Average L1 Active Cycles         cycle   908,675.45
    Total L1 Elapsed Cycles          cycle   42,628,520
    Average L2 Active Cycles         cycle 1,114,863.25
    Total L2 Elapsed Cycles          cycle   49,728,768
    Average SM Active Cycles         cycle   908,675.45
    Total SM Elapsed Cycles          cycle   42,628,520
    Average SMSP Active Cycles       cycle   907,935.43
    Total SMSP Elapsed Cycles        cycle  170,514,080
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 12.46%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 14.62% above the average, while the minimum instance value is 5.59% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.23%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 14.35% above the average, while the minimum instance value is 5.63% below the       
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.46%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 14.62% above the average, while the minimum instance value is 5.59% below the       
          average.                                                                                                      

  conv2d_dweight_dbias_tiled_k3(const float *, const float *, float *, float *, int, int, int, int) (1, 1, 32768)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       585.00
    Elapsed Cycles                cycle    2,482,240
    Memory Throughput                 %        49.46
    DRAM Throughput                   %         0.27
    Duration                         ms         4.24
    L1/TEX Cache Throughput           %        93.67
    L2 Cache Throughput               %        14.26
    SM Active Cycles              cycle 2,477,900.75
    Compute (SM) Throughput           %        49.46
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                 32,768
    Registers Per Thread             register/thread              64
    Shared Memory Configuration Size           Kbyte           65.54
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block           11.54
    # SMs                                         SM              40
    Threads                                   thread       8,388,608
    Uses Green Context                                             0
    Waves Per SM                                              204.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block            5
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        97.38
    Achieved Active Warps Per SM           warp        31.16
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    56,196.50
    Total DRAM Elapsed Cycles        cycle  169,636,864
    Average L1 Active Cycles         cycle 2,477,900.75
    Total L1 Elapsed Cycles          cycle   99,110,112
    Average L2 Active Cycles         cycle 3,432,800.12
    Total L2 Elapsed Cycles          cycle  116,091,392
    Average SM Active Cycles         cycle 2,477,900.75
    Total SM Elapsed Cycles          cycle   99,110,112
    Average SMSP Active Cycles       cycle 2,475,325.51
    Total SMSP Elapsed Cycles        cycle  396,440,448
    -------------------------- ----------- ------------

  upsample2x_backward_sum4_nhwc_f4(const float *, float *, int, int, int, int, int) (8, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.85
    SM Frequency                    Mhz       576.89
    Elapsed Cycles                cycle        3,658
    Memory Throughput                 %         7.56
    DRAM Throughput                   %         7.56
    Duration                         us         6.34
    L1/TEX Cache Throughput           %        27.30
    L2 Cache Throughput               %         3.74
    SM Active Cycles              cycle       375.05
    Compute (SM) Throughput           %         1.22
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      8
    Registers Per Thread             register/thread              24
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           2,048
    Uses Green Context                                             0
    Waves Per SM                                                0.05
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 80%                                                                                             
          The grid for this launch is configured to execute only 8 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.90
    Achieved Active Warps Per SM           warp         7.97
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.1%                                                                                     
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     2,323.50
    Total DRAM Elapsed Cycles        cycle      245,760
    Average L1 Active Cycles         cycle       375.05
    Total L1 Elapsed Cycles          cycle      145,456
    Average L2 Active Cycles         cycle       862.69
    Total L2 Elapsed Cycles          cycle      170,624
    Average SM Active Cycles         cycle       375.05
    Total SM Elapsed Cycles          cycle      145,456
    Average SMSP Active Cycles       cycle       370.60
    Total SMSP Elapsed Cycles        cycle      581,824
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.281%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 80.29% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.205%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 80.50% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.281%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 80.29% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.093%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 31.48% above the average, while the minimum instance value is 16.19% below the      
          average.                                                                                                      

  relu_backward_f4(const float *, float *, const float *, int) (8, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.79
    SM Frequency                    Mhz       574.78
    Elapsed Cycles                cycle        3,072
    Memory Throughput                 %         4.66
    DRAM Throughput                   %         4.66
    Duration                         us         5.34
    L1/TEX Cache Throughput           %        20.09
    L2 Cache Throughput               %         2.83
    SM Active Cycles              cycle       254.85
    Compute (SM) Throughput           %         0.56
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      8
    Registers Per Thread             register/thread              18
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           2,048
    Uses Green Context                                             0
    Waves Per SM                                                0.05
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 80%                                                                                             
          The grid for this launch is configured to execute only 8 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.70
    Achieved Active Warps Per SM           warp         7.91
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.3%                                                                                     
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.7%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        1,194
    Total DRAM Elapsed Cycles        cycle      204,800
    Average L1 Active Cycles         cycle       254.85
    Total L1 Elapsed Cycles          cycle      119,904
    Average L2 Active Cycles         cycle       650.81
    Total L2 Elapsed Cycles          cycle      143,680
    Average SM Active Cycles         cycle       254.85
    Total SM Elapsed Cycles          cycle      119,904
    Average SMSP Active Cycles       cycle       248.41
    Total SMSP Elapsed Cycles        cycle      479,616
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 6.858%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 80.66% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.689%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 80.71% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.858%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 80.66% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.398%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 37.24% above the average, while the minimum instance value is 19.18% below the      
          average.                                                                                                      

  conv2d_dinput_tiled_gmem_k3(const float *, float *, const float *, int, int, int, int) (1, 1, 128)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.98
    SM Frequency                    Mhz       584.91
    Elapsed Cycles                cycle      199,703
    Memory Throughput                 %        38.91
    DRAM Throughput                   %         1.21
    Duration                         us       341.41
    L1/TEX Cache Throughput           %        69.36
    L2 Cache Throughput               %         0.87
    SM Active Cycles              cycle   177,262.52
    Compute (SM) Throughput           %        38.91
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        78.13
    Achieved Active Warps Per SM           warp        25.00
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 21.87%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (78.1%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    20,591.50
    Total DRAM Elapsed Cycles        cycle   13,606,912
    Average L1 Active Cycles         cycle   177,262.52
    Total L1 Elapsed Cycles          cycle    8,014,192
    Average L2 Active Cycles         cycle    69,963.72
    Total L2 Elapsed Cycles          cycle    9,339,264
    Average SM Active Cycles         cycle   177,262.52
    Total SM Elapsed Cycles          cycle    8,014,192
    Average SMSP Active Cycles       cycle   177,095.04
    Total SMSP Elapsed Cycles        cycle   32,056,768
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.379%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 10.60% above the average, while the minimum instance value is 5.53% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.602%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 10.86% above the average, while the minimum instance value is 4.49% below the       
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.379%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 10.60% above the average, while the minimum instance value is 5.53% below the       
          average.                                                                                                      

  conv2d_dweight_dbias_tiled_k3(const float *, const float *, float *, float *, int, int, int, int) (1, 1, 16384)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.01
    SM Frequency                    Mhz       584.99
    Elapsed Cycles                cycle      834,987
    Memory Throughput                 %        68.50
    DRAM Throughput                   %         0.33
    Duration                         ms         1.43
    L1/TEX Cache Throughput           %        87.44
    L2 Cache Throughput               %         3.00
    SM Active Cycles              cycle   832,231.20
    Compute (SM) Throughput           %        68.50
    ----------------------- ----------- ------------

    INF   Compute and Memory are well-balanced: To reduce runtime, both computation and memory traffic must be reduced. 
          Check both the Compute Workload Analysis and Memory Workload Analysis sections.                               

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                 16,384
    Registers Per Thread             register/thread              64
    Shared Memory Configuration Size           Kbyte           65.54
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block           11.54
    # SMs                                         SM              40
    Threads                                   thread       4,194,304
    Uses Green Context                                             0
    Waves Per SM                                              102.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block            5
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        96.85
    Achieved Active Warps Per SM           warp        30.99
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       23,385
    Total DRAM Elapsed Cycles        cycle   57,167,872
    Average L1 Active Cycles         cycle   832,231.20
    Total L1 Elapsed Cycles          cycle   33,437,160
    Average L2 Active Cycles         cycle   470,429.03
    Total L2 Elapsed Cycles          cycle   39,051,104
    Average SM Active Cycles         cycle   832,231.20
    Total SM Elapsed Cycles          cycle   33,437,160
    Average SMSP Active Cycles       cycle   832,258.72
    Total SMSP Elapsed Cycles        cycle  133,748,640
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 10.37%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 26.89% above the average, while the minimum instance value is 2.99% below the       
          average.                                                                                                      

  maxpool2x2_backward_scatter_noatomic(const float *, float *, const int *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.76
    SM Frequency                    Mhz       575.63
    Elapsed Cycles                cycle        2,913
    Memory Throughput                 %        14.60
    DRAM Throughput                   %        14.60
    Duration                         us         5.06
    L1/TEX Cache Throughput           %        14.37
    L2 Cache Throughput               %         4.71
    SM Active Cycles              cycle       830.58
    Compute (SM) Throughput           %         1.80
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.88
    Achieved Active Warps Per SM           warp         7.96
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.12%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.9%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     3,513.50
    Total DRAM Elapsed Cycles        cycle      192,512
    Average L1 Active Cycles         cycle       830.58
    Total L1 Elapsed Cycles          cycle      113,496
    Average L2 Active Cycles         cycle     1,128.09
    Total L2 Elapsed Cycles          cycle      135,936
    Average SM Active Cycles         cycle       830.58
    Total SM Elapsed Cycles          cycle      113,496
    Average SMSP Active Cycles       cycle       808.27
    Total SMSP Elapsed Cycles        cycle      453,984
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 6.926%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 23.66% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 7.226%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 25.37% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.926%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 23.66% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.163%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 23.21% above the average, while the minimum instance value is 18.27% below the      
          average.                                                                                                      

  relu_backward_f4(const float *, float *, const float *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.80
    SM Frequency                    Mhz       576.22
    Elapsed Cycles                cycle        3,396
    Memory Throughput                 %        16.14
    DRAM Throughput                   %        16.14
    Duration                         us         5.89
    L1/TEX Cache Throughput           %        16.09
    L2 Cache Throughput               %         8.54
    SM Active Cycles              cycle     1,272.90
    Compute (SM) Throughput           %         1.98
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              18
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        22.81
    Achieved Active Warps Per SM           warp         7.30
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 77.19%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (22.8%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        4,566
    Total DRAM Elapsed Cycles        cycle      226,304
    Average L1 Active Cycles         cycle     1,272.90
    Total L1 Elapsed Cycles          cycle      135,856
    Average L2 Active Cycles         cycle     1,506.88
    Total L2 Elapsed Cycles          cycle      158,752
    Average SM Active Cycles         cycle     1,272.90
    Total SM Elapsed Cycles          cycle      135,856
    Average SMSP Active Cycles       cycle     1,145.91
    Total SMSP Elapsed Cycles        cycle      543,424
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.629%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 25.69% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.972%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 26.59% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.629%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 25.69% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.794%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 22.37% above the average, while the minimum instance value is 11.94% below the      
          average.                                                                                                      

  conv2d_dinput_tiled_gmem_k3(const float *, float *, const float *, int, int, int, int) (1, 1, 256)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.00
    SM Frequency                    Mhz       584.98
    Elapsed Cycles                cycle      978,717
    Memory Throughput                 %        42.61
    DRAM Throughput                   %         0.65
    Duration                         ms         1.67
    L1/TEX Cache Throughput           %        85.22
    L2 Cache Throughput               %         7.35
    SM Active Cycles              cycle   885,714.85
    Compute (SM) Throughput           %        30.16
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        86.31
    Achieved Active Warps Per SM           warp        27.62
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 13.69%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (86.3%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       54,376
    Total DRAM Elapsed Cycles        cycle   66,874,368
    Average L1 Active Cycles         cycle   885,714.85
    Total L1 Elapsed Cycles          cycle   39,155,384
    Average L2 Active Cycles         cycle 1,025,140.41
    Total L2 Elapsed Cycles          cycle   45,773,856
    Average SM Active Cycles         cycle   885,714.85
    Total SM Elapsed Cycles          cycle   39,155,384
    Average SMSP Active Cycles       cycle   885,418.72
    Total SMSP Elapsed Cycles        cycle  156,621,536
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.424%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 9.31% above the average, while the minimum instance value is 6.59% below the average.       
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.496%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 9.39% above the average, while the minimum instance value is 6.65% below the        
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.424%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 9.31% above the average, while the minimum instance value is 6.59% below the        
          average.                                                                                                      

  conv2d_dweight_dbias_tiled_k3(const float *, const float *, float *, float *, int, int, int, int) (1, 1, 32768)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       584.99
    Elapsed Cycles                cycle    2,476,825
    Memory Throughput                 %        49.47
    DRAM Throughput                   %         0.27
    Duration                         ms         4.23
    L1/TEX Cache Throughput           %        93.70
    L2 Cache Throughput               %        14.34
    SM Active Cycles              cycle 2,472,033.48
    Compute (SM) Throughput           %        49.47
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                 32,768
    Registers Per Thread             register/thread              64
    Shared Memory Configuration Size           Kbyte           65.54
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block           11.54
    # SMs                                         SM              40
    Threads                                   thread       8,388,608
    Uses Green Context                                             0
    Waves Per SM                                              204.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block            5
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        97.34
    Achieved Active Warps Per SM           warp        31.15
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       56,144
    Total DRAM Elapsed Cycles        cycle  169,013,248
    Average L1 Active Cycles         cycle 2,472,033.48
    Total L1 Elapsed Cycles          cycle   99,091,504
    Average L2 Active Cycles         cycle 3,411,681.28
    Total L2 Elapsed Cycles          cycle  115,838,048
    Average SM Active Cycles         cycle 2,472,033.48
    Total SM Elapsed Cycles          cycle   99,091,504
    Average SMSP Active Cycles       cycle 2,473,708.23
    Total SMSP Elapsed Cycles        cycle  396,366,016
    -------------------------- ----------- ------------

  maxpool2x2_backward_scatter_noatomic(const float *, float *, const int *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.75
    SM Frequency                    Mhz       580.72
    Elapsed Cycles                cycle        5,449
    Memory Throughput                 %        60.55
    DRAM Throughput                   %        60.55
    Duration                         us         9.38
    L1/TEX Cache Throughput           %        33.40
    L2 Cache Throughput               %        16.89
    SM Active Cycles              cycle     3,156.60
    Compute (SM) Throughput           %         7.69
    ----------------------- ----------- ------------

    OPT   Memory is more heavily utilized than Compute: Look at the Memory Workload Analysis section to identify the    
          DRAM bottleneck. Check memory replay (coalescing) metrics to make sure you're efficiently utilizing the       
          bytes transferred. Also consider whether it is possible to do more work per memory access (kernel fusion) or  
          whether there are values you can (re)compute.                                                                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 50%                                                                                             
          A wave of thread blocks is defined as the maximum number of blocks that can be executed in parallel on the    
          target GPU. The number of blocks in a wave depends on the number of multiprocessors and the theoretical       
          occupancy of the kernel. This kernel launch results in 1 full waves and a partial wave of 96 thread blocks.   
          Under the assumption of a uniform execution duration of all thread blocks, the partial wave may account for   
          up to 50.0% of the total kernel runtime with a lower occupancy of 26.4%. Try launching a grid with no         
          partial wave. The overall impact of this tail effect also lessens with the number of full waves executed for  
          a grid. See the Hardware Model                                                                                
          (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model) description for more      
          details on launch configurations.                                                                             

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        73.59
    Achieved Active Warps Per SM           warp        23.55
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 26.41%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (73.6%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    26,969.50
    Total DRAM Elapsed Cycles        cycle      356,352
    Average L1 Active Cycles         cycle     3,156.60
    Total L1 Elapsed Cycles          cycle      212,968
    Average L2 Active Cycles         cycle     4,660.47
    Total L2 Elapsed Cycles          cycle      254,880
    Average SM Active Cycles         cycle     3,156.60
    Total SM Elapsed Cycles          cycle      212,968
    Average SMSP Active Cycles       cycle     3,093.36
    Total SMSP Elapsed Cycles        cycle      851,872
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 6.045%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 10.20% above the average, while the minimum instance value is 12.50% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.045%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 10.20% above the average, while the minimum instance value is 12.50% below the      
          average.                                                                                                      

  relu_backward_f4(const float *, float *, const float *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.50
    SM Frequency                    Mhz       581.31
    Elapsed Cycles                cycle        8,003
    Memory Throughput                 %        64.35
    DRAM Throughput                   %        64.35
    Duration                         us        13.76
    L1/TEX Cache Throughput           %        31.57
    L2 Cache Throughput               %        26.73
    SM Active Cycles              cycle     5,189.93
    Compute (SM) Throughput           %         6.66
    ----------------------- ----------- ------------

    OPT   Memory is more heavily utilized than Compute: Look at the Memory Workload Analysis section to identify the    
          DRAM bottleneck. Check memory replay (coalescing) metrics to make sure you're efficiently utilizing the       
          bytes transferred. Also consider whether it is possible to do more work per memory access (kernel fusion) or  
          whether there are values you can (re)compute.                                                                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              18
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 50%                                                                                             
          A wave of thread blocks is defined as the maximum number of blocks that can be executed in parallel on the    
          target GPU. The number of blocks in a wave depends on the number of multiprocessors and the theoretical       
          occupancy of the kernel. This kernel launch results in 1 full waves and a partial wave of 96 thread blocks.   
          Under the assumption of a uniform execution duration of all thread blocks, the partial wave may account for   
          up to 50.0% of the total kernel runtime with a lower occupancy of 22.7%. Try launching a grid with no         
          partial wave. The overall impact of this tail effect also lessens with the number of full waves executed for  
          a grid. See the Hardware Model                                                                                
          (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model) description for more      
          details on launch configurations.                                                                             

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        77.27
    Achieved Active Warps Per SM           warp        24.73
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 22.73%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (77.3%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       39,869
    Total DRAM Elapsed Cycles        cycle      495,616
    Average L1 Active Cycles         cycle     5,189.93
    Total L1 Elapsed Cycles          cycle      302,320
    Average L2 Active Cycles         cycle     7,025.81
    Total L2 Elapsed Cycles          cycle      374,304
    Average SM Active Cycles         cycle     5,189.93
    Total SM Elapsed Cycles          cycle      302,320
    Average SMSP Active Cycles       cycle     5,116.69
    Total SMSP Elapsed Cycles        cycle    1,209,280
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 5.331%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 7.87% above the average, while the minimum instance value is 15.49% below the average.      

  conv2d_dinput_tiled_cmem_k3(const float *, float *, int, int, int, int) (2, 2, 3)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       584.96
    Elapsed Cycles                cycle      393,205
    Memory Throughput                 %         9.12
    DRAM Throughput                   %         1.00
    Duration                         us       672.19
    L1/TEX Cache Throughput           %        30.83
    L2 Cache Throughput               %         0.90
    SM Active Cycles              cycle   116,229.98
    Compute (SM) Throughput           %         4.23
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     12
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread           3,072
    Uses Green Context                                             0
    Waves Per SM                                                0.07
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 70%                                                                                             
          The grid for this launch is configured to execute only 12 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        25.02
    Achieved Active Warps Per SM           warp         8.01
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 74.98%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (25.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       33,688
    Total DRAM Elapsed Cycles        cycle   26,836,992
    Average L1 Active Cycles         cycle   116,229.98
    Total L1 Elapsed Cycles          cycle   15,708,280
    Average L2 Active Cycles         cycle   132,045.97
    Total L2 Elapsed Cycles          cycle   18,389,888
    Average SM Active Cycles         cycle   116,229.98
    Total SM Elapsed Cycles          cycle   15,708,280
    Average SMSP Active Cycles       cycle   115,912.21
    Total SMSP Elapsed Cycles        cycle   62,833,120
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 20.82%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 70.35% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.72%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 70.21% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 20.82%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 70.35% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  conv2d_dweight_dbias_tiled_k3(const float *, const float *, float *, float *, int, int, int, int) (2, 2, 768)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       584.92
    Elapsed Cycles                cycle      210,056
    Memory Throughput                 %        54.85
    DRAM Throughput                   %         1.90
    Duration                         us       359.10
    L1/TEX Cache Throughput           %        87.50
    L2 Cache Throughput               %        10.38
    SM Active Cycles              cycle   205,598.25
    Compute (SM) Throughput           %        54.85
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  3,072
    Registers Per Thread             register/thread              64
    Shared Memory Configuration Size           Kbyte           65.54
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block           11.54
    # SMs                                         SM              40
    Threads                                   thread         786,432
    Uses Green Context                                             0
    Waves Per SM                                               19.20
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block            5
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        96.27
    Achieved Active Warps Per SM           warp        30.81
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    34,015.50
    Total DRAM Elapsed Cycles        cycle   14,331,904
    Average L1 Active Cycles         cycle   205,598.25
    Total L1 Elapsed Cycles          cycle    8,379,152
    Average L2 Active Cycles         cycle   202,378.53
    Total L2 Elapsed Cycles          cycle    9,822,784
    Average SM Active Cycles         cycle   205,598.25
    Total SM Elapsed Cycles          cycle    8,379,152
    Average SMSP Active Cycles       cycle   205,836.55
    Total SMSP Elapsed Cycles        cycle   33,516,608
    -------------------------- ----------- ------------

  conv2d_fwd_tiled_cmem_k3(const float *, float *, const float *, int, int, int, int) (2, 2, 256)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.06
    SM Frequency                    Mhz       584.96
    Elapsed Cycles                cycle       59,473
    Memory Throughput                 %        40.66
    DRAM Throughput                   %        10.80
    Duration                         us       101.66
    L1/TEX Cache Throughput           %        81.35
    L2 Cache Throughput               %        19.36
    SM Active Cycles              cycle    56,430.12
    Compute (SM) Throughput           %        30.98
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                  1,024
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread         262,144
    Uses Green Context                                             0
    Waves Per SM                                                6.40
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        90.48
    Achieved Active Warps Per SM           warp        28.95
    ------------------------------- ----------- ------------

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    55,549.50
    Total DRAM Elapsed Cycles        cycle    4,116,480
    Average L1 Active Cycles         cycle    56,430.12
    Total L1 Elapsed Cycles          cycle    2,398,072
    Average L2 Active Cycles         cycle    71,327.44
    Total L2 Elapsed Cycles          cycle    2,780,128
    Average SM Active Cycles         cycle    56,430.12
    Total SM Elapsed Cycles          cycle    2,398,072
    Average SMSP Active Cycles       cycle    56,289.27
    Total SMSP Elapsed Cycles        cycle    9,592,288
    -------------------------- ----------- ------------

  relu_forward_f4(const float *, float *, int) (256, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.76
    SM Frequency                    Mhz       577.31
    Elapsed Cycles                cycle        5,345
    Memory Throughput                 %        48.69
    DRAM Throughput                   %        48.69
    Duration                         us         9.25
    L1/TEX Cache Throughput           %        36.48
    L2 Cache Throughput               %        26.75
    SM Active Cycles              cycle     3,074.50
    Compute (SM) Throughput           %         8.35
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 50%                                                                                             
          A wave of thread blocks is defined as the maximum number of blocks that can be executed in parallel on the    
          target GPU. The number of blocks in a wave depends on the number of multiprocessors and the theoretical       
          occupancy of the kernel. This kernel launch results in 1 full waves and a partial wave of 96 thread blocks.   
          Under the assumption of a uniform execution duration of all thread blocks, the partial wave may account for   
          up to 50.0% of the total kernel runtime with a lower occupancy of 23.9%. Try launching a grid with no         
          partial wave. The overall impact of this tail effect also lessens with the number of full waves executed for  
          a grid. See the Hardware Model                                                                                
          (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model) description for more      
          details on launch configurations.                                                                             

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        76.06
    Achieved Active Warps Per SM           warp        24.34
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 23.94%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (76.1%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       21,438
    Total DRAM Elapsed Cycles        cycle      352,256
    Average L1 Active Cycles         cycle     3,074.50
    Total L1 Elapsed Cycles          cycle      204,072
    Average L2 Active Cycles         cycle     4,153.84
    Total L2 Elapsed Cycles          cycle      250,400
    Average SM Active Cycles         cycle     3,074.50
    Total SM Elapsed Cycles          cycle      204,072
    Average SMSP Active Cycles       cycle     3,026.25
    Total SMSP Elapsed Cycles        cycle      816,288
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 7.098%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 11.78% above the average, while the minimum instance value is 13.97% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 7.098%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 11.78% above the average, while the minimum instance value is 13.97% below the      
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 5.644%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 10.63% above the average, while the minimum instance value is 4.57% below the       
          average.                                                                                                      

  maxpool2x2_forward_nhwc_f4(const float *, float *, int *, int, int, int, int, int) (64, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       579.76
    Elapsed Cycles                cycle        5,756
    Memory Throughput                 %        38.90
    DRAM Throughput                   %        38.90
    Duration                         us         9.92
    L1/TEX Cache Throughput           %        23.43
    L2 Cache Throughput               %        19.17
    SM Active Cycles              cycle     3,496.12
    Compute (SM) Throughput           %        11.72
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.4 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     64
    Registers Per Thread             register/thread              30
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread          16,384
    Uses Green Context                                             0
    Waves Per SM                                                0.40
    -------------------------------- --------------- ---------------

    OPT   If you execute __syncthreads() to synchronize the threads of a block, it is recommended to have more than the 
          achieved 1 blocks per multiprocessor. This way, blocks that aren't waiting for __syncthreads() can keep the   
          hardware busy.                                                                                                

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            8
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        36.26
    Achieved Active Warps Per SM           warp        11.60
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 63.74%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (36.3%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    19,269.50
    Total DRAM Elapsed Cycles        cycle      396,288
    Average L1 Active Cycles         cycle     3,496.12
    Total L1 Elapsed Cycles          cycle      235,944
    Average L2 Active Cycles         cycle     4,316.59
    Total L2 Elapsed Cycles          cycle      269,664
    Average SM Active Cycles         cycle     3,496.12
    Total SM Elapsed Cycles          cycle      235,944
    Average SMSP Active Cycles       cycle     3,306.57
    Total SMSP Elapsed Cycles        cycle      943,776
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.656%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 14.60% above the average, while the minimum instance value is 26.12% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.508%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 16.96% above the average, while the minimum instance value is 36.16% below the average.     
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.656%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 14.60% above the average, while the minimum instance value is 26.12% below the      
          average.                                                                                                      

  conv2d_fwd_tiled_gmem_k3(const float *, float *, const float *, const float *, int, int, int, int) (1, 1, 128)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         5.01
    SM Frequency                    Mhz       584.98
    Elapsed Cycles                cycle    1,078,103
    Memory Throughput                 %        38.64
    DRAM Throughput                   %         0.56
    Duration                         ms         1.84
    L1/TEX Cache Throughput           %        77.29
    L2 Cache Throughput               %         7.40
    SM Active Cycles              cycle   921,479.68
    Compute (SM) Throughput           %        27.38
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        72.07
    Achieved Active Warps Per SM           warp        23.06
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 27.93%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (72.1%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    51,332.50
    Total DRAM Elapsed Cycles        cycle   73,843,712
    Average L1 Active Cycles         cycle   921,479.68
    Total L1 Elapsed Cycles          cycle   43,116,520
    Average L2 Active Cycles         cycle    1,218,260
    Total L2 Elapsed Cycles          cycle   50,422,080
    Average SM Active Cycles         cycle   921,479.68
    Total SM Elapsed Cycles          cycle   43,116,520
    Average SMSP Active Cycles       cycle   921,300.24
    Total SMSP Elapsed Cycles        cycle  172,466,080
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 12.81%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 14.99% above the average, while the minimum instance value is 5.79% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.81%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 14.99% above the average, while the minimum instance value is 5.64% below the       
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 12.81%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 14.99% above the average, while the minimum instance value is 5.79% below the       
          average.                                                                                                      

  relu_forward_f4(const float *, float *, int) (32, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.95
    SM Frequency                    Mhz       579.47
    Elapsed Cycles                cycle        3,062
    Memory Throughput                 %         8.78
    DRAM Throughput                   %         8.78
    Duration                         us         5.28
    L1/TEX Cache Throughput           %        12.09
    L2 Cache Throughput               %         6.66
    SM Active Cycles              cycle       986.12
    Compute (SM) Throughput           %         1.90
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.2 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                     32
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           8,192
    Uses Green Context                                             0
    Waves Per SM                                                0.20
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 20%                                                                                             
          The grid for this launch is configured to execute only 32 blocks, which is less than the GPU's 40             
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        23.96
    Achieved Active Warps Per SM           warp         7.67
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 76.04%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.0%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle        2,292
    Total DRAM Elapsed Cycles        cycle      208,896
    Average L1 Active Cycles         cycle       986.12
    Total L1 Elapsed Cycles          cycle      121,440
    Average L2 Active Cycles         cycle     1,156.12
    Total L2 Elapsed Cycles          cycle      143,008
    Average SM Active Cycles         cycle       986.12
    Total SM Elapsed Cycles          cycle      121,440
    Average SMSP Active Cycles       cycle       960.27
    Total SMSP Elapsed Cycles        cycle      485,760
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.289%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 25.52% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.55%                                                                                           
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 27.03% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.289%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 25.52% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.661%                                                                                          
          One or more L2 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 25.75% above the average, while the minimum instance value is 18.78% below the      
          average.                                                                                                      

  maxpool2x2_forward_nhwc_f4(const float *, float *, int *, int, int, int, int, int) (8, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.98
    SM Frequency                    Mhz       577.97
    Elapsed Cycles                cycle        4,090
    Memory Throughput                 %         7.08
    DRAM Throughput                   %         7.08
    Duration                         us         7.07
    L1/TEX Cache Throughput           %        22.35
    L2 Cache Throughput               %         4.07
    SM Active Cycles              cycle       458.12
    Compute (SM) Throughput           %         2.12
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      8
    Registers Per Thread             register/thread              30
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           2,048
    Uses Green Context                                             0
    Waves Per SM                                                0.05
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 80%                                                                                             
          The grid for this launch is configured to execute only 8 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            8
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.50
    Achieved Active Warps Per SM           warp         7.84
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.5%                                                                                     
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.5%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle     2,492.50
    Total DRAM Elapsed Cycles        cycle      281,600
    Average L1 Active Cycles         cycle       458.12
    Total L1 Elapsed Cycles          cycle      162,760
    Average L2 Active Cycles         cycle     1,112.84
    Total L2 Elapsed Cycles          cycle      190,848
    Average SM Active Cycles         cycle       458.12
    Total SM Elapsed Cycles          cycle      162,760
    Average SMSP Active Cycles       cycle       448.07
    Total SMSP Elapsed Cycles        cycle      651,040
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 9.082%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 80.66% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.872%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 80.57% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 9.082%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 80.66% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  conv2d_fwd_tiled_gmem_k3(const float *, float *, const float *, const float *, int, int, int, int) (1, 1, 128)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       584.91
    Elapsed Cycles                cycle      200,582
    Memory Throughput                 %        38.82
    DRAM Throughput                   %         1.22
    Duration                         us       342.91
    L1/TEX Cache Throughput           %        69.20
    L2 Cache Throughput               %         0.76
    SM Active Cycles              cycle   175,807.30
    Compute (SM) Throughput           %        38.82
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.8 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    128
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread          32,768
    Uses Green Context                                             0
    Waves Per SM                                                0.80
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        78.13
    Achieved Active Warps Per SM           warp        25.00
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 21.87%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (78.1%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle    20,830.50
    Total DRAM Elapsed Cycles        cycle   13,697,024
    Average L1 Active Cycles         cycle   175,807.30
    Total L1 Elapsed Cycles          cycle    8,034,008
    Average L2 Active Cycles         cycle    77,423.16
    Total L2 Elapsed Cycles          cycle    9,380,320
    Average SM Active Cycles         cycle   175,807.30
    Total SM Elapsed Cycles          cycle    8,034,008
    Average SMSP Active Cycles       cycle   175,062.91
    Total SMSP Elapsed Cycles        cycle   32,136,032
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 10.69%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 12.22% above the average, while the minimum instance value is 4.68% below the average.      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.03%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 11.51% above the average, while the minimum instance value is 4.49% below the       
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 10.69%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 12.22% above the average, while the minimum instance value is 4.68% below the       
          average.                                                                                                      

  relu_forward_f4(const float *, float *, int) (8, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.93
    SM Frequency                    Mhz       577.70
    Elapsed Cycles                cycle        2,866
    Memory Throughput                 %         2.57
    DRAM Throughput                   %         2.57
    Duration                         us         4.96
    L1/TEX Cache Throughput           %        14.59
    L2 Cache Throughput               %         2.19
    SM Active Cycles              cycle       224.75
    Compute (SM) Throughput           %         0.51
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      8
    Registers Per Thread             register/thread              16
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           2,048
    Uses Green Context                                             0
    Waves Per SM                                                0.05
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 80%                                                                                             
          The grid for this launch is configured to execute only 8 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           16
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        24.59
    Achieved Active Warps Per SM           warp         7.87
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 75.41%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.6%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle          628
    Total DRAM Elapsed Cycles        cycle      195,584
    Average L1 Active Cycles         cycle       224.75
    Total L1 Elapsed Cycles          cycle      112,952
    Average L2 Active Cycles         cycle       532.38
    Total L2 Elapsed Cycles          cycle      133,824
    Average SM Active Cycles         cycle       224.75
    Total SM Elapsed Cycles          cycle      112,952
    Average SMSP Active Cycles       cycle       218.01
    Total SMSP Elapsed Cycles        cycle      451,808
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 6.39%                                                                                           
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 80.29% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.219%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 80.55% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 6.39%                                                                                           
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 80.29% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  upsample2x_forward_nhwc_f4(const float *, float *, int, int, int, int, int) (8, 1, 1)x(256, 1, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.83
    SM Frequency                    Mhz       576.85
    Elapsed Cycles                cycle        3,490
    Memory Throughput                 %         3.88
    DRAM Throughput                   %         2.20
    Duration                         us         6.05
    L1/TEX Cache Throughput           %        32.27
    L2 Cache Throughput               %         3.88
    SM Active Cycles              cycle       339.60
    Compute (SM) Throughput           %         1.12
    ----------------------- ----------- ------------

    OPT   This kernel grid is too small to fill the available resources on this device, resulting in only 0.1 full      
          waves across all SMs. Look at Launch Statistics for more details.                                             

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                      8
    Registers Per Thread             register/thread              18
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block        byte/block               0
    # SMs                                         SM              40
    Threads                                   thread           2,048
    Uses Green Context                                             0
    Waves Per SM                                                0.05
    -------------------------------- --------------- ---------------

    OPT   Est. Speedup: 80%                                                                                             
          The grid for this launch is configured to execute only 8 blocks, which is less than the GPU's 40              
          multiprocessors. This can underutilize some multiprocessors. If you do not intend to execute this kernel      
          concurrently with other workloads, consider reducing the block size to have at least one block per            
          multiprocessor or increase the size of the grid to fully utilize the available hardware resources. See the    
          Hardware Model (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-hw-model)            
          description for more details on launch configurations.                                                        

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block           10
    Block Limit Shared Mem                block           16
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        22.62
    Achieved Active Warps Per SM           warp         7.24
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 77.38%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (22.6%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       643.50
    Total DRAM Elapsed Cycles        cycle      233,472
    Average L1 Active Cycles         cycle       339.60
    Total L1 Elapsed Cycles          cycle      138,296
    Average L2 Active Cycles         cycle       956.94
    Total L2 Elapsed Cycles          cycle      162,784
    Average SM Active Cycles         cycle       339.60
    Total SM Elapsed Cycles          cycle      138,296
    Average SMSP Active Cycles       cycle       324.95
    Total SMSP Elapsed Cycles        cycle      553,184
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 7.927%                                                                                          
          One or more SMs have a much lower number of active cycles than the average number of active cycles. Maximum   
          instance value is 80.70% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 7.637%                                                                                          
          One or more SMSPs have a much lower number of active cycles than the average number of active cycles. Maximum 
          instance value is 81.26% above the average, while the minimum instance value is 100.00% below the average.    
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 7.927%                                                                                          
          One or more L1 Slices have a much lower number of active cycles than the average number of active cycles.     
          Maximum instance value is 80.70% above the average, while the minimum instance value is 100.00% below the     
          average.                                                                                                      

  conv2d_fwd_tiled_gmem_k3(const float *, float *, const float *, const float *, int, int, int, int) (1, 1, 256)x(16, 16, 1), Context 1, Stream 7, Device 0, CC 7.5
    Section: GPU Speed Of Light Throughput
    ----------------------- ----------- ------------
    Metric Name             Metric Unit Metric Value
    ----------------------- ----------- ------------
    DRAM Frequency                  Ghz         4.99
    SM Frequency                    Mhz       584.97
    Elapsed Cycles                cycle      982,170
    Memory Throughput                 %        42.58
    DRAM Throughput                   %         0.65
    Duration                         ms         1.68
    L1/TEX Cache Throughput           %        85.17
    L2 Cache Throughput               %         7.58
    SM Active Cycles              cycle   889,651.47
    Compute (SM) Throughput           %        30.14
    ----------------------- ----------- ------------

    OPT   This kernel exhibits low compute throughput and memory bandwidth utilization relative to the peak performance 
          of this device. Achieved compute throughput and/or memory bandwidth below 60.0% of peak typically indicate    
          latency issues. Look at Scheduler Statistics and Warp State Statistics for potential reasons.                 

    Section: Launch Statistics
    -------------------------------- --------------- ---------------
    Metric Name                          Metric Unit    Metric Value
    -------------------------------- --------------- ---------------
    Block Size                                                   256
    Function Cache Configuration                     CachePreferNone
    Grid Size                                                    256
    Registers Per Thread             register/thread              63
    Shared Memory Configuration Size           Kbyte           32.77
    Driver Shared Memory Per Block        byte/block               0
    Dynamic Shared Memory Per Block       byte/block               0
    Static Shared Memory Per Block       Kbyte/block            1.30
    # SMs                                         SM              40
    Threads                                   thread          65,536
    Uses Green Context                                             0
    Waves Per SM                                                1.60
    -------------------------------- --------------- ---------------

    Section: Occupancy
    ------------------------------- ----------- ------------
    Metric Name                     Metric Unit Metric Value
    ------------------------------- ----------- ------------
    Block Limit SM                        block           16
    Block Limit Registers                 block            4
    Block Limit Shared Mem                block           21
    Block Limit Warps                     block            4
    Theoretical Active Warps per SM        warp           32
    Theoretical Occupancy                     %          100
    Achieved Occupancy                        %        85.84
    Achieved Active Warps Per SM           warp        27.47
    ------------------------------- ----------- ------------

    OPT   Est. Local Speedup: 14.16%                                                                                    
          The difference between calculated theoretical (100.0%) and measured achieved occupancy (85.8%) can be the     
          result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can   
          occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices   
          Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on     
          optimizing occupancy.                                                                                         

    Section: GPU and Memory Workload Distribution
    -------------------------- ----------- ------------
    Metric Name                Metric Unit Metric Value
    -------------------------- ----------- ------------
    Average DRAM Active Cycles       cycle       54,656
    Total DRAM Elapsed Cycles        cycle   67,050,496
    Average L1 Active Cycles         cycle   889,651.47
    Total L1 Elapsed Cycles          cycle   39,188,920
    Average L2 Active Cycles         cycle 1,044,105.91
    Total L2 Elapsed Cycles          cycle   45,935,392
    Average SM Active Cycles         cycle   889,651.47
    Total SM Elapsed Cycles          cycle   39,188,920
    Average SMSP Active Cycles       cycle   888,382.18
    Total SMSP Elapsed Cycles        cycle  156,755,680
    -------------------------- ----------- ------------

    OPT   Est. Speedup: 8.327%                                                                                          
          One or more SMs have a much higher number of active cycles than the average number of active cycles. Maximum  
          instance value is 9.17% above the average, while the minimum instance value is 6.81% below the average.       
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.361%                                                                                          
          One or more SMSPs have a much higher number of active cycles than the average number of active cycles.        
          Maximum instance value is 9.22% above the average, while the minimum instance value is 5.96% below the        
          average.                                                                                                      
    ----- --------------------------------------------------------------------------------------------------------------
    OPT   Est. Speedup: 8.327%                                                                                          
          One or more L1 Slices have a much higher number of active cycles than the average number of active cycles.    
          Maximum instance value is 9.17% above the average, while the minimum instance value is 6.81% below the        
          average.