From 4c73e96508b3d071ab8175dc3181e31c70f057b3 Mon Sep 17 00:00:00 2001 From: "msc25h24 Ho Tin Hung (hohung)" Date: Mon, 15 Jun 2026 17:22:17 +0200 Subject: [PATCH 01/39] init --- .gitignore | 6 + Makefile | 4 +- software/tests/CMakeLists.txt | 4 + .../tests/fdotp-32b-single/data/.gitignore | 3 + software/tests/fdotp-32b-single/data/layer.h | 150 +++++++++++++ .../tests/fdotp-32b-single/kernel/fdotp.c | 166 ++++++++++++++ .../tests/fdotp-32b-single/kernel/fdotp.h | 33 +++ software/tests/fdotp-32b-single/main copy.c | 130 +++++++++++ software/tests/fdotp-32b-single/main.c | 205 ++++++++++++++++++ .../fdotp-32b-single/script/data_1024.json | 12 + .../fdotp-32b-single/script/data_8192.json | 12 + .../tests/fdotp-32b-single/script/gen_data.py | 186 ++++++++++++++++ 12 files changed, 909 insertions(+), 2 deletions(-) create mode 100644 software/tests/fdotp-32b-single/data/.gitignore create mode 100644 software/tests/fdotp-32b-single/data/layer.h create mode 100644 software/tests/fdotp-32b-single/kernel/fdotp.c create mode 100644 software/tests/fdotp-32b-single/kernel/fdotp.h create mode 100644 software/tests/fdotp-32b-single/main copy.c create mode 100644 software/tests/fdotp-32b-single/main.c create mode 100644 software/tests/fdotp-32b-single/script/data_1024.json create mode 100644 software/tests/fdotp-32b-single/script/data_8192.json create mode 100644 software/tests/fdotp-32b-single/script/gen_data.py diff --git a/.gitignore b/.gitignore index 51c4fe1..00071ef 100644 --- a/.gitignore +++ b/.gitignore @@ -40,3 +40,9 @@ hardware/bootrom/bootrom.elf hardware/bootrom/bootrom.sv # Configuration auto-generated files config/cachepool.hjson + +sim.sh +CLAUDE.md +scratchpad.txt +claude_doc +temp diff --git a/Makefile b/Makefile index bf9889c..5965c52 100644 --- a/Makefile +++ b/Makefile @@ -16,8 +16,8 @@ CACHEPOOL_DIR := $(shell git rev-parse --show-toplevel 2>/dev/null || echo $$CAC SOFTWARE_DIR ?= ${CACHEPOOL_DIR}/software # Host compilers (for DPI, simulators, tools) -CXX ?= /usr/pack/gcc-11.2.0-af/linux-x64/bin/g++ -CC ?= /usr/pack/gcc-11.2.0-af/linux-x64/bin/gcc +CXX := /usr/pack/gcc-11.2.0-af/linux-x64/bin/g++ +CC := /usr/pack/gcc-11.2.0-af/linux-x64/bin/gcc CXX_PATH ?= $(shell realpath -P $(CXX)) CC_PATH ?= $(shell realpath -P $(CC)) GCC_LIB ?= /usr/pack/gcc-11.2.0-af/linux-x64/lib64 diff --git a/software/tests/CMakeLists.txt b/software/tests/CMakeLists.txt index 583337e..415547c 100644 --- a/software/tests/CMakeLists.txt +++ b/software/tests/CMakeLists.txt @@ -67,6 +67,7 @@ include_directories(${SNRUNTIME_INCLUDE_DIRS}) # Kernels ## Vector Kernels add_library(fdotp-32b fdotp-32b/kernel/fdotp.c) +add_library(fdotp-32b-single fdotp-32b-single/kernel/fdotp.c) add_library(idotp-32b idotp-32b/kernel/idotp.c) add_library(fmatmul-32b fmatmul-32b/kernel/fmatmul.c) @@ -100,6 +101,9 @@ add_spatz_test_oneParam(fdotp-32b fdotp-32b/main.c 8192) add_spatz_test_oneParam(fdotp-32b fdotp-32b/main.c 32768) add_spatz_test_oneParam(fdotp-32b fdotp-32b/main.c 65536) +add_spatz_test_oneParam(fdotp-32b-single fdotp-32b-single/main.c 1024) +add_spatz_test_oneParam(fdotp-32b-single fdotp-32b-single/main.c 8192) + add_spatz_test_threeParam(gemv gemv/main.c 128 128 32) add_spatz_test_threeParam(gemv gemv/main.c 256 128 32) add_spatz_test_threeParam(gemv gemv/main.c 512 128 32) diff --git a/software/tests/fdotp-32b-single/data/.gitignore b/software/tests/fdotp-32b-single/data/.gitignore new file mode 100644 index 0000000..3005476 --- /dev/null +++ b/software/tests/fdotp-32b-single/data/.gitignore @@ -0,0 +1,3 @@ +# Generated data headers — reproduced by `make gen-data` +*.h +!layer.h diff --git a/software/tests/fdotp-32b-single/data/layer.h b/software/tests/fdotp-32b-single/data/layer.h new file mode 100644 index 0000000..4a68cf6 --- /dev/null +++ b/software/tests/fdotp-32b-single/data/layer.h @@ -0,0 +1,150 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#pragma once + +#include + +typedef enum { FP64 = 8, FP32 = 4, FP16 = 2, FP8 = 1 } precision_t; + +/** + * @struct gemm_layer_struct + * @brief This structure contains all parameters necessary for GEMM. + * @var gemm_layer_struct::M + * Dimension of matrix product MxK * KxN + * @var gemm_layer_struct::M_p + * M divided by number of compute cores + * @var gemm_layer_struct::N + * Dimension of matrix product MxK * KxN + * @var gemm_layer_struct::K + * Dimension of matrix product MxK * KxN + * @var gemm_layer_struct::TA + * Transpose matrix A + * @var gemm_layer_struct::TB + * Transpose matrix B + * @var gemm_layer_struct::TILE_M + * Tile factor across M dimension + * @var gemm_layer_struct::TILE_N + * Tile factor across N dimension + * @var gemm_layer_struct::TILE_K + * Tile factor across K dimension + * @var gemm_layer_struct::A + * Pointer to matrix A + * @var gemm_layer_struct::B + * Pointer to matrix B + * @var gemm_layer_struct::C + * Pointer to matrix C + * @var gemm_layer_struct::ALPHA + * constant factor: A * B + ALPHA * C + * @var gemm_layer_struct::dtype + * Precision of GEMM + * @var gemm_layer_struct::expand + * Use expanding DOTP instructions + */ +typedef struct gemm_layer_struct { + uint32_t M; + uint32_t M_p; + uint32_t N; + uint32_t K; + + uint32_t TA; + uint32_t TB; + + uint32_t TILE_M; + uint32_t TILE_N; + uint32_t TILE_K; + + double *A; + double *B; + double *C; + + uint32_t ALPHA; + + precision_t dtype; + uint32_t expand; +} gemm_layer; + +/** + * @struct conv_layer_struct + * @brief This structure contains all parameters necessary for Convolutional + * layers + * @var conv_layer_struct::CO + * Number of output channels + * @var conv_layer_struct::CI + * Number of input channels + * @var conv_layer_struct::IH + * Height of input feature map + * @var conv_layer_struct::IW + * Width of input feature map + * @var conv_layer_struct::OH + * Height of output feature map + * @var conv_layer_struct::OW + * Width of output feature map + * @var conv_layer_struct::FH + * Height of filter + * @var conv_layer_struct::FW + * Width of filter + * @var conv_layer_struct::pad + * Padding on all sides + * @var conv_layer_struct::ifmap + * Pointer to input feature map + * @var conv_layer_struct::weights + * Pointer to weights + * @var conv_layer_struct::ofmap + * Pointer to output feature map + * @var conv_layer_struct::TILE_CI + * Tiling factor of input channel + * @var conv_layer_struct::cluster2cluster + * Flag for enabling cluster 2 cluster communication + * @var conv_layer_struct::im2col + * Flag for enabling im2col + GEMM + * @var conv_layer_struct::gamma + * Pointer to gamma for BatchNorm + * @var conv_layer_struct::beta + * Pointer to beta for BatchNorm + * @var gemm_layer_struct::dtype + * Precision of Convolution layer + */ +typedef struct conv_layer_struct { + // CONV2D + uint32_t CO; + uint32_t CI; + uint32_t IH; + uint32_t IW; + uint32_t OH; + uint32_t OW; + uint32_t FH; + uint32_t FW; + uint32_t pad; + + double *ifmap; + double *weights; + double *ofmap; + + uint32_t TILE_CI; + uint32_t cluster2cluster; + uint32_t im2col; + + // BATCHNORM + double *gamma; + double *beta; + + precision_t dtype; +} conv_layer; + +/** + * @struct dotp_layer_struct + * @brief This structure contains all parameters necessary for DOTP + * layers + * @var dotp_layer_struct::M + * Length of the vectors + * @var gemm_layer_struct::dtype + * Precision of Convolution layer + */ +typedef struct dotp_layer_struct { + // DOTP + uint32_t M; + + precision_t dtype; +} dotp_layer; diff --git a/software/tests/fdotp-32b-single/kernel/fdotp.c b/software/tests/fdotp-32b-single/kernel/fdotp.c new file mode 100644 index 0000000..e57ae15 --- /dev/null +++ b/software/tests/fdotp-32b-single/kernel/fdotp.c @@ -0,0 +1,166 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Matteo Perotti + +#include "fdotp.h" + +static inline int fp_check(const float a, const float b) { + const float threshold = 0.01f; + + // Absolute value + float comp = a - b; + if (comp < 0) + comp = -comp; + + return comp > threshold; +} + +// 32-bit dot-product: a * b +float fdotp_v32b_lmul8(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) { + unsigned int vl; + unsigned int iter = rounds; + + float red; + + // Set the vl + asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(avl)); + + asm volatile("vle32.v v8, (%0)" ::"r"(a)); + iter --; + asm volatile("vle32.v v16, (%0)" ::"r"(b)); + asm volatile("vfmul.vv v24, v8, v16"); + + // Stripmine and accumulate a partial reduced vector + while (iter > 0) { + // Load chunk a and b + a += offset; + asm volatile("vle32.v v8, (%0)" ::"r"(a)); + b += offset; + asm volatile("vle32.v v16, (%0)" ::"r"(b)); + iter --; + + // Multiply and accumulate + asm volatile("vfmacc.vv v24, v8, v16"); + } + + // Reduce and return + asm volatile("vfredusum.vs v0, v24, v0"); + asm volatile("vfmv.f.s %0, v0" : "=f"(red)); + return red; +} + +// 32-bit dot-product: a * b +float fdotp_v32b_lmul4(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) { + unsigned int vl; + unsigned int iter = rounds; + + float red; + + // Set the vl + asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(avl)); + + asm volatile("vle32.v v8, (%0)" ::"r"(a)); + iter --; + asm volatile("vle32.v v16, (%0)" ::"r"(b)); + asm volatile("vfmul.vv v24, v8, v16"); + + // Stripmine and accumulate a partial reduced vector + do { + // Load chunk a and b + a += offset; + asm volatile("vle32.v v8, (%0)" ::"r"(a)); + b += offset; + asm volatile("vle32.v v16, (%0)" ::"r"(b)); + iter --; + + // Multiply and accumulate + asm volatile("vfmacc.vv v24, v8, v16"); + } while (iter > 0); + + // Reduce and return + asm volatile("vfredusum.vs v0, v24, v0"); + asm volatile("vfmv.f.s %0, v0" : "=f"(red)); + return red; +} + +// 32-bit dot-product: a * b +float fdotp_v32b_lmul2(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) { + unsigned int vl; + unsigned int iter = rounds; + + float red; + + // Set the vl + asm volatile("vsetvli %0, %1, e32, m2, ta, ma" : "=r"(vl) : "r"(avl)); + + asm volatile("vle32.v v8, (%0)" ::"r"(a)); + iter --; + asm volatile("vle32.v v16, (%0)" ::"r"(b)); + asm volatile("vfmul.vv v24, v8, v16"); + + // Stripmine and accumulate a partial reduced vector + do { + // Load chunk a and b + a += offset; + asm volatile("vle32.v v8, (%0)" ::"r"(a)); + b += offset; + asm volatile("vle32.v v16, (%0)" ::"r"(b)); + iter --; + + // Multiply and accumulate + asm volatile("vfmacc.vv v24, v8, v16"); + } while (iter > 0); + + // Reduce and return + asm volatile("vfredusum.vs v0, v24, v0"); + asm volatile("vfmv.f.s %0, v0" : "=f"(red)); + return red; +} + +// 32-bit dot-product: a * b +float fdotp_v32b_lmul1(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) { + unsigned int vl; + unsigned int iter = rounds; + + float red; + + // Set the vl + asm volatile("vsetvli %0, %1, e32, m1, ta, ma" : "=r"(vl) : "r"(avl)); + + asm volatile("vle32.v v8, (%0)" ::"r"(a)); + iter --; + asm volatile("vle32.v v16, (%0)" ::"r"(b)); + asm volatile("vfmul.vv v24, v8, v16"); + + // Stripmine and accumulate a partial reduced vector + do { + // Load chunk a and b + a += offset; + asm volatile("vle32.v v8, (%0)" ::"r"(a)); + b += offset; + asm volatile("vle32.v v16, (%0)" ::"r"(b)); + iter --; + + // Multiply and accumulate + asm volatile("vfmacc.vv v24, v8, v16"); + } while (iter > 0); + + // Reduce and return + asm volatile("vfredusum.vs v0, v24, v0"); + asm volatile("vfmv.f.s %0, v0" : "=f"(red)); + return red; +} diff --git a/software/tests/fdotp-32b-single/kernel/fdotp.h b/software/tests/fdotp-32b-single/kernel/fdotp.h new file mode 100644 index 0000000..dee0958 --- /dev/null +++ b/software/tests/fdotp-32b-single/kernel/fdotp.h @@ -0,0 +1,33 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Matteo Perotti + +#ifndef _FDOTPROD_H_ +#define _FDOTPROD_H_ + +inline float fdotp_v32b_lmul8(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) + __attribute__((always_inline)); + +inline float fdotp_v32b_lmul4(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) + __attribute__((always_inline)); + +inline float fdotp_v32b_lmul2(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) + __attribute__((always_inline)); + +inline float fdotp_v32b_lmul1(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) + __attribute__((always_inline)); +#endif diff --git a/software/tests/fdotp-32b-single/main copy.c b/software/tests/fdotp-32b-single/main copy.c new file mode 100644 index 0000000..52a4ffd --- /dev/null +++ b/software/tests/fdotp-32b-single/main copy.c @@ -0,0 +1,130 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Diyou Shen + +#include +#include +#include + +#include DATAHEADER +#include "kernel/fdotp.c" + +// Single-core baseline of fdotp-32b: the whole dot product is computed on +// core 0 only. The other cores fall straight through to `return 0`. +// +// NOTE: no cluster barriers and no l1d_xbar_config() are used here. Those +// helpers issue snrt_cluster_hw_barrier() internally and would deadlock, +// since the remaining cores never reach the barrier. +int main() { + const uint32_t num_cores = 1; + const uint32_t cid = snrt_cluster_core_idx(); + + if (cid == 0) { + const int measure_iter = 3; + + // Byte-level interleaving for DRAM (default 512b), used to keep all DRAM + // channels busy while a single core streams the whole vector. + const uint32_t Interleave = 512; + const uint32_t max_vlen = 512; + // Best LMUL setting for the current configuration + const uint32_t lmul = Interleave * 8 / max_vlen; + + // Each round computes Interleave/4 32-bit elements + const uint32_t elem_per_round = Interleave * num_cores / 4; + // How many rounds are needed to cover the whole vector? + const uint32_t rounds = + (dotp_l.M > elem_per_round) + ? ((dotp_l.M + elem_per_round - 1) / elem_per_round) + : 1; + const uint32_t dim = elem_per_round / num_cores; + + // Initialize the cache (barrier-free, safe to call from core 0 alone) + l1d_init(0); + + printf("round:%u, lmul:%u, dim:%u\n", rounds, lmul, dim); + + // Reset timer + uint32_t timer = (uint32_t)-1; + uint32_t timer_tmp, timer_iter1 = 0; + + float *a_int = dotp_A_dram + dim * cid; + float *b_int = dotp_B_dram + dim * cid; + + for (int iter = 0; iter < measure_iter; iter++) { + // Start dump + start_kernel(); + + // Start timer + timer_tmp = benchmark_get_cycle(); + + // Calculate dotp over the whole vector + float acc; + if (lmul >= 8) + acc = fdotp_v32b_lmul8(a_int, b_int, elem_per_round, dim, rounds); + else if (lmul >= 4) + acc = fdotp_v32b_lmul4(a_int, b_int, elem_per_round, dim, rounds); + else if (lmul >= 2) + acc = fdotp_v32b_lmul2(a_int, b_int, elem_per_round, dim, rounds); + else if (lmul >= 1) + acc = fdotp_v32b_lmul1(a_int, b_int, elem_per_round, dim, rounds); + else + return -3; + + // Make sure spatz has finished writing + snrt_fence_spatz(); + + result[cid] = acc; + + // End timer and keep the best runtime + timer_tmp = benchmark_get_cycle() - timer_tmp; + timer = (timer < timer_tmp) ? timer : timer_tmp; + if (iter == 0) + timer_iter1 = timer; + + stop_kernel(); + } + + // Check and display results + uint32_t performance = 1000 * 2 * dotp_l.M / timer; + uint32_t perf_iter1 = 1000 * 2 * dotp_l.M / timer_iter1; + uint32_t utilization = performance / (2 * num_cores * 4); + uint32_t util_iter1 = perf_iter1 / (2 * num_cores * 4); + write_cyc(timer); + + printf("\n----- (%d) sp fdotp (single core) -----\n", dotp_l.M); + printf("The 1st execution took %u cycles.\n", timer_iter1); + printf("The performance is %u OP/1000cycle (%u%%o utilization).\n", + perf_iter1, util_iter1); + printf("The execution took %u cycles.\n", timer); + printf("The performance is %u OP/1000cycle (%u%%o utilization).\n", + performance, utilization); + + // Each iteration recomputes the same full dot product, so result[0] + // holds a single dot product and must match the golden value directly. + if (fp_check(result[0], dotp_result)) { + printf("Check Failed!\n"); + printf("Calc:"); + snrt_printf_float(result[0]); + printf(", Exp:"); + snrt_printf_float(dotp_result); + printf("\n"); + return -1; + } + } + + return 0; +} diff --git a/software/tests/fdotp-32b-single/main.c b/software/tests/fdotp-32b-single/main.c new file mode 100644 index 0000000..e544c74 --- /dev/null +++ b/software/tests/fdotp-32b-single/main.c @@ -0,0 +1,205 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Diyou Shen + +#include +#include +#include + +#include DATAHEADER +#include "kernel/fdotp.c" + +// Single-core baseline of fdotp-32b: the whole dot product is computed on +// core 0 only. The other cores fall straight through to `return 0`. +// +// NOTE: no cluster barriers and no l1d_xbar_config() are used here. Those +// helpers issue snrt_cluster_hw_barrier() internally and would deadlock, +// since the remaining cores never reach the barrier. +int main() { + const uint32_t num_cores = 1; + const uint32_t cid = snrt_cluster_core_idx(); + + if (cid == 0) { + const uint32_t measure_iter = 3; + + /*** DRAM Parameters for Optimization ***/ + const uint32_t l2_interleave = 16; + const uint32_t l2_channel = 4; + // in bits + const uint32_t l2_lanewidth = 512; + // This is the continuous address block (bits) in DRAM + const uint32_t l2_block_size = l2_lanewidth * l2_interleave; + const uint32_t l2_block_elem = l2_block_size / 32; + + /*** Core Parameters for Optimization ***/ + const uint32_t elem_per_core = dotp_l.M / num_cores; + const uint32_t lmul_m1 = 512; + const uint32_t lmul_m1_elem = lmul_m1 / 32; + + const uint32_t lmul_max = elem_per_core / lmul_m1_elem; + uint32_t lmul; + if (lmul_max >= 8) { + lmul = 8; + } else if (lmul_max >= 4) { + lmul = 4; + } else if (lmul_max >= 2) { + lmul = 2; + } else if (lmul_max == 1) { + lmul = 1; + } else { + // if (cid == 0) { + printf("FATAL: Problem size too small!\n"); + return -2; + // } + } + + uint32_t elem_per_round = lmul * lmul_m1_elem; + // We need to reduce scrambling size while keeping all channels busy + // This is needed to reduce the loop control overhead + uint32_t rounds = dotp_l.M / elem_per_round / num_cores; + + + if ((elem_per_round * num_cores) < (l2_block_elem * l2_channel)) { + // if (cid == 0) { + printf("Warning: Current scheme cannot utilize all bandwidth!\n"); + // } + } + + // We want to map one block for one core to access + // This will make the cores visiting different DRAM channel + // Therefore, we need to scramble the L1 xbar at the same size + // Notice scrambling here is in bytes + const uint32_t l1_scramble_bits = 31 - __builtin_clz(elem_per_round*32/8); + + // Set xbar policy + l1d_xbar_config(l1_scramble_bits); + + // Now for all cores, it will execute #elem_per_round# data each round + // And then jump #elem_per_round*num_cores# elements in address for next round + uint32_t elem_jump_per_round = elem_per_round * num_cores; + + // Reset timer + uint32_t timer = (uint32_t)-1; + uint32_t timer_tmp, timer_iter1; + + // Calculate the starting points for each core + float *a_int = dotp_A_dram + cid * elem_per_round; + float *b_int = dotp_B_dram + cid * elem_per_round; + + // if (cid == 0) { + printf("lmul:%u, elem:%u, offs:%u, iter:%u\n", lmul, elem_per_round, elem_jump_per_round, rounds); + // } + + + for (int iter = 0; iter < measure_iter; iter ++) { + // Start dump + // if (cid == 0) + start_kernel(); + + // snrt_cluster_hw_barrier(); + + // Start timer + timer_tmp = benchmark_get_cycle(); + + // Calculate dotp + float acc; + + if (lmul >= 8) + acc = fdotp_v32b_lmul8(a_int, b_int, elem_jump_per_round, elem_per_round, rounds); + else if (lmul >= 4) + acc = fdotp_v32b_lmul4(a_int, b_int, elem_jump_per_round, elem_per_round, rounds); + else if (lmul >= 2) + acc = fdotp_v32b_lmul2(a_int, b_int, elem_jump_per_round, elem_per_round, rounds); + else if (lmul >= 1) + acc = fdotp_v32b_lmul1(a_int, b_int, elem_jump_per_round, elem_per_round, rounds); + else + return -3; + + result[cid] = acc; + + // Make sure spatz has finished writing + snrt_fence_spatz(); + + // Wait for all cores to finish + // snrt_cluster_hw_barrier(); + + // End timer and check if new best runtime + // if (cid == 0) { + timer_tmp = benchmark_get_cycle() - timer_tmp; + timer = (timer < timer_tmp) ? timer : timer_tmp; + if (iter == 0) + timer_iter1 = timer; + + stop_kernel(); + // } + + // // Final reduction: two-level tree with group size 4 + // const uint32_t red_group = 4; + + // // Level 1: lead core of each group accumulates its group + // if (cid % red_group == 0) { + // for (uint32_t i = 1; i < red_group && (cid + i) < num_cores; ++i) + // acc += result[cid + i]; + // result[cid] = acc; + // } + + // // snrt_cluster_hw_barrier(); + + // // Level 2: core 0 sums all group results + // if (cid == 0) { + // for (uint32_t g = red_group; g < num_cores; g += red_group) + // acc += result[g]; + // result[0] = acc; + // } + + } + + // snrt_cluster_hw_barrier(); + + // Check and display results + // if (cid == 0) { + // The timer did not count the reduction time + uint32_t performance = 1000 * 2 * dotp_l.M / timer; + uint32_t perf_iter1 = 1000 * 2 * dotp_l.M / timer_iter1; + uint32_t utilization = performance / (2 * num_cores * 4); + uint32_t util_iter1 = perf_iter1 / (2 * num_cores * 4); + write_cyc(timer); + + printf("\n----- (%d) sp fdotp -----\n", dotp_l.M); + printf("The 1st execution took %u cycles.\n", timer_iter1); + printf("The performance is %u OP/1000cycle (%u%%o utilization).\n", + perf_iter1 , util_iter1); + printf("The execution took %u cycles.\n", timer); + printf("The performance is %u OP/1000cycle (%u%%o utilization).\n", + performance, utilization); + // } + + // if (cid == 0) { + if (fp_check(result[0], dotp_result*measure_iter)) { + printf("Check Failed!\n"); + printf("Calc:"); + snrt_printf_float(result[0]); + printf(", Exp:"); + snrt_printf_float((float)(dotp_result * measure_iter)); + printf("\n"); + return -1; + } + // } + } + + return 0; +} diff --git a/software/tests/fdotp-32b-single/script/data_1024.json b/software/tests/fdotp-32b-single/script/data_1024.json new file mode 100644 index 0000000..96712c5 --- /dev/null +++ b/software/tests/fdotp-32b-single/script/data_1024.json @@ -0,0 +1,12 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Parameters for a DOTP + +{ + kernel: "DOTP" + M: 1024, + prec: 32, + expand: 0 +} diff --git a/software/tests/fdotp-32b-single/script/data_8192.json b/software/tests/fdotp-32b-single/script/data_8192.json new file mode 100644 index 0000000..aa351d3 --- /dev/null +++ b/software/tests/fdotp-32b-single/script/data_8192.json @@ -0,0 +1,12 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Parameters for a DOTP + +{ + kernel: "DOTP" + M: 8192, + prec: 32, + expand: 0 +} diff --git a/software/tests/fdotp-32b-single/script/gen_data.py b/software/tests/fdotp-32b-single/script/gen_data.py new file mode 100644 index 0000000..8513133 --- /dev/null +++ b/software/tests/fdotp-32b-single/script/gen_data.py @@ -0,0 +1,186 @@ +#!/usr/bin/env python3 +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Author: Matheus Cavalcante + +import numpy as np +import torch +import argparse +import pathlib +import hjson +from functools import reduce + +np.random.seed(42) +torch.manual_seed(42) + +global verbose + + +def array_to_cstr(a, fmt=float): + out = "{" + if fmt == float: + if isinstance(a, np.ndarray): + a = a.flat + if isinstance(a, torch.Tensor): + a = a.numpy().flat + for el in a: + out += "{}, ".format(el) + else: + for sign, exp, mant in zip( + a["sign"].numpy().flat, + a["exponent"].numpy().flat, + a["mantissa"].numpy().flat, + ): + value = sign * 2**7 + exp * 2**2 + mant + out += "0x{:02x}, ".format(value) + out = out[:-2] + "}" + return out + + +def emit_header_file(layer_type: str, **kwargs): + + file_path = pathlib.Path(__file__).parent.parent / "data" + emit_str = ( + "// Copyright 2023 ETH Zurich and University of Bologna.\n" + + "// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n" + + "// SPDX-License-Identifier: Apache-2.0\n\n" + + "// This file was generated automatically.\n\n" + ) + + file = file_path / ("data_" + str(kwargs["M"]) + ".h") + emit_str += emit_dotp_layer(**kwargs) + with file.open("w") as f: + f.write(emit_str) + + +def emit_dotp_layer(name="dotp", **kwargs): + vec_A = kwargs["A"] + vec_B = kwargs["B"] + result = kwargs["result"] + + m = kwargs["M"] + + layer_str = "" + layer_str += '#include "layer.h"\n\n' + layer_str += f"dotp_layer {name}_l __attribute__((section(\".data\"))) = {{\n" + layer_str += f"\t.M = {m},\n" + layer_str += f'\t.dtype = FP{kwargs["prec"]},\n' + layer_str += "};\n\n\n" + + ctypes = {"64": "double", "32": "float", "16": "__fp16", "8": "char"} + + dtype = ctypes[str(kwargs["prec"])] + if dtype != "char": + layer_str += ( + f'static {dtype} {name}_A_dram [{m}] __attribute__((section(".pdcp_src"), used)) = ' + + array_to_cstr(vec_A) + + ";\n\n\n" + ) + layer_str += ( + f'static {dtype} {name}_B_dram [{m}] __attribute__((section(".pdcp_src"), used))= ' + + array_to_cstr(vec_B) + + ";\n\n\n" + ) + layer_str += ( + f'static {dtype} {name}_result __attribute__((section(".data"))) = ' + + array_to_cstr(result) + + ";\n\n\n" + ) + layer_str += '// Global memory location to hold reduction results for each core\n' + layer_str += ( + f'{dtype} result [64] __attribute__((section(".data"))) = {{0}}' + + ";\n\n\n" + ) + else: + layer_str += ( + f"static {dtype} {name}_A_dram [{m}] = " + + array_to_cstr(kwargs["bits_A"], fmt="char") + + ";\n\n\n" + ) + layer_str += ( + f"static {dtype} {name}_B_dram [{m}] = " + + array_to_cstr(kwargs["bits_B"], fmt="char") + + ";\n\n\n" + ) + layer_str += ( + f"static {dtype} {name}_result = " + + array_to_cstr(kwargs["result"], fmt="char") + + ";\n\n\n" + ) + + return layer_str + + +def rand_data_generator(shape, prec, alt=False): + if prec == 64: + return torch.randn(shape, requires_grad=False, dtype=torch.float64), {} + elif prec == 32: + return torch.randn(shape, requires_grad=False, dtype=torch.float32), {} + elif prec == 16: + if alt: + return torch.randn(shape, requires_grad=False, dtype=torch.bfloat16), {} + else: + return torch.randn(shape, requires_grad=False, dtype=torch.float16), {} + elif prec == 8: + sign = torch.randint( + 0, 2, shape, requires_grad=False, dtype=torch.uint8 + ) # -1 or 1 + exponent = torch.randint( + 0, 16, shape, requires_grad=False, dtype=torch.uint8 + ) # < 0b01111 + mantissa = torch.randint( + 0, 4, shape, requires_grad=False, dtype=torch.uint8 + ) # can be arbitrary + bits = {"sign": sign, "exponent": exponent, "mantissa": mantissa} + # TODO: not actually correct + return ((-1.0) ** sign.double()) * (2.0 ** (exponent.double() - 15.0)) * ( + 1.0 + mantissa.double() / (2**2) + ), bits + + +def dotp(a, b): + return reduce(lambda a, b: a + b, np.multiply(a, b)) + + +def main(): + + parser = argparse.ArgumentParser(description="Generate data for kernels") + parser.add_argument( + "-c", + "--cfg", + type=pathlib.Path, + required=True, + help="Select param config file kernel", + ) + parser.add_argument("-v", "--verbose", action="store_true", help="Set verbose") + + args = parser.parse_args() + + global verbose + verbose = args.verbose + + with args.cfg.open() as f: + param = hjson.loads(f.read()) + + vec_A, bits_A = rand_data_generator((param["M"], 1), param["prec"]) + vec_B, bits_B = rand_data_generator((param["M"], 1), param["prec"]) + result = dotp(vec_A, vec_B) + + kwargs = { + "A": vec_A, + "B": vec_B, + "result": result, + "M": param["M"], + "prec": param["prec"], + "expand": param["expand"], + "bits_A": bits_A, + "bits_B": bits_B, + } + + emit_header_file("dotp", **kwargs) + + +if __name__ == "__main__": + main() From d1dcb953c886034ce0d8a4d0333ab33793d5f819 Mon Sep 17 00:00:00 2001 From: "msc25h24 Ho Tin Hung (hohung)" Date: Tue, 16 Jun 2026 17:25:43 +0200 Subject: [PATCH 02/39] [HW] init L1 private cache controller --- hardware/src/cachepool_l1_ctrl.sv | 707 ++++++++++++++++++++++++++++++ 1 file changed, 707 insertions(+) create mode 100644 hardware/src/cachepool_l1_ctrl.sv diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv new file mode 100644 index 0000000..bb19554 --- /dev/null +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -0,0 +1,707 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Ho Tin Hung +// +// Per-core private L1 data cache controller. +// +// Core side is a plain TCDM interface: NrTCDMPortsPerCore request/response +// streams (the Spatz lanes + one Snitch port). Inside, this module: +// * coalesces the Spatz lanes into one wide HPDcache request (sid=0), +// * translates the Snitch port into one HPDcache request (sid=1), +// * packs all metadata that must survive the HPDcache round-trip into `tid`, +// * runs one HPDcache (write-through, no coherence) as the private L1, +// * merges HPDcache's mem read/write channels into one downstream TCDM pair +// (l2_req_o/l2_rsp_i) that feeds the shared distributed L2 through the +// existing tcdm_cache_interco, +// * scatters the response back to the originating lanes. +// +// No cache coherence is implemented here. Write-through narrows but does not +// close the cross-core shared-data window; that is accepted for now. +// +// Coalescer metadata has no package; all coalescer-facing types (tcdm_meta_t, +// downstream_info_t, word_offset_t, ...) are defined at the tile and passed in +// as parameters. + +module cachepool_l1_ctrl + import cachepool_pkg::*; + import hpdcache_pkg::*; + import reqrsp_pkg::*; +#( + // Core-side topology + parameter int unsigned NrTCDMPortsPerCore = 5, // Spatz lanes + 1 Snitch + parameter int unsigned DataWidth = 32, // narrow (per-lane) data width + parameter int unsigned ByteWidth = 8, + + // tid / coalescer geometry (must match the types below) + parameter int unsigned LP1NumWordOffsetBits = 2, // $clog2(wordWidth/DataWidth) + parameter int unsigned LP1NrBitsCoalOffset = 2, // bits per coalescer ofst entry + // (lane count is NrLP1CoalInputs, derived below) + + parameter hpdcache_cfg_t HPDcacheCfg = '0, + parameter type wbuf_timecnt_t = logic, + + // Core-side TCDM request/response + parameter type l1_cache_req_t = logic, + parameter type l1_cache_rsp_t = logic, + + // Coalescer payload types (defined at tile) + parameter type tcdm_meta_t = logic, // { tcdm_user_t user; logic write; hpdcache_req_op_t amo; } + parameter type downstream_info_t = logic, // par_coalescer_top downstream info struct + parameter type word_offset_t = logic, // logic[LP1NumWordOffsetBits-1:0] + + // Downstream (L2) TCDM request/response + parameter type l2_cache_req_t = logic, + parameter type l2_cache_rsp_t = logic, + + // HPDcache request interface types + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_data_word_t = logic, + parameter type hpdcache_data_be_t = logic, + parameter type hpdcache_req_offset_t = logic, + parameter type hpdcache_req_data_t = logic, + parameter type hpdcache_req_be_t = logic, + parameter type hpdcache_req_sid_t = logic, + parameter type hpdcache_req_tid_t = logic, + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic, + + // HPDcache memory interface types + parameter type hpdcache_mem_addr_t = logic, + parameter type hpdcache_mem_id_t = logic, + parameter type hpdcache_mem_data_t = logic, + parameter type hpdcache_mem_be_t = logic, + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_req_w_t = logic, + parameter type hpdcache_mem_resp_r_t = logic, + parameter type hpdcache_mem_resp_w_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic wbuf_flush_i, + + // Core-side TCDM interface (Spatz lanes [0..NrLP1CoalInputs-1] + Snitch [last]). + // Request handshake : core_req_i.q_valid / core_req_ready_o + // Response handshake: core_rsp_o.p_valid / core_rsp_ready_i + input l1_cache_req_t [NrTCDMPortsPerCore-1:0] core_req_i, + output l1_cache_rsp_t [NrTCDMPortsPerCore-1:0] core_rsp_o, + output logic [NrTCDMPortsPerCore-1:0] core_req_ready_o, + input logic [NrTCDMPortsPerCore-1:0] core_rsp_ready_i, + + // Downstream (L2) TCDM interface + output l2_cache_req_t l2_req_o, + input l2_cache_rsp_t l2_rsp_i, + output logic l2_rsp_ready_o, // response ready -> interco core_rsp_ready_i + + // Performance events + output logic evt_cache_write_miss_o, + output logic evt_cache_read_miss_o, + output logic evt_cache_dir_unc_err_o, + output logic evt_cache_dir_cor_err_o, + output logic evt_cache_dat_unc_err_o, + output logic evt_cache_dat_cor_err_o, + output logic evt_scrub_complete_o, + output logic evt_uncached_req_o, + output logic evt_cmo_req_o, + output logic evt_write_req_o, + output logic evt_read_req_o, + output logic evt_prefetch_req_o, + output logic evt_req_on_hold_o, + output logic evt_rtab_rollback_o, + output logic evt_stall_refill_o, + output logic evt_stall_o, + + // Status interface + output logic wbuf_empty_o, + + // Configuration interface + input logic cfg_enable_i, + input wbuf_timecnt_t cfg_wbuf_threshold_i, + input logic cfg_wbuf_reset_timecnt_on_write_i, + input logic cfg_wbuf_sequential_waw_i, + input logic cfg_wbuf_inhibit_write_coalescing_i, + input logic cfg_prefetch_updt_plru_i, + input logic cfg_error_on_cacheable_amo_i, + input logic cfg_rtab_single_entry_i, + input logic cfg_default_wb_i, + input logic cfg_scrub_enable_i, + input logic [5:0] cfg_scrub_period_i, + input logic cfg_scrub_restart_i +); + + //////////////// + // PARAMETERS // + //////////////// + localparam int unsigned NrLP1CoalInputs = NrTCDMPortsPerCore - 1; // Spatz lanes + localparam int unsigned SnitchPort = NrTCDMPortsPerCore - 1; // last port + localparam int unsigned coalescedDataWidth = HPDcacheCfg.u.wordWidth; // wide word + localparam int unsigned LaneBytes = DataWidth / ByteWidth; // bytes per lane word + localparam int unsigned WordBytes = coalescedDataWidth / ByteWidth; + + // tid layout (one fixed, non-overlapping scheme), MSB -> LSB: + // { word_offset | is_fpu | core_id | write | req_id | ofsts | hitmap } + // Snitch path uses word_offset (ofsts/hitmap = 0); Spatz path uses ofsts/hitmap + // (word_offset = 0). The {is_fpu, core_id, write, req_id} block is at fixed + // positions for both. sid (0 Spatz / 1 Snitch) selects the unpack path. + localparam int unsigned ReqIdW = $bits(reqid_t); + localparam int unsigned HitmapW = NrLP1CoalInputs; + localparam int unsigned OfstsW = NrLP1CoalInputs * LP1NrBitsCoalOffset; + localparam int unsigned CoalInfoW = HitmapW + OfstsW; + localparam int unsigned TidUserW = CoreIDWidth + ReqIdW + 2; // {is_fpu,core_id,write,req_id} + localparam int unsigned HitmapLsb = 0; + localparam int unsigned OfstsLsb = HitmapW; + localparam int unsigned ReqIdLsb = CoalInfoW; + localparam int unsigned WritePos = CoalInfoW + ReqIdW; + localparam int unsigned CoreIdLsb = CoalInfoW + ReqIdW + 1; + localparam int unsigned IsFpuPos = CoalInfoW + ReqIdW + 1 + CoreIDWidth; + localparam int unsigned WordOffLsb = CoalInfoW + TidUserW; + + /////////////////// + // LOCAL SIGNALS // + /////////////////// + + // Per-port unpacked core request fields + logic [NrTCDMPortsPerCore-1:0] cache_req_valid; + logic [NrTCDMPortsPerCore-1:0] cache_req_ready; + hpdcache_req_offset_t [NrTCDMPortsPerCore-1:0] cache_req_addr_offset; + word_offset_t [NrTCDMPortsPerCore-1:0] cache_req_word_offset; + logic [NrTCDMPortsPerCore-1:0][CoreIDWidth-1:0] cache_req_coreid; + reqid_t [NrTCDMPortsPerCore-1:0] cache_req_reqid; + logic [NrTCDMPortsPerCore-1:0] cache_req_is_fpu; + logic [NrTCDMPortsPerCore-1:0] cache_req_write; + narrow_data_t [NrTCDMPortsPerCore-1:0] cache_req_data; + amo_op_e [NrTCDMPortsPerCore-1:0] cache_req_amo; + narrow_addr_t [NrTCDMPortsPerCore-1:0] cache_req_addr; + narrow_strb_t [NrTCDMPortsPerCore-1:0] cache_req_strb; + + // Per-port HPDcache request view + coalescer info payload + hpdcache_req_t [NrTCDMPortsPerCore-1:0] l1_cache_req; + tcdm_meta_t [NrTCDMPortsPerCore-1:0] cache_req_info; + + // Coalescer downstream request payload (Spatz path) + logic coal_req_valid; + logic coal_req_ready; + narrow_addr_t coal_req_addr; + downstream_info_t coal_req_info; + logic coal_req_write; + logic [coalescedDataWidth-1:0] coal_req_wdata; + logic [WordBytes-1:0] coal_req_wmask; + + // Coalescer upstream response (Spatz lanes) + logic [NrLP1CoalInputs-1:0] coal_resp_valid; + logic [NrLP1CoalInputs-1:0] coal_resp_ready; + logic [NrLP1CoalInputs-1:0] coal_resp_write; + narrow_data_t [NrLP1CoalInputs-1:0] coal_resp_data; + tcdm_meta_t [NrLP1CoalInputs-1:0] coal_resp_info; + + // Coalescer downstream response payload (reconstructed from the HPDcache rsp) + logic coal_resp_down_valid; + logic coal_resp_down_ready; + downstream_info_t coal_resp_down_info; + logic coal_resp_down_write; + + // HPDcache requester arrays (0 = Spatz, 1 = Snitch) + logic l1_req_valid [HPDcacheCfg.u.nRequesters]; + logic l1_req_ready [HPDcacheCfg.u.nRequesters]; + hpdcache_req_t l1_req [HPDcacheCfg.u.nRequesters]; + logic l1_rsp_valid [HPDcacheCfg.u.nRequesters]; + hpdcache_rsp_t l1_rsp [HPDcacheCfg.u.nRequesters]; + logic core_req_abort [HPDcacheCfg.u.nRequesters]; + hpdcache_tag_t core_req_tag [HPDcacheCfg.u.nRequesters]; + hpdcache_pma_t dummy_pma [HPDcacheCfg.u.nRequesters]; + + // HPDcache <-> L2 mem channels + hpdcache_mem_req_t l1_mem_req_read, l1_mem_req_write, l1_l2_req; + hpdcache_mem_req_w_t l1_mem_req_write_data; + logic l1_mem_req_read_valid, l1_mem_req_read_ready; + logic l1_mem_req_write_valid, l1_mem_req_write_ready, __l1_mem_req_write_ready; + logic l1_mem_req_write_data_valid, l1_mem_req_write_data_ready; + logic l1_mem_req_write_both_valid; + logic l1_l2_req_valid; + tcdm_user_t l1_l2_req_meta; + + hpdcache_mem_resp_r_t l1_mem_resp_read; + hpdcache_mem_resp_w_t l1_mem_resp_write; + logic l1_mem_resp_read_valid, l1_mem_resp_read_ready; + logic l1_mem_resp_write_valid, l1_mem_resp_write_ready; + + /////////////////////////////// + // Core request unpacking // + /////////////////////////////// + for (genvar i = 0; i < NrTCDMPortsPerCore; i++) begin : gen_req_unpack + // Request grant on the explicit handshake port. + assign core_req_ready_o[i] = cache_req_ready[i]; + assign cache_req_valid[i] = core_req_i[i].q_valid; + assign cache_req_addr_offset[i] = core_req_i[i].q.addr[HPDcacheCfg.reqOffsetWidth-1:0]; + assign cache_req_word_offset[i] = core_req_i[i].q.addr[$clog2(DataWidth/ByteWidth) +: LP1NumWordOffsetBits]; + assign cache_req_coreid[i] = core_req_i[i].q.user.core_id; + assign cache_req_reqid[i] = core_req_i[i].q.user.req_id; + assign cache_req_is_fpu[i] = core_req_i[i].q.user.is_fpu; + assign cache_req_write[i] = core_req_i[i].q.write; + assign cache_req_data[i] = core_req_i[i].q.data; + assign cache_req_amo[i] = core_req_i[i].q.amo; + assign cache_req_addr[i] = core_req_i[i].q.addr; + assign cache_req_strb[i] = core_req_i[i].q.strb; + end + + /////////////////////////////// + // Per-port HPDcache req view // + /////////////////////////////// + for (genvar i = 0; i < NrTCDMPortsPerCore; i++) begin : gen_req_view + assign l1_cache_req[i].addr_offset = cache_req_addr_offset[i]; + assign l1_cache_req[i].wdata = cache_req_data[i]; + assign l1_cache_req[i].be = cache_req_strb[i]; + assign l1_cache_req[i].size = hpdcache_req_size_t'($clog2(coalescedDataWidth/8)); + assign l1_cache_req[i].sid = hpdcache_req_sid_t'(!cache_req_is_fpu[i]); // 0 Spatz / 1 Snitch + assign l1_cache_req[i].need_rsp = 1'b1; + assign l1_cache_req[i].phys_indexed = 1'b1; + assign l1_cache_req[i].addr_tag = cache_req_addr[i][HPDcacheCfg.reqOffsetWidth +: HPDcacheCfg.tagWidth]; + assign l1_cache_req[i].pma.uncacheable = 1'b0; + assign l1_cache_req[i].pma.io = 1'b0; + assign l1_cache_req[i].pma.wr_policy_hint = HPDCACHE_WR_POLICY_WT; + // Snitch-path tid (per-port). Spatz lanes get their tid rebuilt post-coalesce. + assign l1_cache_req[i].tid = pack_tid_snitch(cache_req_word_offset[i], + cache_req_is_fpu[i], + cache_req_coreid[i], + cache_req_write[i], + cache_req_reqid[i]); + + // Op map (loads/stores/AMOs). AMOs flow through HPDcache in phase 1. + always_comb begin : gen_op + if (cache_req_amo[i] == AMONone) begin + l1_cache_req[i].op = cache_req_write[i] ? HPDCACHE_REQ_STORE : HPDCACHE_REQ_LOAD; + end else begin + unique case (cache_req_amo[i]) + AMOSwap: l1_cache_req[i].op = HPDCACHE_REQ_AMO_SWAP; + AMOAdd: l1_cache_req[i].op = HPDCACHE_REQ_AMO_ADD; + AMOAnd: l1_cache_req[i].op = HPDCACHE_REQ_AMO_AND; + AMOOr: l1_cache_req[i].op = HPDCACHE_REQ_AMO_OR; + AMOXor: l1_cache_req[i].op = HPDCACHE_REQ_AMO_XOR; + AMOMax: l1_cache_req[i].op = HPDCACHE_REQ_AMO_MAX; + AMOMaxu: l1_cache_req[i].op = HPDCACHE_REQ_AMO_MAXU; + AMOMin: l1_cache_req[i].op = HPDCACHE_REQ_AMO_MIN; + AMOMinu: l1_cache_req[i].op = HPDCACHE_REQ_AMO_MINU; + AMOLR: l1_cache_req[i].op = HPDCACHE_REQ_AMO_LR; + AMOSC: l1_cache_req[i].op = HPDCACHE_REQ_AMO_SC; + default: l1_cache_req[i].op = HPDCACHE_REQ_LOAD; + endcase + end + end + + // Coalescer info payload (carried per lane, returned with the response). + assign cache_req_info[i].user.core_id = cache_req_coreid[i]; + assign cache_req_info[i].user.tile_id = '0; // tagged at tile level + assign cache_req_info[i].user.is_amo = (cache_req_amo[i] != AMONone); + assign cache_req_info[i].user.req_id = cache_req_reqid[i]; + assign cache_req_info[i].user.is_fpu = cache_req_is_fpu[i]; + assign cache_req_info[i].write = cache_req_write[i]; + assign cache_req_info[i].amo = l1_cache_req[i].op; + end + + ////////////////////////// + // Spatz req coalescing // + ////////////////////////// + par_coalescer_top #( + .ReqAddrWidth (L1AddrWidth), + .NumPorts (NrLP1CoalInputs), + .info_t (tcdm_meta_t), + .UpstreamDataWidth (DataWidth), + .DownstreamDataWidth (coalescedDataWidth), + .ByteWidth (ByteWidth) + ) i_l1_req_coalescer ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .id_i ('0), + + .upstream_req_valid_i (cache_req_valid[NrLP1CoalInputs-1:0]), + .upstream_req_ready_o (cache_req_ready[NrLP1CoalInputs-1:0]), + .upstream_req_addr_i (cache_req_addr[NrLP1CoalInputs-1:0]), + .upstream_req_info_i (cache_req_info[NrLP1CoalInputs-1:0]), + .upstream_req_write_i (cache_req_write[NrLP1CoalInputs-1:0]), + .upstream_req_wdata_i (cache_req_data[NrLP1CoalInputs-1:0]), + .upstream_req_wstrb_i (cache_req_strb[NrLP1CoalInputs-1:0]), + + .upstream_resp_valid_o (coal_resp_valid), + .upstream_resp_ready_i (coal_resp_ready), + .upstream_resp_write_o (coal_resp_write), + .upstream_resp_data_o (coal_resp_data), + .upstream_resp_info_o (coal_resp_info), + + .downstream_req_valid_o (coal_req_valid), + .downstream_req_ready_i (coal_req_ready), + .downstream_req_addr_o (coal_req_addr), + .downstream_req_info_o (coal_req_info), + .downstream_req_write_o (coal_req_write), + .downstream_req_wdata_o (coal_req_wdata), + .downstream_req_wmask_o (coal_req_wmask), + + .downstream_resp_valid_i (coal_resp_down_valid), + .downstream_resp_ready_o (coal_resp_down_ready), + .downstream_resp_data_i (l1_rsp[0].rdata), + .downstream_resp_info_i (coal_resp_down_info), + .downstream_resp_write_i (coal_resp_down_write) + ); + + ////////////////////////////////////// + // HPDcache requester 0 (Spatz/coal) // + ////////////////////////////////////// + // Shared user for the coalesced request: all coalesced lanes belong to one + // Spatz instruction (same core/req_id), so any hit lane's user is the shared + // one. Pick the first hit lane. + logic coal_hit; + tcdm_meta_t coal_meta; + always_comb begin : gen_coal_shared_meta + coal_hit = 1'b0; + coal_meta = '0; + for (int unsigned id = 0; id < NrLP1CoalInputs; id++) begin + if (coal_req_info.hitmap[id] && !coal_hit) begin + coal_hit = 1'b1; + coal_meta = coal_req_info.infos[id]; + end + end + end + + // BE for the coalesced (wide) request. + // NOTE: preserved hitmap-shift scheme (each hit lane marks its lane-width bytes + // at its lane index) rather than the coalescer's wmask, per design intent. + // Revisit with owner before switching to coal_req_wmask. + logic [WordBytes-1:0] coal_be; + always_comb begin : gen_coal_be + coal_be = '0; + for (int unsigned id = 0; id < NrLP1CoalInputs; id++) begin + if (coal_req_info.hitmap[id]) begin + coal_be |= ({LaneBytes{1'b1}} << (id * LaneBytes)); + end + end + end + + always_comb begin : gen_l1_req_spatz + l1_req[0] = '0; + l1_req[0].addr_offset = coal_req_addr[HPDcacheCfg.reqOffsetWidth-1:0]; + l1_req[0].addr_tag = coal_req_addr[HPDcacheCfg.reqOffsetWidth +: HPDcacheCfg.tagWidth]; + l1_req[0].wdata = coal_req_wdata; + l1_req[0].be = coal_be; + l1_req[0].size = hpdcache_req_size_t'($clog2(coalescedDataWidth/8)); + l1_req[0].sid = hpdcache_req_sid_t'(0); // Spatz + l1_req[0].need_rsp = 1'b1; + l1_req[0].phys_indexed = 1'b1; + l1_req[0].pma.uncacheable = 1'b0; + l1_req[0].pma.io = 1'b0; + l1_req[0].pma.wr_policy_hint = HPDCACHE_WR_POLICY_WT; + // op: AMOs are never coalesced; for an AMO carry the hit lane's op. + l1_req[0].op = coal_meta.user.is_amo ? coal_meta.amo + : (coal_req_write ? HPDCACHE_REQ_STORE : HPDCACHE_REQ_LOAD); + // tid: pack the coalescer scatter info + shared user. + l1_req[0].tid = coal_req_valid + ? pack_tid_spatz(coal_req_info.hitmap, coal_req_info.ofsts, + coal_meta.user.is_fpu, coal_meta.user.core_id, + coal_req_write, coal_meta.user.req_id) + : '0; + end + + assign l1_req_valid[0] = coal_req_valid; + assign coal_req_ready = l1_req_ready[0]; + + /////////////////////////////////// + // HPDcache requester 1 (Snitch) // + /////////////////////////////////// + // Snitch writes its narrow word into the wide cache word at its byte position. + logic [$clog2(WordBytes)-1:0] sn_byte_pos; + assign sn_byte_pos = l1_cache_req[SnitchPort].addr_offset % WordBytes; + + always_comb begin : gen_l1_req_snitch + l1_req[1] = l1_cache_req[SnitchPort]; + l1_req[1].sid = hpdcache_req_sid_t'(1); // Snitch + l1_req[1].wdata = hpdcache_req_data_t'(cache_req_data[SnitchPort]) << (sn_byte_pos * ByteWidth); + l1_req[1].be = hpdcache_req_be_t'(cache_req_strb[SnitchPort]) << sn_byte_pos; + l1_req[1].tid = core_req_i[SnitchPort].q_valid ? l1_cache_req[SnitchPort].tid : '0; + end + + assign l1_req_valid[1] = core_req_i[SnitchPort].q_valid; + assign cache_req_ready[SnitchPort] = l1_req_ready[1]; + + /////////////////////////////// + // Spatz response scatter // + /////////////////////////////// + // Rebuild the coalescer downstream response info from the round-tripped tid + // (requester 0), then feed the coalescer so it scatters to the Spatz lanes. + tcdm_user_t coal_resp_user; + always_comb begin : gen_coal_resp_info + coal_resp_down_info = '0; + coal_resp_down_info.hitmap = l1_rsp[0].tid[HitmapLsb +: HitmapW]; + coal_resp_down_info.ofsts = l1_rsp[0].tid[OfstsLsb +: OfstsW]; + + coal_resp_user = '0; + coal_resp_user.is_fpu = l1_rsp[0].tid[IsFpuPos]; + coal_resp_user.core_id = l1_rsp[0].tid[CoreIdLsb +: CoreIDWidth]; + coal_resp_user.req_id = l1_rsp[0].tid[ReqIdLsb +: ReqIdW]; + coal_resp_user.is_amo = 1'b0; + + // All coalesced lanes share the same user (one Spatz instruction). + for (int unsigned j = 0; j < NrLP1CoalInputs; j++) begin + coal_resp_down_info.infos[j].user = coal_resp_user; + coal_resp_down_info.infos[j].write = l1_rsp[0].tid[WritePos]; + coal_resp_down_info.infos[j].amo = HPDCACHE_REQ_LOAD; + end + end + + assign coal_resp_down_valid = l1_rsp_valid[0]; + assign coal_resp_down_write = l1_rsp[0].tid[WritePos]; + + // Coalescer upstream responses -> Spatz lane TCDM responses. The core's + // per-lane response ready drains the coalescer's resp FIFOs (which absorb the + // un-back-pressurable HPDcache core response). + for (genvar i = 0; i < NrLP1CoalInputs; i++) begin : gen_spatz_resp + assign core_rsp_o[i].q_ready = cache_req_ready[i]; // request grant (also on core_req_ready_o) + assign coal_resp_ready[i] = core_rsp_ready_i[i]; + assign core_rsp_o[i].p_valid = coal_resp_valid[i]; + assign core_rsp_o[i].p.data = coal_resp_data[i]; + assign core_rsp_o[i].p.user = coal_resp_info[i].user; + assign core_rsp_o[i].p.write = coal_resp_write[i]; + end + + /////////////////////////////// + // Snitch response (bypass) // + /////////////////////////////// + // NOTE: HPDcache's core response is not back-pressurable, so core_rsp_ready_i + // [SnitchPort] cannot stall it. Snitch is scalar with a single outstanding load + // and is assumed always ready; add a spill here if that ever changes. + logic [$clog2(coalescedDataWidth)-1:0] sn_bit_offset; + assign sn_bit_offset = l1_rsp[1].tid[WordOffLsb +: LP1NumWordOffsetBits] * DataWidth; + + always_comb begin : gen_snitch_resp + core_rsp_o[SnitchPort] = '0; + core_rsp_o[SnitchPort].p_valid = l1_rsp_valid[1]; + core_rsp_o[SnitchPort].q_ready = cache_req_ready[SnitchPort]; + core_rsp_o[SnitchPort].p.data = l1_rsp[1].rdata[0][sn_bit_offset +: DataWidth]; + core_rsp_o[SnitchPort].p.user.is_fpu = l1_rsp[1].tid[IsFpuPos]; + core_rsp_o[SnitchPort].p.user.core_id = l1_rsp[1].tid[CoreIdLsb +: CoreIDWidth]; + core_rsp_o[SnitchPort].p.user.req_id = l1_rsp[1].tid[ReqIdLsb +: ReqIdW]; + core_rsp_o[SnitchPort].p.user.is_amo = 1'b0; + core_rsp_o[SnitchPort].p.user.tile_id = '0; + core_rsp_o[SnitchPort].p.write = l1_rsp[1].tid[WritePos]; + end + + //////////////////////// + // L2 -> L1 response // + //////////////////////// + // The L2 response valid/ready handshake is (l2_rsp_i.p_valid / l2_rsp_ready_o); + // the ready rides on a separate wire (the interco's core_rsp_ready_i), not in + // tcdm_rsp_t (whose q_ready is the request grant). HPDcache's mem_resp_*_ready + // drives it, so refills/write-acks are properly back-pressured. Read/write + // responses are distinguished by p.write and steered to the matching HPDcache + // mem channel. The original HPDcache mem id is recovered by removing the + // per-core offset the tile added (req_id - core_id); the L1 controller is + // core-private and core_id-agnostic. + always_comb begin : rsp_translation + l1_mem_resp_read_valid = 1'b0; + l1_mem_resp_write_valid = 1'b0; + l1_mem_resp_read = '0; + l1_mem_resp_write = '0; + + if (l2_rsp_i.p.write) begin + l1_mem_resp_write_valid = l2_rsp_i.p_valid; + l1_mem_resp_write.mem_resp_w_is_atomic = l2_rsp_i.p.user.is_amo; + l1_mem_resp_write.mem_resp_w_error = HPDCACHE_MEM_RESP_OK; + l1_mem_resp_write.mem_resp_w_id = l2_rsp_i.p.user.req_id - l2_rsp_i.p.user.core_id; + end else begin + l1_mem_resp_read_valid = l2_rsp_i.p_valid; + l1_mem_resp_read.mem_resp_r_error = HPDCACHE_MEM_RESP_OK; + l1_mem_resp_read.mem_resp_r_id = l2_rsp_i.p.user.req_id - l2_rsp_i.p.user.core_id; + l1_mem_resp_read.mem_resp_r_data = l2_rsp_i.p.data; + l1_mem_resp_read.mem_resp_r_last = 1'b1; + end + end + + // Response ready back to the interco: HPDcache mem-resp ready for the matching + // channel. + assign l2_rsp_ready_o = l2_rsp_i.p.write ? l1_mem_resp_write_ready + : l1_mem_resp_read_ready; + + /////////////////////////// + // L1 -> L2 request merge // + /////////////////////////// + assign l1_mem_req_write_both_valid = l1_mem_req_write_valid && l1_mem_req_write_data_valid; + + rr_arb_tree #( + .NumIn (2), + .DataType (hpdcache_mem_req_t), + .AxiVldRdy (1'b1) + ) i_l1_l2_req_rr_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .rr_i (1'b1), + .req_i ({l1_mem_req_read_valid, l1_mem_req_write_both_valid}), + .gnt_o ({l1_mem_req_read_ready, __l1_mem_req_write_ready}), + .data_i ({l1_mem_req_read, l1_mem_req_write}), + .req_o (l1_l2_req_valid), + .gnt_i (l2_rsp_i.q_ready), + .data_o (l1_l2_req), + .idx_o () + ); + + assign l1_mem_req_write_ready = __l1_mem_req_write_ready & l1_mem_req_write_both_valid; + assign l1_mem_req_write_data_ready = __l1_mem_req_write_ready & l1_mem_req_write_both_valid; + + // Downstream request metadata. The full HPDcache mem id rides in req_id and is + // trusted to round-trip; the tile offsets it by core_id for uniqueness across + // its private caches (undone on the response). core_id/tile_id tagged at tile. + always_comb begin : req_meta + l1_l2_req_meta = '0; + l1_l2_req_meta.is_amo = (l1_l2_req.mem_req_command == HPDCACHE_MEM_ATOMIC); + l1_l2_req_meta.is_fpu = l1_l2_req.mem_req_id[HPDcacheCfg.u.memIdWidth-1]; + l1_l2_req_meta.req_id = l1_l2_req.mem_req_id; + l1_l2_req_meta.core_id = '0; + l1_l2_req_meta.tile_id = '0; + end + + always_comb begin : l2_req_drive + l2_req_o = '0; + l2_req_o.q.addr = l1_l2_req.mem_req_addr; + l2_req_o.q.write = (l1_l2_req.mem_req_command == HPDCACHE_MEM_WRITE); + l2_req_o.q.amo = AMONone; + l2_req_o.q.data = l1_mem_req_write_data.mem_req_w_data; + l2_req_o.q.strb = l1_mem_req_write_data.mem_req_w_be; + l2_req_o.q.user = l1_l2_req_meta; + l2_req_o.q_valid = l1_l2_req_valid; + end + + ////////////// + // L1 CACHE // + ////////////// + for (genvar i = 0; i < int'(HPDcacheCfg.u.nRequesters); i++) begin : gen_pma + assign dummy_pma[i].uncacheable = 1'b0; + assign dummy_pma[i].io = 1'b0; + assign dummy_pma[i].wr_policy_hint = HPDCACHE_WR_POLICY_WT; + assign core_req_abort[i] = 1'b0; // phys-indexed: never abort + assign core_req_tag[i] = '0; // phys-indexed: tag in req + end + + hpdcache #( + .HPDcacheCfg (HPDcacheCfg), + .wbuf_timecnt_t (wbuf_timecnt_t), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_data_word_t (hpdcache_data_word_t), + .hpdcache_data_be_t (hpdcache_data_be_t), + .hpdcache_req_offset_t(hpdcache_req_offset_t), + .hpdcache_req_data_t (hpdcache_req_data_t), + .hpdcache_req_be_t (hpdcache_req_be_t), + .hpdcache_req_sid_t (hpdcache_req_sid_t), + .hpdcache_req_tid_t (hpdcache_req_tid_t), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t), + .hpdcache_mem_addr_t (hpdcache_mem_addr_t), + .hpdcache_mem_id_t (hpdcache_mem_id_t), + .hpdcache_mem_data_t (hpdcache_mem_data_t), + .hpdcache_mem_be_t (hpdcache_mem_be_t), + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), + .hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t), + .hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t) + ) i_l1_hpdcache ( + .clk_i (clk_i), + .rst_ni(rst_ni), + .wbuf_flush_i(wbuf_flush_i), + + .core_req_valid_i(l1_req_valid), + .core_req_ready_o(l1_req_ready), + .core_req_i (l1_req), + .core_req_abort_i(core_req_abort), + .core_req_tag_i (core_req_tag), + .core_req_pma_i (dummy_pma), + .core_rsp_valid_o(l1_rsp_valid), + .core_rsp_o (l1_rsp), + + // Read memory interface + .mem_req_read_ready_i (l1_mem_req_read_ready), + .mem_req_read_valid_o (l1_mem_req_read_valid), + .mem_req_read_o (l1_mem_req_read), + .mem_resp_read_ready_o(l1_mem_resp_read_ready), + .mem_resp_read_valid_i(l1_mem_resp_read_valid), + .mem_resp_read_i (l1_mem_resp_read), + .mem_resp_read_inval_i (1'b0), + .mem_resp_read_inval_nline_i('0), + + // Write memory interface + .mem_req_write_ready_i (l1_mem_req_write_ready), + .mem_req_write_valid_o (l1_mem_req_write_valid), + .mem_req_write_o (l1_mem_req_write), + .mem_req_write_data_ready_i(l1_mem_req_write_data_ready), + .mem_req_write_data_valid_o(l1_mem_req_write_data_valid), + .mem_req_write_data_o (l1_mem_req_write_data), + .mem_resp_write_ready_o (l1_mem_resp_write_ready), + .mem_resp_write_valid_i (l1_mem_resp_write_valid), + .mem_resp_write_i (l1_mem_resp_write), + + // Performance events + .evt_cache_write_miss_o (evt_cache_write_miss_o), + .evt_cache_read_miss_o (evt_cache_read_miss_o), + .evt_cache_dir_unc_err_o(evt_cache_dir_unc_err_o), + .evt_cache_dir_cor_err_o(evt_cache_dir_cor_err_o), + .evt_cache_dat_unc_err_o(evt_cache_dat_unc_err_o), + .evt_cache_dat_cor_err_o(evt_cache_dat_cor_err_o), + .evt_scrub_complete_o (evt_scrub_complete_o), + .evt_uncached_req_o (evt_uncached_req_o), + .evt_cmo_req_o (evt_cmo_req_o), + .evt_write_req_o (evt_write_req_o), + .evt_read_req_o (evt_read_req_o), + .evt_prefetch_req_o (evt_prefetch_req_o), + .evt_req_on_hold_o (evt_req_on_hold_o), + .evt_rtab_rollback_o (evt_rtab_rollback_o), + .evt_stall_refill_o (evt_stall_refill_o), + .evt_stall_o (evt_stall_o), + + // Status + .wbuf_empty_o(wbuf_empty_o), + + // Configuration + .cfg_enable_i (cfg_enable_i), + .cfg_wbuf_threshold_i (cfg_wbuf_threshold_i), + .cfg_wbuf_reset_timecnt_on_write_i (cfg_wbuf_reset_timecnt_on_write_i), + .cfg_wbuf_sequential_waw_i (cfg_wbuf_sequential_waw_i), + .cfg_wbuf_inhibit_write_coalescing_i(cfg_wbuf_inhibit_write_coalescing_i), + .cfg_prefetch_updt_plru_i (cfg_prefetch_updt_plru_i), + .cfg_error_on_cacheable_amo_i (cfg_error_on_cacheable_amo_i), + .cfg_rtab_single_entry_i (cfg_rtab_single_entry_i), + .cfg_default_wb_i (cfg_default_wb_i), + .cfg_scrub_enable_i (cfg_scrub_enable_i), + .cfg_scrub_period_i (cfg_scrub_period_i), + .cfg_scrub_restart_i (cfg_scrub_restart_i) + ); + + //////////////////////// + // tid pack functions // + //////////////////////// + function automatic hpdcache_req_tid_t pack_tid_snitch( + input word_offset_t word_offset, + input logic is_fpu, + input logic [CoreIDWidth-1:0] core_id, + input logic write, + input reqid_t req_id); + pack_tid_snitch = '0; + pack_tid_snitch[ReqIdLsb +: ReqIdW] = req_id; + pack_tid_snitch[WritePos] = write; + pack_tid_snitch[CoreIdLsb +: CoreIDWidth] = core_id; + pack_tid_snitch[IsFpuPos] = is_fpu; + pack_tid_snitch[WordOffLsb +: LP1NumWordOffsetBits] = word_offset; + endfunction + + function automatic hpdcache_req_tid_t pack_tid_spatz( + input logic [HitmapW-1:0] hitmap, + input logic [OfstsW-1:0] ofsts, + input logic is_fpu, + input logic [CoreIDWidth-1:0] core_id, + input logic write, + input reqid_t req_id); + pack_tid_spatz = '0; + pack_tid_spatz[HitmapLsb +: HitmapW] = hitmap; + pack_tid_spatz[OfstsLsb +: OfstsW] = ofsts; + pack_tid_spatz[ReqIdLsb +: ReqIdW] = req_id; + pack_tid_spatz[WritePos] = write; + pack_tid_spatz[CoreIdLsb +: CoreIDWidth] = core_id; + pack_tid_spatz[IsFpuPos] = is_fpu; + endfunction + +endmodule From 1471b1a563d218a67db1d3898dea612e4340b14c Mon Sep 17 00:00:00 2001 From: "msc25h24 Ho Tin Hung (hohung)" Date: Tue, 16 Jun 2026 17:26:47 +0200 Subject: [PATCH 03/39] [HW] init L1 private cache controller --- hardware/src/cachepool_l1_ctrl.sv | 707 ++++++++++++++++++++++++++++++ 1 file changed, 707 insertions(+) create mode 100644 hardware/src/cachepool_l1_ctrl.sv diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv new file mode 100644 index 0000000..bb19554 --- /dev/null +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -0,0 +1,707 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Ho Tin Hung +// +// Per-core private L1 data cache controller. +// +// Core side is a plain TCDM interface: NrTCDMPortsPerCore request/response +// streams (the Spatz lanes + one Snitch port). Inside, this module: +// * coalesces the Spatz lanes into one wide HPDcache request (sid=0), +// * translates the Snitch port into one HPDcache request (sid=1), +// * packs all metadata that must survive the HPDcache round-trip into `tid`, +// * runs one HPDcache (write-through, no coherence) as the private L1, +// * merges HPDcache's mem read/write channels into one downstream TCDM pair +// (l2_req_o/l2_rsp_i) that feeds the shared distributed L2 through the +// existing tcdm_cache_interco, +// * scatters the response back to the originating lanes. +// +// No cache coherence is implemented here. Write-through narrows but does not +// close the cross-core shared-data window; that is accepted for now. +// +// Coalescer metadata has no package; all coalescer-facing types (tcdm_meta_t, +// downstream_info_t, word_offset_t, ...) are defined at the tile and passed in +// as parameters. + +module cachepool_l1_ctrl + import cachepool_pkg::*; + import hpdcache_pkg::*; + import reqrsp_pkg::*; +#( + // Core-side topology + parameter int unsigned NrTCDMPortsPerCore = 5, // Spatz lanes + 1 Snitch + parameter int unsigned DataWidth = 32, // narrow (per-lane) data width + parameter int unsigned ByteWidth = 8, + + // tid / coalescer geometry (must match the types below) + parameter int unsigned LP1NumWordOffsetBits = 2, // $clog2(wordWidth/DataWidth) + parameter int unsigned LP1NrBitsCoalOffset = 2, // bits per coalescer ofst entry + // (lane count is NrLP1CoalInputs, derived below) + + parameter hpdcache_cfg_t HPDcacheCfg = '0, + parameter type wbuf_timecnt_t = logic, + + // Core-side TCDM request/response + parameter type l1_cache_req_t = logic, + parameter type l1_cache_rsp_t = logic, + + // Coalescer payload types (defined at tile) + parameter type tcdm_meta_t = logic, // { tcdm_user_t user; logic write; hpdcache_req_op_t amo; } + parameter type downstream_info_t = logic, // par_coalescer_top downstream info struct + parameter type word_offset_t = logic, // logic[LP1NumWordOffsetBits-1:0] + + // Downstream (L2) TCDM request/response + parameter type l2_cache_req_t = logic, + parameter type l2_cache_rsp_t = logic, + + // HPDcache request interface types + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_data_word_t = logic, + parameter type hpdcache_data_be_t = logic, + parameter type hpdcache_req_offset_t = logic, + parameter type hpdcache_req_data_t = logic, + parameter type hpdcache_req_be_t = logic, + parameter type hpdcache_req_sid_t = logic, + parameter type hpdcache_req_tid_t = logic, + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic, + + // HPDcache memory interface types + parameter type hpdcache_mem_addr_t = logic, + parameter type hpdcache_mem_id_t = logic, + parameter type hpdcache_mem_data_t = logic, + parameter type hpdcache_mem_be_t = logic, + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_req_w_t = logic, + parameter type hpdcache_mem_resp_r_t = logic, + parameter type hpdcache_mem_resp_w_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic wbuf_flush_i, + + // Core-side TCDM interface (Spatz lanes [0..NrLP1CoalInputs-1] + Snitch [last]). + // Request handshake : core_req_i.q_valid / core_req_ready_o + // Response handshake: core_rsp_o.p_valid / core_rsp_ready_i + input l1_cache_req_t [NrTCDMPortsPerCore-1:0] core_req_i, + output l1_cache_rsp_t [NrTCDMPortsPerCore-1:0] core_rsp_o, + output logic [NrTCDMPortsPerCore-1:0] core_req_ready_o, + input logic [NrTCDMPortsPerCore-1:0] core_rsp_ready_i, + + // Downstream (L2) TCDM interface + output l2_cache_req_t l2_req_o, + input l2_cache_rsp_t l2_rsp_i, + output logic l2_rsp_ready_o, // response ready -> interco core_rsp_ready_i + + // Performance events + output logic evt_cache_write_miss_o, + output logic evt_cache_read_miss_o, + output logic evt_cache_dir_unc_err_o, + output logic evt_cache_dir_cor_err_o, + output logic evt_cache_dat_unc_err_o, + output logic evt_cache_dat_cor_err_o, + output logic evt_scrub_complete_o, + output logic evt_uncached_req_o, + output logic evt_cmo_req_o, + output logic evt_write_req_o, + output logic evt_read_req_o, + output logic evt_prefetch_req_o, + output logic evt_req_on_hold_o, + output logic evt_rtab_rollback_o, + output logic evt_stall_refill_o, + output logic evt_stall_o, + + // Status interface + output logic wbuf_empty_o, + + // Configuration interface + input logic cfg_enable_i, + input wbuf_timecnt_t cfg_wbuf_threshold_i, + input logic cfg_wbuf_reset_timecnt_on_write_i, + input logic cfg_wbuf_sequential_waw_i, + input logic cfg_wbuf_inhibit_write_coalescing_i, + input logic cfg_prefetch_updt_plru_i, + input logic cfg_error_on_cacheable_amo_i, + input logic cfg_rtab_single_entry_i, + input logic cfg_default_wb_i, + input logic cfg_scrub_enable_i, + input logic [5:0] cfg_scrub_period_i, + input logic cfg_scrub_restart_i +); + + //////////////// + // PARAMETERS // + //////////////// + localparam int unsigned NrLP1CoalInputs = NrTCDMPortsPerCore - 1; // Spatz lanes + localparam int unsigned SnitchPort = NrTCDMPortsPerCore - 1; // last port + localparam int unsigned coalescedDataWidth = HPDcacheCfg.u.wordWidth; // wide word + localparam int unsigned LaneBytes = DataWidth / ByteWidth; // bytes per lane word + localparam int unsigned WordBytes = coalescedDataWidth / ByteWidth; + + // tid layout (one fixed, non-overlapping scheme), MSB -> LSB: + // { word_offset | is_fpu | core_id | write | req_id | ofsts | hitmap } + // Snitch path uses word_offset (ofsts/hitmap = 0); Spatz path uses ofsts/hitmap + // (word_offset = 0). The {is_fpu, core_id, write, req_id} block is at fixed + // positions for both. sid (0 Spatz / 1 Snitch) selects the unpack path. + localparam int unsigned ReqIdW = $bits(reqid_t); + localparam int unsigned HitmapW = NrLP1CoalInputs; + localparam int unsigned OfstsW = NrLP1CoalInputs * LP1NrBitsCoalOffset; + localparam int unsigned CoalInfoW = HitmapW + OfstsW; + localparam int unsigned TidUserW = CoreIDWidth + ReqIdW + 2; // {is_fpu,core_id,write,req_id} + localparam int unsigned HitmapLsb = 0; + localparam int unsigned OfstsLsb = HitmapW; + localparam int unsigned ReqIdLsb = CoalInfoW; + localparam int unsigned WritePos = CoalInfoW + ReqIdW; + localparam int unsigned CoreIdLsb = CoalInfoW + ReqIdW + 1; + localparam int unsigned IsFpuPos = CoalInfoW + ReqIdW + 1 + CoreIDWidth; + localparam int unsigned WordOffLsb = CoalInfoW + TidUserW; + + /////////////////// + // LOCAL SIGNALS // + /////////////////// + + // Per-port unpacked core request fields + logic [NrTCDMPortsPerCore-1:0] cache_req_valid; + logic [NrTCDMPortsPerCore-1:0] cache_req_ready; + hpdcache_req_offset_t [NrTCDMPortsPerCore-1:0] cache_req_addr_offset; + word_offset_t [NrTCDMPortsPerCore-1:0] cache_req_word_offset; + logic [NrTCDMPortsPerCore-1:0][CoreIDWidth-1:0] cache_req_coreid; + reqid_t [NrTCDMPortsPerCore-1:0] cache_req_reqid; + logic [NrTCDMPortsPerCore-1:0] cache_req_is_fpu; + logic [NrTCDMPortsPerCore-1:0] cache_req_write; + narrow_data_t [NrTCDMPortsPerCore-1:0] cache_req_data; + amo_op_e [NrTCDMPortsPerCore-1:0] cache_req_amo; + narrow_addr_t [NrTCDMPortsPerCore-1:0] cache_req_addr; + narrow_strb_t [NrTCDMPortsPerCore-1:0] cache_req_strb; + + // Per-port HPDcache request view + coalescer info payload + hpdcache_req_t [NrTCDMPortsPerCore-1:0] l1_cache_req; + tcdm_meta_t [NrTCDMPortsPerCore-1:0] cache_req_info; + + // Coalescer downstream request payload (Spatz path) + logic coal_req_valid; + logic coal_req_ready; + narrow_addr_t coal_req_addr; + downstream_info_t coal_req_info; + logic coal_req_write; + logic [coalescedDataWidth-1:0] coal_req_wdata; + logic [WordBytes-1:0] coal_req_wmask; + + // Coalescer upstream response (Spatz lanes) + logic [NrLP1CoalInputs-1:0] coal_resp_valid; + logic [NrLP1CoalInputs-1:0] coal_resp_ready; + logic [NrLP1CoalInputs-1:0] coal_resp_write; + narrow_data_t [NrLP1CoalInputs-1:0] coal_resp_data; + tcdm_meta_t [NrLP1CoalInputs-1:0] coal_resp_info; + + // Coalescer downstream response payload (reconstructed from the HPDcache rsp) + logic coal_resp_down_valid; + logic coal_resp_down_ready; + downstream_info_t coal_resp_down_info; + logic coal_resp_down_write; + + // HPDcache requester arrays (0 = Spatz, 1 = Snitch) + logic l1_req_valid [HPDcacheCfg.u.nRequesters]; + logic l1_req_ready [HPDcacheCfg.u.nRequesters]; + hpdcache_req_t l1_req [HPDcacheCfg.u.nRequesters]; + logic l1_rsp_valid [HPDcacheCfg.u.nRequesters]; + hpdcache_rsp_t l1_rsp [HPDcacheCfg.u.nRequesters]; + logic core_req_abort [HPDcacheCfg.u.nRequesters]; + hpdcache_tag_t core_req_tag [HPDcacheCfg.u.nRequesters]; + hpdcache_pma_t dummy_pma [HPDcacheCfg.u.nRequesters]; + + // HPDcache <-> L2 mem channels + hpdcache_mem_req_t l1_mem_req_read, l1_mem_req_write, l1_l2_req; + hpdcache_mem_req_w_t l1_mem_req_write_data; + logic l1_mem_req_read_valid, l1_mem_req_read_ready; + logic l1_mem_req_write_valid, l1_mem_req_write_ready, __l1_mem_req_write_ready; + logic l1_mem_req_write_data_valid, l1_mem_req_write_data_ready; + logic l1_mem_req_write_both_valid; + logic l1_l2_req_valid; + tcdm_user_t l1_l2_req_meta; + + hpdcache_mem_resp_r_t l1_mem_resp_read; + hpdcache_mem_resp_w_t l1_mem_resp_write; + logic l1_mem_resp_read_valid, l1_mem_resp_read_ready; + logic l1_mem_resp_write_valid, l1_mem_resp_write_ready; + + /////////////////////////////// + // Core request unpacking // + /////////////////////////////// + for (genvar i = 0; i < NrTCDMPortsPerCore; i++) begin : gen_req_unpack + // Request grant on the explicit handshake port. + assign core_req_ready_o[i] = cache_req_ready[i]; + assign cache_req_valid[i] = core_req_i[i].q_valid; + assign cache_req_addr_offset[i] = core_req_i[i].q.addr[HPDcacheCfg.reqOffsetWidth-1:0]; + assign cache_req_word_offset[i] = core_req_i[i].q.addr[$clog2(DataWidth/ByteWidth) +: LP1NumWordOffsetBits]; + assign cache_req_coreid[i] = core_req_i[i].q.user.core_id; + assign cache_req_reqid[i] = core_req_i[i].q.user.req_id; + assign cache_req_is_fpu[i] = core_req_i[i].q.user.is_fpu; + assign cache_req_write[i] = core_req_i[i].q.write; + assign cache_req_data[i] = core_req_i[i].q.data; + assign cache_req_amo[i] = core_req_i[i].q.amo; + assign cache_req_addr[i] = core_req_i[i].q.addr; + assign cache_req_strb[i] = core_req_i[i].q.strb; + end + + /////////////////////////////// + // Per-port HPDcache req view // + /////////////////////////////// + for (genvar i = 0; i < NrTCDMPortsPerCore; i++) begin : gen_req_view + assign l1_cache_req[i].addr_offset = cache_req_addr_offset[i]; + assign l1_cache_req[i].wdata = cache_req_data[i]; + assign l1_cache_req[i].be = cache_req_strb[i]; + assign l1_cache_req[i].size = hpdcache_req_size_t'($clog2(coalescedDataWidth/8)); + assign l1_cache_req[i].sid = hpdcache_req_sid_t'(!cache_req_is_fpu[i]); // 0 Spatz / 1 Snitch + assign l1_cache_req[i].need_rsp = 1'b1; + assign l1_cache_req[i].phys_indexed = 1'b1; + assign l1_cache_req[i].addr_tag = cache_req_addr[i][HPDcacheCfg.reqOffsetWidth +: HPDcacheCfg.tagWidth]; + assign l1_cache_req[i].pma.uncacheable = 1'b0; + assign l1_cache_req[i].pma.io = 1'b0; + assign l1_cache_req[i].pma.wr_policy_hint = HPDCACHE_WR_POLICY_WT; + // Snitch-path tid (per-port). Spatz lanes get their tid rebuilt post-coalesce. + assign l1_cache_req[i].tid = pack_tid_snitch(cache_req_word_offset[i], + cache_req_is_fpu[i], + cache_req_coreid[i], + cache_req_write[i], + cache_req_reqid[i]); + + // Op map (loads/stores/AMOs). AMOs flow through HPDcache in phase 1. + always_comb begin : gen_op + if (cache_req_amo[i] == AMONone) begin + l1_cache_req[i].op = cache_req_write[i] ? HPDCACHE_REQ_STORE : HPDCACHE_REQ_LOAD; + end else begin + unique case (cache_req_amo[i]) + AMOSwap: l1_cache_req[i].op = HPDCACHE_REQ_AMO_SWAP; + AMOAdd: l1_cache_req[i].op = HPDCACHE_REQ_AMO_ADD; + AMOAnd: l1_cache_req[i].op = HPDCACHE_REQ_AMO_AND; + AMOOr: l1_cache_req[i].op = HPDCACHE_REQ_AMO_OR; + AMOXor: l1_cache_req[i].op = HPDCACHE_REQ_AMO_XOR; + AMOMax: l1_cache_req[i].op = HPDCACHE_REQ_AMO_MAX; + AMOMaxu: l1_cache_req[i].op = HPDCACHE_REQ_AMO_MAXU; + AMOMin: l1_cache_req[i].op = HPDCACHE_REQ_AMO_MIN; + AMOMinu: l1_cache_req[i].op = HPDCACHE_REQ_AMO_MINU; + AMOLR: l1_cache_req[i].op = HPDCACHE_REQ_AMO_LR; + AMOSC: l1_cache_req[i].op = HPDCACHE_REQ_AMO_SC; + default: l1_cache_req[i].op = HPDCACHE_REQ_LOAD; + endcase + end + end + + // Coalescer info payload (carried per lane, returned with the response). + assign cache_req_info[i].user.core_id = cache_req_coreid[i]; + assign cache_req_info[i].user.tile_id = '0; // tagged at tile level + assign cache_req_info[i].user.is_amo = (cache_req_amo[i] != AMONone); + assign cache_req_info[i].user.req_id = cache_req_reqid[i]; + assign cache_req_info[i].user.is_fpu = cache_req_is_fpu[i]; + assign cache_req_info[i].write = cache_req_write[i]; + assign cache_req_info[i].amo = l1_cache_req[i].op; + end + + ////////////////////////// + // Spatz req coalescing // + ////////////////////////// + par_coalescer_top #( + .ReqAddrWidth (L1AddrWidth), + .NumPorts (NrLP1CoalInputs), + .info_t (tcdm_meta_t), + .UpstreamDataWidth (DataWidth), + .DownstreamDataWidth (coalescedDataWidth), + .ByteWidth (ByteWidth) + ) i_l1_req_coalescer ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .id_i ('0), + + .upstream_req_valid_i (cache_req_valid[NrLP1CoalInputs-1:0]), + .upstream_req_ready_o (cache_req_ready[NrLP1CoalInputs-1:0]), + .upstream_req_addr_i (cache_req_addr[NrLP1CoalInputs-1:0]), + .upstream_req_info_i (cache_req_info[NrLP1CoalInputs-1:0]), + .upstream_req_write_i (cache_req_write[NrLP1CoalInputs-1:0]), + .upstream_req_wdata_i (cache_req_data[NrLP1CoalInputs-1:0]), + .upstream_req_wstrb_i (cache_req_strb[NrLP1CoalInputs-1:0]), + + .upstream_resp_valid_o (coal_resp_valid), + .upstream_resp_ready_i (coal_resp_ready), + .upstream_resp_write_o (coal_resp_write), + .upstream_resp_data_o (coal_resp_data), + .upstream_resp_info_o (coal_resp_info), + + .downstream_req_valid_o (coal_req_valid), + .downstream_req_ready_i (coal_req_ready), + .downstream_req_addr_o (coal_req_addr), + .downstream_req_info_o (coal_req_info), + .downstream_req_write_o (coal_req_write), + .downstream_req_wdata_o (coal_req_wdata), + .downstream_req_wmask_o (coal_req_wmask), + + .downstream_resp_valid_i (coal_resp_down_valid), + .downstream_resp_ready_o (coal_resp_down_ready), + .downstream_resp_data_i (l1_rsp[0].rdata), + .downstream_resp_info_i (coal_resp_down_info), + .downstream_resp_write_i (coal_resp_down_write) + ); + + ////////////////////////////////////// + // HPDcache requester 0 (Spatz/coal) // + ////////////////////////////////////// + // Shared user for the coalesced request: all coalesced lanes belong to one + // Spatz instruction (same core/req_id), so any hit lane's user is the shared + // one. Pick the first hit lane. + logic coal_hit; + tcdm_meta_t coal_meta; + always_comb begin : gen_coal_shared_meta + coal_hit = 1'b0; + coal_meta = '0; + for (int unsigned id = 0; id < NrLP1CoalInputs; id++) begin + if (coal_req_info.hitmap[id] && !coal_hit) begin + coal_hit = 1'b1; + coal_meta = coal_req_info.infos[id]; + end + end + end + + // BE for the coalesced (wide) request. + // NOTE: preserved hitmap-shift scheme (each hit lane marks its lane-width bytes + // at its lane index) rather than the coalescer's wmask, per design intent. + // Revisit with owner before switching to coal_req_wmask. + logic [WordBytes-1:0] coal_be; + always_comb begin : gen_coal_be + coal_be = '0; + for (int unsigned id = 0; id < NrLP1CoalInputs; id++) begin + if (coal_req_info.hitmap[id]) begin + coal_be |= ({LaneBytes{1'b1}} << (id * LaneBytes)); + end + end + end + + always_comb begin : gen_l1_req_spatz + l1_req[0] = '0; + l1_req[0].addr_offset = coal_req_addr[HPDcacheCfg.reqOffsetWidth-1:0]; + l1_req[0].addr_tag = coal_req_addr[HPDcacheCfg.reqOffsetWidth +: HPDcacheCfg.tagWidth]; + l1_req[0].wdata = coal_req_wdata; + l1_req[0].be = coal_be; + l1_req[0].size = hpdcache_req_size_t'($clog2(coalescedDataWidth/8)); + l1_req[0].sid = hpdcache_req_sid_t'(0); // Spatz + l1_req[0].need_rsp = 1'b1; + l1_req[0].phys_indexed = 1'b1; + l1_req[0].pma.uncacheable = 1'b0; + l1_req[0].pma.io = 1'b0; + l1_req[0].pma.wr_policy_hint = HPDCACHE_WR_POLICY_WT; + // op: AMOs are never coalesced; for an AMO carry the hit lane's op. + l1_req[0].op = coal_meta.user.is_amo ? coal_meta.amo + : (coal_req_write ? HPDCACHE_REQ_STORE : HPDCACHE_REQ_LOAD); + // tid: pack the coalescer scatter info + shared user. + l1_req[0].tid = coal_req_valid + ? pack_tid_spatz(coal_req_info.hitmap, coal_req_info.ofsts, + coal_meta.user.is_fpu, coal_meta.user.core_id, + coal_req_write, coal_meta.user.req_id) + : '0; + end + + assign l1_req_valid[0] = coal_req_valid; + assign coal_req_ready = l1_req_ready[0]; + + /////////////////////////////////// + // HPDcache requester 1 (Snitch) // + /////////////////////////////////// + // Snitch writes its narrow word into the wide cache word at its byte position. + logic [$clog2(WordBytes)-1:0] sn_byte_pos; + assign sn_byte_pos = l1_cache_req[SnitchPort].addr_offset % WordBytes; + + always_comb begin : gen_l1_req_snitch + l1_req[1] = l1_cache_req[SnitchPort]; + l1_req[1].sid = hpdcache_req_sid_t'(1); // Snitch + l1_req[1].wdata = hpdcache_req_data_t'(cache_req_data[SnitchPort]) << (sn_byte_pos * ByteWidth); + l1_req[1].be = hpdcache_req_be_t'(cache_req_strb[SnitchPort]) << sn_byte_pos; + l1_req[1].tid = core_req_i[SnitchPort].q_valid ? l1_cache_req[SnitchPort].tid : '0; + end + + assign l1_req_valid[1] = core_req_i[SnitchPort].q_valid; + assign cache_req_ready[SnitchPort] = l1_req_ready[1]; + + /////////////////////////////// + // Spatz response scatter // + /////////////////////////////// + // Rebuild the coalescer downstream response info from the round-tripped tid + // (requester 0), then feed the coalescer so it scatters to the Spatz lanes. + tcdm_user_t coal_resp_user; + always_comb begin : gen_coal_resp_info + coal_resp_down_info = '0; + coal_resp_down_info.hitmap = l1_rsp[0].tid[HitmapLsb +: HitmapW]; + coal_resp_down_info.ofsts = l1_rsp[0].tid[OfstsLsb +: OfstsW]; + + coal_resp_user = '0; + coal_resp_user.is_fpu = l1_rsp[0].tid[IsFpuPos]; + coal_resp_user.core_id = l1_rsp[0].tid[CoreIdLsb +: CoreIDWidth]; + coal_resp_user.req_id = l1_rsp[0].tid[ReqIdLsb +: ReqIdW]; + coal_resp_user.is_amo = 1'b0; + + // All coalesced lanes share the same user (one Spatz instruction). + for (int unsigned j = 0; j < NrLP1CoalInputs; j++) begin + coal_resp_down_info.infos[j].user = coal_resp_user; + coal_resp_down_info.infos[j].write = l1_rsp[0].tid[WritePos]; + coal_resp_down_info.infos[j].amo = HPDCACHE_REQ_LOAD; + end + end + + assign coal_resp_down_valid = l1_rsp_valid[0]; + assign coal_resp_down_write = l1_rsp[0].tid[WritePos]; + + // Coalescer upstream responses -> Spatz lane TCDM responses. The core's + // per-lane response ready drains the coalescer's resp FIFOs (which absorb the + // un-back-pressurable HPDcache core response). + for (genvar i = 0; i < NrLP1CoalInputs; i++) begin : gen_spatz_resp + assign core_rsp_o[i].q_ready = cache_req_ready[i]; // request grant (also on core_req_ready_o) + assign coal_resp_ready[i] = core_rsp_ready_i[i]; + assign core_rsp_o[i].p_valid = coal_resp_valid[i]; + assign core_rsp_o[i].p.data = coal_resp_data[i]; + assign core_rsp_o[i].p.user = coal_resp_info[i].user; + assign core_rsp_o[i].p.write = coal_resp_write[i]; + end + + /////////////////////////////// + // Snitch response (bypass) // + /////////////////////////////// + // NOTE: HPDcache's core response is not back-pressurable, so core_rsp_ready_i + // [SnitchPort] cannot stall it. Snitch is scalar with a single outstanding load + // and is assumed always ready; add a spill here if that ever changes. + logic [$clog2(coalescedDataWidth)-1:0] sn_bit_offset; + assign sn_bit_offset = l1_rsp[1].tid[WordOffLsb +: LP1NumWordOffsetBits] * DataWidth; + + always_comb begin : gen_snitch_resp + core_rsp_o[SnitchPort] = '0; + core_rsp_o[SnitchPort].p_valid = l1_rsp_valid[1]; + core_rsp_o[SnitchPort].q_ready = cache_req_ready[SnitchPort]; + core_rsp_o[SnitchPort].p.data = l1_rsp[1].rdata[0][sn_bit_offset +: DataWidth]; + core_rsp_o[SnitchPort].p.user.is_fpu = l1_rsp[1].tid[IsFpuPos]; + core_rsp_o[SnitchPort].p.user.core_id = l1_rsp[1].tid[CoreIdLsb +: CoreIDWidth]; + core_rsp_o[SnitchPort].p.user.req_id = l1_rsp[1].tid[ReqIdLsb +: ReqIdW]; + core_rsp_o[SnitchPort].p.user.is_amo = 1'b0; + core_rsp_o[SnitchPort].p.user.tile_id = '0; + core_rsp_o[SnitchPort].p.write = l1_rsp[1].tid[WritePos]; + end + + //////////////////////// + // L2 -> L1 response // + //////////////////////// + // The L2 response valid/ready handshake is (l2_rsp_i.p_valid / l2_rsp_ready_o); + // the ready rides on a separate wire (the interco's core_rsp_ready_i), not in + // tcdm_rsp_t (whose q_ready is the request grant). HPDcache's mem_resp_*_ready + // drives it, so refills/write-acks are properly back-pressured. Read/write + // responses are distinguished by p.write and steered to the matching HPDcache + // mem channel. The original HPDcache mem id is recovered by removing the + // per-core offset the tile added (req_id - core_id); the L1 controller is + // core-private and core_id-agnostic. + always_comb begin : rsp_translation + l1_mem_resp_read_valid = 1'b0; + l1_mem_resp_write_valid = 1'b0; + l1_mem_resp_read = '0; + l1_mem_resp_write = '0; + + if (l2_rsp_i.p.write) begin + l1_mem_resp_write_valid = l2_rsp_i.p_valid; + l1_mem_resp_write.mem_resp_w_is_atomic = l2_rsp_i.p.user.is_amo; + l1_mem_resp_write.mem_resp_w_error = HPDCACHE_MEM_RESP_OK; + l1_mem_resp_write.mem_resp_w_id = l2_rsp_i.p.user.req_id - l2_rsp_i.p.user.core_id; + end else begin + l1_mem_resp_read_valid = l2_rsp_i.p_valid; + l1_mem_resp_read.mem_resp_r_error = HPDCACHE_MEM_RESP_OK; + l1_mem_resp_read.mem_resp_r_id = l2_rsp_i.p.user.req_id - l2_rsp_i.p.user.core_id; + l1_mem_resp_read.mem_resp_r_data = l2_rsp_i.p.data; + l1_mem_resp_read.mem_resp_r_last = 1'b1; + end + end + + // Response ready back to the interco: HPDcache mem-resp ready for the matching + // channel. + assign l2_rsp_ready_o = l2_rsp_i.p.write ? l1_mem_resp_write_ready + : l1_mem_resp_read_ready; + + /////////////////////////// + // L1 -> L2 request merge // + /////////////////////////// + assign l1_mem_req_write_both_valid = l1_mem_req_write_valid && l1_mem_req_write_data_valid; + + rr_arb_tree #( + .NumIn (2), + .DataType (hpdcache_mem_req_t), + .AxiVldRdy (1'b1) + ) i_l1_l2_req_rr_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .rr_i (1'b1), + .req_i ({l1_mem_req_read_valid, l1_mem_req_write_both_valid}), + .gnt_o ({l1_mem_req_read_ready, __l1_mem_req_write_ready}), + .data_i ({l1_mem_req_read, l1_mem_req_write}), + .req_o (l1_l2_req_valid), + .gnt_i (l2_rsp_i.q_ready), + .data_o (l1_l2_req), + .idx_o () + ); + + assign l1_mem_req_write_ready = __l1_mem_req_write_ready & l1_mem_req_write_both_valid; + assign l1_mem_req_write_data_ready = __l1_mem_req_write_ready & l1_mem_req_write_both_valid; + + // Downstream request metadata. The full HPDcache mem id rides in req_id and is + // trusted to round-trip; the tile offsets it by core_id for uniqueness across + // its private caches (undone on the response). core_id/tile_id tagged at tile. + always_comb begin : req_meta + l1_l2_req_meta = '0; + l1_l2_req_meta.is_amo = (l1_l2_req.mem_req_command == HPDCACHE_MEM_ATOMIC); + l1_l2_req_meta.is_fpu = l1_l2_req.mem_req_id[HPDcacheCfg.u.memIdWidth-1]; + l1_l2_req_meta.req_id = l1_l2_req.mem_req_id; + l1_l2_req_meta.core_id = '0; + l1_l2_req_meta.tile_id = '0; + end + + always_comb begin : l2_req_drive + l2_req_o = '0; + l2_req_o.q.addr = l1_l2_req.mem_req_addr; + l2_req_o.q.write = (l1_l2_req.mem_req_command == HPDCACHE_MEM_WRITE); + l2_req_o.q.amo = AMONone; + l2_req_o.q.data = l1_mem_req_write_data.mem_req_w_data; + l2_req_o.q.strb = l1_mem_req_write_data.mem_req_w_be; + l2_req_o.q.user = l1_l2_req_meta; + l2_req_o.q_valid = l1_l2_req_valid; + end + + ////////////// + // L1 CACHE // + ////////////// + for (genvar i = 0; i < int'(HPDcacheCfg.u.nRequesters); i++) begin : gen_pma + assign dummy_pma[i].uncacheable = 1'b0; + assign dummy_pma[i].io = 1'b0; + assign dummy_pma[i].wr_policy_hint = HPDCACHE_WR_POLICY_WT; + assign core_req_abort[i] = 1'b0; // phys-indexed: never abort + assign core_req_tag[i] = '0; // phys-indexed: tag in req + end + + hpdcache #( + .HPDcacheCfg (HPDcacheCfg), + .wbuf_timecnt_t (wbuf_timecnt_t), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_data_word_t (hpdcache_data_word_t), + .hpdcache_data_be_t (hpdcache_data_be_t), + .hpdcache_req_offset_t(hpdcache_req_offset_t), + .hpdcache_req_data_t (hpdcache_req_data_t), + .hpdcache_req_be_t (hpdcache_req_be_t), + .hpdcache_req_sid_t (hpdcache_req_sid_t), + .hpdcache_req_tid_t (hpdcache_req_tid_t), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t), + .hpdcache_mem_addr_t (hpdcache_mem_addr_t), + .hpdcache_mem_id_t (hpdcache_mem_id_t), + .hpdcache_mem_data_t (hpdcache_mem_data_t), + .hpdcache_mem_be_t (hpdcache_mem_be_t), + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), + .hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t), + .hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t) + ) i_l1_hpdcache ( + .clk_i (clk_i), + .rst_ni(rst_ni), + .wbuf_flush_i(wbuf_flush_i), + + .core_req_valid_i(l1_req_valid), + .core_req_ready_o(l1_req_ready), + .core_req_i (l1_req), + .core_req_abort_i(core_req_abort), + .core_req_tag_i (core_req_tag), + .core_req_pma_i (dummy_pma), + .core_rsp_valid_o(l1_rsp_valid), + .core_rsp_o (l1_rsp), + + // Read memory interface + .mem_req_read_ready_i (l1_mem_req_read_ready), + .mem_req_read_valid_o (l1_mem_req_read_valid), + .mem_req_read_o (l1_mem_req_read), + .mem_resp_read_ready_o(l1_mem_resp_read_ready), + .mem_resp_read_valid_i(l1_mem_resp_read_valid), + .mem_resp_read_i (l1_mem_resp_read), + .mem_resp_read_inval_i (1'b0), + .mem_resp_read_inval_nline_i('0), + + // Write memory interface + .mem_req_write_ready_i (l1_mem_req_write_ready), + .mem_req_write_valid_o (l1_mem_req_write_valid), + .mem_req_write_o (l1_mem_req_write), + .mem_req_write_data_ready_i(l1_mem_req_write_data_ready), + .mem_req_write_data_valid_o(l1_mem_req_write_data_valid), + .mem_req_write_data_o (l1_mem_req_write_data), + .mem_resp_write_ready_o (l1_mem_resp_write_ready), + .mem_resp_write_valid_i (l1_mem_resp_write_valid), + .mem_resp_write_i (l1_mem_resp_write), + + // Performance events + .evt_cache_write_miss_o (evt_cache_write_miss_o), + .evt_cache_read_miss_o (evt_cache_read_miss_o), + .evt_cache_dir_unc_err_o(evt_cache_dir_unc_err_o), + .evt_cache_dir_cor_err_o(evt_cache_dir_cor_err_o), + .evt_cache_dat_unc_err_o(evt_cache_dat_unc_err_o), + .evt_cache_dat_cor_err_o(evt_cache_dat_cor_err_o), + .evt_scrub_complete_o (evt_scrub_complete_o), + .evt_uncached_req_o (evt_uncached_req_o), + .evt_cmo_req_o (evt_cmo_req_o), + .evt_write_req_o (evt_write_req_o), + .evt_read_req_o (evt_read_req_o), + .evt_prefetch_req_o (evt_prefetch_req_o), + .evt_req_on_hold_o (evt_req_on_hold_o), + .evt_rtab_rollback_o (evt_rtab_rollback_o), + .evt_stall_refill_o (evt_stall_refill_o), + .evt_stall_o (evt_stall_o), + + // Status + .wbuf_empty_o(wbuf_empty_o), + + // Configuration + .cfg_enable_i (cfg_enable_i), + .cfg_wbuf_threshold_i (cfg_wbuf_threshold_i), + .cfg_wbuf_reset_timecnt_on_write_i (cfg_wbuf_reset_timecnt_on_write_i), + .cfg_wbuf_sequential_waw_i (cfg_wbuf_sequential_waw_i), + .cfg_wbuf_inhibit_write_coalescing_i(cfg_wbuf_inhibit_write_coalescing_i), + .cfg_prefetch_updt_plru_i (cfg_prefetch_updt_plru_i), + .cfg_error_on_cacheable_amo_i (cfg_error_on_cacheable_amo_i), + .cfg_rtab_single_entry_i (cfg_rtab_single_entry_i), + .cfg_default_wb_i (cfg_default_wb_i), + .cfg_scrub_enable_i (cfg_scrub_enable_i), + .cfg_scrub_period_i (cfg_scrub_period_i), + .cfg_scrub_restart_i (cfg_scrub_restart_i) + ); + + //////////////////////// + // tid pack functions // + //////////////////////// + function automatic hpdcache_req_tid_t pack_tid_snitch( + input word_offset_t word_offset, + input logic is_fpu, + input logic [CoreIDWidth-1:0] core_id, + input logic write, + input reqid_t req_id); + pack_tid_snitch = '0; + pack_tid_snitch[ReqIdLsb +: ReqIdW] = req_id; + pack_tid_snitch[WritePos] = write; + pack_tid_snitch[CoreIdLsb +: CoreIDWidth] = core_id; + pack_tid_snitch[IsFpuPos] = is_fpu; + pack_tid_snitch[WordOffLsb +: LP1NumWordOffsetBits] = word_offset; + endfunction + + function automatic hpdcache_req_tid_t pack_tid_spatz( + input logic [HitmapW-1:0] hitmap, + input logic [OfstsW-1:0] ofsts, + input logic is_fpu, + input logic [CoreIDWidth-1:0] core_id, + input logic write, + input reqid_t req_id); + pack_tid_spatz = '0; + pack_tid_spatz[HitmapLsb +: HitmapW] = hitmap; + pack_tid_spatz[OfstsLsb +: OfstsW] = ofsts; + pack_tid_spatz[ReqIdLsb +: ReqIdW] = req_id; + pack_tid_spatz[WritePos] = write; + pack_tid_spatz[CoreIdLsb +: CoreIDWidth] = core_id; + pack_tid_spatz[IsFpuPos] = is_fpu; + endfunction + +endmodule From e9c57855c35718282a554158ae95f1fe0877ad52 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Tue, 16 Jun 2026 17:35:26 +0200 Subject: [PATCH 04/39] [HW] init l1 ctrl and comitter overwrite --- hardware/src/cachepool_l1_ctrl.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv index bb19554..6881fbe 100644 --- a/hardware/src/cachepool_l1_ctrl.sv +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -418,8 +418,8 @@ module cachepool_l1_ctrl l1_req[1].tid = core_req_i[SnitchPort].q_valid ? l1_cache_req[SnitchPort].tid : '0; end - assign l1_req_valid[1] = core_req_i[SnitchPort].q_valid; - assign cache_req_ready[SnitchPort] = l1_req_ready[1]; + assign l1_req_valid[1] = core_req_i[SnitchPort].q_valid; + assign cache_req_ready[SnitchPort] = l1_req_ready[1]; /////////////////////////////// // Spatz response scatter // From b9e916a2a856f96c1dab4b57df4ba186664e76c3 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Fri, 19 Jun 2026 14:45:51 +0200 Subject: [PATCH 05/39] private L1 defs and configs --- hardware/src/cachepool_pkg.sv | 29 +++++++-- hardware/src/cachepool_tile.sv | 111 ++++++++++++++++++++++++++++++++- 2 files changed, 133 insertions(+), 7 deletions(-) diff --git a/hardware/src/cachepool_pkg.sv b/hardware/src/cachepool_pkg.sv index 3727d6c..c4cb4b7 100644 --- a/hardware/src/cachepool_pkg.sv +++ b/hardware/src/cachepool_pkg.sv @@ -63,8 +63,17 @@ package cachepool_pkg; // 4 ports from Spatz + 1 shared port from Snitch/FPU localparam int unsigned NrTCDMPortsPerCore = 5; - // How many remote ports for each tile in total? - localparam int unsigned NumRemotePortTile = NumRemotePortCore * NrTCDMPortsPerCore; + // Number of L1->L2 interco / remote-NoC planes. + // Historically the tile fabric was replicated once per core TCDM port + // (NrTCDMPortsPerCore planes). With the per-core private L1, each core + // coalesces its NrTCDMPortsPerCore ports into ONE cacheline-wide downstream, + // so the interco / remote NoC collapses to a single plane. This param + // decouples the NoC plane count from the core port count. + localparam int unsigned NumL2Plane = 1; + + // How many remote ports for each tile in total? (one remote slot per plane) + // localparam int unsigned NumRemotePortTile = NumRemotePortCore * NrTCDMPortsPerCore; + localparam int unsigned NumRemotePortTile = NumRemotePortCore * NumL2Plane; //////////////////// // GROUP CONFIG // @@ -388,6 +397,11 @@ package cachepool_pkg; typedef logic [L1AddrWidth-1:0] narrow_addr_t; typedef logic [SPMAddrWidth-1:0] spm_addr_t; + // Cacheline-wide TCDM payload for the private-L1 -> shared-L2 downstream path + // (and the remote / inter-group NoC that carries it). One beat per cacheline. + typedef logic [L1LineWidth-1:0] cacheline_data_t; + typedef logic [L1LineWidth/8-1:0] cacheline_strb_t; + typedef struct packed { logic is_burst; burst_len_t burst_len; @@ -448,7 +462,10 @@ package cachepool_pkg; logic [TileIDWidth-1:0] dst_tile_id; } remote_group_user_t; - `REQRSP_TYPEDEF_ALL(remote_group, narrow_addr_t, narrow_data_t, narrow_strb_t, remote_group_user_t) + // Inter-group remote (FlooNoC) payload carries cacheline-wide L1->L2 traffic. + // (was: narrow_data_t / narrow_strb_t for the old 32b core->L2 path) + // `REQRSP_TYPEDEF_ALL(remote_group, narrow_addr_t, narrow_data_t, narrow_strb_t, remote_group_user_t) + `REQRSP_TYPEDEF_ALL(remote_group, narrow_addr_t, cacheline_data_t, cacheline_strb_t, remote_group_user_t) // XY mesh coordinates for a group. port_id selects the eject port (always 0 for single-link). typedef struct packed { @@ -540,10 +557,14 @@ package cachepool_pkg; // REQRSP: cache transaction (same payload type as L2 in current code) `REQRSP_TYPEDEF_ALL (cache_trans, axi_addr_t, axi_wide_data_t, axi_wide_strb_t, refill_user_t) - // TCDM req/rsp bus => core to L1 + // TCDM req/rsp bus => core to L1 (narrow, 32b) `TCDM_TYPEDEF_ALL(tcdm, narrow_addr_t, narrow_data_t, narrow_strb_t, tcdm_user_t) `TCDM_TYPEDEF_ALL(spm, spm_addr_t, narrow_data_t, narrow_strb_t, tcdm_user_t) + // TCDM req/rsp bus => private L1 to shared L2 (cacheline-wide). Used by the + // collapsed tile interco and the remote NoC that carries L1->L2 traffic. + `TCDM_TYPEDEF_ALL(tcdm_cacheline, narrow_addr_t, cacheline_data_t, cacheline_strb_t, tcdm_user_t) + // AXI typedef bundles `AXI_TYPEDEF_ALL(spatz_axi_narrow, axi_addr_t, axi_narrow_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t) `AXI_TYPEDEF_ALL(spatz_axi_in, axi_addr_t, axi_id_in_t, axi_narrow_data_t, axi_narrow_strb_t, axi_user_t) diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index 0fa53fb..b990cb2 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -9,11 +9,13 @@ `include "common_cells/registers.svh" `include "reqrsp_interface/typedef.svh" `include "snitch_vm/typedef.svh" +`include "hpdcache_typedef.svh" /// Tile implementation for CachePool module cachepool_tile import cachepool_pkg::*; import spatz_pkg::*; + import hpdcache_pkg::*; import fpnew_pkg::fpu_implementation_t; import snitch_pma_pkg::snitch_pma_t; import snitch_icache_pkg::icache_l1_events_t; @@ -290,12 +292,115 @@ module cachepool_tile typedef logic [$clog2(L1NumSet)-1:0] tcdm_bank_addr_t; - // The metadata type used to restore the information from req to rsp + //////////////////////////////////////////// + // Private L1 (LP1) HPDcache config & types // + //////////////////////////////////////////// + // Per-core private L1 data cache (HPDcache, write-through, no coherence). + // It coalesces the core's Spatz TCDM lanes; its mem interface is the + // cacheline-wide downstream (l2_req) that feeds the shared L2 through the + // collapsed tile interco. Config/types defined here and passed to + // cachepool_l1_ctrl as parameters. + + // Spatz coalescer geometry + localparam int unsigned NrLP1CoalInputs = NrTCDMPortsPerCore - 1; // Spatz lanes + localparam int unsigned LP1ExtPorts = NrLP1CoalInputs; + localparam int unsigned LP1WordWidth = 128; // HPDcache word width + localparam int unsigned LP1NrBitsCoalOffset = $clog2(LP1WordWidth/DataWidth); // coalescer offset_t width + localparam int unsigned LP1NumWordOffsetBits = $clog2(LP1WordWidth/DataWidth); // tid word-offset field + localparam int unsigned LP1CoalInfoWidth = LP1ExtPorts + LP1ExtPorts*LP1NrBitsCoalOffset; + localparam int unsigned LP1ReqIdWidth = $clog2(NumSpatzOutstandingLoads); + localparam int unsigned LP1TidWidth = CoreIDWidth + LP1ReqIdWidth + 2 + LP1CoalInfoWidth; // +2: is_fpu, write + localparam int unsigned LP1NrRequesters = 2; // Snitch + Spatz(coalesced) + + localparam hpdcache_pkg::hpdcache_user_cfg_t HPDcacheUserCfg = '{ + nRequesters: LP1NrRequesters, + paWidth: 32, + wordWidth: LP1WordWidth, + sets: 64, // TODO: 32 sets => 8KB/core target (currently 16KB) + ways: 4, + clWords: 4, + reqWords: 1, + reqTransIdWidth: LP1TidWidth + LP1NumWordOffsetBits, + reqSrcIdWidth: 1, // selects requester port (0 Spatz / 1 Snitch) + victimSel: hpdcache_pkg::HPDCACHE_VICTIM_PLRU, + dataWaysPerRamWord: 1, + dataSetsPerRam: 64, + dataRamByteEnable: 1'b1, + accessWords: 4, + mshrSets: 8, + mshrWays: 4, + mshrWaysPerRamWord: 4, + mshrSetsPerRam: 8, + mshrRamByteEnable: 1'b1, + mshrUseRegbank: 1'b1, + cbufEntries: 2, + refillCoreRspFeedthrough: 1'b1, + refillFifoDepth: 2, + wbufDirEntries: 4, + wbufDataEntries: 4, + wbufWords: 4, + wbufTimecntWidth: 3, + rtabEntries: 4, + flushEntries: 2, + flushFifoDepth: 2, + memAddrWidth: L1AddrWidth, + memIdWidth: LP1TidWidth, + memDataWidth: L1LineWidth, + wtEn: 1'b1, // write-through + wbEn: 1'b0, + lowLatency: 1'b1, + eccEn: 1'b0, + eccScrubberEn: 1'b0 + }; + localparam hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg = hpdcacheBuildConfig(HPDcacheUserCfg); + + // The metadata type used to restore the information from req to rsp. + // (extended with `amo` for the private-L1 datapath) typedef struct packed { - tcdm_user_t user; - logic write; + tcdm_user_t user; + logic write; + hpdcache_req_op_t amo; } tcdm_meta_t; + // HPDcache request-side typedefs + typedef logic [HPDcacheCfg.tagWidth-1:0] hpdcache_tag_t; + typedef logic [HPDcacheCfg.u.wordWidth-1:0] hpdcache_data_word_t; + typedef logic [HPDcacheCfg.u.wordWidth/8-1:0] hpdcache_data_be_t; + typedef logic [HPDcacheCfg.reqOffsetWidth-1:0] hpdcache_req_offset_t; + typedef hpdcache_data_word_t [HPDcacheCfg.u.reqWords-1:0] hpdcache_req_data_t; + typedef hpdcache_data_be_t [HPDcacheCfg.u.reqWords-1:0] hpdcache_req_be_t; + typedef logic [HPDcacheCfg.u.reqSrcIdWidth-1:0] hpdcache_req_sid_t; + typedef logic [HPDcacheCfg.u.reqTransIdWidth-1:0] hpdcache_req_tid_t; + `HPDCACHE_TYPEDEF_REQ_T(hpdcache_req_t, hpdcache_req_offset_t, hpdcache_req_data_t, + hpdcache_req_be_t, hpdcache_req_sid_t, hpdcache_req_tid_t, hpdcache_tag_t); + `HPDCACHE_TYPEDEF_RSP_T(hpdcache_rsp_t, hpdcache_req_data_t, hpdcache_req_sid_t, hpdcache_req_tid_t); + typedef logic [HPDcacheCfg.u.wbufTimecntWidth-1:0] hpdcache_wbuf_timecnt_t; + + // HPDcache memory-side typedefs (L1 -> L2 mem channels) + typedef logic [HPDcacheCfg.u.memAddrWidth-1:0] hpdcache_mem_addr_t; + typedef logic [HPDcacheCfg.u.memIdWidth-1:0] hpdcache_mem_id_t; + typedef logic [HPDcacheCfg.u.memDataWidth-1:0] hpdcache_mem_data_t; + typedef logic [HPDcacheCfg.u.memDataWidth/8-1:0] hpdcache_mem_be_t; + `HPDCACHE_TYPEDEF_MEM_REQ_T(hpdcache_mem_req_t, hpdcache_mem_addr_t, hpdcache_mem_id_t); + `HPDCACHE_TYPEDEF_MEM_RESP_R_T(hpdcache_mem_resp_r_t, hpdcache_mem_id_t, hpdcache_mem_data_t); + `HPDCACHE_TYPEDEF_MEM_REQ_W_T(hpdcache_mem_req_w_t, hpdcache_mem_data_t, hpdcache_mem_be_t); + `HPDCACHE_TYPEDEF_MEM_RESP_W_T(hpdcache_mem_resp_w_t, hpdcache_mem_id_t); + + // Spatz request coalescer types. downstream_info_t MUST match + // par_coalescer_top's internal struct exactly: + // { down_id_t id; logic[ExtPorts] hitmap; offset_t[ExtPorts] ofsts; + // info_t[ExtPorts] infos; logic bypass_coalescer } + // with down_id_t = logic, offset_t = logic[$clog2(Down/Up)-1:0], info_t = tcdm_meta_t. + typedef logic [LP1NrBitsCoalOffset-1:0] lp1_offset_t; + typedef logic [LP1NumWordOffsetBits-1:0] word_offset_t; + typedef struct packed { + logic id; + logic [LP1ExtPorts-1:0] hitmap; + lp1_offset_t [LP1ExtPorts-1:0] ofsts; + tcdm_meta_t [LP1ExtPorts-1:0] infos; + logic bypass_coalescer; + } downstream_info_t; + // Regbus peripherals. `AXI_TYPEDEF_ALL(axi_mst, addr_t, id_mst_t, data_t, strb_t, user_t) `AXI_TYPEDEF_ALL(axi_slv, addr_t, id_slv_t, data_t, strb_t, user_t) From 8ae8f1337769e7c1753705c5b1322b611ae70f99 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Fri, 19 Jun 2026 16:58:15 +0200 Subject: [PATCH 06/39] [HW] L1 instantiate, upstream wiring, and tile_id handling --- hardware/src/cachepool_l1_ctrl.sv | 38 +++++--- hardware/src/cachepool_pkg.sv | 6 ++ hardware/src/cachepool_tile.sv | 151 +++++++++++++++++++++++++++++- 3 files changed, 179 insertions(+), 16 deletions(-) diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv index bb19554..0d59005 100644 --- a/hardware/src/cachepool_l1_ctrl.sv +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -140,21 +140,24 @@ module cachepool_l1_ctrl localparam int unsigned WordBytes = coalescedDataWidth / ByteWidth; // tid layout (one fixed, non-overlapping scheme), MSB -> LSB: - // { word_offset | is_fpu | core_id | write | req_id | ofsts | hitmap } + // { word_offset | is_fpu | tile_id | core_id | write | req_id | ofsts | hitmap } // Snitch path uses word_offset (ofsts/hitmap = 0); Spatz path uses ofsts/hitmap - // (word_offset = 0). The {is_fpu, core_id, write, req_id} block is at fixed - // positions for both. sid (0 Spatz / 1 Snitch) selects the unpack path. + // (word_offset = 0). The {is_fpu, tile_id, core_id, write, req_id} block is at + // fixed positions for both. sid (0 Spatz / 1 Snitch) selects the unpack path. + // tile_id is round-tripped so the core-side response recovers the full origin + // metadata (the private L1 is otherwise core/tile-agnostic). localparam int unsigned ReqIdW = $bits(reqid_t); localparam int unsigned HitmapW = NrLP1CoalInputs; localparam int unsigned OfstsW = NrLP1CoalInputs * LP1NrBitsCoalOffset; localparam int unsigned CoalInfoW = HitmapW + OfstsW; - localparam int unsigned TidUserW = CoreIDWidth + ReqIdW + 2; // {is_fpu,core_id,write,req_id} + localparam int unsigned TidUserW = CoreIDWidth + TileIDWidth + ReqIdW + 2; // {is_fpu,tile_id,core_id,write,req_id} localparam int unsigned HitmapLsb = 0; localparam int unsigned OfstsLsb = HitmapW; localparam int unsigned ReqIdLsb = CoalInfoW; localparam int unsigned WritePos = CoalInfoW + ReqIdW; localparam int unsigned CoreIdLsb = CoalInfoW + ReqIdW + 1; - localparam int unsigned IsFpuPos = CoalInfoW + ReqIdW + 1 + CoreIDWidth; + localparam int unsigned TileIdLsb = CoreIdLsb + CoreIDWidth; + localparam int unsigned IsFpuPos = TileIdLsb + TileIDWidth; localparam int unsigned WordOffLsb = CoalInfoW + TidUserW; /////////////////// @@ -167,6 +170,7 @@ module cachepool_l1_ctrl hpdcache_req_offset_t [NrTCDMPortsPerCore-1:0] cache_req_addr_offset; word_offset_t [NrTCDMPortsPerCore-1:0] cache_req_word_offset; logic [NrTCDMPortsPerCore-1:0][CoreIDWidth-1:0] cache_req_coreid; + logic [NrTCDMPortsPerCore-1:0][TileIDWidth-1:0] cache_req_tileid; reqid_t [NrTCDMPortsPerCore-1:0] cache_req_reqid; logic [NrTCDMPortsPerCore-1:0] cache_req_is_fpu; logic [NrTCDMPortsPerCore-1:0] cache_req_write; @@ -236,6 +240,7 @@ module cachepool_l1_ctrl assign cache_req_addr_offset[i] = core_req_i[i].q.addr[HPDcacheCfg.reqOffsetWidth-1:0]; assign cache_req_word_offset[i] = core_req_i[i].q.addr[$clog2(DataWidth/ByteWidth) +: LP1NumWordOffsetBits]; assign cache_req_coreid[i] = core_req_i[i].q.user.core_id; + assign cache_req_tileid[i] = core_req_i[i].q.user.tile_id; assign cache_req_reqid[i] = core_req_i[i].q.user.req_id; assign cache_req_is_fpu[i] = core_req_i[i].q.user.is_fpu; assign cache_req_write[i] = core_req_i[i].q.write; @@ -263,6 +268,7 @@ module cachepool_l1_ctrl // Snitch-path tid (per-port). Spatz lanes get their tid rebuilt post-coalesce. assign l1_cache_req[i].tid = pack_tid_snitch(cache_req_word_offset[i], cache_req_is_fpu[i], + cache_req_tileid[i], cache_req_coreid[i], cache_req_write[i], cache_req_reqid[i]); @@ -291,7 +297,7 @@ module cachepool_l1_ctrl // Coalescer info payload (carried per lane, returned with the response). assign cache_req_info[i].user.core_id = cache_req_coreid[i]; - assign cache_req_info[i].user.tile_id = '0; // tagged at tile level + assign cache_req_info[i].user.tile_id = cache_req_tileid[i]; // round-tripped for core rsp assign cache_req_info[i].user.is_amo = (cache_req_amo[i] != AMONone); assign cache_req_info[i].user.req_id = cache_req_reqid[i]; assign cache_req_info[i].user.is_fpu = cache_req_is_fpu[i]; @@ -395,7 +401,8 @@ module cachepool_l1_ctrl // tid: pack the coalescer scatter info + shared user. l1_req[0].tid = coal_req_valid ? pack_tid_spatz(coal_req_info.hitmap, coal_req_info.ofsts, - coal_meta.user.is_fpu, coal_meta.user.core_id, + coal_meta.user.is_fpu, coal_meta.user.tile_id, + coal_meta.user.core_id, coal_req_write, coal_meta.user.req_id) : '0; end @@ -434,6 +441,7 @@ module cachepool_l1_ctrl coal_resp_user = '0; coal_resp_user.is_fpu = l1_rsp[0].tid[IsFpuPos]; + coal_resp_user.tile_id = l1_rsp[0].tid[TileIdLsb +: TileIDWidth]; coal_resp_user.core_id = l1_rsp[0].tid[CoreIdLsb +: CoreIDWidth]; coal_resp_user.req_id = l1_rsp[0].tid[ReqIdLsb +: ReqIdW]; coal_resp_user.is_amo = 1'b0; @@ -479,7 +487,7 @@ module cachepool_l1_ctrl core_rsp_o[SnitchPort].p.user.core_id = l1_rsp[1].tid[CoreIdLsb +: CoreIDWidth]; core_rsp_o[SnitchPort].p.user.req_id = l1_rsp[1].tid[ReqIdLsb +: ReqIdW]; core_rsp_o[SnitchPort].p.user.is_amo = 1'b0; - core_rsp_o[SnitchPort].p.user.tile_id = '0; + core_rsp_o[SnitchPort].p.user.tile_id = l1_rsp[1].tid[TileIdLsb +: TileIDWidth]; core_rsp_o[SnitchPort].p.write = l1_rsp[1].tid[WritePos]; end @@ -492,8 +500,10 @@ module cachepool_l1_ctrl // drives it, so refills/write-acks are properly back-pressured. Read/write // responses are distinguished by p.write and steered to the matching HPDcache // mem channel. The original HPDcache mem id is recovered by removing the - // per-core offset the tile added (req_id - core_id); the L1 controller is - // core-private and core_id-agnostic. + // per-private-cache offset the tile added to make ids unique towards the shared + // L2 (req_id += core_id + tile_id), i.e. req_id - core_id - tile_id. The L1 + // controller is core/tile-private and agnostic of its own ids (it reads them + // back from the echoed downstream user). always_comb begin : rsp_translation l1_mem_resp_read_valid = 1'b0; l1_mem_resp_write_valid = 1'b0; @@ -504,11 +514,11 @@ module cachepool_l1_ctrl l1_mem_resp_write_valid = l2_rsp_i.p_valid; l1_mem_resp_write.mem_resp_w_is_atomic = l2_rsp_i.p.user.is_amo; l1_mem_resp_write.mem_resp_w_error = HPDCACHE_MEM_RESP_OK; - l1_mem_resp_write.mem_resp_w_id = l2_rsp_i.p.user.req_id - l2_rsp_i.p.user.core_id; + l1_mem_resp_write.mem_resp_w_id = l2_rsp_i.p.user.req_id - l2_rsp_i.p.user.core_id - l2_rsp_i.p.user.tile_id; end else begin l1_mem_resp_read_valid = l2_rsp_i.p_valid; l1_mem_resp_read.mem_resp_r_error = HPDCACHE_MEM_RESP_OK; - l1_mem_resp_read.mem_resp_r_id = l2_rsp_i.p.user.req_id - l2_rsp_i.p.user.core_id; + l1_mem_resp_read.mem_resp_r_id = l2_rsp_i.p.user.req_id - l2_rsp_i.p.user.core_id - l2_rsp_i.p.user.tile_id; l1_mem_resp_read.mem_resp_r_data = l2_rsp_i.p.data; l1_mem_resp_read.mem_resp_r_last = 1'b1; end @@ -677,6 +687,7 @@ module cachepool_l1_ctrl function automatic hpdcache_req_tid_t pack_tid_snitch( input word_offset_t word_offset, input logic is_fpu, + input logic [TileIDWidth-1:0] tile_id, input logic [CoreIDWidth-1:0] core_id, input logic write, input reqid_t req_id); @@ -684,6 +695,7 @@ module cachepool_l1_ctrl pack_tid_snitch[ReqIdLsb +: ReqIdW] = req_id; pack_tid_snitch[WritePos] = write; pack_tid_snitch[CoreIdLsb +: CoreIDWidth] = core_id; + pack_tid_snitch[TileIdLsb +: TileIDWidth] = tile_id; pack_tid_snitch[IsFpuPos] = is_fpu; pack_tid_snitch[WordOffLsb +: LP1NumWordOffsetBits] = word_offset; endfunction @@ -692,6 +704,7 @@ module cachepool_l1_ctrl input logic [HitmapW-1:0] hitmap, input logic [OfstsW-1:0] ofsts, input logic is_fpu, + input logic [TileIDWidth-1:0] tile_id, input logic [CoreIDWidth-1:0] core_id, input logic write, input reqid_t req_id); @@ -701,6 +714,7 @@ module cachepool_l1_ctrl pack_tid_spatz[ReqIdLsb +: ReqIdW] = req_id; pack_tid_spatz[WritePos] = write; pack_tid_spatz[CoreIdLsb +: CoreIDWidth] = core_id; + pack_tid_spatz[TileIdLsb +: TileIDWidth] = tile_id; pack_tid_spatz[IsFpuPos] = is_fpu; endfunction diff --git a/hardware/src/cachepool_pkg.sv b/hardware/src/cachepool_pkg.sv index c4cb4b7..363358d 100644 --- a/hardware/src/cachepool_pkg.sv +++ b/hardware/src/cachepool_pkg.sv @@ -125,6 +125,12 @@ package cachepool_pkg; // UART Configuration localparam int unsigned UartAddr = 32'hC001_0000; + ///////////////////////// + // CACHEPOOL LP1 CFG // + ///////////////////////// + + localparam int unsigned NumLP1CacheCtrl = NumCoresTile; + /////////////////////// // CACHEPOOL L1 CFG // /////////////////////// diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index b990cb2..078ce2b 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -309,7 +309,7 @@ module cachepool_tile localparam int unsigned LP1NumWordOffsetBits = $clog2(LP1WordWidth/DataWidth); // tid word-offset field localparam int unsigned LP1CoalInfoWidth = LP1ExtPorts + LP1ExtPorts*LP1NrBitsCoalOffset; localparam int unsigned LP1ReqIdWidth = $clog2(NumSpatzOutstandingLoads); - localparam int unsigned LP1TidWidth = CoreIDWidth + LP1ReqIdWidth + 2 + LP1CoalInfoWidth; // +2: is_fpu, write + localparam int unsigned LP1TidWidth = CoreIDWidth + TileIDWidth + LP1ReqIdWidth + 2 + LP1CoalInfoWidth; // +2: is_fpu, write; tile_id+core_id round-tripped localparam int unsigned LP1NrRequesters = 2; // Snitch + Spatz(coalesced) localparam hpdcache_pkg::hpdcache_user_cfg_t HPDcacheUserCfg = '{ @@ -528,6 +528,18 @@ module cachepool_tile tcdm_req_t [NumL1CtrlTile-1:0] cache_amo_req; tcdm_rsp_t [NumL1CtrlTile-1:0] cache_amo_rsp; + // ---- Private L1 (LP1) -> shared L1/L2 downstream (cacheline-wide) ---- + // One private L1 per core; its single mem-side downstream feeds the collapsed + // tile interco towards the shared cache (named L1 in this file). lp1_l1_req_unique + // tags a per-core id (core_id, req_id+=c) so the shared L1 round-trips it + // (recovered in the LP1 ctrl as req_id - core_id). + tcdm_cacheline_req_t [NumL1CtrlTile-1:0] lp1_l1_req, lp1_l1_req_unique; + tcdm_cacheline_rsp_t [NumL1CtrlTile-1:0] lp1_l1_rsp; + logic [NumL1CtrlTile-1:0] lp1_l1_rsp_ready; + + tcdm_req_t [NumLP1CacheCtrl-1:0][NrTCDMPortsPerCore-1:0] cache_req_transposed; + tcdm_rsp_t [NumLP1CacheCtrl-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_transposed; + logic [NumLP1CacheCtrl-1:0][NrTCDMPortsPerCore-1:0] lp1_cache_rsp_ready, lp1_cache_req_ready; logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_valid; logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_ready; @@ -620,21 +632,27 @@ module cachepool_tile logic [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_pready, cache_xbar_pready; logic [NumL1CtrlTile-1:0] cache_amo_pready; + // ---------------------------------------------------------------------------- + // [LP1] Old core<->interco bridge, replaced by the per-core private L1. + // The cores now drive their TCDM ports into cachepool_l1_ctrl (gen_lp1_cache); + // the LP1 downstream (lp1_l1_req_unique) feeds the collapsed interco. The old + // unmerge / cache_req reshape below is superseded and commented out. + // ---------------------------------------------------------------------------- always_comb begin : cache_flush_protection for (int j = 0; unsigned'(j) < NrTCDMPortsCores; j++) begin /***** REQ *****/ unmerge_req[j].q = tcdm_req[j].q; unmerge_req[j].q_valid = tcdm_req[j].q_valid; unmerge_pready[j] = 1'b1; - + /***** RSP *****/ tcdm_rsp[j].p = unmerge_rsp[j].p; tcdm_rsp[j].p_valid = unmerge_rsp[j].p_valid; tcdm_rsp[j].q_ready = unmerge_rsp[j].q_ready; end - + end - + for (genvar j = 0; j < NrTCDMPortsPerCore; j++) begin for (genvar cb = 0; cb < NumL1CtrlTile; cb++) begin always_comb begin @@ -643,7 +661,132 @@ module cachepool_tile cache_pready[j][cb] = unmerge_pready[cb*NrTCDMPortsPerCore+j]; unmerge_rsp [cb*NrTCDMPortsPerCore+j] = cache_rsp [j][cb]; end + + end + end + for (genvar i = 0; i < NumLP1CacheCtrl; i++) begin : gen_lp1_cache_transpose + for (genvar j = 0; j < NrTCDMPortsPerCore; j++) begin : gen_lp1_cache_transpose_signals + assign cache_req_transposed[i][j] = cache_req[j][i]; + + assign cache_rsp[j][i].p_valid = cache_rsp_transposed[i][j].p_valid; + assign cache_rsp[j][i].p.data = cache_rsp_transposed[i][j].p.data; + assign cache_rsp[j][i].p.user = cache_rsp_transposed[i][j].p.user; + assign cache_rsp[j][i].p.write = cache_rsp_transposed[i][j].p.write; + + assign cache_rsp[j][i].q_ready = lp1_cache_req_ready[i][j]; + assign lp1_cache_rsp_ready[i][j] = cache_pready[j][i]; + end + end + + // ---------------------------------------------------------------------------- + // [LP1] Per-core private L1 data cache (HPDcache, write-through, no coherence). + // Core side: the core's NrTCDMPortsPerCore TCDM ports (Spatz lanes [0..N-2] + + // Snitch [N-1]). The LP1 coalesces/translates internally and exposes ONE + // cacheline-wide downstream (lp1_l1_req / lp1_l1_rsp) to the shared L1/L2. + // The core is always ready to accept responses (matches the legacy + // unmerge_pready = 1'b1 convention), so core_rsp_ready_i is tied high. + // ---------------------------------------------------------------------------- + for (genvar c = 0; c < NumLP1CacheCtrl; c++) begin : gen_lp1_cache + cachepool_l1_ctrl #( + .NrTCDMPortsPerCore (NrTCDMPortsPerCore ), + .DataWidth (DataWidth ), + .ByteWidth (8 ), + .LP1NumWordOffsetBits (LP1NumWordOffsetBits ), + .LP1NrBitsCoalOffset (LP1NrBitsCoalOffset ), + .HPDcacheCfg (HPDcacheCfg ), + .wbuf_timecnt_t (hpdcache_wbuf_timecnt_t), + .l1_cache_req_t (tcdm_req_t ), + .l1_cache_rsp_t (tcdm_rsp_t ), + .tcdm_meta_t (tcdm_meta_t ), + .downstream_info_t (downstream_info_t ), + .word_offset_t (word_offset_t ), + .l2_cache_req_t (tcdm_cacheline_req_t ), + .l2_cache_rsp_t (tcdm_cacheline_rsp_t ), + .hpdcache_tag_t (hpdcache_tag_t ), + .hpdcache_data_word_t (hpdcache_data_word_t ), + .hpdcache_data_be_t (hpdcache_data_be_t ), + .hpdcache_req_offset_t (hpdcache_req_offset_t ), + .hpdcache_req_data_t (hpdcache_req_data_t ), + .hpdcache_req_be_t (hpdcache_req_be_t ), + .hpdcache_req_sid_t (hpdcache_req_sid_t ), + .hpdcache_req_tid_t (hpdcache_req_tid_t ), + .hpdcache_req_t (hpdcache_req_t ), + .hpdcache_rsp_t (hpdcache_rsp_t ), + .hpdcache_mem_addr_t (hpdcache_mem_addr_t ), + .hpdcache_mem_id_t (hpdcache_mem_id_t ), + .hpdcache_mem_data_t (hpdcache_mem_data_t ), + .hpdcache_mem_be_t (hpdcache_mem_be_t ), + .hpdcache_mem_req_t (hpdcache_mem_req_t ), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t ), + .hpdcache_mem_resp_r_t (hpdcache_mem_resp_r_t ), + .hpdcache_mem_resp_w_t (hpdcache_mem_resp_w_t ) + ) i_lp1_cache ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .wbuf_flush_i (1'b0 ), + + // Core side (NrTCDMPortsPerCore narrow TCDM ports for this core) + .core_req_i (cache_req_transposed [c]), + .core_rsp_o (cache_rsp_transposed [c]), + .core_req_ready_o (lp1_cache_req_ready [c]), + .core_rsp_ready_i (lp1_cache_rsp_ready [c]), + + // Downstream (cacheline-wide) to shared L1/L2 via the interco + .l2_req_o (lp1_l1_req [c]), + .l2_rsp_i (lp1_l1_rsp [c]), + .l2_rsp_ready_o (lp1_l1_rsp_ready [c]), + + // Performance events: unconnected (perf counters unused for now) + .evt_cache_write_miss_o (), + .evt_cache_read_miss_o (), + .evt_cache_dir_unc_err_o (), + .evt_cache_dir_cor_err_o (), + .evt_cache_dat_unc_err_o (), + .evt_cache_dat_cor_err_o (), + .evt_scrub_complete_o (), + .evt_uncached_req_o (), + .evt_cmo_req_o (), + .evt_write_req_o (), + .evt_read_req_o (), + .evt_prefetch_req_o (), + .evt_req_on_hold_o (), + .evt_rtab_rollback_o (), + .evt_stall_refill_o (), + .evt_stall_o (), + .wbuf_empty_o (), + + // Configuration (static for now) + .cfg_enable_i (1'b1), + .cfg_wbuf_threshold_i ('0 ), // drain writes immediately (WT) + .cfg_wbuf_reset_timecnt_on_write_i (1'b0), + .cfg_wbuf_sequential_waw_i (1'b0), + .cfg_wbuf_inhibit_write_coalescing_i (1'b0), + .cfg_prefetch_updt_plru_i (1'b0), + .cfg_error_on_cacheable_amo_i (1'b0), + .cfg_rtab_single_entry_i (1'b0), + .cfg_default_wb_i (1'b0), // write-through default + .cfg_scrub_enable_i (1'b0), + .cfg_scrub_period_i ('0 ), + .cfg_scrub_restart_i (1'b0) + ); + end + + // [LP1] Tag each private L1 downstream with a globally-unique id so the shared + // L1/L2 can round-trip it. core_id selects the response path in the interco + // (input port == core_id); tile_id marks this tile (for remote response + // routing). req_id += core_id + tile_id offsets the HPDcache mem id so that + // ids from different private caches (across cores AND remote tiles, which are + // mutually agnostic) stay distinct towards the shared L2 (which keys on + // req_id). The LP1 ctrl recovers the original via req_id - core_id - tile_id. + for (genvar c = 0; c < NumLP1CacheCtrl; c++) begin : gen_lp1_l1_req_unique + logic [CoreIDWidth-1:0] c_id; + assign c_id = c[CoreIDWidth-1:0]; + always_comb begin + lp1_l1_req_unique[c] = lp1_l1_req[c]; + lp1_l1_req_unique[c].q.user.core_id = c_id; + lp1_l1_req_unique[c].q.user.tile_id = tile_id_i; + lp1_l1_req_unique[c].q.user.req_id = lp1_l1_req[c].q.user.req_id + c_id + tile_id_i; end end From b3f9d5810a5e89698c929cd340187f291da067de Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Mon, 22 Jun 2026 15:39:22 +0200 Subject: [PATCH 07/39] [HW] tile cache interco collapse, and adjustment at group-level --- hardware/src/cachepool_group.sv | 191 +++++++----- hardware/src/cachepool_tile.sv | 526 +++++++++++++++++++++++--------- 2 files changed, 510 insertions(+), 207 deletions(-) diff --git a/hardware/src/cachepool_group.sv b/hardware/src/cachepool_group.sv index 1e6e5d4..c1f215f 100644 --- a/hardware/src/cachepool_group.sv +++ b/hardware/src/cachepool_group.sv @@ -93,10 +93,16 @@ module cachepool_group /*** ATTENTION: `NrSramCfg` should be changed if `L1NumDataBank` and `L1NumTagBank` is changed ***/ parameter int unsigned NrSramCfg = 1, + // [LP1] Strategy-B collapse: inter-group ports no longer fan out per TCDM + // plane; the per-tile count is NumRemoteGroupPortCore * NumL2Plane. + // localparam int unsigned TotRGPorts = (NumRemoteGroupPortCore == 0) ? 0 : + // NumTilesPerGroup*NumRemoteGroupPortCore*NrTCDMPortsPerCore-1, + // localparam int unsigned NumRemoteGroupPortTile = (NumRemoteGroupPortCore == 0) ? 1 : + // NumRemoteGroupPortCore * NrTCDMPortsPerCore localparam int unsigned TotRGPorts = (NumRemoteGroupPortCore == 0) ? 0 : - NumTilesPerGroup*NumRemoteGroupPortCore*NrTCDMPortsPerCore-1, + NumTilesPerGroup*NumRemoteGroupPortCore*NumL2Plane-1, localparam int unsigned NumRemoteGroupPortTile = (NumRemoteGroupPortCore == 0) ? 1 : - NumRemoteGroupPortCore * NrTCDMPortsPerCore + NumRemoteGroupPortCore * NumL2Plane ) ( /// System clock. input logic clk_i, @@ -149,9 +155,9 @@ module cachepool_group /// Inter-group remote access ports (to other groups). /// Layout: [NumTilesPerGroup-1:0][NumRemoteGroupPortTile-1:0] flattened to /// [NumTilesPerGroup * NumRemoteGroupPortTile - 1 : 0]. - /// Per-tile flat index: j + r * NrTCDMPortsPerCore (j = interco instance, - /// r = inter-group slot within that instance). - /// NumRemoteGroupPortTile = NumRemoteGroupPortCore * NrTCDMPortsPerCore. + /// Per-tile flat index: j + r * NumL2Plane (j = L2 plane, r = inter-group + /// slot within that plane). + /// NumRemoteGroupPortTile = NumRemoteGroupPortCore * NumL2Plane. /// Uses REQRSP-style types with built-in ready and remote_group_user_t. output remote_group_req_t [TotRGPorts:0] remote_group_req_o, input remote_group_rsp_t [TotRGPorts:0] remote_group_rsp_i, @@ -632,25 +638,35 @@ module cachepool_group // Tile remote access signals // In/Out relative to the tile (out--leave a tile; in--enter a tile) - // Tile-side flat layout: index = j + r*NrTCDMPortsPerCore (j=xbar idx, r=remote slot within xbar) - tcdm_req_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_out_req; - tcdm_rsp_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_out_rsp; + // [LP1] Strategy-B + Option-A: tile-side remote ports are cacheline-wide now, + // and the per-plane (NrTCDMPortsPerCore) xbar fan-out collapses to NumL2Plane. + // Tile-side flat layout: index = j + r*NumL2Plane (j=xbar idx, r=remote slot within xbar) + // tcdm_req_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_out_req; + // tcdm_rsp_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_out_rsp; + tcdm_cacheline_req_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_out_req; + tcdm_cacheline_rsp_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_out_rsp; logic [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_ready, tile_remote_out_ready; - tcdm_req_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_req; - tcdm_rsp_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_rsp; + // tcdm_req_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_req; + // tcdm_rsp_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_rsp; + tcdm_cacheline_req_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_req; + tcdm_cacheline_rsp_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_rsp; - // Xbar-side: NrTCDMPortsPerCore xbars, each with NumTilesPerGroup*NumRemotePortCore ports + // Xbar-side: NumL2Plane xbars, each with NumTilesPerGroup*NumRemotePortCore ports // Xbar port index = t*NumRemotePortCore + r - tcdm_req_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_req_chan; - logic [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_req_valid, tile_remote_out_req_ready; - tcdm_rsp_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_rsp_chan; - logic [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_rsp_valid, tile_remote_out_rsp_ready; - - tcdm_req_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_req_chan; - logic [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_req_valid, tile_remote_in_req_ready; - tcdm_rsp_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_rsp_chan; - logic [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_rsp_valid, tile_remote_in_rsp_ready; + // tcdm_req_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_req_chan; + // tcdm_rsp_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_rsp_chan; + // tcdm_req_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_req_chan; + // tcdm_rsp_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_rsp_chan; + tcdm_cacheline_req_chan_t [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_req_chan; + logic [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_req_valid, tile_remote_out_req_ready; + tcdm_cacheline_rsp_chan_t [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_rsp_chan; + logic [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_rsp_valid, tile_remote_out_rsp_ready; + + tcdm_cacheline_req_chan_t [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_req_chan; + logic [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_req_valid, tile_remote_in_req_ready; + tcdm_cacheline_rsp_chan_t [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_rsp_chan; + logic [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_rsp_valid, tile_remote_in_rsp_ready; // Per-group override of package-level remote xbar selection width. // The package uses NumTiles (total), but the group's xbar is sized per-group. @@ -660,31 +676,34 @@ module cachepool_group // Tile-side selection: narrow type, only carries tile_id remote_tile_sel_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] remote_out_sel_tile; // Xbar-side selection: wider type, encodes tile_id*NumRemotePortCore + core_id%NumRemotePortCore - local_remote_xbar_sel_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] remote_out_sel_xbar, remote_in_sel_xbar; + // local_remote_xbar_sel_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] remote_out_sel_xbar, remote_in_sel_xbar; + local_remote_xbar_sel_t [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] remote_out_sel_xbar, remote_in_sel_xbar; for (genvar t = 0; t < NumTilesPerGroup; t++) begin - for (genvar j = 0; j < NrTCDMPortsPerCore; j++) begin + // [LP1] j now indexes the (single) L2 plane; tile flat index = j + r*NumL2Plane. + // for (genvar j = 0; j < NrTCDMPortsPerCore; j++) begin + for (genvar j = 0; j < NumL2Plane; j++) begin for (genvar r = 0; r < NumRemotePortCore; r++) begin - // tile flat index: j + r*NrTCDMPortsPerCore + // tile flat index: j + r*NumL2Plane // xbar port index: t*NumRemotePortCore + r - assign tile_remote_out_req_chan [j][t*NumRemotePortCore+r] = tile_remote_out_req[t][j+r*NrTCDMPortsPerCore].q; - assign tile_remote_out_req_valid[j][t*NumRemotePortCore+r] = tile_remote_out_req[t][j+r*NrTCDMPortsPerCore].q_valid; - assign tile_remote_out_rsp_ready[j][t*NumRemotePortCore+r] = tile_remote_in_ready[t][j+r*NrTCDMPortsPerCore]; + assign tile_remote_out_req_chan [j][t*NumRemotePortCore+r] = tile_remote_out_req[t][j+r*NumL2Plane].q; + assign tile_remote_out_req_valid[j][t*NumRemotePortCore+r] = tile_remote_out_req[t][j+r*NumL2Plane].q_valid; + assign tile_remote_out_rsp_ready[j][t*NumRemotePortCore+r] = tile_remote_in_ready[t][j+r*NumL2Plane]; - assign tile_remote_out_rsp[t][j+r*NrTCDMPortsPerCore].p = tile_remote_out_rsp_chan [j][t*NumRemotePortCore+r]; - assign tile_remote_out_rsp[t][j+r*NrTCDMPortsPerCore].p_valid = tile_remote_out_rsp_valid[j][t*NumRemotePortCore+r]; - assign tile_remote_out_rsp[t][j+r*NrTCDMPortsPerCore].q_ready = tile_remote_out_req_ready[j][t*NumRemotePortCore+r]; + assign tile_remote_out_rsp[t][j+r*NumL2Plane].p = tile_remote_out_rsp_chan [j][t*NumRemotePortCore+r]; + assign tile_remote_out_rsp[t][j+r*NumL2Plane].p_valid = tile_remote_out_rsp_valid[j][t*NumRemotePortCore+r]; + assign tile_remote_out_rsp[t][j+r*NumL2Plane].q_ready = tile_remote_out_req_ready[j][t*NumRemotePortCore+r]; - assign tile_remote_in_req[t][j+r*NrTCDMPortsPerCore].q = tile_remote_in_req_chan [j][t*NumRemotePortCore+r]; - assign tile_remote_in_req[t][j+r*NrTCDMPortsPerCore].q_valid = tile_remote_in_req_valid[j][t*NumRemotePortCore+r]; - assign tile_remote_out_ready[t][j+r*NrTCDMPortsPerCore] = tile_remote_in_rsp_ready[j][t*NumRemotePortCore+r]; + assign tile_remote_in_req[t][j+r*NumL2Plane].q = tile_remote_in_req_chan [j][t*NumRemotePortCore+r]; + assign tile_remote_in_req[t][j+r*NumL2Plane].q_valid = tile_remote_in_req_valid[j][t*NumRemotePortCore+r]; + assign tile_remote_out_ready[t][j+r*NumL2Plane] = tile_remote_in_rsp_ready[j][t*NumRemotePortCore+r]; - assign tile_remote_in_rsp_chan [j][t*NumRemotePortCore+r] = tile_remote_in_rsp[t][j+r*NrTCDMPortsPerCore].p; - assign tile_remote_in_rsp_valid[j][t*NumRemotePortCore+r] = tile_remote_in_rsp[t][j+r*NrTCDMPortsPerCore].p_valid; - assign tile_remote_in_req_ready[j][t*NumRemotePortCore+r] = tile_remote_in_rsp[t][j+r*NrTCDMPortsPerCore].q_ready; + assign tile_remote_in_rsp_chan [j][t*NumRemotePortCore+r] = tile_remote_in_rsp[t][j+r*NumL2Plane].p; + assign tile_remote_in_rsp_valid[j][t*NumRemotePortCore+r] = tile_remote_in_rsp[t][j+r*NumL2Plane].p_valid; + assign tile_remote_in_req_ready[j][t*NumRemotePortCore+r] = tile_remote_in_rsp[t][j+r*NumL2Plane].q_ready; assign remote_out_sel_xbar[j][t*NumRemotePortCore+r] = local_remote_xbar_sel_t'( - remote_out_sel_tile[t][j+r*NrTCDMPortsPerCore] * NumRemotePortCore + remote_out_sel_tile[t][j+r*NumL2Plane] * NumRemotePortCore + tile_remote_out_req_chan[j][t*NumRemotePortCore+r].user.core_id % NumRemotePortCore); assign remote_in_sel_xbar[j][t*NumRemotePortCore+r] = local_remote_xbar_sel_t'( @@ -880,38 +899,72 @@ module cachepool_group // Remote XBar // ------------ - for (genvar p = 0; p < NrTCDMPortsPerCore; p++) begin : gen_remote_tile_xbar - // Decide which tile to go - reqrsp_xbar #( - .NumInp (NumTilesPerGroup * NumRemotePortCore ), - .NumOut (NumTilesPerGroup * NumRemotePortCore ), - .PipeReg (1'b1 ), - .RspReg (1'b1 ), - .ExtReqPrio (1'b0 ), - .ExtRspPrio (1'b0 ), - .tcdm_req_chan_t (tcdm_req_chan_t ), - .tcdm_rsp_chan_t (tcdm_rsp_chan_t ) - ) i_tile_remote_xbar ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .slv_req_i (tile_remote_out_req_chan [p] ), - .slv_req_valid_i (tile_remote_out_req_valid[p] ), - .slv_req_ready_o (tile_remote_out_req_ready[p] ), - .slv_rsp_o (tile_remote_out_rsp_chan [p] ), - .slv_rsp_valid_o (tile_remote_out_rsp_valid[p] ), - .slv_rsp_ready_i (tile_remote_out_rsp_ready[p] ), - .slv_sel_i (remote_out_sel_xbar [p] ), - .slv_rr_i ('0 ), - .slv_selected_o (/*selection info in cid*/ ), - .mst_req_o (tile_remote_in_req_chan [p] ), - .mst_req_valid_o (tile_remote_in_req_valid [p] ), - .mst_req_ready_i (tile_remote_in_req_ready [p] ), - .mst_rsp_i (tile_remote_in_rsp_chan [p] ), - .mst_rsp_valid_i (tile_remote_in_rsp_valid [p] ), - .mst_rsp_ready_o (tile_remote_in_rsp_ready [p] ), - .mst_rr_i ('0 ), - .mst_sel_i (remote_in_sel_xbar [p] ) - ); - end + // for (genvar p = 0; p < NrTCDMPortsPerCore; p++) begin : gen_remote_tile_xbar + // // Decide which tile to go + // reqrsp_xbar #( + // .NumInp (NumTilesPerGroup * NumRemotePortCore ), + // .NumOut (NumTilesPerGroup * NumRemotePortCore ), + // .PipeReg (1'b1 ), + // .RspReg (1'b1 ), + // .ExtReqPrio (1'b0 ), + // .ExtRspPrio (1'b0 ), + // .tcdm_req_chan_t (tcdm_req_chan_t ), + // .tcdm_rsp_chan_t (tcdm_rsp_chan_t ) + // ) i_tile_remote_xbar ( + // .clk_i (clk_i ), + // .rst_ni (rst_ni ), + // .slv_req_i (tile_remote_out_req_chan [p] ), + // .slv_req_valid_i (tile_remote_out_req_valid[p] ), + // .slv_req_ready_o (tile_remote_out_req_ready[p] ), + // .slv_rsp_o (tile_remote_out_rsp_chan [p] ), + // .slv_rsp_valid_o (tile_remote_out_rsp_valid[p] ), + // .slv_rsp_ready_i (tile_remote_out_rsp_ready[p] ), + // .slv_sel_i (remote_out_sel_xbar [p] ), + // .slv_rr_i ('0 ), + // .slv_selected_o (/*selection info in cid*/ ), + // .mst_req_o (tile_remote_in_req_chan [p] ), + // .mst_req_valid_o (tile_remote_in_req_valid [p] ), + // .mst_req_ready_i (tile_remote_in_req_ready [p] ), + // .mst_rsp_i (tile_remote_in_rsp_chan [p] ), + // .mst_rsp_valid_i (tile_remote_in_rsp_valid [p] ), + // .mst_rsp_ready_o (tile_remote_in_rsp_ready [p] ), + // .mst_rr_i ('0 ), + // .mst_sel_i (remote_in_sel_xbar [p] ) + // ); + // end + + // [LP1] Strategy-B collapse: a SINGLE intra-group remote crossbar (NumL2Plane = 1) + // carrying cacheline-wide payloads. The de-interleave above maps every tile's + // remote slots onto plane 0, so this one xbar serves the whole group. + reqrsp_xbar #( + .NumInp (NumTilesPerGroup * NumRemotePortCore ), + .NumOut (NumTilesPerGroup * NumRemotePortCore ), + .PipeReg (1'b1 ), + .RspReg (1'b1 ), + .ExtReqPrio (1'b0 ), + .ExtRspPrio (1'b0 ), + .tcdm_req_chan_t (tcdm_cacheline_req_chan_t ), + .tcdm_rsp_chan_t (tcdm_cacheline_rsp_chan_t ) + ) i_tile_remote_xbar ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .slv_req_i (tile_remote_out_req_chan [0] ), + .slv_req_valid_i (tile_remote_out_req_valid[0] ), + .slv_req_ready_o (tile_remote_out_req_ready[0] ), + .slv_rsp_o (tile_remote_out_rsp_chan [0] ), + .slv_rsp_valid_o (tile_remote_out_rsp_valid[0] ), + .slv_rsp_ready_i (tile_remote_out_rsp_ready[0] ), + .slv_sel_i (remote_out_sel_xbar [0] ), + .slv_rr_i ('0 ), + .slv_selected_o (/*selection info in cid*/ ), + .mst_req_o (tile_remote_in_req_chan [0] ), + .mst_req_valid_o (tile_remote_in_req_valid [0] ), + .mst_req_ready_i (tile_remote_in_req_ready [0] ), + .mst_rsp_i (tile_remote_in_rsp_chan [0] ), + .mst_rsp_valid_i (tile_remote_in_rsp_valid [0] ), + .mst_rsp_ready_o (tile_remote_in_rsp_ready [0] ), + .mst_rr_i ('0 ), + .mst_sel_i (remote_in_sel_xbar [0] ) + ); endmodule diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index 078ce2b..1d91ad4 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -105,7 +105,10 @@ module cachepool_tile /// # SRAM Configuration rules needed: L1D Tag + L1D Data + L1D FIFO + L1I Tag + L1I Data /*** ATTENTION: `NrSramCfg` should be changed if `L1NumDataBank` and `L1NumTagBank` is changed ***/ parameter int unsigned NrSramCfg = 1, - localparam int unsigned TotRGPorts = (NumRemoteGroupPortCore == 0) ? 0 : NumRemoteGroupPortCore*NrTCDMPortsPerCore-1 + // [LP1] Strategy-B collapse: inter-group remote ports no longer fan out per + // TCDM plane; the flat count drops to NumRemoteGroupPortCore * NumL2Plane. + // localparam int unsigned TotRGPorts = (NumRemoteGroupPortCore == 0) ? 0 : NumRemoteGroupPortCore*NrTCDMPortsPerCore-1 + localparam int unsigned TotRGPorts = (NumRemoteGroupPortCore == 0) ? 0 : NumRemoteGroupPortCore*NumL2Plane-1 ) ( /// System clock. input logic clk_i, @@ -146,13 +149,21 @@ module cachepool_tile output axi_out_req_t [TileNarrowAxiPorts-1:0] axi_wide_req_o, input axi_out_resp_t [TileNarrowAxiPorts-1:0] axi_wide_rsp_i, /// Remote Tile access ports (to remote tiles) - output tcdm_req_t [NumRemotePortTile-1:0] remote_req_o, + // [LP1] Strategy-B collapse + Option-A width: the intra-group remote NoC is now + // cacheline-wide (tcdm_cacheline_*) and the flat dimension collapses to + // NumRemotePortTile = NumRemotePortCore * NumL2Plane (NumL2Plane = 1). Old + // narrow ports commented out. + // output tcdm_req_t [NumRemotePortTile-1:0] remote_req_o, + // input tcdm_rsp_t [NumRemotePortTile-1:0] remote_rsp_i, + // input tcdm_req_t [NumRemotePortTile-1:0] remote_req_i, + // output tcdm_rsp_t [NumRemotePortTile-1:0] remote_rsp_o, + output tcdm_cacheline_req_t [NumRemotePortTile-1:0] remote_req_o, output remote_tile_sel_t [NumRemotePortTile-1:0] remote_req_dst_o, - input tcdm_rsp_t [NumRemotePortTile-1:0] remote_rsp_i, + input tcdm_cacheline_rsp_t [NumRemotePortTile-1:0] remote_rsp_i, input logic [NumRemotePortTile-1:0] remote_rsp_ready_i, /// Remote Tile access ports (from remote tiles) - input tcdm_req_t [NumRemotePortTile-1:0] remote_req_i, - output tcdm_rsp_t [NumRemotePortTile-1:0] remote_rsp_o, + input tcdm_cacheline_req_t [NumRemotePortTile-1:0] remote_req_i, + output tcdm_cacheline_rsp_t [NumRemotePortTile-1:0] remote_rsp_o, output logic [NumRemotePortTile-1:0] remote_rsp_ready_o, /// Inter-group remote access ports (to other groups). /// Flat layout: flat index = j + r * NrTCDMPortsPerCore, @@ -516,17 +527,30 @@ module cachepool_tile tcdm_req_t [NrTCDMPortsCores-1:0] unmerge_req; tcdm_rsp_t [NrTCDMPortsCores-1:0] unmerge_rsp; - tcdm_req_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_req, cache_xbar_req; - tcdm_rsp_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_rsp, cache_xbar_rsp; + // [LP1] cache_req/cache_rsp stay as the per-core *narrow* TCDM ports that feed + // the private L1 (gen_lp1_cache_transpose). The interco mem-side collapses to a + // single cacheline-wide plane per L2 controller (NumL2Plane = 1), so cache_xbar_* + // lose the NrTCDMPortsPerCore dimension and become tcdm_cacheline_*. + tcdm_req_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_req; + tcdm_rsp_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_rsp; + // tcdm_req_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_req, cache_xbar_req; + // tcdm_rsp_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_rsp, cache_xbar_rsp; + tcdm_cacheline_req_t [NumL1CtrlTile-1:0] cache_xbar_req; + tcdm_cacheline_rsp_t [NumL1CtrlTile-1:0] cache_xbar_rsp; // Post-xbar gated copies. // cache_ctrl_req : xbar output with q_valid suppressed during flush. - // cache_bank_rsp : raw response from the bank/AMO stage; q_ready is gated before + // cache_bank_rsp : raw response from the bank stage; q_ready is gated before // being returned to the interco as cache_xbar_rsp. - tcdm_req_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_ctrl_req; - tcdm_rsp_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_bank_rsp; + // tcdm_req_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_ctrl_req; + // tcdm_rsp_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_bank_rsp; + tcdm_cacheline_req_t [NumL1CtrlTile-1:0] cache_ctrl_req; + tcdm_cacheline_rsp_t [NumL1CtrlTile-1:0] cache_bank_rsp; - tcdm_req_t [NumL1CtrlTile-1:0] cache_amo_req; - tcdm_rsp_t [NumL1CtrlTile-1:0] cache_amo_rsp; + // [LP1] Phase 1: AMOs are serviced inside the private L1 (HPDcache); the L2-side + // spatz_cache_amo is bypassed (kept instantiated-but-unused below for phase 2). + // cache_amo_* are therefore unused in the collapsed path. + // tcdm_req_t [NumL1CtrlTile-1:0] cache_amo_req; + // tcdm_rsp_t [NumL1CtrlTile-1:0] cache_amo_rsp; // ---- Private L1 (LP1) -> shared L1/L2 downstream (cacheline-wide) ---- // One private L1 per core; its single mem-side downstream feeds the collapsed @@ -541,19 +565,35 @@ module cachepool_tile tcdm_rsp_t [NumLP1CacheCtrl-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_transposed; logic [NumLP1CacheCtrl-1:0][NrTCDMPortsPerCore-1:0] lp1_cache_rsp_ready, lp1_cache_req_ready; - logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_valid; - logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_ready; - tcdm_addr_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_addr; - tcdm_user_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_meta; - logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_write; - data_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_data; - strb_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_strb; - - logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_valid; - logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_ready; - logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_write; - data_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_data; - tcdm_user_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_meta; + // [LP1] Collapsed: one cacheline-wide port per L2 controller (was a 2-D + // [NumL1CtrlTile][NrTCDMPortsPerCore] fan-in feeding the in-ctrl coalescer). + // data/strb widen from DataWidth to the cacheline (the private L1 already + // coalesced upstream; the L2-side coalescer in the insitu fork is removed). + // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_valid; + // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_ready; + // tcdm_addr_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_addr; + // tcdm_user_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_meta; + // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_write; + // data_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_data; + // strb_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_strb; + // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_valid; + // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_ready; + // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_write; + // data_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_data; + // tcdm_user_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_meta; + logic [NumL1CtrlTile-1:0] cache_req_valid; + logic [NumL1CtrlTile-1:0] cache_req_ready; + tcdm_addr_t [NumL1CtrlTile-1:0] cache_req_addr; + tcdm_user_t [NumL1CtrlTile-1:0] cache_req_meta; + logic [NumL1CtrlTile-1:0] cache_req_write; + cacheline_data_t [NumL1CtrlTile-1:0] cache_req_data; + cacheline_strb_t [NumL1CtrlTile-1:0] cache_req_strb; + + logic [NumL1CtrlTile-1:0] cache_rsp_valid; + logic [NumL1CtrlTile-1:0] cache_rsp_ready; + logic [NumL1CtrlTile-1:0] cache_rsp_write; + cacheline_data_t [NumL1CtrlTile-1:0] cache_rsp_data; + tcdm_user_t [NumL1CtrlTile-1:0] cache_rsp_meta; logic [NumL1CtrlTile-1:0][NumTagBankPerCtrl-1:0] l1_tag_bank_req; logic [NumL1CtrlTile-1:0][NumTagBankPerCtrl-1:0] l1_tag_bank_we; @@ -629,8 +669,13 @@ module cachepool_tile logic [NrTCDMPortsCores-1:0] unmerge_pready; - logic [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_pready, cache_xbar_pready; - logic [NumL1CtrlTile-1:0] cache_amo_pready; + // [LP1] cache_pready stays per-core narrow (LP1 core-side resp-ready, via the + // transpose). cache_xbar_pready is the interco mem-side resp-ready: one per L2 + // controller now. cache_amo_pready unused in the collapsed (AMO-in-L1) path. + // logic [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_pready, cache_xbar_pready; + // logic [NumL1CtrlTile-1:0] cache_amo_pready; + logic [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_pready; + logic [NumL1CtrlTile-1:0] cache_xbar_pready; // ---------------------------------------------------------------------------- // [LP1] Old core<->interco bridge, replaced by the per-core private L1. @@ -806,23 +851,24 @@ module cachepool_tile // response-ready (remote_in_pready) is still gated to prevent draining in-flight // completions during the flush window. - tcdm_req_t [NumRemotePortTile-1:0] remote_req_gated; - tcdm_rsp_t [NumRemotePortTile-1:0] remote_rsp_xbar; + // [LP1] cacheline-wide now; the single L2 plane means the flat index is just the + // remote slot r (no j de-interleave, NumRemotePortTile == NumRemotePortCore). + tcdm_cacheline_req_t [NumRemotePortTile-1:0] remote_req_gated; + tcdm_cacheline_rsp_t [NumRemotePortTile-1:0] remote_rsp_xbar; always_comb begin : remote_flush_protection - for (int j = 0; j < NrTCDMPortsPerCore; j++) begin - for (int r = 0; r < NumRemotePortCore; r++) begin - automatic int unsigned flat = j + r * NrTCDMPortsPerCore; - - remote_req_gated[flat].q = remote_req_i[flat].q; - remote_req_gated[flat].q_valid = remote_req_i[flat].q_valid; - - remote_rsp_o[flat] = remote_rsp_xbar[flat]; - - // Gate response-ready back to us: prevent draining completions - // of requests that arrived just before the flush. - remote_in_pready[flat] = remote_rsp_ready_i[flat] && !l1d_busy_i; - end + // for (int j = 0; j < NrTCDMPortsPerCore; j++) begin + // for (int r = 0; r < NumRemotePortCore; r++) begin + // automatic int unsigned flat = j + r * NrTCDMPortsPerCore; + for (int r = 0; r < NumRemotePortTile; r++) begin + remote_req_gated[r].q = remote_req_i[r].q; + remote_req_gated[r].q_valid = remote_req_i[r].q_valid; + + remote_rsp_o[r] = remote_rsp_xbar[r]; + + // Gate response-ready back to us: prevent draining completions + // of requests that arrived just before the flush. + remote_in_pready[r] = remote_rsp_ready_i[r] && !l1d_busy_i; end end @@ -839,23 +885,28 @@ module cachepool_tile // Same flat layout as remote ports: flat = j + r * NrTCDMPortsPerCore. // Total count: NumRemoteGroupPortCore * NrTCDMPortsPerCore. - localparam int unsigned NumRemoteGroupPortTile = NumRemoteGroupPortCore * NrTCDMPortsPerCore; + // [LP1] Single L2 plane: count drops to NumRemoteGroupPortCore * NumL2Plane, and + // the interco-side signals are cacheline-wide (Option A). The external ports + // (remote_group_req_t) are already cacheline-wide via the pkg typedef. + // localparam int unsigned NumRemoteGroupPortTile = NumRemoteGroupPortCore * NrTCDMPortsPerCore; + localparam int unsigned NumRemoteGroupPortTile = NumRemoteGroupPortCore * NumL2Plane; - // Internal TCDM-style signals going to/from the interco. - tcdm_req_t [NumRemoteGroupPortTile-1:0] rg_interco_in_req; // incoming requests to interco - tcdm_rsp_t [NumRemoteGroupPortTile-1:0] rg_interco_in_rsp; // responses from interco (for incoming) - logic [NumRemoteGroupPortTile-1:0] rg_interco_in_pready; // response ready for incoming + // Internal TCDM-style (cacheline-wide) signals going to/from the interco. + tcdm_cacheline_req_t [NumRemoteGroupPortTile-1:0] rg_interco_in_req; // incoming requests to interco + tcdm_cacheline_rsp_t [NumRemoteGroupPortTile-1:0] rg_interco_in_rsp; // responses from interco (for incoming) + logic [NumRemoteGroupPortTile-1:0] rg_interco_in_pready; // response ready for incoming - tcdm_req_t [NumRemoteGroupPortTile-1:0] rg_interco_out_req; // outgoing requests from interco - tcdm_rsp_t [NumRemoteGroupPortTile-1:0] rg_interco_out_rsp; // responses returning (for outgoing) - logic [NumRemoteGroupPortTile-1:0] rg_interco_out_pready;// response ready for outgoing - remote_tile_sel_t [NumRemoteGroupPortTile-1:0] rg_interco_out_dst; // target tile from interco + tcdm_cacheline_req_t [NumRemoteGroupPortTile-1:0] rg_interco_out_req; // outgoing requests from interco + tcdm_cacheline_rsp_t [NumRemoteGroupPortTile-1:0] rg_interco_out_rsp; // responses returning (for outgoing) + logic [NumRemoteGroupPortTile-1:0] rg_interco_out_pready;// response ready for outgoing + remote_tile_sel_t [NumRemoteGroupPortTile-1:0] rg_interco_out_dst; // target tile from interco if (NumRemoteGroupPortCore > 0) begin : gen_remote_group_ports always_comb begin - for (int j = 0; j < NrTCDMPortsPerCore; j++) begin + // [LP1] j now indexes the (single) L2 plane; flat de-interleave uses NumL2Plane. + for (int j = 0; j < NumL2Plane; j++) begin for (int r = 0; r < NumRemoteGroupPortCore; r++) begin - automatic int unsigned flat = j + r * NrTCDMPortsPerCore; + automatic int unsigned flat = j + r * NumL2Plane; // ----------------------------------------------------------- // Incoming: REQRSP → TCDM conversion → interco @@ -966,23 +1017,23 @@ module cachepool_tile assign rg_interco_out_dst = '0; end - /// Wire requests after strb handling to the cache controller. - /// Each xbar j handles NumRemotePortCore remote slots at flat indices - /// j + r*NrTCDMPortsPerCore for r in [0, NumRemotePortCore). - /// Similarly, each xbar j handles NumRemoteGroupPortCore inter-group remote slots at flat indices - /// j + r*NrTCDMPortsPerCore for r in [0, NumRemoteGroupPortCore). - for (genvar j = 0; j < NrTCDMPortsPerCore; j++) begin : gen_cache_xbar - // Collect the NumRemotePortCore remote slots for this xbar. - tcdm_req_t [NumRemotePortCore-1:0] xbar_remote_req_gated; - tcdm_rsp_t [NumRemotePortCore-1:0] xbar_remote_rsp_xbar; - logic [NumRemotePortCore-1:0] xbar_remote_in_pready; - logic [NumRemotePortCore-1:0] xbar_remote_out_pready; - tcdm_rsp_t [NumRemotePortCore-1:0] xbar_remote_rsp_i; - remote_tile_sel_t [NumRemotePortCore-1:0] xbar_remote_req_dst; - tcdm_req_t [NumRemotePortCore-1:0] xbar_remote_req_o; + /// [LP1] Strategy-B collapse: the 5-plane (NrTCDMPortsPerCore) interco fan-out + /// becomes a SINGLE cacheline-wide plane (NumL2Plane = 1). The core side is now + /// the per-core private-L1 downstreams (lp1_l1_req_unique), and the mem side + /// drives one cacheline port per L2 controller (cache_xbar_*, no plane index). + /// Remote/inter-group slots are de-interleaved by NumL2Plane (so flat = r). + for (genvar j = 0; j < NumL2Plane; j++) begin : gen_cache_xbar + // Collect the NumRemotePortCore remote slots for this plane. + tcdm_cacheline_req_t [NumRemotePortCore-1:0] xbar_remote_req_gated; + tcdm_cacheline_rsp_t [NumRemotePortCore-1:0] xbar_remote_rsp_xbar; + logic [NumRemotePortCore-1:0] xbar_remote_in_pready; + logic [NumRemotePortCore-1:0] xbar_remote_out_pready; + tcdm_cacheline_rsp_t [NumRemotePortCore-1:0] xbar_remote_rsp_i; + remote_tile_sel_t [NumRemotePortCore-1:0] xbar_remote_req_dst; + tcdm_cacheline_req_t [NumRemotePortCore-1:0] xbar_remote_req_o; for (genvar r = 0; r < NumRemotePortCore; r++) begin : gen_remote_slice - localparam int unsigned flat = j + r * NrTCDMPortsPerCore; + localparam int unsigned flat = j + r * NumL2Plane; assign xbar_remote_req_gated [r] = remote_req_gated [flat]; assign xbar_remote_in_pready [r] = remote_in_pready [flat]; assign xbar_remote_rsp_i [r] = remote_rsp_i [flat]; @@ -996,16 +1047,16 @@ module cachepool_tile // When NumRemoteGroupPortCore == 0, no inter-group remote signals exist and the interco is // instantiated without inter-group remote ports (backward-compatible). if (NumRemoteGroupPortCore > 0) begin : gen_remote_group_slice - tcdm_req_t [NumRemoteGroupPortCore-1:0] xbar_remote_group_in_req; - tcdm_rsp_t [NumRemoteGroupPortCore-1:0] xbar_remote_group_in_rsp; - logic [NumRemoteGroupPortCore-1:0] xbar_remote_group_in_pready; - tcdm_req_t [NumRemoteGroupPortCore-1:0] xbar_remote_group_out_req; - tcdm_rsp_t [NumRemoteGroupPortCore-1:0] xbar_remote_group_out_rsp; - logic [NumRemoteGroupPortCore-1:0] xbar_remote_group_out_pready; - remote_tile_sel_t [NumRemoteGroupPortCore-1:0] xbar_remote_group_out_dst; + tcdm_cacheline_req_t [NumRemoteGroupPortCore-1:0] xbar_remote_group_in_req; + tcdm_cacheline_rsp_t [NumRemoteGroupPortCore-1:0] xbar_remote_group_in_rsp; + logic [NumRemoteGroupPortCore-1:0] xbar_remote_group_in_pready; + tcdm_cacheline_req_t [NumRemoteGroupPortCore-1:0] xbar_remote_group_out_req; + tcdm_cacheline_rsp_t [NumRemoteGroupPortCore-1:0] xbar_remote_group_out_rsp; + logic [NumRemoteGroupPortCore-1:0] xbar_remote_group_out_pready; + remote_tile_sel_t [NumRemoteGroupPortCore-1:0] xbar_remote_group_out_dst; for (genvar r = 0; r < NumRemoteGroupPortCore; r++) begin : gen_remote_group_slice_r - localparam int unsigned flat = j + r * NrTCDMPortsPerCore; + localparam int unsigned flat = j + r * NumL2Plane; // Incoming: from conversion/flush → interco input assign xbar_remote_group_in_req [r] = rg_interco_in_req [flat]; assign xbar_remote_group_in_pready [r] = rg_interco_in_pready [flat]; @@ -1017,65 +1068,132 @@ module cachepool_tile assign rg_interco_out_pready [flat] = xbar_remote_group_out_pready[r]; end + // tcdm_cache_interco #( + // .NumTiles (NumTiles ), + // .NumCores (NrCores ), + // .NumCache (NumL1CtrlTile ), + // .NumTotCache (NumL1CacheCtrl ), + // .NumRemotePort (NumRemotePortCore ), + // .NumRemoteGroupPort (NumRemoteGroupPortCore ), + // .NumTilesPerGroup (NumTilesPerGroup ), + // .AddrWidth (TCDMAddrWidth ), + // .TileIDWidth (TileIDWidth ), + // .tcdm_req_t (tcdm_req_t ), + // .tcdm_rsp_t (tcdm_rsp_t ), + // .tcdm_req_chan_t (tcdm_req_chan_t ), + // .tcdm_rsp_chan_t (tcdm_rsp_chan_t ) + // ) i_cache_xbar ( + // .clk_i ( clk_i ), + // .rst_ni ( rst_ni ), + // .tile_id_i ( tile_id_i ), + // .dynamic_offset_i ( dynamic_offset ), + // .private_start_addr_i ( private_start_addr_i ), + // .num_private_cache_i ( num_private_cache ), + // .core_req_i ({xbar_remote_group_in_req, xbar_remote_req_gated, cache_req [j]}), + // .core_rsp_ready_i ({xbar_remote_group_in_pready, xbar_remote_in_pready, cache_pready [j]}), + // .core_rsp_o ({xbar_remote_group_in_rsp, xbar_remote_rsp_xbar, cache_rsp [j]}), + // .tile_sel_o ( xbar_remote_req_dst ), + // .remote_group_sel_o ( xbar_remote_group_out_dst ), + // .mem_req_o ({xbar_remote_group_out_req, xbar_remote_req_o, cache_xbar_req [j]}), + // .mem_rsp_ready_o ({xbar_remote_group_out_pready, xbar_remote_out_pready, cache_xbar_pready[j]}), + // .mem_rsp_i ({xbar_remote_group_out_rsp, xbar_remote_rsp_i, cache_xbar_rsp [j]}) + // ); + + // [LP1] New collapsed, cacheline-wide interco for the single L2 plane. + // Core side : the NumL1CtrlTile per-core private-L1 downstreams + // (lp1_l1_req_unique), already coalesced & id-tagged. + // Mem side : one cacheline port per L2 controller (cache_xbar_*), no + // plane index (NumL2Plane = 1). + // Routing math is identical to before (width-agnostic, Option A); only the + // data/strb width and the port multiplicity change. tcdm_cache_interco #( - .NumTiles (NumTiles ), - .NumCores (NrCores ), - .NumCache (NumL1CtrlTile ), - .NumTotCache (NumL1CacheCtrl ), - .NumRemotePort (NumRemotePortCore ), + .NumTiles (NumTiles ), + .NumCores (NrCores ), + .NumCache (NumL1CtrlTile ), + .NumTotCache (NumL1CacheCtrl ), + .NumRemotePort (NumRemotePortCore ), .NumRemoteGroupPort (NumRemoteGroupPortCore ), - .NumTilesPerGroup (NumTilesPerGroup ), - .AddrWidth (TCDMAddrWidth ), - .TileIDWidth (TileIDWidth ), - .tcdm_req_t (tcdm_req_t ), - .tcdm_rsp_t (tcdm_rsp_t ), - .tcdm_req_chan_t (tcdm_req_chan_t ), - .tcdm_rsp_chan_t (tcdm_rsp_chan_t ) + .NumTilesPerGroup (NumTilesPerGroup ), + .AddrWidth (TCDMAddrWidth ), + .TileIDWidth (TileIDWidth ), + .tcdm_req_t (tcdm_cacheline_req_t ), + .tcdm_rsp_t (tcdm_cacheline_rsp_t ), + .tcdm_req_chan_t (tcdm_cacheline_req_chan_t ), + .tcdm_rsp_chan_t (tcdm_cacheline_rsp_chan_t ) ) i_cache_xbar ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .tile_id_i ( tile_id_i ), - .dynamic_offset_i ( dynamic_offset ), - .private_start_addr_i ( private_start_addr_i ), - .num_private_cache_i ( num_private_cache ), - .core_req_i ({xbar_remote_group_in_req, xbar_remote_req_gated, cache_req [j]}), - .core_rsp_ready_i ({xbar_remote_group_in_pready, xbar_remote_in_pready, cache_pready [j]}), - .core_rsp_o ({xbar_remote_group_in_rsp, xbar_remote_rsp_xbar, cache_rsp [j]}), - .tile_sel_o ( xbar_remote_req_dst ), - .remote_group_sel_o ( xbar_remote_group_out_dst ), - .mem_req_o ({xbar_remote_group_out_req, xbar_remote_req_o, cache_xbar_req [j]}), - .mem_rsp_ready_o ({xbar_remote_group_out_pready, xbar_remote_out_pready, cache_xbar_pready[j]}), - .mem_rsp_i ({xbar_remote_group_out_rsp, xbar_remote_rsp_i, cache_xbar_rsp [j]}) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .tile_id_i ( tile_id_i ), + .dynamic_offset_i ( dynamic_offset ), + .private_start_addr_i ( private_start_addr_i ), + .num_private_cache_i ( num_private_cache ), + .core_req_i ({xbar_remote_group_in_req, xbar_remote_req_gated, lp1_l1_req_unique}), + .core_rsp_ready_i ({xbar_remote_group_in_pready, xbar_remote_in_pready, lp1_l1_rsp_ready }), + .core_rsp_o ({xbar_remote_group_in_rsp, xbar_remote_rsp_xbar, lp1_l1_rsp }), + .tile_sel_o ( xbar_remote_req_dst ), + .remote_group_sel_o ( xbar_remote_group_out_dst ), + .mem_req_o ({xbar_remote_group_out_req, xbar_remote_req_o, cache_xbar_req }), + .mem_rsp_ready_o ({xbar_remote_group_out_pready, xbar_remote_out_pready, cache_xbar_pready}), + .mem_rsp_i ({xbar_remote_group_out_rsp, xbar_remote_rsp_i, cache_xbar_rsp }) ); end else begin : gen_no_remote_group // No inter-group remote ports: instantiate interco without inter-group remote ports (backward-compatible). + // [LP1] Collapsed, cacheline-wide variant. Old narrow/5-plane instance below. + // tcdm_cache_interco #( + // .NumTiles (NumTiles ), + // .NumCores (NrCores ), + // .NumCache (NumL1CtrlTile ), + // .NumTotCache (NumL1CacheCtrl ), + // .NumRemotePort (NumRemotePortCore ), + // .AddrWidth (TCDMAddrWidth ), + // .TileIDWidth (TileIDWidth ), + // .tcdm_req_t (tcdm_req_t ), + // .tcdm_rsp_t (tcdm_rsp_t ), + // .tcdm_req_chan_t (tcdm_req_chan_t ), + // .tcdm_rsp_chan_t (tcdm_rsp_chan_t ) + // ) i_cache_xbar ( + // .clk_i ( clk_i ), + // .rst_ni ( rst_ni ), + // .tile_id_i ( tile_id_i ), + // .dynamic_offset_i ( dynamic_offset ), + // .private_start_addr_i ( private_start_addr_i ), + // .num_private_cache_i ( num_private_cache ), + // .core_req_i ({xbar_remote_req_gated, cache_req [j]} ), + // .core_rsp_ready_i ({xbar_remote_in_pready, cache_pready [j]} ), + // .core_rsp_o ({xbar_remote_rsp_xbar, cache_rsp [j]} ), + // .tile_sel_o ( xbar_remote_req_dst ), + // .remote_group_sel_o ( ), + // .mem_req_o ({xbar_remote_req_o, cache_xbar_req [j]}), + // .mem_rsp_ready_o ({xbar_remote_out_pready, cache_xbar_pready[j]}), + // .mem_rsp_i ({xbar_remote_rsp_i, cache_xbar_rsp [j]}) + // ); tcdm_cache_interco #( - .NumTiles (NumTiles ), - .NumCores (NrCores ), - .NumCache (NumL1CtrlTile ), - .NumTotCache (NumL1CacheCtrl ), - .NumRemotePort (NumRemotePortCore ), - .AddrWidth (TCDMAddrWidth ), - .TileIDWidth (TileIDWidth ), - .tcdm_req_t (tcdm_req_t ), - .tcdm_rsp_t (tcdm_rsp_t ), - .tcdm_req_chan_t (tcdm_req_chan_t ), - .tcdm_rsp_chan_t (tcdm_rsp_chan_t ) + .NumTiles (NumTiles ), + .NumCores (NrCores ), + .NumCache (NumL1CtrlTile ), + .NumTotCache (NumL1CacheCtrl ), + .NumRemotePort (NumRemotePortCore ), + .AddrWidth (TCDMAddrWidth ), + .TileIDWidth (TileIDWidth ), + .tcdm_req_t (tcdm_cacheline_req_t ), + .tcdm_rsp_t (tcdm_cacheline_rsp_t ), + .tcdm_req_chan_t (tcdm_cacheline_req_chan_t ), + .tcdm_rsp_chan_t (tcdm_cacheline_rsp_chan_t ) ) i_cache_xbar ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .tile_id_i ( tile_id_i ), - .dynamic_offset_i ( dynamic_offset ), - .private_start_addr_i ( private_start_addr_i ), - .num_private_cache_i ( num_private_cache ), - .core_req_i ({xbar_remote_req_gated, cache_req [j]} ), - .core_rsp_ready_i ({xbar_remote_in_pready, cache_pready [j]} ), - .core_rsp_o ({xbar_remote_rsp_xbar, cache_rsp [j]} ), - .tile_sel_o ( xbar_remote_req_dst ), - .remote_group_sel_o ( ), - .mem_req_o ({xbar_remote_req_o, cache_xbar_req [j]}), - .mem_rsp_ready_o ({xbar_remote_out_pready, cache_xbar_pready[j]}), - .mem_rsp_i ({xbar_remote_rsp_i, cache_xbar_rsp [j]}) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .tile_id_i ( tile_id_i ), + .dynamic_offset_i ( dynamic_offset ), + .private_start_addr_i ( private_start_addr_i ), + .num_private_cache_i ( num_private_cache ), + .core_req_i ({xbar_remote_req_gated, lp1_l1_req_unique} ), + .core_rsp_ready_i ({xbar_remote_in_pready, lp1_l1_rsp_ready } ), + .core_rsp_o ({xbar_remote_rsp_xbar, lp1_l1_rsp } ), + .tile_sel_o ( xbar_remote_req_dst ), + .remote_group_sel_o ( ), + .mem_req_o ({xbar_remote_req_o, cache_xbar_req } ), + .mem_rsp_ready_o ({xbar_remote_out_pready, cache_xbar_pready} ), + .mem_rsp_i ({xbar_remote_rsp_i, cache_xbar_rsp } ) ); end end @@ -1084,6 +1202,11 @@ module cachepool_tile // Only Snitch will send out amo requests // Ports from Spatz can bypass this module + // [LP1] OLD per-plane AMO + spill structure. Superseded by the single + // cacheline-wide spill path below: the private L1 already coalesced the + // Spatz lanes and handles AMOs (phase 1), so there is one cacheline port per + // L2 controller and the L2-side spatz_cache_amo is bypassed. Kept for ref. + /* for (genvar j = 0; j < NrTCDMPortsPerCore; j++) begin : gen_cache_amo_connect if (j == NrTCDMPortsPerCore-1) begin : gen_amo spatz_cache_amo #( @@ -1199,6 +1322,54 @@ module cachepool_tile end end + */ + + // [LP1] Single cacheline port per L2 controller. A spill register cuts the + // interco -> bank critical path (matching the old timing budget). AMOs are + // serviced upstream in the private L1, so spatz_cache_amo is bypassed here. + tcdm_cacheline_req_t cache_req_reg; + tcdm_cacheline_rsp_t cache_rsp_reg; + + spill_register #( + .T ( tcdm_cacheline_req_chan_t ), + .Bypass ( 1'b0 ) + ) i_spill_reg_cache_req ( + .clk_i , + .rst_ni ( rst_ni ), + .valid_i ( cache_ctrl_req[cb].q_valid ), + .ready_o ( cache_bank_rsp[cb].q_ready ), + .data_i ( cache_ctrl_req[cb].q ), + .valid_o ( cache_req_reg.q_valid ), + .ready_i ( cache_rsp_reg.q_ready ), + .data_o ( cache_req_reg.q ) + ); + + spill_register #( + .T ( tcdm_cacheline_rsp_chan_t ), + .Bypass ( 1'b1 ) + ) i_spill_reg_cache_rsp ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( cache_rsp_reg.p_valid ), + .ready_o ( cache_rsp_ready [cb] ), + .data_i ( cache_rsp_reg.p ), + .valid_o ( cache_bank_rsp [cb].p_valid), + .ready_i ( cache_xbar_pready[cb] ), + .data_o ( cache_bank_rsp [cb].p ) + ); + + assign cache_req_valid[cb] = cache_req_reg.q_valid; + assign cache_req_addr [cb] = cache_req_reg.q.addr; + assign cache_req_meta [cb] = cache_req_reg.q.user; + assign cache_req_write[cb] = cache_req_reg.q.write; + assign cache_req_data [cb] = cache_req_reg.q.data; + assign cache_req_strb [cb] = cache_req_reg.q.strb; + + assign cache_rsp_reg.p_valid = cache_rsp_valid[cb]; + assign cache_rsp_reg.q_ready = cache_req_ready[cb]; + assign cache_rsp_reg.p.data = cache_rsp_data [cb]; + assign cache_rsp_reg.p.user = cache_rsp_meta [cb]; + assign cache_rsp_reg.p.write = cache_rsp_write[cb]; end // Post-xbar flush gate (applied uniformly across all ports). @@ -1206,13 +1377,13 @@ module cachepool_tile // while a flush is in progress, and gates q_ready going back to the interco so the // xbar cannot dequeue a buffered request that is already sitting at its output. always_comb begin : cache_xbar_flush_gate - for (int j = 0; j < NrTCDMPortsPerCore; j++) begin - for (int cb = 0; cb < NumL1CtrlTile; cb++) begin - cache_ctrl_req[j][cb] = cache_xbar_req[j][cb]; - cache_ctrl_req[j][cb].q_valid = cache_xbar_req[j][cb].q_valid && !l1d_busy_i; - cache_xbar_rsp[j][cb] = cache_bank_rsp[j][cb]; - cache_xbar_rsp[j][cb].q_ready = cache_bank_rsp[j][cb].q_ready && !l1d_busy_i; - end + // [LP1] One cacheline port per L2 controller (the NrTCDMPortsPerCore plane + // dimension is gone). + for (int cb = 0; cb < NumL1CtrlTile; cb++) begin + cache_ctrl_req[cb] = cache_xbar_req[cb]; + cache_ctrl_req[cb].q_valid = cache_xbar_req[cb].q_valid && !l1d_busy_i; + cache_xbar_rsp[cb] = cache_bank_rsp[cb]; + cache_xbar_rsp[cb].q_ready = cache_bank_rsp[cb].q_ready && !l1d_busy_i; end end @@ -1357,12 +1528,91 @@ module cachepool_tile assign l1d_insn_ready_o = flush_pending_q && (cache_flush_d == '0); for (genvar cb = 0; cb < NumL1CtrlTile; cb++) begin: gen_l1_cache_ctrl + // cachepool_cache_ctrl #( + // // Core + // .NumPorts (NrTCDMPortsPerCore ), + // .CoalExtFactor (L1CoalFactor ), + // .AddrWidth (L1AddrWidth ), + // .WordWidth (DataWidth ), + // .ByteWidth (8 ), + // .TagWidth (L1TagDataWidth ), + // // Cache + // .NumCacheEntry (L1NumEntryPerCtrl ), + // .CacheLineWidth (L1LineWidth ), + // .SetAssociativity (L1AssoPerCtrl ), + // .BankFactor (L1BankFactor ), + // // .LogDebug (0 ), + // .RefillDataWidth (RefillDataWidth ), + // // Type + // .core_meta_t (tcdm_user_t ), + // .impl_in_t (impl_in_t ), + // .refill_req_t (cache_refill_req_chan_t), + // .refill_rsp_t (cache_refill_rsp_chan_t), + // .burst_req_t (burst_req_t ) + // ) i_l1_controller ( + // .clk_i (clk_i ), + // .rst_ni (rst_ni ), + // .impl_i ('0 ), + // // Sync Control + // .cache_sync_valid_i (ctrl_sync_valid[cb] ), + // .cache_sync_ready_o (ctrl_sync_ready[cb] ), + // .cache_sync_insn_i (ctrl_sync_insn[cb] ), + // // SPM Size + // // The calculation of spm region in cache is different + // // than other modules (needs to times 2) + // // Currently assume full cache + // .bank_depth_for_SPM_i ('0 ), + // // Request + // .core_req_valid_i (cache_req_valid[cb] ), + // .core_req_ready_o (cache_req_ready[cb] ), + // .core_req_addr_i (cache_req_addr [cb] ), + // .core_req_meta_i (cache_req_meta [cb] ), + // .core_req_write_i (cache_req_write[cb] ), + // .core_req_wdata_i (cache_req_data [cb] ), + // .core_req_wstrb_i (cache_req_strb [cb] ), + // // Response + // .core_resp_valid_o (cache_rsp_valid[cb] ), + // .core_resp_ready_i (cache_rsp_ready[cb] ), + // .core_resp_write_o (cache_rsp_write[cb] ), + // .core_resp_data_o (cache_rsp_data [cb] ), + // .core_resp_meta_o (cache_rsp_meta [cb] ), + // // TCDM Refill + // .refill_req_o (cache_refill_req [cb] ), + // .refill_burst_o (cache_refill_burst [cb] ), + // .refill_req_valid_o (cache_refill_req_valid[cb] ), + // .refill_req_ready_i (cache_refill_req_ready[cb] ), + // .refill_rsp_i (cache_refill_rsp [cb] ), + // .refill_rsp_valid_i (cache_refill_rsp_valid[cb] ), + // .refill_rsp_ready_o (cache_refill_rsp_ready[cb] ), + // // Tag Banks + // .tcdm_tag_bank_req_o (l1_tag_bank_req [cb] ), + // .tcdm_tag_bank_we_o (l1_tag_bank_we [cb] ), + // .tcdm_tag_bank_addr_o (l1_tag_bank_addr [cb] ), + // .tcdm_tag_bank_wdata_o (l1_tag_bank_wdata[cb] ), + // .tcdm_tag_bank_be_o (l1_tag_bank_be [cb] ), + // .tcdm_tag_bank_rdata_i (l1_tag_bank_rdata[cb] ), + // // Data Banks + // .tcdm_data_bank_req_o (l1_data_bank_req [cb] ), + // .tcdm_data_bank_we_o (l1_data_bank_we [cb] ), + // .tcdm_data_bank_addr_o (l1_data_bank_addr [cb] ), + // .tcdm_data_bank_wdata_o(l1_data_bank_wdata[cb] ), + // .tcdm_data_bank_be_o (l1_data_bank_be [cb] ), + // .tcdm_data_bank_rdata_i(l1_data_bank_rdata[cb] ), + // .tcdm_data_bank_gnt_i (l1_data_bank_gnt [cb] ) + // ); + + // [LP1] New shared-cache (L2) controller: ONE cacheline-wide core port. + // The private L1 already coalesced the Spatz lanes upstream, so the L2-side + // coalescer (i_par_coalescer_for_spatz) is removed in the insitu fork and + // CoalExtFactor collapses to 1, WordWidth widens to the full cache line. + // The fork's core_req_*/core_resp_* interface must present this single + // cacheline port (the tile drives the scalar cache_req_*/cache_rsp_* below). cachepool_cache_ctrl #( // Core - .NumPorts (NrTCDMPortsPerCore ), - .CoalExtFactor (L1CoalFactor ), + .NumPorts (1 ), + .CoalExtFactor (1 ), .AddrWidth (L1AddrWidth ), - .WordWidth (DataWidth ), + .WordWidth (L1LineWidth ), .ByteWidth (8 ), .TagWidth (L1TagDataWidth ), // Cache @@ -1391,7 +1641,7 @@ module cachepool_tile // than other modules (needs to times 2) // Currently assume full cache .bank_depth_for_SPM_i ('0 ), - // Request + // Request (single cacheline port) .core_req_valid_i (cache_req_valid[cb] ), .core_req_ready_o (cache_req_ready[cb] ), .core_req_addr_i (cache_req_addr [cb] ), From b19ab82533f8d1470a8e9471197bf53e8a2a6a65 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Mon, 22 Jun 2026 17:44:16 +0200 Subject: [PATCH 08/39] [HW] SRAM datawidth matching and noc wrapper adjustments --- Bender.yml | 26 ++++---- hardware/src/cachepool_group_noc_wrapper.sv | 17 +++-- hardware/src/cachepool_pkg.sv | 8 ++- hardware/src/cachepool_tile.sv | 74 +++++++++++++++------ 4 files changed, 86 insertions(+), 39 deletions(-) diff --git a/Bender.yml b/Bender.yml index 7873a05..f27b934 100644 --- a/Bender.yml +++ b/Bender.yml @@ -6,18 +6,20 @@ package: name: cachepool dependencies: - axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } - axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.7.0 } - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.28.0 } - FPnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: pulp-v0.1.3 } - register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 } - riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.7.0 } - tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 } - Insitu-Cache: { git: "https://github.com/pulp-platform/Insitu-Cache.git", rev: zexin/cachepool_dev } - dram_rtl_sim: { git: "https://github.com/pulp-platform/dram_rtl_sim.git", rev: cachepool } - floo_noc: { git: "https://github.com/pulp-platform/FlooNoC.git", rev: main } - cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: main } - spatz: { git: "https://github.com/pulp-platform/spatz.git", rev: cachepool-32b } + axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } + axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.7.0 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.28.0 } + FPnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: pulp-v0.1.3 } + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 } + riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.7.0 } + tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 } + # Insitu-Cache: { git: "https://github.com/pulp-platform/Insitu-Cache.git", rev: zexin/cachepool_dev } + Insitu-Cache: { git: "https://github.com/HHT1228/Insitu-Cache.git", rev: hohung-multi-tile } + hpdcache: { git: "https://github.com/HHT1228/cv-hpdcache", rev: cachepool/no_coherence } + dram_rtl_sim: { git: "https://github.com/pulp-platform/dram_rtl_sim.git", rev: cachepool } + floo_noc: { git: "https://github.com/pulp-platform/FlooNoC.git", rev: main } + cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: main } + spatz: { git: "https://github.com/pulp-platform/spatz.git", rev: cachepool-32b } workspace: checkout_dir: "./hardware/deps" diff --git a/hardware/src/cachepool_group_noc_wrapper.sv b/hardware/src/cachepool_group_noc_wrapper.sv index 85ea868..28a31ed 100644 --- a/hardware/src/cachepool_group_noc_wrapper.sv +++ b/hardware/src/cachepool_group_noc_wrapper.sv @@ -104,8 +104,12 @@ module cachepool_group_noc_wrapper // ------------------------------------------------------------------------- // Localparams // ------------------------------------------------------------------------- + // [LP1] Strategy-B collapse: inter-group ports no longer fan out per TCDM plane; + // the per-tile count is NumRemoteGroupPortCore * NumL2Plane (matches cachepool_group). + // localparam int unsigned NumRemoteGroupPortTile = (NumRemoteGroupPortCore == 0) ? 1 + // : NumRemoteGroupPortCore * NrTCDMPortsPerCore; localparam int unsigned NumRemoteGroupPortTile = (NumRemoteGroupPortCore == 0) ? 1 - : NumRemoteGroupPortCore * NrTCDMPortsPerCore; + : NumRemoteGroupPortCore * NumL2Plane; localparam int unsigned NumRemoteGroupPortGroup = NumRemoteGroupPortTile * NumTilesPerGroup; localparam int unsigned NumNoCPortsGroup = NumNoCPortsPerTile * NumTilesPerGroup; localparam int unsigned SlvXbarSelW = (NumRemoteGroupPortGroup > 1) ? $clog2(NumRemoteGroupPortGroup) : 1; @@ -242,15 +246,16 @@ module cachepool_group_noc_wrapper assign mst_xbar_mst_sel[n] = eject_rsp[noc_port].hdr.src_port_id; end - // Static port-to-NoC-channel mapping: each flat port p has xbar index - // j = p % NrTCDMPortsPerCore, and is steered to NoC channel j % NumNoCPortsPerTile. - // Spatz ports (j=0..NrTCDMPortsPerCore-2) divide evenly across channels; - // Snitch (j=NrTCDMPortsPerCore-1) maps by the same modulo. + // [LP1] Static port-to-NoC-channel mapping. After the Strategy-B collapse the + // tile emits NumRemoteGroupPortCore * NumL2Plane inter-group ports; the L2 + // plane index is p % NumL2Plane, steered to NoC channel (plane % NumNoCPortsPerTile). + // (With NumL2Plane == 1 every port maps to channel 0.) localparam int unsigned NocMstSelWidth = (NumNoCPortsPerTile > 1) ? $clog2(NumNoCPortsPerTile) : 1; logic [NumRemoteGroupPortTile-1:0][NocMstSelWidth-1:0] noc_mst_sel; for (genvar p = 0; p < NumRemoteGroupPortTile; p++) begin : gen_noc_mst_sel - assign noc_mst_sel[p] = NocMstSelWidth'((p % NrTCDMPortsPerCore) % NumNoCPortsPerTile); + // assign noc_mst_sel[p] = NocMstSelWidth'((p % NrTCDMPortsPerCore) % NumNoCPortsPerTile); + assign noc_mst_sel[p] = NocMstSelWidth'((p % NumL2Plane) % NumNoCPortsPerTile); end reqrsp_xbar #( diff --git a/hardware/src/cachepool_pkg.sv b/hardware/src/cachepool_pkg.sv index 363358d..20607fa 100644 --- a/hardware/src/cachepool_pkg.sv +++ b/hardware/src/cachepool_pkg.sv @@ -163,7 +163,13 @@ package cachepool_pkg; localparam int unsigned NumL1CtrlTile = NumL1CacheCtrl / NumTiles; // Number of data banks assigned to each cache controller - localparam int unsigned NumDataBankPerCtrl = (L1LineWidth / SpatzDataWidth) * L1AssoPerCtrl * L1BankFactor; + // [LP1] Cacheline-granular L2: each data bank now holds a FULL cache line (the + // L2 ctrl uses WordWidth = CacheLineWidth), so the per-line word count + // (L1LineWidth/SpatzDataWidth = NumWordPerLine) is absorbed into the bank width + // and dropped from the bank count. Banks = SetAssoc * BankFactor, matching the + // ctrl's [SetAssociativity][NumDataBankPerWay=BankFactor] ports 1:1. + // localparam int unsigned NumDataBankPerCtrl = (L1LineWidth / SpatzDataWidth) * L1AssoPerCtrl * L1BankFactor; + localparam int unsigned NumDataBankPerCtrl = L1AssoPerCtrl * L1BankFactor; // Number of tag banks assigned to each cache controller localparam int unsigned NumTagBankPerCtrl = L1AssoPerCtrl * L1BankFactor; // Number of entries of L1 Cache (total number across multiple cache controllers) diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index 1d91ad4..e083de1 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -602,12 +602,18 @@ module cachepool_tile logic [NumL1CtrlTile-1:0][NumTagBankPerCtrl-1:0] l1_tag_bank_be; tag_data_t [NumL1CtrlTile-1:0][NumTagBankPerCtrl-1:0] l1_tag_bank_rdata; + // [LP1] Cacheline-granular L2 data banks: NumDataBankPerCtrl is now SetAssoc*BankFactor + // banks, each holding a full cache line. req/we/addr/gnt stay 1-per-bank; wdata/rdata + // widen to a cache line and be becomes a cacheline byte-mask. logic [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_req; logic [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_we; tcdm_bank_addr_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_addr; - data_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_wdata; - logic [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0][DataWidth/8-1:0] l1_data_bank_be; - data_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_rdata; + // data_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_wdata; + // logic [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0][DataWidth/8-1:0] l1_data_bank_be; + // data_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_rdata; + cacheline_data_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_wdata; + logic [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0][L1LineWidth/8-1:0] l1_data_bank_be; + cacheline_data_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_rdata; logic [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_gnt; tcdm_bank_addr_t cfg_spm_size; @@ -1802,16 +1808,11 @@ module cachepool_tile ); end - // TODO: Should we use a single large bank or multiple narrow ones? - for (genvar bank = 0; bank < (NumDataBankPerCtrl/NumWordPerLine); - bank++) begin : gen_l1_data_banks - localparam int unsigned BaseIdx = bank * NumWordPerLine; - logic [NumWordPerLine*WordBytes-1:0] bank_be; - - for (genvar w = 0; w < NumWordPerLine; w++) begin : gen_bank_be - assign bank_be[w*WordBytes +: WordBytes] = l1_data_bank_be[cb][BaseIdx + w]; - end - + // [LP1] Cacheline-granular: each bank is directly one cacheline-wide SRAM + // (NumDataBankPerCtrl == SetAssoc*BankFactor now), matching the L2 ctrl's + // per-bank cacheline ports. The old NumWordPerLine grouping (which packed + // narrow per-word entries into a cacheline SRAM) is no longer needed. + for (genvar bank = 0; bank < NumDataBankPerCtrl; bank++) begin : gen_l1_data_banks tc_sram_impl #( .NumWords (L1CacheWayEntry/L1BankFactor), .DataWidth (L1LineWidth), @@ -1824,17 +1825,50 @@ module cachepool_tile .rst_ni (rst_ni ), .impl_i ('0 ), .impl_o (/* unused */ ), - .req_i ( l1_data_bank_req [cb][BaseIdx] ), - .we_i ( l1_data_bank_we [cb][BaseIdx] ), - .addr_i ( l1_data_bank_addr [cb][BaseIdx] ), - .wdata_i( l1_data_bank_wdata[cb][BaseIdx+:NumWordPerLine]), - .be_i ( bank_be ), - .rdata_o( l1_data_bank_rdata[cb][BaseIdx+:NumWordPerLine]) + .req_i ( l1_data_bank_req [cb][bank] ), + .we_i ( l1_data_bank_we [cb][bank] ), + .addr_i ( l1_data_bank_addr [cb][bank] ), + .wdata_i( l1_data_bank_wdata[cb][bank] ), // full cache line + .be_i ( l1_data_bank_be [cb][bank] ), // cacheline byte-mask + .rdata_o( l1_data_bank_rdata[cb][bank] ) ); - assign l1_data_bank_gnt[cb][BaseIdx+:NumWordPerLine] = {NumWordPerLine{1'b1}}; + assign l1_data_bank_gnt[cb][bank] = 1'b1; end + // TODO: Should we use a single large bank or multiple narrow ones? + // for (genvar bank = 0; bank < (NumDataBankPerCtrl/NumWordPerLine); + // bank++) begin : gen_l1_data_banks + // localparam int unsigned BaseIdx = bank * NumWordPerLine; + // logic [NumWordPerLine*WordBytes-1:0] bank_be; + + // for (genvar w = 0; w < NumWordPerLine; w++) begin : gen_bank_be + // assign bank_be[w*WordBytes +: WordBytes] = l1_data_bank_be[cb][BaseIdx + w]; + // end + + // tc_sram_impl #( + // .NumWords (L1CacheWayEntry/L1BankFactor), + // .DataWidth (L1LineWidth), + // .ByteWidth (8 ), + // .NumPorts (1 ), + // .Latency (1 ), + // .SimInit ("zeros" ) + // ) i_data_bank ( + // .clk_i (clk_i ), + // .rst_ni (rst_ni ), + // .impl_i ('0 ), + // .impl_o (/* unused */ ), + // .req_i ( l1_data_bank_req [cb][BaseIdx] ), + // .we_i ( l1_data_bank_we [cb][BaseIdx] ), + // .addr_i ( l1_data_bank_addr [cb][BaseIdx] ), + // .wdata_i( l1_data_bank_wdata[cb][BaseIdx+:NumWordPerLine]), + // .be_i ( bank_be ), + // .rdata_o( l1_data_bank_rdata[cb][BaseIdx+:NumWordPerLine]) + // ); + + // assign l1_data_bank_gnt[cb][BaseIdx+:NumWordPerLine] = {NumWordPerLine{1'b1}}; + // end + // for (genvar j = 0; j < NumDataBankPerCtrl; j++) begin : gen_l1_data_banks // tc_sram_impl #( // .NumWords (L1CacheWayEntry/L1BankFactor), From 79c44e9e27da4f9332411c3851be0502e4d0652b Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Tue, 23 Jun 2026 15:37:28 +0200 Subject: [PATCH 09/39] Private L1 bender and dep setup and portid_t matching, sim clear --- Bender.local | 3 ++- Bender.lock | 16 +++++++++++----- Bender.yml | 4 +++- hardware/src/cachepool_pkg.sv | 13 ++++++++++++- 4 files changed, 28 insertions(+), 8 deletions(-) diff --git a/Bender.local b/Bender.local index 7af084b..2ff8279 100644 --- a/Bender.local +++ b/Bender.local @@ -5,5 +5,6 @@ overrides: axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 } - Insitu-Cache: { git: "https://github.com/pulp-platform/Insitu-Cache.git", rev: zexin/cachepool_dev } + Insitu-Cache: { path: "../Insitu-Cache" } + hpdcache: { path: "../cv-hpdcache" } diff --git a/Bender.lock b/Bender.lock index 62bfa1f..0b95bc1 100644 --- a/Bender.lock +++ b/Bender.lock @@ -63,7 +63,7 @@ packages: dependencies: - axi floo_noc: - revision: 97306733f33acbb646c7e403c03a674fc1404b44 + revision: f7f81e2c65c231a8fab4cf8a6e6cd2aa3efdcdb6 version: null source: Git: https://github.com/pulp-platform/FlooNoC.git @@ -96,6 +96,12 @@ packages: Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git dependencies: - common_cells + hpdcache: + revision: null + version: null + source: + Path: ../cv-hpdcache + dependencies: [] idma: revision: 28a36e5e07705549e59fc33db96ab681bc1ca88e version: 0.6.5 @@ -109,10 +115,10 @@ packages: - obi - register_interface insitu-cache: - revision: fa761ddebc946f9b46509d84945bf41ee1a9ec49 + revision: null version: null source: - Git: https://github.com/pulp-platform/Insitu-Cache.git + Path: ../Insitu-Cache dependencies: - axi - common_cells @@ -150,10 +156,10 @@ packages: dependencies: - tech_cells_generic spatz: - revision: 944e9042379fbe1db69567655cffd7a2e260ff16 + revision: null version: null source: - Git: https://github.com/pulp-platform/spatz.git + Path: hardware/deps/spatz dependencies: - axi - axi_riscv_atomics diff --git a/Bender.yml b/Bender.yml index f27b934..ecb880c 100644 --- a/Bender.yml +++ b/Bender.yml @@ -15,7 +15,7 @@ dependencies: tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 } # Insitu-Cache: { git: "https://github.com/pulp-platform/Insitu-Cache.git", rev: zexin/cachepool_dev } Insitu-Cache: { git: "https://github.com/HHT1228/Insitu-Cache.git", rev: hohung-multi-tile } - hpdcache: { git: "https://github.com/HHT1228/cv-hpdcache", rev: cachepool/no_coherence } + hpdcache: { git: "https://github.com/HHT1228/cv-hpdcache.git", rev: cachepool/no_coherence } dram_rtl_sim: { git: "https://github.com/pulp-platform/dram_rtl_sim.git", rev: cachepool } floo_noc: { git: "https://github.com/pulp-platform/FlooNoC.git", rev: main } cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: main } @@ -43,6 +43,8 @@ sources: # Level 1 - hardware/src/cachepool_pkg.sv - hardware/src/cachepool_cc.sv + # Private L1 data cache (per-core HPDcache wrapper) — must precede the tile + - hardware/src/cachepool_l1_ctrl.sv # Barrier - hardware/src/cachepool_tile_barrier.sv - hardware/src/cachepool_cluster_barrier.sv diff --git a/hardware/src/cachepool_pkg.sv b/hardware/src/cachepool_pkg.sv index 20607fa..8953825 100644 --- a/hardware/src/cachepool_pkg.sv +++ b/hardware/src/cachepool_pkg.sv @@ -458,7 +458,18 @@ package cachepool_pkg; /////////////////// typedef logic [RemoteXbarSelWidth-1:0] remote_xbar_sel_t; - typedef logic [$clog2(NrTCDMPortsPerCore)-1:0] portid_t; + // [LP1] port_id / src_port_id index a remote-group port within a tile, so the + // correct width is $clog2(NumRemoteGroupPortTile). Pre-collapse that equalled + // NrTCDMPortsPerCore (=5); after the Strategy-B collapse the governing count is + // NumRemoteGroupPortCore * NumL2Plane (mirrors the per-module NumRemoteGroupPortTile + // localparams). NrTCDMPortsPerCore here over-sized portid_t to 3 bits and tripped + // vsim-3015 (PCDPC) at the uncast master-xbar select connections. + // Distinct name from the per-module NumRemoteGroupPortTile localparams to avoid + // a wildcard-import override warning; same value by construction. + localparam int unsigned PortIdPortCount = (NumRemoteGroupPortCore == 0) + ? 1 : NumRemoteGroupPortCore * NumL2Plane; + // typedef logic [$clog2(NrTCDMPortsPerCore)-1:0] portid_t; + typedef logic [((PortIdPortCount > 1) ? $clog2(PortIdPortCount) : 1)-1:0] portid_t; typedef struct packed { logic [CoreIDWidth-1:0] core_id; From 41a4a291b8db03ad38af475914058eaf8547f6c2 Mon Sep 17 00:00:00 2001 From: Diyou Shen Date: Mon, 15 Jun 2026 16:27:28 +0200 Subject: [PATCH 10/39] [Periph] Clean up unused register. --- .../cachepool_peripheral.sv | 30 +- .../cachepool_peripheral_reg.hjson | 86 ++---- .../cachepool_peripheral_reg_pkg.sv | 124 +++----- .../cachepool_peripheral_reg_top.sv | 285 ++++++------------ hardware/src/cachepool_cluster.sv | 7 +- .../snRuntime/include/cachepool_peripheral.h | 78 ++--- software/snRuntime/include/l1cache.h | 4 +- software/snRuntime/include/snrt.h | 5 - software/snRuntime/src/interrupt.c | 3 +- software/snRuntime/src/l1cache.c | 20 +- .../snRuntime/src/platforms/shared/start.c | 3 - software/tests/load-store/main.c | 6 +- 12 files changed, 222 insertions(+), 429 deletions(-) diff --git a/hardware/cachepool_peripheral/cachepool_peripheral.sv b/hardware/cachepool_peripheral/cachepool_peripheral.sv index d539b76..8077342 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral.sv +++ b/hardware/cachepool_peripheral/cachepool_peripheral.sv @@ -18,8 +18,6 @@ module cachepool_peripheral parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, parameter type cache_insn_t = logic, - // Nr of course in the cluster - parameter logic [31:0] NrCores = 0, /// Derived parameter *Do not override* parameter type addr_t = logic [AddrWidth-1:0], parameter type spm_size_t = logic [SPMWidth-1:0] @@ -35,7 +33,6 @@ module cachepool_peripheral input addr_t tcdm_end_address_i, output addr_t private_start_addr_o, output logic icache_prefetch_enable_o, - output logic [NrCores-1:0] cl_clint_o, output logic cluster_probe_o, input logic [9:0] cluster_hart_base_id_i, /// For cache xbar dynamic configuration @@ -88,8 +85,6 @@ module cachepool_peripheral //////////// L1 DCache //////////// - logic [NumPerfCounters-1:0][47:0] perf_counter_d, perf_counter_q; - logic [NrCores-1:0] cl_clint_d, cl_clint_q; logic [9:0] l1d_spm_size_d, l1d_spm_size_q; logic [3:0] l1d_private_d, l1d_private_q; addr_t private_start_addr_d, private_start_addr_q; @@ -126,6 +121,16 @@ module cachepool_peripheral assign l1d_private_o = l1d_private_q; assign private_start_addr_o = private_start_addr_q; + // Concatenate all tile-select register words into one wide vector and slice + // to NumTiles. Unused upper bits (for small configs) are optimised away. + localparam int unsigned NumTileSelWords = cachepool_peripheral_reg_pkg::NumTileSelRegs; + logic [NumTileSelWords*32-1:0] tile_sel_raw; + always_comb begin : tile_sel_concat + for (int i = 0; i < NumTileSelWords; i++) begin + tile_sel_raw[i*32 +: 32] = reg2hw.cfg_l1d_tile_sel[i].q; + end + end + // Cache Flush Controller // Operates at tile granularity. l1d_lock_q[t] is set when tile t is // issued an instruction and cleared when tile t returns ready. @@ -151,7 +156,7 @@ module cachepool_peripheral // For non-private modes (shared/all/init), tile_sel is forced to '1. l1d_insn_o.insn = reg2hw.cfg_l1d_insn.q; l1d_insn_o.tile_sel = (reg2hw.cfg_l1d_insn.q == 2'b00) - ? reg2hw.cfg_l1d_tile_sel.q[NumTiles-1:0] + ? tile_sel_raw[NumTiles-1:0] : {NumTiles{1'b1}}; l1d_insn_valid_o = 1'b1; // Lock only the tiles that will receive the instruction. @@ -178,19 +183,6 @@ module cachepool_peripheral assign hw2reg.l1d_flush_status.d = (l1d_lock_q != '0); // assign l1d_busy_o = (l1d_lock_q != '0); - // Wake-up logic: Bits in cl_clint_q can be set/cleared with writes to - // cl_clint_set/cl_clint_clear - always_comb begin - cl_clint_d = cl_clint_q; - if (reg2hw.cl_clint_set.qe) begin - cl_clint_d = cl_clint_q | reg2hw.cl_clint_set.q; - end else if (reg2hw.cl_clint_clear.qe) begin - cl_clint_d = cl_clint_q & ~reg2hw.cl_clint_clear.q; - end - end - `FF(cl_clint_q, cl_clint_d, '0, clk_i, rst_ni) - assign cl_clint_o = cl_clint_q[NrCores-1:0]; - // Enable icache prefetch assign icache_prefetch_enable_o = reg2hw.icache_prefetch_enable.q; diff --git a/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson b/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson index 79d7cda..870963a 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson +++ b/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson @@ -4,8 +4,8 @@ // Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details. { param_list: [ - { name: "NumPerfCounters", - desc: "Number of performance counters", + { name: "NumTileSelRegs", + desc: "Number of 32-bit tile-select registers. Default 2 covers up to 64 tiles (16 groups x 4 tiles).", type: "int", default: "2" }, @@ -17,59 +17,6 @@ ] regwidth: 32, registers: [ - { - multireg: { - name: "HART_SELECT", - desc: '''Select from which hart in the cluster, starting from `0`, - the event should be counted. For each performance counter - the cores can be selected individually. If a hart greater - than the clusters total hart size is selected the selection - will wrap and the hart corresponding to `hart_select % total_harts_in_cluster` - will be selected.''' - swaccess: "rw", - hwaccess: "hro", - count: "NumPerfCounters", - cname: "hart_select", - compact: "false", - fields: [{ - bits: "9:0", - name: "HART_SELECT", - desc: "Select source of per-hart performance counter" - }] - } - }, - { - name: "CL_CLINT_SET", - desc: ''' - Set bits in the cluster-local CLINT. Writing a 1 at location i sets the cluster-local interrupt - of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID. - ''' - hwext: "true", - hwqe: "true", - swaccess: "wo", - hwaccess: "hro", - fields: [{ - bits: "31:0", - name: "CL_CLINT_SET", - desc: "Set cluster-local interrupt of hart i" - }] - }, - { - name: "CL_CLINT_CLEAR", - desc: ''' - Clear bits in the cluster-local CLINT. Writing a 1 at location i clears the cluster-local interrupt - of hart i, where i is relative to the first hart in the cluster, ignoring the cluster base hart ID. - ''' - hwext: "true", - hwqe: "true", - swaccess: "wo", - hwaccess: "hro", - fields: [{ - bits: "31:0", - name: "CL_CLINT_CLEAR", - desc: "Clear cluster-local interrupt of hart i" - }] - }, { name: "HW_BARRIER", desc: '''Hardware barrier register. Loads to this register will block until all cores have @@ -173,18 +120,23 @@ }] }, { - name: "CFG_L1D_TILE_SEL", - desc: '''Controls Tiles to be flushed''' - // hwext: "true", - // hwqe: "true", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - fields: [{ - bits: "31:0", - name: "TILE", - desc: "Select the tile to be flush, only used in private partition flush." - }] + multireg: { + name: "CFG_L1D_TILE_SEL", + desc: '''One-hot tile selection mask for private-partition flush. + Each 32-bit register covers 32 tiles: register 0 → tiles 0-31, + register 1 → tiles 32-63. Only used when CFG_L1D_INSN == 2'b00.''' + swaccess: "rw", + hwaccess: "hro", + count: "NumTileSelRegs", + cname: "cfg_l1d_tile_sel", + compact: "false", + resval: "0", + fields: [{ + bits: "31:0", + name: "TILE", + desc: "Tile select bits for this 32-tile bank." + }] + } }, { name: "L1D_SPM_COMMIT", diff --git a/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv b/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv index df8c6e6..7afdf12 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv +++ b/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv @@ -7,7 +7,7 @@ package cachepool_peripheral_reg_pkg; // Param list - parameter int NumPerfCounters = 2; + parameter int NumTileSelRegs = 2; // Address widths within the block parameter int BlockAw = 7; @@ -16,20 +16,6 @@ package cachepool_peripheral_reg_pkg; // Typedefs for registers // //////////////////////////// - typedef struct packed { - logic [9:0] q; - } cachepool_peripheral_reg2hw_hart_select_mreg_t; - - typedef struct packed { - logic [31:0] q; - logic qe; - } cachepool_peripheral_reg2hw_cl_clint_set_reg_t; - - typedef struct packed { - logic [31:0] q; - logic qe; - } cachepool_peripheral_reg2hw_cl_clint_clear_reg_t; - typedef struct packed { logic [31:0] q; } cachepool_peripheral_reg2hw_hw_barrier_reg_t; @@ -64,7 +50,7 @@ package cachepool_peripheral_reg_pkg; typedef struct packed { logic [31:0] q; - } cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_reg_t; + } cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_mreg_t; typedef struct packed { logic q; @@ -115,18 +101,15 @@ package cachepool_peripheral_reg_pkg; // Register -> HW type typedef struct packed { - cachepool_peripheral_reg2hw_hart_select_mreg_t [1:0] hart_select; // [275:256] - cachepool_peripheral_reg2hw_cl_clint_set_reg_t cl_clint_set; // [255:223] - cachepool_peripheral_reg2hw_cl_clint_clear_reg_t cl_clint_clear; // [222:190] - cachepool_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [189:158] - cachepool_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [157:157] - cachepool_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [156:156] - cachepool_peripheral_reg2hw_spatz_cycle_reg_t spatz_cycle; // [155:124] - cachepool_peripheral_reg2hw_cluster_boot_control_reg_t cluster_boot_control; // [123:92] - cachepool_peripheral_reg2hw_cluster_eoc_exit_reg_t cluster_eoc_exit; // [91:88] - cachepool_peripheral_reg2hw_cfg_l1d_spm_reg_t cfg_l1d_spm; // [87:78] - cachepool_peripheral_reg2hw_cfg_l1d_insn_reg_t cfg_l1d_insn; // [77:76] - cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_reg_t cfg_l1d_tile_sel; // [75:44] + cachepool_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [221:190] + cachepool_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [189:189] + cachepool_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [188:188] + cachepool_peripheral_reg2hw_spatz_cycle_reg_t spatz_cycle; // [187:156] + cachepool_peripheral_reg2hw_cluster_boot_control_reg_t cluster_boot_control; // [155:124] + cachepool_peripheral_reg2hw_cluster_eoc_exit_reg_t cluster_eoc_exit; // [123:120] + cachepool_peripheral_reg2hw_cfg_l1d_spm_reg_t cfg_l1d_spm; // [119:110] + cachepool_peripheral_reg2hw_cfg_l1d_insn_reg_t cfg_l1d_insn; // [109:108] + cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_mreg_t [1:0] cfg_l1d_tile_sel; // [107:44] cachepool_peripheral_reg2hw_l1d_spm_commit_reg_t l1d_spm_commit; // [43:43] cachepool_peripheral_reg2hw_l1d_insn_commit_reg_t l1d_insn_commit; // [42:42] cachepool_peripheral_reg2hw_l1d_private_reg_t l1d_private; // [41:38] @@ -145,40 +128,31 @@ package cachepool_peripheral_reg_pkg; } cachepool_peripheral_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_HART_SELECT_0_OFFSET = 7'h 0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_HART_SELECT_1_OFFSET = 7'h 4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CL_CLINT_SET_OFFSET = 7'h 8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CL_CLINT_CLEAR_OFFSET = 7'h c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET = 7'h 10; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 7'h 14; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET = 7'h 18; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET = 7'h 1c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET = 7'h 20; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET = 7'h 24; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET = 7'h 28; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET = 7'h 2c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_OFFSET = 7'h 30; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET = 7'h 34; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET = 7'h 38; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET = 7'h 3c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET = 7'h 40; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET = 7'h 44; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET = 7'h 48; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET = 7'h 4c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET = 7'h 40; // Reset values for hwext registers and their fields - parameter logic [31:0] CACHEPOOL_PERIPHERAL_CL_CLINT_SET_RESVAL = 32'h 0; - parameter logic [31:0] CACHEPOOL_PERIPHERAL_CL_CLINT_CLEAR_RESVAL = 32'h 0; parameter logic [31:0] CACHEPOOL_PERIPHERAL_HW_BARRIER_RESVAL = 32'h 0; parameter logic [0:0] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_RESVAL = 1'h 0; parameter logic [0:0] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_STATUS_RESVAL = 1'h 0; // Register index typedef enum int { - CACHEPOOL_PERIPHERAL_HART_SELECT_0, - CACHEPOOL_PERIPHERAL_HART_SELECT_1, - CACHEPOOL_PERIPHERAL_CL_CLINT_SET, - CACHEPOOL_PERIPHERAL_CL_CLINT_CLEAR, CACHEPOOL_PERIPHERAL_HW_BARRIER, CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE, CACHEPOOL_PERIPHERAL_SPATZ_STATUS, @@ -187,7 +161,8 @@ package cachepool_peripheral_reg_pkg; CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT, CACHEPOOL_PERIPHERAL_CFG_L1D_SPM, CACHEPOOL_PERIPHERAL_CFG_L1D_INSN, - CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL, + CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0, + CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1, CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT, CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT, CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS, @@ -198,27 +173,24 @@ package cachepool_peripheral_reg_pkg; } cachepool_peripheral_id_e; // Register width information to check illegal writes - parameter logic [3:0] CACHEPOOL_PERIPHERAL_PERMIT [20] = '{ - 4'b 0011, // index[ 0] CACHEPOOL_PERIPHERAL_HART_SELECT_0 - 4'b 0011, // index[ 1] CACHEPOOL_PERIPHERAL_HART_SELECT_1 - 4'b 1111, // index[ 2] CACHEPOOL_PERIPHERAL_CL_CLINT_SET - 4'b 1111, // index[ 3] CACHEPOOL_PERIPHERAL_CL_CLINT_CLEAR - 4'b 1111, // index[ 4] CACHEPOOL_PERIPHERAL_HW_BARRIER - 4'b 0001, // index[ 5] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE - 4'b 0001, // index[ 6] CACHEPOOL_PERIPHERAL_SPATZ_STATUS - 4'b 1111, // index[ 7] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE - 4'b 1111, // index[ 8] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL - 4'b 0001, // index[ 9] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT - 4'b 0011, // index[10] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM - 4'b 0001, // index[11] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN - 4'b 1111, // index[12] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL - 4'b 0001, // index[13] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT - 4'b 0001, // index[14] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT - 4'b 0001, // index[15] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS - 4'b 0001, // index[16] CACHEPOOL_PERIPHERAL_L1D_PRIVATE - 4'b 1111, // index[17] CACHEPOOL_PERIPHERAL_L1D_ADDR - 4'b 0001, // index[18] CACHEPOOL_PERIPHERAL_XBAR_OFFSET - 4'b 0001 // index[19] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT + parameter logic [3:0] CACHEPOOL_PERIPHERAL_PERMIT [17] = '{ + 4'b 1111, // index[ 0] CACHEPOOL_PERIPHERAL_HW_BARRIER + 4'b 0001, // index[ 1] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE + 4'b 0001, // index[ 2] CACHEPOOL_PERIPHERAL_SPATZ_STATUS + 4'b 1111, // index[ 3] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE + 4'b 1111, // index[ 4] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL + 4'b 0001, // index[ 5] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT + 4'b 0011, // index[ 6] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM + 4'b 0001, // index[ 7] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN + 4'b 1111, // index[ 8] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0 + 4'b 1111, // index[ 9] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1 + 4'b 0001, // index[10] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT + 4'b 0001, // index[11] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT + 4'b 0001, // index[12] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS + 4'b 0001, // index[13] CACHEPOOL_PERIPHERAL_L1D_PRIVATE + 4'b 1111, // index[14] CACHEPOOL_PERIPHERAL_L1D_ADDR + 4'b 0001, // index[15] CACHEPOOL_PERIPHERAL_XBAR_OFFSET + 4'b 0001 // index[16] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT }; endpackage diff --git a/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv b/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv index c6ece73..723cf3f 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv +++ b/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv @@ -68,16 +68,6 @@ module cachepool_peripheral_reg_top #( // Define SW related signals // Format: __{wd|we|qs} // or _{wd|we|qs} if field == 1 or 0 - logic [9:0] hart_select_0_qs; - logic [9:0] hart_select_0_wd; - logic hart_select_0_we; - logic [9:0] hart_select_1_qs; - logic [9:0] hart_select_1_wd; - logic hart_select_1_we; - logic [31:0] cl_clint_set_wd; - logic cl_clint_set_we; - logic [31:0] cl_clint_clear_wd; - logic cl_clint_clear_we; logic [31:0] hw_barrier_qs; logic hw_barrier_re; logic icache_prefetch_enable_wd; @@ -99,9 +89,12 @@ module cachepool_peripheral_reg_top #( logic [1:0] cfg_l1d_insn_qs; logic [1:0] cfg_l1d_insn_wd; logic cfg_l1d_insn_we; - logic [31:0] cfg_l1d_tile_sel_qs; - logic [31:0] cfg_l1d_tile_sel_wd; - logic cfg_l1d_tile_sel_we; + logic [31:0] cfg_l1d_tile_sel_0_qs; + logic [31:0] cfg_l1d_tile_sel_0_wd; + logic cfg_l1d_tile_sel_0_we; + logic [31:0] cfg_l1d_tile_sel_1_qs; + logic [31:0] cfg_l1d_tile_sel_1_wd; + logic cfg_l1d_tile_sel_1_we; logic l1d_spm_commit_qs; logic l1d_spm_commit_wd; logic l1d_spm_commit_we; @@ -124,94 +117,6 @@ module cachepool_peripheral_reg_top #( logic xbar_offset_commit_we; // Register instances - - // Subregister 0 of Multireg hart_select - // R[hart_select_0]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_0_we), - .wd (hart_select_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[0].q ), - - // to register interface (read) - .qs (hart_select_0_qs) - ); - - // Subregister 1 of Multireg hart_select - // R[hart_select_1]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_1_we), - .wd (hart_select_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[1].q ), - - // to register interface (read) - .qs (hart_select_1_qs) - ); - - - // R[cl_clint_set]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_cl_clint_set ( - .re (1'b0), - .we (cl_clint_set_we), - .wd (cl_clint_set_wd), - .d ('0), - .qre (), - .qe (reg2hw.cl_clint_set.qe), - .q (reg2hw.cl_clint_set.q ), - .qs () - ); - - - // R[cl_clint_clear]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_cl_clint_clear ( - .re (1'b0), - .we (cl_clint_clear_we), - .wd (cl_clint_clear_wd), - .d ('0), - .qre (), - .qe (reg2hw.cl_clint_clear.qe), - .q (reg2hw.cl_clint_clear.q ), - .qs () - ); - - // R[hw_barrier]: V(True) prim_subreg_ext #( @@ -415,19 +320,48 @@ module cachepool_peripheral_reg_top #( ); - // R[cfg_l1d_tile_sel]: V(False) + + // Subregister 0 of Multireg cfg_l1d_tile_sel + // R[cfg_l1d_tile_sel_0]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_l1d_tile_sel_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_l1d_tile_sel_0_we), + .wd (cfg_l1d_tile_sel_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_l1d_tile_sel[0].q ), + + // to register interface (read) + .qs (cfg_l1d_tile_sel_0_qs) + ); + + // Subregister 1 of Multireg cfg_l1d_tile_sel + // R[cfg_l1d_tile_sel_1]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_cfg_l1d_tile_sel ( + ) u_cfg_l1d_tile_sel_1 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_l1d_tile_sel_we), - .wd (cfg_l1d_tile_sel_wd), + .we (cfg_l1d_tile_sel_1_we), + .wd (cfg_l1d_tile_sel_1_wd), // from internal hardware .de (1'b0), @@ -435,10 +369,10 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_l1d_tile_sel.q ), + .q (reg2hw.cfg_l1d_tile_sel[1].q ), // to register interface (read) - .qs (cfg_l1d_tile_sel_qs) + .qs (cfg_l1d_tile_sel_1_qs) ); @@ -622,29 +556,26 @@ module cachepool_peripheral_reg_top #( - logic [19:0] addr_hit; + logic [16:0] addr_hit; always_comb begin addr_hit = '0; - addr_hit[ 0] = (reg_addr == CACHEPOOL_PERIPHERAL_HART_SELECT_0_OFFSET); - addr_hit[ 1] = (reg_addr == CACHEPOOL_PERIPHERAL_HART_SELECT_1_OFFSET); - addr_hit[ 2] = (reg_addr == CACHEPOOL_PERIPHERAL_CL_CLINT_SET_OFFSET); - addr_hit[ 3] = (reg_addr == CACHEPOOL_PERIPHERAL_CL_CLINT_CLEAR_OFFSET); - addr_hit[ 4] = (reg_addr == CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET); - addr_hit[ 5] = (reg_addr == CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); - addr_hit[ 6] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET); - addr_hit[ 7] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET); - addr_hit[ 8] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET); - addr_hit[ 9] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET); - addr_hit[10] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET); - addr_hit[11] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET); - addr_hit[12] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_OFFSET); - addr_hit[13] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET); - addr_hit[14] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET); - addr_hit[15] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET); - addr_hit[16] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET); - addr_hit[17] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET); - addr_hit[18] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET); - addr_hit[19] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET); + addr_hit[ 0] = (reg_addr == CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET); + addr_hit[ 1] = (reg_addr == CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET); + addr_hit[ 3] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET); + addr_hit[ 4] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET); + addr_hit[ 5] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET); + addr_hit[ 6] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET); + addr_hit[ 7] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET); + addr_hit[ 8] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_OFFSET); + addr_hit[ 9] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_OFFSET); + addr_hit[10] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET); + addr_hit[11] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET); + addr_hit[12] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET); + addr_hit[13] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET); + addr_hit[14] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET); + addr_hit[15] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET); + addr_hit[16] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -668,68 +599,56 @@ module cachepool_peripheral_reg_top #( (addr_hit[13] & (|(CACHEPOOL_PERIPHERAL_PERMIT[13] & ~reg_be))) | (addr_hit[14] & (|(CACHEPOOL_PERIPHERAL_PERMIT[14] & ~reg_be))) | (addr_hit[15] & (|(CACHEPOOL_PERIPHERAL_PERMIT[15] & ~reg_be))) | - (addr_hit[16] & (|(CACHEPOOL_PERIPHERAL_PERMIT[16] & ~reg_be))) | - (addr_hit[17] & (|(CACHEPOOL_PERIPHERAL_PERMIT[17] & ~reg_be))) | - (addr_hit[18] & (|(CACHEPOOL_PERIPHERAL_PERMIT[18] & ~reg_be))) | - (addr_hit[19] & (|(CACHEPOOL_PERIPHERAL_PERMIT[19] & ~reg_be))))); + (addr_hit[16] & (|(CACHEPOOL_PERIPHERAL_PERMIT[16] & ~reg_be))))); end - assign hart_select_0_we = addr_hit[0] & reg_we & !reg_error; - assign hart_select_0_wd = reg_wdata[9:0]; - - assign hart_select_1_we = addr_hit[1] & reg_we & !reg_error; - assign hart_select_1_wd = reg_wdata[9:0]; - - assign cl_clint_set_we = addr_hit[2] & reg_we & !reg_error; - assign cl_clint_set_wd = reg_wdata[31:0]; - - assign cl_clint_clear_we = addr_hit[3] & reg_we & !reg_error; - assign cl_clint_clear_wd = reg_wdata[31:0]; + assign hw_barrier_re = addr_hit[0] & reg_re & !reg_error; - assign hw_barrier_re = addr_hit[4] & reg_re & !reg_error; - - assign icache_prefetch_enable_we = addr_hit[5] & reg_we & !reg_error; + assign icache_prefetch_enable_we = addr_hit[1] & reg_we & !reg_error; assign icache_prefetch_enable_wd = reg_wdata[0]; - assign spatz_status_we = addr_hit[6] & reg_we & !reg_error; + assign spatz_status_we = addr_hit[2] & reg_we & !reg_error; assign spatz_status_wd = reg_wdata[0]; - assign spatz_cycle_we = addr_hit[7] & reg_we & !reg_error; + assign spatz_cycle_we = addr_hit[3] & reg_we & !reg_error; assign spatz_cycle_wd = reg_wdata[31:0]; - assign cluster_boot_control_we = addr_hit[8] & reg_we & !reg_error; + assign cluster_boot_control_we = addr_hit[4] & reg_we & !reg_error; assign cluster_boot_control_wd = reg_wdata[31:0]; - assign cluster_eoc_exit_we = addr_hit[9] & reg_we & !reg_error; + assign cluster_eoc_exit_we = addr_hit[5] & reg_we & !reg_error; assign cluster_eoc_exit_wd = reg_wdata[3:0]; - assign cfg_l1d_spm_we = addr_hit[10] & reg_we & !reg_error; + assign cfg_l1d_spm_we = addr_hit[6] & reg_we & !reg_error; assign cfg_l1d_spm_wd = reg_wdata[9:0]; - assign cfg_l1d_insn_we = addr_hit[11] & reg_we & !reg_error; + assign cfg_l1d_insn_we = addr_hit[7] & reg_we & !reg_error; assign cfg_l1d_insn_wd = reg_wdata[1:0]; - assign cfg_l1d_tile_sel_we = addr_hit[12] & reg_we & !reg_error; - assign cfg_l1d_tile_sel_wd = reg_wdata[31:0]; + assign cfg_l1d_tile_sel_0_we = addr_hit[8] & reg_we & !reg_error; + assign cfg_l1d_tile_sel_0_wd = reg_wdata[31:0]; + + assign cfg_l1d_tile_sel_1_we = addr_hit[9] & reg_we & !reg_error; + assign cfg_l1d_tile_sel_1_wd = reg_wdata[31:0]; - assign l1d_spm_commit_we = addr_hit[13] & reg_we & !reg_error; + assign l1d_spm_commit_we = addr_hit[10] & reg_we & !reg_error; assign l1d_spm_commit_wd = reg_wdata[0]; - assign l1d_insn_commit_we = addr_hit[14] & reg_we & !reg_error; + assign l1d_insn_commit_we = addr_hit[11] & reg_we & !reg_error; assign l1d_insn_commit_wd = reg_wdata[0]; - assign l1d_flush_status_re = addr_hit[15] & reg_re & !reg_error; + assign l1d_flush_status_re = addr_hit[12] & reg_re & !reg_error; - assign l1d_private_we = addr_hit[16] & reg_we & !reg_error; + assign l1d_private_we = addr_hit[13] & reg_we & !reg_error; assign l1d_private_wd = reg_wdata[3:0]; - assign l1d_addr_we = addr_hit[17] & reg_we & !reg_error; + assign l1d_addr_we = addr_hit[14] & reg_we & !reg_error; assign l1d_addr_wd = reg_wdata[31:0]; - assign xbar_offset_we = addr_hit[18] & reg_we & !reg_error; + assign xbar_offset_we = addr_hit[15] & reg_we & !reg_error; assign xbar_offset_wd = reg_wdata[4:0]; - assign xbar_offset_commit_we = addr_hit[19] & reg_we & !reg_error; + assign xbar_offset_commit_we = addr_hit[16] & reg_we & !reg_error; assign xbar_offset_commit_wd = reg_wdata[0]; // Read data return @@ -737,82 +656,70 @@ module cachepool_peripheral_reg_top #( reg_rdata_next = '0; unique case (1'b1) addr_hit[0]: begin - reg_rdata_next[9:0] = hart_select_0_qs; + reg_rdata_next[31:0] = hw_barrier_qs; end addr_hit[1]: begin - reg_rdata_next[9:0] = hart_select_1_qs; + reg_rdata_next[0] = '0; end addr_hit[2]: begin - reg_rdata_next[31:0] = '0; + reg_rdata_next[0] = '0; end addr_hit[3]: begin - reg_rdata_next[31:0] = '0; + reg_rdata_next[31:0] = spatz_cycle_qs; end addr_hit[4]: begin - reg_rdata_next[31:0] = hw_barrier_qs; + reg_rdata_next[31:0] = cluster_boot_control_qs; end addr_hit[5]: begin - reg_rdata_next[0] = '0; + reg_rdata_next[3:0] = cluster_eoc_exit_qs; end addr_hit[6]: begin - reg_rdata_next[0] = '0; + reg_rdata_next[9:0] = cfg_l1d_spm_qs; end addr_hit[7]: begin - reg_rdata_next[31:0] = spatz_cycle_qs; + reg_rdata_next[1:0] = cfg_l1d_insn_qs; end addr_hit[8]: begin - reg_rdata_next[31:0] = cluster_boot_control_qs; + reg_rdata_next[31:0] = cfg_l1d_tile_sel_0_qs; end addr_hit[9]: begin - reg_rdata_next[3:0] = cluster_eoc_exit_qs; + reg_rdata_next[31:0] = cfg_l1d_tile_sel_1_qs; end addr_hit[10]: begin - reg_rdata_next[9:0] = cfg_l1d_spm_qs; - end - - addr_hit[11]: begin - reg_rdata_next[1:0] = cfg_l1d_insn_qs; - end - - addr_hit[12]: begin - reg_rdata_next[31:0] = cfg_l1d_tile_sel_qs; - end - - addr_hit[13]: begin reg_rdata_next[0] = l1d_spm_commit_qs; end - addr_hit[14]: begin + addr_hit[11]: begin reg_rdata_next[0] = l1d_insn_commit_qs; end - addr_hit[15]: begin + addr_hit[12]: begin reg_rdata_next[0] = l1d_flush_status_qs; end - addr_hit[16]: begin + addr_hit[13]: begin reg_rdata_next[3:0] = l1d_private_qs; end - addr_hit[17]: begin + addr_hit[14]: begin reg_rdata_next[31:0] = l1d_addr_qs; end - addr_hit[18]: begin + addr_hit[15]: begin reg_rdata_next[4:0] = xbar_offset_qs; end - addr_hit[19]: begin + addr_hit[16]: begin reg_rdata_next[0] = xbar_offset_commit_qs; end diff --git a/hardware/src/cachepool_cluster.sv b/hardware/src/cachepool_cluster.sv index c9102ef..448e5d1 100644 --- a/hardware/src/cachepool_cluster.sv +++ b/hardware/src/cachepool_cluster.sv @@ -196,7 +196,6 @@ module cachepool_cluster // 3. Peripherals axi_addr_t private_start_addr; logic icache_prefetch_enable; - logic [NrCores-1:0] cl_interrupt; logic [$clog2(L1AddrWidth)-1:0] dynamic_offset; logic [3:0] l1d_private; cache_insn_t l1d_insn; @@ -292,7 +291,7 @@ module cachepool_cluster // Peripherals .icache_events_o ( /* unused */ ), .icache_prefetch_enable_i ( icache_prefetch_enable ), - .cl_interrupt_i ( cl_interrupt [g*NumCoreGroup +: NumCoreGroup] ), + .cl_interrupt_i ( '0 ), .dynamic_offset_i ( dynamic_offset ), .l1d_private_i ( l1d_private ), .l1d_insn_i ( l1d_insn ), @@ -759,8 +758,7 @@ module cachepool_cluster .NumTiles (NumTiles ), .reg_req_t (reg_req_t ), .reg_rsp_t (reg_rsp_t ), - .cache_insn_t (cache_insn_t ), - .NrCores (NrCores ) + .cache_insn_t (cache_insn_t ) ) i_cachepool_cluster_peripheral ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -771,7 +769,6 @@ module cachepool_cluster .tcdm_start_address_i (tcdm_start_address ), .tcdm_end_address_i (tcdm_end_address ), .icache_prefetch_enable_o (icache_prefetch_enable), - .cl_clint_o (cl_interrupt ), .cluster_hart_base_id_i (hart_base_id_i ), .cluster_probe_o (cluster_probe_o ), .dynamic_offset_o (dynamic_offset ), diff --git a/software/snRuntime/include/cachepool_peripheral.h b/software/snRuntime/include/cachepool_peripheral.h index aad79f5..5a26778 100644 --- a/software/snRuntime/include/cachepool_peripheral.h +++ b/software/snRuntime/include/cachepool_peripheral.h @@ -13,63 +13,33 @@ #ifdef __cplusplus extern "C" { #endif -// Number of performance counters -#define CACHEPOOL_PERIPHERAL_PARAM_NUM_PERF_COUNTERS 2 +// Number of 32-bit tile-select registers. Default 2 covers up to 64 tiles +// (16 groups x 4 tiles). +#define CACHEPOOL_PERIPHERAL_PARAM_NUM_TILE_SEL_REGS 2 // Register width #define CACHEPOOL_PERIPHERAL_PARAM_REG_WIDTH 32 -// Select from which hart in the cluster, starting from `0`, -#define CACHEPOOL_PERIPHERAL_HART_SELECT_HART_SELECT_FIELD_WIDTH 10 -#define CACHEPOOL_PERIPHERAL_HART_SELECT_HART_SELECT_FIELDS_PER_REG 3 -#define CACHEPOOL_PERIPHERAL_HART_SELECT_MULTIREG_COUNT 2 - -// Select from which hart in the cluster, starting from `0`, -#define CACHEPOOL_PERIPHERAL_HART_SELECT_0_REG_OFFSET 0x0 -#define CACHEPOOL_PERIPHERAL_HART_SELECT_0_HART_SELECT_0_MASK 0x3ff -#define CACHEPOOL_PERIPHERAL_HART_SELECT_0_HART_SELECT_0_OFFSET 0 -#define CACHEPOOL_PERIPHERAL_HART_SELECT_0_HART_SELECT_0_FIELD \ - ((bitfield_field32_t){ \ - .mask = CACHEPOOL_PERIPHERAL_HART_SELECT_0_HART_SELECT_0_MASK, \ - .index = CACHEPOOL_PERIPHERAL_HART_SELECT_0_HART_SELECT_0_OFFSET}) - -// Select from which hart in the cluster, starting from `0`, -#define CACHEPOOL_PERIPHERAL_HART_SELECT_1_REG_OFFSET 0x4 -#define CACHEPOOL_PERIPHERAL_HART_SELECT_1_HART_SELECT_1_MASK 0x3ff -#define CACHEPOOL_PERIPHERAL_HART_SELECT_1_HART_SELECT_1_OFFSET 0 -#define CACHEPOOL_PERIPHERAL_HART_SELECT_1_HART_SELECT_1_FIELD \ - ((bitfield_field32_t){ \ - .mask = CACHEPOOL_PERIPHERAL_HART_SELECT_1_HART_SELECT_1_MASK, \ - .index = CACHEPOOL_PERIPHERAL_HART_SELECT_1_HART_SELECT_1_OFFSET}) - -// Set bits in the cluster-local CLINT. Writing a 1 at location i sets the -// cluster-local interrupt -#define CACHEPOOL_PERIPHERAL_CL_CLINT_SET_REG_OFFSET 0x8 - -// Clear bits in the cluster-local CLINT. Writing a 1 at location i clears -// the cluster-local interrupt -#define CACHEPOOL_PERIPHERAL_CL_CLINT_CLEAR_REG_OFFSET 0xc - // Hardware barrier register. Loads to this register will block until all // cores have -#define CACHEPOOL_PERIPHERAL_HW_BARRIER_REG_OFFSET 0x10 +#define CACHEPOOL_PERIPHERAL_HW_BARRIER_REG_OFFSET 0x0 // Controls prefetching of the instruction cache. -#define CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_REG_OFFSET 0x14 +#define CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_REG_OFFSET 0x4 #define CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_ICACHE_PREFETCH_ENABLE_BIT 0 // Sets the status of the Spatz cluster. -#define CACHEPOOL_PERIPHERAL_SPATZ_STATUS_REG_OFFSET 0x18 +#define CACHEPOOL_PERIPHERAL_SPATZ_STATUS_REG_OFFSET 0x8 #define CACHEPOOL_PERIPHERAL_SPATZ_STATUS_SPATZ_CLUSTER_PROBE_BIT 0 // Store cycle counts of kernels -#define CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_REG_OFFSET 0x1c +#define CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_REG_OFFSET 0xc // Controls the cluster boot process. -#define CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_REG_OFFSET 0x20 +#define CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_REG_OFFSET 0x10 // End of computation and exit status register -#define CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_REG_OFFSET 0x24 +#define CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_REG_OFFSET 0x14 #define CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_EOC_EXIT_MASK 0xf #define CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_EOC_EXIT_OFFSET 0 #define CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_EOC_EXIT_FIELD \ @@ -78,7 +48,7 @@ extern "C" { .index = CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_EOC_EXIT_OFFSET}) // Controls the configurations of L1 DCache SPM size. -#define CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_REG_OFFSET 0x28 +#define CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_REG_OFFSET 0x18 #define CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_SPM_SIZE_MASK 0x3ff #define CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_SPM_SIZE_OFFSET 0 #define CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_SPM_SIZE_FIELD \ @@ -87,7 +57,7 @@ extern "C" { .index = CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_SPM_SIZE_OFFSET}) // Controls the L1 DCache flushing and invalidation. -#define CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_REG_OFFSET 0x2c +#define CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_REG_OFFSET 0x1c #define CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_INSN_MASK 0x3 #define CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_INSN_OFFSET 0 #define CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_INSN_FIELD \ @@ -95,23 +65,31 @@ extern "C" { .index = \ CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_INSN_OFFSET}) -// Controls Tiles to be flushed -#define CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_REG_OFFSET 0x30 +// One-hot tile selection mask for private-partition flush. +#define CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_TILE_FIELD_WIDTH 32 +#define CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_TILE_FIELDS_PER_REG 1 +#define CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_MULTIREG_COUNT 2 + +// One-hot tile selection mask for private-partition flush. +#define CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_REG_OFFSET 0x20 + +// One-hot tile selection mask for private-partition flush. +#define CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_REG_OFFSET 0x24 // Controls the L1 DCache flushing and invalidation. -#define CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_REG_OFFSET 0x34 +#define CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_REG_OFFSET 0x28 #define CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_COMMIT_BIT 0 // Controls the L1 DCache flushing and invalidation. -#define CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_REG_OFFSET 0x38 +#define CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_REG_OFFSET 0x2c #define CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_COMMIT_BIT 0 // Indicate the status of flushing -#define CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_REG_OFFSET 0x3c +#define CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_REG_OFFSET 0x30 #define CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_STATUS_BIT 0 // Number of private banks configured per tile -#define CACHEPOOL_PERIPHERAL_L1D_PRIVATE_REG_OFFSET 0x40 +#define CACHEPOOL_PERIPHERAL_L1D_PRIVATE_REG_OFFSET 0x34 #define CACHEPOOL_PERIPHERAL_L1D_PRIVATE_NUMBER_MASK 0xf #define CACHEPOOL_PERIPHERAL_L1D_PRIVATE_NUMBER_OFFSET 0 #define CACHEPOOL_PERIPHERAL_L1D_PRIVATE_NUMBER_FIELD \ @@ -120,10 +98,10 @@ extern "C" { CACHEPOOL_PERIPHERAL_L1D_PRIVATE_NUMBER_OFFSET}) // Starting address of private L1D partition -#define CACHEPOOL_PERIPHERAL_L1D_ADDR_REG_OFFSET 0x44 +#define CACHEPOOL_PERIPHERAL_L1D_ADDR_REG_OFFSET 0x38 // Cache xbar offset setting -#define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_REG_OFFSET 0x48 +#define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_REG_OFFSET 0x3c #define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET_MASK 0x1f #define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET_OFFSET 0 #define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET_FIELD \ @@ -132,7 +110,7 @@ extern "C" { CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET_OFFSET}) // Cache xbar offset setting -#define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_REG_OFFSET 0x4c +#define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_REG_OFFSET 0x40 #define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_COMMIT_BIT 0 #ifdef __cplusplus diff --git a/software/snRuntime/include/l1cache.h b/software/snRuntime/include/l1cache.h index f2b45b4..67467f6 100644 --- a/software/snRuntime/include/l1cache.h +++ b/software/snRuntime/include/l1cache.h @@ -18,10 +18,10 @@ void l1d_commit(); void l1d_init(uint32_t size); void l1d_flush(); void l1d_shared_flush(); -void l1d_private_flush(uint32_t tile); +void l1d_private_flush(uint64_t tile); void l1d_cluster_flush(); void l1d_cluster_shared_flush(); -void l1d_cluster_private_flush(uint32_t tile); +void l1d_cluster_private_flush(uint64_t tile); void l1d_wait(); void l1d_spm_config (uint32_t size); void l1d_part (uint32_t size); diff --git a/software/snRuntime/include/snrt.h b/software/snRuntime/include/snrt.h index 037c23b..19753c2 100644 --- a/software/snRuntime/include/snrt.h +++ b/software/snRuntime/include/snrt.h @@ -47,11 +47,6 @@ typedef struct snrt_slice { struct snrt_peripherals { volatile uint32_t *wakeup; uint32_t *perf_counters; - /** - * @brief Cluster-local CLINT - * - */ - volatile uint32_t *cl_clint; }; /// Barrier to use with snrt_barrier diff --git a/software/snRuntime/src/interrupt.c b/software/snRuntime/src/interrupt.c index 3c2f04e..c688cab 100644 --- a/software/snRuntime/src/interrupt.c +++ b/software/snRuntime/src/interrupt.c @@ -35,8 +35,7 @@ void irq_m_cluster(uint32_t core_idx); //================================================================================ void snrt_int_init(struct snrt_team_root *team) { - // Put the clint address in tls for faster access - clint_p = team->peripherals.cl_clint; + (void)team; } /** diff --git a/software/snRuntime/src/l1cache.c b/software/snRuntime/src/l1cache.c index 6107656..347eefe 100644 --- a/software/snRuntime/src/l1cache.c +++ b/software/snRuntime/src/l1cache.c @@ -70,19 +70,23 @@ void l1d_flush() { l1d_commit(); } -// Flush private partitions in input tiles (onehot) -void l1d_private_flush(uint32_t tile) { +// Flush private partitions in selected tiles. +// tile is a one-hot bitmask: bit i selects tile i. +// Bits 0-31 go to register 0, bits 32-63 to register 1. +void l1d_private_flush(uint64_t tile) { uint32_t *insn = (uint32_t *)(_snrt_team_current->root->cluster_mem.end + CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_REG_OFFSET); - // 2'b00 stands for flush all *insn = 0; - uint32_t *tile_reg = + uint32_t *tile_lo = (uint32_t *)(_snrt_team_current->root->cluster_mem.end + - CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_REG_OFFSET); - // 2'b00 stands for flush all - *tile_reg = tile; + CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_REG_OFFSET); + uint32_t *tile_hi = + (uint32_t *)(_snrt_team_current->root->cluster_mem.end + + CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_REG_OFFSET); + *tile_lo = (uint32_t)(tile); + *tile_hi = (uint32_t)(tile >> 32); l1d_commit(); } @@ -110,7 +114,7 @@ void l1d_cluster_flush() { // Cluster-wide private flush: all cores fence and sync, core 0 issues the flush instruction. // Must be called by all cores in the cluster. -void l1d_cluster_private_flush(uint32_t tile) { +void l1d_cluster_private_flush(uint64_t tile) { asm volatile("fence" ::: "memory"); snrt_cluster_hw_barrier(); if (snrt_cluster_core_idx() == 0) { diff --git a/software/snRuntime/src/platforms/shared/start.c b/software/snRuntime/src/platforms/shared/start.c index 9d5ceb8..4e85e53 100644 --- a/software/snRuntime/src/platforms/shared/start.c +++ b/software/snRuntime/src/platforms/shared/start.c @@ -81,9 +81,6 @@ void _snrt_init_team(uint32_t cluster_core_id, uint32_t cluster_core_num, // *)(spm_start + bootdata->tcdm_size + // CACHEPOOL_PERIPHERAL_PERF_COUNTER_ENABLE_0_REG_OFFSET); team->peripherals.wakeup = (uint32_t *)0; // not supported in RTL anymore - team->peripherals.cl_clint = - (uint32_t *)(spm_start + bootdata->tcdm_size + - CACHEPOOL_PERIPHERAL_CL_CLINT_SET_REG_OFFSET); // Init allocator snrt_alloc_init(team, sizeof(struct putc_buffer)); diff --git a/software/tests/load-store/main.c b/software/tests/load-store/main.c index 6c952f9..8a1a7f8 100644 --- a/software/tests/load-store/main.c +++ b/software/tests/load-store/main.c @@ -134,7 +134,7 @@ static void cache_flush_all() { // Flush private banks of selected tiles (one-hot mask) and wait. // Must be called by all cores. -static void cache_flush_private(uint32_t tile_mask) { +static void cache_flush_private(uint64_t tile_mask) { l1d_cluster_private_flush(tile_mask); } @@ -172,8 +172,8 @@ int main() { // xbar offset: size of per-core region in address bits const uint32_t local_offset = 31 - __builtin_clz(dim_core * sizeof(uint32_t)); - // One-hot mask covering all tiles - const uint32_t all_tiles = (1u << num_tiles) - 1u; + // One-hot mask covering all tiles (uint64_t supports up to 64 tiles) + const uint64_t all_tiles = (UINT64_C(1) << num_tiles) - 1; // Per-core pointers into each array uint32_t *a_ptr = gemm_A_dram + dim_core * cid; // private, value 1 From 2dbe16906b208b96b7713ae690a5c5f7aada0676 Mon Sep 17 00:00:00 2001 From: Diyou Shen Date: Mon, 15 Jun 2026 16:28:44 +0200 Subject: [PATCH 11/39] [SW] Remove unused runtime functions --- software/snRuntime/CMakeLists.txt | 19 ------------ software/snRuntime/include/snrt.h | 13 -------- .../snRuntime/src/platforms/shared/start.c | 6 ---- software/snRuntime/src/team.c | 31 ------------------- 4 files changed, 69 deletions(-) diff --git a/software/snRuntime/CMakeLists.txt b/software/snRuntime/CMakeLists.txt index d2e7218..5c6b3cb 100644 --- a/software/snRuntime/CMakeLists.txt +++ b/software/snRuntime/CMakeLists.txt @@ -64,7 +64,6 @@ set(sources src/team.c src/alloc.c src/interrupt.c - src/perf_cnt.c src/l1cache.c ) @@ -74,24 +73,6 @@ set(standalone_snitch_sources src/platforms/standalone/putchar.c ) -# Sources only compatible with the LLVM toolchain -if (CMAKE_C_COMPILER_ID STREQUAL "Clang") - set(sources - ${sources} - # OpenMP support - src/omp/omp.c - src/omp/kmp.c - src/omp/eu.c - src/dm.c - ) - # Check if static OpenMP runtime is requested - if(OMPSTATIC_NUMTHREADS GREATER 0) - message(STATUS "Using ${OMPSTATIC_NUMTHREADS} threads for optimized OpenMP runtime") - add_compile_definitions(OMPSTATIC_NUMTHREADS=${OMPSTATIC_NUMTHREADS}) - else() - message(STATUS "Generic OpenMP runtime") - endif() -endif() if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) # Build all runtimes diff --git a/software/snRuntime/include/snrt.h b/software/snRuntime/include/snrt.h index 19753c2..a963625 100644 --- a/software/snRuntime/include/snrt.h +++ b/software/snRuntime/include/snrt.h @@ -45,8 +45,6 @@ typedef struct snrt_slice { /// Peripherals to the Snitch SoC struct snrt_peripherals { - volatile uint32_t *wakeup; - uint32_t *perf_counters; }; /// Barrier to use with snrt_barrier @@ -68,24 +66,13 @@ extern struct snrt_peripherals *snrt_peripherals(); extern uint32_t snrt_global_core_base_hartid(); extern uint32_t snrt_global_core_idx(); extern uint32_t snrt_global_core_num(); -extern uint32_t snrt_global_compute_core_idx(); -extern uint32_t snrt_global_compute_core_num(); -extern uint32_t snrt_global_dm_core_idx(); -extern uint32_t snrt_global_dm_core_num(); extern uint32_t snrt_cluster_core_base_hartid(); extern uint32_t snrt_cluster_core_idx(); extern uint32_t snrt_cluster_core_num(); extern uint32_t snrt_cluster_tile_idx(); extern uint32_t snrt_cluster_tile_num(); -extern uint32_t snrt_cluster_compute_core_idx(); -extern uint32_t snrt_cluster_compute_core_num(); -extern uint32_t snrt_cluster_dm_core_idx(); -extern uint32_t snrt_cluster_dm_core_num(); extern uint32_t snrt_cluster_idx(); extern uint32_t snrt_cluster_num(); -extern int snrt_is_compute_core(); -extern int snrt_is_dm_core(); -extern void snrt_wakeup(uint32_t mask); /// get pointer to barrier register extern uint32_t _snrt_barrier_reg_ptr(); diff --git a/software/snRuntime/src/platforms/shared/start.c b/software/snRuntime/src/platforms/shared/start.c index 4e85e53..dbe1757 100644 --- a/software/snRuntime/src/platforms/shared/start.c +++ b/software/snRuntime/src/platforms/shared/start.c @@ -75,12 +75,6 @@ void _snrt_init_team(uint32_t cluster_core_id, uint32_t cluster_core_num, // it's as good a point as any. putc_buffer[snrt_hartid()].hdr.size = 0; - // init peripherals - // team->peripherals.perf_counters = - // (uint32_t - // *)(spm_start + bootdata->tcdm_size + - // CACHEPOOL_PERIPHERAL_PERF_COUNTER_ENABLE_0_REG_OFFSET); - team->peripherals.wakeup = (uint32_t *)0; // not supported in RTL anymore // Init allocator snrt_alloc_init(team, sizeof(struct putc_buffer)); diff --git a/software/snRuntime/src/team.c b/software/snRuntime/src/team.c index 8acd9e0..6de4e7b 100644 --- a/software/snRuntime/src/team.c +++ b/software/snRuntime/src/team.c @@ -74,36 +74,6 @@ uint32_t snrt_cluster_core_num() { return _snrt_team_current->root->cluster_core_num; } -uint32_t snrt_cluster_compute_core_idx() { - // TODO: Actually derive this from the device tree! - return snrt_cluster_core_idx(); -} - -uint32_t snrt_cluster_compute_core_num() { - // TODO: Actually derive this from the device tree! - return snrt_cluster_core_num() - 1; -} - -uint32_t snrt_cluster_dm_core_idx() { - // TODO: Actually derive this from the device tree! - return snrt_cluster_core_num() - 1; -} - -uint32_t snrt_cluster_dm_core_num() { - // TODO: Actually derive this from the device tree! - return 1; -} - -int snrt_is_compute_core() { - // TODO: Actually derive this from the device tree! - return snrt_cluster_core_idx() < snrt_cluster_core_num() - 1; -} - -int snrt_is_dm_core() { - // TODO: Actually derive this from the device tree! - return !snrt_is_compute_core(); -} - uint32_t _snrt_barrier_reg_ptr() { return _snrt_team_current->root->barrier_reg_ptr; } @@ -116,4 +86,3 @@ snrt_slice_t snrt_cluster_memory() { return _snrt_team_current->root->cluster_mem; } -void snrt_wakeup(uint32_t mask) { *snrt_peripherals()->wakeup = mask; } From 75080d80e879b082fb3e0715ddd58e2b243f8282 Mon Sep 17 00:00:00 2001 From: Diyou Shen Date: Tue, 16 Jun 2026 08:57:39 +0200 Subject: [PATCH 12/39] [Lint] Fix some small linting issues and adjust L2 ICache size. --- hardware/src/axi_hier_interco.sv | 2 +- hardware/src/cachepool_pkg.sv | 2 +- util/lint/script/lint.tcl | 5 +++++ 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/hardware/src/axi_hier_interco.sv b/hardware/src/axi_hier_interco.sv index b4ab001..dfc4d99 100644 --- a/hardware/src/axi_hier_interco.sv +++ b/hardware/src/axi_hier_interco.sv @@ -232,7 +232,7 @@ module axi_hier_interco .AxiDataWidth (DataWidth ), .AxiIdWidth (IntIdWidth ), .AxiUserWidth (UserWidth ), - .MaxTrans (32'd16 ), + .MaxTrans (32'd8 ), .NrAddrRules (NrAddrRules ), .SerialLookup (0 ), .slv_req_t (int_req_t ), diff --git a/hardware/src/cachepool_pkg.sv b/hardware/src/cachepool_pkg.sv index 8953825..b75f041 100644 --- a/hardware/src/cachepool_pkg.sv +++ b/hardware/src/cachepool_pkg.sv @@ -108,7 +108,7 @@ package cachepool_pkg; // Group-level L2 ICache (shared read-only cache, primarily for coalescing) localparam int unsigned L2ICacheLineWidth = 512; localparam int unsigned L2ICacheSets = 4; - localparam int unsigned L2ICacheSizeByte = 65536; + localparam int unsigned L2ICacheSizeByte = 8192; localparam int unsigned L2ICacheLineCount = L2ICacheSizeByte / (L2ICacheSets * L2ICacheLineWidth / 8); // Be careful on unsigned long int passed in from configuration. diff --git a/util/lint/script/lint.tcl b/util/lint/script/lint.tcl index 843fb66..a234255 100644 --- a/util/lint/script/lint.tcl +++ b/util/lint/script/lint.tcl @@ -12,6 +12,11 @@ set_option allow_module_override yes set_option designread_disable_flatten no set_option nopreserve yes set_option top cachepool_cluster_wrapper +# Large configs (16-group/64-tile) produce AXI ID widths up to 12 bits. +# axi_id_serialize and axi_demux_simple both create 2^IdWidth structures; +# raise synthesis thresholds so SpyGlass can elaborate them. +set_option mthresh 5000 +set_option sgsyn_loop_limit 5000 # Do not elaborate some problematic FPU modules set_option stop fpnew_sdotp_multi From 79d52812bd1d09e8bc03c15b2f4417ceef350109 Mon Sep 17 00:00:00 2001 From: Diyou Shen Date: Tue, 16 Jun 2026 16:46:06 +0200 Subject: [PATCH 13/39] [MISC] Clean up Makefile and change the test size for load-store test. --- Makefile | 41 ++++++++++++++----------------- software/tests/load-store/main.c | 2 +- util/auto-benchmark/configs-ci.sh | 2 +- util/auto-benchmark/configs.sh | 2 +- 4 files changed, 21 insertions(+), 26 deletions(-) diff --git a/Makefile b/Makefile index 5965c52..d3dcc51 100644 --- a/Makefile +++ b/Makefile @@ -147,7 +147,7 @@ $(BOOTROM_DIR)/bootdata.cc: $(SCRIPTS_DIR)/generate_bootdata.py $(HJSON_OUT) ${PYTHON} $< -c $(HJSON_OUT) -d $(BOOTROM_DIR) -t bootdata.cc.tpl -o $@ $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.dump $(BOOTROM_DIR)/bootrom.bin: \ - $(BOOTROM_DIR)/bootrom.S $(BOOTROM_DIR)/bootdata_bootrom.cc $(BOOTROM_DIR)/bootrom.ld Makefile + $(BOOTROM_DIR)/bootrom.S $(BOOTROM_DIR)/bootdata_bootrom.cc $(BOOTROM_DIR)/bootrom.ld riscv -riscv64-gcc-9.5.0 riscv64-unknown-elf-gcc \ -mabi=ilp32 -march=rv32imaf -static -nostartfiles \ -T$(BOOTROM_DIR)/bootrom.ld \ @@ -195,7 +195,7 @@ VSIM_FLAGS := VSIM_BENDER = .PHONY: dram-build -dram-build: $(DRAMSYS_PATH)/README.md dram-clean dram-config +dram-build: $(DRAMSYS_PATH)/README.md dram-config cd $(DRAMSYS_PATH) && \ if [ ! -d "build" ]; then \ mkdir build && cd build; \ @@ -358,34 +358,29 @@ clean.data: clean.sw: rm -rf ${SOFTWARE_DIR}/build +# Common CMake flags shared by sw and vsim targets. +# vsim appends -DSNITCH_SIMULATOR to point tests at the compiled binary. +SW_CMAKE_FLAGS = \ + -DENABLE_CACHEPOOL_TESTS=${ENABLE_CACHEPOOL_TESTS} \ + -DCACHEPOOL_DIR=$(CACHEPOOL_DIR) \ + -DRUNTIME_DIR=${SOFTWARE_DIR} \ + -DSPATZ_SW_DIR=$(SPATZ_SW_DIR) \ + -DLLVM_PATH=${LLVM_INSTALL_DIR} \ + -DGCC_PATH=${GCC_INSTALL_DIR} \ + -DPYTHON=${PYTHON} \ + -DBUILD_TESTS=ON + .PHONY: sw -sw: generate bootrom gen-data clean.sw - echo ${SOFTWARE_DIR} +sw: generate bootrom gen-data mkdir -p ${SOFTWARE_DIR}/build - cd ${SOFTWARE_DIR}/build && ${CMAKE} \ - -DENABLE_CACHEPOOL_TESTS=${ENABLE_CACHEPOOL_TESTS} \ - -DCACHEPOOL_DIR=$(CACHEPOOL_DIR) \ - -DRUNTIME_DIR=${SOFTWARE_DIR} \ - -DSPATZ_SW_DIR=$(SPATZ_SW_DIR) \ - -DLLVM_PATH=${LLVM_INSTALL_DIR} \ - -DGCC_PATH=${GCC_INSTALL_DIR} \ - -DPYTHON=${PYTHON} \ - -DBUILD_TESTS=ON .. && $(MAKE) + cd ${SOFTWARE_DIR}/build && ${CMAKE} ${SW_CMAKE_FLAGS} .. && $(MAKE) .PHONY: vsim vsim: generate bootrom gen-data dpi ${SIMBIN_DIR}/cachepool_cluster.vsim - echo ${SOFTWARE_DIR} mkdir -p ${SOFTWARE_DIR}/build - cd ${SOFTWARE_DIR}/build && ${CMAKE} \ - -DENABLE_CACHEPOOL_TESTS=${ENABLE_CACHEPOOL_TESTS} \ - -DCACHEPOOL_DIR=$(CACHEPOOL_DIR) \ - -DRUNTIME_DIR=${SOFTWARE_DIR} \ - -DSPATZ_SW_DIR=$(SPATZ_SW_DIR) \ - -DLLVM_PATH=${LLVM_INSTALL_DIR} \ - -DGCC_PATH=${GCC_INSTALL_DIR} \ - -DPYTHON=${PYTHON} \ + cd ${SOFTWARE_DIR}/build && ${CMAKE} ${SW_CMAKE_FLAGS} \ -DSNITCH_SIMULATOR=${SIMBIN_DIR}/cachepool_cluster.vsim \ - -DBUILD_TESTS=ON .. && $(MAKE) + .. && $(MAKE) .PHONY: clean clean: clean.sw clean.vsim clean.data diff --git a/software/tests/load-store/main.c b/software/tests/load-store/main.c index 8a1a7f8..6af02b4 100644 --- a/software/tests/load-store/main.c +++ b/software/tests/load-store/main.c @@ -53,7 +53,7 @@ // Total elements = max_cores * TEST_CLS * ELEMS_PER_CL. // Default config: 16 cores * 4 CL * 16 elem/CL = 1024. // A/B/C are placed in the private region; D is placed in the shared region. -#define LOAD_STORE_TOTAL_ELEMS 1024 +#define LOAD_STORE_TOTAL_ELEMS 262144 // Private region: default boundary puts these addresses in the private partition static uint32_t gemm_A_dram[LOAD_STORE_TOTAL_ELEMS] diff --git a/util/auto-benchmark/configs-ci.sh b/util/auto-benchmark/configs-ci.sh index 70557e2..66397e9 100644 --- a/util/auto-benchmark/configs-ci.sh +++ b/util/auto-benchmark/configs-ci.sh @@ -1,5 +1,5 @@ # Configs and kernel suffixes (without prefix) CONFIGS="cachepool_fpu_2g" -KERNELS="spin-lock load-store_M16 fdotp-32b_M32768 gemv_M512_N128_K32 fmatmul-32b_M64_N64_K64 fft-32b_M1024_N16 multi_producer_single_consumer_double_linked_list_M1_N1350_K10 byte-enable" +KERNELS="spin-lock load-store fdotp-32b_M32768 gemv_M512_N128_K32 fmatmul-32b_M64_N64_K64 fft-32b_M1024_N16 multi_producer_single_consumer_double_linked_list_M1_N1350_K10 byte-enable" PREFIX="test-cachepool-" # common prefix for all kernels ROOT_PATH=../.. # adjust if needed (path to repo root) diff --git a/util/auto-benchmark/configs.sh b/util/auto-benchmark/configs.sh index bb8fa6c..8fc6f6c 100755 --- a/util/auto-benchmark/configs.sh +++ b/util/auto-benchmark/configs.sh @@ -1,6 +1,6 @@ # Configs and kernel suffixes (without prefix) -CONFIGS="cachepool_fpu_2g cachepool_fpu_4g" +CONFIGS="cachepool_fpu_2g cachepool_fpu_16g" KERNELS="spin-lock fdotp-32b_M65536 gemv-opt_M1024_N128_K32 gemv_M1024_N128_K32 fmatmul-32b_M64_N64_K64 multi_producer_single_consumer_double_linked_list_M1_N1350_K100 byte-enable" From c154ed19473132b7923a649bc94a148f90547633 Mon Sep 17 00:00:00 2001 From: Diyou Shen Date: Wed, 17 Jun 2026 15:41:45 +0200 Subject: [PATCH 14/39] [CFG] Add a 4x4 smaller configuration for faster testing --- config/cachepool_fpu_16g_tiny.mk | 104 ++++++++++++++++++++ config/config.mk | 6 +- hardware/src/cachepool_cluster.sv | 16 +-- hardware/src/cachepool_group.sv | 2 +- hardware/src/cachepool_group_noc_wrapper.sv | 2 +- hardware/src/cachepool_tile.sv | 6 +- software/tests/gemv/script/gen_data.py | 6 +- 7 files changed, 123 insertions(+), 19 deletions(-) create mode 100644 config/cachepool_fpu_16g_tiny.mk diff --git a/config/cachepool_fpu_16g_tiny.mk b/config/cachepool_fpu_16g_tiny.mk new file mode 100644 index 0000000..a5ab4e9 --- /dev/null +++ b/config/cachepool_fpu_16g_tiny.mk @@ -0,0 +1,104 @@ +# Copyright 2025 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Author: Diyou Shen, ETH Zurich + +######################### +## CachePool Cluster ## +######################### + +# Number of groups +num_groups ?= 16 + +# 4×4 mesh +num_groups_x ?= 4 + +# Number of tiles +num_tiles_per_group ?= 2 + +# Number of cores +num_cores_per_tile ?= 2 + +# Core datawidth +data_width ?= 32 + +# Core addrwidth +addr_width ?= 32 + +num_remote_ports_per_tile ?= 1 + +num_rg_ports_per_core ?= 1 + +num_noc_ports_per_tile ?= 1 + + +###################### +## CachePool Tile ## +###################### + +##### L1 Data Cache ##### + +# L1 data cacheline width (in Bit) +l1d_cacheline_width ?= 512 + +# L1 data cache banking factor (how many banks per core?) +l1d_bank_factor ?= 1 + +# L1 coalecsing window +l1d_coal_window ?= 2 + +# L1 data cache number of ways per +l1d_num_way ?= 4 + +# L1 data cache size per tile (KiB) +l1d_tile_size ?= 256 + +# L1 data cache tag width (TODO: should be calcualted) +l1d_tag_data_width ?= 92 + +#################### +## CachePool CC ## +#################### +# Spatz fpu support? +spatz_fpu_en ?= 1 + +# Spatz number of FPU +spatz_num_fpu ?= 4 + +# Spatz number of IPU +spatz_num_ipu ?= 4 + +# Spatz max outstanding transactions +spatz_max_trans ?= 32 + +# Snitch/FPU max outstanding transactions +snitch_max_trans ?= 16 + + +##################### +## L2 Main Memory ## +##################### +# DRAM type (selects DRAMSys config and sets default refill_data_width) +dram_type ?= HBM2 + +# L2 number of channels +l2_channel ?= 8 + +# L2 bank width (DRAM width, change with care) +l2_bank_width ?= 512 + +# L2 interleaving factor (in order of bank_width) +l2_interleave ?= 16 + +axi_user_width ?= 16 + + +################## +## Peripherals ## +################## +# Hardware stack size (in Byte) +stack_hw_size ?= 1024 + +# Stack size (total, including share and private, 32'h800) +stack_tot_size ?= 2048 diff --git a/config/config.mk b/config/config.mk index 6fbd811..25a6508 100644 --- a/config/config.mk +++ b/config/config.mk @@ -131,11 +131,11 @@ snitch_max_trans ?= 16 ######################### ifeq ($(l1d_cacheline_width),512) - axi_user_width := 17 + axi_user_width ?= 17 else ifeq ($(l1d_cacheline_width),256) - axi_user_width := 18 + axi_user_width ?= 18 else ifeq ($(l1d_cacheline_width),128) - axi_user_width := 21 + axi_user_width ?= 21 endif ##################### diff --git a/hardware/src/cachepool_cluster.sv b/hardware/src/cachepool_cluster.sv index 448e5d1..e75ff20 100644 --- a/hardware/src/cachepool_cluster.sv +++ b/hardware/src/cachepool_cluster.sv @@ -194,14 +194,14 @@ module cachepool_cluster axi_narrow_resp_t [NumTiles-1:0][1:0] axi_out_resp; // 3. Peripherals - axi_addr_t private_start_addr; - logic icache_prefetch_enable; - logic [$clog2(L1AddrWidth)-1:0] dynamic_offset; - logic [3:0] l1d_private; - cache_insn_t l1d_insn; - logic l1d_insn_valid; - logic [NumTiles-1:0] l1d_insn_ready; - logic [NumTiles-1:0] l1d_busy; + axi_addr_t private_start_addr; + logic icache_prefetch_enable; + logic [$clog2(L1AddrWidth)-1:0] dynamic_offset; + cache_insn_t l1d_insn; + logic l1d_insn_valid; + logic [NumTiles-1:0] l1d_insn_ready; + logic [NumTiles-1:0] l1d_busy; + logic [$clog2(NumL1CtrlTile):0] l1d_private; // Per-group error signals. logic [NumGroups-1:0] group_error; diff --git a/hardware/src/cachepool_group.sv b/hardware/src/cachepool_group.sv index c1f215f..016b25a 100644 --- a/hardware/src/cachepool_group.sv +++ b/hardware/src/cachepool_group.sv @@ -146,7 +146,7 @@ module cachepool_group input logic icache_prefetch_enable_i, input logic [NrCores-1:0] cl_interrupt_i, input logic [$clog2(AxiAddrWidth)-1:0] dynamic_offset_i, - input logic [3:0] l1d_private_i, + input logic [$clog2(NumL1CtrlTile):0] l1d_private_i, input cache_insn_t l1d_insn_i, input logic l1d_insn_valid_i, output logic [NumTilesPerGroup-1:0] l1d_insn_ready_o, diff --git a/hardware/src/cachepool_group_noc_wrapper.sv b/hardware/src/cachepool_group_noc_wrapper.sv index 28a31ed..735ef9b 100644 --- a/hardware/src/cachepool_group_noc_wrapper.sv +++ b/hardware/src/cachepool_group_noc_wrapper.sv @@ -74,7 +74,7 @@ module cachepool_group_noc_wrapper input logic icache_prefetch_enable_i, input logic [NrCores-1:0] cl_interrupt_i, input logic [$clog2(AxiAddrWidth)-1:0] dynamic_offset_i, - input logic [3:0] l1d_private_i, + input logic [$clog2(NumL1CtrlTile):0] l1d_private_i, input cache_insn_t l1d_insn_i, input logic l1d_insn_valid_i, output logic [NumTilesPerGroup-1:0] l1d_insn_ready_o, diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index e083de1..fd8a1bb 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -181,7 +181,7 @@ module cachepool_tile input logic [NrCores-1:0] cl_interrupt_i, input logic [$clog2(AxiAddrWidth)-1:0] dynamic_offset_i, input cache_insn_t l1d_insn_i, - input logic [3:0] l1d_private_i, + input logic [$clog2(NumL1CtrlTile):0] l1d_private_i, input logic l1d_insn_valid_i, output logic l1d_insn_ready_o, input logic l1d_busy_i, @@ -202,8 +202,8 @@ module cachepool_tile // Constants // --------- // TODO: Should be imported from Memory-mapped Reg - logic [2:0] num_private_cache; - assign num_private_cache = l1d_private_i[2:0]; + logic [$clog2(NumL1CtrlTile):0] num_private_cache; + assign num_private_cache = l1d_private_i [$clog2(NumL1CtrlTile):0]; /// Minimum width to hold the core number. // localparam int unsigned CoreIDWidth = cf_math_pkg::idx_width(NrCores); diff --git a/software/tests/gemv/script/gen_data.py b/software/tests/gemv/script/gen_data.py index 5c7e8eb..2a98add 100644 --- a/software/tests/gemv/script/gen_data.py +++ b/software/tests/gemv/script/gen_data.py @@ -76,17 +76,17 @@ def emit_gemv_layer(name="gemv", **kwargs): dtype = ctypes[str(kwargs["prec"])] if dtype != "char": layer_str += ( - f'static {dtype} {name}_A_dram [{m} * {n}] __attribute__((section(".data"))) = ' + f'static {dtype} {name}_A_dram [{m} * {n}] __attribute__((section(".pdcp_src"))) = ' + array_to_cstr(mat_A) + ";\n\n\n" ) layer_str += ( - f'static {dtype} {name}_B_dram [{n}] __attribute__((section(".data"))) = ' + f'static {dtype} {name}_B_dram [{n}] __attribute__((section(".pdcp_src"))) = ' + array_to_cstr(vec_B) + ";\n\n\n" ) layer_str += ( - f'static {dtype} {name}_result [{m}] __attribute__((section(".data"))) = ' + f'static {dtype} {name}_result [{m}] __attribute__((section(".pdcp_src"))) = ' + array_to_cstr(result) + ";\n\n\n" ) From 3dd812e9914da8a3ddc26cf7bdb97c6a06b9cee4 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Tue, 23 Jun 2026 18:01:53 +0200 Subject: [PATCH 15/39] [CFG] tiny config setup --- config/cachepool_fpu_2g_tiny.mk | 104 ++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 config/cachepool_fpu_2g_tiny.mk diff --git a/config/cachepool_fpu_2g_tiny.mk b/config/cachepool_fpu_2g_tiny.mk new file mode 100644 index 0000000..1da4b07 --- /dev/null +++ b/config/cachepool_fpu_2g_tiny.mk @@ -0,0 +1,104 @@ +# Copyright 2025 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Author: Diyou Shen, ETH Zurich + +######################### +## CachePool Cluster ## +######################### + +# Number of groups +num_groups ?= 2 + +# 1×2 mesh +num_groups_x ?= 1 + +# Number of tiles +num_tiles_per_group ?= 2 + +# Number of cores +num_cores_per_tile ?= 2 + +# Core datawidth +data_width ?= 32 + +# Core addrwidth +addr_width ?= 32 + +num_remote_ports_per_tile ?= 1 + +num_rg_ports_per_core ?= 1 + +num_noc_ports_per_tile ?= 1 + + +###################### +## CachePool Tile ## +###################### + +##### L1 Data Cache ##### + +# L1 data cacheline width (in Bit) +l1d_cacheline_width ?= 512 + +# L1 data cache banking factor (how many banks per core?) +l1d_bank_factor ?= 1 + +# L1 coalecsing window +l1d_coal_window ?= 2 + +# L1 data cache number of ways per +l1d_num_way ?= 4 + +# L1 data cache size per tile (KiB) +l1d_tile_size ?= 256 + +# L1 data cache tag width (TODO: should be calcualted) +l1d_tag_data_width ?= 92 + +#################### +## CachePool CC ## +#################### +# Spatz fpu support? +spatz_fpu_en ?= 1 + +# Spatz number of FPU +spatz_num_fpu ?= 4 + +# Spatz number of IPU +spatz_num_ipu ?= 4 + +# Spatz max outstanding transactions +spatz_max_trans ?= 32 + +# Snitch/FPU max outstanding transactions +snitch_max_trans ?= 16 + + +##################### +## L2 Main Memory ## +##################### +# DRAM type (selects DRAMSys config and sets default refill_data_width) +dram_type ?= HBM2 + +# L2 number of channels +l2_channel ?= 8 + +# L2 bank width (DRAM width, change with care) +l2_bank_width ?= 512 + +# L2 interleaving factor (in order of bank_width) +l2_interleave ?= 16 + +axi_user_width ?= 16 + + +################## +## Peripherals ## +################## +# Hardware stack size (in Byte) +stack_hw_size ?= 1024 + +# Stack size (total, including share and private, 32'h800) +stack_tot_size ?= 2048 From 39dc1dcd3cb7a5ecfaaa8f39a836fba4f1d9092c Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Wed, 24 Jun 2026 18:11:33 +0200 Subject: [PATCH 16/39] [SW] simple kernels to test private L1 functions --- config/cachepool_fpu_4g_tiny.mk | 104 ++++++++++++++++++++ hardware/src/cachepool_tile.sv | 4 +- software/tests/CMakeLists.txt | 3 + software/tests/lp1_private/main.c | 155 ++++++++++++++++++++++++++++++ software/tests/lp1_sanity/main.c | 94 ++++++++++++++++++ 5 files changed, 358 insertions(+), 2 deletions(-) create mode 100644 config/cachepool_fpu_4g_tiny.mk create mode 100644 software/tests/lp1_private/main.c create mode 100644 software/tests/lp1_sanity/main.c diff --git a/config/cachepool_fpu_4g_tiny.mk b/config/cachepool_fpu_4g_tiny.mk new file mode 100644 index 0000000..4f67515 --- /dev/null +++ b/config/cachepool_fpu_4g_tiny.mk @@ -0,0 +1,104 @@ +# Copyright 2025 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Author: Diyou Shen, ETH Zurich + +######################### +## CachePool Cluster ## +######################### + +# Number of groups +num_groups ?= 4 + +# 2×2 mesh +num_groups_x ?= 2 + +# Number of tiles +num_tiles_per_group ?= 2 + +# Number of cores +num_cores_per_tile ?= 2 + +# Core datawidth +data_width ?= 32 + +# Core addrwidth +addr_width ?= 32 + +num_remote_ports_per_tile ?= 1 + +num_rg_ports_per_core ?= 1 + +num_noc_ports_per_tile ?= 1 + + +###################### +## CachePool Tile ## +###################### + +##### L1 Data Cache ##### + +# L1 data cacheline width (in Bit) +l1d_cacheline_width ?= 512 + +# L1 data cache banking factor (how many banks per core?) +l1d_bank_factor ?= 1 + +# L1 coalecsing window +l1d_coal_window ?= 2 + +# L1 data cache number of ways per +l1d_num_way ?= 4 + +# L1 data cache size per tile (KiB) +l1d_tile_size ?= 256 + +# L1 data cache tag width (TODO: should be calcualted) +l1d_tag_data_width ?= 92 + +#################### +## CachePool CC ## +#################### +# Spatz fpu support? +spatz_fpu_en ?= 1 + +# Spatz number of FPU +spatz_num_fpu ?= 4 + +# Spatz number of IPU +spatz_num_ipu ?= 4 + +# Spatz max outstanding transactions +spatz_max_trans ?= 32 + +# Snitch/FPU max outstanding transactions +snitch_max_trans ?= 16 + + +##################### +## L2 Main Memory ## +##################### +# DRAM type (selects DRAMSys config and sets default refill_data_width) +dram_type ?= HBM2 + +# L2 number of channels +l2_channel ?= 8 + +# L2 bank width (DRAM width, change with care) +l2_bank_width ?= 512 + +# L2 interleaving factor (in order of bank_width) +l2_interleave ?= 16 + +axi_user_width ?= 16 + + +################## +## Peripherals ## +################## +# Hardware stack size (in Byte) +stack_hw_size ?= 1024 + +# Stack size (total, including share and private, 32'h800) +stack_tot_size ?= 2048 diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index fd8a1bb..d5d45bb 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -327,7 +327,7 @@ module cachepool_tile nRequesters: LP1NrRequesters, paWidth: 32, wordWidth: LP1WordWidth, - sets: 64, // TODO: 32 sets => 8KB/core target (currently 16KB) + sets: 32, ways: 4, clWords: 4, reqWords: 1, @@ -335,7 +335,7 @@ module cachepool_tile reqSrcIdWidth: 1, // selects requester port (0 Spatz / 1 Snitch) victimSel: hpdcache_pkg::HPDCACHE_VICTIM_PLRU, dataWaysPerRamWord: 1, - dataSetsPerRam: 64, + dataSetsPerRam: 32, dataRamByteEnable: 1'b1, accessWords: 4, mshrSets: 8, diff --git a/software/tests/CMakeLists.txt b/software/tests/CMakeLists.txt index 415547c..635b019 100644 --- a/software/tests/CMakeLists.txt +++ b/software/tests/CMakeLists.txt @@ -127,6 +127,9 @@ add_spatz_test_oneParam(idotp-32b idotp-32b/main.c 8192) add_spatz_test_oneParam(idotp-32b idotp-32b/main.c 32768) +add_spatz_test_zeroParam(lp1_sanity lp1_sanity/main.c) +add_spatz_test_zeroParam(lp1_private lp1_private/main.c) + add_spatz_test_zeroParam(load-store load-store/main.c) add_spatz_test_zeroParam(bandwidth bandwidth/main.c) diff --git a/software/tests/lp1_private/main.c b/software/tests/lp1_private/main.c new file mode 100644 index 0000000..3c3774a --- /dev/null +++ b/software/tests/lp1_private/main.c @@ -0,0 +1,155 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// LP1 private — Tier 1 per-core private-slice test for the private L1 (HPDcache) +// bring-up. +// +// Goal: prove the private-L1 load/store/refill/writeback datapath works when +// ALL cores drive it in parallel, WITHOUT any coherence. Every core owns a +// disjoint, cacheline-aligned slice of two arrays; no address is ever touched +// by two cores, so correctness must not depend on coherence. +// +// Two phases, each on the core's own slice: +// Phase A (scalar): write a known pattern, read it back, check. +// Phase B (vector): vle32/vse32 copy src -> dst, then scalar-verify dst. +// Phase B exercises the Spatz coalescer scatter/gather through the L1. +// +// Why no false sharing: WORDS_PER_CORE is a multiple of the 16-word (64-byte) +// cacheline and the arrays are 64-byte aligned, so each core's slice occupies +// whole cachelines that no other core touches. With private L1s and no +// coherence this is exactly the case that MUST still pass. +// +// Reporting is serialized round-robin with the HARDWARE barrier (coherence- +// independent MMIO register) instead of a shared reduction, so the verdict +// itself introduces no cross-core sharing. Each core prints its own PASS/FAIL; +// CI greps for "FAIL". + +#include +#include +#include +#include + +// 512-bit cacheline = 64 bytes = 16 x uint32. Keep the per-core slice a whole +// number of cachelines so adjacent cores never share a line. +#define CL_WORDS 16U +#define LINES_PER_CORE 4U +#define WORDS_PER_CORE (CL_WORDS * LINES_PER_CORE) // 64 words = 4 cachelines + +// Upper bound on cores across the configs we build (fpu_2g=32, fpu_4g=64, +// tiny variants fewer). Sized generously; only the first num_cores slices are +// touched. +#define LP1_MAX_CORES 64U + +// Two private arrays, cacheline-aligned, in cacheable .data (reached through +// the L1). Each core touches only [cid*WORDS_PER_CORE : +WORDS_PER_CORE). +static volatile uint32_t priv_src[LP1_MAX_CORES * WORDS_PER_CORE] + __attribute__((aligned(64))) __attribute__((section(".data"))); +static volatile uint32_t priv_dst[LP1_MAX_CORES * WORDS_PER_CORE] + __attribute__((aligned(64))) __attribute__((section(".data"))); + +uint32_t s_errors [32] __attribute__((section(".data"))) = {0}; +uint32_t v_errors [32] __attribute__((section(".data"))) = {0}; + +// Per-core expected pattern: distinct per core and per index. +static inline uint32_t pattern(uint32_t cid, uint32_t i) { + return (cid << 24) | (0x00ABCD00u) | (i & 0xFFu); +} + +// Vector copy count words from src to dst (both this core's private slice). +static void vec_copy(volatile uint32_t *dst, volatile uint32_t *src, + uint32_t count) { + uint32_t avl = count; + uint32_t vl; + do { + asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(avl)); + asm volatile("vle32.v v0, (%0)" ::"r"(src)); + asm volatile("vse32.v v0, (%0)" ::"r"(dst)); + src += vl; + dst += vl; + avl -= vl; + } while (avl > 0); +} + +int main() { + const uint32_t num_cores = snrt_cluster_core_num(); + const uint32_t cid = snrt_cluster_core_idx(); + + // Cores beyond the static capacity must not run (would alias another slice). + const uint32_t active = (num_cores < LP1_MAX_CORES) ? num_cores : LP1_MAX_CORES; + + volatile uint32_t *my_src = priv_src + cid * WORDS_PER_CORE; + volatile uint32_t *my_dst = priv_dst + cid * WORDS_PER_CORE; + + // uint32_t s_errors = 0; + // uint32_t v_errors = 0; + + if (cid == 0) { + printf("\n*** LP1 private (Tier 1: per-core private slices) ***\n"); + printf("Cores:%u words/core:%u (%u cachelines)\n", + num_cores, WORDS_PER_CORE, LINES_PER_CORE); + } + snrt_cluster_hw_barrier(); + + if (cid < active) { + // ----- Phase A: scalar write then read-back on own slice ----- + for (uint32_t i = 0; i < WORDS_PER_CORE; i++) + my_src[i] = pattern(cid, i); + for (uint32_t i = 0; i < WORDS_PER_CORE; i++) { + uint32_t got = my_src[i]; + uint32_t exp = pattern(cid, i); + // if (got != exp) s_errors++; + if (got != exp) s_errors[cid]++; + } + + snrt_fence(); + + // ----- Phase B: vector copy src -> dst, then scalar verify dst ----- + for (uint32_t i = 0; i < WORDS_PER_CORE; i++) + my_dst[i] = 0u; // clear so a no-op copy can't masquerade as success + snrt_fence_spatz(); // order Snitch clear-stores BEFORE the Spatz vector stores + vec_copy(my_dst, my_src, WORDS_PER_CORE); + snrt_fence_spatz(); // drain Spatz vector stores BEFORE the Snitch scalar reads + for (uint32_t i = 0; i < WORDS_PER_CORE; i++) { + uint32_t got = my_dst[i]; + uint32_t exp = pattern(cid, i); + // if (got != exp) v_errors++; + if (got != exp) v_errors[cid]++; + } + + // snrt_fence(); + } + + snrt_cluster_hw_barrier(); + + // Serialized per-core reporting: round-robin gated by the HW barrier, so no + // shared memory and no coherence are involved in producing the verdict. + for (uint32_t k = 0; k < active; k++) { + if (cid == k) { + // if (s_errors == 0 && v_errors == 0) + if (s_errors[cid] == 0 && v_errors[cid] == 0) + printf(" core %2u: PASS\n", cid); + else + printf(" core %2u: FAIL (scalar errors: %u, vector errors: %u)\n", cid, s_errors[cid], v_errors[cid]); + } + snrt_cluster_hw_barrier(); + } + + if (cid == 0) + printf("*** LP1 private complete ***\n"); + + snrt_cluster_hw_barrier(); + return 0; +} diff --git a/software/tests/lp1_sanity/main.c b/software/tests/lp1_sanity/main.c new file mode 100644 index 0000000..7339ff8 --- /dev/null +++ b/software/tests/lp1_sanity/main.c @@ -0,0 +1,94 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// LP1 sanity — Tier 0 single-core smoke test for the private L1 (HPDcache) +// bring-up. +// +// Goal: the absolute floor. Prove that, with a per-core private L1 inserted and +// NO cache coherence, the system still boots, a single core can drive the L1 +// scalar load/store datapath, reach the UART, synchronize via the HARDWARE +// barrier, and signal EOC. Nothing here is shared between cores, so the result +// must NOT depend on coherence. +// +// Deliberately avoided at this stage: +// - cache partitioning (l1d_part) and partition-boundary tricks, +// - selective private/shared flush, +// - the bank-interleave offset config (l1d_xbar_config), +// - any cross-core shared address. +// Those belong to later tiers; keeping them out makes a failure here +// unambiguously a core / L1-datapath / boot problem. +// +// Only core 0 does work. Every other core simply parks on the hardware barrier. +// snrt_cluster_hw_barrier() resolves to a hardware barrier MMIO register, so it +// is coherence-independent and safe to rely on here. + +#include +#include +#include +#include + +// Number of scalar words core 0 round-trips through its private L1. +#define SANITY_WORDS 16 + +// Private scratch in cacheable .data. Touched ONLY by core 0 — never shared, +// so no coherence is required for the round-trip below. +static volatile uint32_t sanity_buf[SANITY_WORDS] + __attribute__((section(".data"))); + +int main() { + const uint32_t num_cores = snrt_cluster_core_num(); + const uint32_t cid = snrt_cluster_core_idx(); + + // Initial rendezvous: confirms every core booted and the HW barrier works + // before core 0 starts driving the L1. + snrt_cluster_hw_barrier(); + + if (cid == 0) { + printf("\n*** LP1 sanity (Tier 0: single-core smoke) ***\n"); + printf("Cores:%u (only core 0 active)\n", num_cores); + + uint32_t errors = 0; + + // Scalar write phase: drive SANITY_WORDS stores into the private L1. + for (uint32_t i = 0; i < SANITY_WORDS; i++) { + sanity_buf[i] = 0xC0DE0000u + i; + } + + // Scalar read-back phase: pull them back and check. A correct private L1 + // must return exactly what was written (hit-on-own-write, then refill on a + // re-read after eviction is implicitly exercised by the small footprint). + for (uint32_t i = 0; i < SANITY_WORDS; i++) { + uint32_t got = sanity_buf[i]; + uint32_t exp = 0xC0DE0000u + i; + if (got != exp) { + printf(" FAIL idx %u exp 0x%08x got 0x%08x\n", i, exp, got); + errors++; + } + } + + if (errors == 0) + printf("lp1_sanity: PASS\n"); + else + printf("lp1_sanity: FAIL (%u errors)\n", errors); + + printf("*** LP1 sanity complete ***\n"); + } + + // Final rendezvous so no core races ahead to EOC before core 0 is done. + snrt_cluster_hw_barrier(); + + return 0; +} From a452ce8088227799860d72e8c8e15b821b2c1df4 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Thu, 25 Jun 2026 16:42:45 +0200 Subject: [PATCH 17/39] [CFG][SW] init 4x4 mesh build; replacement/refill sw test --- Makefile | 2 +- config/floonoc_cachepool_16g.yml | 96 +++ hardware/generated/floo_cachepool_noc_pkg.sv | 855 ++++++++++++++++--- hardware/src/cachepool_l1_ctrl.sv | 2 +- software/tests/CMakeLists.txt | 1 + software/tests/lp1_eviction/main.c | 182 ++++ software/tests/lp1_private/main.c | 17 +- software/tests/lp1_sanity/main.c | 2 + 8 files changed, 1034 insertions(+), 123 deletions(-) create mode 100644 config/floonoc_cachepool_16g.yml create mode 100644 software/tests/lp1_eviction/main.c diff --git a/Makefile b/Makefile index d3dcc51..ad6caf8 100644 --- a/Makefile +++ b/Makefile @@ -168,7 +168,7 @@ $(BOOTROM_DIR)/bootrom.sv: $(BOOTROM_DIR)/bootrom.bin $(BOOTROM_DIR)/bootdata.cc ########### FLOO_DIR ?= $(shell $(BENDER_INSTALL_DIR)/bender path floo_noc) FLOO_GEN_OUTDIR ?= $(ROOT_DIR)/hardware/generated -FLOO_CFG ?= $(ROOT_DIR)/config/floonoc_cachepool_4g.yml +FLOO_CFG ?= $(ROOT_DIR)/config/floonoc_cachepool_16g.yml FLOO_NAME = cachepool FLOO_NOC ?= $(FLOO_GEN_OUTDIR)/floo_$(FLOO_NAME)_noc_pkg.sv diff --git a/config/floonoc_cachepool_16g.yml b/config/floonoc_cachepool_16g.yml new file mode 100644 index 0000000..c295846 --- /dev/null +++ b/config/floonoc_cachepool_16g.yml @@ -0,0 +1,96 @@ +# Copyright 2025 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# 4x4 group mesh for the cachepool_fpu_16g / _16g_tiny configs (num_groups=16, +# num_groups_x=4 => num_groups_y=4). Faithful extension of the 2x2 +# floonoc_cachepool_4g.yml. CHECK BEFORE TRUSTING: the HBM endpoint count (8 = +# one per mesh row on each of the west/east edges, i.e. 2*num_groups_y) and the +# HBM addr_range stride are extrapolated from the 4g pattern; confirm they match +# the 16g memory map / DRAMSys backing. + +name: cachepool +description: "CachePool AXI NoC" +network_type: "axi" + +routing: + route_algo: "SRC" + use_id_table: true + +protocols: + - name: "wide_in" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 + - name: "wide_out" + type: "wide" + protocol: "AXI4" + data_width: 256 + addr_width: 32 + id_width: 2 + user_width: 1 + +endpoints: + - name: "group" + array: [4, 4] + mgr_port_protocol: + - "wide_in" + - name: "hbm" + array: [8] + addr_range: + base: 0x8000_0000 + size: 0x0010_0000 + sbr_port_protocol: + - "wide_out" + - name: "host_peri" + addr_range: + - start: 0x0000_0000 + end: 0x7FFF_FFFF + - start: 0xA000_0000 + end: 0xC000_FFFF + mgr_port_protocol: + - "wide_in" + sbr_port_protocol: + - "wide_out" + +routers: + - name: "group_router" + array: [4, 4] + degree: 5 + +connections: + - src: "group" + dst: "group_router" + src_range: + - [0, 3] + - [0, 3] + dst_range: + - [0, 3] + - [0, 3] + dst_dir: "Eject" + # HBM West (4, one per mesh row on the west edge) + - src: "hbm" + dst: "group_router" + src_range: + - [0, 3] + dst_range: + - [0, 0] + - [0, 3] + dst_dir: "West" + # HBM East (4, one per mesh row on the east edge) + - src: "hbm" + dst: "group_router" + src_range: + - [4, 7] + dst_range: + - [3, 3] + - [0, 3] + dst_dir: "East" + # Special + - src: "host_peri" + dst: "group_router" + dst_idx: [0, 0] + dst_dir: "South" diff --git a/hardware/generated/floo_cachepool_noc_pkg.sv b/hardware/generated/floo_cachepool_noc_pkg.sv index e475728..de13767 100644 --- a/hardware/generated/floo_cachepool_noc_pkg.sv +++ b/hardware/generated/floo_cachepool_noc_pkg.sv @@ -11,37 +11,66 @@ package floo_cachepool_noc_pkg; import floo_pkg::*; + ///////////////////////////// + // Endpoint Dimensions // + ///////////////////////////// + + localparam int unsigned NumGroupX = 4; +localparam int unsigned NumGroupY = 4; +localparam int unsigned NumHbm = 8; + + ///////////////////// // Address Map // ///////////////////// - typedef enum logic[3:0] { + typedef enum logic[4:0] { GroupX0Y0 = 0, GroupX0Y1 = 1, - GroupX1Y0 = 2, - GroupX1Y1 = 3, - Hbm0 = 4, - Hbm1 = 5, - Hbm2 = 6, - Hbm3 = 7, - HostPeri = 8, - NumEndpoints = 9} ep_id_e; + GroupX0Y2 = 2, + GroupX0Y3 = 3, + GroupX1Y0 = 4, + GroupX1Y1 = 5, + GroupX1Y2 = 6, + GroupX1Y3 = 7, + GroupX2Y0 = 8, + GroupX2Y1 = 9, + GroupX2Y2 = 10, + GroupX2Y3 = 11, + GroupX3Y0 = 12, + GroupX3Y1 = 13, + GroupX3Y2 = 14, + GroupX3Y3 = 15, + Hbm0 = 16, + Hbm1 = 17, + Hbm2 = 18, + Hbm3 = 19, + Hbm4 = 20, + Hbm5 = 21, + Hbm6 = 22, + Hbm7 = 23, + HostPeri = 24, + NumEndpoints = 25} ep_id_e; - typedef enum logic[2:0] { + typedef enum logic[3:0] { Hbm0SamIdx = 0, Hbm1SamIdx = 1, Hbm2SamIdx = 2, Hbm3SamIdx = 3, - HostPeriSamIdx = 5} sam_idx_e; + Hbm4SamIdx = 4, + Hbm5SamIdx = 5, + Hbm6SamIdx = 6, + Hbm7SamIdx = 7, + HostPeriSamIdx = 9} sam_idx_e; typedef logic[0:0] rob_idx_t; typedef logic[0:0] port_id_t; -typedef logic[3:0] id_t; -typedef logic[8:0] route_t; +typedef logic[4:0] id_t; +typedef logic[20:0] route_t; typedef struct packed { @@ -50,7 +79,7 @@ typedef logic[8:0] route_t; id_t end_addr; } route_map_rule_t; - localparam int unsigned SamNumRules = 6; + localparam int unsigned SamNumRules = 10; typedef struct packed { id_t idx; @@ -59,22 +88,34 @@ typedef struct packed { } sam_rule_t; localparam sam_rule_t[SamNumRules-1:0] Sam = '{ -'{ idx: 8, +'{ idx: 24, start_addr: 32'h00000000, end_addr: 32'h7fffffff},// HostPeri -'{ idx: 8, +'{ idx: 24, start_addr: 32'ha0000000, end_addr: 32'hc000ffff},// HostPeri -'{ idx: 7, +'{ idx: 23, + start_addr: 32'h80700000, + end_addr: 32'h80800000},// Hbm7 +'{ idx: 22, + start_addr: 32'h80600000, + end_addr: 32'h80700000},// Hbm6 +'{ idx: 21, + start_addr: 32'h80500000, + end_addr: 32'h80600000},// Hbm5 +'{ idx: 20, + start_addr: 32'h80400000, + end_addr: 32'h80500000},// Hbm4 +'{ idx: 19, start_addr: 32'h80300000, end_addr: 32'h80400000},// Hbm3 -'{ idx: 6, +'{ idx: 18, start_addr: 32'h80200000, end_addr: 32'h80300000},// Hbm2 -'{ idx: 5, +'{ idx: 17, start_addr: 32'h80100000, end_addr: 32'h80200000},// Hbm1 -'{ idx: 4, +'{ idx: 16, start_addr: 32'h80000000, end_addr: 32'h80100000} // Hbm0 @@ -83,103 +124,679 @@ localparam sam_rule_t[SamNumRules-1:0] Sam = '{ localparam route_t[NumEndpoints-1:0][NumEndpoints-1:0] RoutingTables = '{ '{ -9'b000000000,// -> host_peri_ni -9'b001001000,// -> hbm_ni_3 -9'b000001001,// -> hbm_ni_2 -9'b000011000,// -> hbm_ni_1 -9'b000000011,// -> hbm_ni_0 -9'b100001000,// -> group_ni_1_1 -9'b000100001,// -> group_ni_1_0 -9'b000100000,// -> group_ni_0_1 -9'b000000100 // -> group_ni_0_0 -}, -'{ -9'b010010011,// -> host_peri_ni -9'b000000000,// -> hbm_ni_3 -9'b000000000,// -> hbm_ni_2 -9'b000000000,// -> hbm_ni_1 -9'b000000000,// -> hbm_ni_0 -9'b000000100,// -> group_ni_1_1 -9'b000100010,// -> group_ni_1_0 -9'b000100011,// -> group_ni_0_1 -9'b100010011 // -> group_ni_0_0 -}, -'{ -9'b000010011,// -> host_peri_ni -9'b000000000,// -> hbm_ni_3 -9'b000000000,// -> hbm_ni_2 -9'b000000000,// -> hbm_ni_1 -9'b000000000,// -> hbm_ni_0 -9'b000100000,// -> group_ni_1_1 -9'b000000100,// -> group_ni_1_0 -9'b100000011,// -> group_ni_0_1 -9'b000100011 // -> group_ni_0_0 -}, -'{ -9'b000010010,// -> host_peri_ni -9'b000000000,// -> hbm_ni_3 -9'b000000000,// -> hbm_ni_2 -9'b000000000,// -> hbm_ni_1 -9'b000000000,// -> hbm_ni_0 -9'b000100001,// -> group_ni_1_1 -9'b100001010,// -> group_ni_1_0 -9'b000000100,// -> group_ni_0_1 -9'b000100010 // -> group_ni_0_0 -}, -'{ -9'b000000010,// -> host_peri_ni -9'b000000000,// -> hbm_ni_3 -9'b000000000,// -> hbm_ni_2 -9'b000000000,// -> hbm_ni_1 -9'b000000000,// -> hbm_ni_0 -9'b100001000,// -> group_ni_1_1 -9'b000100001,// -> group_ni_1_0 -9'b000100000,// -> group_ni_0_1 -9'b000000100 // -> group_ni_0_0 -}, -'{ -9'b010010011,// -> host_peri_ni -9'b000000001,// -> hbm_ni_3 -9'b000001010,// -> hbm_ni_2 -9'b000011011,// -> hbm_ni_1 -9'b011010011,// -> hbm_ni_0 -9'b000000000,// -> group_ni_1_1 -9'b000000000,// -> group_ni_1_0 -9'b000000000,// -> group_ni_0_1 -9'b000000000 // -> group_ni_0_0 -}, -'{ -9'b000010011,// -> host_peri_ni -9'b000001000,// -> hbm_ni_3 -9'b000000001,// -> hbm_ni_2 -9'b011000011,// -> hbm_ni_1 -9'b000011011,// -> hbm_ni_0 -9'b000000000,// -> group_ni_1_1 -9'b000000000,// -> group_ni_1_0 -9'b000000000,// -> group_ni_0_1 -9'b000000000 // -> group_ni_0_0 -}, -'{ -9'b000010010,// -> host_peri_ni -9'b000001001,// -> hbm_ni_3 -9'b001001010,// -> hbm_ni_2 -9'b000000011,// -> hbm_ni_1 -9'b000011010,// -> hbm_ni_0 -9'b000000000,// -> group_ni_1_1 -9'b000000000,// -> group_ni_1_0 -9'b000000000,// -> group_ni_0_1 -9'b000000000 // -> group_ni_0_0 -}, -'{ -9'b000000010,// -> host_peri_ni -9'b001001000,// -> hbm_ni_3 -9'b000001001,// -> hbm_ni_2 -9'b000011000,// -> hbm_ni_1 -9'b000000011,// -> hbm_ni_0 -9'b000000000,// -> group_ni_1_1 -9'b000000000,// -> group_ni_1_0 -9'b000000000,// -> group_ni_0_1 -9'b000000000 // -> group_ni_0_0 +21'b000000000000000000000,// -> host_peri_ni +21'b001001001001000000000,// -> hbm_ni_7 +21'b000001001001001000000,// -> hbm_ni_6 +21'b000000001001001001000,// -> hbm_ni_5 +21'b000000000001001001001,// -> hbm_ni_4 +21'b000000000011000000000,// -> hbm_ni_3 +21'b000000000000011000000,// -> hbm_ni_2 +21'b000000000000000011000,// -> hbm_ni_1 +21'b000000000000000000011,// -> hbm_ni_0 +21'b100001001001000000000,// -> group_ni_3_3 +21'b000100001001001000000,// -> group_ni_3_2 +21'b000000100001001001000,// -> group_ni_3_1 +21'b000000000100001001001,// -> group_ni_3_0 +21'b000100001001000000000,// -> group_ni_2_3 +21'b000000100001001000000,// -> group_ni_2_2 +21'b000000000100001001000,// -> group_ni_2_1 +21'b000000000000100001001,// -> group_ni_2_0 +21'b000000100001000000000,// -> group_ni_1_3 +21'b000000000100001000000,// -> group_ni_1_2 +21'b000000000000100001000,// -> group_ni_1_1 +21'b000000000000000100001,// -> group_ni_1_0 +21'b000000000100000000000,// -> group_ni_0_3 +21'b000000000000100000000,// -> group_ni_0_2 +21'b000000000000000100000,// -> group_ni_0_1 +21'b000000000000000000100 // -> group_ni_0_0 +}, +'{ +21'b010010010010011011011,// -> host_peri_ni +21'b000000000000000000000,// -> hbm_ni_7 +21'b000000000000000000000,// -> hbm_ni_6 +21'b000000000000000000000,// -> hbm_ni_5 +21'b000000000000000000000,// -> hbm_ni_4 +21'b000000000000000000000,// -> hbm_ni_3 +21'b000000000000000000000,// -> hbm_ni_2 +21'b000000000000000000000,// -> hbm_ni_1 +21'b000000000000000000000,// -> hbm_ni_0 +21'b000000000000000000100,// -> group_ni_3_3 +21'b000000000000000100010,// -> group_ni_3_2 +21'b000000000000100010010,// -> group_ni_3_1 +21'b000000000100010010010,// -> group_ni_3_0 +21'b000000000000000100011,// -> group_ni_2_3 +21'b000000000000100010011,// -> group_ni_2_2 +21'b000000000100010010011,// -> group_ni_2_1 +21'b000000100010010010011,// -> group_ni_2_0 +21'b000000000000100011011,// -> group_ni_1_3 +21'b000000000100010011011,// -> group_ni_1_2 +21'b000000100010010011011,// -> group_ni_1_1 +21'b000100010010010011011,// -> group_ni_1_0 +21'b000000000100011011011,// -> group_ni_0_3 +21'b000000100010011011011,// -> group_ni_0_2 +21'b000100010010011011011,// -> group_ni_0_1 +21'b100010010010011011011 // -> group_ni_0_0 +}, +'{ +21'b000010010010011011011,// -> host_peri_ni +21'b000000000000000000000,// -> hbm_ni_7 +21'b000000000000000000000,// -> hbm_ni_6 +21'b000000000000000000000,// -> hbm_ni_5 +21'b000000000000000000000,// -> hbm_ni_4 +21'b000000000000000000000,// -> hbm_ni_3 +21'b000000000000000000000,// -> hbm_ni_2 +21'b000000000000000000000,// -> hbm_ni_1 +21'b000000000000000000000,// -> hbm_ni_0 +21'b000000000000000100000,// -> group_ni_3_3 +21'b000000000000000000100,// -> group_ni_3_2 +21'b000000000000000100010,// -> group_ni_3_1 +21'b000000000000100010010,// -> group_ni_3_0 +21'b000000000000100000011,// -> group_ni_2_3 +21'b000000000000000100011,// -> group_ni_2_2 +21'b000000000000100010011,// -> group_ni_2_1 +21'b000000000100010010011,// -> group_ni_2_0 +21'b000000000100000011011,// -> group_ni_1_3 +21'b000000000000100011011,// -> group_ni_1_2 +21'b000000000100010011011,// -> group_ni_1_1 +21'b000000100010010011011,// -> group_ni_1_0 +21'b000000100000011011011,// -> group_ni_0_3 +21'b000000000100011011011,// -> group_ni_0_2 +21'b000000100010011011011,// -> group_ni_0_1 +21'b000100010010011011011 // -> group_ni_0_0 +}, +'{ +21'b000000010010011011011,// -> host_peri_ni +21'b000000000000000000000,// -> hbm_ni_7 +21'b000000000000000000000,// -> hbm_ni_6 +21'b000000000000000000000,// -> hbm_ni_5 +21'b000000000000000000000,// -> hbm_ni_4 +21'b000000000000000000000,// -> hbm_ni_3 +21'b000000000000000000000,// -> hbm_ni_2 +21'b000000000000000000000,// -> hbm_ni_1 +21'b000000000000000000000,// -> hbm_ni_0 +21'b000000000000100000000,// -> group_ni_3_3 +21'b000000000000000100000,// -> group_ni_3_2 +21'b000000000000000000100,// -> group_ni_3_1 +21'b000000000000000100010,// -> group_ni_3_0 +21'b000000000100000000011,// -> group_ni_2_3 +21'b000000000000100000011,// -> group_ni_2_2 +21'b000000000000000100011,// -> group_ni_2_1 +21'b000000000000100010011,// -> group_ni_2_0 +21'b000000100000000011011,// -> group_ni_1_3 +21'b000000000100000011011,// -> group_ni_1_2 +21'b000000000000100011011,// -> group_ni_1_1 +21'b000000000100010011011,// -> group_ni_1_0 +21'b000100000000011011011,// -> group_ni_0_3 +21'b000000100000011011011,// -> group_ni_0_2 +21'b000000000100011011011,// -> group_ni_0_1 +21'b000000100010011011011 // -> group_ni_0_0 +}, +'{ +21'b000000000010011011011,// -> host_peri_ni +21'b000000000000000000000,// -> hbm_ni_7 +21'b000000000000000000000,// -> hbm_ni_6 +21'b000000000000000000000,// -> hbm_ni_5 +21'b000000000000000000000,// -> hbm_ni_4 +21'b000000000000000000000,// -> hbm_ni_3 +21'b000000000000000000000,// -> hbm_ni_2 +21'b000000000000000000000,// -> hbm_ni_1 +21'b000000000000000000000,// -> hbm_ni_0 +21'b000000000100000000000,// -> group_ni_3_3 +21'b000000000000100000000,// -> group_ni_3_2 +21'b000000000000000100000,// -> group_ni_3_1 +21'b000000000000000000100,// -> group_ni_3_0 +21'b000000100000000000011,// -> group_ni_2_3 +21'b000000000100000000011,// -> group_ni_2_2 +21'b000000000000100000011,// -> group_ni_2_1 +21'b000000000000000100011,// -> group_ni_2_0 +21'b000100000000000011011,// -> group_ni_1_3 +21'b000000100000000011011,// -> group_ni_1_2 +21'b000000000100000011011,// -> group_ni_1_1 +21'b000000000000100011011,// -> group_ni_1_0 +21'b100000000000011011011,// -> group_ni_0_3 +21'b000100000000011011011,// -> group_ni_0_2 +21'b000000100000011011011,// -> group_ni_0_1 +21'b000000000100011011011 // -> group_ni_0_0 +}, +'{ +21'b000000000010010010010,// -> host_peri_ni +21'b000000000000000000000,// -> hbm_ni_7 +21'b000000000000000000000,// -> hbm_ni_6 +21'b000000000000000000000,// -> hbm_ni_5 +21'b000000000000000000000,// -> hbm_ni_4 +21'b000000000000000000000,// -> hbm_ni_3 +21'b000000000000000000000,// -> hbm_ni_2 +21'b000000000000000000000,// -> hbm_ni_1 +21'b000000000000000000000,// -> hbm_ni_0 +21'b000000000100001001001,// -> group_ni_3_3 +21'b000000100001001001010,// -> group_ni_3_2 +21'b000100001001001010010,// -> group_ni_3_1 +21'b100001001001010010010,// -> group_ni_3_0 +21'b000000000000100001001,// -> group_ni_2_3 +21'b000000000100001001010,// -> group_ni_2_2 +21'b000000100001001010010,// -> group_ni_2_1 +21'b000100001001010010010,// -> group_ni_2_0 +21'b000000000000000100001,// -> group_ni_1_3 +21'b000000000000100001010,// -> group_ni_1_2 +21'b000000000100001010010,// -> group_ni_1_1 +21'b000000100001010010010,// -> group_ni_1_0 +21'b000000000000000000100,// -> group_ni_0_3 +21'b000000000000000100010,// -> group_ni_0_2 +21'b000000000000100010010,// -> group_ni_0_1 +21'b000000000100010010010 // -> group_ni_0_0 +}, +'{ +21'b000000000000010010010,// -> host_peri_ni +21'b000000000000000000000,// -> hbm_ni_7 +21'b000000000000000000000,// -> hbm_ni_6 +21'b000000000000000000000,// -> hbm_ni_5 +21'b000000000000000000000,// -> hbm_ni_4 +21'b000000000000000000000,// -> hbm_ni_3 +21'b000000000000000000000,// -> hbm_ni_2 +21'b000000000000000000000,// -> hbm_ni_1 +21'b000000000000000000000,// -> hbm_ni_0 +21'b000000100001001001000,// -> group_ni_3_3 +21'b000000000100001001001,// -> group_ni_3_2 +21'b000000100001001001010,// -> group_ni_3_1 +21'b000100001001001010010,// -> group_ni_3_0 +21'b000000000100001001000,// -> group_ni_2_3 +21'b000000000000100001001,// -> group_ni_2_2 +21'b000000000100001001010,// -> group_ni_2_1 +21'b000000100001001010010,// -> group_ni_2_0 +21'b000000000000100001000,// -> group_ni_1_3 +21'b000000000000000100001,// -> group_ni_1_2 +21'b000000000000100001010,// -> group_ni_1_1 +21'b000000000100001010010,// -> group_ni_1_0 +21'b000000000000000100000,// -> group_ni_0_3 +21'b000000000000000000100,// -> group_ni_0_2 +21'b000000000000000100010,// -> group_ni_0_1 +21'b000000000000100010010 // -> group_ni_0_0 +}, +'{ +21'b000000000000000010010,// -> host_peri_ni +21'b000000000000000000000,// -> hbm_ni_7 +21'b000000000000000000000,// -> hbm_ni_6 +21'b000000000000000000000,// -> hbm_ni_5 +21'b000000000000000000000,// -> hbm_ni_4 +21'b000000000000000000000,// -> hbm_ni_3 +21'b000000000000000000000,// -> hbm_ni_2 +21'b000000000000000000000,// -> hbm_ni_1 +21'b000000000000000000000,// -> hbm_ni_0 +21'b000100001001001000000,// -> group_ni_3_3 +21'b000000100001001001000,// -> group_ni_3_2 +21'b000000000100001001001,// -> group_ni_3_1 +21'b000000100001001001010,// -> group_ni_3_0 +21'b000000100001001000000,// -> group_ni_2_3 +21'b000000000100001001000,// -> group_ni_2_2 +21'b000000000000100001001,// -> group_ni_2_1 +21'b000000000100001001010,// -> group_ni_2_0 +21'b000000000100001000000,// -> group_ni_1_3 +21'b000000000000100001000,// -> group_ni_1_2 +21'b000000000000000100001,// -> group_ni_1_1 +21'b000000000000100001010,// -> group_ni_1_0 +21'b000000000000100000000,// -> group_ni_0_3 +21'b000000000000000100000,// -> group_ni_0_2 +21'b000000000000000000100,// -> group_ni_0_1 +21'b000000000000000100010 // -> group_ni_0_0 +}, +'{ +21'b000000000000000000010,// -> host_peri_ni +21'b000000000000000000000,// -> hbm_ni_7 +21'b000000000000000000000,// -> hbm_ni_6 +21'b000000000000000000000,// -> hbm_ni_5 +21'b000000000000000000000,// -> hbm_ni_4 +21'b000000000000000000000,// -> hbm_ni_3 +21'b000000000000000000000,// -> hbm_ni_2 +21'b000000000000000000000,// -> hbm_ni_1 +21'b000000000000000000000,// -> hbm_ni_0 +21'b100001001001000000000,// -> group_ni_3_3 +21'b000100001001001000000,// -> group_ni_3_2 +21'b000000100001001001000,// -> group_ni_3_1 +21'b000000000100001001001,// -> group_ni_3_0 +21'b000100001001000000000,// -> group_ni_2_3 +21'b000000100001001000000,// -> group_ni_2_2 +21'b000000000100001001000,// -> group_ni_2_1 +21'b000000000000100001001,// -> group_ni_2_0 +21'b000000100001000000000,// -> group_ni_1_3 +21'b000000000100001000000,// -> group_ni_1_2 +21'b000000000000100001000,// -> group_ni_1_1 +21'b000000000000000100001,// -> group_ni_1_0 +21'b000000000100000000000,// -> group_ni_0_3 +21'b000000000000100000000,// -> group_ni_0_2 +21'b000000000000000100000,// -> group_ni_0_1 +21'b000000000000000000100 // -> group_ni_0_0 +}, +'{ +21'b010010010010011011011,// -> host_peri_ni +21'b000000000000000000001,// -> hbm_ni_7 +21'b000000000000000001010,// -> hbm_ni_6 +21'b000000000000001010010,// -> hbm_ni_5 +21'b000000000001010010010,// -> hbm_ni_4 +21'b000000000011011011011,// -> hbm_ni_3 +21'b000000011010011011011,// -> hbm_ni_2 +21'b000011010010011011011,// -> hbm_ni_1 +21'b011010010010011011011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000010010010011011011,// -> host_peri_ni +21'b000000000000000001000,// -> hbm_ni_7 +21'b000000000000000000001,// -> hbm_ni_6 +21'b000000000000000001010,// -> hbm_ni_5 +21'b000000000000001010010,// -> hbm_ni_4 +21'b000000011000011011011,// -> hbm_ni_3 +21'b000000000011011011011,// -> hbm_ni_2 +21'b000000011010011011011,// -> hbm_ni_1 +21'b000011010010011011011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000010010011011011,// -> host_peri_ni +21'b000000000000001000000,// -> hbm_ni_7 +21'b000000000000000001000,// -> hbm_ni_6 +21'b000000000000000000001,// -> hbm_ni_5 +21'b000000000000000001010,// -> hbm_ni_4 +21'b000011000000011011011,// -> hbm_ni_3 +21'b000000011000011011011,// -> hbm_ni_2 +21'b000000000011011011011,// -> hbm_ni_1 +21'b000000011010011011011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000000010011011011,// -> host_peri_ni +21'b000000000001000000000,// -> hbm_ni_7 +21'b000000000000001000000,// -> hbm_ni_6 +21'b000000000000000001000,// -> hbm_ni_5 +21'b000000000000000000001,// -> hbm_ni_4 +21'b011000000000011011011,// -> hbm_ni_3 +21'b000011000000011011011,// -> hbm_ni_2 +21'b000000011000011011011,// -> hbm_ni_1 +21'b000000000011011011011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000010010010010011011,// -> host_peri_ni +21'b000000000000000001001,// -> hbm_ni_7 +21'b000000000000001001010,// -> hbm_ni_6 +21'b000000000001001010010,// -> hbm_ni_5 +21'b000000001001010010010,// -> hbm_ni_4 +21'b000000000000011011011,// -> hbm_ni_3 +21'b000000000011010011011,// -> hbm_ni_2 +21'b000000011010010011011,// -> hbm_ni_1 +21'b000011010010010011011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000010010010011011,// -> host_peri_ni +21'b000000000000001001000,// -> hbm_ni_7 +21'b000000000000000001001,// -> hbm_ni_6 +21'b000000000000001001010,// -> hbm_ni_5 +21'b000000000001001010010,// -> hbm_ni_4 +21'b000000000011000011011,// -> hbm_ni_3 +21'b000000000000011011011,// -> hbm_ni_2 +21'b000000000011010011011,// -> hbm_ni_1 +21'b000000011010010011011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000000010010011011,// -> host_peri_ni +21'b000000000001001000000,// -> hbm_ni_7 +21'b000000000000001001000,// -> hbm_ni_6 +21'b000000000000000001001,// -> hbm_ni_5 +21'b000000000000001001010,// -> hbm_ni_4 +21'b000000011000000011011,// -> hbm_ni_3 +21'b000000000011000011011,// -> hbm_ni_2 +21'b000000000000011011011,// -> hbm_ni_1 +21'b000000000011010011011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000000000010011011,// -> host_peri_ni +21'b000000001001000000000,// -> hbm_ni_7 +21'b000000000001001000000,// -> hbm_ni_6 +21'b000000000000001001000,// -> hbm_ni_5 +21'b000000000000000001001,// -> hbm_ni_4 +21'b000011000000000011011,// -> hbm_ni_3 +21'b000000011000000011011,// -> hbm_ni_2 +21'b000000000011000011011,// -> hbm_ni_1 +21'b000000000000011011011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000010010010010011,// -> host_peri_ni +21'b000000000000001001001,// -> hbm_ni_7 +21'b000000000001001001010,// -> hbm_ni_6 +21'b000000001001001010010,// -> hbm_ni_5 +21'b000001001001010010010,// -> hbm_ni_4 +21'b000000000000000011011,// -> hbm_ni_3 +21'b000000000000011010011,// -> hbm_ni_2 +21'b000000000011010010011,// -> hbm_ni_1 +21'b000000011010010010011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000000010010010011,// -> host_peri_ni +21'b000000000001001001000,// -> hbm_ni_7 +21'b000000000000001001001,// -> hbm_ni_6 +21'b000000000001001001010,// -> hbm_ni_5 +21'b000000001001001010010,// -> hbm_ni_4 +21'b000000000000011000011,// -> hbm_ni_3 +21'b000000000000000011011,// -> hbm_ni_2 +21'b000000000000011010011,// -> hbm_ni_1 +21'b000000000011010010011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000000000010010011,// -> host_peri_ni +21'b000000001001001000000,// -> hbm_ni_7 +21'b000000000001001001000,// -> hbm_ni_6 +21'b000000000000001001001,// -> hbm_ni_5 +21'b000000000001001001010,// -> hbm_ni_4 +21'b000000000011000000011,// -> hbm_ni_3 +21'b000000000000011000011,// -> hbm_ni_2 +21'b000000000000000011011,// -> hbm_ni_1 +21'b000000000000011010011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000000000000010011,// -> host_peri_ni +21'b000001001001000000000,// -> hbm_ni_7 +21'b000000001001001000000,// -> hbm_ni_6 +21'b000000000001001001000,// -> hbm_ni_5 +21'b000000000000001001001,// -> hbm_ni_4 +21'b000000011000000000011,// -> hbm_ni_3 +21'b000000000011000000011,// -> hbm_ni_2 +21'b000000000000011000011,// -> hbm_ni_1 +21'b000000000000000011011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000000010010010010,// -> host_peri_ni +21'b000000000001001001001,// -> hbm_ni_7 +21'b000000001001001001010,// -> hbm_ni_6 +21'b000001001001001010010,// -> hbm_ni_5 +21'b001001001001010010010,// -> hbm_ni_4 +21'b000000000000000000011,// -> hbm_ni_3 +21'b000000000000000011010,// -> hbm_ni_2 +21'b000000000000011010010,// -> hbm_ni_1 +21'b000000000011010010010,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000000000010010010,// -> host_peri_ni +21'b000000001001001001000,// -> hbm_ni_7 +21'b000000000001001001001,// -> hbm_ni_6 +21'b000000001001001001010,// -> hbm_ni_5 +21'b000001001001001010010,// -> hbm_ni_4 +21'b000000000000000011000,// -> hbm_ni_3 +21'b000000000000000000011,// -> hbm_ni_2 +21'b000000000000000011010,// -> hbm_ni_1 +21'b000000000000011010010,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000000000000010010,// -> host_peri_ni +21'b000001001001001000000,// -> hbm_ni_7 +21'b000000001001001001000,// -> hbm_ni_6 +21'b000000000001001001001,// -> hbm_ni_5 +21'b000000001001001001010,// -> hbm_ni_4 +21'b000000000000011000000,// -> hbm_ni_3 +21'b000000000000000011000,// -> hbm_ni_2 +21'b000000000000000000011,// -> hbm_ni_1 +21'b000000000000000011010,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 +}, +'{ +21'b000000000000000000010,// -> host_peri_ni +21'b001001001001000000000,// -> hbm_ni_7 +21'b000001001001001000000,// -> hbm_ni_6 +21'b000000001001001001000,// -> hbm_ni_5 +21'b000000000001001001001,// -> hbm_ni_4 +21'b000000000011000000000,// -> hbm_ni_3 +21'b000000000000011000000,// -> hbm_ni_2 +21'b000000000000000011000,// -> hbm_ni_1 +21'b000000000000000000011,// -> hbm_ni_0 +21'b000000000000000000000,// -> group_ni_3_3 +21'b000000000000000000000,// -> group_ni_3_2 +21'b000000000000000000000,// -> group_ni_3_1 +21'b000000000000000000000,// -> group_ni_3_0 +21'b000000000000000000000,// -> group_ni_2_3 +21'b000000000000000000000,// -> group_ni_2_2 +21'b000000000000000000000,// -> group_ni_2_1 +21'b000000000000000000000,// -> group_ni_2_0 +21'b000000000000000000000,// -> group_ni_1_3 +21'b000000000000000000000,// -> group_ni_1_2 +21'b000000000000000000000,// -> group_ni_1_1 +21'b000000000000000000000,// -> group_ni_1_0 +21'b000000000000000000000,// -> group_ni_0_3 +21'b000000000000000000000,// -> group_ni_0_2 +21'b000000000000000000000,// -> group_ni_0_1 +21'b000000000000000000000 // -> group_ni_0_0 }} ; @@ -189,8 +806,8 @@ localparam sam_rule_t[SamNumRules-1:0] Sam = '{ XYAddrOffsetX: 0, XYAddrOffsetY: 0, IdAddrOffset: 0, - NumSamRules: 6, - NumRoutes: 9, + NumSamRules: 10, + NumRoutes: 25, CollectiveCfg: '{ OpCfg: '{ EnNarrowMulticast: 1'b0, EnWideMulticast: 1'b0, EnLsbAnd: 1'b0, diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv index 0d59005..5c872b6 100644 --- a/hardware/src/cachepool_l1_ctrl.sv +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -2,7 +2,7 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // -// Author: Ho Tin Hung +// Author: Ho Tin Hung, ETH Zurich // // Per-core private L1 data cache controller. // diff --git a/software/tests/CMakeLists.txt b/software/tests/CMakeLists.txt index 635b019..ada3441 100644 --- a/software/tests/CMakeLists.txt +++ b/software/tests/CMakeLists.txt @@ -129,6 +129,7 @@ add_spatz_test_oneParam(idotp-32b idotp-32b/main.c 32768) add_spatz_test_zeroParam(lp1_sanity lp1_sanity/main.c) add_spatz_test_zeroParam(lp1_private lp1_private/main.c) +add_spatz_test_zeroParam(lp1_eviction lp1_eviction/main.c) add_spatz_test_zeroParam(load-store load-store/main.c) diff --git a/software/tests/lp1_eviction/main.c b/software/tests/lp1_eviction/main.c new file mode 100644 index 0000000..b1d16e1 --- /dev/null +++ b/software/tests/lp1_eviction/main.c @@ -0,0 +1,182 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Ho Tin Hung, ETH Zurich + +// LP1 eviction — capacity / replacement test for the private L1 (HPDcache). +// +// The earlier tiers (lp1_sanity, lp1_private) only ever touch a handful of +// cachelines per core, so the L1's replacement machinery NEVER fires: no line +// is ever evicted, no line is ever refilled-after-eviction. This test closes +// that gap. It is the difference between "behaves like a buffer" and "behaves +// like a cache". +// +// Every core works on a DISJOINT, cacheline-aligned private slice (no address +// is shared, so correctness must not depend on coherence -- exactly as in +// lp1_private). Within its own slice each core: +// +// Phase A (capacity): scalar-write a region several times the size of the L1, +// then read it back and verify. Because the working set far exceeds the +// 8 KB cache, the early lines are guaranteed to have been evicted by the +// time the last ones are written; reading them back forces a refill from +// L2. Correct read-back therefore proves the whole loop: write-through to +// L2, capacity eviction, and refill-after-eviction return the right data. +// This phase is geometry-INDEPENDENT: any working set > cache evicts. +// +// Phase B (conflict): touch (ways+N) distinct lines that all map to the SAME +// set, then read them all back. Since more lines than ways contend for one +// set, at least (lines-ways) of them must be evicted and refilled; correct +// read-back exercises per-set victim selection specifically. This phase +// ASSUMES direct bit-field set indexing (no set hashing); if that +// assumption is wrong it degrades to a strided access pattern that still +// passes -- it can never false-FAIL. +// +// No fence is placed between a core's own stores and the later loads to the +// same addresses: single-core read-after-write through eviction (store -> +// write-through -> evict -> load -> refill, including the write-buffer-vs-refill +// ordering inside HPDcache) is a correctness guarantee the cache MUST provide. +// Fencing here would mask exactly the kind of ordering bug this test should +// catch. +// +// Reporting is serialized round-robin via the HARDWARE barrier (coherence- +// independent MMIO register), and each core reports from LOCAL counters, so the +// verdict introduces no cross-core sharing whatsoever. CI greps for "FAIL". + +#include +#include +#include +#include + +// ---- L1 geometry: must track HPDcacheUserCfg in hardware/src/cachepool_tile.sv +#define CL_WORDS 16U // 64 B line = 16 x u32 +#define L1_SETS 32U +#define L1_WAYS 4U +#define L1_LINE_WORDS CL_WORDS +#define L1_WORDS (L1_SETS * L1_WAYS * L1_LINE_WORDS) // 2048 w = 8 KB + +// ---- Phase A: sweep a region SWEEP_MULT times the L1 to force capacity evict. +#define SWEEP_MULT 4U +#define SWEEP_WORDS (SWEEP_MULT * L1_WORDS) // 8192 w = 32 KB / core + +// ---- Phase B: lines spaced one whole cache (sets * line) apart share a set. +#define SET_STRIDE_WORDS (L1_SETS * L1_LINE_WORDS) // 512 w = 2 KB +#define CONFLICT_LINES (L1_WAYS + 4U) // 8 > ways -> evicts + +// Upper bound on cores across the configs we build (fpu_2g=32, fpu_4g=64). Only +// the first `active` slices are touched; larger configs simply idle the rest so +// no core ever aliases another's slice. +#define LP1_MAX_CORES 64U + +// Per-core private region, cacheline-aligned, in uninitialized cacheable DRAM +// scratch (.dram): reached through the L1 but not image-loaded or zeroed, so the +// 2 MB footprint costs nothing in the ELF. Every word is written before it is +// read, so the lack of zero-init is irrelevant. +static volatile uint32_t sweep_buf[LP1_MAX_CORES * SWEEP_WORDS] + __attribute__((aligned(64))) __attribute__((section(".dram"))); + +// Distinct per (core, index): a wrong-line refill returns a wrong index field, +// and a cross-core leak returns a wrong core field -- both are caught. +static inline uint32_t patA(uint32_t cid, uint32_t i) { + return ((cid & 0xFFu) << 24) | (i & 0x00FFFFFFu); +} +// Distinct per (core, conflict-line k). +static inline uint32_t patB(uint32_t cid, uint32_t k) { + return 0xB0000000u | ((cid & 0xFFFFu) << 8) | (k & 0xFFu); +} + +int main() { + const uint32_t num_cores = snrt_cluster_core_num(); + const uint32_t cid = snrt_cluster_core_idx(); + const uint32_t active = (num_cores < LP1_MAX_CORES) ? num_cores : LP1_MAX_CORES; + + volatile uint32_t *my_buf = sweep_buf + cid * SWEEP_WORDS; + + // Local counters only -> no shared state, no false sharing. + uint32_t cap_err = 0; + uint32_t conf_err = 0; + uint32_t first_bad_idx = 0xFFFFFFFFu; // for a single debug line on failure + uint32_t first_bad_exp = 0, first_bad_got = 0; + + if (cid == 0) { + printf("\n*** LP1 eviction (capacity + conflict replacement) ***\n"); + printf("Cores:%u L1:%uKB(%uw) sweep:%uKB(%uw, %ux L1) conflict:%u lines/set\n", + num_cores, (L1_WORDS * 4U) / 1024U, L1_WORDS, + (SWEEP_WORDS * 4U) / 1024U, SWEEP_WORDS, SWEEP_MULT, CONFLICT_LINES); + + start_kernel(); + } + snrt_cluster_hw_barrier(); + + if (cid < active) { + // ----- Phase A: capacity sweep ----- + // Write the whole oversized region; the front of it is evicted long before + // we reach the end. + for (uint32_t i = 0; i < SWEEP_WORDS; i++) + my_buf[i] = patA(cid, i); + // Read it all back; the evicted front must refill correctly from L2. + for (uint32_t i = 0; i < SWEEP_WORDS; i++) { + uint32_t got = my_buf[i]; + uint32_t exp = patA(cid, i); + if (got != exp) { + if (cap_err == 0) { first_bad_idx = i; first_bad_exp = exp; first_bad_got = got; } + cap_err++; + } + } + + // ----- Phase B: single-set conflict sweep ----- + // CONFLICT_LINES addresses, each SET_STRIDE_WORDS apart, all map to one set + // (assuming direct bit-field indexing). Writing more than `ways` of them + // forces evictions within that one set; reading them all back forces the + // evicted ones to refill. Touch one word (the line's first) per line. + for (uint32_t k = 0; k < CONFLICT_LINES; k++) + my_buf[k * SET_STRIDE_WORDS] = patB(cid, k); + // Read in reverse so the line written last (still resident) is checked + // first and the earliest (already evicted) is checked last. + for (uint32_t k = CONFLICT_LINES; k-- > 0;) { + uint32_t got = my_buf[k * SET_STRIDE_WORDS]; + uint32_t exp = patB(cid, k); + if (got != exp) conf_err++; + } + } + + snrt_cluster_hw_barrier(); + + if (cid == 0) { + stop_kernel(); + } + + // Serialized per-core reporting, round-robin gated by the HW barrier. + for (uint32_t k = 0; k < active; k++) { + if (cid == k) { + if (cap_err == 0 && conf_err == 0) { + printf(" core %2u: PASS\n", cid); + } else { + printf(" core %2u: FAIL (capacity errors: %u, conflict errors: %u)\n", + cid, cap_err, conf_err); + if (first_bad_idx != 0xFFFFFFFFu) + printf(" first cap miss @w%u exp 0x%08x got 0x%08x\n", + first_bad_idx, first_bad_exp, first_bad_got); + } + } + snrt_cluster_hw_barrier(); + } + + if (cid == 0) + printf("*** LP1 eviction complete ***\n"); + + snrt_cluster_hw_barrier(); + return 0; +} diff --git a/software/tests/lp1_private/main.c b/software/tests/lp1_private/main.c index 3c3774a..b5db381 100644 --- a/software/tests/lp1_private/main.c +++ b/software/tests/lp1_private/main.c @@ -14,6 +14,8 @@ // See the License for the specific language governing permissions and // limitations under the License. +// Author: Ho Tin Hung, ETH Zurich + // LP1 private — Tier 1 per-core private-slice test for the private L1 (HPDcache) // bring-up. // @@ -60,8 +62,8 @@ static volatile uint32_t priv_src[LP1_MAX_CORES * WORDS_PER_CORE] static volatile uint32_t priv_dst[LP1_MAX_CORES * WORDS_PER_CORE] __attribute__((aligned(64))) __attribute__((section(".data"))); -uint32_t s_errors [32] __attribute__((section(".data"))) = {0}; -uint32_t v_errors [32] __attribute__((section(".data"))) = {0}; +uint32_t s_errors [LP1_MAX_CORES] __attribute__((section(".data"))) = {0}; +uint32_t v_errors [LP1_MAX_CORES] __attribute__((section(".data"))) = {0}; // Per-core expected pattern: distinct per core and per index. static inline uint32_t pattern(uint32_t cid, uint32_t i) { @@ -100,7 +102,10 @@ int main() { printf("\n*** LP1 private (Tier 1: per-core private slices) ***\n"); printf("Cores:%u words/core:%u (%u cachelines)\n", num_cores, WORDS_PER_CORE, LINES_PER_CORE); + + start_kernel(); } + snrt_cluster_hw_barrier(); if (cid < active) { @@ -119,9 +124,13 @@ int main() { // ----- Phase B: vector copy src -> dst, then scalar verify dst ----- for (uint32_t i = 0; i < WORDS_PER_CORE; i++) my_dst[i] = 0u; // clear so a no-op copy can't masquerade as success + snrt_fence_spatz(); // order Snitch clear-stores BEFORE the Spatz vector stores + vec_copy(my_dst, my_src, WORDS_PER_CORE); + snrt_fence_spatz(); // drain Spatz vector stores BEFORE the Snitch scalar reads + for (uint32_t i = 0; i < WORDS_PER_CORE; i++) { uint32_t got = my_dst[i]; uint32_t exp = pattern(cid, i); @@ -134,6 +143,10 @@ int main() { snrt_cluster_hw_barrier(); + if (cid == 0) { + stop_kernel(); + } + // Serialized per-core reporting: round-robin gated by the HW barrier, so no // shared memory and no coherence are involved in producing the verdict. for (uint32_t k = 0; k < active; k++) { diff --git a/software/tests/lp1_sanity/main.c b/software/tests/lp1_sanity/main.c index 7339ff8..f6c2028 100644 --- a/software/tests/lp1_sanity/main.c +++ b/software/tests/lp1_sanity/main.c @@ -14,6 +14,8 @@ // See the License for the specific language governing permissions and // limitations under the License. +// Author: Ho Tin Hung, ETH Zurich + // LP1 sanity — Tier 0 single-core smoke test for the private L1 (HPDcache) // bring-up. // From 08db94b4b87cdf5d7c56d9be6da05812664870da Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Fri, 26 Jun 2026 17:52:58 +0200 Subject: [PATCH 18/39] [HW] init AMO support impl --- hardware/src/cachepool_l1_ctrl.sv | 35 +++++++++++++++++++++++++++++++ hardware/src/spatz_cache_amo.sv | 24 +++++++++++++++------ 2 files changed, 53 insertions(+), 6 deletions(-) diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv index 5c872b6..aa891a4 100644 --- a/hardware/src/cachepool_l1_ctrl.sv +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -423,6 +423,11 @@ module cachepool_l1_ctrl l1_req[1].wdata = hpdcache_req_data_t'(cache_req_data[SnitchPort]) << (sn_byte_pos * ByteWidth); l1_req[1].be = hpdcache_req_be_t'(cache_req_strb[SnitchPort]) << sn_byte_pos; l1_req[1].tid = core_req_i[SnitchPort].q_valid ? l1_cache_req[SnitchPort].tid : '0; + // Phase 2: AMOs (incl. LR/SC) are serviced at the shared L2 by spatz_cache_amo, + // not inside this private L1. Mark them uncacheable so HPDcache routes them + // through its uncached/ATOP handler (forwards the atomic downstream) instead of + // doing a local self-update. Plain loads/stores stay cacheable WT. + l1_req[1].pma.uncacheable = (cache_req_amo[SnitchPort] != AMONone); end assign l1_req_valid[1] = core_req_i[SnitchPort].q_valid; @@ -576,6 +581,36 @@ module cachepool_l1_ctrl l2_req_o.q.strb = l1_mem_req_write_data.mem_req_w_be; l2_req_o.q.user = l1_l2_req_meta; l2_req_o.q_valid = l1_l2_req_valid; + + // Phase 2 AMO: phase 1 forced q.amo=AMONone (atomics were serviced inside + // HPDcache). Now route them to the shared-L2 spatz_cache_amo by translating + // HPDcache's AXI5-ATOP subtype back into the reqrsp amo_op_e the AMO unit reads. + // Atomics arrive with command==ATOMIC, so q.write stays 0 above: the AMO unit + // issues the operand-A read itself and generates its own write-back / SC write. + // The operand (rs2) rides on the write-data channel (mem_req_w_data) already + // aligned to the target byte offset. + if (l1_l2_req.mem_req_command == HPDCACHE_MEM_ATOMIC) begin + unique case (l1_l2_req.mem_req_atomic) + HPDCACHE_MEM_ATOMIC_ADD : l2_req_o.q.amo = AMOAdd; + HPDCACHE_MEM_ATOMIC_SET : l2_req_o.q.amo = AMOOr; + HPDCACHE_MEM_ATOMIC_EOR : l2_req_o.q.amo = AMOXor; + HPDCACHE_MEM_ATOMIC_SMAX: l2_req_o.q.amo = AMOMax; + HPDCACHE_MEM_ATOMIC_SMIN: l2_req_o.q.amo = AMOMin; + HPDCACHE_MEM_ATOMIC_UMAX: l2_req_o.q.amo = AMOMaxu; + HPDCACHE_MEM_ATOMIC_UMIN: l2_req_o.q.amo = AMOMinu; + HPDCACHE_MEM_ATOMIC_SWAP: l2_req_o.q.amo = AMOSwap; + HPDCACHE_MEM_ATOMIC_LDEX: l2_req_o.q.amo = AMOLR; + HPDCACHE_MEM_ATOMIC_STEX: l2_req_o.q.amo = AMOSC; + // HPDcache encodes RISC-V AMOAND as ATOP CLR with an inverted operand + // (clears the bits set in ~rs2, i.e. mem & ~(~rs2)). The spatz AMO ALU only + // has AMOAnd (A & B), so re-invert the operand here to recover rs2. + HPDCACHE_MEM_ATOMIC_CLR : begin + l2_req_o.q.amo = AMOAnd; + l2_req_o.q.data = ~l1_mem_req_write_data.mem_req_w_data; + end + default : l2_req_o.q.amo = AMONone; + endcase + end end ////////////// diff --git a/hardware/src/spatz_cache_amo.sv b/hardware/src/spatz_cache_amo.sv index ddcd512..d22afa1 100644 --- a/hardware/src/spatz_cache_amo.sv +++ b/hardware/src/spatz_cache_amo.sv @@ -56,7 +56,12 @@ module spatz_cache_amo input tcdm_rsp_t mem_rsp_i ); - logic idx_q, idx_d; + // logic idx_q, idx_d; + // Phase 2: the AMO unit now faces a cacheline-wide port (DataWidth=512) but the + // atomic is still a 32-bit word. NumWords/IdxW generalize the 1-bit lane select. + localparam int unsigned NumWords = DataWidth/32; + localparam int unsigned IdxW = (NumWords > 1) ? $clog2(NumWords) : 1; + logic [IdxW-1:0] idx_q, idx_d; logic [31:0] operand_a, operand_b_q, amo_result, amo_result_q; logic [AddrMemWidth-1:0] addr_q; amo_op_e amo_op_q; @@ -192,7 +197,8 @@ module spatz_cache_amo // ------- // Atomics // ------- - logic [63:0] wdata; + // logic [63:0] wdata; + logic [DataWidth-1:0] wdata; assign wdata = $unsigned(amo_req.data); logic amo_result_en; @@ -203,10 +209,14 @@ module spatz_cache_amo `FFL(addr_q, amo_req.addr, load_amo, '0) // Which word to pick. `FFL(idx_q, idx_d, load_amo, '0) - `FFL(operand_b_q, (amo_req.strb[0] ? wdata[31:0] : wdata[63:32]), load_amo, '0) + // `FFL(operand_b_q, (amo_req.strb[0] ? wdata[31:0] : wdata[63:32]), load_amo, '0) + `FFL(operand_b_q, wdata[32*idx_d +: 32], load_amo, '0) `FFL(amo_result_q, amo_result, amo_result_en, '0) - assign idx_d = ((DataWidth == 64) ? amo_req.strb[DataWidth/8/2] : 0); + // assign idx_d = ((DataWidth == 64) ? amo_req.strb[DataWidth/8/2] : 0); + // Lane (32-bit word) index within the cacheline, from the word-aligned address. + // Equivalent to the old strb-based half-select for DataWidth==64 (addr[2]<->strb[4]). + assign idx_d = (NumWords > 1) ? amo_req.addr[2 +: IdxW] : '0; assign load_amo = amo_req_valid & amo_req_ready & core_ready & ~(amo_insn inside {AMONone, AMOLR, AMOSC}); assign operand_a = amo_rsp.data[32*idx_q+:32]; @@ -250,8 +260,10 @@ module spatz_cache_amo core_ready = 1'b0; mem_req_o.q.write = 1'b1; mem_req_o.q.addr = addr_q; - mem_req_o.q.strb = 'b1111 << (idx_q*4); - mem_req_o.q.data = amo_result_q << (idx_q*32); + // mem_req_o.q.strb = 'b1111 << (idx_q*4); + // mem_req_o.q.data = amo_result_q << (idx_q*32); + mem_req_o.q.strb = StrbWidth'('hF) << (idx_q*4); + mem_req_o.q.data = DataWidth'(amo_result_q) << (idx_q*32); mem_req_o.q.user = amo_user_q; // Indicate that we are doing an AMO write-back // Used to filter out the response From 44e36f88495318abb6da6aef27b30a9b05cd0a7d Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Mon, 29 Jun 2026 16:25:06 +0200 Subject: [PATCH 19/39] [HW] shared D$ AMO support impl --- hardware/src/cachepool_tile.sv | 57 +++++++++++++++++++++++++++------ hardware/src/spatz_cache_amo.sv | 55 +++++++++++++++++++++++++------ 2 files changed, 94 insertions(+), 18 deletions(-) diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index d5d45bb..ef76fe8 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -551,6 +551,12 @@ module cachepool_tile // cache_amo_* are therefore unused in the collapsed path. // tcdm_req_t [NumL1CtrlTile-1:0] cache_amo_req; // tcdm_rsp_t [NumL1CtrlTile-1:0] cache_amo_rsp; + // Phase 2: spatz_cache_amo is re-instantiated per L2 controller (cb) on the single + // cacheline port, between the flush-gated xbar output (cache_ctrl_req) and the bank + // spill register. The private L1 forwards AMOs downstream (uncacheable); this unit + // does the real bank-side RMW. cache_amo_* carry the unit's mem side to the bank. + tcdm_cacheline_req_t [NumL1CtrlTile-1:0] cache_amo_req; + tcdm_cacheline_rsp_t [NumL1CtrlTile-1:0] cache_amo_rsp; // ---- Private L1 (LP1) -> shared L1/L2 downstream (cacheline-wide) ---- // One private L1 per core; its single mem-side downstream feeds the collapsed @@ -679,9 +685,10 @@ module cachepool_tile // transpose). cache_xbar_pready is the interco mem-side resp-ready: one per L2 // controller now. cache_amo_pready unused in the collapsed (AMO-in-L1) path. // logic [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_pready, cache_xbar_pready; - // logic [NumL1CtrlTile-1:0] cache_amo_pready; logic [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_pready; logic [NumL1CtrlTile-1:0] cache_xbar_pready; + // Phase 2: mem-side resp-ready of the per-cb spatz_cache_amo toward the bank spill. + logic [NumL1CtrlTile-1:0] cache_amo_pready; // ---------------------------------------------------------------------------- // [LP1] Old core<->interco bridge, replaced by the per-core private L1. @@ -1331,20 +1338,48 @@ module cachepool_tile */ // [LP1] Single cacheline port per L2 controller. A spill register cuts the - // interco -> bank critical path (matching the old timing budget). AMOs are - // serviced upstream in the private L1, so spatz_cache_amo is bypassed here. + // interco -> bank critical path (matching the old timing budget). + // Phase 2: spatz_cache_amo is re-instantiated here (one per cb) on the cacheline + // port. It serializes every access to this controller (the system-wide atomicity + // point) and performs the RMW for AMOs the private L1 forwarded uncacheable. Its + // mem side (cache_amo_*) drives the bank spill register below; plain loads/stores + // pass through it unchanged. tcdm_cacheline_req_t cache_req_reg; tcdm_cacheline_rsp_t cache_rsp_reg; + spatz_cache_amo #( + .AddrMemWidth ( L1AddrWidth ), + .DataWidth ( L1LineWidth ), + .CoreIDWidth ( CoreIDWidth ), + .tcdm_req_t ( tcdm_cacheline_req_t ), + .tcdm_rsp_t ( tcdm_cacheline_rsp_t ), + .tcdm_req_chan_t ( tcdm_cacheline_req_chan_t ), + .tcdm_rsp_chan_t ( tcdm_cacheline_rsp_chan_t ), + .tcdm_user_t ( tcdm_user_t ) + ) i_cache_amo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .core_req_i ( cache_ctrl_req[cb] ), + .core_rsp_ready_i ( cache_xbar_pready[cb]), + .core_rsp_o ( cache_bank_rsp[cb] ), + .mem_req_o ( cache_amo_req[cb] ), + .mem_rsp_ready_o ( cache_amo_pready[cb]), + .mem_rsp_i ( cache_amo_rsp[cb] ) + ); + spill_register #( .T ( tcdm_cacheline_req_chan_t ), .Bypass ( 1'b0 ) ) i_spill_reg_cache_req ( .clk_i , .rst_ni ( rst_ni ), - .valid_i ( cache_ctrl_req[cb].q_valid ), - .ready_o ( cache_bank_rsp[cb].q_ready ), - .data_i ( cache_ctrl_req[cb].q ), + // Phase 2: fed from the AMO unit's mem side instead of the xbar directly. + // .valid_i ( cache_ctrl_req[cb].q_valid ), + // .ready_o ( cache_bank_rsp[cb].q_ready ), + // .data_i ( cache_ctrl_req[cb].q ), + .valid_i ( cache_amo_req[cb].q_valid ), + .ready_o ( cache_amo_rsp[cb].q_ready ), + .data_i ( cache_amo_req[cb].q ), .valid_o ( cache_req_reg.q_valid ), .ready_i ( cache_rsp_reg.q_ready ), .data_o ( cache_req_reg.q ) @@ -1359,9 +1394,13 @@ module cachepool_tile .valid_i ( cache_rsp_reg.p_valid ), .ready_o ( cache_rsp_ready [cb] ), .data_i ( cache_rsp_reg.p ), - .valid_o ( cache_bank_rsp [cb].p_valid), - .ready_i ( cache_xbar_pready[cb] ), - .data_o ( cache_bank_rsp [cb].p ) + // Phase 2: bank response returns to the AMO unit's mem side, not the xbar. + // .valid_o ( cache_bank_rsp [cb].p_valid), + // .ready_i ( cache_xbar_pready[cb] ), + // .data_o ( cache_bank_rsp [cb].p ) + .valid_o ( cache_amo_rsp [cb].p_valid), + .ready_i ( cache_amo_pready[cb] ), + .data_o ( cache_amo_rsp [cb].p ) ); assign cache_req_valid[cb] = cache_req_reg.q_valid; diff --git a/hardware/src/spatz_cache_amo.sv b/hardware/src/spatz_cache_amo.sv index d22afa1..5dca308 100644 --- a/hardware/src/spatz_cache_amo.sv +++ b/hardware/src/spatz_cache_amo.sv @@ -227,9 +227,29 @@ module spatz_cache_amo mem_req_o.q = amo_req; mem_req_o.q_valid = amo_req_valid; core_ready = amo_req_ready; - mem_req_o.q.write = amo_req.write | (sc_successful & (amo_insn == AMOSC)); + // Phase 2 (WI-4a): an SC must always present its outcome on the *write* channel, + // because HPDcache's uncached handler waits on mem_resp_write for an SC and decodes + // success from mem_resp_w_is_atomic. A *successful* SC performs the real store; a + // *failed* SC still issues a write but with zero byte-enables (a no-op store) so the + // bank still returns a write ack. Hence write=1 for every SC, success or fail. + // NOTE: the zero-strb no-op store relies on the bandwidth-matched bank path + // (BurstLength==1, i.e. refill_data_width==l1d_cacheline_width) forwarding the write + // downstream and returning its B response. Under BurstLength>1 the cache_ctrl + // suppresses zero-strb writes (no response) -> a failed SC would hang; that config + // would instead need the response synthesized here. + // mem_req_o.q.write = amo_req.write | (sc_successful & (amo_insn == AMOSC)); + mem_req_o.q.write = amo_req.write | (amo_insn == AMOSC); mem_req_o.q.amo = AMONone; mem_req_o.q.data = amo_req.data; + // Failed SC: keep it a write transaction but disable all byte-enables (no store). + mem_req_o.q.strb = (amo_insn == AMOSC && !sc_successful) ? '0 : amo_req.strb; + // The bank echoes user.is_amo on its response. In phase 2 that bit must mean + // "atomic write-ack" so the L1 ctrl routes the response on the write channel and + // maps it to mem_resp_w_is_atomic -- not merely "the request was atomic". Strip it + // on the forwarded request so the old-value READ response (arith AMO / LR) is never + // mistaken for a write-ack. WriteBackAMO re-asserts it for the RMW write-back below; + // an SC carries its success/failure in is_amo (-> mem_resp_w_is_atomic). + mem_req_o.q.user.is_amo = (amo_insn == AMOSC) ? sc_successful : 1'b0; amo_result_en = 1'b0; @@ -306,24 +326,41 @@ module spatz_cache_amo core_rsp_o.q_ready = core_ready; mem_rsp_ready_o = amo_rsp_ready; - if (amo_rsp_valid && mem_rsp_i.p.user.is_amo) begin - // Means we receive a response message generated by AMO, should not forward to core - core_rsp_o.p = '0; - core_rsp_o.p_valid = 1'b0; - mem_rsp_ready_o = 1'b1; - end + // Phase 2 (WI-4a): the AMO write-back response (user.is_amo=1) used to be a purely + // internal artifact and was dropped here so the core observed a single response. + // The unit now sits below HPDcache's uncached/AMO handler, which expects BOTH an + // old-value read response AND a write ack for an arithmetic AMO (and a write-channel + // response for SC). So the is_amo write-back must flow upward as that write ack + // instead of being filtered; forwarding is unconditional. The old-value read + // response no longer carries is_amo (stripped on the request above), so the two are + // unambiguous downstream (read channel vs write channel, by p.write). + // if (amo_rsp_valid && mem_rsp_i.p.user.is_amo) begin + // // Means we receive a response message generated by AMO, should not forward to core + // core_rsp_o.p = '0; + // core_rsp_o.p_valid = 1'b0; + // mem_rsp_ready_o = 1'b1; + // end end // ---------- // Assertions // ---------- // Check that data width is legal (a power of two and at least 32 bit). + // Phase 2: the unit now faces a cacheline-wide port (DataWidth up to the L1 line + // width, e.g. 512), with the 32-bit amo.w targeting one word selected by addr[5:2]. + // `ASSERT_INIT(DataWidthCheck, + // DataWidth >= 32 && DataWidth <= 64 && 2**$clog2(DataWidth) == DataWidth) `ASSERT_INIT(DataWidthCheck, - DataWidth >= 32 && DataWidth <= 64 && 2**$clog2(DataWidth) == DataWidth) + DataWidth >= 32 && DataWidth <= 512 && 2**$clog2(DataWidth) == DataWidth) // Make sure that write is never set for AMOs. `ASSERT(AMOWriteEnable, amo_req_valid && !amo_insn inside {AMONone} |-> !amo_req.write) // Byte enable mask is correct - `ASSERT(ByteMaskCorrect, amo_req_valid && !amo_insn inside {AMONone} |-> amo_req.strb[4*idx_d+:4] == '1) + // Phase 2: LR arrives on the read channel and carries no byte-enables, so exclude it + // from the byte-mask cross-check (only RMW AMOs and SC carry an aligned strb group). + // Use explicit parens around `inside`: unlike the single-element {AMONone} idiom, the + // negation of a multi-element set does not survive `!`'s tighter precedence. + // `ASSERT(ByteMaskCorrect, amo_req_valid && !amo_insn inside {AMONone} |-> amo_req.strb[4*idx_d+:4] == '1) + `ASSERT(ByteMaskCorrect, amo_req_valid && !(amo_insn inside {AMONone, AMOLR}) |-> amo_req.strb[4*idx_d+:4] == '1) endmodule From 77683f1d4fffedb9dd4de4bce67884f2d84b4a09 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Mon, 29 Jun 2026 18:01:57 +0200 Subject: [PATCH 20/39] [SW] amo sanity test --- sim/scripts/vsim_tile.tcl | 30 +++++- software/tests/CMakeLists.txt | 2 + software/tests/arith_amo/main.c | 185 ++++++++++++++++++++++++++++++++ 3 files changed, 215 insertions(+), 2 deletions(-) create mode 100644 software/tests/arith_amo/main.c diff --git a/sim/scripts/vsim_tile.tcl b/sim/scripts/vsim_tile.tcl index 5a9565e..8f128fa 100644 --- a/sim/scripts/vsim_tile.tcl +++ b/sim/scripts/vsim_tile.tcl @@ -22,15 +22,41 @@ add wave -noupdate -group ${parent_grp} -group tile[$1] -group wide_xbar ${tile_ add wave -noupdate -group ${parent_grp} -group tile[$1] -group Barrier ${tile_path}/i_tile/i_cachepool_tile_barrier/* +# Add waves for private L1 (LP1 = per-core HPDcache, in cachepool_l1_ctrl). +# One instance per core; NumLP1CacheCtrl == NumL1CtrlTile (= num_cores_per_tile), +# so this reuses the same loop bound as the shared cache below. onerror/resume +# tolerates over-iteration for configs with fewer cores per tile. +for {set c 0} {$c < 4} {incr c} { + onerror {resume} + + quietly set lp1_path ${tile_path}/i_tile/gen_lp1_cache[$c]/i_lp1_cache + add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group hpdcache ${lp1_path}/i_l1_hpdcache/core_req_i + add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group hpdcache ${lp1_path}/i_l1_hpdcache/core_req_ready_o + add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group hpdcache ${lp1_path}/i_l1_hpdcache/core_rsp_valid_o + add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group hpdcache ${lp1_path}/i_l1_hpdcache/core_rsp_o + add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group hpdcache ${lp1_path}/i_l1_hpdcache/* + + + add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group ctrl ${lp1_path}/i_l1_hpdcache/hpdcache_ctrl_i/* + add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group wbuf ${lp1_path}/i_l1_hpdcache/gen_wbuf/hpdcache_wbuf_i/* + add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group coalescer ${lp1_path}/i_l1_req_coalescer/* + add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group Internal ${lp1_path}/* +} + # Add waves for cache controller for {set c 0} {$c < 4} {incr c} { onerror {resume} quietly set cache_path ${tile_path}/i_tile/gen_l1_cache_ctrl[$c]/i_l1_controller - add wave -noupdate -group ${parent_grp} -group tile[$1] -group cache[$c] -group amo ${tile_path}/i_tile/gen_cache_connect[$c]/gen_cache_amo_connect[${SNITCH_IDX}]/gen_amo/i_cache_amo/* + # [Phase 2 / WI-3] The L2-side spatz_cache_amo is now one instance per L2 + # controller on the single cacheline port (gen_cache_connect[$c]/i_cache_amo), + # replacing the old per-plane gen_cache_amo_connect[SNITCH_IDX]/gen_amo nesting. + add wave -noupdate -group ${parent_grp} -group tile[$1] -group cache[$c] -group amo ${tile_path}/i_tile/gen_cache_connect[$c]/i_cache_amo/* - add wave -noupdate -group ${parent_grp} -group tile[$1] -group cache[$c] -group coalescer ${cache_path}/i_par_coalescer_for_spatz/gen_extend_window/i_par_coalescer_extend_window/i_par_coalescer/* + # [LP1] The per-L2 Spatz coalescer (i_par_coalescer_for_spatz) was removed in the + # insitu fork (the private L1 coalesces upstream now), so this path no longer exists. + # add wave -noupdate -group ${parent_grp} -group tile[$1] -group cache[$c] -group coalescer ${cache_path}/i_par_coalescer_for_spatz/gen_extend_window/i_par_coalescer_extend_window/i_par_coalescer/* add wave -noupdate -group ${parent_grp} -group tile[$1] -group cache[$c] -group core ${cache_path}/i_insitu_cache_tcdm_wrapper/i_insitu_cache_core/* add wave -noupdate -group ${parent_grp} -group tile[$1] -group cache[$c] -group meta_ctrl0 ${cache_path}/i_insitu_cache_tcdm_wrapper/gen_cache_banks[0]/i_access_ctrl_for_meta/* add wave -noupdate -group ${parent_grp} -group tile[$1] -group cache[$c] -group meta_ctrl1 ${cache_path}/i_insitu_cache_tcdm_wrapper/gen_cache_banks[1]/i_access_ctrl_for_meta/* diff --git a/software/tests/CMakeLists.txt b/software/tests/CMakeLists.txt index ada3441..3f4621f 100644 --- a/software/tests/CMakeLists.txt +++ b/software/tests/CMakeLists.txt @@ -131,6 +131,8 @@ add_spatz_test_zeroParam(lp1_sanity lp1_sanity/main.c) add_spatz_test_zeroParam(lp1_private lp1_private/main.c) add_spatz_test_zeroParam(lp1_eviction lp1_eviction/main.c) +add_spatz_test_zeroParam(arith_amo arith_amo/main.c) + add_spatz_test_zeroParam(load-store load-store/main.c) add_spatz_test_zeroParam(bandwidth bandwidth/main.c) diff --git a/software/tests/arith_amo/main.c b/software/tests/arith_amo/main.c new file mode 100644 index 0000000..33ff789 --- /dev/null +++ b/software/tests/arith_amo/main.c @@ -0,0 +1,185 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Ho Tin Hung, ETH Zurich + +// Arithmetic AMO sanity — single-core functional test for the phase-2 AMO path +// (Snitch AMO -> private L1 forwards uncacheable -> shared-L2 spatz_cache_amo RMW). +// +// Scope: ONE core (core 0) exercising every RV32 `amo*.w` arithmetic op plus the +// in-cacheline word selection. Cross-core atomicity and LR/SC are separate tests. +// +// CRITICAL verification rule (WI-5 / self-staleness is intentionally deferred): +// We must NOT check results with a plain (cacheable) load. After an uncacheable +// AMO, this core's L1 line for the address is NOT refreshed, so a cacheable load +// could read a stale pre-AMO value and make a correct DUT look broken (or hide a +// bug). Everything here is verified through L2-authoritative paths only: +// - the AMO's own returned OLD value, and +// - a no-op `amoor(addr, 0)` used as an atomic "read current value". +// Initial values are likewise established with `amoswap` (not a normal store), +// which also sidesteps any write-buffer-vs-uncached-AMO ordering hazard. +// +// Only core 0 does work; all other cores park on the hardware barrier (MMIO, +// coherence-independent), exactly as in lp1_sanity. + +#include +#include +#include +#include + +// ----------------------------------------------------------------------------- +// AMO primitives (explicit inline asm so the exact amo*.w instruction is tested) +// amo.w rd, rs2, (rs1): rd <- mem[rs1] (old); mem[rs1] <- old rs2 +// ----------------------------------------------------------------------------- +#define DEF_AMO(suffix, mnem) \ + static inline uint32_t amo_##suffix(volatile uint32_t *addr, uint32_t val) { \ + uint32_t old; \ + asm volatile(mnem " %0, %2, (%1)" \ + : "=r"(old) \ + : "r"(addr), "r"(val) \ + : "memory"); \ + return old; \ + } + +DEF_AMO(add, "amoadd.w") +DEF_AMO(and, "amoand.w") // exercises the ATOP-CLR operand re-invert in L1-ctrl +DEF_AMO(or, "amoor.w") +DEF_AMO(xor, "amoxor.w") +DEF_AMO(swap, "amoswap.w") +DEF_AMO(max, "amomax.w") // signed +DEF_AMO(min, "amomin.w") // signed +DEF_AMO(maxu, "amomaxu.w") // unsigned +DEF_AMO(minu, "amominu.w") // unsigned + +// Atomic "read current value" without modifying it (old | 0 == old). +static inline uint32_t amo_read(volatile uint32_t *addr) { + return amo_or(addr, 0u); +} + +// ----------------------------------------------------------------------------- +// Test buffers (cacheable .data; the AMO op itself is marked uncacheable in HW). +// buf2 is cacheline-aligned (64B = 16 words) so word index == addr[5:2]. +// ----------------------------------------------------------------------------- +static volatile uint32_t buf_a __attribute__((section(".data"))); + +#define WS_WORDS 32 // two 64-byte cachelines worth of 32-bit words +static volatile uint32_t buf2[WS_WORDS] + __attribute__((section(".data"), aligned(64))); + +// ----------------------------------------------------------------------------- +// Check helper +// ----------------------------------------------------------------------------- +static uint32_t errors; + +#define CHECK(label, got, exp) \ + do { \ + uint32_t _g = (got), _e = (exp); \ + if (_g != _e) { \ + printf(" FAIL %-14s exp 0x%08x got 0x%08x\n", (label), _e, _g); \ + errors++; \ + } \ + } while (0) + +int main() { + const uint32_t num_cores = snrt_cluster_core_num(); + const uint32_t cid = snrt_cluster_core_idx(); + + // Rendezvous: confirm every core booted and the HW barrier works. + snrt_cluster_hw_barrier(); + + if (cid == 0) { + printf("\n*** arith_amo (single-core arithmetic AMO sanity) ***\n"); + printf("Cores:%u (only core 0 active)\n", num_cores); + + start_kernel(); + + errors = 0; + + volatile uint32_t *a = &buf_a; + uint32_t r; + + // --- Part 1: logical/arith chain on a single word ----------------------- + // Each step asserts the returned OLD value; the running memory value is + // re-checked by the following step (and by amo_read at the end). + amo_swap(a, 0); // init a=0 (ignore return) + r = amo_add (a, 5); CHECK("add#1", r, 0x00000000); // a=5 + r = amo_add (a, 3); CHECK("add#2", r, 0x00000005); // a=8 + r = amo_swap(a, 0xFFFFFFFF); CHECK("swap", r, 0x00000008); // a=0xFFFFFFFF + r = amo_and (a, 0x0F0F0F0F); CHECK("and", r, 0xFFFFFFFF); // a=0x0F0F0F0F + r = amo_or (a, 0x00F000F0); CHECK("or", r, 0x0F0F0F0F); // a=0x0FFF0FFF + r = amo_xor (a, 0xFFFFFFFF); CHECK("xor", r, 0x0FFF0FFF); // a=0xF000F000 + r = amo_read(a); CHECK("read#1", r, 0xF000F000); // unchanged + + // --- Part 2: signed max/min -------------------------------------------- + amo_swap(a, 10); + r = amo_max (a, 5); CHECK("smax#1", r, 10); // a=max(10,5)=10 + r = amo_max (a, 20); CHECK("smax#2", r, 10); // a=20 + r = amo_min (a, 7); CHECK("smin#1", r, 20); // a=7 + r = amo_min (a, 100); CHECK("smin#2", r, 7); // a=7 + r = amo_read(a); CHECK("read#2", r, 7); + // signed semantics: 0xFFFFFFFF == -1 < 1 + amo_swap(a, 0xFFFFFFFF); + r = amo_max (a, 1); CHECK("smax-neg", r, 0xFFFFFFFF);// a=max(-1,1)=1 + r = amo_read(a); CHECK("read#3", r, 1); + amo_swap(a, 0xFFFFFFFF); + r = amo_min (a, 1); CHECK("smin-neg", r, 0xFFFFFFFF);// a=min(-1,1)=-1 + r = amo_read(a); CHECK("read#4", r, 0xFFFFFFFF); + + // --- Part 3: unsigned max/min ------------------------------------------ + // unsigned: 0xFFFFFFFF is the largest, not -1. + amo_swap(a, 0xFFFFFFFF); + r = amo_maxu(a, 1); CHECK("umax", r, 0xFFFFFFFF); // a=0xFFFFFFFF + r = amo_minu(a, 1); CHECK("umin#1", r, 0xFFFFFFFF); // a=min_u(...,1)=1 + r = amo_minu(a, 100); CHECK("umin#2", r, 1); // a=1 + r = amo_maxu(a, 0); CHECK("umax0", r, 1); // a=1 + r = amo_read(a); CHECK("read#5", r, 1); + + // --- Part 4: in-cacheline word selection ------------------------------- + // Independently RMW all 32 words across two lines; verify per-word old + // values AND that no AMO clobbers a neighbouring word (write-back strb). + for (uint32_t i = 0; i < WS_WORDS; i++) + amo_swap(&buf2[i], 0x1000u + i); // unique init per word + for (uint32_t i = 0; i < WS_WORDS; i++) { + uint32_t old = amo_add(&buf2[i], i); // a[i] -> 0x1000+i+i + if (old != (0x1000u + i)) { + printf(" FAIL ws-old word %2u exp 0x%08x got 0x%08x\n", + i, 0x1000u + i, old); + errors++; + } + } + for (uint32_t i = 0; i < WS_WORDS; i++) { + uint32_t cur = amo_read(&buf2[i]); // expect 0x1000 + 2*i + if (cur != (0x1000u + 2u * i)) { + printf(" FAIL ws-final word %2u exp 0x%08x got 0x%08x\n", + i, 0x1000u + 2u * i, cur); + errors++; + } + } + + stop_kernel(); + + if (errors == 0) + printf("arith_amo: PASS\n"); + else + printf("arith_amo: FAIL (%u errors)\n", errors); + printf("*** arith_amo complete ***\n"); + } + + // Final rendezvous so no core races to EOC before core 0 finishes. + snrt_cluster_hw_barrier(); + + return 0; +} From cbe237a7858abd031eeb25de27dc2db52a440321 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Tue, 30 Jun 2026 11:24:24 +0200 Subject: [PATCH 21/39] [HW] hpdcache memIdWidth match with reqid_t --- hardware/src/cachepool_tile.sv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index ef76fe8..516a0e3 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -338,10 +338,10 @@ module cachepool_tile dataSetsPerRam: 32, dataRamByteEnable: 1'b1, accessWords: 4, - mshrSets: 8, + mshrSets: 4, mshrWays: 4, mshrWaysPerRamWord: 4, - mshrSetsPerRam: 8, + mshrSetsPerRam: 4, mshrRamByteEnable: 1'b1, mshrUseRegbank: 1'b1, cbufEntries: 2, @@ -355,7 +355,8 @@ module cachepool_tile flushEntries: 2, flushFifoDepth: 2, memAddrWidth: L1AddrWidth, - memIdWidth: LP1TidWidth, + // memIdWidth: LP1TidWidth, + memIdWidth: $clog2(NumSpatzOutstandingLoads), memDataWidth: L1LineWidth, wtEn: 1'b1, // write-through wbEn: 1'b0, From 876a5814c774d3ce5b2c903f9557419cd9b9644f Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Tue, 30 Jun 2026 15:23:48 +0200 Subject: [PATCH 22/39] [SW] LRSC amo test --- software/tests/CMakeLists.txt | 1 + software/tests/lrsc_amo/main.c | 161 +++++++++++++++++++++++++++++++++ 2 files changed, 162 insertions(+) create mode 100644 software/tests/lrsc_amo/main.c diff --git a/software/tests/CMakeLists.txt b/software/tests/CMakeLists.txt index 3f4621f..94ffc8f 100644 --- a/software/tests/CMakeLists.txt +++ b/software/tests/CMakeLists.txt @@ -132,6 +132,7 @@ add_spatz_test_zeroParam(lp1_private lp1_private/main.c) add_spatz_test_zeroParam(lp1_eviction lp1_eviction/main.c) add_spatz_test_zeroParam(arith_amo arith_amo/main.c) +add_spatz_test_zeroParam(lrsc_amo lrsc_amo/main.c) add_spatz_test_zeroParam(load-store load-store/main.c) diff --git a/software/tests/lrsc_amo/main.c b/software/tests/lrsc_amo/main.c new file mode 100644 index 0000000..60cf409 --- /dev/null +++ b/software/tests/lrsc_amo/main.c @@ -0,0 +1,161 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Ho Tin Hung, ETH Zurich + +// LR/SC sanity — single-core functional test for the phase-2 atomic path +// (Snitch LR/SC -> private L1 forwards uncacheable -> shared-L2 spatz_cache_amo +// reservation + conditional store). +// +// Reservation model in THIS design (spatz_cache_amo.sv): +// - LR places a reservation {core, addr} (:171-175) +// - SC succeeds iff a valid same-core reservation matches addr, +// returns 0; it then CLEARS the reservation (:190-192) +// - SC return code: 0 = success, 1 = fail (:155) +// - Only a store from ANOTHER core breaks a reservation (:183-187); +// same-core ops never break it. So we cannot fail an SC with an +// intervening same-core store -- failures are triggered STRUCTURALLY: +// * SC with no preceding LR -> fail (no valid reservation) +// * second SC after a first SC -> fail (first SC cleared it) +// +// CRITICAL verification rule (same as arith_amo / WI-5 deferred): +// Never read back with a plain (cacheable) load -- after an uncacheable +// atomic this core's L1 line is not refreshed. Memory state is checked only +// through L2-authoritative paths: the SC return code, the LR return value, +// and a no-op `amo_or(addr,0)` used as an atomic "read current value". +// Initial values are established with `amo_swap` (AMOSwap, not AMOLR, so it +// does not itself set a reservation). +// +// To keep the LR/SC pair tight, all return values of a scenario are captured +// BEFORE any CHECK/printf, so no spill or UART traffic lands between LR and SC. +// +// Only core 0 does work; all other cores park on the hardware barrier. + +#include +#include +#include +#include + +// ----------------------------------------------------------------------------- +// Atomic primitives (explicit inline asm so the exact instruction is tested) +// ----------------------------------------------------------------------------- +static inline uint32_t load_reserved(volatile uint32_t *addr) { + uint32_t val; + asm volatile("lr.w %0, (%1)" : "=r"(val) : "r"(addr) : "memory"); + return val; +} + +// sc.w rd, rs2, (rs1): rd <- 0 on success / 1 on failure; mem[rs1] <- rs2 on success +static inline uint32_t store_conditional(volatile uint32_t *addr, uint32_t val) { + uint32_t status; + asm volatile("sc.w %0, %2, (%1)" : "=r"(status) : "r"(addr), "r"(val) : "memory"); + return status; +} + +static inline uint32_t amo_swap(volatile uint32_t *addr, uint32_t val) { + uint32_t old; + asm volatile("amoswap.w %0, %2, (%1)" : "=r"(old) : "r"(addr), "r"(val) : "memory"); + return old; +} + +// Atomic "read current value" without modifying it (old | 0 == old). +static inline uint32_t amo_read(volatile uint32_t *addr) { + uint32_t old; + asm volatile("amoor.w %0, %2, (%1)" : "=r"(old) : "r"(addr), "r"(0u) : "memory"); + return old; +} + +// ----------------------------------------------------------------------------- +// Test buffer (cacheable .data; the atomics themselves are uncacheable in HW). +// ----------------------------------------------------------------------------- +static volatile uint32_t buf_a __attribute__((section(".data"))); + +static uint32_t errors; + +#define CHECK(label, got, exp) \ + do { \ + uint32_t _g = (got), _e = (exp); \ + if (_g != _e) { \ + printf(" FAIL %-14s exp 0x%08x got 0x%08x\n", (label), _e, _g); \ + errors++; \ + } \ + } while (0) + +int main() { + const uint32_t num_cores = snrt_cluster_core_num(); + const uint32_t cid = snrt_cluster_core_idx(); + + // Rendezvous: confirm every core booted and the HW barrier works. + snrt_cluster_hw_barrier(); + + if (cid == 0) { + printf("\n*** lrsc_amo (single-core LR/SC sanity) ***\n"); + printf("Cores:%u (only core 0 active)\n", num_cores); + + start_kernel(); + + errors = 0; + volatile uint32_t *a = &buf_a; + + // --- Scenario 1: LR; SC(same addr) -> success, value written ----------- + { + amo_swap(a, 0xAAAA0000u); // init (no reservation set) + uint32_t lrval = load_reserved(a); // reserve {core0, a} + uint32_t sc = store_conditional(a, 0xBBBB1111u); // matches -> success + uint32_t mem = amo_read(a); + CHECK("s1.lr", lrval, 0xAAAA0000u); // LR returns current value + CHECK("s1.sc", sc, 0u); // 0 = success + CHECK("s1.mem", mem, 0xBBBB1111u); // store took effect + } + + // --- Scenario 2: SC with no preceding LR -> fail, memory unchanged ----- + // (Scenario 1's successful SC already cleared the reservation, so there is + // no valid reservation entering here.) + { + amo_swap(a, 0xCCCC2222u); // init + uint32_t sc = store_conditional(a, 0xDDDD3333u); // no LR -> fail + uint32_t mem = amo_read(a); + CHECK("s2.sc", sc, 1u); // 1 = fail + CHECK("s2.mem", mem, 0xCCCC2222u); // unchanged + } + + // --- Scenario 3: LR; SC; SC -> first succeeds, second fails ------------ + { + amo_swap(a, 0x11110000u); // init + uint32_t lrval = load_reserved(a); // reserve + uint32_t sc1 = store_conditional(a, 0x22221111u); // success, clears resv + uint32_t sc2 = store_conditional(a, 0x33332222u); // no resv -> fail + uint32_t mem = amo_read(a); + CHECK("s3.lr", lrval, 0x11110000u); + CHECK("s3.sc1", sc1, 0u); // first SC success + CHECK("s3.sc2", sc2, 1u); // second SC fail + CHECK("s3.mem", mem, 0x22221111u); // only the first store landed + } + + stop_kernel(); + + if (errors == 0) + printf("lrsc_amo: PASS\n"); + else + printf("lrsc_amo: FAIL (%u errors)\n", errors); + printf("*** lrsc_amo complete ***\n"); + } + + // Final rendezvous so no core races to EOC before core 0 finishes. + snrt_cluster_hw_barrier(); + + return 0; +} From 896e748a9a0e83e77345f7303e3ed392bb1b222f Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Wed, 1 Jul 2026 17:16:47 +0200 Subject: [PATCH 23/39] [HW] peripheral reg, port extension, and FSM for private L1 CMO --- .../cachepool_peripheral.sv | 59 +- .../cachepool_peripheral_reg.hjson | 93 + .../cachepool_peripheral_reg_pkg.sv | 1037 +- .../cachepool_peripheral_reg_top.sv | 9388 ++++++++++++++++- hardware/src/cachepool_cluster.sv | 16 +- hardware/src/cachepool_group.sv | 14 +- hardware/src/cachepool_group_noc_wrapper.sv | 9 +- hardware/src/cachepool_l1_ctrl.sv | 94 + hardware/src/cachepool_pkg.sv | 9 + hardware/src/cachepool_tile.sv | 13 +- .../snRuntime/include/cachepool_peripheral.h | 1303 +++ 11 files changed, 11856 insertions(+), 179 deletions(-) diff --git a/hardware/cachepool_peripheral/cachepool_peripheral.sv b/hardware/cachepool_peripheral/cachepool_peripheral.sv index 8077342..2b420cd 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral.sv +++ b/hardware/cachepool_peripheral/cachepool_peripheral.sv @@ -15,9 +15,12 @@ module cachepool_peripheral parameter int unsigned SPMWidth = 0, // Number of tiles (used for flush controller granularity) parameter int unsigned NumTiles = 1, + // Number of cores (one per-core LP1 CMO slot). Must be <= NumLp1CmoRegs. + parameter int unsigned NumCores = 1, parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, parameter type cache_insn_t = logic, + parameter type lp1_cmo_req_t = logic, /// Derived parameter *Do not override* parameter type addr_t = logic [AddrWidth-1:0], parameter type spm_size_t = logic [SPMWidth-1:0] @@ -42,7 +45,11 @@ module cachepool_peripheral output cache_insn_t l1d_insn_o, output logic l1d_insn_valid_o, input logic [NumTiles-1:0] l1d_insn_ready_i, - output logic [NumTiles-1:0] l1d_busy_o + output logic [NumTiles-1:0] l1d_busy_o, + // Per-core private-L1 (LP1) CMO injector interface (one slot per core). + output lp1_cmo_req_t [NumCores-1:0] lp1_cmo_req_o, + output logic [NumCores-1:0] lp1_cmo_valid_o, + input logic [NumCores-1:0] lp1_cmo_done_i ); cachepool_peripheral_reg2hw_t reg2hw; @@ -183,6 +190,56 @@ module cachepool_peripheral assign hw2reg.l1d_flush_status.d = (l1d_lock_q != '0); // assign l1d_busy_o = (l1d_lock_q != '0); + //////////// Private-L1 (LP1) per-core CMO //////////// + // Per-core handshake mirroring the L1D flush path above, but vectorized so + // that independent cores running unrelated critical sections issue CMOs + // without contending on a shared trigger register. Per core slot [c]: + // commit[c] & !lock[c] -> pulse valid[c], present op/addr, set lock[c], + // and self-clear the commit bit + // done[c] -> clear lock[c] + // status[c] = lock[c] (busy while a CMO is in flight) + logic [NumLp1CmoRegs-1:0] lp1_cmo_lock_d, lp1_cmo_lock_q; + + always_comb begin : lp1_cmo_cfg + lp1_cmo_lock_d = lp1_cmo_lock_q; + + // Default every register-file back-channel low (covers unused upper slots + // when NumCores < NumLp1CmoRegs). + for (int unsigned i = 0; i < NumLp1CmoRegs; i++) begin + hw2reg.lp1_cmo_commit[i].d = 1'b0; + hw2reg.lp1_cmo_commit[i].de = 1'b0; + hw2reg.lp1_cmo_status[i].d = 1'b0; + end + + // Default the per-core outputs. + lp1_cmo_req_o = '0; + lp1_cmo_valid_o = '0; + + for (int unsigned c = 0; c < NumCores; c++) begin + // Present the requested op/addr for this core's injector. + lp1_cmo_req_o[c].op = reg2hw.cfg_lp1_cmo[c].q; + lp1_cmo_req_o[c].addr = reg2hw.cfg_lp1_cmo_addr[c].q; + + // Issue when committed and not already in flight. + if (reg2hw.lp1_cmo_commit[c].q && !lp1_cmo_lock_q[c]) begin + lp1_cmo_valid_o[c] = 1'b1; + lp1_cmo_lock_d[c] = 1'b1; + hw2reg.lp1_cmo_commit[c].d = 1'b0; // self-clear the commit + hw2reg.lp1_cmo_commit[c].de = 1'b1; + end + + // Clear the lock when the injector signals completion. + if (lp1_cmo_done_i[c]) begin + lp1_cmo_lock_d[c] = 1'b0; + end + + // Busy/done status polled by the runtime. + hw2reg.lp1_cmo_status[c].d = lp1_cmo_lock_q[c]; + end + end + + `FF(lp1_cmo_lock_q, lp1_cmo_lock_d, '0, clk_i, rst_ni) + // Enable icache prefetch assign icache_prefetch_enable_o = reg2hw.icache_prefetch_enable.q; diff --git a/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson b/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson index 870963a..6f8e872 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson +++ b/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson @@ -9,6 +9,14 @@ type: "int", default: "2" }, + { name: "NumLp1CmoRegs", + desc: '''Number of per-core LP1 (private-L1) CMO register slots -- one per core / + per private L1. Core `cid` uses slot `cid`. Default 64 covers every + currently-built config (2g/4g full = 32 cores; 2g/4g/16g tiny up to + 64 cores). Bump to 256 for full 16g (256 cores).''', + type: "int", + default: "64" + }, ], name: "cachepool_peripheral", clock_primary: "clk_i", @@ -226,6 +234,91 @@ name: "COMMIT", desc: "Commit the xbar offset configurations." }] + }, + // --------------------------------------------------------------------------- + // Per-core private-L1 (LP1) CMO trigger block. + // Vectorized per core (multireg, one slot per core) so that independent cores + // running unrelated critical sections can issue CMOs concurrently without + // racing on a shared trigger register. Mirrors the CFG_L1D_INSN / + // L1D_INSN_COMMIT / L1D_FLUSH_STATUS handshake, one instance per core. + // Software: core `cid` writes CFG_LP1_CMO[cid] (+ CFG_LP1_CMO_ADDR[cid] for + // INVAL_NLINE), pulses LP1_CMO_COMMIT[cid], then polls LP1_CMO_STATUS[cid]. + // --------------------------------------------------------------------------- + { + multireg: { + name: "CFG_LP1_CMO", + desc: '''Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), + 1 = INVAL_ALL, 2 = INVAL_NLINE. Paired with CFG_LP1_CMO_ADDR + (INVAL_NLINE only) and triggered by LP1_CMO_COMMIT.''' + swaccess: "rw", + hwaccess: "hro", + count: "NumLp1CmoRegs", + cname: "cfg_lp1_cmo", + compact: "false", + resval: "0", + fields: [{ + bits: "2:0", + name: "OP", + desc: "CMO opcode: 0=FENCE, 1=INVAL_ALL, 2=INVAL_NLINE." + }] + } + }, + { + multireg: { + name: "CFG_LP1_CMO_ADDR", + desc: '''Per-core cacheline address for LP1 INVAL_NLINE. Ignored for + FENCE / INVAL_ALL.''' + swaccess: "rw", + hwaccess: "hro", + count: "NumLp1CmoRegs", + cname: "cfg_lp1_cmo_addr", + compact: "false", + resval: "0", + fields: [{ + bits: "31:0", + name: "ADDR", + desc: "Cacheline address for INVAL_NLINE." + }] + } + }, + { + multireg: { + name: "LP1_CMO_COMMIT", + desc: '''Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in + CFG_LP1_CMO[cid]; hardware clears it to 0 once the CMO is accepted + (mirrors L1D_INSN_COMMIT).''' + swaccess: "rw", + hwaccess: "hrw", + count: "NumLp1CmoRegs", + cname: "lp1_cmo_commit", + compact: "false", + resval: "0", + fields: [{ + bits: "0", + name: "COMMIT", + desc: "Commit/trigger the CMO for this core." + }] + } + }, + { + multireg: { + name: "LP1_CMO_STATUS", + desc: '''Per-core LP1 CMO status. High while this core's CMO is in flight; + Low when idle/complete. Polled by the runtime (like + L1D_FLUSH_STATUS).''' + hwext: "true", + swaccess: "ro", + hwaccess: "hwo", + count: "NumLp1CmoRegs", + cname: "lp1_cmo_status", + compact: "false", + resval: "0", + fields: [{ + bits: "0:0", + name: "STATUS", + desc: "High for running CMO; Low for idle/complete." + }] + } } ] } diff --git a/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv b/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv index 7afdf12..30c13ad 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv +++ b/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv @@ -8,9 +8,10 @@ package cachepool_peripheral_reg_pkg; // Param list parameter int NumTileSelRegs = 2; + parameter int NumLp1CmoRegs = 64; // Address widths within the block - parameter int BlockAw = 7; + parameter int BlockAw = 11; //////////////////////////// // Typedefs for registers // @@ -76,6 +77,18 @@ package cachepool_peripheral_reg_pkg; logic q; } cachepool_peripheral_reg2hw_xbar_offset_commit_reg_t; + typedef struct packed { + logic [2:0] q; + } cachepool_peripheral_reg2hw_cfg_lp1_cmo_mreg_t; + + typedef struct packed { + logic [31:0] q; + } cachepool_peripheral_reg2hw_cfg_lp1_cmo_addr_mreg_t; + + typedef struct packed { + logic q; + } cachepool_peripheral_reg2hw_lp1_cmo_commit_mreg_t; + typedef struct packed { logic [31:0] d; } cachepool_peripheral_hw2reg_hw_barrier_reg_t; @@ -99,57 +112,455 @@ package cachepool_peripheral_reg_pkg; logic de; } cachepool_peripheral_hw2reg_xbar_offset_commit_reg_t; + typedef struct packed { + logic d; + logic de; + } cachepool_peripheral_hw2reg_lp1_cmo_commit_mreg_t; + + typedef struct packed { + logic d; + } cachepool_peripheral_hw2reg_lp1_cmo_status_mreg_t; + // Register -> HW type typedef struct packed { - cachepool_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [221:190] - cachepool_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [189:189] - cachepool_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [188:188] - cachepool_peripheral_reg2hw_spatz_cycle_reg_t spatz_cycle; // [187:156] - cachepool_peripheral_reg2hw_cluster_boot_control_reg_t cluster_boot_control; // [155:124] - cachepool_peripheral_reg2hw_cluster_eoc_exit_reg_t cluster_eoc_exit; // [123:120] - cachepool_peripheral_reg2hw_cfg_l1d_spm_reg_t cfg_l1d_spm; // [119:110] - cachepool_peripheral_reg2hw_cfg_l1d_insn_reg_t cfg_l1d_insn; // [109:108] - cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_mreg_t [1:0] cfg_l1d_tile_sel; // [107:44] - cachepool_peripheral_reg2hw_l1d_spm_commit_reg_t l1d_spm_commit; // [43:43] - cachepool_peripheral_reg2hw_l1d_insn_commit_reg_t l1d_insn_commit; // [42:42] - cachepool_peripheral_reg2hw_l1d_private_reg_t l1d_private; // [41:38] - cachepool_peripheral_reg2hw_l1d_addr_reg_t l1d_addr; // [37:6] - cachepool_peripheral_reg2hw_xbar_offset_reg_t xbar_offset; // [5:1] - cachepool_peripheral_reg2hw_xbar_offset_commit_reg_t xbar_offset_commit; // [0:0] + cachepool_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [2525:2494] + cachepool_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [2493:2493] + cachepool_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [2492:2492] + cachepool_peripheral_reg2hw_spatz_cycle_reg_t spatz_cycle; // [2491:2460] + cachepool_peripheral_reg2hw_cluster_boot_control_reg_t cluster_boot_control; // [2459:2428] + cachepool_peripheral_reg2hw_cluster_eoc_exit_reg_t cluster_eoc_exit; // [2427:2424] + cachepool_peripheral_reg2hw_cfg_l1d_spm_reg_t cfg_l1d_spm; // [2423:2414] + cachepool_peripheral_reg2hw_cfg_l1d_insn_reg_t cfg_l1d_insn; // [2413:2412] + cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_mreg_t [1:0] cfg_l1d_tile_sel; // [2411:2348] + cachepool_peripheral_reg2hw_l1d_spm_commit_reg_t l1d_spm_commit; // [2347:2347] + cachepool_peripheral_reg2hw_l1d_insn_commit_reg_t l1d_insn_commit; // [2346:2346] + cachepool_peripheral_reg2hw_l1d_private_reg_t l1d_private; // [2345:2342] + cachepool_peripheral_reg2hw_l1d_addr_reg_t l1d_addr; // [2341:2310] + cachepool_peripheral_reg2hw_xbar_offset_reg_t xbar_offset; // [2309:2305] + cachepool_peripheral_reg2hw_xbar_offset_commit_reg_t xbar_offset_commit; // [2304:2304] + cachepool_peripheral_reg2hw_cfg_lp1_cmo_mreg_t [63:0] cfg_lp1_cmo; // [2303:2112] + cachepool_peripheral_reg2hw_cfg_lp1_cmo_addr_mreg_t [63:0] cfg_lp1_cmo_addr; // [2111:64] + cachepool_peripheral_reg2hw_lp1_cmo_commit_mreg_t [63:0] lp1_cmo_commit; // [63:0] } cachepool_peripheral_reg2hw_t; // HW -> register type typedef struct packed { - cachepool_peripheral_hw2reg_hw_barrier_reg_t hw_barrier; // [38:7] - cachepool_peripheral_hw2reg_l1d_spm_commit_reg_t l1d_spm_commit; // [6:5] - cachepool_peripheral_hw2reg_l1d_insn_commit_reg_t l1d_insn_commit; // [4:3] - cachepool_peripheral_hw2reg_l1d_flush_status_reg_t l1d_flush_status; // [2:2] - cachepool_peripheral_hw2reg_xbar_offset_commit_reg_t xbar_offset_commit; // [1:0] + cachepool_peripheral_hw2reg_hw_barrier_reg_t hw_barrier; // [230:199] + cachepool_peripheral_hw2reg_l1d_spm_commit_reg_t l1d_spm_commit; // [198:197] + cachepool_peripheral_hw2reg_l1d_insn_commit_reg_t l1d_insn_commit; // [196:195] + cachepool_peripheral_hw2reg_l1d_flush_status_reg_t l1d_flush_status; // [194:194] + cachepool_peripheral_hw2reg_xbar_offset_commit_reg_t xbar_offset_commit; // [193:192] + cachepool_peripheral_hw2reg_lp1_cmo_commit_mreg_t [63:0] lp1_cmo_commit; // [191:64] + cachepool_peripheral_hw2reg_lp1_cmo_status_mreg_t [63:0] lp1_cmo_status; // [63:0] } cachepool_peripheral_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET = 7'h 0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 7'h 4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET = 7'h 8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET = 7'h c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET = 7'h 10; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET = 7'h 14; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET = 7'h 18; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET = 7'h 1c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_OFFSET = 7'h 20; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_OFFSET = 7'h 24; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET = 7'h 28; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET = 7'h 2c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET = 7'h 30; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET = 7'h 34; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET = 7'h 38; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET = 7'h 3c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET = 7'h 40; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET = 11'h 0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 11'h 4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET = 11'h 8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET = 11'h c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET = 11'h 10; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET = 11'h 14; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET = 11'h 18; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET = 11'h 1c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_OFFSET = 11'h 20; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_OFFSET = 11'h 24; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET = 11'h 28; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET = 11'h 2c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET = 11'h 30; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET = 11'h 34; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET = 11'h 38; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET = 11'h 3c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET = 11'h 40; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_OFFSET = 11'h 44; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_OFFSET = 11'h 48; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_OFFSET = 11'h 4c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_OFFSET = 11'h 50; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_OFFSET = 11'h 54; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_OFFSET = 11'h 58; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_OFFSET = 11'h 5c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_OFFSET = 11'h 60; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_OFFSET = 11'h 64; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_OFFSET = 11'h 68; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_OFFSET = 11'h 6c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_OFFSET = 11'h 70; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_OFFSET = 11'h 74; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_OFFSET = 11'h 78; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_OFFSET = 11'h 7c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_OFFSET = 11'h 80; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_OFFSET = 11'h 84; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_OFFSET = 11'h 88; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_OFFSET = 11'h 8c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_OFFSET = 11'h 90; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_OFFSET = 11'h 94; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_OFFSET = 11'h 98; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_OFFSET = 11'h 9c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_OFFSET = 11'h a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_OFFSET = 11'h a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_OFFSET = 11'h a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_OFFSET = 11'h ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_OFFSET = 11'h b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_OFFSET = 11'h b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_OFFSET = 11'h b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_OFFSET = 11'h bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_OFFSET = 11'h c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_OFFSET = 11'h c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_OFFSET = 11'h c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_OFFSET = 11'h cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_OFFSET = 11'h d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_OFFSET = 11'h d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_OFFSET = 11'h d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_OFFSET = 11'h dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_OFFSET = 11'h e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_OFFSET = 11'h e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_OFFSET = 11'h e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_OFFSET = 11'h ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_OFFSET = 11'h f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_OFFSET = 11'h f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_OFFSET = 11'h f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_OFFSET = 11'h fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_OFFSET = 11'h 100; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_OFFSET = 11'h 104; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_OFFSET = 11'h 108; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_OFFSET = 11'h 10c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_OFFSET = 11'h 110; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_OFFSET = 11'h 114; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_OFFSET = 11'h 118; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_OFFSET = 11'h 11c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_OFFSET = 11'h 120; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_OFFSET = 11'h 440; // Reset values for hwext registers and their fields parameter logic [31:0] CACHEPOOL_PERIPHERAL_HW_BARRIER_RESVAL = 32'h 0; parameter logic [0:0] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_RESVAL = 1'h 0; parameter logic [0:0] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_STATUS_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_STATUS_0_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_STATUS_1_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_STATUS_2_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_STATUS_3_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_STATUS_4_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_STATUS_5_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_STATUS_6_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_STATUS_7_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_STATUS_8_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_STATUS_9_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_STATUS_10_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_STATUS_11_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_STATUS_12_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_STATUS_13_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_STATUS_14_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_STATUS_15_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_STATUS_16_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_STATUS_17_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_STATUS_18_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_STATUS_19_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_STATUS_20_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_STATUS_21_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_STATUS_22_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_STATUS_23_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_STATUS_24_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_STATUS_25_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_STATUS_26_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_STATUS_27_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_STATUS_28_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_STATUS_29_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_STATUS_30_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_STATUS_31_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_STATUS_32_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_STATUS_33_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_STATUS_34_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_STATUS_35_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_STATUS_36_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_STATUS_37_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_STATUS_38_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_STATUS_39_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_STATUS_40_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_STATUS_41_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_STATUS_42_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_STATUS_43_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_STATUS_44_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_STATUS_45_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_STATUS_46_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_STATUS_47_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_STATUS_48_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_STATUS_49_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_STATUS_50_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_STATUS_51_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_STATUS_52_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_STATUS_53_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_STATUS_54_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_STATUS_55_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_STATUS_56_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_STATUS_57_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_STATUS_58_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_STATUS_59_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_STATUS_60_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_STATUS_61_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_STATUS_62_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_STATUS_63_RESVAL = 1'h 0; // Register index typedef enum int { @@ -169,28 +580,540 @@ package cachepool_peripheral_reg_pkg; CACHEPOOL_PERIPHERAL_L1D_PRIVATE, CACHEPOOL_PERIPHERAL_L1D_ADDR, CACHEPOOL_PERIPHERAL_XBAR_OFFSET, - CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT + CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63 } cachepool_peripheral_id_e; // Register width information to check illegal writes - parameter logic [3:0] CACHEPOOL_PERIPHERAL_PERMIT [17] = '{ - 4'b 1111, // index[ 0] CACHEPOOL_PERIPHERAL_HW_BARRIER - 4'b 0001, // index[ 1] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE - 4'b 0001, // index[ 2] CACHEPOOL_PERIPHERAL_SPATZ_STATUS - 4'b 1111, // index[ 3] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE - 4'b 1111, // index[ 4] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL - 4'b 0001, // index[ 5] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT - 4'b 0011, // index[ 6] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM - 4'b 0001, // index[ 7] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN - 4'b 1111, // index[ 8] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0 - 4'b 1111, // index[ 9] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1 - 4'b 0001, // index[10] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT - 4'b 0001, // index[11] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT - 4'b 0001, // index[12] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS - 4'b 0001, // index[13] CACHEPOOL_PERIPHERAL_L1D_PRIVATE - 4'b 1111, // index[14] CACHEPOOL_PERIPHERAL_L1D_ADDR - 4'b 0001, // index[15] CACHEPOOL_PERIPHERAL_XBAR_OFFSET - 4'b 0001 // index[16] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT + parameter logic [3:0] CACHEPOOL_PERIPHERAL_PERMIT [273] = '{ + 4'b 1111, // index[ 0] CACHEPOOL_PERIPHERAL_HW_BARRIER + 4'b 0001, // index[ 1] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE + 4'b 0001, // index[ 2] CACHEPOOL_PERIPHERAL_SPATZ_STATUS + 4'b 1111, // index[ 3] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE + 4'b 1111, // index[ 4] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL + 4'b 0001, // index[ 5] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT + 4'b 0011, // index[ 6] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM + 4'b 0001, // index[ 7] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN + 4'b 1111, // index[ 8] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0 + 4'b 1111, // index[ 9] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1 + 4'b 0001, // index[ 10] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT + 4'b 0001, // index[ 11] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT + 4'b 0001, // index[ 12] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS + 4'b 0001, // index[ 13] CACHEPOOL_PERIPHERAL_L1D_PRIVATE + 4'b 1111, // index[ 14] CACHEPOOL_PERIPHERAL_L1D_ADDR + 4'b 0001, // index[ 15] CACHEPOOL_PERIPHERAL_XBAR_OFFSET + 4'b 0001, // index[ 16] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT + 4'b 0001, // index[ 17] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0 + 4'b 0001, // index[ 18] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1 + 4'b 0001, // index[ 19] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2 + 4'b 0001, // index[ 20] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3 + 4'b 0001, // index[ 21] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4 + 4'b 0001, // index[ 22] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5 + 4'b 0001, // index[ 23] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6 + 4'b 0001, // index[ 24] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7 + 4'b 0001, // index[ 25] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8 + 4'b 0001, // index[ 26] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9 + 4'b 0001, // index[ 27] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10 + 4'b 0001, // index[ 28] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11 + 4'b 0001, // index[ 29] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12 + 4'b 0001, // index[ 30] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13 + 4'b 0001, // index[ 31] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14 + 4'b 0001, // index[ 32] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15 + 4'b 0001, // index[ 33] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16 + 4'b 0001, // index[ 34] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17 + 4'b 0001, // index[ 35] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18 + 4'b 0001, // index[ 36] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19 + 4'b 0001, // index[ 37] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20 + 4'b 0001, // index[ 38] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21 + 4'b 0001, // index[ 39] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22 + 4'b 0001, // index[ 40] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23 + 4'b 0001, // index[ 41] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24 + 4'b 0001, // index[ 42] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25 + 4'b 0001, // index[ 43] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26 + 4'b 0001, // index[ 44] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27 + 4'b 0001, // index[ 45] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28 + 4'b 0001, // index[ 46] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29 + 4'b 0001, // index[ 47] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30 + 4'b 0001, // index[ 48] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31 + 4'b 0001, // index[ 49] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32 + 4'b 0001, // index[ 50] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33 + 4'b 0001, // index[ 51] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34 + 4'b 0001, // index[ 52] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35 + 4'b 0001, // index[ 53] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36 + 4'b 0001, // index[ 54] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37 + 4'b 0001, // index[ 55] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38 + 4'b 0001, // index[ 56] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39 + 4'b 0001, // index[ 57] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40 + 4'b 0001, // index[ 58] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41 + 4'b 0001, // index[ 59] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42 + 4'b 0001, // index[ 60] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43 + 4'b 0001, // index[ 61] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44 + 4'b 0001, // index[ 62] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45 + 4'b 0001, // index[ 63] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46 + 4'b 0001, // index[ 64] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47 + 4'b 0001, // index[ 65] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48 + 4'b 0001, // index[ 66] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49 + 4'b 0001, // index[ 67] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50 + 4'b 0001, // index[ 68] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51 + 4'b 0001, // index[ 69] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52 + 4'b 0001, // index[ 70] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53 + 4'b 0001, // index[ 71] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54 + 4'b 0001, // index[ 72] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55 + 4'b 0001, // index[ 73] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56 + 4'b 0001, // index[ 74] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57 + 4'b 0001, // index[ 75] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58 + 4'b 0001, // index[ 76] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59 + 4'b 0001, // index[ 77] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60 + 4'b 0001, // index[ 78] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61 + 4'b 0001, // index[ 79] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62 + 4'b 0001, // index[ 80] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63 + 4'b 1111, // index[ 81] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0 + 4'b 1111, // index[ 82] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1 + 4'b 1111, // index[ 83] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2 + 4'b 1111, // index[ 84] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3 + 4'b 1111, // index[ 85] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4 + 4'b 1111, // index[ 86] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5 + 4'b 1111, // index[ 87] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6 + 4'b 1111, // index[ 88] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7 + 4'b 1111, // index[ 89] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8 + 4'b 1111, // index[ 90] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9 + 4'b 1111, // index[ 91] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10 + 4'b 1111, // index[ 92] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11 + 4'b 1111, // index[ 93] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12 + 4'b 1111, // index[ 94] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13 + 4'b 1111, // index[ 95] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14 + 4'b 1111, // index[ 96] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15 + 4'b 1111, // index[ 97] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16 + 4'b 1111, // index[ 98] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17 + 4'b 1111, // index[ 99] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18 + 4'b 1111, // index[100] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19 + 4'b 1111, // index[101] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20 + 4'b 1111, // index[102] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21 + 4'b 1111, // index[103] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22 + 4'b 1111, // index[104] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23 + 4'b 1111, // index[105] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24 + 4'b 1111, // index[106] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25 + 4'b 1111, // index[107] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26 + 4'b 1111, // index[108] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27 + 4'b 1111, // index[109] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28 + 4'b 1111, // index[110] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29 + 4'b 1111, // index[111] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30 + 4'b 1111, // index[112] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31 + 4'b 1111, // index[113] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32 + 4'b 1111, // index[114] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33 + 4'b 1111, // index[115] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34 + 4'b 1111, // index[116] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35 + 4'b 1111, // index[117] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36 + 4'b 1111, // index[118] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37 + 4'b 1111, // index[119] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38 + 4'b 1111, // index[120] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39 + 4'b 1111, // index[121] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40 + 4'b 1111, // index[122] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41 + 4'b 1111, // index[123] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42 + 4'b 1111, // index[124] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43 + 4'b 1111, // index[125] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44 + 4'b 1111, // index[126] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45 + 4'b 1111, // index[127] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46 + 4'b 1111, // index[128] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47 + 4'b 1111, // index[129] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48 + 4'b 1111, // index[130] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49 + 4'b 1111, // index[131] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50 + 4'b 1111, // index[132] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51 + 4'b 1111, // index[133] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52 + 4'b 1111, // index[134] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53 + 4'b 1111, // index[135] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54 + 4'b 1111, // index[136] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55 + 4'b 1111, // index[137] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56 + 4'b 1111, // index[138] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57 + 4'b 1111, // index[139] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58 + 4'b 1111, // index[140] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59 + 4'b 1111, // index[141] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60 + 4'b 1111, // index[142] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61 + 4'b 1111, // index[143] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62 + 4'b 1111, // index[144] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63 + 4'b 0001, // index[145] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0 + 4'b 0001, // index[146] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1 + 4'b 0001, // index[147] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2 + 4'b 0001, // index[148] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3 + 4'b 0001, // index[149] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4 + 4'b 0001, // index[150] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5 + 4'b 0001, // index[151] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6 + 4'b 0001, // index[152] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7 + 4'b 0001, // index[153] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8 + 4'b 0001, // index[154] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9 + 4'b 0001, // index[155] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10 + 4'b 0001, // index[156] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11 + 4'b 0001, // index[157] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12 + 4'b 0001, // index[158] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13 + 4'b 0001, // index[159] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14 + 4'b 0001, // index[160] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15 + 4'b 0001, // index[161] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16 + 4'b 0001, // index[162] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17 + 4'b 0001, // index[163] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18 + 4'b 0001, // index[164] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19 + 4'b 0001, // index[165] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20 + 4'b 0001, // index[166] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21 + 4'b 0001, // index[167] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22 + 4'b 0001, // index[168] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23 + 4'b 0001, // index[169] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24 + 4'b 0001, // index[170] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25 + 4'b 0001, // index[171] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26 + 4'b 0001, // index[172] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27 + 4'b 0001, // index[173] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28 + 4'b 0001, // index[174] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29 + 4'b 0001, // index[175] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30 + 4'b 0001, // index[176] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31 + 4'b 0001, // index[177] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32 + 4'b 0001, // index[178] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33 + 4'b 0001, // index[179] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34 + 4'b 0001, // index[180] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35 + 4'b 0001, // index[181] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36 + 4'b 0001, // index[182] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37 + 4'b 0001, // index[183] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38 + 4'b 0001, // index[184] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39 + 4'b 0001, // index[185] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40 + 4'b 0001, // index[186] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41 + 4'b 0001, // index[187] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42 + 4'b 0001, // index[188] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43 + 4'b 0001, // index[189] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44 + 4'b 0001, // index[190] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45 + 4'b 0001, // index[191] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46 + 4'b 0001, // index[192] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47 + 4'b 0001, // index[193] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48 + 4'b 0001, // index[194] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49 + 4'b 0001, // index[195] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50 + 4'b 0001, // index[196] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51 + 4'b 0001, // index[197] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52 + 4'b 0001, // index[198] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53 + 4'b 0001, // index[199] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54 + 4'b 0001, // index[200] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55 + 4'b 0001, // index[201] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56 + 4'b 0001, // index[202] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57 + 4'b 0001, // index[203] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58 + 4'b 0001, // index[204] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59 + 4'b 0001, // index[205] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60 + 4'b 0001, // index[206] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61 + 4'b 0001, // index[207] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62 + 4'b 0001, // index[208] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63 + 4'b 0001, // index[209] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0 + 4'b 0001, // index[210] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1 + 4'b 0001, // index[211] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2 + 4'b 0001, // index[212] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3 + 4'b 0001, // index[213] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4 + 4'b 0001, // index[214] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5 + 4'b 0001, // index[215] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6 + 4'b 0001, // index[216] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7 + 4'b 0001, // index[217] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8 + 4'b 0001, // index[218] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9 + 4'b 0001, // index[219] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10 + 4'b 0001, // index[220] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11 + 4'b 0001, // index[221] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12 + 4'b 0001, // index[222] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13 + 4'b 0001, // index[223] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14 + 4'b 0001, // index[224] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15 + 4'b 0001, // index[225] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16 + 4'b 0001, // index[226] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17 + 4'b 0001, // index[227] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18 + 4'b 0001, // index[228] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19 + 4'b 0001, // index[229] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20 + 4'b 0001, // index[230] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21 + 4'b 0001, // index[231] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22 + 4'b 0001, // index[232] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23 + 4'b 0001, // index[233] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24 + 4'b 0001, // index[234] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25 + 4'b 0001, // index[235] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26 + 4'b 0001, // index[236] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27 + 4'b 0001, // index[237] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28 + 4'b 0001, // index[238] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29 + 4'b 0001, // index[239] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30 + 4'b 0001, // index[240] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31 + 4'b 0001, // index[241] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32 + 4'b 0001, // index[242] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33 + 4'b 0001, // index[243] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34 + 4'b 0001, // index[244] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35 + 4'b 0001, // index[245] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36 + 4'b 0001, // index[246] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37 + 4'b 0001, // index[247] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38 + 4'b 0001, // index[248] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39 + 4'b 0001, // index[249] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40 + 4'b 0001, // index[250] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41 + 4'b 0001, // index[251] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42 + 4'b 0001, // index[252] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43 + 4'b 0001, // index[253] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44 + 4'b 0001, // index[254] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45 + 4'b 0001, // index[255] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46 + 4'b 0001, // index[256] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47 + 4'b 0001, // index[257] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48 + 4'b 0001, // index[258] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49 + 4'b 0001, // index[259] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50 + 4'b 0001, // index[260] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51 + 4'b 0001, // index[261] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52 + 4'b 0001, // index[262] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53 + 4'b 0001, // index[263] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54 + 4'b 0001, // index[264] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55 + 4'b 0001, // index[265] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56 + 4'b 0001, // index[266] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57 + 4'b 0001, // index[267] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58 + 4'b 0001, // index[268] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59 + 4'b 0001, // index[269] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60 + 4'b 0001, // index[270] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61 + 4'b 0001, // index[271] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62 + 4'b 0001 // index[272] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63 }; endpackage diff --git a/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv b/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv index 723cf3f..5cda172 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv +++ b/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv @@ -10,7 +10,7 @@ module cachepool_peripheral_reg_top #( parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, - parameter int AW = 7 + parameter int AW = 11 ) ( input logic clk_i, input logic rst_ni, @@ -115,6 +115,710 @@ module cachepool_peripheral_reg_top #( logic xbar_offset_commit_qs; logic xbar_offset_commit_wd; logic xbar_offset_commit_we; + logic [2:0] cfg_lp1_cmo_0_qs; + logic [2:0] cfg_lp1_cmo_0_wd; + logic cfg_lp1_cmo_0_we; + logic [2:0] cfg_lp1_cmo_1_qs; + logic [2:0] cfg_lp1_cmo_1_wd; + logic cfg_lp1_cmo_1_we; + logic [2:0] cfg_lp1_cmo_2_qs; + logic [2:0] cfg_lp1_cmo_2_wd; + logic cfg_lp1_cmo_2_we; + logic [2:0] cfg_lp1_cmo_3_qs; + logic [2:0] cfg_lp1_cmo_3_wd; + logic cfg_lp1_cmo_3_we; + logic [2:0] cfg_lp1_cmo_4_qs; + logic [2:0] cfg_lp1_cmo_4_wd; + logic cfg_lp1_cmo_4_we; + logic [2:0] cfg_lp1_cmo_5_qs; + logic [2:0] cfg_lp1_cmo_5_wd; + logic cfg_lp1_cmo_5_we; + logic [2:0] cfg_lp1_cmo_6_qs; + logic [2:0] cfg_lp1_cmo_6_wd; + logic cfg_lp1_cmo_6_we; + logic [2:0] cfg_lp1_cmo_7_qs; + logic [2:0] cfg_lp1_cmo_7_wd; + logic cfg_lp1_cmo_7_we; + logic [2:0] cfg_lp1_cmo_8_qs; + logic [2:0] cfg_lp1_cmo_8_wd; + logic cfg_lp1_cmo_8_we; + logic [2:0] cfg_lp1_cmo_9_qs; + logic [2:0] cfg_lp1_cmo_9_wd; + logic cfg_lp1_cmo_9_we; + logic [2:0] cfg_lp1_cmo_10_qs; + logic [2:0] cfg_lp1_cmo_10_wd; + logic cfg_lp1_cmo_10_we; + logic [2:0] cfg_lp1_cmo_11_qs; + logic [2:0] cfg_lp1_cmo_11_wd; + logic cfg_lp1_cmo_11_we; + logic [2:0] cfg_lp1_cmo_12_qs; + logic [2:0] cfg_lp1_cmo_12_wd; + logic cfg_lp1_cmo_12_we; + logic [2:0] cfg_lp1_cmo_13_qs; + logic [2:0] cfg_lp1_cmo_13_wd; + logic cfg_lp1_cmo_13_we; + logic [2:0] cfg_lp1_cmo_14_qs; + logic [2:0] cfg_lp1_cmo_14_wd; + logic cfg_lp1_cmo_14_we; + logic [2:0] cfg_lp1_cmo_15_qs; + logic [2:0] cfg_lp1_cmo_15_wd; + logic cfg_lp1_cmo_15_we; + logic [2:0] cfg_lp1_cmo_16_qs; + logic [2:0] cfg_lp1_cmo_16_wd; + logic cfg_lp1_cmo_16_we; + logic [2:0] cfg_lp1_cmo_17_qs; + logic [2:0] cfg_lp1_cmo_17_wd; + logic cfg_lp1_cmo_17_we; + logic [2:0] cfg_lp1_cmo_18_qs; + logic [2:0] cfg_lp1_cmo_18_wd; + logic cfg_lp1_cmo_18_we; + logic [2:0] cfg_lp1_cmo_19_qs; + logic [2:0] cfg_lp1_cmo_19_wd; + logic cfg_lp1_cmo_19_we; + logic [2:0] cfg_lp1_cmo_20_qs; + logic [2:0] cfg_lp1_cmo_20_wd; + logic cfg_lp1_cmo_20_we; + logic [2:0] cfg_lp1_cmo_21_qs; + logic [2:0] cfg_lp1_cmo_21_wd; + logic cfg_lp1_cmo_21_we; + logic [2:0] cfg_lp1_cmo_22_qs; + logic [2:0] cfg_lp1_cmo_22_wd; + logic cfg_lp1_cmo_22_we; + logic [2:0] cfg_lp1_cmo_23_qs; + logic [2:0] cfg_lp1_cmo_23_wd; + logic cfg_lp1_cmo_23_we; + logic [2:0] cfg_lp1_cmo_24_qs; + logic [2:0] cfg_lp1_cmo_24_wd; + logic cfg_lp1_cmo_24_we; + logic [2:0] cfg_lp1_cmo_25_qs; + logic [2:0] cfg_lp1_cmo_25_wd; + logic cfg_lp1_cmo_25_we; + logic [2:0] cfg_lp1_cmo_26_qs; + logic [2:0] cfg_lp1_cmo_26_wd; + logic cfg_lp1_cmo_26_we; + logic [2:0] cfg_lp1_cmo_27_qs; + logic [2:0] cfg_lp1_cmo_27_wd; + logic cfg_lp1_cmo_27_we; + logic [2:0] cfg_lp1_cmo_28_qs; + logic [2:0] cfg_lp1_cmo_28_wd; + logic cfg_lp1_cmo_28_we; + logic [2:0] cfg_lp1_cmo_29_qs; + logic [2:0] cfg_lp1_cmo_29_wd; + logic cfg_lp1_cmo_29_we; + logic [2:0] cfg_lp1_cmo_30_qs; + logic [2:0] cfg_lp1_cmo_30_wd; + logic cfg_lp1_cmo_30_we; + logic [2:0] cfg_lp1_cmo_31_qs; + logic [2:0] cfg_lp1_cmo_31_wd; + logic cfg_lp1_cmo_31_we; + logic [2:0] cfg_lp1_cmo_32_qs; + logic [2:0] cfg_lp1_cmo_32_wd; + logic cfg_lp1_cmo_32_we; + logic [2:0] cfg_lp1_cmo_33_qs; + logic [2:0] cfg_lp1_cmo_33_wd; + logic cfg_lp1_cmo_33_we; + logic [2:0] cfg_lp1_cmo_34_qs; + logic [2:0] cfg_lp1_cmo_34_wd; + logic cfg_lp1_cmo_34_we; + logic [2:0] cfg_lp1_cmo_35_qs; + logic [2:0] cfg_lp1_cmo_35_wd; + logic cfg_lp1_cmo_35_we; + logic [2:0] cfg_lp1_cmo_36_qs; + logic [2:0] cfg_lp1_cmo_36_wd; + logic cfg_lp1_cmo_36_we; + logic [2:0] cfg_lp1_cmo_37_qs; + logic [2:0] cfg_lp1_cmo_37_wd; + logic cfg_lp1_cmo_37_we; + logic [2:0] cfg_lp1_cmo_38_qs; + logic [2:0] cfg_lp1_cmo_38_wd; + logic cfg_lp1_cmo_38_we; + logic [2:0] cfg_lp1_cmo_39_qs; + logic [2:0] cfg_lp1_cmo_39_wd; + logic cfg_lp1_cmo_39_we; + logic [2:0] cfg_lp1_cmo_40_qs; + logic [2:0] cfg_lp1_cmo_40_wd; + logic cfg_lp1_cmo_40_we; + logic [2:0] cfg_lp1_cmo_41_qs; + logic [2:0] cfg_lp1_cmo_41_wd; + logic cfg_lp1_cmo_41_we; + logic [2:0] cfg_lp1_cmo_42_qs; + logic [2:0] cfg_lp1_cmo_42_wd; + logic cfg_lp1_cmo_42_we; + logic [2:0] cfg_lp1_cmo_43_qs; + logic [2:0] cfg_lp1_cmo_43_wd; + logic cfg_lp1_cmo_43_we; + logic [2:0] cfg_lp1_cmo_44_qs; + logic [2:0] cfg_lp1_cmo_44_wd; + logic cfg_lp1_cmo_44_we; + logic [2:0] cfg_lp1_cmo_45_qs; + logic [2:0] cfg_lp1_cmo_45_wd; + logic cfg_lp1_cmo_45_we; + logic [2:0] cfg_lp1_cmo_46_qs; + logic [2:0] cfg_lp1_cmo_46_wd; + logic cfg_lp1_cmo_46_we; + logic [2:0] cfg_lp1_cmo_47_qs; + logic [2:0] cfg_lp1_cmo_47_wd; + logic cfg_lp1_cmo_47_we; + logic [2:0] cfg_lp1_cmo_48_qs; + logic [2:0] cfg_lp1_cmo_48_wd; + logic cfg_lp1_cmo_48_we; + logic [2:0] cfg_lp1_cmo_49_qs; + logic [2:0] cfg_lp1_cmo_49_wd; + logic cfg_lp1_cmo_49_we; + logic [2:0] cfg_lp1_cmo_50_qs; + logic [2:0] cfg_lp1_cmo_50_wd; + logic cfg_lp1_cmo_50_we; + logic [2:0] cfg_lp1_cmo_51_qs; + logic [2:0] cfg_lp1_cmo_51_wd; + logic cfg_lp1_cmo_51_we; + logic [2:0] cfg_lp1_cmo_52_qs; + logic [2:0] cfg_lp1_cmo_52_wd; + logic cfg_lp1_cmo_52_we; + logic [2:0] cfg_lp1_cmo_53_qs; + logic [2:0] cfg_lp1_cmo_53_wd; + logic cfg_lp1_cmo_53_we; + logic [2:0] cfg_lp1_cmo_54_qs; + logic [2:0] cfg_lp1_cmo_54_wd; + logic cfg_lp1_cmo_54_we; + logic [2:0] cfg_lp1_cmo_55_qs; + logic [2:0] cfg_lp1_cmo_55_wd; + logic cfg_lp1_cmo_55_we; + logic [2:0] cfg_lp1_cmo_56_qs; + logic [2:0] cfg_lp1_cmo_56_wd; + logic cfg_lp1_cmo_56_we; + logic [2:0] cfg_lp1_cmo_57_qs; + logic [2:0] cfg_lp1_cmo_57_wd; + logic cfg_lp1_cmo_57_we; + logic [2:0] cfg_lp1_cmo_58_qs; + logic [2:0] cfg_lp1_cmo_58_wd; + logic cfg_lp1_cmo_58_we; + logic [2:0] cfg_lp1_cmo_59_qs; + logic [2:0] cfg_lp1_cmo_59_wd; + logic cfg_lp1_cmo_59_we; + logic [2:0] cfg_lp1_cmo_60_qs; + logic [2:0] cfg_lp1_cmo_60_wd; + logic cfg_lp1_cmo_60_we; + logic [2:0] cfg_lp1_cmo_61_qs; + logic [2:0] cfg_lp1_cmo_61_wd; + logic cfg_lp1_cmo_61_we; + logic [2:0] cfg_lp1_cmo_62_qs; + logic [2:0] cfg_lp1_cmo_62_wd; + logic cfg_lp1_cmo_62_we; + logic [2:0] cfg_lp1_cmo_63_qs; + logic [2:0] cfg_lp1_cmo_63_wd; + logic cfg_lp1_cmo_63_we; + logic [31:0] cfg_lp1_cmo_addr_0_qs; + logic [31:0] cfg_lp1_cmo_addr_0_wd; + logic cfg_lp1_cmo_addr_0_we; + logic [31:0] cfg_lp1_cmo_addr_1_qs; + logic [31:0] cfg_lp1_cmo_addr_1_wd; + logic cfg_lp1_cmo_addr_1_we; + logic [31:0] cfg_lp1_cmo_addr_2_qs; + logic [31:0] cfg_lp1_cmo_addr_2_wd; + logic cfg_lp1_cmo_addr_2_we; + logic [31:0] cfg_lp1_cmo_addr_3_qs; + logic [31:0] cfg_lp1_cmo_addr_3_wd; + logic cfg_lp1_cmo_addr_3_we; + logic [31:0] cfg_lp1_cmo_addr_4_qs; + logic [31:0] cfg_lp1_cmo_addr_4_wd; + logic cfg_lp1_cmo_addr_4_we; + logic [31:0] cfg_lp1_cmo_addr_5_qs; + logic [31:0] cfg_lp1_cmo_addr_5_wd; + logic cfg_lp1_cmo_addr_5_we; + logic [31:0] cfg_lp1_cmo_addr_6_qs; + logic [31:0] cfg_lp1_cmo_addr_6_wd; + logic cfg_lp1_cmo_addr_6_we; + logic [31:0] cfg_lp1_cmo_addr_7_qs; + logic [31:0] cfg_lp1_cmo_addr_7_wd; + logic cfg_lp1_cmo_addr_7_we; + logic [31:0] cfg_lp1_cmo_addr_8_qs; + logic [31:0] cfg_lp1_cmo_addr_8_wd; + logic cfg_lp1_cmo_addr_8_we; + logic [31:0] cfg_lp1_cmo_addr_9_qs; + logic [31:0] cfg_lp1_cmo_addr_9_wd; + logic cfg_lp1_cmo_addr_9_we; + logic [31:0] cfg_lp1_cmo_addr_10_qs; + logic [31:0] cfg_lp1_cmo_addr_10_wd; + logic cfg_lp1_cmo_addr_10_we; + logic [31:0] cfg_lp1_cmo_addr_11_qs; + logic [31:0] cfg_lp1_cmo_addr_11_wd; + logic cfg_lp1_cmo_addr_11_we; + logic [31:0] cfg_lp1_cmo_addr_12_qs; + logic [31:0] cfg_lp1_cmo_addr_12_wd; + logic cfg_lp1_cmo_addr_12_we; + logic [31:0] cfg_lp1_cmo_addr_13_qs; + logic [31:0] cfg_lp1_cmo_addr_13_wd; + logic cfg_lp1_cmo_addr_13_we; + logic [31:0] cfg_lp1_cmo_addr_14_qs; + logic [31:0] cfg_lp1_cmo_addr_14_wd; + logic cfg_lp1_cmo_addr_14_we; + logic [31:0] cfg_lp1_cmo_addr_15_qs; + logic [31:0] cfg_lp1_cmo_addr_15_wd; + logic cfg_lp1_cmo_addr_15_we; + logic [31:0] cfg_lp1_cmo_addr_16_qs; + logic [31:0] cfg_lp1_cmo_addr_16_wd; + logic cfg_lp1_cmo_addr_16_we; + logic [31:0] cfg_lp1_cmo_addr_17_qs; + logic [31:0] cfg_lp1_cmo_addr_17_wd; + logic cfg_lp1_cmo_addr_17_we; + logic [31:0] cfg_lp1_cmo_addr_18_qs; + logic [31:0] cfg_lp1_cmo_addr_18_wd; + logic cfg_lp1_cmo_addr_18_we; + logic [31:0] cfg_lp1_cmo_addr_19_qs; + logic [31:0] cfg_lp1_cmo_addr_19_wd; + logic cfg_lp1_cmo_addr_19_we; + logic [31:0] cfg_lp1_cmo_addr_20_qs; + logic [31:0] cfg_lp1_cmo_addr_20_wd; + logic cfg_lp1_cmo_addr_20_we; + logic [31:0] cfg_lp1_cmo_addr_21_qs; + logic [31:0] cfg_lp1_cmo_addr_21_wd; + logic cfg_lp1_cmo_addr_21_we; + logic [31:0] cfg_lp1_cmo_addr_22_qs; + logic [31:0] cfg_lp1_cmo_addr_22_wd; + logic cfg_lp1_cmo_addr_22_we; + logic [31:0] cfg_lp1_cmo_addr_23_qs; + logic [31:0] cfg_lp1_cmo_addr_23_wd; + logic cfg_lp1_cmo_addr_23_we; + logic [31:0] cfg_lp1_cmo_addr_24_qs; + logic [31:0] cfg_lp1_cmo_addr_24_wd; + logic cfg_lp1_cmo_addr_24_we; + logic [31:0] cfg_lp1_cmo_addr_25_qs; + logic [31:0] cfg_lp1_cmo_addr_25_wd; + logic cfg_lp1_cmo_addr_25_we; + logic [31:0] cfg_lp1_cmo_addr_26_qs; + logic [31:0] cfg_lp1_cmo_addr_26_wd; + logic cfg_lp1_cmo_addr_26_we; + logic [31:0] cfg_lp1_cmo_addr_27_qs; + logic [31:0] cfg_lp1_cmo_addr_27_wd; + logic cfg_lp1_cmo_addr_27_we; + logic [31:0] cfg_lp1_cmo_addr_28_qs; + logic [31:0] cfg_lp1_cmo_addr_28_wd; + logic cfg_lp1_cmo_addr_28_we; + logic [31:0] cfg_lp1_cmo_addr_29_qs; + logic [31:0] cfg_lp1_cmo_addr_29_wd; + logic cfg_lp1_cmo_addr_29_we; + logic [31:0] cfg_lp1_cmo_addr_30_qs; + logic [31:0] cfg_lp1_cmo_addr_30_wd; + logic cfg_lp1_cmo_addr_30_we; + logic [31:0] cfg_lp1_cmo_addr_31_qs; + logic [31:0] cfg_lp1_cmo_addr_31_wd; + logic cfg_lp1_cmo_addr_31_we; + logic [31:0] cfg_lp1_cmo_addr_32_qs; + logic [31:0] cfg_lp1_cmo_addr_32_wd; + logic cfg_lp1_cmo_addr_32_we; + logic [31:0] cfg_lp1_cmo_addr_33_qs; + logic [31:0] cfg_lp1_cmo_addr_33_wd; + logic cfg_lp1_cmo_addr_33_we; + logic [31:0] cfg_lp1_cmo_addr_34_qs; + logic [31:0] cfg_lp1_cmo_addr_34_wd; + logic cfg_lp1_cmo_addr_34_we; + logic [31:0] cfg_lp1_cmo_addr_35_qs; + logic [31:0] cfg_lp1_cmo_addr_35_wd; + logic cfg_lp1_cmo_addr_35_we; + logic [31:0] cfg_lp1_cmo_addr_36_qs; + logic [31:0] cfg_lp1_cmo_addr_36_wd; + logic cfg_lp1_cmo_addr_36_we; + logic [31:0] cfg_lp1_cmo_addr_37_qs; + logic [31:0] cfg_lp1_cmo_addr_37_wd; + logic cfg_lp1_cmo_addr_37_we; + logic [31:0] cfg_lp1_cmo_addr_38_qs; + logic [31:0] cfg_lp1_cmo_addr_38_wd; + logic cfg_lp1_cmo_addr_38_we; + logic [31:0] cfg_lp1_cmo_addr_39_qs; + logic [31:0] cfg_lp1_cmo_addr_39_wd; + logic cfg_lp1_cmo_addr_39_we; + logic [31:0] cfg_lp1_cmo_addr_40_qs; + logic [31:0] cfg_lp1_cmo_addr_40_wd; + logic cfg_lp1_cmo_addr_40_we; + logic [31:0] cfg_lp1_cmo_addr_41_qs; + logic [31:0] cfg_lp1_cmo_addr_41_wd; + logic cfg_lp1_cmo_addr_41_we; + logic [31:0] cfg_lp1_cmo_addr_42_qs; + logic [31:0] cfg_lp1_cmo_addr_42_wd; + logic cfg_lp1_cmo_addr_42_we; + logic [31:0] cfg_lp1_cmo_addr_43_qs; + logic [31:0] cfg_lp1_cmo_addr_43_wd; + logic cfg_lp1_cmo_addr_43_we; + logic [31:0] cfg_lp1_cmo_addr_44_qs; + logic [31:0] cfg_lp1_cmo_addr_44_wd; + logic cfg_lp1_cmo_addr_44_we; + logic [31:0] cfg_lp1_cmo_addr_45_qs; + logic [31:0] cfg_lp1_cmo_addr_45_wd; + logic cfg_lp1_cmo_addr_45_we; + logic [31:0] cfg_lp1_cmo_addr_46_qs; + logic [31:0] cfg_lp1_cmo_addr_46_wd; + logic cfg_lp1_cmo_addr_46_we; + logic [31:0] cfg_lp1_cmo_addr_47_qs; + logic [31:0] cfg_lp1_cmo_addr_47_wd; + logic cfg_lp1_cmo_addr_47_we; + logic [31:0] cfg_lp1_cmo_addr_48_qs; + logic [31:0] cfg_lp1_cmo_addr_48_wd; + logic cfg_lp1_cmo_addr_48_we; + logic [31:0] cfg_lp1_cmo_addr_49_qs; + logic [31:0] cfg_lp1_cmo_addr_49_wd; + logic cfg_lp1_cmo_addr_49_we; + logic [31:0] cfg_lp1_cmo_addr_50_qs; + logic [31:0] cfg_lp1_cmo_addr_50_wd; + logic cfg_lp1_cmo_addr_50_we; + logic [31:0] cfg_lp1_cmo_addr_51_qs; + logic [31:0] cfg_lp1_cmo_addr_51_wd; + logic cfg_lp1_cmo_addr_51_we; + logic [31:0] cfg_lp1_cmo_addr_52_qs; + logic [31:0] cfg_lp1_cmo_addr_52_wd; + logic cfg_lp1_cmo_addr_52_we; + logic [31:0] cfg_lp1_cmo_addr_53_qs; + logic [31:0] cfg_lp1_cmo_addr_53_wd; + logic cfg_lp1_cmo_addr_53_we; + logic [31:0] cfg_lp1_cmo_addr_54_qs; + logic [31:0] cfg_lp1_cmo_addr_54_wd; + logic cfg_lp1_cmo_addr_54_we; + logic [31:0] cfg_lp1_cmo_addr_55_qs; + logic [31:0] cfg_lp1_cmo_addr_55_wd; + logic cfg_lp1_cmo_addr_55_we; + logic [31:0] cfg_lp1_cmo_addr_56_qs; + logic [31:0] cfg_lp1_cmo_addr_56_wd; + logic cfg_lp1_cmo_addr_56_we; + logic [31:0] cfg_lp1_cmo_addr_57_qs; + logic [31:0] cfg_lp1_cmo_addr_57_wd; + logic cfg_lp1_cmo_addr_57_we; + logic [31:0] cfg_lp1_cmo_addr_58_qs; + logic [31:0] cfg_lp1_cmo_addr_58_wd; + logic cfg_lp1_cmo_addr_58_we; + logic [31:0] cfg_lp1_cmo_addr_59_qs; + logic [31:0] cfg_lp1_cmo_addr_59_wd; + logic cfg_lp1_cmo_addr_59_we; + logic [31:0] cfg_lp1_cmo_addr_60_qs; + logic [31:0] cfg_lp1_cmo_addr_60_wd; + logic cfg_lp1_cmo_addr_60_we; + logic [31:0] cfg_lp1_cmo_addr_61_qs; + logic [31:0] cfg_lp1_cmo_addr_61_wd; + logic cfg_lp1_cmo_addr_61_we; + logic [31:0] cfg_lp1_cmo_addr_62_qs; + logic [31:0] cfg_lp1_cmo_addr_62_wd; + logic cfg_lp1_cmo_addr_62_we; + logic [31:0] cfg_lp1_cmo_addr_63_qs; + logic [31:0] cfg_lp1_cmo_addr_63_wd; + logic cfg_lp1_cmo_addr_63_we; + logic lp1_cmo_commit_0_qs; + logic lp1_cmo_commit_0_wd; + logic lp1_cmo_commit_0_we; + logic lp1_cmo_commit_1_qs; + logic lp1_cmo_commit_1_wd; + logic lp1_cmo_commit_1_we; + logic lp1_cmo_commit_2_qs; + logic lp1_cmo_commit_2_wd; + logic lp1_cmo_commit_2_we; + logic lp1_cmo_commit_3_qs; + logic lp1_cmo_commit_3_wd; + logic lp1_cmo_commit_3_we; + logic lp1_cmo_commit_4_qs; + logic lp1_cmo_commit_4_wd; + logic lp1_cmo_commit_4_we; + logic lp1_cmo_commit_5_qs; + logic lp1_cmo_commit_5_wd; + logic lp1_cmo_commit_5_we; + logic lp1_cmo_commit_6_qs; + logic lp1_cmo_commit_6_wd; + logic lp1_cmo_commit_6_we; + logic lp1_cmo_commit_7_qs; + logic lp1_cmo_commit_7_wd; + logic lp1_cmo_commit_7_we; + logic lp1_cmo_commit_8_qs; + logic lp1_cmo_commit_8_wd; + logic lp1_cmo_commit_8_we; + logic lp1_cmo_commit_9_qs; + logic lp1_cmo_commit_9_wd; + logic lp1_cmo_commit_9_we; + logic lp1_cmo_commit_10_qs; + logic lp1_cmo_commit_10_wd; + logic lp1_cmo_commit_10_we; + logic lp1_cmo_commit_11_qs; + logic lp1_cmo_commit_11_wd; + logic lp1_cmo_commit_11_we; + logic lp1_cmo_commit_12_qs; + logic lp1_cmo_commit_12_wd; + logic lp1_cmo_commit_12_we; + logic lp1_cmo_commit_13_qs; + logic lp1_cmo_commit_13_wd; + logic lp1_cmo_commit_13_we; + logic lp1_cmo_commit_14_qs; + logic lp1_cmo_commit_14_wd; + logic lp1_cmo_commit_14_we; + logic lp1_cmo_commit_15_qs; + logic lp1_cmo_commit_15_wd; + logic lp1_cmo_commit_15_we; + logic lp1_cmo_commit_16_qs; + logic lp1_cmo_commit_16_wd; + logic lp1_cmo_commit_16_we; + logic lp1_cmo_commit_17_qs; + logic lp1_cmo_commit_17_wd; + logic lp1_cmo_commit_17_we; + logic lp1_cmo_commit_18_qs; + logic lp1_cmo_commit_18_wd; + logic lp1_cmo_commit_18_we; + logic lp1_cmo_commit_19_qs; + logic lp1_cmo_commit_19_wd; + logic lp1_cmo_commit_19_we; + logic lp1_cmo_commit_20_qs; + logic lp1_cmo_commit_20_wd; + logic lp1_cmo_commit_20_we; + logic lp1_cmo_commit_21_qs; + logic lp1_cmo_commit_21_wd; + logic lp1_cmo_commit_21_we; + logic lp1_cmo_commit_22_qs; + logic lp1_cmo_commit_22_wd; + logic lp1_cmo_commit_22_we; + logic lp1_cmo_commit_23_qs; + logic lp1_cmo_commit_23_wd; + logic lp1_cmo_commit_23_we; + logic lp1_cmo_commit_24_qs; + logic lp1_cmo_commit_24_wd; + logic lp1_cmo_commit_24_we; + logic lp1_cmo_commit_25_qs; + logic lp1_cmo_commit_25_wd; + logic lp1_cmo_commit_25_we; + logic lp1_cmo_commit_26_qs; + logic lp1_cmo_commit_26_wd; + logic lp1_cmo_commit_26_we; + logic lp1_cmo_commit_27_qs; + logic lp1_cmo_commit_27_wd; + logic lp1_cmo_commit_27_we; + logic lp1_cmo_commit_28_qs; + logic lp1_cmo_commit_28_wd; + logic lp1_cmo_commit_28_we; + logic lp1_cmo_commit_29_qs; + logic lp1_cmo_commit_29_wd; + logic lp1_cmo_commit_29_we; + logic lp1_cmo_commit_30_qs; + logic lp1_cmo_commit_30_wd; + logic lp1_cmo_commit_30_we; + logic lp1_cmo_commit_31_qs; + logic lp1_cmo_commit_31_wd; + logic lp1_cmo_commit_31_we; + logic lp1_cmo_commit_32_qs; + logic lp1_cmo_commit_32_wd; + logic lp1_cmo_commit_32_we; + logic lp1_cmo_commit_33_qs; + logic lp1_cmo_commit_33_wd; + logic lp1_cmo_commit_33_we; + logic lp1_cmo_commit_34_qs; + logic lp1_cmo_commit_34_wd; + logic lp1_cmo_commit_34_we; + logic lp1_cmo_commit_35_qs; + logic lp1_cmo_commit_35_wd; + logic lp1_cmo_commit_35_we; + logic lp1_cmo_commit_36_qs; + logic lp1_cmo_commit_36_wd; + logic lp1_cmo_commit_36_we; + logic lp1_cmo_commit_37_qs; + logic lp1_cmo_commit_37_wd; + logic lp1_cmo_commit_37_we; + logic lp1_cmo_commit_38_qs; + logic lp1_cmo_commit_38_wd; + logic lp1_cmo_commit_38_we; + logic lp1_cmo_commit_39_qs; + logic lp1_cmo_commit_39_wd; + logic lp1_cmo_commit_39_we; + logic lp1_cmo_commit_40_qs; + logic lp1_cmo_commit_40_wd; + logic lp1_cmo_commit_40_we; + logic lp1_cmo_commit_41_qs; + logic lp1_cmo_commit_41_wd; + logic lp1_cmo_commit_41_we; + logic lp1_cmo_commit_42_qs; + logic lp1_cmo_commit_42_wd; + logic lp1_cmo_commit_42_we; + logic lp1_cmo_commit_43_qs; + logic lp1_cmo_commit_43_wd; + logic lp1_cmo_commit_43_we; + logic lp1_cmo_commit_44_qs; + logic lp1_cmo_commit_44_wd; + logic lp1_cmo_commit_44_we; + logic lp1_cmo_commit_45_qs; + logic lp1_cmo_commit_45_wd; + logic lp1_cmo_commit_45_we; + logic lp1_cmo_commit_46_qs; + logic lp1_cmo_commit_46_wd; + logic lp1_cmo_commit_46_we; + logic lp1_cmo_commit_47_qs; + logic lp1_cmo_commit_47_wd; + logic lp1_cmo_commit_47_we; + logic lp1_cmo_commit_48_qs; + logic lp1_cmo_commit_48_wd; + logic lp1_cmo_commit_48_we; + logic lp1_cmo_commit_49_qs; + logic lp1_cmo_commit_49_wd; + logic lp1_cmo_commit_49_we; + logic lp1_cmo_commit_50_qs; + logic lp1_cmo_commit_50_wd; + logic lp1_cmo_commit_50_we; + logic lp1_cmo_commit_51_qs; + logic lp1_cmo_commit_51_wd; + logic lp1_cmo_commit_51_we; + logic lp1_cmo_commit_52_qs; + logic lp1_cmo_commit_52_wd; + logic lp1_cmo_commit_52_we; + logic lp1_cmo_commit_53_qs; + logic lp1_cmo_commit_53_wd; + logic lp1_cmo_commit_53_we; + logic lp1_cmo_commit_54_qs; + logic lp1_cmo_commit_54_wd; + logic lp1_cmo_commit_54_we; + logic lp1_cmo_commit_55_qs; + logic lp1_cmo_commit_55_wd; + logic lp1_cmo_commit_55_we; + logic lp1_cmo_commit_56_qs; + logic lp1_cmo_commit_56_wd; + logic lp1_cmo_commit_56_we; + logic lp1_cmo_commit_57_qs; + logic lp1_cmo_commit_57_wd; + logic lp1_cmo_commit_57_we; + logic lp1_cmo_commit_58_qs; + logic lp1_cmo_commit_58_wd; + logic lp1_cmo_commit_58_we; + logic lp1_cmo_commit_59_qs; + logic lp1_cmo_commit_59_wd; + logic lp1_cmo_commit_59_we; + logic lp1_cmo_commit_60_qs; + logic lp1_cmo_commit_60_wd; + logic lp1_cmo_commit_60_we; + logic lp1_cmo_commit_61_qs; + logic lp1_cmo_commit_61_wd; + logic lp1_cmo_commit_61_we; + logic lp1_cmo_commit_62_qs; + logic lp1_cmo_commit_62_wd; + logic lp1_cmo_commit_62_we; + logic lp1_cmo_commit_63_qs; + logic lp1_cmo_commit_63_wd; + logic lp1_cmo_commit_63_we; + logic lp1_cmo_status_0_qs; + logic lp1_cmo_status_0_re; + logic lp1_cmo_status_1_qs; + logic lp1_cmo_status_1_re; + logic lp1_cmo_status_2_qs; + logic lp1_cmo_status_2_re; + logic lp1_cmo_status_3_qs; + logic lp1_cmo_status_3_re; + logic lp1_cmo_status_4_qs; + logic lp1_cmo_status_4_re; + logic lp1_cmo_status_5_qs; + logic lp1_cmo_status_5_re; + logic lp1_cmo_status_6_qs; + logic lp1_cmo_status_6_re; + logic lp1_cmo_status_7_qs; + logic lp1_cmo_status_7_re; + logic lp1_cmo_status_8_qs; + logic lp1_cmo_status_8_re; + logic lp1_cmo_status_9_qs; + logic lp1_cmo_status_9_re; + logic lp1_cmo_status_10_qs; + logic lp1_cmo_status_10_re; + logic lp1_cmo_status_11_qs; + logic lp1_cmo_status_11_re; + logic lp1_cmo_status_12_qs; + logic lp1_cmo_status_12_re; + logic lp1_cmo_status_13_qs; + logic lp1_cmo_status_13_re; + logic lp1_cmo_status_14_qs; + logic lp1_cmo_status_14_re; + logic lp1_cmo_status_15_qs; + logic lp1_cmo_status_15_re; + logic lp1_cmo_status_16_qs; + logic lp1_cmo_status_16_re; + logic lp1_cmo_status_17_qs; + logic lp1_cmo_status_17_re; + logic lp1_cmo_status_18_qs; + logic lp1_cmo_status_18_re; + logic lp1_cmo_status_19_qs; + logic lp1_cmo_status_19_re; + logic lp1_cmo_status_20_qs; + logic lp1_cmo_status_20_re; + logic lp1_cmo_status_21_qs; + logic lp1_cmo_status_21_re; + logic lp1_cmo_status_22_qs; + logic lp1_cmo_status_22_re; + logic lp1_cmo_status_23_qs; + logic lp1_cmo_status_23_re; + logic lp1_cmo_status_24_qs; + logic lp1_cmo_status_24_re; + logic lp1_cmo_status_25_qs; + logic lp1_cmo_status_25_re; + logic lp1_cmo_status_26_qs; + logic lp1_cmo_status_26_re; + logic lp1_cmo_status_27_qs; + logic lp1_cmo_status_27_re; + logic lp1_cmo_status_28_qs; + logic lp1_cmo_status_28_re; + logic lp1_cmo_status_29_qs; + logic lp1_cmo_status_29_re; + logic lp1_cmo_status_30_qs; + logic lp1_cmo_status_30_re; + logic lp1_cmo_status_31_qs; + logic lp1_cmo_status_31_re; + logic lp1_cmo_status_32_qs; + logic lp1_cmo_status_32_re; + logic lp1_cmo_status_33_qs; + logic lp1_cmo_status_33_re; + logic lp1_cmo_status_34_qs; + logic lp1_cmo_status_34_re; + logic lp1_cmo_status_35_qs; + logic lp1_cmo_status_35_re; + logic lp1_cmo_status_36_qs; + logic lp1_cmo_status_36_re; + logic lp1_cmo_status_37_qs; + logic lp1_cmo_status_37_re; + logic lp1_cmo_status_38_qs; + logic lp1_cmo_status_38_re; + logic lp1_cmo_status_39_qs; + logic lp1_cmo_status_39_re; + logic lp1_cmo_status_40_qs; + logic lp1_cmo_status_40_re; + logic lp1_cmo_status_41_qs; + logic lp1_cmo_status_41_re; + logic lp1_cmo_status_42_qs; + logic lp1_cmo_status_42_re; + logic lp1_cmo_status_43_qs; + logic lp1_cmo_status_43_re; + logic lp1_cmo_status_44_qs; + logic lp1_cmo_status_44_re; + logic lp1_cmo_status_45_qs; + logic lp1_cmo_status_45_re; + logic lp1_cmo_status_46_qs; + logic lp1_cmo_status_46_re; + logic lp1_cmo_status_47_qs; + logic lp1_cmo_status_47_re; + logic lp1_cmo_status_48_qs; + logic lp1_cmo_status_48_re; + logic lp1_cmo_status_49_qs; + logic lp1_cmo_status_49_re; + logic lp1_cmo_status_50_qs; + logic lp1_cmo_status_50_re; + logic lp1_cmo_status_51_qs; + logic lp1_cmo_status_51_re; + logic lp1_cmo_status_52_qs; + logic lp1_cmo_status_52_re; + logic lp1_cmo_status_53_qs; + logic lp1_cmo_status_53_re; + logic lp1_cmo_status_54_qs; + logic lp1_cmo_status_54_re; + logic lp1_cmo_status_55_qs; + logic lp1_cmo_status_55_re; + logic lp1_cmo_status_56_qs; + logic lp1_cmo_status_56_re; + logic lp1_cmo_status_57_qs; + logic lp1_cmo_status_57_re; + logic lp1_cmo_status_58_qs; + logic lp1_cmo_status_58_re; + logic lp1_cmo_status_59_qs; + logic lp1_cmo_status_59_re; + logic lp1_cmo_status_60_qs; + logic lp1_cmo_status_60_re; + logic lp1_cmo_status_61_qs; + logic lp1_cmo_status_61_re; + logic lp1_cmo_status_62_qs; + logic lp1_cmo_status_62_re; + logic lp1_cmo_status_63_qs; + logic lp1_cmo_status_63_re; // Register instances // R[hw_barrier]: V(True) @@ -555,172 +1259,8628 @@ module cachepool_peripheral_reg_top #( + // Subregister 0 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_0]: V(False) - logic [16:0] addr_hit; + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_0_we), + .wd (cfg_lp1_cmo_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[0].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_0_qs) + ); + + // Subregister 1 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_1]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_1_we), + .wd (cfg_lp1_cmo_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[1].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_1_qs) + ); + + // Subregister 2 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_2]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_2_we), + .wd (cfg_lp1_cmo_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[2].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_2_qs) + ); + + // Subregister 3 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_3]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_3_we), + .wd (cfg_lp1_cmo_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[3].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_3_qs) + ); + + // Subregister 4 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_4]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_4_we), + .wd (cfg_lp1_cmo_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[4].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_4_qs) + ); + + // Subregister 5 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_5]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_5_we), + .wd (cfg_lp1_cmo_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[5].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_5_qs) + ); + + // Subregister 6 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_6]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_6_we), + .wd (cfg_lp1_cmo_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[6].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_6_qs) + ); + + // Subregister 7 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_7]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_7_we), + .wd (cfg_lp1_cmo_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[7].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_7_qs) + ); + + // Subregister 8 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_8]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_8_we), + .wd (cfg_lp1_cmo_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[8].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_8_qs) + ); + + // Subregister 9 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_9]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_9_we), + .wd (cfg_lp1_cmo_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[9].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_9_qs) + ); + + // Subregister 10 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_10]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_10_we), + .wd (cfg_lp1_cmo_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[10].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_10_qs) + ); + + // Subregister 11 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_11]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_11_we), + .wd (cfg_lp1_cmo_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[11].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_11_qs) + ); + + // Subregister 12 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_12]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_12_we), + .wd (cfg_lp1_cmo_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[12].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_12_qs) + ); + + // Subregister 13 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_13]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_13_we), + .wd (cfg_lp1_cmo_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[13].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_13_qs) + ); + + // Subregister 14 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_14]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_14_we), + .wd (cfg_lp1_cmo_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[14].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_14_qs) + ); + + // Subregister 15 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_15]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_15_we), + .wd (cfg_lp1_cmo_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[15].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_15_qs) + ); + + // Subregister 16 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_16]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_16_we), + .wd (cfg_lp1_cmo_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[16].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_16_qs) + ); + + // Subregister 17 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_17]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_17_we), + .wd (cfg_lp1_cmo_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[17].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_17_qs) + ); + + // Subregister 18 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_18]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_18_we), + .wd (cfg_lp1_cmo_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[18].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_18_qs) + ); + + // Subregister 19 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_19]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_19_we), + .wd (cfg_lp1_cmo_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[19].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_19_qs) + ); + + // Subregister 20 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_20]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_20_we), + .wd (cfg_lp1_cmo_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[20].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_20_qs) + ); + + // Subregister 21 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_21]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_21_we), + .wd (cfg_lp1_cmo_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[21].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_21_qs) + ); + + // Subregister 22 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_22]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_22_we), + .wd (cfg_lp1_cmo_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[22].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_22_qs) + ); + + // Subregister 23 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_23]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_23_we), + .wd (cfg_lp1_cmo_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[23].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_23_qs) + ); + + // Subregister 24 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_24]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_24_we), + .wd (cfg_lp1_cmo_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[24].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_24_qs) + ); + + // Subregister 25 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_25]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_25_we), + .wd (cfg_lp1_cmo_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[25].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_25_qs) + ); + + // Subregister 26 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_26]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_26_we), + .wd (cfg_lp1_cmo_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[26].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_26_qs) + ); + + // Subregister 27 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_27]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_27_we), + .wd (cfg_lp1_cmo_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[27].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_27_qs) + ); + + // Subregister 28 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_28]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_28_we), + .wd (cfg_lp1_cmo_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[28].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_28_qs) + ); + + // Subregister 29 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_29]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_29_we), + .wd (cfg_lp1_cmo_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[29].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_29_qs) + ); + + // Subregister 30 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_30]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_30_we), + .wd (cfg_lp1_cmo_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[30].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_30_qs) + ); + + // Subregister 31 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_31]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_31_we), + .wd (cfg_lp1_cmo_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[31].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_31_qs) + ); + + // Subregister 32 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_32]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_32_we), + .wd (cfg_lp1_cmo_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[32].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_32_qs) + ); + + // Subregister 33 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_33]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_33_we), + .wd (cfg_lp1_cmo_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[33].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_33_qs) + ); + + // Subregister 34 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_34]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_34_we), + .wd (cfg_lp1_cmo_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[34].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_34_qs) + ); + + // Subregister 35 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_35]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_35 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_35_we), + .wd (cfg_lp1_cmo_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[35].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_35_qs) + ); + + // Subregister 36 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_36]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_36 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_36_we), + .wd (cfg_lp1_cmo_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[36].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_36_qs) + ); + + // Subregister 37 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_37]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_37 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_37_we), + .wd (cfg_lp1_cmo_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[37].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_37_qs) + ); + + // Subregister 38 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_38]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_38 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_38_we), + .wd (cfg_lp1_cmo_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[38].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_38_qs) + ); + + // Subregister 39 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_39]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_39 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_39_we), + .wd (cfg_lp1_cmo_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[39].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_39_qs) + ); + + // Subregister 40 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_40]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_40 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_40_we), + .wd (cfg_lp1_cmo_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[40].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_40_qs) + ); + + // Subregister 41 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_41]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_41 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_41_we), + .wd (cfg_lp1_cmo_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[41].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_41_qs) + ); + + // Subregister 42 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_42]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_42 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_42_we), + .wd (cfg_lp1_cmo_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[42].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_42_qs) + ); + + // Subregister 43 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_43]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_43 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_43_we), + .wd (cfg_lp1_cmo_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[43].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_43_qs) + ); + + // Subregister 44 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_44]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_44 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_44_we), + .wd (cfg_lp1_cmo_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[44].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_44_qs) + ); + + // Subregister 45 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_45]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_45 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_45_we), + .wd (cfg_lp1_cmo_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[45].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_45_qs) + ); + + // Subregister 46 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_46]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_46 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_46_we), + .wd (cfg_lp1_cmo_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[46].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_46_qs) + ); + + // Subregister 47 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_47]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_47 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_47_we), + .wd (cfg_lp1_cmo_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[47].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_47_qs) + ); + + // Subregister 48 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_48]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_48 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_48_we), + .wd (cfg_lp1_cmo_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[48].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_48_qs) + ); + + // Subregister 49 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_49]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_49 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_49_we), + .wd (cfg_lp1_cmo_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[49].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_49_qs) + ); + + // Subregister 50 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_50]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_50 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_50_we), + .wd (cfg_lp1_cmo_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[50].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_50_qs) + ); + + // Subregister 51 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_51]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_51 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_51_we), + .wd (cfg_lp1_cmo_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[51].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_51_qs) + ); + + // Subregister 52 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_52]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_52 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_52_we), + .wd (cfg_lp1_cmo_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[52].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_52_qs) + ); + + // Subregister 53 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_53]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_53 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_53_we), + .wd (cfg_lp1_cmo_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[53].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_53_qs) + ); + + // Subregister 54 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_54]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_54 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_54_we), + .wd (cfg_lp1_cmo_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[54].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_54_qs) + ); + + // Subregister 55 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_55]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_55 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_55_we), + .wd (cfg_lp1_cmo_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[55].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_55_qs) + ); + + // Subregister 56 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_56]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_56 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_56_we), + .wd (cfg_lp1_cmo_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[56].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_56_qs) + ); + + // Subregister 57 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_57]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_57 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_57_we), + .wd (cfg_lp1_cmo_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[57].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_57_qs) + ); + + // Subregister 58 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_58]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_58 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_58_we), + .wd (cfg_lp1_cmo_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[58].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_58_qs) + ); + + // Subregister 59 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_59]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_59 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_59_we), + .wd (cfg_lp1_cmo_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[59].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_59_qs) + ); + + // Subregister 60 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_60]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_60 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_60_we), + .wd (cfg_lp1_cmo_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[60].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_60_qs) + ); + + // Subregister 61 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_61]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_61 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_61_we), + .wd (cfg_lp1_cmo_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[61].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_61_qs) + ); + + // Subregister 62 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_62]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_62 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_62_we), + .wd (cfg_lp1_cmo_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[62].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_62_qs) + ); + + // Subregister 63 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_63]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_63 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_63_we), + .wd (cfg_lp1_cmo_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[63].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_63_qs) + ); + + + + // Subregister 0 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_0]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_0_we), + .wd (cfg_lp1_cmo_addr_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[0].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_0_qs) + ); + + // Subregister 1 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_1]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_1_we), + .wd (cfg_lp1_cmo_addr_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[1].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_1_qs) + ); + + // Subregister 2 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_2]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_2_we), + .wd (cfg_lp1_cmo_addr_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[2].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_2_qs) + ); + + // Subregister 3 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_3]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_3_we), + .wd (cfg_lp1_cmo_addr_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[3].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_3_qs) + ); + + // Subregister 4 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_4]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_4_we), + .wd (cfg_lp1_cmo_addr_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[4].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_4_qs) + ); + + // Subregister 5 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_5]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_5_we), + .wd (cfg_lp1_cmo_addr_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[5].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_5_qs) + ); + + // Subregister 6 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_6]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_6_we), + .wd (cfg_lp1_cmo_addr_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[6].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_6_qs) + ); + + // Subregister 7 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_7]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_7_we), + .wd (cfg_lp1_cmo_addr_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[7].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_7_qs) + ); + + // Subregister 8 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_8]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_8_we), + .wd (cfg_lp1_cmo_addr_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[8].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_8_qs) + ); + + // Subregister 9 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_9]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_9_we), + .wd (cfg_lp1_cmo_addr_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[9].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_9_qs) + ); + + // Subregister 10 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_10]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_10_we), + .wd (cfg_lp1_cmo_addr_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[10].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_10_qs) + ); + + // Subregister 11 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_11]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_11_we), + .wd (cfg_lp1_cmo_addr_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[11].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_11_qs) + ); + + // Subregister 12 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_12]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_12_we), + .wd (cfg_lp1_cmo_addr_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[12].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_12_qs) + ); + + // Subregister 13 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_13]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_13_we), + .wd (cfg_lp1_cmo_addr_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[13].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_13_qs) + ); + + // Subregister 14 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_14]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_14_we), + .wd (cfg_lp1_cmo_addr_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[14].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_14_qs) + ); + + // Subregister 15 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_15]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_15_we), + .wd (cfg_lp1_cmo_addr_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[15].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_15_qs) + ); + + // Subregister 16 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_16]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_16_we), + .wd (cfg_lp1_cmo_addr_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[16].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_16_qs) + ); + + // Subregister 17 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_17]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_17_we), + .wd (cfg_lp1_cmo_addr_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[17].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_17_qs) + ); + + // Subregister 18 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_18]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_18_we), + .wd (cfg_lp1_cmo_addr_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[18].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_18_qs) + ); + + // Subregister 19 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_19]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_19_we), + .wd (cfg_lp1_cmo_addr_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[19].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_19_qs) + ); + + // Subregister 20 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_20]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_20_we), + .wd (cfg_lp1_cmo_addr_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[20].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_20_qs) + ); + + // Subregister 21 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_21]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_21_we), + .wd (cfg_lp1_cmo_addr_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[21].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_21_qs) + ); + + // Subregister 22 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_22]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_22_we), + .wd (cfg_lp1_cmo_addr_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[22].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_22_qs) + ); + + // Subregister 23 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_23]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_23_we), + .wd (cfg_lp1_cmo_addr_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[23].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_23_qs) + ); + + // Subregister 24 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_24]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_24_we), + .wd (cfg_lp1_cmo_addr_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[24].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_24_qs) + ); + + // Subregister 25 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_25]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_25_we), + .wd (cfg_lp1_cmo_addr_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[25].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_25_qs) + ); + + // Subregister 26 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_26]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_26_we), + .wd (cfg_lp1_cmo_addr_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[26].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_26_qs) + ); + + // Subregister 27 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_27]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_27_we), + .wd (cfg_lp1_cmo_addr_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[27].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_27_qs) + ); + + // Subregister 28 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_28]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_28_we), + .wd (cfg_lp1_cmo_addr_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[28].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_28_qs) + ); + + // Subregister 29 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_29]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_29_we), + .wd (cfg_lp1_cmo_addr_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[29].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_29_qs) + ); + + // Subregister 30 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_30]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_30_we), + .wd (cfg_lp1_cmo_addr_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[30].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_30_qs) + ); + + // Subregister 31 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_31]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_31_we), + .wd (cfg_lp1_cmo_addr_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[31].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_31_qs) + ); + + // Subregister 32 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_32]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_32_we), + .wd (cfg_lp1_cmo_addr_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[32].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_32_qs) + ); + + // Subregister 33 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_33]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_33_we), + .wd (cfg_lp1_cmo_addr_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[33].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_33_qs) + ); + + // Subregister 34 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_34]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_34_we), + .wd (cfg_lp1_cmo_addr_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[34].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_34_qs) + ); + + // Subregister 35 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_35]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_35 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_35_we), + .wd (cfg_lp1_cmo_addr_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[35].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_35_qs) + ); + + // Subregister 36 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_36]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_36 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_36_we), + .wd (cfg_lp1_cmo_addr_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[36].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_36_qs) + ); + + // Subregister 37 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_37]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_37 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_37_we), + .wd (cfg_lp1_cmo_addr_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[37].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_37_qs) + ); + + // Subregister 38 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_38]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_38 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_38_we), + .wd (cfg_lp1_cmo_addr_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[38].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_38_qs) + ); + + // Subregister 39 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_39]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_39 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_39_we), + .wd (cfg_lp1_cmo_addr_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[39].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_39_qs) + ); + + // Subregister 40 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_40]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_40 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_40_we), + .wd (cfg_lp1_cmo_addr_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[40].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_40_qs) + ); + + // Subregister 41 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_41]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_41 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_41_we), + .wd (cfg_lp1_cmo_addr_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[41].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_41_qs) + ); + + // Subregister 42 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_42]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_42 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_42_we), + .wd (cfg_lp1_cmo_addr_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[42].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_42_qs) + ); + + // Subregister 43 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_43]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_43 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_43_we), + .wd (cfg_lp1_cmo_addr_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[43].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_43_qs) + ); + + // Subregister 44 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_44]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_44 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_44_we), + .wd (cfg_lp1_cmo_addr_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[44].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_44_qs) + ); + + // Subregister 45 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_45]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_45 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_45_we), + .wd (cfg_lp1_cmo_addr_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[45].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_45_qs) + ); + + // Subregister 46 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_46]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_46 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_46_we), + .wd (cfg_lp1_cmo_addr_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[46].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_46_qs) + ); + + // Subregister 47 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_47]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_47 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_47_we), + .wd (cfg_lp1_cmo_addr_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[47].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_47_qs) + ); + + // Subregister 48 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_48]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_48 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_48_we), + .wd (cfg_lp1_cmo_addr_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[48].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_48_qs) + ); + + // Subregister 49 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_49]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_49 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_49_we), + .wd (cfg_lp1_cmo_addr_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[49].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_49_qs) + ); + + // Subregister 50 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_50]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_50 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_50_we), + .wd (cfg_lp1_cmo_addr_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[50].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_50_qs) + ); + + // Subregister 51 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_51]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_51 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_51_we), + .wd (cfg_lp1_cmo_addr_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[51].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_51_qs) + ); + + // Subregister 52 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_52]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_52 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_52_we), + .wd (cfg_lp1_cmo_addr_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[52].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_52_qs) + ); + + // Subregister 53 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_53]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_53 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_53_we), + .wd (cfg_lp1_cmo_addr_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[53].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_53_qs) + ); + + // Subregister 54 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_54]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_54 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_54_we), + .wd (cfg_lp1_cmo_addr_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[54].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_54_qs) + ); + + // Subregister 55 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_55]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_55 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_55_we), + .wd (cfg_lp1_cmo_addr_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[55].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_55_qs) + ); + + // Subregister 56 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_56]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_56 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_56_we), + .wd (cfg_lp1_cmo_addr_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[56].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_56_qs) + ); + + // Subregister 57 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_57]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_57 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_57_we), + .wd (cfg_lp1_cmo_addr_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[57].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_57_qs) + ); + + // Subregister 58 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_58]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_58 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_58_we), + .wd (cfg_lp1_cmo_addr_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[58].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_58_qs) + ); + + // Subregister 59 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_59]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_59 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_59_we), + .wd (cfg_lp1_cmo_addr_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[59].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_59_qs) + ); + + // Subregister 60 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_60]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_60 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_60_we), + .wd (cfg_lp1_cmo_addr_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[60].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_60_qs) + ); + + // Subregister 61 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_61]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_61 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_61_we), + .wd (cfg_lp1_cmo_addr_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[61].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_61_qs) + ); + + // Subregister 62 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_62]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_62 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_62_we), + .wd (cfg_lp1_cmo_addr_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[62].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_62_qs) + ); + + // Subregister 63 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_63]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_63 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_63_we), + .wd (cfg_lp1_cmo_addr_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[63].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_63_qs) + ); + + + + // Subregister 0 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_0_we), + .wd (lp1_cmo_commit_0_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[0].de), + .d (hw2reg.lp1_cmo_commit[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[0].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_0_qs) + ); + + // Subregister 1 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_1_we), + .wd (lp1_cmo_commit_1_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[1].de), + .d (hw2reg.lp1_cmo_commit[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[1].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_1_qs) + ); + + // Subregister 2 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_2_we), + .wd (lp1_cmo_commit_2_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[2].de), + .d (hw2reg.lp1_cmo_commit[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[2].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_2_qs) + ); + + // Subregister 3 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_3_we), + .wd (lp1_cmo_commit_3_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[3].de), + .d (hw2reg.lp1_cmo_commit[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[3].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_3_qs) + ); + + // Subregister 4 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_4_we), + .wd (lp1_cmo_commit_4_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[4].de), + .d (hw2reg.lp1_cmo_commit[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[4].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_4_qs) + ); + + // Subregister 5 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_5_we), + .wd (lp1_cmo_commit_5_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[5].de), + .d (hw2reg.lp1_cmo_commit[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[5].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_5_qs) + ); + + // Subregister 6 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_6_we), + .wd (lp1_cmo_commit_6_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[6].de), + .d (hw2reg.lp1_cmo_commit[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[6].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_6_qs) + ); + + // Subregister 7 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_7_we), + .wd (lp1_cmo_commit_7_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[7].de), + .d (hw2reg.lp1_cmo_commit[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[7].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_7_qs) + ); + + // Subregister 8 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_8_we), + .wd (lp1_cmo_commit_8_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[8].de), + .d (hw2reg.lp1_cmo_commit[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[8].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_8_qs) + ); + + // Subregister 9 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_9_we), + .wd (lp1_cmo_commit_9_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[9].de), + .d (hw2reg.lp1_cmo_commit[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[9].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_9_qs) + ); + + // Subregister 10 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_10_we), + .wd (lp1_cmo_commit_10_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[10].de), + .d (hw2reg.lp1_cmo_commit[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[10].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_10_qs) + ); + + // Subregister 11 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_11_we), + .wd (lp1_cmo_commit_11_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[11].de), + .d (hw2reg.lp1_cmo_commit[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[11].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_11_qs) + ); + + // Subregister 12 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_12_we), + .wd (lp1_cmo_commit_12_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[12].de), + .d (hw2reg.lp1_cmo_commit[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[12].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_12_qs) + ); + + // Subregister 13 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_13_we), + .wd (lp1_cmo_commit_13_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[13].de), + .d (hw2reg.lp1_cmo_commit[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[13].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_13_qs) + ); + + // Subregister 14 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_14_we), + .wd (lp1_cmo_commit_14_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[14].de), + .d (hw2reg.lp1_cmo_commit[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[14].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_14_qs) + ); + + // Subregister 15 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_15]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_15_we), + .wd (lp1_cmo_commit_15_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[15].de), + .d (hw2reg.lp1_cmo_commit[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[15].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_15_qs) + ); + + // Subregister 16 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_16]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_16_we), + .wd (lp1_cmo_commit_16_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[16].de), + .d (hw2reg.lp1_cmo_commit[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[16].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_16_qs) + ); + + // Subregister 17 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_17]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_17_we), + .wd (lp1_cmo_commit_17_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[17].de), + .d (hw2reg.lp1_cmo_commit[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[17].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_17_qs) + ); + + // Subregister 18 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_18]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_18_we), + .wd (lp1_cmo_commit_18_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[18].de), + .d (hw2reg.lp1_cmo_commit[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[18].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_18_qs) + ); + + // Subregister 19 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_19]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_19_we), + .wd (lp1_cmo_commit_19_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[19].de), + .d (hw2reg.lp1_cmo_commit[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[19].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_19_qs) + ); + + // Subregister 20 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_20]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_20_we), + .wd (lp1_cmo_commit_20_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[20].de), + .d (hw2reg.lp1_cmo_commit[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[20].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_20_qs) + ); + + // Subregister 21 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_21]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_21_we), + .wd (lp1_cmo_commit_21_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[21].de), + .d (hw2reg.lp1_cmo_commit[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[21].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_21_qs) + ); + + // Subregister 22 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_22]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_22_we), + .wd (lp1_cmo_commit_22_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[22].de), + .d (hw2reg.lp1_cmo_commit[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[22].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_22_qs) + ); + + // Subregister 23 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_23]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_23_we), + .wd (lp1_cmo_commit_23_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[23].de), + .d (hw2reg.lp1_cmo_commit[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[23].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_23_qs) + ); + + // Subregister 24 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_24]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_24_we), + .wd (lp1_cmo_commit_24_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[24].de), + .d (hw2reg.lp1_cmo_commit[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[24].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_24_qs) + ); + + // Subregister 25 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_25]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_25_we), + .wd (lp1_cmo_commit_25_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[25].de), + .d (hw2reg.lp1_cmo_commit[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[25].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_25_qs) + ); + + // Subregister 26 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_26]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_26_we), + .wd (lp1_cmo_commit_26_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[26].de), + .d (hw2reg.lp1_cmo_commit[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[26].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_26_qs) + ); + + // Subregister 27 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_27]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_27_we), + .wd (lp1_cmo_commit_27_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[27].de), + .d (hw2reg.lp1_cmo_commit[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[27].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_27_qs) + ); + + // Subregister 28 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_28]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_28_we), + .wd (lp1_cmo_commit_28_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[28].de), + .d (hw2reg.lp1_cmo_commit[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[28].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_28_qs) + ); + + // Subregister 29 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_29]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_29_we), + .wd (lp1_cmo_commit_29_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[29].de), + .d (hw2reg.lp1_cmo_commit[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[29].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_29_qs) + ); + + // Subregister 30 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_30]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_30_we), + .wd (lp1_cmo_commit_30_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[30].de), + .d (hw2reg.lp1_cmo_commit[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[30].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_30_qs) + ); + + // Subregister 31 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_31]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_31_we), + .wd (lp1_cmo_commit_31_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[31].de), + .d (hw2reg.lp1_cmo_commit[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[31].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_31_qs) + ); + + // Subregister 32 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_32]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_32_we), + .wd (lp1_cmo_commit_32_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[32].de), + .d (hw2reg.lp1_cmo_commit[32].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[32].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_32_qs) + ); + + // Subregister 33 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_33]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_33_we), + .wd (lp1_cmo_commit_33_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[33].de), + .d (hw2reg.lp1_cmo_commit[33].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[33].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_33_qs) + ); + + // Subregister 34 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_34]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_34_we), + .wd (lp1_cmo_commit_34_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[34].de), + .d (hw2reg.lp1_cmo_commit[34].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[34].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_34_qs) + ); + + // Subregister 35 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_35]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_35 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_35_we), + .wd (lp1_cmo_commit_35_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[35].de), + .d (hw2reg.lp1_cmo_commit[35].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[35].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_35_qs) + ); + + // Subregister 36 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_36]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_36 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_36_we), + .wd (lp1_cmo_commit_36_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[36].de), + .d (hw2reg.lp1_cmo_commit[36].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[36].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_36_qs) + ); + + // Subregister 37 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_37]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_37 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_37_we), + .wd (lp1_cmo_commit_37_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[37].de), + .d (hw2reg.lp1_cmo_commit[37].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[37].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_37_qs) + ); + + // Subregister 38 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_38]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_38 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_38_we), + .wd (lp1_cmo_commit_38_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[38].de), + .d (hw2reg.lp1_cmo_commit[38].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[38].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_38_qs) + ); + + // Subregister 39 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_39]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_39 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_39_we), + .wd (lp1_cmo_commit_39_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[39].de), + .d (hw2reg.lp1_cmo_commit[39].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[39].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_39_qs) + ); + + // Subregister 40 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_40]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_40 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_40_we), + .wd (lp1_cmo_commit_40_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[40].de), + .d (hw2reg.lp1_cmo_commit[40].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[40].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_40_qs) + ); + + // Subregister 41 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_41]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_41 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_41_we), + .wd (lp1_cmo_commit_41_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[41].de), + .d (hw2reg.lp1_cmo_commit[41].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[41].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_41_qs) + ); + + // Subregister 42 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_42]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_42 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_42_we), + .wd (lp1_cmo_commit_42_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[42].de), + .d (hw2reg.lp1_cmo_commit[42].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[42].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_42_qs) + ); + + // Subregister 43 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_43]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_43 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_43_we), + .wd (lp1_cmo_commit_43_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[43].de), + .d (hw2reg.lp1_cmo_commit[43].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[43].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_43_qs) + ); + + // Subregister 44 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_44]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_44 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_44_we), + .wd (lp1_cmo_commit_44_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[44].de), + .d (hw2reg.lp1_cmo_commit[44].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[44].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_44_qs) + ); + + // Subregister 45 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_45]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_45 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_45_we), + .wd (lp1_cmo_commit_45_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[45].de), + .d (hw2reg.lp1_cmo_commit[45].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[45].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_45_qs) + ); + + // Subregister 46 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_46]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_46 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_46_we), + .wd (lp1_cmo_commit_46_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[46].de), + .d (hw2reg.lp1_cmo_commit[46].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[46].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_46_qs) + ); + + // Subregister 47 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_47]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_47 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_47_we), + .wd (lp1_cmo_commit_47_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[47].de), + .d (hw2reg.lp1_cmo_commit[47].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[47].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_47_qs) + ); + + // Subregister 48 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_48]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_48 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_48_we), + .wd (lp1_cmo_commit_48_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[48].de), + .d (hw2reg.lp1_cmo_commit[48].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[48].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_48_qs) + ); + + // Subregister 49 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_49]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_49 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_49_we), + .wd (lp1_cmo_commit_49_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[49].de), + .d (hw2reg.lp1_cmo_commit[49].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[49].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_49_qs) + ); + + // Subregister 50 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_50]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_50 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_50_we), + .wd (lp1_cmo_commit_50_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[50].de), + .d (hw2reg.lp1_cmo_commit[50].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[50].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_50_qs) + ); + + // Subregister 51 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_51]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_51 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_51_we), + .wd (lp1_cmo_commit_51_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[51].de), + .d (hw2reg.lp1_cmo_commit[51].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[51].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_51_qs) + ); + + // Subregister 52 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_52]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_52 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_52_we), + .wd (lp1_cmo_commit_52_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[52].de), + .d (hw2reg.lp1_cmo_commit[52].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[52].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_52_qs) + ); + + // Subregister 53 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_53]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_53 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_53_we), + .wd (lp1_cmo_commit_53_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[53].de), + .d (hw2reg.lp1_cmo_commit[53].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[53].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_53_qs) + ); + + // Subregister 54 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_54]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_54 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_54_we), + .wd (lp1_cmo_commit_54_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[54].de), + .d (hw2reg.lp1_cmo_commit[54].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[54].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_54_qs) + ); + + // Subregister 55 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_55]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_55 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_55_we), + .wd (lp1_cmo_commit_55_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[55].de), + .d (hw2reg.lp1_cmo_commit[55].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[55].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_55_qs) + ); + + // Subregister 56 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_56]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_56 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_56_we), + .wd (lp1_cmo_commit_56_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[56].de), + .d (hw2reg.lp1_cmo_commit[56].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[56].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_56_qs) + ); + + // Subregister 57 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_57]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_57 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_57_we), + .wd (lp1_cmo_commit_57_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[57].de), + .d (hw2reg.lp1_cmo_commit[57].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[57].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_57_qs) + ); + + // Subregister 58 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_58]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_58 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_58_we), + .wd (lp1_cmo_commit_58_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[58].de), + .d (hw2reg.lp1_cmo_commit[58].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[58].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_58_qs) + ); + + // Subregister 59 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_59]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_59 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_59_we), + .wd (lp1_cmo_commit_59_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[59].de), + .d (hw2reg.lp1_cmo_commit[59].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[59].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_59_qs) + ); + + // Subregister 60 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_60]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_60 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_60_we), + .wd (lp1_cmo_commit_60_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[60].de), + .d (hw2reg.lp1_cmo_commit[60].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[60].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_60_qs) + ); + + // Subregister 61 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_61]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_61 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_61_we), + .wd (lp1_cmo_commit_61_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[61].de), + .d (hw2reg.lp1_cmo_commit[61].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[61].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_61_qs) + ); + + // Subregister 62 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_62]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_62 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_62_we), + .wd (lp1_cmo_commit_62_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[62].de), + .d (hw2reg.lp1_cmo_commit[62].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[62].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_62_qs) + ); + + // Subregister 63 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_63]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_63 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_63_we), + .wd (lp1_cmo_commit_63_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[63].de), + .d (hw2reg.lp1_cmo_commit[63].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[63].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_63_qs) + ); + + + + // Subregister 0 of Multireg lp1_cmo_status + // R[lp1_cmo_status_0]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_0 ( + .re (lp1_cmo_status_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[0].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_0_qs) + ); + + // Subregister 1 of Multireg lp1_cmo_status + // R[lp1_cmo_status_1]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_1 ( + .re (lp1_cmo_status_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[1].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_1_qs) + ); + + // Subregister 2 of Multireg lp1_cmo_status + // R[lp1_cmo_status_2]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_2 ( + .re (lp1_cmo_status_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[2].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_2_qs) + ); + + // Subregister 3 of Multireg lp1_cmo_status + // R[lp1_cmo_status_3]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_3 ( + .re (lp1_cmo_status_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[3].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_3_qs) + ); + + // Subregister 4 of Multireg lp1_cmo_status + // R[lp1_cmo_status_4]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_4 ( + .re (lp1_cmo_status_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[4].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_4_qs) + ); + + // Subregister 5 of Multireg lp1_cmo_status + // R[lp1_cmo_status_5]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_5 ( + .re (lp1_cmo_status_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[5].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_5_qs) + ); + + // Subregister 6 of Multireg lp1_cmo_status + // R[lp1_cmo_status_6]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_6 ( + .re (lp1_cmo_status_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[6].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_6_qs) + ); + + // Subregister 7 of Multireg lp1_cmo_status + // R[lp1_cmo_status_7]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_7 ( + .re (lp1_cmo_status_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[7].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_7_qs) + ); + + // Subregister 8 of Multireg lp1_cmo_status + // R[lp1_cmo_status_8]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_8 ( + .re (lp1_cmo_status_8_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[8].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_8_qs) + ); + + // Subregister 9 of Multireg lp1_cmo_status + // R[lp1_cmo_status_9]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_9 ( + .re (lp1_cmo_status_9_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[9].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_9_qs) + ); + + // Subregister 10 of Multireg lp1_cmo_status + // R[lp1_cmo_status_10]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_10 ( + .re (lp1_cmo_status_10_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[10].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_10_qs) + ); + + // Subregister 11 of Multireg lp1_cmo_status + // R[lp1_cmo_status_11]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_11 ( + .re (lp1_cmo_status_11_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[11].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_11_qs) + ); + + // Subregister 12 of Multireg lp1_cmo_status + // R[lp1_cmo_status_12]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_12 ( + .re (lp1_cmo_status_12_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[12].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_12_qs) + ); + + // Subregister 13 of Multireg lp1_cmo_status + // R[lp1_cmo_status_13]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_13 ( + .re (lp1_cmo_status_13_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[13].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_13_qs) + ); + + // Subregister 14 of Multireg lp1_cmo_status + // R[lp1_cmo_status_14]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_14 ( + .re (lp1_cmo_status_14_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[14].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_14_qs) + ); + + // Subregister 15 of Multireg lp1_cmo_status + // R[lp1_cmo_status_15]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_15 ( + .re (lp1_cmo_status_15_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[15].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_15_qs) + ); + + // Subregister 16 of Multireg lp1_cmo_status + // R[lp1_cmo_status_16]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_16 ( + .re (lp1_cmo_status_16_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[16].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_16_qs) + ); + + // Subregister 17 of Multireg lp1_cmo_status + // R[lp1_cmo_status_17]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_17 ( + .re (lp1_cmo_status_17_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[17].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_17_qs) + ); + + // Subregister 18 of Multireg lp1_cmo_status + // R[lp1_cmo_status_18]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_18 ( + .re (lp1_cmo_status_18_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[18].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_18_qs) + ); + + // Subregister 19 of Multireg lp1_cmo_status + // R[lp1_cmo_status_19]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_19 ( + .re (lp1_cmo_status_19_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[19].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_19_qs) + ); + + // Subregister 20 of Multireg lp1_cmo_status + // R[lp1_cmo_status_20]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_20 ( + .re (lp1_cmo_status_20_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[20].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_20_qs) + ); + + // Subregister 21 of Multireg lp1_cmo_status + // R[lp1_cmo_status_21]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_21 ( + .re (lp1_cmo_status_21_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[21].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_21_qs) + ); + + // Subregister 22 of Multireg lp1_cmo_status + // R[lp1_cmo_status_22]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_22 ( + .re (lp1_cmo_status_22_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[22].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_22_qs) + ); + + // Subregister 23 of Multireg lp1_cmo_status + // R[lp1_cmo_status_23]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_23 ( + .re (lp1_cmo_status_23_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[23].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_23_qs) + ); + + // Subregister 24 of Multireg lp1_cmo_status + // R[lp1_cmo_status_24]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_24 ( + .re (lp1_cmo_status_24_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[24].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_24_qs) + ); + + // Subregister 25 of Multireg lp1_cmo_status + // R[lp1_cmo_status_25]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_25 ( + .re (lp1_cmo_status_25_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[25].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_25_qs) + ); + + // Subregister 26 of Multireg lp1_cmo_status + // R[lp1_cmo_status_26]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_26 ( + .re (lp1_cmo_status_26_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[26].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_26_qs) + ); + + // Subregister 27 of Multireg lp1_cmo_status + // R[lp1_cmo_status_27]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_27 ( + .re (lp1_cmo_status_27_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[27].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_27_qs) + ); + + // Subregister 28 of Multireg lp1_cmo_status + // R[lp1_cmo_status_28]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_28 ( + .re (lp1_cmo_status_28_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[28].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_28_qs) + ); + + // Subregister 29 of Multireg lp1_cmo_status + // R[lp1_cmo_status_29]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_29 ( + .re (lp1_cmo_status_29_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[29].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_29_qs) + ); + + // Subregister 30 of Multireg lp1_cmo_status + // R[lp1_cmo_status_30]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_30 ( + .re (lp1_cmo_status_30_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[30].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_30_qs) + ); + + // Subregister 31 of Multireg lp1_cmo_status + // R[lp1_cmo_status_31]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_31 ( + .re (lp1_cmo_status_31_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[31].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_31_qs) + ); + + // Subregister 32 of Multireg lp1_cmo_status + // R[lp1_cmo_status_32]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_32 ( + .re (lp1_cmo_status_32_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[32].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_32_qs) + ); + + // Subregister 33 of Multireg lp1_cmo_status + // R[lp1_cmo_status_33]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_33 ( + .re (lp1_cmo_status_33_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[33].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_33_qs) + ); + + // Subregister 34 of Multireg lp1_cmo_status + // R[lp1_cmo_status_34]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_34 ( + .re (lp1_cmo_status_34_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[34].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_34_qs) + ); + + // Subregister 35 of Multireg lp1_cmo_status + // R[lp1_cmo_status_35]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_35 ( + .re (lp1_cmo_status_35_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[35].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_35_qs) + ); + + // Subregister 36 of Multireg lp1_cmo_status + // R[lp1_cmo_status_36]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_36 ( + .re (lp1_cmo_status_36_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[36].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_36_qs) + ); + + // Subregister 37 of Multireg lp1_cmo_status + // R[lp1_cmo_status_37]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_37 ( + .re (lp1_cmo_status_37_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[37].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_37_qs) + ); + + // Subregister 38 of Multireg lp1_cmo_status + // R[lp1_cmo_status_38]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_38 ( + .re (lp1_cmo_status_38_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[38].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_38_qs) + ); + + // Subregister 39 of Multireg lp1_cmo_status + // R[lp1_cmo_status_39]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_39 ( + .re (lp1_cmo_status_39_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[39].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_39_qs) + ); + + // Subregister 40 of Multireg lp1_cmo_status + // R[lp1_cmo_status_40]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_40 ( + .re (lp1_cmo_status_40_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[40].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_40_qs) + ); + + // Subregister 41 of Multireg lp1_cmo_status + // R[lp1_cmo_status_41]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_41 ( + .re (lp1_cmo_status_41_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[41].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_41_qs) + ); + + // Subregister 42 of Multireg lp1_cmo_status + // R[lp1_cmo_status_42]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_42 ( + .re (lp1_cmo_status_42_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[42].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_42_qs) + ); + + // Subregister 43 of Multireg lp1_cmo_status + // R[lp1_cmo_status_43]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_43 ( + .re (lp1_cmo_status_43_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[43].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_43_qs) + ); + + // Subregister 44 of Multireg lp1_cmo_status + // R[lp1_cmo_status_44]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_44 ( + .re (lp1_cmo_status_44_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[44].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_44_qs) + ); + + // Subregister 45 of Multireg lp1_cmo_status + // R[lp1_cmo_status_45]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_45 ( + .re (lp1_cmo_status_45_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[45].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_45_qs) + ); + + // Subregister 46 of Multireg lp1_cmo_status + // R[lp1_cmo_status_46]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_46 ( + .re (lp1_cmo_status_46_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[46].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_46_qs) + ); + + // Subregister 47 of Multireg lp1_cmo_status + // R[lp1_cmo_status_47]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_47 ( + .re (lp1_cmo_status_47_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[47].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_47_qs) + ); + + // Subregister 48 of Multireg lp1_cmo_status + // R[lp1_cmo_status_48]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_48 ( + .re (lp1_cmo_status_48_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[48].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_48_qs) + ); + + // Subregister 49 of Multireg lp1_cmo_status + // R[lp1_cmo_status_49]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_49 ( + .re (lp1_cmo_status_49_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[49].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_49_qs) + ); + + // Subregister 50 of Multireg lp1_cmo_status + // R[lp1_cmo_status_50]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_50 ( + .re (lp1_cmo_status_50_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[50].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_50_qs) + ); + + // Subregister 51 of Multireg lp1_cmo_status + // R[lp1_cmo_status_51]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_51 ( + .re (lp1_cmo_status_51_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[51].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_51_qs) + ); + + // Subregister 52 of Multireg lp1_cmo_status + // R[lp1_cmo_status_52]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_52 ( + .re (lp1_cmo_status_52_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[52].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_52_qs) + ); + + // Subregister 53 of Multireg lp1_cmo_status + // R[lp1_cmo_status_53]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_53 ( + .re (lp1_cmo_status_53_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[53].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_53_qs) + ); + + // Subregister 54 of Multireg lp1_cmo_status + // R[lp1_cmo_status_54]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_54 ( + .re (lp1_cmo_status_54_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[54].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_54_qs) + ); + + // Subregister 55 of Multireg lp1_cmo_status + // R[lp1_cmo_status_55]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_55 ( + .re (lp1_cmo_status_55_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[55].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_55_qs) + ); + + // Subregister 56 of Multireg lp1_cmo_status + // R[lp1_cmo_status_56]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_56 ( + .re (lp1_cmo_status_56_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[56].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_56_qs) + ); + + // Subregister 57 of Multireg lp1_cmo_status + // R[lp1_cmo_status_57]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_57 ( + .re (lp1_cmo_status_57_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[57].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_57_qs) + ); + + // Subregister 58 of Multireg lp1_cmo_status + // R[lp1_cmo_status_58]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_58 ( + .re (lp1_cmo_status_58_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[58].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_58_qs) + ); + + // Subregister 59 of Multireg lp1_cmo_status + // R[lp1_cmo_status_59]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_59 ( + .re (lp1_cmo_status_59_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[59].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_59_qs) + ); + + // Subregister 60 of Multireg lp1_cmo_status + // R[lp1_cmo_status_60]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_60 ( + .re (lp1_cmo_status_60_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[60].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_60_qs) + ); + + // Subregister 61 of Multireg lp1_cmo_status + // R[lp1_cmo_status_61]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_61 ( + .re (lp1_cmo_status_61_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[61].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_61_qs) + ); + + // Subregister 62 of Multireg lp1_cmo_status + // R[lp1_cmo_status_62]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_62 ( + .re (lp1_cmo_status_62_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[62].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_62_qs) + ); + + // Subregister 63 of Multireg lp1_cmo_status + // R[lp1_cmo_status_63]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_63 ( + .re (lp1_cmo_status_63_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[63].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_63_qs) + ); + + + + + logic [272:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET); + addr_hit[ 1] = (reg_addr == CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET); + addr_hit[ 3] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET); + addr_hit[ 4] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET); + addr_hit[ 5] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET); + addr_hit[ 6] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET); + addr_hit[ 7] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET); + addr_hit[ 8] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_OFFSET); + addr_hit[ 9] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_OFFSET); + addr_hit[ 10] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET); + addr_hit[ 11] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET); + addr_hit[ 12] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET); + addr_hit[ 13] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET); + addr_hit[ 14] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET); + addr_hit[ 15] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET); + addr_hit[ 16] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET); + addr_hit[ 17] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_OFFSET); + addr_hit[ 18] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_OFFSET); + addr_hit[ 19] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_OFFSET); + addr_hit[ 20] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_OFFSET); + addr_hit[ 21] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_OFFSET); + addr_hit[ 22] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_OFFSET); + addr_hit[ 23] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_OFFSET); + addr_hit[ 24] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_OFFSET); + addr_hit[ 25] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_OFFSET); + addr_hit[ 26] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_OFFSET); + addr_hit[ 27] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_OFFSET); + addr_hit[ 28] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_OFFSET); + addr_hit[ 29] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_OFFSET); + addr_hit[ 30] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_OFFSET); + addr_hit[ 31] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_OFFSET); + addr_hit[ 32] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_OFFSET); + addr_hit[ 33] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_OFFSET); + addr_hit[ 34] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_OFFSET); + addr_hit[ 35] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_OFFSET); + addr_hit[ 36] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_OFFSET); + addr_hit[ 37] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_OFFSET); + addr_hit[ 38] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_OFFSET); + addr_hit[ 39] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_OFFSET); + addr_hit[ 40] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_OFFSET); + addr_hit[ 41] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_OFFSET); + addr_hit[ 42] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_OFFSET); + addr_hit[ 43] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_OFFSET); + addr_hit[ 44] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_OFFSET); + addr_hit[ 45] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_OFFSET); + addr_hit[ 46] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_OFFSET); + addr_hit[ 47] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_OFFSET); + addr_hit[ 48] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_OFFSET); + addr_hit[ 49] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_OFFSET); + addr_hit[ 50] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_OFFSET); + addr_hit[ 51] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_OFFSET); + addr_hit[ 52] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_OFFSET); + addr_hit[ 53] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_OFFSET); + addr_hit[ 54] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_OFFSET); + addr_hit[ 55] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_OFFSET); + addr_hit[ 56] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_OFFSET); + addr_hit[ 57] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_OFFSET); + addr_hit[ 58] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_OFFSET); + addr_hit[ 59] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_OFFSET); + addr_hit[ 60] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_OFFSET); + addr_hit[ 61] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_OFFSET); + addr_hit[ 62] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_OFFSET); + addr_hit[ 63] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_OFFSET); + addr_hit[ 64] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_OFFSET); + addr_hit[ 65] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_OFFSET); + addr_hit[ 66] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_OFFSET); + addr_hit[ 67] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_OFFSET); + addr_hit[ 68] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_OFFSET); + addr_hit[ 69] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_OFFSET); + addr_hit[ 70] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_OFFSET); + addr_hit[ 71] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_OFFSET); + addr_hit[ 72] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_OFFSET); + addr_hit[ 73] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_OFFSET); + addr_hit[ 74] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_OFFSET); + addr_hit[ 75] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_OFFSET); + addr_hit[ 76] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_OFFSET); + addr_hit[ 77] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_OFFSET); + addr_hit[ 78] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_OFFSET); + addr_hit[ 79] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_OFFSET); + addr_hit[ 80] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OFFSET); + addr_hit[ 81] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0_OFFSET); + addr_hit[ 82] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1_OFFSET); + addr_hit[ 83] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2_OFFSET); + addr_hit[ 84] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3_OFFSET); + addr_hit[ 85] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4_OFFSET); + addr_hit[ 86] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5_OFFSET); + addr_hit[ 87] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6_OFFSET); + addr_hit[ 88] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7_OFFSET); + addr_hit[ 89] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8_OFFSET); + addr_hit[ 90] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9_OFFSET); + addr_hit[ 91] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10_OFFSET); + addr_hit[ 92] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11_OFFSET); + addr_hit[ 93] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12_OFFSET); + addr_hit[ 94] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13_OFFSET); + addr_hit[ 95] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14_OFFSET); + addr_hit[ 96] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15_OFFSET); + addr_hit[ 97] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16_OFFSET); + addr_hit[ 98] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17_OFFSET); + addr_hit[ 99] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18_OFFSET); + addr_hit[100] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19_OFFSET); + addr_hit[101] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20_OFFSET); + addr_hit[102] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21_OFFSET); + addr_hit[103] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22_OFFSET); + addr_hit[104] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23_OFFSET); + addr_hit[105] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24_OFFSET); + addr_hit[106] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25_OFFSET); + addr_hit[107] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26_OFFSET); + addr_hit[108] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27_OFFSET); + addr_hit[109] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28_OFFSET); + addr_hit[110] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29_OFFSET); + addr_hit[111] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30_OFFSET); + addr_hit[112] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31_OFFSET); + addr_hit[113] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32_OFFSET); + addr_hit[114] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33_OFFSET); + addr_hit[115] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34_OFFSET); + addr_hit[116] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35_OFFSET); + addr_hit[117] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36_OFFSET); + addr_hit[118] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37_OFFSET); + addr_hit[119] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38_OFFSET); + addr_hit[120] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39_OFFSET); + addr_hit[121] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40_OFFSET); + addr_hit[122] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41_OFFSET); + addr_hit[123] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42_OFFSET); + addr_hit[124] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43_OFFSET); + addr_hit[125] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44_OFFSET); + addr_hit[126] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45_OFFSET); + addr_hit[127] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46_OFFSET); + addr_hit[128] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47_OFFSET); + addr_hit[129] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48_OFFSET); + addr_hit[130] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49_OFFSET); + addr_hit[131] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50_OFFSET); + addr_hit[132] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51_OFFSET); + addr_hit[133] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52_OFFSET); + addr_hit[134] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53_OFFSET); + addr_hit[135] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54_OFFSET); + addr_hit[136] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55_OFFSET); + addr_hit[137] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56_OFFSET); + addr_hit[138] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57_OFFSET); + addr_hit[139] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58_OFFSET); + addr_hit[140] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59_OFFSET); + addr_hit[141] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60_OFFSET); + addr_hit[142] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61_OFFSET); + addr_hit[143] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62_OFFSET); + addr_hit[144] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63_OFFSET); + addr_hit[145] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_OFFSET); + addr_hit[146] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_OFFSET); + addr_hit[147] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_OFFSET); + addr_hit[148] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_OFFSET); + addr_hit[149] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_OFFSET); + addr_hit[150] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_OFFSET); + addr_hit[151] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_OFFSET); + addr_hit[152] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_OFFSET); + addr_hit[153] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_OFFSET); + addr_hit[154] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_OFFSET); + addr_hit[155] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_OFFSET); + addr_hit[156] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_OFFSET); + addr_hit[157] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_OFFSET); + addr_hit[158] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_OFFSET); + addr_hit[159] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_OFFSET); + addr_hit[160] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_OFFSET); + addr_hit[161] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_OFFSET); + addr_hit[162] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_OFFSET); + addr_hit[163] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_OFFSET); + addr_hit[164] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_OFFSET); + addr_hit[165] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_OFFSET); + addr_hit[166] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_OFFSET); + addr_hit[167] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_OFFSET); + addr_hit[168] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_OFFSET); + addr_hit[169] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_OFFSET); + addr_hit[170] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_OFFSET); + addr_hit[171] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_OFFSET); + addr_hit[172] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_OFFSET); + addr_hit[173] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_OFFSET); + addr_hit[174] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_OFFSET); + addr_hit[175] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_OFFSET); + addr_hit[176] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_OFFSET); + addr_hit[177] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_OFFSET); + addr_hit[178] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_OFFSET); + addr_hit[179] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_OFFSET); + addr_hit[180] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_OFFSET); + addr_hit[181] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_OFFSET); + addr_hit[182] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_OFFSET); + addr_hit[183] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_OFFSET); + addr_hit[184] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_OFFSET); + addr_hit[185] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_OFFSET); + addr_hit[186] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_OFFSET); + addr_hit[187] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_OFFSET); + addr_hit[188] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_OFFSET); + addr_hit[189] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_OFFSET); + addr_hit[190] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_OFFSET); + addr_hit[191] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_OFFSET); + addr_hit[192] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_OFFSET); + addr_hit[193] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_OFFSET); + addr_hit[194] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_OFFSET); + addr_hit[195] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_OFFSET); + addr_hit[196] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_OFFSET); + addr_hit[197] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_OFFSET); + addr_hit[198] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_OFFSET); + addr_hit[199] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_OFFSET); + addr_hit[200] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_OFFSET); + addr_hit[201] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_OFFSET); + addr_hit[202] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_OFFSET); + addr_hit[203] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_OFFSET); + addr_hit[204] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_OFFSET); + addr_hit[205] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_OFFSET); + addr_hit[206] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_OFFSET); + addr_hit[207] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_OFFSET); + addr_hit[208] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_OFFSET); + addr_hit[209] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_OFFSET); + addr_hit[210] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_OFFSET); + addr_hit[211] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_OFFSET); + addr_hit[212] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_OFFSET); + addr_hit[213] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_OFFSET); + addr_hit[214] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_OFFSET); + addr_hit[215] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_OFFSET); + addr_hit[216] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_OFFSET); + addr_hit[217] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_OFFSET); + addr_hit[218] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_OFFSET); + addr_hit[219] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_OFFSET); + addr_hit[220] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_OFFSET); + addr_hit[221] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_OFFSET); + addr_hit[222] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_OFFSET); + addr_hit[223] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_OFFSET); + addr_hit[224] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_OFFSET); + addr_hit[225] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_OFFSET); + addr_hit[226] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_OFFSET); + addr_hit[227] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_OFFSET); + addr_hit[228] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_OFFSET); + addr_hit[229] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_OFFSET); + addr_hit[230] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_OFFSET); + addr_hit[231] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_OFFSET); + addr_hit[232] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_OFFSET); + addr_hit[233] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_OFFSET); + addr_hit[234] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_OFFSET); + addr_hit[235] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_OFFSET); + addr_hit[236] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_OFFSET); + addr_hit[237] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_OFFSET); + addr_hit[238] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_OFFSET); + addr_hit[239] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_OFFSET); + addr_hit[240] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_OFFSET); + addr_hit[241] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_OFFSET); + addr_hit[242] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_OFFSET); + addr_hit[243] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_OFFSET); + addr_hit[244] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_OFFSET); + addr_hit[245] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_OFFSET); + addr_hit[246] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_OFFSET); + addr_hit[247] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_OFFSET); + addr_hit[248] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_OFFSET); + addr_hit[249] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_OFFSET); + addr_hit[250] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_OFFSET); + addr_hit[251] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_OFFSET); + addr_hit[252] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_OFFSET); + addr_hit[253] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_OFFSET); + addr_hit[254] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_OFFSET); + addr_hit[255] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_OFFSET); + addr_hit[256] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_OFFSET); + addr_hit[257] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_OFFSET); + addr_hit[258] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_OFFSET); + addr_hit[259] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_OFFSET); + addr_hit[260] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_OFFSET); + addr_hit[261] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_OFFSET); + addr_hit[262] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_OFFSET); + addr_hit[263] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_OFFSET); + addr_hit[264] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_OFFSET); + addr_hit[265] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_OFFSET); + addr_hit[266] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_OFFSET); + addr_hit[267] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_OFFSET); + addr_hit[268] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_OFFSET); + addr_hit[269] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_OFFSET); + addr_hit[270] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_OFFSET); + addr_hit[271] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_OFFSET); + addr_hit[272] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 9] & ~reg_be))) | + (addr_hit[ 10] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 10] & ~reg_be))) | + (addr_hit[ 11] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 11] & ~reg_be))) | + (addr_hit[ 12] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 12] & ~reg_be))) | + (addr_hit[ 13] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 13] & ~reg_be))) | + (addr_hit[ 14] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 14] & ~reg_be))) | + (addr_hit[ 15] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 15] & ~reg_be))) | + (addr_hit[ 16] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 16] & ~reg_be))) | + (addr_hit[ 17] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 17] & ~reg_be))) | + (addr_hit[ 18] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 18] & ~reg_be))) | + (addr_hit[ 19] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 19] & ~reg_be))) | + (addr_hit[ 20] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 20] & ~reg_be))) | + (addr_hit[ 21] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 21] & ~reg_be))) | + (addr_hit[ 22] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 22] & ~reg_be))) | + (addr_hit[ 23] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 23] & ~reg_be))) | + (addr_hit[ 24] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 24] & ~reg_be))) | + (addr_hit[ 25] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 25] & ~reg_be))) | + (addr_hit[ 26] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 26] & ~reg_be))) | + (addr_hit[ 27] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 27] & ~reg_be))) | + (addr_hit[ 28] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 28] & ~reg_be))) | + (addr_hit[ 29] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 29] & ~reg_be))) | + (addr_hit[ 30] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 30] & ~reg_be))) | + (addr_hit[ 31] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 31] & ~reg_be))) | + (addr_hit[ 32] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 32] & ~reg_be))) | + (addr_hit[ 33] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 33] & ~reg_be))) | + (addr_hit[ 34] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 34] & ~reg_be))) | + (addr_hit[ 35] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 35] & ~reg_be))) | + (addr_hit[ 36] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 36] & ~reg_be))) | + (addr_hit[ 37] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 37] & ~reg_be))) | + (addr_hit[ 38] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 38] & ~reg_be))) | + (addr_hit[ 39] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 39] & ~reg_be))) | + (addr_hit[ 40] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 40] & ~reg_be))) | + (addr_hit[ 41] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 41] & ~reg_be))) | + (addr_hit[ 42] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 42] & ~reg_be))) | + (addr_hit[ 43] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 43] & ~reg_be))) | + (addr_hit[ 44] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 44] & ~reg_be))) | + (addr_hit[ 45] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 45] & ~reg_be))) | + (addr_hit[ 46] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 46] & ~reg_be))) | + (addr_hit[ 47] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 47] & ~reg_be))) | + (addr_hit[ 48] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 48] & ~reg_be))) | + (addr_hit[ 49] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 49] & ~reg_be))) | + (addr_hit[ 50] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 50] & ~reg_be))) | + (addr_hit[ 51] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 51] & ~reg_be))) | + (addr_hit[ 52] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 52] & ~reg_be))) | + (addr_hit[ 53] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 53] & ~reg_be))) | + (addr_hit[ 54] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 54] & ~reg_be))) | + (addr_hit[ 55] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 55] & ~reg_be))) | + (addr_hit[ 56] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 56] & ~reg_be))) | + (addr_hit[ 57] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 57] & ~reg_be))) | + (addr_hit[ 58] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 58] & ~reg_be))) | + (addr_hit[ 59] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 59] & ~reg_be))) | + (addr_hit[ 60] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 60] & ~reg_be))) | + (addr_hit[ 61] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 61] & ~reg_be))) | + (addr_hit[ 62] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 62] & ~reg_be))) | + (addr_hit[ 63] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 63] & ~reg_be))) | + (addr_hit[ 64] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 64] & ~reg_be))) | + (addr_hit[ 65] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 65] & ~reg_be))) | + (addr_hit[ 66] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 66] & ~reg_be))) | + (addr_hit[ 67] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 67] & ~reg_be))) | + (addr_hit[ 68] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 68] & ~reg_be))) | + (addr_hit[ 69] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 69] & ~reg_be))) | + (addr_hit[ 70] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 70] & ~reg_be))) | + (addr_hit[ 71] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 71] & ~reg_be))) | + (addr_hit[ 72] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 72] & ~reg_be))) | + (addr_hit[ 73] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 73] & ~reg_be))) | + (addr_hit[ 74] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 74] & ~reg_be))) | + (addr_hit[ 75] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 75] & ~reg_be))) | + (addr_hit[ 76] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 76] & ~reg_be))) | + (addr_hit[ 77] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 77] & ~reg_be))) | + (addr_hit[ 78] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 78] & ~reg_be))) | + (addr_hit[ 79] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 79] & ~reg_be))) | + (addr_hit[ 80] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 80] & ~reg_be))) | + (addr_hit[ 81] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 81] & ~reg_be))) | + (addr_hit[ 82] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 82] & ~reg_be))) | + (addr_hit[ 83] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 83] & ~reg_be))) | + (addr_hit[ 84] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 84] & ~reg_be))) | + (addr_hit[ 85] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 85] & ~reg_be))) | + (addr_hit[ 86] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 86] & ~reg_be))) | + (addr_hit[ 87] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 87] & ~reg_be))) | + (addr_hit[ 88] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 88] & ~reg_be))) | + (addr_hit[ 89] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 89] & ~reg_be))) | + (addr_hit[ 90] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 90] & ~reg_be))) | + (addr_hit[ 91] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 91] & ~reg_be))) | + (addr_hit[ 92] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 92] & ~reg_be))) | + (addr_hit[ 93] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 93] & ~reg_be))) | + (addr_hit[ 94] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 94] & ~reg_be))) | + (addr_hit[ 95] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 95] & ~reg_be))) | + (addr_hit[ 96] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 96] & ~reg_be))) | + (addr_hit[ 97] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 97] & ~reg_be))) | + (addr_hit[ 98] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 98] & ~reg_be))) | + (addr_hit[ 99] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 99] & ~reg_be))) | + (addr_hit[100] & (|(CACHEPOOL_PERIPHERAL_PERMIT[100] & ~reg_be))) | + (addr_hit[101] & (|(CACHEPOOL_PERIPHERAL_PERMIT[101] & ~reg_be))) | + (addr_hit[102] & (|(CACHEPOOL_PERIPHERAL_PERMIT[102] & ~reg_be))) | + (addr_hit[103] & (|(CACHEPOOL_PERIPHERAL_PERMIT[103] & ~reg_be))) | + (addr_hit[104] & (|(CACHEPOOL_PERIPHERAL_PERMIT[104] & ~reg_be))) | + (addr_hit[105] & (|(CACHEPOOL_PERIPHERAL_PERMIT[105] & ~reg_be))) | + (addr_hit[106] & (|(CACHEPOOL_PERIPHERAL_PERMIT[106] & ~reg_be))) | + (addr_hit[107] & (|(CACHEPOOL_PERIPHERAL_PERMIT[107] & ~reg_be))) | + (addr_hit[108] & (|(CACHEPOOL_PERIPHERAL_PERMIT[108] & ~reg_be))) | + (addr_hit[109] & (|(CACHEPOOL_PERIPHERAL_PERMIT[109] & ~reg_be))) | + (addr_hit[110] & (|(CACHEPOOL_PERIPHERAL_PERMIT[110] & ~reg_be))) | + (addr_hit[111] & (|(CACHEPOOL_PERIPHERAL_PERMIT[111] & ~reg_be))) | + (addr_hit[112] & (|(CACHEPOOL_PERIPHERAL_PERMIT[112] & ~reg_be))) | + (addr_hit[113] & (|(CACHEPOOL_PERIPHERAL_PERMIT[113] & ~reg_be))) | + (addr_hit[114] & (|(CACHEPOOL_PERIPHERAL_PERMIT[114] & ~reg_be))) | + (addr_hit[115] & (|(CACHEPOOL_PERIPHERAL_PERMIT[115] & ~reg_be))) | + (addr_hit[116] & (|(CACHEPOOL_PERIPHERAL_PERMIT[116] & ~reg_be))) | + (addr_hit[117] & (|(CACHEPOOL_PERIPHERAL_PERMIT[117] & ~reg_be))) | + (addr_hit[118] & (|(CACHEPOOL_PERIPHERAL_PERMIT[118] & ~reg_be))) | + (addr_hit[119] & (|(CACHEPOOL_PERIPHERAL_PERMIT[119] & ~reg_be))) | + (addr_hit[120] & (|(CACHEPOOL_PERIPHERAL_PERMIT[120] & ~reg_be))) | + (addr_hit[121] & (|(CACHEPOOL_PERIPHERAL_PERMIT[121] & ~reg_be))) | + (addr_hit[122] & (|(CACHEPOOL_PERIPHERAL_PERMIT[122] & ~reg_be))) | + (addr_hit[123] & (|(CACHEPOOL_PERIPHERAL_PERMIT[123] & ~reg_be))) | + (addr_hit[124] & (|(CACHEPOOL_PERIPHERAL_PERMIT[124] & ~reg_be))) | + (addr_hit[125] & (|(CACHEPOOL_PERIPHERAL_PERMIT[125] & ~reg_be))) | + (addr_hit[126] & (|(CACHEPOOL_PERIPHERAL_PERMIT[126] & ~reg_be))) | + (addr_hit[127] & (|(CACHEPOOL_PERIPHERAL_PERMIT[127] & ~reg_be))) | + (addr_hit[128] & (|(CACHEPOOL_PERIPHERAL_PERMIT[128] & ~reg_be))) | + (addr_hit[129] & (|(CACHEPOOL_PERIPHERAL_PERMIT[129] & ~reg_be))) | + (addr_hit[130] & (|(CACHEPOOL_PERIPHERAL_PERMIT[130] & ~reg_be))) | + (addr_hit[131] & (|(CACHEPOOL_PERIPHERAL_PERMIT[131] & ~reg_be))) | + (addr_hit[132] & (|(CACHEPOOL_PERIPHERAL_PERMIT[132] & ~reg_be))) | + (addr_hit[133] & (|(CACHEPOOL_PERIPHERAL_PERMIT[133] & ~reg_be))) | + (addr_hit[134] & (|(CACHEPOOL_PERIPHERAL_PERMIT[134] & ~reg_be))) | + (addr_hit[135] & (|(CACHEPOOL_PERIPHERAL_PERMIT[135] & ~reg_be))) | + (addr_hit[136] & (|(CACHEPOOL_PERIPHERAL_PERMIT[136] & ~reg_be))) | + (addr_hit[137] & (|(CACHEPOOL_PERIPHERAL_PERMIT[137] & ~reg_be))) | + (addr_hit[138] & (|(CACHEPOOL_PERIPHERAL_PERMIT[138] & ~reg_be))) | + (addr_hit[139] & (|(CACHEPOOL_PERIPHERAL_PERMIT[139] & ~reg_be))) | + (addr_hit[140] & (|(CACHEPOOL_PERIPHERAL_PERMIT[140] & ~reg_be))) | + (addr_hit[141] & (|(CACHEPOOL_PERIPHERAL_PERMIT[141] & ~reg_be))) | + (addr_hit[142] & (|(CACHEPOOL_PERIPHERAL_PERMIT[142] & ~reg_be))) | + (addr_hit[143] & (|(CACHEPOOL_PERIPHERAL_PERMIT[143] & ~reg_be))) | + (addr_hit[144] & (|(CACHEPOOL_PERIPHERAL_PERMIT[144] & ~reg_be))) | + (addr_hit[145] & (|(CACHEPOOL_PERIPHERAL_PERMIT[145] & ~reg_be))) | + (addr_hit[146] & (|(CACHEPOOL_PERIPHERAL_PERMIT[146] & ~reg_be))) | + (addr_hit[147] & (|(CACHEPOOL_PERIPHERAL_PERMIT[147] & ~reg_be))) | + (addr_hit[148] & (|(CACHEPOOL_PERIPHERAL_PERMIT[148] & ~reg_be))) | + (addr_hit[149] & (|(CACHEPOOL_PERIPHERAL_PERMIT[149] & ~reg_be))) | + (addr_hit[150] & (|(CACHEPOOL_PERIPHERAL_PERMIT[150] & ~reg_be))) | + (addr_hit[151] & (|(CACHEPOOL_PERIPHERAL_PERMIT[151] & ~reg_be))) | + (addr_hit[152] & (|(CACHEPOOL_PERIPHERAL_PERMIT[152] & ~reg_be))) | + (addr_hit[153] & (|(CACHEPOOL_PERIPHERAL_PERMIT[153] & ~reg_be))) | + (addr_hit[154] & (|(CACHEPOOL_PERIPHERAL_PERMIT[154] & ~reg_be))) | + (addr_hit[155] & (|(CACHEPOOL_PERIPHERAL_PERMIT[155] & ~reg_be))) | + (addr_hit[156] & (|(CACHEPOOL_PERIPHERAL_PERMIT[156] & ~reg_be))) | + (addr_hit[157] & (|(CACHEPOOL_PERIPHERAL_PERMIT[157] & ~reg_be))) | + (addr_hit[158] & (|(CACHEPOOL_PERIPHERAL_PERMIT[158] & ~reg_be))) | + (addr_hit[159] & (|(CACHEPOOL_PERIPHERAL_PERMIT[159] & ~reg_be))) | + (addr_hit[160] & (|(CACHEPOOL_PERIPHERAL_PERMIT[160] & ~reg_be))) | + (addr_hit[161] & (|(CACHEPOOL_PERIPHERAL_PERMIT[161] & ~reg_be))) | + (addr_hit[162] & (|(CACHEPOOL_PERIPHERAL_PERMIT[162] & ~reg_be))) | + (addr_hit[163] & (|(CACHEPOOL_PERIPHERAL_PERMIT[163] & ~reg_be))) | + (addr_hit[164] & (|(CACHEPOOL_PERIPHERAL_PERMIT[164] & ~reg_be))) | + (addr_hit[165] & (|(CACHEPOOL_PERIPHERAL_PERMIT[165] & ~reg_be))) | + (addr_hit[166] & (|(CACHEPOOL_PERIPHERAL_PERMIT[166] & ~reg_be))) | + (addr_hit[167] & (|(CACHEPOOL_PERIPHERAL_PERMIT[167] & ~reg_be))) | + (addr_hit[168] & (|(CACHEPOOL_PERIPHERAL_PERMIT[168] & ~reg_be))) | + (addr_hit[169] & (|(CACHEPOOL_PERIPHERAL_PERMIT[169] & ~reg_be))) | + (addr_hit[170] & (|(CACHEPOOL_PERIPHERAL_PERMIT[170] & ~reg_be))) | + (addr_hit[171] & (|(CACHEPOOL_PERIPHERAL_PERMIT[171] & ~reg_be))) | + (addr_hit[172] & (|(CACHEPOOL_PERIPHERAL_PERMIT[172] & ~reg_be))) | + (addr_hit[173] & (|(CACHEPOOL_PERIPHERAL_PERMIT[173] & ~reg_be))) | + (addr_hit[174] & (|(CACHEPOOL_PERIPHERAL_PERMIT[174] & ~reg_be))) | + (addr_hit[175] & (|(CACHEPOOL_PERIPHERAL_PERMIT[175] & ~reg_be))) | + (addr_hit[176] & (|(CACHEPOOL_PERIPHERAL_PERMIT[176] & ~reg_be))) | + (addr_hit[177] & (|(CACHEPOOL_PERIPHERAL_PERMIT[177] & ~reg_be))) | + (addr_hit[178] & (|(CACHEPOOL_PERIPHERAL_PERMIT[178] & ~reg_be))) | + (addr_hit[179] & (|(CACHEPOOL_PERIPHERAL_PERMIT[179] & ~reg_be))) | + (addr_hit[180] & (|(CACHEPOOL_PERIPHERAL_PERMIT[180] & ~reg_be))) | + (addr_hit[181] & (|(CACHEPOOL_PERIPHERAL_PERMIT[181] & ~reg_be))) | + (addr_hit[182] & (|(CACHEPOOL_PERIPHERAL_PERMIT[182] & ~reg_be))) | + (addr_hit[183] & (|(CACHEPOOL_PERIPHERAL_PERMIT[183] & ~reg_be))) | + (addr_hit[184] & (|(CACHEPOOL_PERIPHERAL_PERMIT[184] & ~reg_be))) | + (addr_hit[185] & (|(CACHEPOOL_PERIPHERAL_PERMIT[185] & ~reg_be))) | + (addr_hit[186] & (|(CACHEPOOL_PERIPHERAL_PERMIT[186] & ~reg_be))) | + (addr_hit[187] & (|(CACHEPOOL_PERIPHERAL_PERMIT[187] & ~reg_be))) | + (addr_hit[188] & (|(CACHEPOOL_PERIPHERAL_PERMIT[188] & ~reg_be))) | + (addr_hit[189] & (|(CACHEPOOL_PERIPHERAL_PERMIT[189] & ~reg_be))) | + (addr_hit[190] & (|(CACHEPOOL_PERIPHERAL_PERMIT[190] & ~reg_be))) | + (addr_hit[191] & (|(CACHEPOOL_PERIPHERAL_PERMIT[191] & ~reg_be))) | + (addr_hit[192] & (|(CACHEPOOL_PERIPHERAL_PERMIT[192] & ~reg_be))) | + (addr_hit[193] & (|(CACHEPOOL_PERIPHERAL_PERMIT[193] & ~reg_be))) | + (addr_hit[194] & (|(CACHEPOOL_PERIPHERAL_PERMIT[194] & ~reg_be))) | + (addr_hit[195] & (|(CACHEPOOL_PERIPHERAL_PERMIT[195] & ~reg_be))) | + (addr_hit[196] & (|(CACHEPOOL_PERIPHERAL_PERMIT[196] & ~reg_be))) | + (addr_hit[197] & (|(CACHEPOOL_PERIPHERAL_PERMIT[197] & ~reg_be))) | + (addr_hit[198] & (|(CACHEPOOL_PERIPHERAL_PERMIT[198] & ~reg_be))) | + (addr_hit[199] & (|(CACHEPOOL_PERIPHERAL_PERMIT[199] & ~reg_be))) | + (addr_hit[200] & (|(CACHEPOOL_PERIPHERAL_PERMIT[200] & ~reg_be))) | + (addr_hit[201] & (|(CACHEPOOL_PERIPHERAL_PERMIT[201] & ~reg_be))) | + (addr_hit[202] & (|(CACHEPOOL_PERIPHERAL_PERMIT[202] & ~reg_be))) | + (addr_hit[203] & (|(CACHEPOOL_PERIPHERAL_PERMIT[203] & ~reg_be))) | + (addr_hit[204] & (|(CACHEPOOL_PERIPHERAL_PERMIT[204] & ~reg_be))) | + (addr_hit[205] & (|(CACHEPOOL_PERIPHERAL_PERMIT[205] & ~reg_be))) | + (addr_hit[206] & (|(CACHEPOOL_PERIPHERAL_PERMIT[206] & ~reg_be))) | + (addr_hit[207] & (|(CACHEPOOL_PERIPHERAL_PERMIT[207] & ~reg_be))) | + (addr_hit[208] & (|(CACHEPOOL_PERIPHERAL_PERMIT[208] & ~reg_be))) | + (addr_hit[209] & (|(CACHEPOOL_PERIPHERAL_PERMIT[209] & ~reg_be))) | + (addr_hit[210] & (|(CACHEPOOL_PERIPHERAL_PERMIT[210] & ~reg_be))) | + (addr_hit[211] & (|(CACHEPOOL_PERIPHERAL_PERMIT[211] & ~reg_be))) | + (addr_hit[212] & (|(CACHEPOOL_PERIPHERAL_PERMIT[212] & ~reg_be))) | + (addr_hit[213] & (|(CACHEPOOL_PERIPHERAL_PERMIT[213] & ~reg_be))) | + (addr_hit[214] & (|(CACHEPOOL_PERIPHERAL_PERMIT[214] & ~reg_be))) | + (addr_hit[215] & (|(CACHEPOOL_PERIPHERAL_PERMIT[215] & ~reg_be))) | + (addr_hit[216] & (|(CACHEPOOL_PERIPHERAL_PERMIT[216] & ~reg_be))) | + (addr_hit[217] & (|(CACHEPOOL_PERIPHERAL_PERMIT[217] & ~reg_be))) | + (addr_hit[218] & (|(CACHEPOOL_PERIPHERAL_PERMIT[218] & ~reg_be))) | + (addr_hit[219] & (|(CACHEPOOL_PERIPHERAL_PERMIT[219] & ~reg_be))) | + (addr_hit[220] & (|(CACHEPOOL_PERIPHERAL_PERMIT[220] & ~reg_be))) | + (addr_hit[221] & (|(CACHEPOOL_PERIPHERAL_PERMIT[221] & ~reg_be))) | + (addr_hit[222] & (|(CACHEPOOL_PERIPHERAL_PERMIT[222] & ~reg_be))) | + (addr_hit[223] & (|(CACHEPOOL_PERIPHERAL_PERMIT[223] & ~reg_be))) | + (addr_hit[224] & (|(CACHEPOOL_PERIPHERAL_PERMIT[224] & ~reg_be))) | + (addr_hit[225] & (|(CACHEPOOL_PERIPHERAL_PERMIT[225] & ~reg_be))) | + (addr_hit[226] & (|(CACHEPOOL_PERIPHERAL_PERMIT[226] & ~reg_be))) | + (addr_hit[227] & (|(CACHEPOOL_PERIPHERAL_PERMIT[227] & ~reg_be))) | + (addr_hit[228] & (|(CACHEPOOL_PERIPHERAL_PERMIT[228] & ~reg_be))) | + (addr_hit[229] & (|(CACHEPOOL_PERIPHERAL_PERMIT[229] & ~reg_be))) | + (addr_hit[230] & (|(CACHEPOOL_PERIPHERAL_PERMIT[230] & ~reg_be))) | + (addr_hit[231] & (|(CACHEPOOL_PERIPHERAL_PERMIT[231] & ~reg_be))) | + (addr_hit[232] & (|(CACHEPOOL_PERIPHERAL_PERMIT[232] & ~reg_be))) | + (addr_hit[233] & (|(CACHEPOOL_PERIPHERAL_PERMIT[233] & ~reg_be))) | + (addr_hit[234] & (|(CACHEPOOL_PERIPHERAL_PERMIT[234] & ~reg_be))) | + (addr_hit[235] & (|(CACHEPOOL_PERIPHERAL_PERMIT[235] & ~reg_be))) | + (addr_hit[236] & (|(CACHEPOOL_PERIPHERAL_PERMIT[236] & ~reg_be))) | + (addr_hit[237] & (|(CACHEPOOL_PERIPHERAL_PERMIT[237] & ~reg_be))) | + (addr_hit[238] & (|(CACHEPOOL_PERIPHERAL_PERMIT[238] & ~reg_be))) | + (addr_hit[239] & (|(CACHEPOOL_PERIPHERAL_PERMIT[239] & ~reg_be))) | + (addr_hit[240] & (|(CACHEPOOL_PERIPHERAL_PERMIT[240] & ~reg_be))) | + (addr_hit[241] & (|(CACHEPOOL_PERIPHERAL_PERMIT[241] & ~reg_be))) | + (addr_hit[242] & (|(CACHEPOOL_PERIPHERAL_PERMIT[242] & ~reg_be))) | + (addr_hit[243] & (|(CACHEPOOL_PERIPHERAL_PERMIT[243] & ~reg_be))) | + (addr_hit[244] & (|(CACHEPOOL_PERIPHERAL_PERMIT[244] & ~reg_be))) | + (addr_hit[245] & (|(CACHEPOOL_PERIPHERAL_PERMIT[245] & ~reg_be))) | + (addr_hit[246] & (|(CACHEPOOL_PERIPHERAL_PERMIT[246] & ~reg_be))) | + (addr_hit[247] & (|(CACHEPOOL_PERIPHERAL_PERMIT[247] & ~reg_be))) | + (addr_hit[248] & (|(CACHEPOOL_PERIPHERAL_PERMIT[248] & ~reg_be))) | + (addr_hit[249] & (|(CACHEPOOL_PERIPHERAL_PERMIT[249] & ~reg_be))) | + (addr_hit[250] & (|(CACHEPOOL_PERIPHERAL_PERMIT[250] & ~reg_be))) | + (addr_hit[251] & (|(CACHEPOOL_PERIPHERAL_PERMIT[251] & ~reg_be))) | + (addr_hit[252] & (|(CACHEPOOL_PERIPHERAL_PERMIT[252] & ~reg_be))) | + (addr_hit[253] & (|(CACHEPOOL_PERIPHERAL_PERMIT[253] & ~reg_be))) | + (addr_hit[254] & (|(CACHEPOOL_PERIPHERAL_PERMIT[254] & ~reg_be))) | + (addr_hit[255] & (|(CACHEPOOL_PERIPHERAL_PERMIT[255] & ~reg_be))) | + (addr_hit[256] & (|(CACHEPOOL_PERIPHERAL_PERMIT[256] & ~reg_be))) | + (addr_hit[257] & (|(CACHEPOOL_PERIPHERAL_PERMIT[257] & ~reg_be))) | + (addr_hit[258] & (|(CACHEPOOL_PERIPHERAL_PERMIT[258] & ~reg_be))) | + (addr_hit[259] & (|(CACHEPOOL_PERIPHERAL_PERMIT[259] & ~reg_be))) | + (addr_hit[260] & (|(CACHEPOOL_PERIPHERAL_PERMIT[260] & ~reg_be))) | + (addr_hit[261] & (|(CACHEPOOL_PERIPHERAL_PERMIT[261] & ~reg_be))) | + (addr_hit[262] & (|(CACHEPOOL_PERIPHERAL_PERMIT[262] & ~reg_be))) | + (addr_hit[263] & (|(CACHEPOOL_PERIPHERAL_PERMIT[263] & ~reg_be))) | + (addr_hit[264] & (|(CACHEPOOL_PERIPHERAL_PERMIT[264] & ~reg_be))) | + (addr_hit[265] & (|(CACHEPOOL_PERIPHERAL_PERMIT[265] & ~reg_be))) | + (addr_hit[266] & (|(CACHEPOOL_PERIPHERAL_PERMIT[266] & ~reg_be))) | + (addr_hit[267] & (|(CACHEPOOL_PERIPHERAL_PERMIT[267] & ~reg_be))) | + (addr_hit[268] & (|(CACHEPOOL_PERIPHERAL_PERMIT[268] & ~reg_be))) | + (addr_hit[269] & (|(CACHEPOOL_PERIPHERAL_PERMIT[269] & ~reg_be))) | + (addr_hit[270] & (|(CACHEPOOL_PERIPHERAL_PERMIT[270] & ~reg_be))) | + (addr_hit[271] & (|(CACHEPOOL_PERIPHERAL_PERMIT[271] & ~reg_be))) | + (addr_hit[272] & (|(CACHEPOOL_PERIPHERAL_PERMIT[272] & ~reg_be))))); + end + + assign hw_barrier_re = addr_hit[0] & reg_re & !reg_error; + + assign icache_prefetch_enable_we = addr_hit[1] & reg_we & !reg_error; + assign icache_prefetch_enable_wd = reg_wdata[0]; + + assign spatz_status_we = addr_hit[2] & reg_we & !reg_error; + assign spatz_status_wd = reg_wdata[0]; + + assign spatz_cycle_we = addr_hit[3] & reg_we & !reg_error; + assign spatz_cycle_wd = reg_wdata[31:0]; + + assign cluster_boot_control_we = addr_hit[4] & reg_we & !reg_error; + assign cluster_boot_control_wd = reg_wdata[31:0]; + + assign cluster_eoc_exit_we = addr_hit[5] & reg_we & !reg_error; + assign cluster_eoc_exit_wd = reg_wdata[3:0]; + + assign cfg_l1d_spm_we = addr_hit[6] & reg_we & !reg_error; + assign cfg_l1d_spm_wd = reg_wdata[9:0]; + + assign cfg_l1d_insn_we = addr_hit[7] & reg_we & !reg_error; + assign cfg_l1d_insn_wd = reg_wdata[1:0]; + + assign cfg_l1d_tile_sel_0_we = addr_hit[8] & reg_we & !reg_error; + assign cfg_l1d_tile_sel_0_wd = reg_wdata[31:0]; + + assign cfg_l1d_tile_sel_1_we = addr_hit[9] & reg_we & !reg_error; + assign cfg_l1d_tile_sel_1_wd = reg_wdata[31:0]; + + assign l1d_spm_commit_we = addr_hit[10] & reg_we & !reg_error; + assign l1d_spm_commit_wd = reg_wdata[0]; + + assign l1d_insn_commit_we = addr_hit[11] & reg_we & !reg_error; + assign l1d_insn_commit_wd = reg_wdata[0]; + + assign l1d_flush_status_re = addr_hit[12] & reg_re & !reg_error; + + assign l1d_private_we = addr_hit[13] & reg_we & !reg_error; + assign l1d_private_wd = reg_wdata[3:0]; + + assign l1d_addr_we = addr_hit[14] & reg_we & !reg_error; + assign l1d_addr_wd = reg_wdata[31:0]; + + assign xbar_offset_we = addr_hit[15] & reg_we & !reg_error; + assign xbar_offset_wd = reg_wdata[4:0]; + + assign xbar_offset_commit_we = addr_hit[16] & reg_we & !reg_error; + assign xbar_offset_commit_wd = reg_wdata[0]; + + assign cfg_lp1_cmo_0_we = addr_hit[17] & reg_we & !reg_error; + assign cfg_lp1_cmo_0_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_1_we = addr_hit[18] & reg_we & !reg_error; + assign cfg_lp1_cmo_1_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_2_we = addr_hit[19] & reg_we & !reg_error; + assign cfg_lp1_cmo_2_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_3_we = addr_hit[20] & reg_we & !reg_error; + assign cfg_lp1_cmo_3_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_4_we = addr_hit[21] & reg_we & !reg_error; + assign cfg_lp1_cmo_4_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_5_we = addr_hit[22] & reg_we & !reg_error; + assign cfg_lp1_cmo_5_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_6_we = addr_hit[23] & reg_we & !reg_error; + assign cfg_lp1_cmo_6_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_7_we = addr_hit[24] & reg_we & !reg_error; + assign cfg_lp1_cmo_7_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_8_we = addr_hit[25] & reg_we & !reg_error; + assign cfg_lp1_cmo_8_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_9_we = addr_hit[26] & reg_we & !reg_error; + assign cfg_lp1_cmo_9_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_10_we = addr_hit[27] & reg_we & !reg_error; + assign cfg_lp1_cmo_10_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_11_we = addr_hit[28] & reg_we & !reg_error; + assign cfg_lp1_cmo_11_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_12_we = addr_hit[29] & reg_we & !reg_error; + assign cfg_lp1_cmo_12_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_13_we = addr_hit[30] & reg_we & !reg_error; + assign cfg_lp1_cmo_13_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_14_we = addr_hit[31] & reg_we & !reg_error; + assign cfg_lp1_cmo_14_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_15_we = addr_hit[32] & reg_we & !reg_error; + assign cfg_lp1_cmo_15_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_16_we = addr_hit[33] & reg_we & !reg_error; + assign cfg_lp1_cmo_16_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_17_we = addr_hit[34] & reg_we & !reg_error; + assign cfg_lp1_cmo_17_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_18_we = addr_hit[35] & reg_we & !reg_error; + assign cfg_lp1_cmo_18_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_19_we = addr_hit[36] & reg_we & !reg_error; + assign cfg_lp1_cmo_19_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_20_we = addr_hit[37] & reg_we & !reg_error; + assign cfg_lp1_cmo_20_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_21_we = addr_hit[38] & reg_we & !reg_error; + assign cfg_lp1_cmo_21_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_22_we = addr_hit[39] & reg_we & !reg_error; + assign cfg_lp1_cmo_22_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_23_we = addr_hit[40] & reg_we & !reg_error; + assign cfg_lp1_cmo_23_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_24_we = addr_hit[41] & reg_we & !reg_error; + assign cfg_lp1_cmo_24_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_25_we = addr_hit[42] & reg_we & !reg_error; + assign cfg_lp1_cmo_25_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_26_we = addr_hit[43] & reg_we & !reg_error; + assign cfg_lp1_cmo_26_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_27_we = addr_hit[44] & reg_we & !reg_error; + assign cfg_lp1_cmo_27_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_28_we = addr_hit[45] & reg_we & !reg_error; + assign cfg_lp1_cmo_28_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_29_we = addr_hit[46] & reg_we & !reg_error; + assign cfg_lp1_cmo_29_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_30_we = addr_hit[47] & reg_we & !reg_error; + assign cfg_lp1_cmo_30_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_31_we = addr_hit[48] & reg_we & !reg_error; + assign cfg_lp1_cmo_31_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_32_we = addr_hit[49] & reg_we & !reg_error; + assign cfg_lp1_cmo_32_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_33_we = addr_hit[50] & reg_we & !reg_error; + assign cfg_lp1_cmo_33_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_34_we = addr_hit[51] & reg_we & !reg_error; + assign cfg_lp1_cmo_34_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_35_we = addr_hit[52] & reg_we & !reg_error; + assign cfg_lp1_cmo_35_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_36_we = addr_hit[53] & reg_we & !reg_error; + assign cfg_lp1_cmo_36_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_37_we = addr_hit[54] & reg_we & !reg_error; + assign cfg_lp1_cmo_37_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_38_we = addr_hit[55] & reg_we & !reg_error; + assign cfg_lp1_cmo_38_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_39_we = addr_hit[56] & reg_we & !reg_error; + assign cfg_lp1_cmo_39_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_40_we = addr_hit[57] & reg_we & !reg_error; + assign cfg_lp1_cmo_40_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_41_we = addr_hit[58] & reg_we & !reg_error; + assign cfg_lp1_cmo_41_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_42_we = addr_hit[59] & reg_we & !reg_error; + assign cfg_lp1_cmo_42_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_43_we = addr_hit[60] & reg_we & !reg_error; + assign cfg_lp1_cmo_43_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_44_we = addr_hit[61] & reg_we & !reg_error; + assign cfg_lp1_cmo_44_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_45_we = addr_hit[62] & reg_we & !reg_error; + assign cfg_lp1_cmo_45_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_46_we = addr_hit[63] & reg_we & !reg_error; + assign cfg_lp1_cmo_46_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_47_we = addr_hit[64] & reg_we & !reg_error; + assign cfg_lp1_cmo_47_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_48_we = addr_hit[65] & reg_we & !reg_error; + assign cfg_lp1_cmo_48_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_49_we = addr_hit[66] & reg_we & !reg_error; + assign cfg_lp1_cmo_49_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_50_we = addr_hit[67] & reg_we & !reg_error; + assign cfg_lp1_cmo_50_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_51_we = addr_hit[68] & reg_we & !reg_error; + assign cfg_lp1_cmo_51_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_52_we = addr_hit[69] & reg_we & !reg_error; + assign cfg_lp1_cmo_52_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_53_we = addr_hit[70] & reg_we & !reg_error; + assign cfg_lp1_cmo_53_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_54_we = addr_hit[71] & reg_we & !reg_error; + assign cfg_lp1_cmo_54_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_55_we = addr_hit[72] & reg_we & !reg_error; + assign cfg_lp1_cmo_55_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_56_we = addr_hit[73] & reg_we & !reg_error; + assign cfg_lp1_cmo_56_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_57_we = addr_hit[74] & reg_we & !reg_error; + assign cfg_lp1_cmo_57_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_58_we = addr_hit[75] & reg_we & !reg_error; + assign cfg_lp1_cmo_58_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_59_we = addr_hit[76] & reg_we & !reg_error; + assign cfg_lp1_cmo_59_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_60_we = addr_hit[77] & reg_we & !reg_error; + assign cfg_lp1_cmo_60_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_61_we = addr_hit[78] & reg_we & !reg_error; + assign cfg_lp1_cmo_61_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_62_we = addr_hit[79] & reg_we & !reg_error; + assign cfg_lp1_cmo_62_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_63_we = addr_hit[80] & reg_we & !reg_error; + assign cfg_lp1_cmo_63_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_addr_0_we = addr_hit[81] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_0_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_1_we = addr_hit[82] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_1_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_2_we = addr_hit[83] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_2_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_3_we = addr_hit[84] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_3_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_4_we = addr_hit[85] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_4_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_5_we = addr_hit[86] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_5_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_6_we = addr_hit[87] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_6_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_7_we = addr_hit[88] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_7_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_8_we = addr_hit[89] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_8_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_9_we = addr_hit[90] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_9_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_10_we = addr_hit[91] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_10_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_11_we = addr_hit[92] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_11_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_12_we = addr_hit[93] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_12_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_13_we = addr_hit[94] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_13_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_14_we = addr_hit[95] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_14_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_15_we = addr_hit[96] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_15_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_16_we = addr_hit[97] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_16_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_17_we = addr_hit[98] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_17_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_18_we = addr_hit[99] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_18_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_19_we = addr_hit[100] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_19_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_20_we = addr_hit[101] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_20_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_21_we = addr_hit[102] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_21_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_22_we = addr_hit[103] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_22_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_23_we = addr_hit[104] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_23_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_24_we = addr_hit[105] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_24_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_25_we = addr_hit[106] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_25_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_26_we = addr_hit[107] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_26_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_27_we = addr_hit[108] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_27_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_28_we = addr_hit[109] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_28_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_29_we = addr_hit[110] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_29_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_30_we = addr_hit[111] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_30_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_31_we = addr_hit[112] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_31_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_32_we = addr_hit[113] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_32_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_33_we = addr_hit[114] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_33_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_34_we = addr_hit[115] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_34_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_35_we = addr_hit[116] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_35_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_36_we = addr_hit[117] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_36_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_37_we = addr_hit[118] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_37_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_38_we = addr_hit[119] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_38_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_39_we = addr_hit[120] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_39_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_40_we = addr_hit[121] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_40_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_41_we = addr_hit[122] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_41_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_42_we = addr_hit[123] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_42_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_43_we = addr_hit[124] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_43_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_44_we = addr_hit[125] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_44_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_45_we = addr_hit[126] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_45_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_46_we = addr_hit[127] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_46_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_47_we = addr_hit[128] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_47_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_48_we = addr_hit[129] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_48_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_49_we = addr_hit[130] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_49_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_50_we = addr_hit[131] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_50_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_51_we = addr_hit[132] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_51_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_52_we = addr_hit[133] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_52_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_53_we = addr_hit[134] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_53_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_54_we = addr_hit[135] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_54_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_55_we = addr_hit[136] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_55_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_56_we = addr_hit[137] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_56_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_57_we = addr_hit[138] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_57_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_58_we = addr_hit[139] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_58_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_59_we = addr_hit[140] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_59_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_60_we = addr_hit[141] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_60_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_61_we = addr_hit[142] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_61_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_62_we = addr_hit[143] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_62_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_63_we = addr_hit[144] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_63_wd = reg_wdata[31:0]; + + assign lp1_cmo_commit_0_we = addr_hit[145] & reg_we & !reg_error; + assign lp1_cmo_commit_0_wd = reg_wdata[0]; + + assign lp1_cmo_commit_1_we = addr_hit[146] & reg_we & !reg_error; + assign lp1_cmo_commit_1_wd = reg_wdata[0]; + + assign lp1_cmo_commit_2_we = addr_hit[147] & reg_we & !reg_error; + assign lp1_cmo_commit_2_wd = reg_wdata[0]; + + assign lp1_cmo_commit_3_we = addr_hit[148] & reg_we & !reg_error; + assign lp1_cmo_commit_3_wd = reg_wdata[0]; + + assign lp1_cmo_commit_4_we = addr_hit[149] & reg_we & !reg_error; + assign lp1_cmo_commit_4_wd = reg_wdata[0]; + + assign lp1_cmo_commit_5_we = addr_hit[150] & reg_we & !reg_error; + assign lp1_cmo_commit_5_wd = reg_wdata[0]; + + assign lp1_cmo_commit_6_we = addr_hit[151] & reg_we & !reg_error; + assign lp1_cmo_commit_6_wd = reg_wdata[0]; + + assign lp1_cmo_commit_7_we = addr_hit[152] & reg_we & !reg_error; + assign lp1_cmo_commit_7_wd = reg_wdata[0]; + + assign lp1_cmo_commit_8_we = addr_hit[153] & reg_we & !reg_error; + assign lp1_cmo_commit_8_wd = reg_wdata[0]; + + assign lp1_cmo_commit_9_we = addr_hit[154] & reg_we & !reg_error; + assign lp1_cmo_commit_9_wd = reg_wdata[0]; + + assign lp1_cmo_commit_10_we = addr_hit[155] & reg_we & !reg_error; + assign lp1_cmo_commit_10_wd = reg_wdata[0]; + + assign lp1_cmo_commit_11_we = addr_hit[156] & reg_we & !reg_error; + assign lp1_cmo_commit_11_wd = reg_wdata[0]; + + assign lp1_cmo_commit_12_we = addr_hit[157] & reg_we & !reg_error; + assign lp1_cmo_commit_12_wd = reg_wdata[0]; + + assign lp1_cmo_commit_13_we = addr_hit[158] & reg_we & !reg_error; + assign lp1_cmo_commit_13_wd = reg_wdata[0]; + + assign lp1_cmo_commit_14_we = addr_hit[159] & reg_we & !reg_error; + assign lp1_cmo_commit_14_wd = reg_wdata[0]; + + assign lp1_cmo_commit_15_we = addr_hit[160] & reg_we & !reg_error; + assign lp1_cmo_commit_15_wd = reg_wdata[0]; + + assign lp1_cmo_commit_16_we = addr_hit[161] & reg_we & !reg_error; + assign lp1_cmo_commit_16_wd = reg_wdata[0]; + + assign lp1_cmo_commit_17_we = addr_hit[162] & reg_we & !reg_error; + assign lp1_cmo_commit_17_wd = reg_wdata[0]; + + assign lp1_cmo_commit_18_we = addr_hit[163] & reg_we & !reg_error; + assign lp1_cmo_commit_18_wd = reg_wdata[0]; + + assign lp1_cmo_commit_19_we = addr_hit[164] & reg_we & !reg_error; + assign lp1_cmo_commit_19_wd = reg_wdata[0]; + + assign lp1_cmo_commit_20_we = addr_hit[165] & reg_we & !reg_error; + assign lp1_cmo_commit_20_wd = reg_wdata[0]; + + assign lp1_cmo_commit_21_we = addr_hit[166] & reg_we & !reg_error; + assign lp1_cmo_commit_21_wd = reg_wdata[0]; + + assign lp1_cmo_commit_22_we = addr_hit[167] & reg_we & !reg_error; + assign lp1_cmo_commit_22_wd = reg_wdata[0]; + + assign lp1_cmo_commit_23_we = addr_hit[168] & reg_we & !reg_error; + assign lp1_cmo_commit_23_wd = reg_wdata[0]; + + assign lp1_cmo_commit_24_we = addr_hit[169] & reg_we & !reg_error; + assign lp1_cmo_commit_24_wd = reg_wdata[0]; + + assign lp1_cmo_commit_25_we = addr_hit[170] & reg_we & !reg_error; + assign lp1_cmo_commit_25_wd = reg_wdata[0]; + + assign lp1_cmo_commit_26_we = addr_hit[171] & reg_we & !reg_error; + assign lp1_cmo_commit_26_wd = reg_wdata[0]; + + assign lp1_cmo_commit_27_we = addr_hit[172] & reg_we & !reg_error; + assign lp1_cmo_commit_27_wd = reg_wdata[0]; + + assign lp1_cmo_commit_28_we = addr_hit[173] & reg_we & !reg_error; + assign lp1_cmo_commit_28_wd = reg_wdata[0]; + + assign lp1_cmo_commit_29_we = addr_hit[174] & reg_we & !reg_error; + assign lp1_cmo_commit_29_wd = reg_wdata[0]; + + assign lp1_cmo_commit_30_we = addr_hit[175] & reg_we & !reg_error; + assign lp1_cmo_commit_30_wd = reg_wdata[0]; + + assign lp1_cmo_commit_31_we = addr_hit[176] & reg_we & !reg_error; + assign lp1_cmo_commit_31_wd = reg_wdata[0]; + + assign lp1_cmo_commit_32_we = addr_hit[177] & reg_we & !reg_error; + assign lp1_cmo_commit_32_wd = reg_wdata[0]; + + assign lp1_cmo_commit_33_we = addr_hit[178] & reg_we & !reg_error; + assign lp1_cmo_commit_33_wd = reg_wdata[0]; + + assign lp1_cmo_commit_34_we = addr_hit[179] & reg_we & !reg_error; + assign lp1_cmo_commit_34_wd = reg_wdata[0]; + + assign lp1_cmo_commit_35_we = addr_hit[180] & reg_we & !reg_error; + assign lp1_cmo_commit_35_wd = reg_wdata[0]; + + assign lp1_cmo_commit_36_we = addr_hit[181] & reg_we & !reg_error; + assign lp1_cmo_commit_36_wd = reg_wdata[0]; + + assign lp1_cmo_commit_37_we = addr_hit[182] & reg_we & !reg_error; + assign lp1_cmo_commit_37_wd = reg_wdata[0]; + + assign lp1_cmo_commit_38_we = addr_hit[183] & reg_we & !reg_error; + assign lp1_cmo_commit_38_wd = reg_wdata[0]; + + assign lp1_cmo_commit_39_we = addr_hit[184] & reg_we & !reg_error; + assign lp1_cmo_commit_39_wd = reg_wdata[0]; + + assign lp1_cmo_commit_40_we = addr_hit[185] & reg_we & !reg_error; + assign lp1_cmo_commit_40_wd = reg_wdata[0]; + + assign lp1_cmo_commit_41_we = addr_hit[186] & reg_we & !reg_error; + assign lp1_cmo_commit_41_wd = reg_wdata[0]; + + assign lp1_cmo_commit_42_we = addr_hit[187] & reg_we & !reg_error; + assign lp1_cmo_commit_42_wd = reg_wdata[0]; + + assign lp1_cmo_commit_43_we = addr_hit[188] & reg_we & !reg_error; + assign lp1_cmo_commit_43_wd = reg_wdata[0]; + + assign lp1_cmo_commit_44_we = addr_hit[189] & reg_we & !reg_error; + assign lp1_cmo_commit_44_wd = reg_wdata[0]; + + assign lp1_cmo_commit_45_we = addr_hit[190] & reg_we & !reg_error; + assign lp1_cmo_commit_45_wd = reg_wdata[0]; + + assign lp1_cmo_commit_46_we = addr_hit[191] & reg_we & !reg_error; + assign lp1_cmo_commit_46_wd = reg_wdata[0]; + + assign lp1_cmo_commit_47_we = addr_hit[192] & reg_we & !reg_error; + assign lp1_cmo_commit_47_wd = reg_wdata[0]; + + assign lp1_cmo_commit_48_we = addr_hit[193] & reg_we & !reg_error; + assign lp1_cmo_commit_48_wd = reg_wdata[0]; + + assign lp1_cmo_commit_49_we = addr_hit[194] & reg_we & !reg_error; + assign lp1_cmo_commit_49_wd = reg_wdata[0]; + + assign lp1_cmo_commit_50_we = addr_hit[195] & reg_we & !reg_error; + assign lp1_cmo_commit_50_wd = reg_wdata[0]; + + assign lp1_cmo_commit_51_we = addr_hit[196] & reg_we & !reg_error; + assign lp1_cmo_commit_51_wd = reg_wdata[0]; + + assign lp1_cmo_commit_52_we = addr_hit[197] & reg_we & !reg_error; + assign lp1_cmo_commit_52_wd = reg_wdata[0]; + + assign lp1_cmo_commit_53_we = addr_hit[198] & reg_we & !reg_error; + assign lp1_cmo_commit_53_wd = reg_wdata[0]; + + assign lp1_cmo_commit_54_we = addr_hit[199] & reg_we & !reg_error; + assign lp1_cmo_commit_54_wd = reg_wdata[0]; + + assign lp1_cmo_commit_55_we = addr_hit[200] & reg_we & !reg_error; + assign lp1_cmo_commit_55_wd = reg_wdata[0]; + + assign lp1_cmo_commit_56_we = addr_hit[201] & reg_we & !reg_error; + assign lp1_cmo_commit_56_wd = reg_wdata[0]; + + assign lp1_cmo_commit_57_we = addr_hit[202] & reg_we & !reg_error; + assign lp1_cmo_commit_57_wd = reg_wdata[0]; + + assign lp1_cmo_commit_58_we = addr_hit[203] & reg_we & !reg_error; + assign lp1_cmo_commit_58_wd = reg_wdata[0]; + + assign lp1_cmo_commit_59_we = addr_hit[204] & reg_we & !reg_error; + assign lp1_cmo_commit_59_wd = reg_wdata[0]; + + assign lp1_cmo_commit_60_we = addr_hit[205] & reg_we & !reg_error; + assign lp1_cmo_commit_60_wd = reg_wdata[0]; + + assign lp1_cmo_commit_61_we = addr_hit[206] & reg_we & !reg_error; + assign lp1_cmo_commit_61_wd = reg_wdata[0]; + + assign lp1_cmo_commit_62_we = addr_hit[207] & reg_we & !reg_error; + assign lp1_cmo_commit_62_wd = reg_wdata[0]; + + assign lp1_cmo_commit_63_we = addr_hit[208] & reg_we & !reg_error; + assign lp1_cmo_commit_63_wd = reg_wdata[0]; + + assign lp1_cmo_status_0_re = addr_hit[209] & reg_re & !reg_error; + + assign lp1_cmo_status_1_re = addr_hit[210] & reg_re & !reg_error; + + assign lp1_cmo_status_2_re = addr_hit[211] & reg_re & !reg_error; + + assign lp1_cmo_status_3_re = addr_hit[212] & reg_re & !reg_error; + + assign lp1_cmo_status_4_re = addr_hit[213] & reg_re & !reg_error; + + assign lp1_cmo_status_5_re = addr_hit[214] & reg_re & !reg_error; + + assign lp1_cmo_status_6_re = addr_hit[215] & reg_re & !reg_error; + + assign lp1_cmo_status_7_re = addr_hit[216] & reg_re & !reg_error; + + assign lp1_cmo_status_8_re = addr_hit[217] & reg_re & !reg_error; + + assign lp1_cmo_status_9_re = addr_hit[218] & reg_re & !reg_error; + + assign lp1_cmo_status_10_re = addr_hit[219] & reg_re & !reg_error; + + assign lp1_cmo_status_11_re = addr_hit[220] & reg_re & !reg_error; + + assign lp1_cmo_status_12_re = addr_hit[221] & reg_re & !reg_error; + + assign lp1_cmo_status_13_re = addr_hit[222] & reg_re & !reg_error; + + assign lp1_cmo_status_14_re = addr_hit[223] & reg_re & !reg_error; + + assign lp1_cmo_status_15_re = addr_hit[224] & reg_re & !reg_error; + + assign lp1_cmo_status_16_re = addr_hit[225] & reg_re & !reg_error; + + assign lp1_cmo_status_17_re = addr_hit[226] & reg_re & !reg_error; + + assign lp1_cmo_status_18_re = addr_hit[227] & reg_re & !reg_error; + + assign lp1_cmo_status_19_re = addr_hit[228] & reg_re & !reg_error; + + assign lp1_cmo_status_20_re = addr_hit[229] & reg_re & !reg_error; + + assign lp1_cmo_status_21_re = addr_hit[230] & reg_re & !reg_error; + + assign lp1_cmo_status_22_re = addr_hit[231] & reg_re & !reg_error; + + assign lp1_cmo_status_23_re = addr_hit[232] & reg_re & !reg_error; + + assign lp1_cmo_status_24_re = addr_hit[233] & reg_re & !reg_error; + + assign lp1_cmo_status_25_re = addr_hit[234] & reg_re & !reg_error; + + assign lp1_cmo_status_26_re = addr_hit[235] & reg_re & !reg_error; + + assign lp1_cmo_status_27_re = addr_hit[236] & reg_re & !reg_error; + + assign lp1_cmo_status_28_re = addr_hit[237] & reg_re & !reg_error; + + assign lp1_cmo_status_29_re = addr_hit[238] & reg_re & !reg_error; + + assign lp1_cmo_status_30_re = addr_hit[239] & reg_re & !reg_error; + + assign lp1_cmo_status_31_re = addr_hit[240] & reg_re & !reg_error; + + assign lp1_cmo_status_32_re = addr_hit[241] & reg_re & !reg_error; + + assign lp1_cmo_status_33_re = addr_hit[242] & reg_re & !reg_error; + + assign lp1_cmo_status_34_re = addr_hit[243] & reg_re & !reg_error; + + assign lp1_cmo_status_35_re = addr_hit[244] & reg_re & !reg_error; + + assign lp1_cmo_status_36_re = addr_hit[245] & reg_re & !reg_error; + + assign lp1_cmo_status_37_re = addr_hit[246] & reg_re & !reg_error; + + assign lp1_cmo_status_38_re = addr_hit[247] & reg_re & !reg_error; + + assign lp1_cmo_status_39_re = addr_hit[248] & reg_re & !reg_error; + + assign lp1_cmo_status_40_re = addr_hit[249] & reg_re & !reg_error; + + assign lp1_cmo_status_41_re = addr_hit[250] & reg_re & !reg_error; + + assign lp1_cmo_status_42_re = addr_hit[251] & reg_re & !reg_error; + + assign lp1_cmo_status_43_re = addr_hit[252] & reg_re & !reg_error; + + assign lp1_cmo_status_44_re = addr_hit[253] & reg_re & !reg_error; + + assign lp1_cmo_status_45_re = addr_hit[254] & reg_re & !reg_error; + + assign lp1_cmo_status_46_re = addr_hit[255] & reg_re & !reg_error; + + assign lp1_cmo_status_47_re = addr_hit[256] & reg_re & !reg_error; + + assign lp1_cmo_status_48_re = addr_hit[257] & reg_re & !reg_error; + + assign lp1_cmo_status_49_re = addr_hit[258] & reg_re & !reg_error; + + assign lp1_cmo_status_50_re = addr_hit[259] & reg_re & !reg_error; + + assign lp1_cmo_status_51_re = addr_hit[260] & reg_re & !reg_error; + + assign lp1_cmo_status_52_re = addr_hit[261] & reg_re & !reg_error; + + assign lp1_cmo_status_53_re = addr_hit[262] & reg_re & !reg_error; + + assign lp1_cmo_status_54_re = addr_hit[263] & reg_re & !reg_error; + + assign lp1_cmo_status_55_re = addr_hit[264] & reg_re & !reg_error; + + assign lp1_cmo_status_56_re = addr_hit[265] & reg_re & !reg_error; + + assign lp1_cmo_status_57_re = addr_hit[266] & reg_re & !reg_error; + + assign lp1_cmo_status_58_re = addr_hit[267] & reg_re & !reg_error; + + assign lp1_cmo_status_59_re = addr_hit[268] & reg_re & !reg_error; + + assign lp1_cmo_status_60_re = addr_hit[269] & reg_re & !reg_error; + + assign lp1_cmo_status_61_re = addr_hit[270] & reg_re & !reg_error; + + assign lp1_cmo_status_62_re = addr_hit[271] & reg_re & !reg_error; + + assign lp1_cmo_status_63_re = addr_hit[272] & reg_re & !reg_error; + + // Read data return always_comb begin - addr_hit = '0; - addr_hit[ 0] = (reg_addr == CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET); - addr_hit[ 1] = (reg_addr == CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); - addr_hit[ 2] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET); - addr_hit[ 3] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET); - addr_hit[ 4] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET); - addr_hit[ 5] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET); - addr_hit[ 6] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET); - addr_hit[ 7] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET); - addr_hit[ 8] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_OFFSET); - addr_hit[ 9] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_OFFSET); - addr_hit[10] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET); - addr_hit[11] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET); - addr_hit[12] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET); - addr_hit[13] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET); - addr_hit[14] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET); - addr_hit[15] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET); - addr_hit[16] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET); - end + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[31:0] = hw_barrier_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[31:0] = spatz_cycle_qs; + end + + addr_hit[4]: begin + reg_rdata_next[31:0] = cluster_boot_control_qs; + end + + addr_hit[5]: begin + reg_rdata_next[3:0] = cluster_eoc_exit_qs; + end + + addr_hit[6]: begin + reg_rdata_next[9:0] = cfg_l1d_spm_qs; + end + + addr_hit[7]: begin + reg_rdata_next[1:0] = cfg_l1d_insn_qs; + end + + addr_hit[8]: begin + reg_rdata_next[31:0] = cfg_l1d_tile_sel_0_qs; + end + + addr_hit[9]: begin + reg_rdata_next[31:0] = cfg_l1d_tile_sel_1_qs; + end + + addr_hit[10]: begin + reg_rdata_next[0] = l1d_spm_commit_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = l1d_insn_commit_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = l1d_flush_status_qs; + end + + addr_hit[13]: begin + reg_rdata_next[3:0] = l1d_private_qs; + end + + addr_hit[14]: begin + reg_rdata_next[31:0] = l1d_addr_qs; + end + + addr_hit[15]: begin + reg_rdata_next[4:0] = xbar_offset_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = xbar_offset_commit_qs; + end + + addr_hit[17]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_0_qs; + end + + addr_hit[18]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_1_qs; + end + + addr_hit[19]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_2_qs; + end + + addr_hit[20]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_3_qs; + end + + addr_hit[21]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_4_qs; + end + + addr_hit[22]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_5_qs; + end + + addr_hit[23]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_6_qs; + end + + addr_hit[24]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_7_qs; + end + + addr_hit[25]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_8_qs; + end + + addr_hit[26]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_9_qs; + end + + addr_hit[27]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_10_qs; + end + + addr_hit[28]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_11_qs; + end + + addr_hit[29]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_12_qs; + end + + addr_hit[30]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_13_qs; + end + + addr_hit[31]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_14_qs; + end + + addr_hit[32]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_15_qs; + end + + addr_hit[33]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_16_qs; + end + + addr_hit[34]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_17_qs; + end + + addr_hit[35]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_18_qs; + end + + addr_hit[36]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_19_qs; + end + + addr_hit[37]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_20_qs; + end + + addr_hit[38]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_21_qs; + end + + addr_hit[39]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_22_qs; + end + + addr_hit[40]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_23_qs; + end + + addr_hit[41]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_24_qs; + end + + addr_hit[42]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_25_qs; + end + + addr_hit[43]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_26_qs; + end + + addr_hit[44]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_27_qs; + end + + addr_hit[45]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_28_qs; + end + + addr_hit[46]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_29_qs; + end + + addr_hit[47]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_30_qs; + end + + addr_hit[48]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_31_qs; + end + + addr_hit[49]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_32_qs; + end + + addr_hit[50]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_33_qs; + end + + addr_hit[51]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_34_qs; + end + + addr_hit[52]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_35_qs; + end + + addr_hit[53]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_36_qs; + end + + addr_hit[54]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_37_qs; + end + + addr_hit[55]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_38_qs; + end + + addr_hit[56]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_39_qs; + end + + addr_hit[57]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_40_qs; + end + + addr_hit[58]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_41_qs; + end + + addr_hit[59]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_42_qs; + end + + addr_hit[60]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_43_qs; + end + + addr_hit[61]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_44_qs; + end + + addr_hit[62]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_45_qs; + end + + addr_hit[63]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_46_qs; + end + + addr_hit[64]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_47_qs; + end + + addr_hit[65]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_48_qs; + end + + addr_hit[66]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_49_qs; + end + + addr_hit[67]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_50_qs; + end + + addr_hit[68]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_51_qs; + end + + addr_hit[69]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_52_qs; + end + + addr_hit[70]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_53_qs; + end + + addr_hit[71]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_54_qs; + end + + addr_hit[72]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_55_qs; + end + + addr_hit[73]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_56_qs; + end + + addr_hit[74]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_57_qs; + end + + addr_hit[75]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_58_qs; + end + + addr_hit[76]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_59_qs; + end + + addr_hit[77]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_60_qs; + end + + addr_hit[78]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_61_qs; + end + + addr_hit[79]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_62_qs; + end + + addr_hit[80]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_63_qs; + end + + addr_hit[81]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_0_qs; + end + + addr_hit[82]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_1_qs; + end + + addr_hit[83]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_2_qs; + end + + addr_hit[84]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_3_qs; + end + + addr_hit[85]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_4_qs; + end + + addr_hit[86]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_5_qs; + end + + addr_hit[87]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_6_qs; + end + + addr_hit[88]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_7_qs; + end + + addr_hit[89]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_8_qs; + end + + addr_hit[90]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_9_qs; + end + + addr_hit[91]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_10_qs; + end + + addr_hit[92]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_11_qs; + end + + addr_hit[93]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_12_qs; + end + + addr_hit[94]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_13_qs; + end + + addr_hit[95]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_14_qs; + end + + addr_hit[96]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_15_qs; + end + + addr_hit[97]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_16_qs; + end + + addr_hit[98]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_17_qs; + end + + addr_hit[99]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_18_qs; + end + + addr_hit[100]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_19_qs; + end + + addr_hit[101]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_20_qs; + end + + addr_hit[102]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_21_qs; + end + + addr_hit[103]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_22_qs; + end + + addr_hit[104]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_23_qs; + end + + addr_hit[105]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_24_qs; + end + + addr_hit[106]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_25_qs; + end + + addr_hit[107]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_26_qs; + end + + addr_hit[108]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_27_qs; + end + + addr_hit[109]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_28_qs; + end + + addr_hit[110]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_29_qs; + end + + addr_hit[111]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_30_qs; + end + + addr_hit[112]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_31_qs; + end + + addr_hit[113]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_32_qs; + end + + addr_hit[114]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_33_qs; + end + + addr_hit[115]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_34_qs; + end + + addr_hit[116]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_35_qs; + end + + addr_hit[117]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_36_qs; + end + + addr_hit[118]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_37_qs; + end + + addr_hit[119]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_38_qs; + end + + addr_hit[120]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_39_qs; + end + + addr_hit[121]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_40_qs; + end + + addr_hit[122]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_41_qs; + end + + addr_hit[123]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_42_qs; + end + + addr_hit[124]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_43_qs; + end + + addr_hit[125]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_44_qs; + end + + addr_hit[126]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_45_qs; + end + + addr_hit[127]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_46_qs; + end + + addr_hit[128]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_47_qs; + end + + addr_hit[129]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_48_qs; + end + + addr_hit[130]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_49_qs; + end + + addr_hit[131]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_50_qs; + end + + addr_hit[132]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_51_qs; + end + + addr_hit[133]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_52_qs; + end + + addr_hit[134]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_53_qs; + end + + addr_hit[135]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_54_qs; + end + + addr_hit[136]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_55_qs; + end + + addr_hit[137]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_56_qs; + end + + addr_hit[138]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_57_qs; + end + + addr_hit[139]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_58_qs; + end + + addr_hit[140]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_59_qs; + end + + addr_hit[141]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_60_qs; + end + + addr_hit[142]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_61_qs; + end + + addr_hit[143]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_62_qs; + end + + addr_hit[144]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_63_qs; + end + + addr_hit[145]: begin + reg_rdata_next[0] = lp1_cmo_commit_0_qs; + end + + addr_hit[146]: begin + reg_rdata_next[0] = lp1_cmo_commit_1_qs; + end + + addr_hit[147]: begin + reg_rdata_next[0] = lp1_cmo_commit_2_qs; + end + + addr_hit[148]: begin + reg_rdata_next[0] = lp1_cmo_commit_3_qs; + end + + addr_hit[149]: begin + reg_rdata_next[0] = lp1_cmo_commit_4_qs; + end + + addr_hit[150]: begin + reg_rdata_next[0] = lp1_cmo_commit_5_qs; + end + + addr_hit[151]: begin + reg_rdata_next[0] = lp1_cmo_commit_6_qs; + end + + addr_hit[152]: begin + reg_rdata_next[0] = lp1_cmo_commit_7_qs; + end + + addr_hit[153]: begin + reg_rdata_next[0] = lp1_cmo_commit_8_qs; + end + + addr_hit[154]: begin + reg_rdata_next[0] = lp1_cmo_commit_9_qs; + end + + addr_hit[155]: begin + reg_rdata_next[0] = lp1_cmo_commit_10_qs; + end - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + addr_hit[156]: begin + reg_rdata_next[0] = lp1_cmo_commit_11_qs; + end - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[ 0] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(CACHEPOOL_PERIPHERAL_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(CACHEPOOL_PERIPHERAL_PERMIT[11] & ~reg_be))) | - (addr_hit[12] & (|(CACHEPOOL_PERIPHERAL_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(CACHEPOOL_PERIPHERAL_PERMIT[13] & ~reg_be))) | - (addr_hit[14] & (|(CACHEPOOL_PERIPHERAL_PERMIT[14] & ~reg_be))) | - (addr_hit[15] & (|(CACHEPOOL_PERIPHERAL_PERMIT[15] & ~reg_be))) | - (addr_hit[16] & (|(CACHEPOOL_PERIPHERAL_PERMIT[16] & ~reg_be))))); - end + addr_hit[157]: begin + reg_rdata_next[0] = lp1_cmo_commit_12_qs; + end - assign hw_barrier_re = addr_hit[0] & reg_re & !reg_error; + addr_hit[158]: begin + reg_rdata_next[0] = lp1_cmo_commit_13_qs; + end - assign icache_prefetch_enable_we = addr_hit[1] & reg_we & !reg_error; - assign icache_prefetch_enable_wd = reg_wdata[0]; + addr_hit[159]: begin + reg_rdata_next[0] = lp1_cmo_commit_14_qs; + end - assign spatz_status_we = addr_hit[2] & reg_we & !reg_error; - assign spatz_status_wd = reg_wdata[0]; + addr_hit[160]: begin + reg_rdata_next[0] = lp1_cmo_commit_15_qs; + end - assign spatz_cycle_we = addr_hit[3] & reg_we & !reg_error; - assign spatz_cycle_wd = reg_wdata[31:0]; + addr_hit[161]: begin + reg_rdata_next[0] = lp1_cmo_commit_16_qs; + end - assign cluster_boot_control_we = addr_hit[4] & reg_we & !reg_error; - assign cluster_boot_control_wd = reg_wdata[31:0]; + addr_hit[162]: begin + reg_rdata_next[0] = lp1_cmo_commit_17_qs; + end - assign cluster_eoc_exit_we = addr_hit[5] & reg_we & !reg_error; - assign cluster_eoc_exit_wd = reg_wdata[3:0]; + addr_hit[163]: begin + reg_rdata_next[0] = lp1_cmo_commit_18_qs; + end - assign cfg_l1d_spm_we = addr_hit[6] & reg_we & !reg_error; - assign cfg_l1d_spm_wd = reg_wdata[9:0]; + addr_hit[164]: begin + reg_rdata_next[0] = lp1_cmo_commit_19_qs; + end - assign cfg_l1d_insn_we = addr_hit[7] & reg_we & !reg_error; - assign cfg_l1d_insn_wd = reg_wdata[1:0]; + addr_hit[165]: begin + reg_rdata_next[0] = lp1_cmo_commit_20_qs; + end - assign cfg_l1d_tile_sel_0_we = addr_hit[8] & reg_we & !reg_error; - assign cfg_l1d_tile_sel_0_wd = reg_wdata[31:0]; + addr_hit[166]: begin + reg_rdata_next[0] = lp1_cmo_commit_21_qs; + end - assign cfg_l1d_tile_sel_1_we = addr_hit[9] & reg_we & !reg_error; - assign cfg_l1d_tile_sel_1_wd = reg_wdata[31:0]; + addr_hit[167]: begin + reg_rdata_next[0] = lp1_cmo_commit_22_qs; + end - assign l1d_spm_commit_we = addr_hit[10] & reg_we & !reg_error; - assign l1d_spm_commit_wd = reg_wdata[0]; + addr_hit[168]: begin + reg_rdata_next[0] = lp1_cmo_commit_23_qs; + end - assign l1d_insn_commit_we = addr_hit[11] & reg_we & !reg_error; - assign l1d_insn_commit_wd = reg_wdata[0]; + addr_hit[169]: begin + reg_rdata_next[0] = lp1_cmo_commit_24_qs; + end - assign l1d_flush_status_re = addr_hit[12] & reg_re & !reg_error; + addr_hit[170]: begin + reg_rdata_next[0] = lp1_cmo_commit_25_qs; + end - assign l1d_private_we = addr_hit[13] & reg_we & !reg_error; - assign l1d_private_wd = reg_wdata[3:0]; + addr_hit[171]: begin + reg_rdata_next[0] = lp1_cmo_commit_26_qs; + end - assign l1d_addr_we = addr_hit[14] & reg_we & !reg_error; - assign l1d_addr_wd = reg_wdata[31:0]; + addr_hit[172]: begin + reg_rdata_next[0] = lp1_cmo_commit_27_qs; + end - assign xbar_offset_we = addr_hit[15] & reg_we & !reg_error; - assign xbar_offset_wd = reg_wdata[4:0]; + addr_hit[173]: begin + reg_rdata_next[0] = lp1_cmo_commit_28_qs; + end - assign xbar_offset_commit_we = addr_hit[16] & reg_we & !reg_error; - assign xbar_offset_commit_wd = reg_wdata[0]; + addr_hit[174]: begin + reg_rdata_next[0] = lp1_cmo_commit_29_qs; + end - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[31:0] = hw_barrier_qs; + addr_hit[175]: begin + reg_rdata_next[0] = lp1_cmo_commit_30_qs; end - addr_hit[1]: begin - reg_rdata_next[0] = '0; + addr_hit[176]: begin + reg_rdata_next[0] = lp1_cmo_commit_31_qs; end - addr_hit[2]: begin - reg_rdata_next[0] = '0; + addr_hit[177]: begin + reg_rdata_next[0] = lp1_cmo_commit_32_qs; end - addr_hit[3]: begin - reg_rdata_next[31:0] = spatz_cycle_qs; + addr_hit[178]: begin + reg_rdata_next[0] = lp1_cmo_commit_33_qs; end - addr_hit[4]: begin - reg_rdata_next[31:0] = cluster_boot_control_qs; + addr_hit[179]: begin + reg_rdata_next[0] = lp1_cmo_commit_34_qs; end - addr_hit[5]: begin - reg_rdata_next[3:0] = cluster_eoc_exit_qs; + addr_hit[180]: begin + reg_rdata_next[0] = lp1_cmo_commit_35_qs; end - addr_hit[6]: begin - reg_rdata_next[9:0] = cfg_l1d_spm_qs; + addr_hit[181]: begin + reg_rdata_next[0] = lp1_cmo_commit_36_qs; end - addr_hit[7]: begin - reg_rdata_next[1:0] = cfg_l1d_insn_qs; + addr_hit[182]: begin + reg_rdata_next[0] = lp1_cmo_commit_37_qs; end - addr_hit[8]: begin - reg_rdata_next[31:0] = cfg_l1d_tile_sel_0_qs; + addr_hit[183]: begin + reg_rdata_next[0] = lp1_cmo_commit_38_qs; end - addr_hit[9]: begin - reg_rdata_next[31:0] = cfg_l1d_tile_sel_1_qs; + addr_hit[184]: begin + reg_rdata_next[0] = lp1_cmo_commit_39_qs; end - addr_hit[10]: begin - reg_rdata_next[0] = l1d_spm_commit_qs; + addr_hit[185]: begin + reg_rdata_next[0] = lp1_cmo_commit_40_qs; end - addr_hit[11]: begin - reg_rdata_next[0] = l1d_insn_commit_qs; + addr_hit[186]: begin + reg_rdata_next[0] = lp1_cmo_commit_41_qs; end - addr_hit[12]: begin - reg_rdata_next[0] = l1d_flush_status_qs; + addr_hit[187]: begin + reg_rdata_next[0] = lp1_cmo_commit_42_qs; end - addr_hit[13]: begin - reg_rdata_next[3:0] = l1d_private_qs; + addr_hit[188]: begin + reg_rdata_next[0] = lp1_cmo_commit_43_qs; end - addr_hit[14]: begin - reg_rdata_next[31:0] = l1d_addr_qs; + addr_hit[189]: begin + reg_rdata_next[0] = lp1_cmo_commit_44_qs; end - addr_hit[15]: begin - reg_rdata_next[4:0] = xbar_offset_qs; + addr_hit[190]: begin + reg_rdata_next[0] = lp1_cmo_commit_45_qs; end - addr_hit[16]: begin - reg_rdata_next[0] = xbar_offset_commit_qs; + addr_hit[191]: begin + reg_rdata_next[0] = lp1_cmo_commit_46_qs; + end + + addr_hit[192]: begin + reg_rdata_next[0] = lp1_cmo_commit_47_qs; + end + + addr_hit[193]: begin + reg_rdata_next[0] = lp1_cmo_commit_48_qs; + end + + addr_hit[194]: begin + reg_rdata_next[0] = lp1_cmo_commit_49_qs; + end + + addr_hit[195]: begin + reg_rdata_next[0] = lp1_cmo_commit_50_qs; + end + + addr_hit[196]: begin + reg_rdata_next[0] = lp1_cmo_commit_51_qs; + end + + addr_hit[197]: begin + reg_rdata_next[0] = lp1_cmo_commit_52_qs; + end + + addr_hit[198]: begin + reg_rdata_next[0] = lp1_cmo_commit_53_qs; + end + + addr_hit[199]: begin + reg_rdata_next[0] = lp1_cmo_commit_54_qs; + end + + addr_hit[200]: begin + reg_rdata_next[0] = lp1_cmo_commit_55_qs; + end + + addr_hit[201]: begin + reg_rdata_next[0] = lp1_cmo_commit_56_qs; + end + + addr_hit[202]: begin + reg_rdata_next[0] = lp1_cmo_commit_57_qs; + end + + addr_hit[203]: begin + reg_rdata_next[0] = lp1_cmo_commit_58_qs; + end + + addr_hit[204]: begin + reg_rdata_next[0] = lp1_cmo_commit_59_qs; + end + + addr_hit[205]: begin + reg_rdata_next[0] = lp1_cmo_commit_60_qs; + end + + addr_hit[206]: begin + reg_rdata_next[0] = lp1_cmo_commit_61_qs; + end + + addr_hit[207]: begin + reg_rdata_next[0] = lp1_cmo_commit_62_qs; + end + + addr_hit[208]: begin + reg_rdata_next[0] = lp1_cmo_commit_63_qs; + end + + addr_hit[209]: begin + reg_rdata_next[0] = lp1_cmo_status_0_qs; + end + + addr_hit[210]: begin + reg_rdata_next[0] = lp1_cmo_status_1_qs; + end + + addr_hit[211]: begin + reg_rdata_next[0] = lp1_cmo_status_2_qs; + end + + addr_hit[212]: begin + reg_rdata_next[0] = lp1_cmo_status_3_qs; + end + + addr_hit[213]: begin + reg_rdata_next[0] = lp1_cmo_status_4_qs; + end + + addr_hit[214]: begin + reg_rdata_next[0] = lp1_cmo_status_5_qs; + end + + addr_hit[215]: begin + reg_rdata_next[0] = lp1_cmo_status_6_qs; + end + + addr_hit[216]: begin + reg_rdata_next[0] = lp1_cmo_status_7_qs; + end + + addr_hit[217]: begin + reg_rdata_next[0] = lp1_cmo_status_8_qs; + end + + addr_hit[218]: begin + reg_rdata_next[0] = lp1_cmo_status_9_qs; + end + + addr_hit[219]: begin + reg_rdata_next[0] = lp1_cmo_status_10_qs; + end + + addr_hit[220]: begin + reg_rdata_next[0] = lp1_cmo_status_11_qs; + end + + addr_hit[221]: begin + reg_rdata_next[0] = lp1_cmo_status_12_qs; + end + + addr_hit[222]: begin + reg_rdata_next[0] = lp1_cmo_status_13_qs; + end + + addr_hit[223]: begin + reg_rdata_next[0] = lp1_cmo_status_14_qs; + end + + addr_hit[224]: begin + reg_rdata_next[0] = lp1_cmo_status_15_qs; + end + + addr_hit[225]: begin + reg_rdata_next[0] = lp1_cmo_status_16_qs; + end + + addr_hit[226]: begin + reg_rdata_next[0] = lp1_cmo_status_17_qs; + end + + addr_hit[227]: begin + reg_rdata_next[0] = lp1_cmo_status_18_qs; + end + + addr_hit[228]: begin + reg_rdata_next[0] = lp1_cmo_status_19_qs; + end + + addr_hit[229]: begin + reg_rdata_next[0] = lp1_cmo_status_20_qs; + end + + addr_hit[230]: begin + reg_rdata_next[0] = lp1_cmo_status_21_qs; + end + + addr_hit[231]: begin + reg_rdata_next[0] = lp1_cmo_status_22_qs; + end + + addr_hit[232]: begin + reg_rdata_next[0] = lp1_cmo_status_23_qs; + end + + addr_hit[233]: begin + reg_rdata_next[0] = lp1_cmo_status_24_qs; + end + + addr_hit[234]: begin + reg_rdata_next[0] = lp1_cmo_status_25_qs; + end + + addr_hit[235]: begin + reg_rdata_next[0] = lp1_cmo_status_26_qs; + end + + addr_hit[236]: begin + reg_rdata_next[0] = lp1_cmo_status_27_qs; + end + + addr_hit[237]: begin + reg_rdata_next[0] = lp1_cmo_status_28_qs; + end + + addr_hit[238]: begin + reg_rdata_next[0] = lp1_cmo_status_29_qs; + end + + addr_hit[239]: begin + reg_rdata_next[0] = lp1_cmo_status_30_qs; + end + + addr_hit[240]: begin + reg_rdata_next[0] = lp1_cmo_status_31_qs; + end + + addr_hit[241]: begin + reg_rdata_next[0] = lp1_cmo_status_32_qs; + end + + addr_hit[242]: begin + reg_rdata_next[0] = lp1_cmo_status_33_qs; + end + + addr_hit[243]: begin + reg_rdata_next[0] = lp1_cmo_status_34_qs; + end + + addr_hit[244]: begin + reg_rdata_next[0] = lp1_cmo_status_35_qs; + end + + addr_hit[245]: begin + reg_rdata_next[0] = lp1_cmo_status_36_qs; + end + + addr_hit[246]: begin + reg_rdata_next[0] = lp1_cmo_status_37_qs; + end + + addr_hit[247]: begin + reg_rdata_next[0] = lp1_cmo_status_38_qs; + end + + addr_hit[248]: begin + reg_rdata_next[0] = lp1_cmo_status_39_qs; + end + + addr_hit[249]: begin + reg_rdata_next[0] = lp1_cmo_status_40_qs; + end + + addr_hit[250]: begin + reg_rdata_next[0] = lp1_cmo_status_41_qs; + end + + addr_hit[251]: begin + reg_rdata_next[0] = lp1_cmo_status_42_qs; + end + + addr_hit[252]: begin + reg_rdata_next[0] = lp1_cmo_status_43_qs; + end + + addr_hit[253]: begin + reg_rdata_next[0] = lp1_cmo_status_44_qs; + end + + addr_hit[254]: begin + reg_rdata_next[0] = lp1_cmo_status_45_qs; + end + + addr_hit[255]: begin + reg_rdata_next[0] = lp1_cmo_status_46_qs; + end + + addr_hit[256]: begin + reg_rdata_next[0] = lp1_cmo_status_47_qs; + end + + addr_hit[257]: begin + reg_rdata_next[0] = lp1_cmo_status_48_qs; + end + + addr_hit[258]: begin + reg_rdata_next[0] = lp1_cmo_status_49_qs; + end + + addr_hit[259]: begin + reg_rdata_next[0] = lp1_cmo_status_50_qs; + end + + addr_hit[260]: begin + reg_rdata_next[0] = lp1_cmo_status_51_qs; + end + + addr_hit[261]: begin + reg_rdata_next[0] = lp1_cmo_status_52_qs; + end + + addr_hit[262]: begin + reg_rdata_next[0] = lp1_cmo_status_53_qs; + end + + addr_hit[263]: begin + reg_rdata_next[0] = lp1_cmo_status_54_qs; + end + + addr_hit[264]: begin + reg_rdata_next[0] = lp1_cmo_status_55_qs; + end + + addr_hit[265]: begin + reg_rdata_next[0] = lp1_cmo_status_56_qs; + end + + addr_hit[266]: begin + reg_rdata_next[0] = lp1_cmo_status_57_qs; + end + + addr_hit[267]: begin + reg_rdata_next[0] = lp1_cmo_status_58_qs; + end + + addr_hit[268]: begin + reg_rdata_next[0] = lp1_cmo_status_59_qs; + end + + addr_hit[269]: begin + reg_rdata_next[0] = lp1_cmo_status_60_qs; + end + + addr_hit[270]: begin + reg_rdata_next[0] = lp1_cmo_status_61_qs; + end + + addr_hit[271]: begin + reg_rdata_next[0] = lp1_cmo_status_62_qs; + end + + addr_hit[272]: begin + reg_rdata_next[0] = lp1_cmo_status_63_qs; end default: begin @@ -745,7 +9905,7 @@ endmodule module cachepool_peripheral_reg_top_intf #( - parameter int AW = 7, + parameter int AW = 11, localparam int DW = 32 ) ( input logic clk_i, diff --git a/hardware/src/cachepool_cluster.sv b/hardware/src/cachepool_cluster.sv index e75ff20..775ab9c 100644 --- a/hardware/src/cachepool_cluster.sv +++ b/hardware/src/cachepool_cluster.sv @@ -202,6 +202,10 @@ module cachepool_cluster logic [NumTiles-1:0] l1d_insn_ready; logic [NumTiles-1:0] l1d_busy; logic [$clog2(NumL1CtrlTile):0] l1d_private; + // Per-core private-L1 (LP1) CMO injector bundle (one slot per core). + lp1_cmo_req_t [NumCores-1:0] lp1_cmo_req; + logic [NumCores-1:0] lp1_cmo_valid; + logic [NumCores-1:0] lp1_cmo_done; // Per-group error signals. logic [NumGroups-1:0] group_error; @@ -298,6 +302,9 @@ module cachepool_cluster .l1d_insn_valid_i ( l1d_insn_valid ), .l1d_insn_ready_o ( l1d_insn_ready[g*NumTilesPerGroup +: NumTilesPerGroup]), .l1d_busy_i ( l1d_busy [g*NumTilesPerGroup +: NumTilesPerGroup]), + .lp1_cmo_req_i ( lp1_cmo_req [g*NumCoreGroup +: NumCoreGroup] ), + .lp1_cmo_valid_i ( lp1_cmo_valid[g*NumCoreGroup +: NumCoreGroup] ), + .lp1_cmo_done_o ( lp1_cmo_done [g*NumCoreGroup +: NumCoreGroup] ), .group_xy_id_i ( group_xy_id_t'{x: gx, y: gy, port_id: 1'b0} ), @@ -756,9 +763,11 @@ module cachepool_cluster .AddrWidth (AxiAddrWidth ), .SPMWidth ($clog2(L1NumSet)), .NumTiles (NumTiles ), + .NumCores (NumCores ), .reg_req_t (reg_req_t ), .reg_rsp_t (reg_rsp_t ), - .cache_insn_t (cache_insn_t ) + .cache_insn_t (cache_insn_t ), + .lp1_cmo_req_t (lp1_cmo_req_t ) ) i_cachepool_cluster_peripheral ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -778,7 +787,10 @@ module cachepool_cluster .l1d_insn_o (l1d_insn ), .l1d_insn_valid_o (l1d_insn_valid ), .l1d_insn_ready_i (l1d_insn_ready ), - .l1d_busy_o (l1d_busy ) + .l1d_busy_o (l1d_busy ), + .lp1_cmo_req_o (lp1_cmo_req ), + .lp1_cmo_valid_o (lp1_cmo_valid ), + .lp1_cmo_done_i (lp1_cmo_done ) ); endmodule diff --git a/hardware/src/cachepool_group.sv b/hardware/src/cachepool_group.sv index 016b25a..06c9b0f 100644 --- a/hardware/src/cachepool_group.sv +++ b/hardware/src/cachepool_group.sv @@ -151,6 +151,10 @@ module cachepool_group input logic l1d_insn_valid_i, output logic [NumTilesPerGroup-1:0] l1d_insn_ready_o, input logic [NumTilesPerGroup-1:0] l1d_busy_i, + // Per-core private-L1 (LP1) CMO injector interface (one slot per core in group). + input lp1_cmo_req_t [NumCoreGroup-1:0] lp1_cmo_req_i, + input logic [NumCoreGroup-1:0] lp1_cmo_valid_i, + output logic [NumCoreGroup-1:0] lp1_cmo_done_o, /// Inter-group remote access ports (to other groups). /// Layout: [NumTilesPerGroup-1:0][NumRemoteGroupPortTile-1:0] flattened to @@ -804,7 +808,10 @@ module cachepool_group .l1d_private_i ( l1d_private_i ), .l1d_insn_valid_i ( l1d_insn_valid_i ), .l1d_insn_ready_o ( l1d_insn_ready_o [t] ), - .l1d_busy_i ( l1d_busy_i [t] ) + .l1d_busy_i ( l1d_busy_i [t] ), + .lp1_cmo_req_i ( lp1_cmo_req_i [t*NumCoresTile +: NumCoresTile] ), + .lp1_cmo_valid_i ( lp1_cmo_valid_i [t*NumCoresTile +: NumCoresTile] ), + .lp1_cmo_done_o ( lp1_cmo_done_o [t*NumCoresTile +: NumCoresTile] ) ); end else begin : gen_tile cachepool_tile #( @@ -890,7 +897,10 @@ module cachepool_group .l1d_private_i ( l1d_private_i ), .l1d_insn_valid_i ( l1d_insn_valid_i ), .l1d_insn_ready_o ( l1d_insn_ready_o [t] ), - .l1d_busy_i ( l1d_busy_i [t] ) + .l1d_busy_i ( l1d_busy_i [t] ), + .lp1_cmo_req_i ( lp1_cmo_req_i [t*NumCoresTile +: NumCoresTile] ), + .lp1_cmo_valid_i ( lp1_cmo_valid_i [t*NumCoresTile +: NumCoresTile] ), + .lp1_cmo_done_o ( lp1_cmo_done_o [t*NumCoresTile +: NumCoresTile] ) ); end end diff --git a/hardware/src/cachepool_group_noc_wrapper.sv b/hardware/src/cachepool_group_noc_wrapper.sv index 735ef9b..8566da2 100644 --- a/hardware/src/cachepool_group_noc_wrapper.sv +++ b/hardware/src/cachepool_group_noc_wrapper.sv @@ -79,6 +79,10 @@ module cachepool_group_noc_wrapper input logic l1d_insn_valid_i, output logic [NumTilesPerGroup-1:0] l1d_insn_ready_o, input logic [NumTilesPerGroup-1:0] l1d_busy_i, + // Per-core private-L1 (LP1) CMO injector interface (one slot per core in group). + input lp1_cmo_req_t [NumCoreGroup-1:0] lp1_cmo_req_i, + input logic [NumCoreGroup-1:0] lp1_cmo_valid_i, + output logic [NumCoreGroup-1:0] lp1_cmo_done_o, input impl_in_t [NrSramCfg-1:0] impl_i, output logic error_o, // XY coordinates of this group in the inter-group mesh @@ -595,7 +599,10 @@ module cachepool_group_noc_wrapper .l1d_insn_i ( l1d_insn_i ), .l1d_insn_valid_i ( l1d_insn_valid_i ), .l1d_insn_ready_o ( l1d_insn_ready_o ), - .l1d_busy_i ( l1d_busy_i ) + .l1d_busy_i ( l1d_busy_i ), + .lp1_cmo_req_i ( lp1_cmo_req_i ), + .lp1_cmo_valid_i ( lp1_cmo_valid_i ), + .lp1_cmo_done_o ( lp1_cmo_done_o ) ); endmodule diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv index aa891a4..50139fa 100644 --- a/hardware/src/cachepool_l1_ctrl.sv +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -23,6 +23,12 @@ // Coalescer metadata has no package; all coalescer-facing types (tcdm_meta_t, // downstream_info_t, word_offset_t, ...) are defined at the tile and passed in // as parameters. +`include "axi/typedef.svh" +`include "common_cells/assertions.svh" +`include "common_cells/registers.svh" +`include "reqrsp_interface/typedef.svh" +`include "snitch_vm/typedef.svh" +`include "hpdcache_typedef.svh" module cachepool_l1_ctrl import cachepool_pkg::*; @@ -81,6 +87,14 @@ module cachepool_l1_ctrl input logic rst_ni, input logic wbuf_flush_i, + // Per-core CMO injector interface (driven by the cluster peripheral). + // lp1_cmo_valid_i pulses for one cycle to request the CMO in lp1_cmo_req_i; + // lp1_cmo_done_o pulses when the CMO has completed (used to clear the + // peripheral's per-core busy/status bit). FSM implemented in Task 3. + input lp1_cmo_req_t lp1_cmo_req_i, + input logic lp1_cmo_valid_i, + output logic lp1_cmo_done_o, + // Core-side TCDM interface (Spatz lanes [0..NrLP1CoalInputs-1] + Snitch [last]). // Request handshake : core_req_i.q_valid / core_req_ready_o // Response handshake: core_rsp_o.p_valid / core_rsp_ready_i @@ -433,6 +447,86 @@ module cachepool_l1_ctrl assign l1_req_valid[1] = core_req_i[SnitchPort].q_valid; assign cache_req_ready[SnitchPort] = l1_req_ready[1]; + ////////////////////////////////////////// + // HPDcache requester 2 (CMO injector) // + ////////////////////////////////////////// + // Converts the peripheral's one-cycle lp1_cmo_valid_i pulse into an HPDcache + // CMO on requester port 2, then reports completion via lp1_cmo_done_o (which + // clears the peripheral's per-core busy/status bit). Single outstanding CMO + // per core (the peripheral won't issue a new one until done), so no flow + // control is needed on the incoming pulse -- it is latched here. + // + // IDLE : wait for lp1_cmo_valid_i; decode + latch op/addr. + // REQ : hold l1_req_valid[2] until l1_req_ready[2] accepts the request. + // RESP : wait for l1_rsp_valid[2]; pulse lp1_cmo_done_o; return to IDLE. + // + // lp1_cmo_req_i.op encoding (from the peripheral register block): + // 0 = FENCE (write-through WBUF drain), 1 = INVAL_ALL, 2 = INVAL_NLINE + localparam int unsigned CmoReqId = 2; + + typedef enum logic [1:0] { CMO_IDLE, CMO_REQ, CMO_RESP } cmo_state_e; + cmo_state_e cmo_state_q, cmo_state_d; + hpdcache_req_op_t cmo_op_q, cmo_op_d; + logic [31:0] cmo_addr_q, cmo_addr_d; + + // Translate the peripheral op code into the HPDcache CMO request op. + function automatic hpdcache_req_op_t cmo_decode(input logic [2:0] op); + case (op) + 3'd0: cmo_decode = HPDCACHE_REQ_CMO_FENCE; + 3'd1: cmo_decode = HPDCACHE_REQ_CMO_INVAL_ALL; + 3'd2: cmo_decode = HPDCACHE_REQ_CMO_INVAL_NLINE; + default: cmo_decode = HPDCACHE_REQ_CMO_FENCE; + endcase + endfunction + + always_comb begin : gen_l1_req_cmo + cmo_state_d = cmo_state_q; + cmo_op_d = cmo_op_q; + cmo_addr_d = cmo_addr_q; + lp1_cmo_done_o = 1'b0; + + // Compose the CMO request (INVAL_NLINE uses addr; FENCE/INVAL_ALL ignore it). + l1_req[CmoReqId] = '0; + l1_req[CmoReqId].op = cmo_op_q; + l1_req[CmoReqId].addr_offset = cmo_addr_q[HPDcacheCfg.reqOffsetWidth-1:0]; + l1_req[CmoReqId].addr_tag = cmo_addr_q[HPDcacheCfg.reqOffsetWidth +: HPDcacheCfg.tagWidth]; + l1_req[CmoReqId].sid = hpdcache_req_sid_t'(CmoReqId); + l1_req[CmoReqId].tid = '0; + l1_req[CmoReqId].need_rsp = 1'b1; // required: how we learn it completed + l1_req[CmoReqId].phys_indexed = 1'b1; + l1_req[CmoReqId].pma.uncacheable = 1'b0; + l1_req[CmoReqId].pma.io = 1'b0; + l1_req[CmoReqId].pma.wr_policy_hint = HPDCACHE_WR_POLICY_WT; + l1_req_valid[CmoReqId] = 1'b0; + + unique case (cmo_state_q) + CMO_IDLE: begin + if (lp1_cmo_valid_i) begin + cmo_op_d = cmo_decode(lp1_cmo_req_i.op); + cmo_addr_d = lp1_cmo_req_i.addr; + cmo_state_d = CMO_REQ; + end + end + CMO_REQ: begin + l1_req_valid[CmoReqId] = 1'b1; + if (l1_req_ready[CmoReqId]) begin + cmo_state_d = CMO_RESP; + end + end + CMO_RESP: begin + if (l1_rsp_valid[CmoReqId]) begin + lp1_cmo_done_o = 1'b1; + cmo_state_d = CMO_IDLE; + end + end + default: cmo_state_d = CMO_IDLE; + endcase + end + + `FF(cmo_state_q, cmo_state_d, CMO_IDLE, clk_i, rst_ni) + `FF(cmo_op_q, cmo_op_d, HPDCACHE_REQ_CMO_FENCE, clk_i, rst_ni) + `FF(cmo_addr_q, cmo_addr_d, '0, clk_i, rst_ni) + /////////////////////////////// // Spatz response scatter // /////////////////////////////// diff --git a/hardware/src/cachepool_pkg.sv b/hardware/src/cachepool_pkg.sv index b75f041..ca5162b 100644 --- a/hardware/src/cachepool_pkg.sv +++ b/hardware/src/cachepool_pkg.sv @@ -432,6 +432,15 @@ package cachepool_pkg; logic [NumTiles-1:0] tile_sel; } cache_insn_t; + // Per-core private-L1 (LP1) CMO request, driven by the peripheral to each + // core's cachepool_l1_ctrl injector. + // op: 0 = FENCE (write-through WBUF drain), 1 = INVAL_ALL, 2 = INVAL_NLINE + // addr: cacheline address for INVAL_NLINE (ignored for FENCE / INVAL_ALL) + typedef struct packed { + logic [2:0] op; + logic [31:0] addr; + } lp1_cmo_req_t; + typedef struct packed { logic for_write_pend; cache_ways_entry_ptr_t depth; diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index 516a0e3..1a15824 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -185,6 +185,10 @@ module cachepool_tile input logic l1d_insn_valid_i, output logic l1d_insn_ready_o, input logic l1d_busy_i, + // Per-core private-L1 (LP1) CMO injector interface (one slot per core). + input lp1_cmo_req_t [NumCoresTile-1:0] lp1_cmo_req_i, + input logic [NumCoresTile-1:0] lp1_cmo_valid_i, + output logic [NumCoresTile-1:0] lp1_cmo_done_o, @@ -321,7 +325,7 @@ module cachepool_tile localparam int unsigned LP1CoalInfoWidth = LP1ExtPorts + LP1ExtPorts*LP1NrBitsCoalOffset; localparam int unsigned LP1ReqIdWidth = $clog2(NumSpatzOutstandingLoads); localparam int unsigned LP1TidWidth = CoreIDWidth + TileIDWidth + LP1ReqIdWidth + 2 + LP1CoalInfoWidth; // +2: is_fpu, write; tile_id+core_id round-tripped - localparam int unsigned LP1NrRequesters = 2; // Snitch + Spatz(coalesced) + localparam int unsigned LP1NrRequesters = 3; // Spatz(coalesced) + Snitch + CMO injector localparam hpdcache_pkg::hpdcache_user_cfg_t HPDcacheUserCfg = '{ nRequesters: LP1NrRequesters, @@ -332,7 +336,7 @@ module cachepool_tile clWords: 4, reqWords: 1, reqTransIdWidth: LP1TidWidth + LP1NumWordOffsetBits, - reqSrcIdWidth: 1, // selects requester port (0 Spatz / 1 Snitch) + reqSrcIdWidth: $clog2(LP1NrRequesters), // selects requester port (0 Spatz / 1 Snitch / 2 CMO) victimSel: hpdcache_pkg::HPDCACHE_VICTIM_PLRU, dataWaysPerRamWord: 1, dataSetsPerRam: 32, @@ -785,6 +789,11 @@ module cachepool_tile .rst_ni (rst_ni ), .wbuf_flush_i (1'b0 ), + // Per-core CMO injector (slot c = this core) + .lp1_cmo_req_i (lp1_cmo_req_i [c]), + .lp1_cmo_valid_i (lp1_cmo_valid_i [c]), + .lp1_cmo_done_o (lp1_cmo_done_o [c]), + // Core side (NrTCDMPortsPerCore narrow TCDM ports for this core) .core_req_i (cache_req_transposed [c]), .core_rsp_o (cache_rsp_transposed [c]), diff --git a/software/snRuntime/include/cachepool_peripheral.h b/software/snRuntime/include/cachepool_peripheral.h index 5a26778..9f347ab 100644 --- a/software/snRuntime/include/cachepool_peripheral.h +++ b/software/snRuntime/include/cachepool_peripheral.h @@ -17,6 +17,9 @@ extern "C" { // (16 groups x 4 tiles). #define CACHEPOOL_PERIPHERAL_PARAM_NUM_TILE_SEL_REGS 2 +// Number of per-core LP1 (private-L1) CMO register slots -- one per core / +#define CACHEPOOL_PERIPHERAL_PARAM_NUM_LP1_CMO_REGS 64 + // Register width #define CACHEPOOL_PERIPHERAL_PARAM_REG_WIDTH 32 @@ -113,6 +116,1306 @@ extern "C" { #define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_REG_OFFSET 0x40 #define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_COMMIT_BIT 0 +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_OP_FIELD_WIDTH 3 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_OP_FIELDS_PER_REG 10 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_MULTIREG_COUNT 64 + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_REG_OFFSET 0x44 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_OP_0_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_OP_0_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_OP_0_FIELD \ + ((bitfield_field32_t){.mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_OP_0_MASK, \ + .index = \ + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_OP_0_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_REG_OFFSET 0x48 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_OP_1_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_OP_1_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_OP_1_FIELD \ + ((bitfield_field32_t){.mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_OP_1_MASK, \ + .index = \ + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_OP_1_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_REG_OFFSET 0x4c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_OP_2_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_OP_2_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_OP_2_FIELD \ + ((bitfield_field32_t){.mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_OP_2_MASK, \ + .index = \ + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_OP_2_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_REG_OFFSET 0x50 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_OP_3_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_OP_3_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_OP_3_FIELD \ + ((bitfield_field32_t){.mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_OP_3_MASK, \ + .index = \ + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_OP_3_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_REG_OFFSET 0x54 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_OP_4_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_OP_4_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_OP_4_FIELD \ + ((bitfield_field32_t){.mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_OP_4_MASK, \ + .index = \ + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_OP_4_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_REG_OFFSET 0x58 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_OP_5_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_OP_5_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_OP_5_FIELD \ + ((bitfield_field32_t){.mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_OP_5_MASK, \ + .index = \ + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_OP_5_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_REG_OFFSET 0x5c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_OP_6_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_OP_6_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_OP_6_FIELD \ + ((bitfield_field32_t){.mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_OP_6_MASK, \ + .index = \ + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_OP_6_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_REG_OFFSET 0x60 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_OP_7_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_OP_7_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_OP_7_FIELD \ + ((bitfield_field32_t){.mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_OP_7_MASK, \ + .index = \ + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_OP_7_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_REG_OFFSET 0x64 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_OP_8_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_OP_8_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_OP_8_FIELD \ + ((bitfield_field32_t){.mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_OP_8_MASK, \ + .index = \ + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_OP_8_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_REG_OFFSET 0x68 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_OP_9_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_OP_9_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_OP_9_FIELD \ + ((bitfield_field32_t){.mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_OP_9_MASK, \ + .index = \ + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_OP_9_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_REG_OFFSET 0x6c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_OP_10_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_OP_10_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_OP_10_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_OP_10_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_OP_10_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_REG_OFFSET 0x70 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_OP_11_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_OP_11_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_OP_11_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_OP_11_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_OP_11_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_REG_OFFSET 0x74 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_OP_12_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_OP_12_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_OP_12_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_OP_12_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_OP_12_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_REG_OFFSET 0x78 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_OP_13_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_OP_13_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_OP_13_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_OP_13_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_OP_13_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_REG_OFFSET 0x7c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_OP_14_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_OP_14_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_OP_14_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_OP_14_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_OP_14_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_REG_OFFSET 0x80 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_OP_15_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_OP_15_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_OP_15_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_OP_15_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_OP_15_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_REG_OFFSET 0x84 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_OP_16_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_OP_16_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_OP_16_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_OP_16_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_OP_16_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_REG_OFFSET 0x88 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_OP_17_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_OP_17_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_OP_17_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_OP_17_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_OP_17_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_REG_OFFSET 0x8c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_OP_18_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_OP_18_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_OP_18_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_OP_18_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_OP_18_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_REG_OFFSET 0x90 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_OP_19_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_OP_19_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_OP_19_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_OP_19_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_OP_19_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_REG_OFFSET 0x94 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_OP_20_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_OP_20_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_OP_20_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_OP_20_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_OP_20_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_REG_OFFSET 0x98 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_OP_21_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_OP_21_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_OP_21_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_OP_21_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_OP_21_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_REG_OFFSET 0x9c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_OP_22_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_OP_22_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_OP_22_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_OP_22_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_OP_22_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_REG_OFFSET 0xa0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_OP_23_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_OP_23_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_OP_23_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_OP_23_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_OP_23_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_REG_OFFSET 0xa4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_OP_24_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_OP_24_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_OP_24_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_OP_24_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_OP_24_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_REG_OFFSET 0xa8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_OP_25_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_OP_25_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_OP_25_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_OP_25_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_OP_25_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_REG_OFFSET 0xac +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_OP_26_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_OP_26_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_OP_26_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_OP_26_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_OP_26_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_REG_OFFSET 0xb0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_OP_27_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_OP_27_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_OP_27_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_OP_27_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_OP_27_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_REG_OFFSET 0xb4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_OP_28_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_OP_28_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_OP_28_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_OP_28_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_OP_28_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_REG_OFFSET 0xb8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_OP_29_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_OP_29_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_OP_29_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_OP_29_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_OP_29_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_REG_OFFSET 0xbc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_OP_30_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_OP_30_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_OP_30_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_OP_30_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_OP_30_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_REG_OFFSET 0xc0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_OP_31_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_OP_31_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_OP_31_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_OP_31_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_OP_31_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_REG_OFFSET 0xc4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_OP_32_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_OP_32_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_OP_32_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_OP_32_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_OP_32_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_REG_OFFSET 0xc8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_OP_33_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_OP_33_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_OP_33_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_OP_33_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_OP_33_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_REG_OFFSET 0xcc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_OP_34_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_OP_34_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_OP_34_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_OP_34_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_OP_34_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_REG_OFFSET 0xd0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_OP_35_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_OP_35_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_OP_35_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_OP_35_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_OP_35_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_REG_OFFSET 0xd4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_OP_36_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_OP_36_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_OP_36_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_OP_36_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_OP_36_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_REG_OFFSET 0xd8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_OP_37_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_OP_37_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_OP_37_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_OP_37_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_OP_37_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_REG_OFFSET 0xdc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_OP_38_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_OP_38_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_OP_38_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_OP_38_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_OP_38_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_REG_OFFSET 0xe0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_OP_39_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_OP_39_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_OP_39_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_OP_39_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_OP_39_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_REG_OFFSET 0xe4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_OP_40_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_OP_40_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_OP_40_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_OP_40_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_OP_40_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_REG_OFFSET 0xe8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_OP_41_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_OP_41_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_OP_41_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_OP_41_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_OP_41_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_REG_OFFSET 0xec +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_OP_42_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_OP_42_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_OP_42_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_OP_42_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_OP_42_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_REG_OFFSET 0xf0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_OP_43_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_OP_43_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_OP_43_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_OP_43_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_OP_43_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_REG_OFFSET 0xf4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_OP_44_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_OP_44_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_OP_44_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_OP_44_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_OP_44_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_REG_OFFSET 0xf8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_OP_45_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_OP_45_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_OP_45_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_OP_45_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_OP_45_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_REG_OFFSET 0xfc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_OP_46_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_OP_46_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_OP_46_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_OP_46_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_OP_46_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_REG_OFFSET 0x100 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_OP_47_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_OP_47_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_OP_47_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_OP_47_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_OP_47_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_REG_OFFSET 0x104 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_OP_48_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_OP_48_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_OP_48_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_OP_48_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_OP_48_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_REG_OFFSET 0x108 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_OP_49_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_OP_49_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_OP_49_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_OP_49_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_OP_49_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_REG_OFFSET 0x10c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_OP_50_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_OP_50_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_OP_50_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_OP_50_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_OP_50_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_REG_OFFSET 0x110 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_OP_51_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_OP_51_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_OP_51_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_OP_51_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_OP_51_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_REG_OFFSET 0x114 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_OP_52_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_OP_52_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_OP_52_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_OP_52_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_OP_52_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_REG_OFFSET 0x118 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_OP_53_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_OP_53_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_OP_53_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_OP_53_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_OP_53_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_REG_OFFSET 0x11c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_OP_54_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_OP_54_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_OP_54_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_OP_54_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_OP_54_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_REG_OFFSET 0x120 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_OP_55_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_OP_55_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_OP_55_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_OP_55_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_OP_55_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_REG_OFFSET 0x124 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_OP_56_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_OP_56_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_OP_56_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_OP_56_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_OP_56_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_REG_OFFSET 0x128 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_OP_57_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_OP_57_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_OP_57_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_OP_57_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_OP_57_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_REG_OFFSET 0x12c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_OP_58_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_OP_58_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_OP_58_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_OP_58_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_OP_58_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_REG_OFFSET 0x130 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_OP_59_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_OP_59_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_OP_59_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_OP_59_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_OP_59_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_REG_OFFSET 0x134 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_OP_60_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_OP_60_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_OP_60_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_OP_60_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_OP_60_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_REG_OFFSET 0x138 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_OP_61_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_OP_61_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_OP_61_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_OP_61_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_OP_61_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_REG_OFFSET 0x13c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_OP_62_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_OP_62_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_OP_62_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_OP_62_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_OP_62_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_REG_OFFSET 0x140 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OP_63_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OP_63_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OP_63_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OP_63_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OP_63_OFFSET}) + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_ADDR_FIELD_WIDTH 32 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_ADDR_FIELDS_PER_REG 1 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_MULTIREG_COUNT 64 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0_REG_OFFSET 0x144 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1_REG_OFFSET 0x148 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2_REG_OFFSET 0x14c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3_REG_OFFSET 0x150 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4_REG_OFFSET 0x154 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5_REG_OFFSET 0x158 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6_REG_OFFSET 0x15c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7_REG_OFFSET 0x160 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8_REG_OFFSET 0x164 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9_REG_OFFSET 0x168 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10_REG_OFFSET 0x16c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11_REG_OFFSET 0x170 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12_REG_OFFSET 0x174 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13_REG_OFFSET 0x178 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14_REG_OFFSET 0x17c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15_REG_OFFSET 0x180 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16_REG_OFFSET 0x184 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17_REG_OFFSET 0x188 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18_REG_OFFSET 0x18c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19_REG_OFFSET 0x190 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20_REG_OFFSET 0x194 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21_REG_OFFSET 0x198 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22_REG_OFFSET 0x19c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23_REG_OFFSET 0x1a0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24_REG_OFFSET 0x1a4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25_REG_OFFSET 0x1a8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26_REG_OFFSET 0x1ac + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27_REG_OFFSET 0x1b0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28_REG_OFFSET 0x1b4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29_REG_OFFSET 0x1b8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30_REG_OFFSET 0x1bc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31_REG_OFFSET 0x1c0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32_REG_OFFSET 0x1c4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33_REG_OFFSET 0x1c8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34_REG_OFFSET 0x1cc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35_REG_OFFSET 0x1d0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36_REG_OFFSET 0x1d4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37_REG_OFFSET 0x1d8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38_REG_OFFSET 0x1dc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39_REG_OFFSET 0x1e0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40_REG_OFFSET 0x1e4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41_REG_OFFSET 0x1e8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42_REG_OFFSET 0x1ec + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43_REG_OFFSET 0x1f0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44_REG_OFFSET 0x1f4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45_REG_OFFSET 0x1f8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46_REG_OFFSET 0x1fc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47_REG_OFFSET 0x200 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48_REG_OFFSET 0x204 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49_REG_OFFSET 0x208 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50_REG_OFFSET 0x20c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51_REG_OFFSET 0x210 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52_REG_OFFSET 0x214 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53_REG_OFFSET 0x218 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54_REG_OFFSET 0x21c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55_REG_OFFSET 0x220 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56_REG_OFFSET 0x224 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57_REG_OFFSET 0x228 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58_REG_OFFSET 0x22c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59_REG_OFFSET 0x230 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60_REG_OFFSET 0x234 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61_REG_OFFSET 0x238 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62_REG_OFFSET 0x23c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63_REG_OFFSET 0x240 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_COMMIT_FIELD_WIDTH 1 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_COMMIT_FIELDS_PER_REG 32 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_MULTIREG_COUNT 64 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_REG_OFFSET 0x244 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_COMMIT_0_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_REG_OFFSET 0x248 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_COMMIT_1_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_REG_OFFSET 0x24c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_COMMIT_2_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_REG_OFFSET 0x250 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_COMMIT_3_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_REG_OFFSET 0x254 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_COMMIT_4_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_REG_OFFSET 0x258 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_COMMIT_5_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_REG_OFFSET 0x25c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_COMMIT_6_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_REG_OFFSET 0x260 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_COMMIT_7_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_REG_OFFSET 0x264 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_COMMIT_8_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_REG_OFFSET 0x268 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_COMMIT_9_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_REG_OFFSET 0x26c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_COMMIT_10_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_REG_OFFSET 0x270 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_COMMIT_11_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_REG_OFFSET 0x274 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_COMMIT_12_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_REG_OFFSET 0x278 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_COMMIT_13_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_REG_OFFSET 0x27c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_COMMIT_14_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_REG_OFFSET 0x280 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_COMMIT_15_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_REG_OFFSET 0x284 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_COMMIT_16_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_REG_OFFSET 0x288 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_COMMIT_17_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_REG_OFFSET 0x28c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_COMMIT_18_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_REG_OFFSET 0x290 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_COMMIT_19_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_REG_OFFSET 0x294 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_COMMIT_20_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_REG_OFFSET 0x298 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_COMMIT_21_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_REG_OFFSET 0x29c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_COMMIT_22_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_REG_OFFSET 0x2a0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_COMMIT_23_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_REG_OFFSET 0x2a4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_COMMIT_24_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_REG_OFFSET 0x2a8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_COMMIT_25_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_REG_OFFSET 0x2ac +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_COMMIT_26_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_REG_OFFSET 0x2b0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_COMMIT_27_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_REG_OFFSET 0x2b4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_COMMIT_28_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_REG_OFFSET 0x2b8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_COMMIT_29_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_REG_OFFSET 0x2bc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_COMMIT_30_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_REG_OFFSET 0x2c0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_COMMIT_31_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_REG_OFFSET 0x2c4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_COMMIT_32_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_REG_OFFSET 0x2c8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_COMMIT_33_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_REG_OFFSET 0x2cc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_COMMIT_34_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_REG_OFFSET 0x2d0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_COMMIT_35_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_REG_OFFSET 0x2d4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_COMMIT_36_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_REG_OFFSET 0x2d8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_COMMIT_37_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_REG_OFFSET 0x2dc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_COMMIT_38_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_REG_OFFSET 0x2e0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_COMMIT_39_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_REG_OFFSET 0x2e4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_COMMIT_40_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_REG_OFFSET 0x2e8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_COMMIT_41_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_REG_OFFSET 0x2ec +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_COMMIT_42_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_REG_OFFSET 0x2f0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_COMMIT_43_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_REG_OFFSET 0x2f4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_COMMIT_44_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_REG_OFFSET 0x2f8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_COMMIT_45_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_REG_OFFSET 0x2fc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_COMMIT_46_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_REG_OFFSET 0x300 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_COMMIT_47_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_REG_OFFSET 0x304 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_COMMIT_48_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_REG_OFFSET 0x308 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_COMMIT_49_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_REG_OFFSET 0x30c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_COMMIT_50_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_REG_OFFSET 0x310 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_COMMIT_51_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_REG_OFFSET 0x314 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_COMMIT_52_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_REG_OFFSET 0x318 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_COMMIT_53_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_REG_OFFSET 0x31c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_COMMIT_54_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_REG_OFFSET 0x320 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_COMMIT_55_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_REG_OFFSET 0x324 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_COMMIT_56_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_REG_OFFSET 0x328 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_COMMIT_57_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_REG_OFFSET 0x32c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_COMMIT_58_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_REG_OFFSET 0x330 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_COMMIT_59_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_REG_OFFSET 0x334 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_COMMIT_60_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_REG_OFFSET 0x338 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_COMMIT_61_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_REG_OFFSET 0x33c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_COMMIT_62_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_REG_OFFSET 0x340 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_COMMIT_63_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_STATUS_FIELD_WIDTH 1 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_STATUS_FIELDS_PER_REG 32 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_MULTIREG_COUNT 64 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_REG_OFFSET 0x344 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_STATUS_0_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_REG_OFFSET 0x348 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_STATUS_1_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_REG_OFFSET 0x34c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_STATUS_2_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_REG_OFFSET 0x350 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_STATUS_3_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_REG_OFFSET 0x354 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_STATUS_4_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_REG_OFFSET 0x358 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_STATUS_5_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_REG_OFFSET 0x35c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_STATUS_6_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_REG_OFFSET 0x360 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_STATUS_7_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_REG_OFFSET 0x364 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_STATUS_8_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_REG_OFFSET 0x368 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_STATUS_9_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_REG_OFFSET 0x36c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_STATUS_10_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_REG_OFFSET 0x370 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_STATUS_11_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_REG_OFFSET 0x374 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_STATUS_12_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_REG_OFFSET 0x378 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_STATUS_13_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_REG_OFFSET 0x37c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_STATUS_14_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_REG_OFFSET 0x380 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_STATUS_15_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_REG_OFFSET 0x384 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_STATUS_16_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_REG_OFFSET 0x388 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_STATUS_17_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_REG_OFFSET 0x38c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_STATUS_18_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_REG_OFFSET 0x390 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_STATUS_19_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_REG_OFFSET 0x394 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_STATUS_20_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_REG_OFFSET 0x398 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_STATUS_21_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_REG_OFFSET 0x39c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_STATUS_22_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_REG_OFFSET 0x3a0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_STATUS_23_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_REG_OFFSET 0x3a4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_STATUS_24_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_REG_OFFSET 0x3a8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_STATUS_25_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_REG_OFFSET 0x3ac +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_STATUS_26_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_REG_OFFSET 0x3b0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_STATUS_27_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_REG_OFFSET 0x3b4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_STATUS_28_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_REG_OFFSET 0x3b8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_STATUS_29_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_REG_OFFSET 0x3bc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_STATUS_30_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_REG_OFFSET 0x3c0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_STATUS_31_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_REG_OFFSET 0x3c4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_STATUS_32_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_REG_OFFSET 0x3c8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_STATUS_33_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_REG_OFFSET 0x3cc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_STATUS_34_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_REG_OFFSET 0x3d0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_STATUS_35_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_REG_OFFSET 0x3d4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_STATUS_36_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_REG_OFFSET 0x3d8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_STATUS_37_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_REG_OFFSET 0x3dc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_STATUS_38_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_REG_OFFSET 0x3e0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_STATUS_39_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_REG_OFFSET 0x3e4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_STATUS_40_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_REG_OFFSET 0x3e8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_STATUS_41_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_REG_OFFSET 0x3ec +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_STATUS_42_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_REG_OFFSET 0x3f0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_STATUS_43_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_REG_OFFSET 0x3f4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_STATUS_44_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_REG_OFFSET 0x3f8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_STATUS_45_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_REG_OFFSET 0x3fc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_STATUS_46_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_REG_OFFSET 0x400 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_STATUS_47_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_REG_OFFSET 0x404 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_STATUS_48_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_REG_OFFSET 0x408 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_STATUS_49_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_REG_OFFSET 0x40c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_STATUS_50_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_REG_OFFSET 0x410 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_STATUS_51_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_REG_OFFSET 0x414 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_STATUS_52_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_REG_OFFSET 0x418 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_STATUS_53_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_REG_OFFSET 0x41c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_STATUS_54_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_REG_OFFSET 0x420 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_STATUS_55_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_REG_OFFSET 0x424 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_STATUS_56_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_REG_OFFSET 0x428 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_STATUS_57_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_REG_OFFSET 0x42c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_STATUS_58_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_REG_OFFSET 0x430 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_STATUS_59_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_REG_OFFSET 0x434 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_STATUS_60_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_REG_OFFSET 0x438 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_STATUS_61_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_REG_OFFSET 0x43c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_STATUS_62_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_REG_OFFSET 0x440 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_STATUS_63_BIT 0 + #ifdef __cplusplus } // extern "C" #endif From 69ee3d1546fcc823f124cfa2c7233ccacff62a76 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Thu, 2 Jul 2026 17:30:27 +0200 Subject: [PATCH 24/39] [SW] private L1 CMO runtime, spin-lock and multi-spin-lock passed --- software/snRuntime/CMakeLists.txt | 1 + software/snRuntime/include/lp1cache.h | 26 ++++++ software/snRuntime/src/lp1cache.c | 65 ++++++++++++++ software/tests/CMakeLists.txt | 2 + software/tests/lp1_cmo/main.c | 125 ++++++++++++++++++++++++++ software/tests/multi-spin-lock/main.c | 109 ++++++++++++++++++++++ software/tests/spin-lock/main.c | 12 +++ 7 files changed, 340 insertions(+) create mode 100644 software/snRuntime/include/lp1cache.h create mode 100644 software/snRuntime/src/lp1cache.c create mode 100644 software/tests/lp1_cmo/main.c create mode 100644 software/tests/multi-spin-lock/main.c diff --git a/software/snRuntime/CMakeLists.txt b/software/snRuntime/CMakeLists.txt index 5c6b3cb..d9ef2d6 100644 --- a/software/snRuntime/CMakeLists.txt +++ b/software/snRuntime/CMakeLists.txt @@ -65,6 +65,7 @@ set(sources src/alloc.c src/interrupt.c src/l1cache.c + src/lp1cache.c ) # platform specific sources diff --git a/software/snRuntime/include/lp1cache.h b/software/snRuntime/include/lp1cache.h new file mode 100644 index 0000000..82be231 --- /dev/null +++ b/software/snRuntime/include/lp1cache.h @@ -0,0 +1,26 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. + +// SPDX-License-Identifier: Apache-2.0 + +// Private-L1 (LP1) cache control. +// +// LP1 is the per-core private HPDcache (write-through, no coherence), distinct +// from the shared distributed L1D controlled in l1cache.h. These primitives +// drive the per-core CMO (Cache Management Operation) injector so software can +// bracket a critical section: +// +// amoswap acquire (L2) -> lp1_inval() -> CS -> lp1_wt_flush() -> release (L2) +// +// Each core acts on its own private L1; call from the core that owns the +// critical section (no barrier -- the register slot is per-core). + +#include "encoding.h" +#include "cachepool_peripheral.h" +#include "team.h" + +extern __thread struct snrt_team *_snrt_team_current; + +void lp1_wt_flush(); // release: drain write-through write buffer +void lp1_inval(); // acquire: invalidate the whole private L1 +void lp1_inval_line(uint32_t addr); // invalidate one cacheline covering addr diff --git a/software/snRuntime/src/lp1cache.c b/software/snRuntime/src/lp1cache.c new file mode 100644 index 0000000..3f5bfcc --- /dev/null +++ b/software/snRuntime/src/lp1cache.c @@ -0,0 +1,65 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. + +// SPDX-License-Identifier: Apache-2.0 + +#include +#include + +// Software critical-section support for the per-core private L1 (HPDcache). +// Each core owns one register slot [cid] (multireg, stride 4 bytes) so that +// independent cores running unrelated critical sections never contend on a +// shared trigger. A CMO is issued by writing op+addr, pulsing commit, then +// polling status (busy while the injector has a request in flight). +// +// op encoding (must match cmo_decode() in cachepool_l1_ctrl.sv): +// 0 = FENCE (write-through WBUF drain -- "flush" under WT policy) +// 1 = INVAL_ALL (invalidate the whole private L1) +// 2 = INVAL_NLINE (invalidate the cacheline covering addr) +#define LP1_CMO_OP_FENCE 0u +#define LP1_CMO_OP_INVAL_ALL 1u +#define LP1_CMO_OP_INVAL_LINE 2u + +// Issue one CMO on this core's slot and block until the injector completes. +static inline void lp1_cmo(uint32_t op, uint32_t addr) { + uint32_t cid = snrt_cluster_core_idx(); + uint64_t base = _snrt_team_current->root->cluster_mem.end; + + volatile uint32_t *op_reg = + (uint32_t *)(base + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_REG_OFFSET + + cid * 4); + volatile uint32_t *addr_reg = + (uint32_t *)(base + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0_REG_OFFSET + + cid * 4); + volatile uint32_t *commit_reg = + (uint32_t *)(base + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_REG_OFFSET + + cid * 4); + volatile uint32_t *status_reg = + (uint32_t *)(base + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_REG_OFFSET + + cid * 4); + + *op_reg = op; + *addr_reg = addr; + // Trigger the injector. The peripheral self-clears commit and raises status. + *commit_reg = 1; + // Wait until the CMO has been accepted and completed by the HPDcache. + while (*status_reg) { + } +} + +// Release side of a critical section: make all prior private-L1 writes visible +// downstream (drain the write-through write buffer) before the L2 release AMO. +void lp1_wt_flush() { + lp1_cmo(LP1_CMO_OP_FENCE, 0); +} + +// Acquire side of a critical section: drop any stale lines so the first reads +// inside the section miss and refetch fresh data from L2. +void lp1_inval() { + lp1_cmo(LP1_CMO_OP_INVAL_ALL, 0); +} + +// Invalidate a single cacheline covering addr (finer-grained than lp1_inval). +void lp1_inval_line(uint32_t addr) { + lp1_cmo(LP1_CMO_OP_INVAL_LINE, addr); +} diff --git a/software/tests/CMakeLists.txt b/software/tests/CMakeLists.txt index 94ffc8f..24e3e5f 100644 --- a/software/tests/CMakeLists.txt +++ b/software/tests/CMakeLists.txt @@ -85,6 +85,7 @@ set(SNITCH_TEST_PREFIX cachepool-) ## RLC add_spatz_test_zeroParam(spin-lock spin-lock/main.c) +add_spatz_test_zeroParam(multi-spin-lock multi-spin-lock/main.c) add_spatz_test_zeroParam(mcs-lock mcs-lock/main.c) add_spatz_test_zeroParam(byte-enable byte-enable/main.c) @@ -130,6 +131,7 @@ add_spatz_test_oneParam(idotp-32b idotp-32b/main.c 32768) add_spatz_test_zeroParam(lp1_sanity lp1_sanity/main.c) add_spatz_test_zeroParam(lp1_private lp1_private/main.c) add_spatz_test_zeroParam(lp1_eviction lp1_eviction/main.c) +add_spatz_test_zeroParam(lp1_cmo lp1_cmo/main.c) add_spatz_test_zeroParam(arith_amo arith_amo/main.c) add_spatz_test_zeroParam(lrsc_amo lrsc_amo/main.c) diff --git a/software/tests/lp1_cmo/main.c b/software/tests/lp1_cmo/main.c new file mode 100644 index 0000000..2265b8f --- /dev/null +++ b/software/tests/lp1_cmo/main.c @@ -0,0 +1,125 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Ho Tin Hung, ETH Zurich + +// LP1 CMO datapath liveness — single-core bring-up gate for the per-core +// private-L1 (HPDcache) CMO injector. +// +// Goal: prove the NEW control path is electrically alive end-to-end before it +// is relied upon in a real kernel (spin-lock). The path is: +// runtime MMIO store -> peripheral reg -> per-core CMO FSM -> l1_ctrl +// injector requester[2] -> HPDcache -> response -> done -> status clears. +// Every prior test kept lp1_cmo_valid at 0, so this is the first exercise of +// that datapath. +// +// This tier tests LIVENESS, not cross-core correctness: each lp1_* call is a +// blocking status poll, so if a CMO never completes (injector never sees +// l1_rsp[2].valid, or the arbiter never grants requester 2) the test HANGS. +// The print marker bracketing each call localizes such a hang to the exact op. +// The post-CMO reloads confirm the refill path still returns correct data. +// Cross-core staleness correctness is the spin-lock test's job. +// +// Only core 0 does work; every other core parks on the hardware barrier, which +// is coherence-independent (MMIO) and safe here. + +#include +#include +#include +#include +#include + +// Small cacheable footprint touched ONLY by core 0 — no sharing, no coherence. +#define CMO_WORDS 16 + +static volatile uint32_t cmo_buf[CMO_WORDS] __attribute__((section(".data"))); + +int main() { + const uint32_t num_cores = snrt_cluster_core_num(); + const uint32_t cid = snrt_cluster_core_idx(); + + // Confirm every core booted and the HW barrier works before core 0 drives + // the CMO datapath. + snrt_cluster_hw_barrier(); + + if (cid == 0) { + printf("\n*** LP1 CMO datapath liveness (single-core) ***\n"); + printf("Cores:%u (only core 0 active)\n", num_cores); + + start_kernel(); + + uint32_t errors = 0; + + // Seed cacheable data. Write-through: values land in L2 and are also + // resident in the private L1. + for (uint32_t i = 0; i < CMO_WORDS; i++) + cmo_buf[i] = 0xCA110000u + i; + + // [1] FENCE / write-through flush. Drains the WBUF; must complete & return. + printf(" [1] lp1_wt_flush (CMO_FENCE) ... issuing\n"); + snrt_fence(); + lp1_wt_flush(); + printf(" [1] lp1_wt_flush DONE\n"); + + // [2] INVAL_ALL. Drops every resident line; must complete & return. + printf(" [2] lp1_inval (INVAL_ALL) ... issuing\n"); + lp1_inval(); + snrt_fence(); + printf(" [2] lp1_inval DONE\n"); + + // After a full invalidate, these loads miss and refill from L2. On a single + // core L2 still holds the seeded values, so the data must match — this + // confirms the post-inval refill path is alive. + for (uint32_t i = 0; i < CMO_WORDS; i++) { + uint32_t got = cmo_buf[i]; + uint32_t exp = 0xCA110000u + i; + if (got != exp) { + printf(" FAIL refill idx %u exp 0x%08x got 0x%08x\n", i, exp, got); + errors++; + } + } + + // [3] INVAL_NLINE on a single address; must complete & return. + printf(" [3] lp1_inval_line ... issuing\n"); + lp1_inval_line((uint32_t)(uintptr_t)&cmo_buf[0]); + snrt_fence(); + printf(" [3] lp1_inval_line DONE\n"); + + // Reload the invalidated line: refills from L2, must match. + { + uint32_t got = cmo_buf[0]; + uint32_t exp = 0xCA110000u; + if (got != exp) { + printf(" FAIL line-refill exp 0x%08x got 0x%08x\n", exp, got); + errors++; + } + } + + stop_kernel(); + + if (errors == 0) + printf("lp1_cmo: PASS\n"); + else + printf("lp1_cmo: FAIL (%u errors)\n", errors); + + printf("*** LP1 CMO liveness complete ***\n"); + } + + // Final rendezvous so no core races ahead to EOC before core 0 is done. + snrt_cluster_hw_barrier(); + + return 0; +} diff --git a/software/tests/multi-spin-lock/main.c b/software/tests/multi-spin-lock/main.c new file mode 100644 index 0000000..544b1ad --- /dev/null +++ b/software/tests/multi-spin-lock/main.c @@ -0,0 +1,109 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Ho Tin Hung, ETH Zurich + +// Multi-spin-lock — DISCRIMINATING cross-core staleness gate for the private-L1 +// (LP1) critical-section CMOs. +// +// Unlike the single-shot spin-lock test (each core touches `result` exactly +// once, always a cold miss that refills fresh from L2 — so it passes even with +// the CMOs removed), this test has each core enter the critical section REPS +// times. On the 2nd+ entry a core would re-read its OWN previously-cached copy +// of `result` (LP1 is write-through, NO coherence), which is stale w.r.t. the +// updates other cores landed at L2 in between. That stale read clobbers those +// updates -> lost increments -> `result < gold`. +// +// The `lp1_inval()` after acquiring the lock drops that stale line so the read +// misses and refetches fresh; the `lp1_wt_flush()` before releasing drains the +// write-through buffer so this core's update reaches L2 before the next winner. +// +// Expected behavior (the discriminating property): +// - WITH the lp1_inval/lp1_wt_flush pair : result == gold (PASS) +// - WITHOUT them (comment the CMO calls) : result < gold (FAIL) +// That fails-without / passes-with contrast is the actual proof the CMOs fix +// staleness. +// +// Kept minimal to avoid hiding the hazard: no in-loop printf and a tiny +// footprint (just `result` + `lock`), so the `result` line stays resident in +// each core's LP1 across iterations rather than being evicted (an eviction +// would turn the re-read into a miss and mask the bug). `result` is volatile so +// every iteration performs a real load/store through the LP1 instead of the +// compiler keeping it in a register. + +#include +#include +#include +#include +#include +#include "spin_lock.h" + +// Critical-section entries per core. >1 is what exposes the staleness hazard. +#define REPS 16 + +#define LP1 + +static volatile uint32_t result __attribute__((section(".data"))); + +spinlock_t lock; + +int main() { + const unsigned int num_cores = snrt_cluster_core_num(); + const unsigned int cid = snrt_cluster_core_idx(); + + // Rendezvous so every core starts the contended loop together. + snrt_cluster_hw_barrier(); + + for (unsigned int r = 0; r < REPS; r++) { + spin_lock(&lock, 20); + +#ifdef LP1 + // Acquire side: drop stale cached copies so the read of `result` is fresh. + lp1_inval(); + snrt_fence(); +#endif + + result += cid; + +#ifdef LP1 + // Release side: drain the write-through buffer so this update reaches L2 + // before the lock is handed to the next core. Fence must precede the flush. + snrt_fence(); + lp1_wt_flush(); +#endif + + spin_unlock(&lock, 20); + } + + // Ensure all cores finished all iterations before core 0 checks the total. + snrt_cluster_hw_barrier(); + + if (cid == 0) { + uint32_t res = result; + // Each core adds cid REPS times: REPS * (0+1+...+(N-1)) = REPS * N(N-1)/2. + uint32_t gold = REPS * ((0 + num_cores - 1) * num_cores / 2); + printf("result: %u; gold: %u\n", res, gold); + if (res == gold) + printf("multi-spin-lock: PASS\n"); + else + printf("multi-spin-lock: FAIL\n"); + } + + // Wait for core 0 to finish displaying results. + snrt_cluster_hw_barrier(); + + return 0; +} diff --git a/software/tests/spin-lock/main.c b/software/tests/spin-lock/main.c index bf214f6..85c4c40 100644 --- a/software/tests/spin-lock/main.c +++ b/software/tests/spin-lock/main.c @@ -19,6 +19,7 @@ // Author: Diyou Shen #include +#include #include #include #include "spin_lock.h" @@ -38,12 +39,23 @@ int main() { // Fetch lock spin_lock (&lock, 20); + // Acquire side of the critical section: drop any stale cached copies so the + // read of `result` below misses and refetches the fresh value from L2. + lp1_inval(); + snrt_fence(); + // Each core print its core id printf("T%d,C%d: Hello\n", tid, cid); // Add cid to the result result += cid; + // Release side of the critical section: drain the write-through write buffer + // (incl. any Spatz stores) so this core's update lands at L2 before the lock + // is released. The fence must precede the flush (WBUF-ordering). + snrt_fence(); + lp1_wt_flush(); + // Release the lock spin_unlock(&lock, 20); From 7ae5cf6955e8f2f4fa5d62dc4526a10446baf6d2 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Tue, 7 Jul 2026 17:27:50 +0200 Subject: [PATCH 25/39] [SW] MCS lock protection for non-coherence L1 --- Makefile | 2 +- hardware/src/cachepool_tile.sv | 15 ++++++---- software/tests/CMakeLists.txt | 3 ++ software/tests/benchmark/mcs_lock.c | 43 +++++++++++++++++++++++++++++ software/tests/fft-32b/main.c | 1 + software/tests/include/mcs_lock.h | 2 +- software/tests/mcs-lock/main.c | 8 +++--- 7 files changed, 62 insertions(+), 12 deletions(-) diff --git a/Makefile b/Makefile index ad6caf8..d3dcc51 100644 --- a/Makefile +++ b/Makefile @@ -168,7 +168,7 @@ $(BOOTROM_DIR)/bootrom.sv: $(BOOTROM_DIR)/bootrom.bin $(BOOTROM_DIR)/bootdata.cc ########### FLOO_DIR ?= $(shell $(BENDER_INSTALL_DIR)/bender path floo_noc) FLOO_GEN_OUTDIR ?= $(ROOT_DIR)/hardware/generated -FLOO_CFG ?= $(ROOT_DIR)/config/floonoc_cachepool_16g.yml +FLOO_CFG ?= $(ROOT_DIR)/config/floonoc_cachepool_4g.yml FLOO_NAME = cachepool FLOO_NOC ?= $(FLOO_GEN_OUTDIR)/floo_$(FLOO_NAME)_noc_pkg.sv diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index 1a15824..311c3ba 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -326,22 +326,25 @@ module cachepool_tile localparam int unsigned LP1ReqIdWidth = $clog2(NumSpatzOutstandingLoads); localparam int unsigned LP1TidWidth = CoreIDWidth + TileIDWidth + LP1ReqIdWidth + 2 + LP1CoalInfoWidth; // +2: is_fpu, write; tile_id+core_id round-tripped localparam int unsigned LP1NrRequesters = 3; // Spatz(coalesced) + Snitch + CMO injector + localparam int unsigned LP1NumSets = 16; + localparam int unsigned LP1NumWays = 4; + localparam int unsigned LP1NumWordsPerLine = 4; localparam hpdcache_pkg::hpdcache_user_cfg_t HPDcacheUserCfg = '{ nRequesters: LP1NrRequesters, - paWidth: 32, + paWidth: TCDMAddrWidth, wordWidth: LP1WordWidth, - sets: 32, - ways: 4, - clWords: 4, + sets: LP1NumSets, + ways: LP1NumWays, + clWords: LP1NumWordsPerLine, reqWords: 1, reqTransIdWidth: LP1TidWidth + LP1NumWordOffsetBits, reqSrcIdWidth: $clog2(LP1NrRequesters), // selects requester port (0 Spatz / 1 Snitch / 2 CMO) victimSel: hpdcache_pkg::HPDCACHE_VICTIM_PLRU, dataWaysPerRamWord: 1, - dataSetsPerRam: 32, + dataSetsPerRam: LP1NumSets, dataRamByteEnable: 1'b1, - accessWords: 4, + accessWords: LP1NumWordsPerLine, mshrSets: 4, mshrWays: 4, mshrWaysPerRamWord: 4, diff --git a/software/tests/CMakeLists.txt b/software/tests/CMakeLists.txt index 24e3e5f..e6f4dc4 100644 --- a/software/tests/CMakeLists.txt +++ b/software/tests/CMakeLists.txt @@ -57,6 +57,9 @@ endmacro() add_library(benchmark benchmark/benchmark.c) add_library(spin_lock benchmark/spin_lock.c) add_library(mcs_lock benchmark/mcs_lock.c) +# Private-L1 (LP1) has no coherence: bracket the MCS handshake with CMO calls +# (see benchmark/mcs_lock.c). Enable for all consumers of the lib. +target_compile_definitions(mcs_lock PUBLIC LP1_CMO) add_compile_options(-O3 -g -ffunction-sections) add_compile_options(-DELEN=64) diff --git a/software/tests/benchmark/mcs_lock.c b/software/tests/benchmark/mcs_lock.c index 54e0615..15ad4b2 100644 --- a/software/tests/benchmark/mcs_lock.c +++ b/software/tests/benchmark/mcs_lock.c @@ -24,6 +24,18 @@ #include "benchmark.h" // #include "printf_lock.h" +// Private-L1 (LP1) Cache Management Operations. On the per-core private +// write-through L1 (no coherence) the MCS handshake variables (`me->locked`, +// `me->next`) are written by one core and spun on by another, so a spinner +// keeps hitting a stale cached copy and never observes the handoff. Bracket +// the handshake with lp1_inval() on the consumer (spin) side and lp1_wt_flush() +// on the producer (publish) side, ordered by snrt_fence(). Guarded by LP1_CMO +// so consumers that do not run on the private L1 are unaffected. +#define LP1_CMO +#ifdef LP1_CMO +#include +#endif + // Each waiter spins on its own node (aligned to keep it on a single line) struct __attribute__((aligned(MCS_CACHELINE))) mcs_node { _Atomic(struct mcs_node*) next __attribute__((aligned(MCS_CACHELINE))); @@ -128,8 +140,21 @@ void __attribute__((noinline)) mcs_lock_acquire(mcs_lock_t* L, int delay) { if (pred) { atomic_store_explicit(&me->locked, true, memory_order_relaxed); atomic_store_explicit(&pred->next, me, memory_order_relaxed); +#ifdef LP1_CMO + // Producer side: order the two stores above and drain the write-through + // buffer so the predecessor observes pred->next=me (and our armed locked + // flag) at L2. Fence must precede the flush (WBUF ordering). + snrt_fence(); + lp1_wt_flush(); +#endif while (atomic_load_explicit(&me->locked, memory_order_relaxed)) { // cachepool_wait(delay); // prevent busy spinning +#ifdef LP1_CMO + // Consumer side: drop the stale private-L1 copy of `locked` so the next + // read misses and refetches the predecessor's handoff (locked=false). + lp1_inval(); + snrt_fence(); +#endif } } @@ -147,6 +172,12 @@ void __attribute__((noinline)) mcs_lock_release(mcs_lock_t* L, int delay) { if (!b) return; // or assert in debug struct mcs_node* me = &b->node; +#ifdef LP1_CMO + // Consumer side: `me->next` is published by the successor from another core; + // drop the stale private-L1 copy before reading it. + lp1_inval(); + snrt_fence(); +#endif struct mcs_node* succ = // atomic_load_explicit(&me->next, memory_order_acquire); atomic_load_explicit(&me->next, memory_order_relaxed); @@ -162,6 +193,12 @@ void __attribute__((noinline)) mcs_lock_release(mcs_lock_t* L, int delay) { // A successor is enqueuing; wait for linkage. do { // cachepool_wait(delay); // prevent busy spinning +#ifdef LP1_CMO + // Consumer side: refetch `me->next` fresh each spin until the successor's + // linkage store is observed at L2. + lp1_inval(); + snrt_fence(); +#endif // succ = atomic_load_explicit(&me->next, memory_order_acquire); succ = atomic_load_explicit(&me->next, memory_order_relaxed); } while (!succ); @@ -169,6 +206,12 @@ void __attribute__((noinline)) mcs_lock_release(mcs_lock_t* L, int delay) { // Handoff: clear the successor's locked flag. atomic_store_explicit(&succ->locked, false, memory_order_release); +#ifdef LP1_CMO + // Producer side: drain the write-through buffer so the successor spinning on + // its `locked` flag observes the handoff promptly. Fence precedes the flush. + snrt_fence(); + lp1_wt_flush(); +#endif mcs_bind_release_slot(b); // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); diff --git a/software/tests/fft-32b/main.c b/software/tests/fft-32b/main.c index f4cbfed..61bf17a 100644 --- a/software/tests/fft-32b/main.c +++ b/software/tests/fft-32b/main.c @@ -113,6 +113,7 @@ int main() { } // In first part of calculation, we need barrier after each round + // l1_fence snrt_cluster_hw_barrier(); } diff --git a/software/tests/include/mcs_lock.h b/software/tests/include/mcs_lock.h index 020a2f1..7462114 100644 --- a/software/tests/include/mcs_lock.h +++ b/software/tests/include/mcs_lock.h @@ -35,7 +35,7 @@ #endif #ifndef MCS_MAX_HARTS -#define MCS_MAX_HARTS 4 // set to your cluster max cores +#define MCS_MAX_HARTS 16 // set to your cluster max cores #endif #ifndef MCS_TLS_SLOTS diff --git a/software/tests/mcs-lock/main.c b/software/tests/mcs-lock/main.c index ae660ad..1263e58 100644 --- a/software/tests/mcs-lock/main.c +++ b/software/tests/mcs-lock/main.c @@ -185,12 +185,12 @@ int main(void) { spin_unlock(&test_spin_lock, 0); #endif - if(core_id != 0) { - while(1){} - } + // if(core_id != 0) { + // while(1){} + // } // Wait for all cores to finish - snrt_cluster_hw_barrier(); // this can trigger Misaligned Load exception + snrt_cluster_hw_barrier(); return 0; } From 67af6c8011ee07b8e5a78eabaca49bc622638236 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Tue, 7 Jul 2026 17:49:56 +0200 Subject: [PATCH 26/39] [SW] fdotp reduction protection for private L1 --- software/tests/fdotp-32b/main.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/software/tests/fdotp-32b/main.c b/software/tests/fdotp-32b/main.c index 5492ff3..a9fc3ae 100644 --- a/software/tests/fdotp-32b/main.c +++ b/software/tests/fdotp-32b/main.c @@ -22,6 +22,16 @@ #include DATAHEADER #include "kernel/fdotp.c" +#include + +// Private-L1 (LP1 = per-core write-through cache, NO coherence): the cross-core +// tree reduction below shares `result[]`. Producers must drain their write to +// L2 (lp1_wt_flush) and consumers must drop stale cached copies (lp1_inval) -- +// otherwise, on the 2nd+ measure_iter pass a lead core re-reads its previously +// cached (stale) copy of a peer's partial and the reduction is wrong. The +// existing barriers provide the ordering; the CMOs provide the visibility. +// Comment out to observe the staleness failure (discriminating check). +#define LP1 int main() { const uint32_t num_cores = snrt_cluster_core_num(); @@ -127,6 +137,13 @@ int main() { // Make sure spatz has finished writing snrt_fence_spatz(); +#ifdef LP1 + // Producer: drain the write-through buffer so result[cid] reaches L2 before + // the reducers read it. Fence must precede the flush. + snrt_fence(); + lp1_wt_flush(); +#endif + // Wait for all cores to finish snrt_cluster_hw_barrier(); @@ -145,15 +162,31 @@ int main() { // Level 1: lead core of each group accumulates its group if (cid % red_group == 0) { +#ifdef LP1 + // Consumer: drop stale private-L1 copies of result[] (from a previous + // measure_iter pass) so the peer partials are refetched fresh from L2. + lp1_inval(); + snrt_fence(); +#endif for (uint32_t i = 1; i < red_group && (cid + i) < num_cores; ++i) acc += result[cid + i]; result[cid] = acc; +#ifdef LP1 + // Producer: expose this group's sum to core 0's level-2 pass. + snrt_fence(); + lp1_wt_flush(); +#endif } snrt_cluster_hw_barrier(); // Level 2: core 0 sums all group results if (cid == 0) { +#ifdef LP1 + // Consumer: refetch the group leads' sums fresh from L2. + lp1_inval(); + snrt_fence(); +#endif for (uint32_t g = red_group; g < num_cores; g += red_group) acc += result[g]; result[0] = acc; From ef0d64d2046a358b4af89b7b5d5e77cf6ab7a6f4 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Wed, 8 Jul 2026 18:22:48 +0200 Subject: [PATCH 27/39] [HW] CMO periph reg parameterize (follow total core num) --- Makefile | 15 + hardware/cachepool_peripheral/Makefile | 15 +- .../cachepool_peripheral_reg.hjson | 13 +- .../cachepool_peripheral_reg_pkg.sv | 3838 +- .../cachepool_peripheral_reg_top.sv | 34822 ++++++++++++++-- .../snRuntime/include/cachepool_peripheral.h | 4760 ++- software/tests/CMakeLists.txt | 4 - .../tests/fdotp-32b-single/data/.gitignore | 3 - software/tests/fdotp-32b-single/data/layer.h | 150 - .../tests/fdotp-32b-single/kernel/fdotp.c | 166 - .../tests/fdotp-32b-single/kernel/fdotp.h | 33 - software/tests/fdotp-32b-single/main copy.c | 130 - software/tests/fdotp-32b-single/main.c | 205 - .../fdotp-32b-single/script/data_1024.json | 12 - .../fdotp-32b-single/script/data_8192.json | 12 - .../tests/fdotp-32b-single/script/gen_data.py | 186 - software/tests/fdotp-32b/main.c | 2 + software/tests/fft-32b/main.c | 2 +- 18 files changed, 38741 insertions(+), 5627 deletions(-) delete mode 100644 software/tests/fdotp-32b-single/data/.gitignore delete mode 100644 software/tests/fdotp-32b-single/data/layer.h delete mode 100644 software/tests/fdotp-32b-single/kernel/fdotp.c delete mode 100644 software/tests/fdotp-32b-single/kernel/fdotp.h delete mode 100644 software/tests/fdotp-32b-single/main copy.c delete mode 100644 software/tests/fdotp-32b-single/main.c delete mode 100644 software/tests/fdotp-32b-single/script/data_1024.json delete mode 100644 software/tests/fdotp-32b-single/script/data_8192.json delete mode 100644 software/tests/fdotp-32b-single/script/gen_data.py diff --git a/Makefile b/Makefile index d3dcc51..27512de 100644 --- a/Makefile +++ b/Makefile @@ -187,6 +187,20 @@ $(FLOO_NOC): install-floogen $(FLOO_CFG) clean-floonoc: rm -f $(FLOO_NOC) +######################### +# Peripheral registers # +######################### +# The LP1 (private-L1) CMO peripheral has one register slot per core. The slot +# count (NumLp1CmoRegs) is baked into the generated reg_pkg/reg_top/C-header by +# regtool, so it must be regenerated whenever the config's core count changes -- +# analogous to update-floonoc for the mesh. We force the regen (-B) because the +# generated .sv/.h are committed and may be newer than the (unchanged) schema. +PERIPH_REG_DIR ?= $(ROOT_DIR)/hardware/cachepool_peripheral + +.PHONY: update-periph-reg +update-periph-reg: + $(MAKE) -C $(PERIPH_REG_DIR) -B all NUM_LP1_CMO_REGS=$(num_cores) + ########### # DramSys # ########### @@ -427,6 +441,7 @@ help: @echo "*cache-init*: source the insitu-cache environment (requires bender checkout)" @echo "*bootrom*: compile and generate the bootrom SystemVerilog module" @echo "*update-floonoc*: regenerate FlooNoC package from FLOO_CFG (run after changing group count)" + @echo "*update-periph-reg*: regenerate the peripheral registers with NumLp1CmoRegs=num_cores (run after changing core count)" @echo "*install-floogen*: install the floogen Python tool (required by update-floonoc)" @echo "*clean-floonoc*: remove the generated FlooNoC package" @echo "" diff --git a/hardware/cachepool_peripheral/Makefile b/hardware/cachepool_peripheral/Makefile index dc79b69..ff8b8df 100644 --- a/hardware/cachepool_peripheral/Makefile +++ b/hardware/cachepool_peripheral/Makefile @@ -15,13 +15,22 @@ PKG=cachepool_peripheral_reg_pkg.sv TOP=cachepool_peripheral_reg_top.sv CDEF=$(ROOTDIR)/software/snRuntime/include/cachepool_peripheral.h +# Number of per-core LP1 (private-L1) CMO register slots. MUST be >= the total +# core count of the target config, or cores with cid >= this value spin forever +# on LP1_CMO_STATUS (their slot is never decoded) -> cluster barrier deadlock. +# The top-level `make update-periph-reg` overrides this with the current +# config's num_cores; the default here is a safe max (256 = full 16g) for a +# standalone `make -C hardware/cachepool_peripheral`. +NUM_LP1_CMO_REGS ?= 256 +REGGEN_PARAMS := -p NumLp1CmoRegs=$(NUM_LP1_CMO_REGS) + all: $(PKG) $(TOP) $(CDEF) $(PKG): $(SCHEMA) - $(PYTHON3) $(REGTOOL) -r -t $(dir $@) $< + $(PYTHON3) $(REGTOOL) $(REGGEN_PARAMS) -r -t $(dir $@) $< $(TOP): $(SCHEMA) - $(PYTHON3) $(REGTOOL) -r -t $(dir $@) $< + $(PYTHON3) $(REGTOOL) $(REGGEN_PARAMS) -r -t $(dir $@) $< %.h: $(SCHEMA) - $(PYTHON3) $(REGTOOL) -D -o $@ $< + $(PYTHON3) $(REGTOOL) $(REGGEN_PARAMS) -D -o $@ $< $(CLANG_FORMAT) -i $@ diff --git a/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson b/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson index 6f8e872..0a7a719 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson +++ b/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson @@ -11,11 +11,16 @@ }, { name: "NumLp1CmoRegs", desc: '''Number of per-core LP1 (private-L1) CMO register slots -- one per core / - per private L1. Core `cid` uses slot `cid`. Default 64 covers every - currently-built config (2g/4g full = 32 cores; 2g/4g/16g tiny up to - 64 cores). Bump to 256 for full 16g (256 cores).''', + per private L1. Core `cid` uses slot `cid`, so this MUST be >= the + target config's total core count; otherwise cores with cid >= this + value spin forever on LP1_CMO_STATUS (their slot is never decoded) + -> cluster barrier deadlock. This is regenerated per config by + `make update-periph-reg`, which overrides this default with num_cores + (32 for 2g/4g, 64 for *_tiny, 256 for full 16g). The default below is + only a safe max for a standalone regtool run; the block still fits the + 64 kB ClusterPeriphSize window at 256.''', type: "int", - default: "64" + default: "256" }, ], name: "cachepool_peripheral", diff --git a/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv b/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv index 30c13ad..af6ca31 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv +++ b/hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv @@ -8,10 +8,10 @@ package cachepool_peripheral_reg_pkg; // Param list parameter int NumTileSelRegs = 2; - parameter int NumLp1CmoRegs = 64; + parameter int NumLp1CmoRegs = 256; // Address widths within the block - parameter int BlockAw = 11; + parameter int BlockAw = 13; //////////////////////////// // Typedefs for registers // @@ -123,311 +123,1079 @@ package cachepool_peripheral_reg_pkg; // Register -> HW type typedef struct packed { - cachepool_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [2525:2494] - cachepool_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [2493:2493] - cachepool_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [2492:2492] - cachepool_peripheral_reg2hw_spatz_cycle_reg_t spatz_cycle; // [2491:2460] - cachepool_peripheral_reg2hw_cluster_boot_control_reg_t cluster_boot_control; // [2459:2428] - cachepool_peripheral_reg2hw_cluster_eoc_exit_reg_t cluster_eoc_exit; // [2427:2424] - cachepool_peripheral_reg2hw_cfg_l1d_spm_reg_t cfg_l1d_spm; // [2423:2414] - cachepool_peripheral_reg2hw_cfg_l1d_insn_reg_t cfg_l1d_insn; // [2413:2412] - cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_mreg_t [1:0] cfg_l1d_tile_sel; // [2411:2348] - cachepool_peripheral_reg2hw_l1d_spm_commit_reg_t l1d_spm_commit; // [2347:2347] - cachepool_peripheral_reg2hw_l1d_insn_commit_reg_t l1d_insn_commit; // [2346:2346] - cachepool_peripheral_reg2hw_l1d_private_reg_t l1d_private; // [2345:2342] - cachepool_peripheral_reg2hw_l1d_addr_reg_t l1d_addr; // [2341:2310] - cachepool_peripheral_reg2hw_xbar_offset_reg_t xbar_offset; // [2309:2305] - cachepool_peripheral_reg2hw_xbar_offset_commit_reg_t xbar_offset_commit; // [2304:2304] - cachepool_peripheral_reg2hw_cfg_lp1_cmo_mreg_t [63:0] cfg_lp1_cmo; // [2303:2112] - cachepool_peripheral_reg2hw_cfg_lp1_cmo_addr_mreg_t [63:0] cfg_lp1_cmo_addr; // [2111:64] - cachepool_peripheral_reg2hw_lp1_cmo_commit_mreg_t [63:0] lp1_cmo_commit; // [63:0] + cachepool_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [9437:9406] + cachepool_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [9405:9405] + cachepool_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [9404:9404] + cachepool_peripheral_reg2hw_spatz_cycle_reg_t spatz_cycle; // [9403:9372] + cachepool_peripheral_reg2hw_cluster_boot_control_reg_t cluster_boot_control; // [9371:9340] + cachepool_peripheral_reg2hw_cluster_eoc_exit_reg_t cluster_eoc_exit; // [9339:9336] + cachepool_peripheral_reg2hw_cfg_l1d_spm_reg_t cfg_l1d_spm; // [9335:9326] + cachepool_peripheral_reg2hw_cfg_l1d_insn_reg_t cfg_l1d_insn; // [9325:9324] + cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_mreg_t [1:0] cfg_l1d_tile_sel; // [9323:9260] + cachepool_peripheral_reg2hw_l1d_spm_commit_reg_t l1d_spm_commit; // [9259:9259] + cachepool_peripheral_reg2hw_l1d_insn_commit_reg_t l1d_insn_commit; // [9258:9258] + cachepool_peripheral_reg2hw_l1d_private_reg_t l1d_private; // [9257:9254] + cachepool_peripheral_reg2hw_l1d_addr_reg_t l1d_addr; // [9253:9222] + cachepool_peripheral_reg2hw_xbar_offset_reg_t xbar_offset; // [9221:9217] + cachepool_peripheral_reg2hw_xbar_offset_commit_reg_t xbar_offset_commit; // [9216:9216] + cachepool_peripheral_reg2hw_cfg_lp1_cmo_mreg_t [255:0] cfg_lp1_cmo; // [9215:8448] + cachepool_peripheral_reg2hw_cfg_lp1_cmo_addr_mreg_t [255:0] cfg_lp1_cmo_addr; // [8447:256] + cachepool_peripheral_reg2hw_lp1_cmo_commit_mreg_t [255:0] lp1_cmo_commit; // [255:0] } cachepool_peripheral_reg2hw_t; // HW -> register type typedef struct packed { - cachepool_peripheral_hw2reg_hw_barrier_reg_t hw_barrier; // [230:199] - cachepool_peripheral_hw2reg_l1d_spm_commit_reg_t l1d_spm_commit; // [198:197] - cachepool_peripheral_hw2reg_l1d_insn_commit_reg_t l1d_insn_commit; // [196:195] - cachepool_peripheral_hw2reg_l1d_flush_status_reg_t l1d_flush_status; // [194:194] - cachepool_peripheral_hw2reg_xbar_offset_commit_reg_t xbar_offset_commit; // [193:192] - cachepool_peripheral_hw2reg_lp1_cmo_commit_mreg_t [63:0] lp1_cmo_commit; // [191:64] - cachepool_peripheral_hw2reg_lp1_cmo_status_mreg_t [63:0] lp1_cmo_status; // [63:0] + cachepool_peripheral_hw2reg_hw_barrier_reg_t hw_barrier; // [806:775] + cachepool_peripheral_hw2reg_l1d_spm_commit_reg_t l1d_spm_commit; // [774:773] + cachepool_peripheral_hw2reg_l1d_insn_commit_reg_t l1d_insn_commit; // [772:771] + cachepool_peripheral_hw2reg_l1d_flush_status_reg_t l1d_flush_status; // [770:770] + cachepool_peripheral_hw2reg_xbar_offset_commit_reg_t xbar_offset_commit; // [769:768] + cachepool_peripheral_hw2reg_lp1_cmo_commit_mreg_t [255:0] lp1_cmo_commit; // [767:256] + cachepool_peripheral_hw2reg_lp1_cmo_status_mreg_t [255:0] lp1_cmo_status; // [255:0] } cachepool_peripheral_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET = 11'h 0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 11'h 4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET = 11'h 8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET = 11'h c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET = 11'h 10; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET = 11'h 14; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET = 11'h 18; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET = 11'h 1c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_OFFSET = 11'h 20; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_OFFSET = 11'h 24; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET = 11'h 28; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET = 11'h 2c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET = 11'h 30; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET = 11'h 34; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET = 11'h 38; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET = 11'h 3c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET = 11'h 40; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_OFFSET = 11'h 44; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_OFFSET = 11'h 48; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_OFFSET = 11'h 4c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_OFFSET = 11'h 50; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_OFFSET = 11'h 54; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_OFFSET = 11'h 58; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_OFFSET = 11'h 5c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_OFFSET = 11'h 60; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_OFFSET = 11'h 64; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_OFFSET = 11'h 68; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_OFFSET = 11'h 6c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_OFFSET = 11'h 70; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_OFFSET = 11'h 74; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_OFFSET = 11'h 78; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_OFFSET = 11'h 7c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_OFFSET = 11'h 80; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_OFFSET = 11'h 84; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_OFFSET = 11'h 88; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_OFFSET = 11'h 8c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_OFFSET = 11'h 90; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_OFFSET = 11'h 94; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_OFFSET = 11'h 98; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_OFFSET = 11'h 9c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_OFFSET = 11'h a0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_OFFSET = 11'h a4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_OFFSET = 11'h a8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_OFFSET = 11'h ac; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_OFFSET = 11'h b0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_OFFSET = 11'h b4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_OFFSET = 11'h b8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_OFFSET = 11'h bc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_OFFSET = 11'h c0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_OFFSET = 11'h c4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_OFFSET = 11'h c8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_OFFSET = 11'h cc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_OFFSET = 11'h d0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_OFFSET = 11'h d4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_OFFSET = 11'h d8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_OFFSET = 11'h dc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_OFFSET = 11'h e0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_OFFSET = 11'h e4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_OFFSET = 11'h e8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_OFFSET = 11'h ec; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_OFFSET = 11'h f0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_OFFSET = 11'h f4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_OFFSET = 11'h f8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_OFFSET = 11'h fc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_OFFSET = 11'h 100; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_OFFSET = 11'h 104; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_OFFSET = 11'h 108; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_OFFSET = 11'h 10c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_OFFSET = 11'h 110; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_OFFSET = 11'h 114; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_OFFSET = 11'h 118; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_OFFSET = 11'h 11c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_OFFSET = 11'h 120; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_OFFSET = 11'h 124; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_OFFSET = 11'h 128; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_OFFSET = 11'h 12c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_OFFSET = 11'h 130; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_OFFSET = 11'h 134; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_OFFSET = 11'h 138; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_OFFSET = 11'h 13c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OFFSET = 11'h 140; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0_OFFSET = 11'h 144; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1_OFFSET = 11'h 148; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2_OFFSET = 11'h 14c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3_OFFSET = 11'h 150; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4_OFFSET = 11'h 154; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5_OFFSET = 11'h 158; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6_OFFSET = 11'h 15c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7_OFFSET = 11'h 160; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8_OFFSET = 11'h 164; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9_OFFSET = 11'h 168; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10_OFFSET = 11'h 16c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11_OFFSET = 11'h 170; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12_OFFSET = 11'h 174; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13_OFFSET = 11'h 178; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14_OFFSET = 11'h 17c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15_OFFSET = 11'h 180; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16_OFFSET = 11'h 184; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17_OFFSET = 11'h 188; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18_OFFSET = 11'h 18c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19_OFFSET = 11'h 190; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20_OFFSET = 11'h 194; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21_OFFSET = 11'h 198; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22_OFFSET = 11'h 19c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23_OFFSET = 11'h 1a0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24_OFFSET = 11'h 1a4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25_OFFSET = 11'h 1a8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26_OFFSET = 11'h 1ac; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27_OFFSET = 11'h 1b0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28_OFFSET = 11'h 1b4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29_OFFSET = 11'h 1b8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30_OFFSET = 11'h 1bc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31_OFFSET = 11'h 1c0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32_OFFSET = 11'h 1c4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33_OFFSET = 11'h 1c8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34_OFFSET = 11'h 1cc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35_OFFSET = 11'h 1d0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36_OFFSET = 11'h 1d4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37_OFFSET = 11'h 1d8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38_OFFSET = 11'h 1dc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39_OFFSET = 11'h 1e0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40_OFFSET = 11'h 1e4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41_OFFSET = 11'h 1e8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42_OFFSET = 11'h 1ec; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43_OFFSET = 11'h 1f0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44_OFFSET = 11'h 1f4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45_OFFSET = 11'h 1f8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46_OFFSET = 11'h 1fc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47_OFFSET = 11'h 200; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48_OFFSET = 11'h 204; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49_OFFSET = 11'h 208; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50_OFFSET = 11'h 20c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51_OFFSET = 11'h 210; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52_OFFSET = 11'h 214; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53_OFFSET = 11'h 218; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54_OFFSET = 11'h 21c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55_OFFSET = 11'h 220; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56_OFFSET = 11'h 224; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57_OFFSET = 11'h 228; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58_OFFSET = 11'h 22c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59_OFFSET = 11'h 230; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60_OFFSET = 11'h 234; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61_OFFSET = 11'h 238; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62_OFFSET = 11'h 23c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63_OFFSET = 11'h 240; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_OFFSET = 11'h 244; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_OFFSET = 11'h 248; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_OFFSET = 11'h 24c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_OFFSET = 11'h 250; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_OFFSET = 11'h 254; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_OFFSET = 11'h 258; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_OFFSET = 11'h 25c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_OFFSET = 11'h 260; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_OFFSET = 11'h 264; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_OFFSET = 11'h 268; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_OFFSET = 11'h 26c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_OFFSET = 11'h 270; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_OFFSET = 11'h 274; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_OFFSET = 11'h 278; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_OFFSET = 11'h 27c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_OFFSET = 11'h 280; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_OFFSET = 11'h 284; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_OFFSET = 11'h 288; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_OFFSET = 11'h 28c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_OFFSET = 11'h 290; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_OFFSET = 11'h 294; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_OFFSET = 11'h 298; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_OFFSET = 11'h 29c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_OFFSET = 11'h 2a0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_OFFSET = 11'h 2a4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_OFFSET = 11'h 2a8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_OFFSET = 11'h 2ac; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_OFFSET = 11'h 2b0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_OFFSET = 11'h 2b4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_OFFSET = 11'h 2b8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_OFFSET = 11'h 2bc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_OFFSET = 11'h 2c0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_OFFSET = 11'h 2c4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_OFFSET = 11'h 2c8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_OFFSET = 11'h 2cc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_OFFSET = 11'h 2d0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_OFFSET = 11'h 2d4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_OFFSET = 11'h 2d8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_OFFSET = 11'h 2dc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_OFFSET = 11'h 2e0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_OFFSET = 11'h 2e4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_OFFSET = 11'h 2e8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_OFFSET = 11'h 2ec; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_OFFSET = 11'h 2f0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_OFFSET = 11'h 2f4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_OFFSET = 11'h 2f8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_OFFSET = 11'h 2fc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_OFFSET = 11'h 300; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_OFFSET = 11'h 304; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_OFFSET = 11'h 308; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_OFFSET = 11'h 30c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_OFFSET = 11'h 310; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_OFFSET = 11'h 314; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_OFFSET = 11'h 318; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_OFFSET = 11'h 31c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_OFFSET = 11'h 320; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_OFFSET = 11'h 324; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_OFFSET = 11'h 328; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_OFFSET = 11'h 32c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_OFFSET = 11'h 330; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_OFFSET = 11'h 334; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_OFFSET = 11'h 338; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_OFFSET = 11'h 33c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_OFFSET = 11'h 340; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_OFFSET = 11'h 344; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_OFFSET = 11'h 348; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_OFFSET = 11'h 34c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_OFFSET = 11'h 350; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_OFFSET = 11'h 354; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_OFFSET = 11'h 358; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_OFFSET = 11'h 35c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_OFFSET = 11'h 360; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_OFFSET = 11'h 364; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_OFFSET = 11'h 368; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_OFFSET = 11'h 36c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_OFFSET = 11'h 370; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_OFFSET = 11'h 374; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_OFFSET = 11'h 378; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_OFFSET = 11'h 37c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_OFFSET = 11'h 380; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_OFFSET = 11'h 384; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_OFFSET = 11'h 388; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_OFFSET = 11'h 38c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_OFFSET = 11'h 390; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_OFFSET = 11'h 394; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_OFFSET = 11'h 398; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_OFFSET = 11'h 39c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_OFFSET = 11'h 3a0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_OFFSET = 11'h 3a4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_OFFSET = 11'h 3a8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_OFFSET = 11'h 3ac; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_OFFSET = 11'h 3b0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_OFFSET = 11'h 3b4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_OFFSET = 11'h 3b8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_OFFSET = 11'h 3bc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_OFFSET = 11'h 3c0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_OFFSET = 11'h 3c4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_OFFSET = 11'h 3c8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_OFFSET = 11'h 3cc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_OFFSET = 11'h 3d0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_OFFSET = 11'h 3d4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_OFFSET = 11'h 3d8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_OFFSET = 11'h 3dc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_OFFSET = 11'h 3e0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_OFFSET = 11'h 3e4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_OFFSET = 11'h 3e8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_OFFSET = 11'h 3ec; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_OFFSET = 11'h 3f0; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_OFFSET = 11'h 3f4; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_OFFSET = 11'h 3f8; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_OFFSET = 11'h 3fc; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_OFFSET = 11'h 400; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_OFFSET = 11'h 404; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_OFFSET = 11'h 408; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_OFFSET = 11'h 40c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_OFFSET = 11'h 410; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_OFFSET = 11'h 414; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_OFFSET = 11'h 418; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_OFFSET = 11'h 41c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_OFFSET = 11'h 420; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_OFFSET = 11'h 424; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_OFFSET = 11'h 428; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_OFFSET = 11'h 42c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_OFFSET = 11'h 430; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_OFFSET = 11'h 434; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_OFFSET = 11'h 438; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_OFFSET = 11'h 43c; - parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET = 13'h 0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 13'h 4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET = 13'h 8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET = 13'h c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET = 13'h 10; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET = 13'h 14; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET = 13'h 18; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET = 13'h 1c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_OFFSET = 13'h 20; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_OFFSET = 13'h 24; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET = 13'h 28; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET = 13'h 2c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET = 13'h 30; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET = 13'h 34; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET = 13'h 38; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET = 13'h 3c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET = 13'h 40; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_OFFSET = 13'h 44; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_OFFSET = 13'h 48; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_OFFSET = 13'h 4c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_OFFSET = 13'h 50; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_OFFSET = 13'h 54; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_OFFSET = 13'h 58; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_OFFSET = 13'h 5c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_OFFSET = 13'h 60; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_OFFSET = 13'h 64; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_OFFSET = 13'h 68; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_OFFSET = 13'h 6c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_OFFSET = 13'h 70; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_OFFSET = 13'h 74; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_OFFSET = 13'h 78; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_OFFSET = 13'h 7c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_OFFSET = 13'h 80; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_OFFSET = 13'h 84; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_OFFSET = 13'h 88; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_OFFSET = 13'h 8c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_OFFSET = 13'h 90; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_OFFSET = 13'h 94; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_OFFSET = 13'h 98; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_OFFSET = 13'h 9c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_OFFSET = 13'h a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_OFFSET = 13'h a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_OFFSET = 13'h a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_OFFSET = 13'h ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_OFFSET = 13'h b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_OFFSET = 13'h b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_OFFSET = 13'h b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_OFFSET = 13'h bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_OFFSET = 13'h c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_OFFSET = 13'h c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_OFFSET = 13'h c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_OFFSET = 13'h cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_OFFSET = 13'h d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_OFFSET = 13'h d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_OFFSET = 13'h d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_OFFSET = 13'h dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_OFFSET = 13'h e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_OFFSET = 13'h e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_OFFSET = 13'h e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_OFFSET = 13'h ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_OFFSET = 13'h f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_OFFSET = 13'h f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_OFFSET = 13'h f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_OFFSET = 13'h fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_OFFSET = 13'h 100; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_OFFSET = 13'h 104; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_OFFSET = 13'h 108; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_OFFSET = 13'h 10c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_OFFSET = 13'h 110; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_OFFSET = 13'h 114; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_OFFSET = 13'h 118; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_OFFSET = 13'h 11c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_OFFSET = 13'h 120; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_OFFSET = 13'h 124; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_OFFSET = 13'h 128; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_OFFSET = 13'h 12c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_OFFSET = 13'h 130; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_OFFSET = 13'h 134; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_OFFSET = 13'h 138; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_OFFSET = 13'h 13c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OFFSET = 13'h 140; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_64_OFFSET = 13'h 144; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_65_OFFSET = 13'h 148; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_66_OFFSET = 13'h 14c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_67_OFFSET = 13'h 150; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_68_OFFSET = 13'h 154; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_69_OFFSET = 13'h 158; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_70_OFFSET = 13'h 15c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_71_OFFSET = 13'h 160; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_72_OFFSET = 13'h 164; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_73_OFFSET = 13'h 168; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_74_OFFSET = 13'h 16c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_75_OFFSET = 13'h 170; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_76_OFFSET = 13'h 174; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_77_OFFSET = 13'h 178; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_78_OFFSET = 13'h 17c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_79_OFFSET = 13'h 180; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_80_OFFSET = 13'h 184; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_81_OFFSET = 13'h 188; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_82_OFFSET = 13'h 18c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_83_OFFSET = 13'h 190; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_84_OFFSET = 13'h 194; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_85_OFFSET = 13'h 198; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_86_OFFSET = 13'h 19c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_87_OFFSET = 13'h 1a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_88_OFFSET = 13'h 1a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_89_OFFSET = 13'h 1a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_90_OFFSET = 13'h 1ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_91_OFFSET = 13'h 1b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_92_OFFSET = 13'h 1b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_93_OFFSET = 13'h 1b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_94_OFFSET = 13'h 1bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_95_OFFSET = 13'h 1c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_96_OFFSET = 13'h 1c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_97_OFFSET = 13'h 1c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_98_OFFSET = 13'h 1cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_99_OFFSET = 13'h 1d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_100_OFFSET = 13'h 1d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_101_OFFSET = 13'h 1d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_102_OFFSET = 13'h 1dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_103_OFFSET = 13'h 1e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_104_OFFSET = 13'h 1e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_105_OFFSET = 13'h 1e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_106_OFFSET = 13'h 1ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_107_OFFSET = 13'h 1f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_108_OFFSET = 13'h 1f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_109_OFFSET = 13'h 1f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_110_OFFSET = 13'h 1fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_111_OFFSET = 13'h 200; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_112_OFFSET = 13'h 204; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_113_OFFSET = 13'h 208; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_114_OFFSET = 13'h 20c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_115_OFFSET = 13'h 210; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_116_OFFSET = 13'h 214; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_117_OFFSET = 13'h 218; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_118_OFFSET = 13'h 21c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_119_OFFSET = 13'h 220; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_120_OFFSET = 13'h 224; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_121_OFFSET = 13'h 228; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_122_OFFSET = 13'h 22c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_123_OFFSET = 13'h 230; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_124_OFFSET = 13'h 234; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_125_OFFSET = 13'h 238; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_126_OFFSET = 13'h 23c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_127_OFFSET = 13'h 240; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_128_OFFSET = 13'h 244; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_129_OFFSET = 13'h 248; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_130_OFFSET = 13'h 24c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_131_OFFSET = 13'h 250; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_132_OFFSET = 13'h 254; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_133_OFFSET = 13'h 258; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_134_OFFSET = 13'h 25c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_135_OFFSET = 13'h 260; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_136_OFFSET = 13'h 264; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_137_OFFSET = 13'h 268; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_138_OFFSET = 13'h 26c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_139_OFFSET = 13'h 270; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_140_OFFSET = 13'h 274; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_141_OFFSET = 13'h 278; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_142_OFFSET = 13'h 27c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_143_OFFSET = 13'h 280; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_144_OFFSET = 13'h 284; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_145_OFFSET = 13'h 288; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_146_OFFSET = 13'h 28c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_147_OFFSET = 13'h 290; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_148_OFFSET = 13'h 294; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_149_OFFSET = 13'h 298; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_150_OFFSET = 13'h 29c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_151_OFFSET = 13'h 2a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_152_OFFSET = 13'h 2a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_153_OFFSET = 13'h 2a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_154_OFFSET = 13'h 2ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_155_OFFSET = 13'h 2b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_156_OFFSET = 13'h 2b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_157_OFFSET = 13'h 2b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_158_OFFSET = 13'h 2bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_159_OFFSET = 13'h 2c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_160_OFFSET = 13'h 2c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_161_OFFSET = 13'h 2c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_162_OFFSET = 13'h 2cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_163_OFFSET = 13'h 2d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_164_OFFSET = 13'h 2d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_165_OFFSET = 13'h 2d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_166_OFFSET = 13'h 2dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_167_OFFSET = 13'h 2e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_168_OFFSET = 13'h 2e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_169_OFFSET = 13'h 2e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_170_OFFSET = 13'h 2ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_171_OFFSET = 13'h 2f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_172_OFFSET = 13'h 2f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_173_OFFSET = 13'h 2f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_174_OFFSET = 13'h 2fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_175_OFFSET = 13'h 300; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_176_OFFSET = 13'h 304; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_177_OFFSET = 13'h 308; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_178_OFFSET = 13'h 30c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_179_OFFSET = 13'h 310; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_180_OFFSET = 13'h 314; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_181_OFFSET = 13'h 318; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_182_OFFSET = 13'h 31c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_183_OFFSET = 13'h 320; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_184_OFFSET = 13'h 324; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_185_OFFSET = 13'h 328; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_186_OFFSET = 13'h 32c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_187_OFFSET = 13'h 330; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_188_OFFSET = 13'h 334; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_189_OFFSET = 13'h 338; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_190_OFFSET = 13'h 33c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_191_OFFSET = 13'h 340; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_192_OFFSET = 13'h 344; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_193_OFFSET = 13'h 348; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_194_OFFSET = 13'h 34c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_195_OFFSET = 13'h 350; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_196_OFFSET = 13'h 354; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_197_OFFSET = 13'h 358; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_198_OFFSET = 13'h 35c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_199_OFFSET = 13'h 360; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_200_OFFSET = 13'h 364; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_201_OFFSET = 13'h 368; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_202_OFFSET = 13'h 36c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_203_OFFSET = 13'h 370; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_204_OFFSET = 13'h 374; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_205_OFFSET = 13'h 378; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_206_OFFSET = 13'h 37c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_207_OFFSET = 13'h 380; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_208_OFFSET = 13'h 384; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_209_OFFSET = 13'h 388; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_210_OFFSET = 13'h 38c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_211_OFFSET = 13'h 390; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_212_OFFSET = 13'h 394; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_213_OFFSET = 13'h 398; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_214_OFFSET = 13'h 39c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_215_OFFSET = 13'h 3a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_216_OFFSET = 13'h 3a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_217_OFFSET = 13'h 3a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_218_OFFSET = 13'h 3ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_219_OFFSET = 13'h 3b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_220_OFFSET = 13'h 3b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_221_OFFSET = 13'h 3b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_222_OFFSET = 13'h 3bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_223_OFFSET = 13'h 3c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_224_OFFSET = 13'h 3c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_225_OFFSET = 13'h 3c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_226_OFFSET = 13'h 3cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_227_OFFSET = 13'h 3d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_228_OFFSET = 13'h 3d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_229_OFFSET = 13'h 3d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_230_OFFSET = 13'h 3dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_231_OFFSET = 13'h 3e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_232_OFFSET = 13'h 3e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_233_OFFSET = 13'h 3e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_234_OFFSET = 13'h 3ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_235_OFFSET = 13'h 3f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_236_OFFSET = 13'h 3f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_237_OFFSET = 13'h 3f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_238_OFFSET = 13'h 3fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_239_OFFSET = 13'h 400; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_240_OFFSET = 13'h 404; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_241_OFFSET = 13'h 408; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_242_OFFSET = 13'h 40c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_243_OFFSET = 13'h 410; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_244_OFFSET = 13'h 414; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_245_OFFSET = 13'h 418; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_246_OFFSET = 13'h 41c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_247_OFFSET = 13'h 420; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_248_OFFSET = 13'h 424; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_249_OFFSET = 13'h 428; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_250_OFFSET = 13'h 42c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_251_OFFSET = 13'h 430; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_252_OFFSET = 13'h 434; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_253_OFFSET = 13'h 438; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_254_OFFSET = 13'h 43c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_255_OFFSET = 13'h 440; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0_OFFSET = 13'h 444; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1_OFFSET = 13'h 448; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2_OFFSET = 13'h 44c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3_OFFSET = 13'h 450; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4_OFFSET = 13'h 454; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5_OFFSET = 13'h 458; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6_OFFSET = 13'h 45c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7_OFFSET = 13'h 460; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8_OFFSET = 13'h 464; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9_OFFSET = 13'h 468; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10_OFFSET = 13'h 46c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11_OFFSET = 13'h 470; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12_OFFSET = 13'h 474; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13_OFFSET = 13'h 478; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14_OFFSET = 13'h 47c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15_OFFSET = 13'h 480; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16_OFFSET = 13'h 484; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17_OFFSET = 13'h 488; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18_OFFSET = 13'h 48c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19_OFFSET = 13'h 490; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20_OFFSET = 13'h 494; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21_OFFSET = 13'h 498; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22_OFFSET = 13'h 49c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23_OFFSET = 13'h 4a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24_OFFSET = 13'h 4a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25_OFFSET = 13'h 4a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26_OFFSET = 13'h 4ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27_OFFSET = 13'h 4b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28_OFFSET = 13'h 4b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29_OFFSET = 13'h 4b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30_OFFSET = 13'h 4bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31_OFFSET = 13'h 4c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32_OFFSET = 13'h 4c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33_OFFSET = 13'h 4c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34_OFFSET = 13'h 4cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35_OFFSET = 13'h 4d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36_OFFSET = 13'h 4d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37_OFFSET = 13'h 4d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38_OFFSET = 13'h 4dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39_OFFSET = 13'h 4e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40_OFFSET = 13'h 4e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41_OFFSET = 13'h 4e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42_OFFSET = 13'h 4ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43_OFFSET = 13'h 4f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44_OFFSET = 13'h 4f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45_OFFSET = 13'h 4f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46_OFFSET = 13'h 4fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47_OFFSET = 13'h 500; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48_OFFSET = 13'h 504; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49_OFFSET = 13'h 508; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50_OFFSET = 13'h 50c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51_OFFSET = 13'h 510; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52_OFFSET = 13'h 514; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53_OFFSET = 13'h 518; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54_OFFSET = 13'h 51c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55_OFFSET = 13'h 520; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56_OFFSET = 13'h 524; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57_OFFSET = 13'h 528; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58_OFFSET = 13'h 52c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59_OFFSET = 13'h 530; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60_OFFSET = 13'h 534; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61_OFFSET = 13'h 538; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62_OFFSET = 13'h 53c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63_OFFSET = 13'h 540; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_64_OFFSET = 13'h 544; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_65_OFFSET = 13'h 548; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_66_OFFSET = 13'h 54c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_67_OFFSET = 13'h 550; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_68_OFFSET = 13'h 554; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_69_OFFSET = 13'h 558; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_70_OFFSET = 13'h 55c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_71_OFFSET = 13'h 560; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_72_OFFSET = 13'h 564; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_73_OFFSET = 13'h 568; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_74_OFFSET = 13'h 56c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_75_OFFSET = 13'h 570; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_76_OFFSET = 13'h 574; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_77_OFFSET = 13'h 578; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_78_OFFSET = 13'h 57c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_79_OFFSET = 13'h 580; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_80_OFFSET = 13'h 584; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_81_OFFSET = 13'h 588; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_82_OFFSET = 13'h 58c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_83_OFFSET = 13'h 590; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_84_OFFSET = 13'h 594; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_85_OFFSET = 13'h 598; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_86_OFFSET = 13'h 59c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_87_OFFSET = 13'h 5a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_88_OFFSET = 13'h 5a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_89_OFFSET = 13'h 5a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_90_OFFSET = 13'h 5ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_91_OFFSET = 13'h 5b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_92_OFFSET = 13'h 5b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_93_OFFSET = 13'h 5b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_94_OFFSET = 13'h 5bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_95_OFFSET = 13'h 5c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_96_OFFSET = 13'h 5c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_97_OFFSET = 13'h 5c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_98_OFFSET = 13'h 5cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_99_OFFSET = 13'h 5d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_100_OFFSET = 13'h 5d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_101_OFFSET = 13'h 5d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_102_OFFSET = 13'h 5dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_103_OFFSET = 13'h 5e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_104_OFFSET = 13'h 5e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_105_OFFSET = 13'h 5e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_106_OFFSET = 13'h 5ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_107_OFFSET = 13'h 5f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_108_OFFSET = 13'h 5f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_109_OFFSET = 13'h 5f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_110_OFFSET = 13'h 5fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_111_OFFSET = 13'h 600; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_112_OFFSET = 13'h 604; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_113_OFFSET = 13'h 608; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_114_OFFSET = 13'h 60c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_115_OFFSET = 13'h 610; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_116_OFFSET = 13'h 614; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_117_OFFSET = 13'h 618; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_118_OFFSET = 13'h 61c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_119_OFFSET = 13'h 620; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_120_OFFSET = 13'h 624; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_121_OFFSET = 13'h 628; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_122_OFFSET = 13'h 62c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_123_OFFSET = 13'h 630; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_124_OFFSET = 13'h 634; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_125_OFFSET = 13'h 638; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_126_OFFSET = 13'h 63c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_127_OFFSET = 13'h 640; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_128_OFFSET = 13'h 644; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_129_OFFSET = 13'h 648; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_130_OFFSET = 13'h 64c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_131_OFFSET = 13'h 650; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_132_OFFSET = 13'h 654; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_133_OFFSET = 13'h 658; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_134_OFFSET = 13'h 65c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_135_OFFSET = 13'h 660; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_136_OFFSET = 13'h 664; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_137_OFFSET = 13'h 668; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_138_OFFSET = 13'h 66c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_139_OFFSET = 13'h 670; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_140_OFFSET = 13'h 674; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_141_OFFSET = 13'h 678; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_142_OFFSET = 13'h 67c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_143_OFFSET = 13'h 680; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_144_OFFSET = 13'h 684; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_145_OFFSET = 13'h 688; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_146_OFFSET = 13'h 68c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_147_OFFSET = 13'h 690; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_148_OFFSET = 13'h 694; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_149_OFFSET = 13'h 698; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_150_OFFSET = 13'h 69c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_151_OFFSET = 13'h 6a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_152_OFFSET = 13'h 6a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_153_OFFSET = 13'h 6a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_154_OFFSET = 13'h 6ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_155_OFFSET = 13'h 6b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_156_OFFSET = 13'h 6b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_157_OFFSET = 13'h 6b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_158_OFFSET = 13'h 6bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_159_OFFSET = 13'h 6c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_160_OFFSET = 13'h 6c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_161_OFFSET = 13'h 6c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_162_OFFSET = 13'h 6cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_163_OFFSET = 13'h 6d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_164_OFFSET = 13'h 6d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_165_OFFSET = 13'h 6d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_166_OFFSET = 13'h 6dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_167_OFFSET = 13'h 6e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_168_OFFSET = 13'h 6e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_169_OFFSET = 13'h 6e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_170_OFFSET = 13'h 6ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_171_OFFSET = 13'h 6f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_172_OFFSET = 13'h 6f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_173_OFFSET = 13'h 6f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_174_OFFSET = 13'h 6fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_175_OFFSET = 13'h 700; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_176_OFFSET = 13'h 704; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_177_OFFSET = 13'h 708; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_178_OFFSET = 13'h 70c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_179_OFFSET = 13'h 710; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_180_OFFSET = 13'h 714; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_181_OFFSET = 13'h 718; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_182_OFFSET = 13'h 71c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_183_OFFSET = 13'h 720; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_184_OFFSET = 13'h 724; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_185_OFFSET = 13'h 728; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_186_OFFSET = 13'h 72c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_187_OFFSET = 13'h 730; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_188_OFFSET = 13'h 734; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_189_OFFSET = 13'h 738; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_190_OFFSET = 13'h 73c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_191_OFFSET = 13'h 740; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_192_OFFSET = 13'h 744; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_193_OFFSET = 13'h 748; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_194_OFFSET = 13'h 74c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_195_OFFSET = 13'h 750; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_196_OFFSET = 13'h 754; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_197_OFFSET = 13'h 758; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_198_OFFSET = 13'h 75c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_199_OFFSET = 13'h 760; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_200_OFFSET = 13'h 764; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_201_OFFSET = 13'h 768; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_202_OFFSET = 13'h 76c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_203_OFFSET = 13'h 770; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_204_OFFSET = 13'h 774; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_205_OFFSET = 13'h 778; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_206_OFFSET = 13'h 77c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_207_OFFSET = 13'h 780; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_208_OFFSET = 13'h 784; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_209_OFFSET = 13'h 788; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_210_OFFSET = 13'h 78c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_211_OFFSET = 13'h 790; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_212_OFFSET = 13'h 794; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_213_OFFSET = 13'h 798; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_214_OFFSET = 13'h 79c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_215_OFFSET = 13'h 7a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_216_OFFSET = 13'h 7a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_217_OFFSET = 13'h 7a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_218_OFFSET = 13'h 7ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_219_OFFSET = 13'h 7b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_220_OFFSET = 13'h 7b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_221_OFFSET = 13'h 7b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_222_OFFSET = 13'h 7bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_223_OFFSET = 13'h 7c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_224_OFFSET = 13'h 7c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_225_OFFSET = 13'h 7c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_226_OFFSET = 13'h 7cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_227_OFFSET = 13'h 7d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_228_OFFSET = 13'h 7d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_229_OFFSET = 13'h 7d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_230_OFFSET = 13'h 7dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_231_OFFSET = 13'h 7e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_232_OFFSET = 13'h 7e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_233_OFFSET = 13'h 7e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_234_OFFSET = 13'h 7ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_235_OFFSET = 13'h 7f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_236_OFFSET = 13'h 7f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_237_OFFSET = 13'h 7f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_238_OFFSET = 13'h 7fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_239_OFFSET = 13'h 800; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_240_OFFSET = 13'h 804; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_241_OFFSET = 13'h 808; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_242_OFFSET = 13'h 80c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_243_OFFSET = 13'h 810; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_244_OFFSET = 13'h 814; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_245_OFFSET = 13'h 818; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_246_OFFSET = 13'h 81c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_247_OFFSET = 13'h 820; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_248_OFFSET = 13'h 824; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_249_OFFSET = 13'h 828; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_250_OFFSET = 13'h 82c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_251_OFFSET = 13'h 830; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_252_OFFSET = 13'h 834; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_253_OFFSET = 13'h 838; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_254_OFFSET = 13'h 83c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_255_OFFSET = 13'h 840; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_OFFSET = 13'h 844; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_OFFSET = 13'h 848; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_OFFSET = 13'h 84c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_OFFSET = 13'h 850; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_OFFSET = 13'h 854; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_OFFSET = 13'h 858; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_OFFSET = 13'h 85c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_OFFSET = 13'h 860; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_OFFSET = 13'h 864; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_OFFSET = 13'h 868; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_OFFSET = 13'h 86c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_OFFSET = 13'h 870; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_OFFSET = 13'h 874; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_OFFSET = 13'h 878; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_OFFSET = 13'h 87c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_OFFSET = 13'h 880; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_OFFSET = 13'h 884; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_OFFSET = 13'h 888; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_OFFSET = 13'h 88c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_OFFSET = 13'h 890; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_OFFSET = 13'h 894; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_OFFSET = 13'h 898; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_OFFSET = 13'h 89c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_OFFSET = 13'h 8a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_OFFSET = 13'h 8a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_OFFSET = 13'h 8a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_OFFSET = 13'h 8ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_OFFSET = 13'h 8b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_OFFSET = 13'h 8b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_OFFSET = 13'h 8b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_OFFSET = 13'h 8bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_OFFSET = 13'h 8c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_OFFSET = 13'h 8c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_OFFSET = 13'h 8c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_OFFSET = 13'h 8cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_OFFSET = 13'h 8d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_OFFSET = 13'h 8d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_OFFSET = 13'h 8d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_OFFSET = 13'h 8dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_OFFSET = 13'h 8e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_OFFSET = 13'h 8e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_OFFSET = 13'h 8e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_OFFSET = 13'h 8ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_OFFSET = 13'h 8f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_OFFSET = 13'h 8f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_OFFSET = 13'h 8f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_OFFSET = 13'h 8fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_OFFSET = 13'h 900; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_OFFSET = 13'h 904; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_OFFSET = 13'h 908; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_OFFSET = 13'h 90c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_OFFSET = 13'h 910; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_OFFSET = 13'h 914; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_OFFSET = 13'h 918; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_OFFSET = 13'h 91c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_OFFSET = 13'h 920; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_OFFSET = 13'h 924; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_OFFSET = 13'h 928; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_OFFSET = 13'h 92c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_OFFSET = 13'h 930; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_OFFSET = 13'h 934; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_OFFSET = 13'h 938; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_OFFSET = 13'h 93c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_OFFSET = 13'h 940; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_64_OFFSET = 13'h 944; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_65_OFFSET = 13'h 948; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_66_OFFSET = 13'h 94c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_67_OFFSET = 13'h 950; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_68_OFFSET = 13'h 954; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_69_OFFSET = 13'h 958; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_70_OFFSET = 13'h 95c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_71_OFFSET = 13'h 960; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_72_OFFSET = 13'h 964; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_73_OFFSET = 13'h 968; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_74_OFFSET = 13'h 96c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_75_OFFSET = 13'h 970; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_76_OFFSET = 13'h 974; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_77_OFFSET = 13'h 978; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_78_OFFSET = 13'h 97c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_79_OFFSET = 13'h 980; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_80_OFFSET = 13'h 984; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_81_OFFSET = 13'h 988; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_82_OFFSET = 13'h 98c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_83_OFFSET = 13'h 990; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_84_OFFSET = 13'h 994; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_85_OFFSET = 13'h 998; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_86_OFFSET = 13'h 99c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_87_OFFSET = 13'h 9a0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_88_OFFSET = 13'h 9a4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_89_OFFSET = 13'h 9a8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_90_OFFSET = 13'h 9ac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_91_OFFSET = 13'h 9b0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_92_OFFSET = 13'h 9b4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_93_OFFSET = 13'h 9b8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_94_OFFSET = 13'h 9bc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_95_OFFSET = 13'h 9c0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_96_OFFSET = 13'h 9c4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_97_OFFSET = 13'h 9c8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_98_OFFSET = 13'h 9cc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_99_OFFSET = 13'h 9d0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_100_OFFSET = 13'h 9d4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_101_OFFSET = 13'h 9d8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_102_OFFSET = 13'h 9dc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_103_OFFSET = 13'h 9e0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_104_OFFSET = 13'h 9e4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_105_OFFSET = 13'h 9e8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_106_OFFSET = 13'h 9ec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_107_OFFSET = 13'h 9f0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_108_OFFSET = 13'h 9f4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_109_OFFSET = 13'h 9f8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_110_OFFSET = 13'h 9fc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_111_OFFSET = 13'h a00; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_112_OFFSET = 13'h a04; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_113_OFFSET = 13'h a08; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_114_OFFSET = 13'h a0c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_115_OFFSET = 13'h a10; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_116_OFFSET = 13'h a14; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_117_OFFSET = 13'h a18; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_118_OFFSET = 13'h a1c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_119_OFFSET = 13'h a20; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_120_OFFSET = 13'h a24; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_121_OFFSET = 13'h a28; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_122_OFFSET = 13'h a2c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_123_OFFSET = 13'h a30; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_124_OFFSET = 13'h a34; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_125_OFFSET = 13'h a38; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_126_OFFSET = 13'h a3c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_127_OFFSET = 13'h a40; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_128_OFFSET = 13'h a44; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_129_OFFSET = 13'h a48; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_130_OFFSET = 13'h a4c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_131_OFFSET = 13'h a50; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_132_OFFSET = 13'h a54; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_133_OFFSET = 13'h a58; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_134_OFFSET = 13'h a5c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_135_OFFSET = 13'h a60; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_136_OFFSET = 13'h a64; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_137_OFFSET = 13'h a68; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_138_OFFSET = 13'h a6c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_139_OFFSET = 13'h a70; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_140_OFFSET = 13'h a74; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_141_OFFSET = 13'h a78; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_142_OFFSET = 13'h a7c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_143_OFFSET = 13'h a80; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_144_OFFSET = 13'h a84; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_145_OFFSET = 13'h a88; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_146_OFFSET = 13'h a8c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_147_OFFSET = 13'h a90; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_148_OFFSET = 13'h a94; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_149_OFFSET = 13'h a98; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_150_OFFSET = 13'h a9c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_151_OFFSET = 13'h aa0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_152_OFFSET = 13'h aa4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_153_OFFSET = 13'h aa8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_154_OFFSET = 13'h aac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_155_OFFSET = 13'h ab0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_156_OFFSET = 13'h ab4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_157_OFFSET = 13'h ab8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_158_OFFSET = 13'h abc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_159_OFFSET = 13'h ac0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_160_OFFSET = 13'h ac4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_161_OFFSET = 13'h ac8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_162_OFFSET = 13'h acc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_163_OFFSET = 13'h ad0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_164_OFFSET = 13'h ad4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_165_OFFSET = 13'h ad8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_166_OFFSET = 13'h adc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_167_OFFSET = 13'h ae0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_168_OFFSET = 13'h ae4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_169_OFFSET = 13'h ae8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_170_OFFSET = 13'h aec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_171_OFFSET = 13'h af0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_172_OFFSET = 13'h af4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_173_OFFSET = 13'h af8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_174_OFFSET = 13'h afc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_175_OFFSET = 13'h b00; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_176_OFFSET = 13'h b04; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_177_OFFSET = 13'h b08; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_178_OFFSET = 13'h b0c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_179_OFFSET = 13'h b10; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_180_OFFSET = 13'h b14; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_181_OFFSET = 13'h b18; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_182_OFFSET = 13'h b1c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_183_OFFSET = 13'h b20; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_184_OFFSET = 13'h b24; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_185_OFFSET = 13'h b28; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_186_OFFSET = 13'h b2c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_187_OFFSET = 13'h b30; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_188_OFFSET = 13'h b34; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_189_OFFSET = 13'h b38; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_190_OFFSET = 13'h b3c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_191_OFFSET = 13'h b40; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_192_OFFSET = 13'h b44; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_193_OFFSET = 13'h b48; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_194_OFFSET = 13'h b4c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_195_OFFSET = 13'h b50; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_196_OFFSET = 13'h b54; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_197_OFFSET = 13'h b58; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_198_OFFSET = 13'h b5c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_199_OFFSET = 13'h b60; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_200_OFFSET = 13'h b64; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_201_OFFSET = 13'h b68; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_202_OFFSET = 13'h b6c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_203_OFFSET = 13'h b70; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_204_OFFSET = 13'h b74; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_205_OFFSET = 13'h b78; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_206_OFFSET = 13'h b7c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_207_OFFSET = 13'h b80; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_208_OFFSET = 13'h b84; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_209_OFFSET = 13'h b88; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_210_OFFSET = 13'h b8c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_211_OFFSET = 13'h b90; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_212_OFFSET = 13'h b94; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_213_OFFSET = 13'h b98; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_214_OFFSET = 13'h b9c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_215_OFFSET = 13'h ba0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_216_OFFSET = 13'h ba4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_217_OFFSET = 13'h ba8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_218_OFFSET = 13'h bac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_219_OFFSET = 13'h bb0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_220_OFFSET = 13'h bb4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_221_OFFSET = 13'h bb8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_222_OFFSET = 13'h bbc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_223_OFFSET = 13'h bc0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_224_OFFSET = 13'h bc4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_225_OFFSET = 13'h bc8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_226_OFFSET = 13'h bcc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_227_OFFSET = 13'h bd0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_228_OFFSET = 13'h bd4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_229_OFFSET = 13'h bd8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_230_OFFSET = 13'h bdc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_231_OFFSET = 13'h be0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_232_OFFSET = 13'h be4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_233_OFFSET = 13'h be8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_234_OFFSET = 13'h bec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_235_OFFSET = 13'h bf0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_236_OFFSET = 13'h bf4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_237_OFFSET = 13'h bf8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_238_OFFSET = 13'h bfc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_239_OFFSET = 13'h c00; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_240_OFFSET = 13'h c04; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_241_OFFSET = 13'h c08; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_242_OFFSET = 13'h c0c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_243_OFFSET = 13'h c10; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_244_OFFSET = 13'h c14; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_245_OFFSET = 13'h c18; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_246_OFFSET = 13'h c1c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_247_OFFSET = 13'h c20; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_248_OFFSET = 13'h c24; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_249_OFFSET = 13'h c28; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_250_OFFSET = 13'h c2c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_251_OFFSET = 13'h c30; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_252_OFFSET = 13'h c34; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_253_OFFSET = 13'h c38; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_254_OFFSET = 13'h c3c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_255_OFFSET = 13'h c40; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_OFFSET = 13'h c44; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_OFFSET = 13'h c48; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_OFFSET = 13'h c4c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_OFFSET = 13'h c50; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_OFFSET = 13'h c54; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_OFFSET = 13'h c58; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_OFFSET = 13'h c5c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_OFFSET = 13'h c60; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_OFFSET = 13'h c64; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_OFFSET = 13'h c68; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_OFFSET = 13'h c6c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_OFFSET = 13'h c70; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_OFFSET = 13'h c74; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_OFFSET = 13'h c78; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_OFFSET = 13'h c7c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_OFFSET = 13'h c80; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_OFFSET = 13'h c84; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_OFFSET = 13'h c88; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_OFFSET = 13'h c8c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_OFFSET = 13'h c90; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_OFFSET = 13'h c94; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_OFFSET = 13'h c98; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_OFFSET = 13'h c9c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_OFFSET = 13'h ca0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_OFFSET = 13'h ca4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_OFFSET = 13'h ca8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_OFFSET = 13'h cac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_OFFSET = 13'h cb0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_OFFSET = 13'h cb4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_OFFSET = 13'h cb8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_OFFSET = 13'h cbc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_OFFSET = 13'h cc0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_OFFSET = 13'h cc4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_OFFSET = 13'h cc8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_OFFSET = 13'h ccc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_OFFSET = 13'h cd0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_OFFSET = 13'h cd4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_OFFSET = 13'h cd8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_OFFSET = 13'h cdc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_OFFSET = 13'h ce0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_OFFSET = 13'h ce4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_OFFSET = 13'h ce8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_OFFSET = 13'h cec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_OFFSET = 13'h cf0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_OFFSET = 13'h cf4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_OFFSET = 13'h cf8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_OFFSET = 13'h cfc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_OFFSET = 13'h d00; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_OFFSET = 13'h d04; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_OFFSET = 13'h d08; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_OFFSET = 13'h d0c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_OFFSET = 13'h d10; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_OFFSET = 13'h d14; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_OFFSET = 13'h d18; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_OFFSET = 13'h d1c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_OFFSET = 13'h d20; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_OFFSET = 13'h d24; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_OFFSET = 13'h d28; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_OFFSET = 13'h d2c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_OFFSET = 13'h d30; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_OFFSET = 13'h d34; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_OFFSET = 13'h d38; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_OFFSET = 13'h d3c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_OFFSET = 13'h d40; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_64_OFFSET = 13'h d44; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_65_OFFSET = 13'h d48; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_66_OFFSET = 13'h d4c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_67_OFFSET = 13'h d50; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_68_OFFSET = 13'h d54; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_69_OFFSET = 13'h d58; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_70_OFFSET = 13'h d5c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_71_OFFSET = 13'h d60; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_72_OFFSET = 13'h d64; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_73_OFFSET = 13'h d68; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_74_OFFSET = 13'h d6c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_75_OFFSET = 13'h d70; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_76_OFFSET = 13'h d74; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_77_OFFSET = 13'h d78; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_78_OFFSET = 13'h d7c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_79_OFFSET = 13'h d80; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_80_OFFSET = 13'h d84; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_81_OFFSET = 13'h d88; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_82_OFFSET = 13'h d8c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_83_OFFSET = 13'h d90; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_84_OFFSET = 13'h d94; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_85_OFFSET = 13'h d98; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_86_OFFSET = 13'h d9c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_87_OFFSET = 13'h da0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_88_OFFSET = 13'h da4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_89_OFFSET = 13'h da8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_90_OFFSET = 13'h dac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_91_OFFSET = 13'h db0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_92_OFFSET = 13'h db4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_93_OFFSET = 13'h db8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_94_OFFSET = 13'h dbc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_95_OFFSET = 13'h dc0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_96_OFFSET = 13'h dc4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_97_OFFSET = 13'h dc8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_98_OFFSET = 13'h dcc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_99_OFFSET = 13'h dd0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_100_OFFSET = 13'h dd4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_101_OFFSET = 13'h dd8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_102_OFFSET = 13'h ddc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_103_OFFSET = 13'h de0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_104_OFFSET = 13'h de4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_105_OFFSET = 13'h de8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_106_OFFSET = 13'h dec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_107_OFFSET = 13'h df0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_108_OFFSET = 13'h df4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_109_OFFSET = 13'h df8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_110_OFFSET = 13'h dfc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_111_OFFSET = 13'h e00; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_112_OFFSET = 13'h e04; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_113_OFFSET = 13'h e08; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_114_OFFSET = 13'h e0c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_115_OFFSET = 13'h e10; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_116_OFFSET = 13'h e14; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_117_OFFSET = 13'h e18; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_118_OFFSET = 13'h e1c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_119_OFFSET = 13'h e20; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_120_OFFSET = 13'h e24; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_121_OFFSET = 13'h e28; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_122_OFFSET = 13'h e2c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_123_OFFSET = 13'h e30; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_124_OFFSET = 13'h e34; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_125_OFFSET = 13'h e38; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_126_OFFSET = 13'h e3c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_127_OFFSET = 13'h e40; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_128_OFFSET = 13'h e44; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_129_OFFSET = 13'h e48; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_130_OFFSET = 13'h e4c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_131_OFFSET = 13'h e50; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_132_OFFSET = 13'h e54; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_133_OFFSET = 13'h e58; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_134_OFFSET = 13'h e5c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_135_OFFSET = 13'h e60; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_136_OFFSET = 13'h e64; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_137_OFFSET = 13'h e68; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_138_OFFSET = 13'h e6c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_139_OFFSET = 13'h e70; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_140_OFFSET = 13'h e74; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_141_OFFSET = 13'h e78; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_142_OFFSET = 13'h e7c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_143_OFFSET = 13'h e80; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_144_OFFSET = 13'h e84; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_145_OFFSET = 13'h e88; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_146_OFFSET = 13'h e8c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_147_OFFSET = 13'h e90; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_148_OFFSET = 13'h e94; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_149_OFFSET = 13'h e98; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_150_OFFSET = 13'h e9c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_151_OFFSET = 13'h ea0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_152_OFFSET = 13'h ea4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_153_OFFSET = 13'h ea8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_154_OFFSET = 13'h eac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_155_OFFSET = 13'h eb0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_156_OFFSET = 13'h eb4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_157_OFFSET = 13'h eb8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_158_OFFSET = 13'h ebc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_159_OFFSET = 13'h ec0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_160_OFFSET = 13'h ec4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_161_OFFSET = 13'h ec8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_162_OFFSET = 13'h ecc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_163_OFFSET = 13'h ed0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_164_OFFSET = 13'h ed4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_165_OFFSET = 13'h ed8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_166_OFFSET = 13'h edc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_167_OFFSET = 13'h ee0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_168_OFFSET = 13'h ee4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_169_OFFSET = 13'h ee8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_170_OFFSET = 13'h eec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_171_OFFSET = 13'h ef0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_172_OFFSET = 13'h ef4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_173_OFFSET = 13'h ef8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_174_OFFSET = 13'h efc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_175_OFFSET = 13'h f00; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_176_OFFSET = 13'h f04; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_177_OFFSET = 13'h f08; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_178_OFFSET = 13'h f0c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_179_OFFSET = 13'h f10; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_180_OFFSET = 13'h f14; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_181_OFFSET = 13'h f18; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_182_OFFSET = 13'h f1c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_183_OFFSET = 13'h f20; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_184_OFFSET = 13'h f24; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_185_OFFSET = 13'h f28; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_186_OFFSET = 13'h f2c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_187_OFFSET = 13'h f30; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_188_OFFSET = 13'h f34; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_189_OFFSET = 13'h f38; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_190_OFFSET = 13'h f3c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_191_OFFSET = 13'h f40; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_192_OFFSET = 13'h f44; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_193_OFFSET = 13'h f48; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_194_OFFSET = 13'h f4c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_195_OFFSET = 13'h f50; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_196_OFFSET = 13'h f54; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_197_OFFSET = 13'h f58; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_198_OFFSET = 13'h f5c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_199_OFFSET = 13'h f60; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_200_OFFSET = 13'h f64; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_201_OFFSET = 13'h f68; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_202_OFFSET = 13'h f6c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_203_OFFSET = 13'h f70; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_204_OFFSET = 13'h f74; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_205_OFFSET = 13'h f78; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_206_OFFSET = 13'h f7c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_207_OFFSET = 13'h f80; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_208_OFFSET = 13'h f84; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_209_OFFSET = 13'h f88; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_210_OFFSET = 13'h f8c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_211_OFFSET = 13'h f90; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_212_OFFSET = 13'h f94; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_213_OFFSET = 13'h f98; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_214_OFFSET = 13'h f9c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_215_OFFSET = 13'h fa0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_216_OFFSET = 13'h fa4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_217_OFFSET = 13'h fa8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_218_OFFSET = 13'h fac; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_219_OFFSET = 13'h fb0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_220_OFFSET = 13'h fb4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_221_OFFSET = 13'h fb8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_222_OFFSET = 13'h fbc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_223_OFFSET = 13'h fc0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_224_OFFSET = 13'h fc4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_225_OFFSET = 13'h fc8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_226_OFFSET = 13'h fcc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_227_OFFSET = 13'h fd0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_228_OFFSET = 13'h fd4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_229_OFFSET = 13'h fd8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_230_OFFSET = 13'h fdc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_231_OFFSET = 13'h fe0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_232_OFFSET = 13'h fe4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_233_OFFSET = 13'h fe8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_234_OFFSET = 13'h fec; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_235_OFFSET = 13'h ff0; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_236_OFFSET = 13'h ff4; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_237_OFFSET = 13'h ff8; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_238_OFFSET = 13'h ffc; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_239_OFFSET = 13'h 1000; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_240_OFFSET = 13'h 1004; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_241_OFFSET = 13'h 1008; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_242_OFFSET = 13'h 100c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_243_OFFSET = 13'h 1010; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_244_OFFSET = 13'h 1014; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_245_OFFSET = 13'h 1018; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_246_OFFSET = 13'h 101c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_247_OFFSET = 13'h 1020; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_248_OFFSET = 13'h 1024; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_249_OFFSET = 13'h 1028; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_250_OFFSET = 13'h 102c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_251_OFFSET = 13'h 1030; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_252_OFFSET = 13'h 1034; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_253_OFFSET = 13'h 1038; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_254_OFFSET = 13'h 103c; + parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_255_OFFSET = 13'h 1040; // Reset values for hwext registers and their fields parameter logic [31:0] CACHEPOOL_PERIPHERAL_HW_BARRIER_RESVAL = 32'h 0; @@ -561,6 +1329,390 @@ package cachepool_peripheral_reg_pkg; parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_STATUS_62_RESVAL = 1'h 0; parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_RESVAL = 1'h 0; parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_STATUS_63_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_64_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_64_STATUS_64_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_65_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_65_STATUS_65_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_66_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_66_STATUS_66_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_67_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_67_STATUS_67_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_68_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_68_STATUS_68_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_69_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_69_STATUS_69_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_70_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_70_STATUS_70_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_71_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_71_STATUS_71_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_72_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_72_STATUS_72_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_73_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_73_STATUS_73_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_74_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_74_STATUS_74_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_75_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_75_STATUS_75_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_76_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_76_STATUS_76_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_77_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_77_STATUS_77_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_78_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_78_STATUS_78_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_79_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_79_STATUS_79_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_80_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_80_STATUS_80_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_81_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_81_STATUS_81_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_82_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_82_STATUS_82_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_83_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_83_STATUS_83_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_84_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_84_STATUS_84_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_85_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_85_STATUS_85_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_86_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_86_STATUS_86_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_87_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_87_STATUS_87_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_88_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_88_STATUS_88_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_89_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_89_STATUS_89_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_90_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_90_STATUS_90_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_91_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_91_STATUS_91_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_92_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_92_STATUS_92_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_93_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_93_STATUS_93_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_94_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_94_STATUS_94_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_95_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_95_STATUS_95_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_96_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_96_STATUS_96_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_97_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_97_STATUS_97_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_98_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_98_STATUS_98_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_99_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_99_STATUS_99_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_100_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_100_STATUS_100_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_101_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_101_STATUS_101_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_102_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_102_STATUS_102_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_103_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_103_STATUS_103_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_104_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_104_STATUS_104_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_105_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_105_STATUS_105_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_106_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_106_STATUS_106_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_107_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_107_STATUS_107_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_108_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_108_STATUS_108_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_109_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_109_STATUS_109_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_110_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_110_STATUS_110_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_111_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_111_STATUS_111_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_112_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_112_STATUS_112_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_113_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_113_STATUS_113_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_114_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_114_STATUS_114_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_115_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_115_STATUS_115_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_116_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_116_STATUS_116_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_117_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_117_STATUS_117_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_118_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_118_STATUS_118_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_119_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_119_STATUS_119_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_120_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_120_STATUS_120_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_121_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_121_STATUS_121_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_122_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_122_STATUS_122_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_123_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_123_STATUS_123_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_124_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_124_STATUS_124_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_125_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_125_STATUS_125_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_126_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_126_STATUS_126_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_127_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_127_STATUS_127_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_128_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_128_STATUS_128_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_129_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_129_STATUS_129_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_130_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_130_STATUS_130_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_131_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_131_STATUS_131_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_132_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_132_STATUS_132_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_133_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_133_STATUS_133_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_134_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_134_STATUS_134_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_135_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_135_STATUS_135_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_136_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_136_STATUS_136_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_137_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_137_STATUS_137_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_138_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_138_STATUS_138_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_139_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_139_STATUS_139_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_140_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_140_STATUS_140_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_141_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_141_STATUS_141_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_142_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_142_STATUS_142_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_143_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_143_STATUS_143_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_144_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_144_STATUS_144_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_145_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_145_STATUS_145_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_146_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_146_STATUS_146_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_147_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_147_STATUS_147_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_148_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_148_STATUS_148_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_149_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_149_STATUS_149_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_150_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_150_STATUS_150_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_151_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_151_STATUS_151_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_152_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_152_STATUS_152_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_153_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_153_STATUS_153_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_154_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_154_STATUS_154_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_155_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_155_STATUS_155_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_156_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_156_STATUS_156_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_157_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_157_STATUS_157_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_158_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_158_STATUS_158_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_159_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_159_STATUS_159_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_160_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_160_STATUS_160_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_161_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_161_STATUS_161_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_162_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_162_STATUS_162_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_163_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_163_STATUS_163_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_164_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_164_STATUS_164_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_165_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_165_STATUS_165_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_166_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_166_STATUS_166_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_167_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_167_STATUS_167_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_168_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_168_STATUS_168_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_169_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_169_STATUS_169_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_170_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_170_STATUS_170_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_171_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_171_STATUS_171_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_172_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_172_STATUS_172_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_173_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_173_STATUS_173_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_174_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_174_STATUS_174_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_175_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_175_STATUS_175_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_176_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_176_STATUS_176_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_177_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_177_STATUS_177_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_178_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_178_STATUS_178_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_179_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_179_STATUS_179_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_180_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_180_STATUS_180_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_181_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_181_STATUS_181_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_182_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_182_STATUS_182_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_183_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_183_STATUS_183_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_184_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_184_STATUS_184_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_185_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_185_STATUS_185_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_186_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_186_STATUS_186_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_187_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_187_STATUS_187_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_188_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_188_STATUS_188_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_189_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_189_STATUS_189_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_190_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_190_STATUS_190_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_191_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_191_STATUS_191_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_192_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_192_STATUS_192_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_193_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_193_STATUS_193_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_194_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_194_STATUS_194_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_195_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_195_STATUS_195_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_196_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_196_STATUS_196_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_197_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_197_STATUS_197_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_198_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_198_STATUS_198_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_199_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_199_STATUS_199_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_200_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_200_STATUS_200_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_201_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_201_STATUS_201_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_202_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_202_STATUS_202_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_203_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_203_STATUS_203_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_204_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_204_STATUS_204_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_205_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_205_STATUS_205_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_206_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_206_STATUS_206_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_207_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_207_STATUS_207_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_208_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_208_STATUS_208_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_209_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_209_STATUS_209_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_210_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_210_STATUS_210_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_211_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_211_STATUS_211_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_212_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_212_STATUS_212_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_213_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_213_STATUS_213_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_214_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_214_STATUS_214_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_215_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_215_STATUS_215_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_216_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_216_STATUS_216_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_217_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_217_STATUS_217_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_218_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_218_STATUS_218_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_219_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_219_STATUS_219_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_220_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_220_STATUS_220_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_221_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_221_STATUS_221_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_222_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_222_STATUS_222_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_223_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_223_STATUS_223_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_224_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_224_STATUS_224_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_225_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_225_STATUS_225_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_226_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_226_STATUS_226_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_227_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_227_STATUS_227_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_228_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_228_STATUS_228_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_229_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_229_STATUS_229_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_230_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_230_STATUS_230_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_231_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_231_STATUS_231_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_232_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_232_STATUS_232_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_233_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_233_STATUS_233_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_234_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_234_STATUS_234_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_235_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_235_STATUS_235_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_236_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_236_STATUS_236_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_237_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_237_STATUS_237_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_238_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_238_STATUS_238_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_239_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_239_STATUS_239_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_240_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_240_STATUS_240_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_241_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_241_STATUS_241_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_242_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_242_STATUS_242_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_243_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_243_STATUS_243_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_244_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_244_STATUS_244_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_245_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_245_STATUS_245_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_246_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_246_STATUS_246_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_247_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_247_STATUS_247_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_248_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_248_STATUS_248_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_249_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_249_STATUS_249_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_250_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_250_STATUS_250_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_251_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_251_STATUS_251_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_252_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_252_STATUS_252_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_253_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_253_STATUS_253_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_254_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_254_STATUS_254_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_255_RESVAL = 1'h 0; + parameter logic [0:0] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_255_STATUS_255_RESVAL = 1'h 0; // Register index typedef enum int { @@ -645,6 +1797,198 @@ package cachepool_peripheral_reg_pkg; CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61, CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62, CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_64, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_65, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_66, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_67, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_68, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_69, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_70, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_71, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_72, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_73, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_74, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_75, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_76, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_77, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_78, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_79, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_80, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_81, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_82, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_83, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_84, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_85, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_86, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_87, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_88, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_89, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_90, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_91, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_92, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_93, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_94, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_95, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_96, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_97, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_98, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_99, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_100, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_101, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_102, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_103, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_104, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_105, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_106, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_107, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_108, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_109, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_110, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_111, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_112, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_113, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_114, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_115, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_116, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_117, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_118, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_119, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_120, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_121, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_122, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_123, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_124, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_125, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_126, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_127, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_128, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_129, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_130, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_131, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_132, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_133, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_134, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_135, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_136, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_137, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_138, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_139, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_140, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_141, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_142, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_143, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_144, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_145, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_146, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_147, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_148, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_149, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_150, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_151, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_152, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_153, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_154, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_155, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_156, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_157, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_158, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_159, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_160, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_161, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_162, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_163, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_164, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_165, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_166, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_167, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_168, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_169, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_170, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_171, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_172, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_173, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_174, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_175, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_176, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_177, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_178, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_179, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_180, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_181, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_182, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_183, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_184, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_185, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_186, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_187, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_188, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_189, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_190, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_191, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_192, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_193, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_194, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_195, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_196, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_197, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_198, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_199, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_200, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_201, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_202, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_203, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_204, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_205, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_206, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_207, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_208, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_209, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_210, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_211, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_212, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_213, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_214, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_215, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_216, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_217, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_218, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_219, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_220, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_221, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_222, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_223, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_224, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_225, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_226, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_227, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_228, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_229, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_230, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_231, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_232, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_233, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_234, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_235, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_236, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_237, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_238, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_239, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_240, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_241, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_242, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_243, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_244, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_245, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_246, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_247, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_248, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_249, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_250, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_251, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_252, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_253, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_254, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_255, CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0, CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1, CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2, @@ -709,6 +2053,198 @@ package cachepool_peripheral_reg_pkg; CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61, CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62, CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_64, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_65, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_66, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_67, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_68, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_69, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_70, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_71, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_72, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_73, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_74, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_75, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_76, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_77, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_78, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_79, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_80, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_81, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_82, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_83, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_84, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_85, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_86, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_87, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_88, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_89, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_90, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_91, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_92, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_93, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_94, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_95, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_96, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_97, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_98, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_99, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_100, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_101, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_102, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_103, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_104, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_105, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_106, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_107, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_108, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_109, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_110, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_111, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_112, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_113, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_114, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_115, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_116, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_117, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_118, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_119, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_120, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_121, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_122, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_123, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_124, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_125, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_126, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_127, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_128, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_129, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_130, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_131, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_132, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_133, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_134, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_135, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_136, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_137, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_138, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_139, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_140, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_141, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_142, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_143, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_144, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_145, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_146, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_147, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_148, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_149, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_150, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_151, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_152, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_153, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_154, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_155, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_156, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_157, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_158, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_159, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_160, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_161, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_162, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_163, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_164, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_165, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_166, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_167, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_168, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_169, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_170, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_171, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_172, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_173, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_174, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_175, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_176, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_177, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_178, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_179, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_180, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_181, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_182, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_183, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_184, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_185, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_186, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_187, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_188, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_189, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_190, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_191, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_192, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_193, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_194, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_195, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_196, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_197, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_198, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_199, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_200, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_201, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_202, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_203, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_204, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_205, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_206, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_207, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_208, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_209, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_210, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_211, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_212, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_213, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_214, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_215, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_216, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_217, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_218, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_219, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_220, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_221, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_222, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_223, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_224, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_225, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_226, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_227, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_228, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_229, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_230, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_231, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_232, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_233, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_234, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_235, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_236, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_237, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_238, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_239, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_240, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_241, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_242, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_243, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_244, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_245, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_246, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_247, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_248, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_249, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_250, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_251, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_252, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_253, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_254, + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_255, CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0, CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1, CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2, @@ -773,6 +2309,198 @@ package cachepool_peripheral_reg_pkg; CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61, CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62, CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_64, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_65, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_66, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_67, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_68, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_69, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_70, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_71, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_72, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_73, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_74, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_75, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_76, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_77, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_78, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_79, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_80, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_81, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_82, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_83, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_84, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_85, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_86, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_87, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_88, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_89, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_90, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_91, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_92, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_93, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_94, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_95, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_96, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_97, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_98, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_99, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_100, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_101, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_102, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_103, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_104, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_105, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_106, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_107, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_108, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_109, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_110, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_111, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_112, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_113, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_114, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_115, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_116, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_117, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_118, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_119, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_120, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_121, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_122, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_123, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_124, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_125, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_126, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_127, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_128, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_129, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_130, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_131, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_132, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_133, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_134, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_135, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_136, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_137, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_138, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_139, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_140, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_141, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_142, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_143, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_144, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_145, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_146, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_147, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_148, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_149, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_150, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_151, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_152, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_153, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_154, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_155, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_156, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_157, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_158, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_159, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_160, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_161, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_162, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_163, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_164, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_165, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_166, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_167, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_168, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_169, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_170, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_171, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_172, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_173, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_174, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_175, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_176, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_177, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_178, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_179, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_180, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_181, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_182, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_183, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_184, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_185, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_186, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_187, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_188, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_189, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_190, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_191, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_192, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_193, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_194, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_195, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_196, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_197, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_198, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_199, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_200, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_201, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_202, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_203, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_204, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_205, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_206, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_207, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_208, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_209, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_210, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_211, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_212, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_213, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_214, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_215, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_216, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_217, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_218, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_219, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_220, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_221, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_222, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_223, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_224, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_225, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_226, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_227, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_228, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_229, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_230, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_231, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_232, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_233, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_234, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_235, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_236, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_237, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_238, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_239, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_240, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_241, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_242, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_243, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_244, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_245, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_246, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_247, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_248, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_249, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_250, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_251, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_252, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_253, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_254, + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_255, CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0, CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1, CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2, @@ -836,284 +2564,1244 @@ package cachepool_peripheral_reg_pkg; CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60, CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61, CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62, - CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63 + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_64, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_65, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_66, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_67, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_68, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_69, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_70, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_71, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_72, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_73, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_74, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_75, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_76, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_77, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_78, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_79, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_80, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_81, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_82, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_83, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_84, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_85, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_86, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_87, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_88, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_89, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_90, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_91, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_92, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_93, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_94, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_95, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_96, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_97, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_98, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_99, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_100, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_101, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_102, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_103, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_104, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_105, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_106, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_107, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_108, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_109, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_110, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_111, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_112, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_113, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_114, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_115, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_116, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_117, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_118, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_119, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_120, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_121, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_122, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_123, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_124, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_125, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_126, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_127, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_128, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_129, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_130, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_131, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_132, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_133, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_134, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_135, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_136, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_137, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_138, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_139, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_140, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_141, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_142, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_143, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_144, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_145, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_146, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_147, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_148, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_149, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_150, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_151, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_152, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_153, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_154, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_155, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_156, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_157, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_158, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_159, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_160, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_161, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_162, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_163, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_164, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_165, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_166, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_167, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_168, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_169, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_170, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_171, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_172, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_173, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_174, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_175, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_176, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_177, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_178, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_179, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_180, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_181, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_182, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_183, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_184, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_185, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_186, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_187, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_188, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_189, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_190, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_191, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_192, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_193, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_194, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_195, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_196, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_197, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_198, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_199, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_200, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_201, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_202, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_203, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_204, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_205, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_206, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_207, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_208, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_209, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_210, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_211, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_212, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_213, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_214, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_215, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_216, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_217, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_218, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_219, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_220, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_221, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_222, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_223, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_224, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_225, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_226, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_227, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_228, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_229, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_230, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_231, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_232, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_233, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_234, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_235, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_236, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_237, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_238, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_239, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_240, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_241, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_242, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_243, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_244, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_245, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_246, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_247, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_248, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_249, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_250, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_251, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_252, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_253, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_254, + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_255 } cachepool_peripheral_id_e; // Register width information to check illegal writes - parameter logic [3:0] CACHEPOOL_PERIPHERAL_PERMIT [273] = '{ - 4'b 1111, // index[ 0] CACHEPOOL_PERIPHERAL_HW_BARRIER - 4'b 0001, // index[ 1] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE - 4'b 0001, // index[ 2] CACHEPOOL_PERIPHERAL_SPATZ_STATUS - 4'b 1111, // index[ 3] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE - 4'b 1111, // index[ 4] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL - 4'b 0001, // index[ 5] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT - 4'b 0011, // index[ 6] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM - 4'b 0001, // index[ 7] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN - 4'b 1111, // index[ 8] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0 - 4'b 1111, // index[ 9] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1 - 4'b 0001, // index[ 10] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT - 4'b 0001, // index[ 11] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT - 4'b 0001, // index[ 12] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS - 4'b 0001, // index[ 13] CACHEPOOL_PERIPHERAL_L1D_PRIVATE - 4'b 1111, // index[ 14] CACHEPOOL_PERIPHERAL_L1D_ADDR - 4'b 0001, // index[ 15] CACHEPOOL_PERIPHERAL_XBAR_OFFSET - 4'b 0001, // index[ 16] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT - 4'b 0001, // index[ 17] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0 - 4'b 0001, // index[ 18] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1 - 4'b 0001, // index[ 19] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2 - 4'b 0001, // index[ 20] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3 - 4'b 0001, // index[ 21] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4 - 4'b 0001, // index[ 22] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5 - 4'b 0001, // index[ 23] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6 - 4'b 0001, // index[ 24] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7 - 4'b 0001, // index[ 25] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8 - 4'b 0001, // index[ 26] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9 - 4'b 0001, // index[ 27] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10 - 4'b 0001, // index[ 28] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11 - 4'b 0001, // index[ 29] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12 - 4'b 0001, // index[ 30] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13 - 4'b 0001, // index[ 31] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14 - 4'b 0001, // index[ 32] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15 - 4'b 0001, // index[ 33] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16 - 4'b 0001, // index[ 34] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17 - 4'b 0001, // index[ 35] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18 - 4'b 0001, // index[ 36] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19 - 4'b 0001, // index[ 37] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20 - 4'b 0001, // index[ 38] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21 - 4'b 0001, // index[ 39] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22 - 4'b 0001, // index[ 40] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23 - 4'b 0001, // index[ 41] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24 - 4'b 0001, // index[ 42] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25 - 4'b 0001, // index[ 43] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26 - 4'b 0001, // index[ 44] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27 - 4'b 0001, // index[ 45] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28 - 4'b 0001, // index[ 46] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29 - 4'b 0001, // index[ 47] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30 - 4'b 0001, // index[ 48] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31 - 4'b 0001, // index[ 49] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32 - 4'b 0001, // index[ 50] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33 - 4'b 0001, // index[ 51] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34 - 4'b 0001, // index[ 52] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35 - 4'b 0001, // index[ 53] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36 - 4'b 0001, // index[ 54] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37 - 4'b 0001, // index[ 55] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38 - 4'b 0001, // index[ 56] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39 - 4'b 0001, // index[ 57] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40 - 4'b 0001, // index[ 58] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41 - 4'b 0001, // index[ 59] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42 - 4'b 0001, // index[ 60] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43 - 4'b 0001, // index[ 61] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44 - 4'b 0001, // index[ 62] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45 - 4'b 0001, // index[ 63] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46 - 4'b 0001, // index[ 64] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47 - 4'b 0001, // index[ 65] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48 - 4'b 0001, // index[ 66] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49 - 4'b 0001, // index[ 67] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50 - 4'b 0001, // index[ 68] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51 - 4'b 0001, // index[ 69] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52 - 4'b 0001, // index[ 70] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53 - 4'b 0001, // index[ 71] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54 - 4'b 0001, // index[ 72] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55 - 4'b 0001, // index[ 73] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56 - 4'b 0001, // index[ 74] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57 - 4'b 0001, // index[ 75] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58 - 4'b 0001, // index[ 76] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59 - 4'b 0001, // index[ 77] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60 - 4'b 0001, // index[ 78] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61 - 4'b 0001, // index[ 79] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62 - 4'b 0001, // index[ 80] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63 - 4'b 1111, // index[ 81] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0 - 4'b 1111, // index[ 82] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1 - 4'b 1111, // index[ 83] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2 - 4'b 1111, // index[ 84] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3 - 4'b 1111, // index[ 85] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4 - 4'b 1111, // index[ 86] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5 - 4'b 1111, // index[ 87] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6 - 4'b 1111, // index[ 88] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7 - 4'b 1111, // index[ 89] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8 - 4'b 1111, // index[ 90] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9 - 4'b 1111, // index[ 91] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10 - 4'b 1111, // index[ 92] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11 - 4'b 1111, // index[ 93] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12 - 4'b 1111, // index[ 94] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13 - 4'b 1111, // index[ 95] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14 - 4'b 1111, // index[ 96] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15 - 4'b 1111, // index[ 97] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16 - 4'b 1111, // index[ 98] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17 - 4'b 1111, // index[ 99] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18 - 4'b 1111, // index[100] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19 - 4'b 1111, // index[101] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20 - 4'b 1111, // index[102] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21 - 4'b 1111, // index[103] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22 - 4'b 1111, // index[104] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23 - 4'b 1111, // index[105] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24 - 4'b 1111, // index[106] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25 - 4'b 1111, // index[107] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26 - 4'b 1111, // index[108] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27 - 4'b 1111, // index[109] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28 - 4'b 1111, // index[110] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29 - 4'b 1111, // index[111] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30 - 4'b 1111, // index[112] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31 - 4'b 1111, // index[113] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32 - 4'b 1111, // index[114] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33 - 4'b 1111, // index[115] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34 - 4'b 1111, // index[116] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35 - 4'b 1111, // index[117] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36 - 4'b 1111, // index[118] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37 - 4'b 1111, // index[119] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38 - 4'b 1111, // index[120] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39 - 4'b 1111, // index[121] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40 - 4'b 1111, // index[122] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41 - 4'b 1111, // index[123] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42 - 4'b 1111, // index[124] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43 - 4'b 1111, // index[125] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44 - 4'b 1111, // index[126] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45 - 4'b 1111, // index[127] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46 - 4'b 1111, // index[128] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47 - 4'b 1111, // index[129] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48 - 4'b 1111, // index[130] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49 - 4'b 1111, // index[131] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50 - 4'b 1111, // index[132] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51 - 4'b 1111, // index[133] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52 - 4'b 1111, // index[134] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53 - 4'b 1111, // index[135] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54 - 4'b 1111, // index[136] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55 - 4'b 1111, // index[137] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56 - 4'b 1111, // index[138] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57 - 4'b 1111, // index[139] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58 - 4'b 1111, // index[140] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59 - 4'b 1111, // index[141] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60 - 4'b 1111, // index[142] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61 - 4'b 1111, // index[143] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62 - 4'b 1111, // index[144] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63 - 4'b 0001, // index[145] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0 - 4'b 0001, // index[146] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1 - 4'b 0001, // index[147] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2 - 4'b 0001, // index[148] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3 - 4'b 0001, // index[149] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4 - 4'b 0001, // index[150] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5 - 4'b 0001, // index[151] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6 - 4'b 0001, // index[152] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7 - 4'b 0001, // index[153] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8 - 4'b 0001, // index[154] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9 - 4'b 0001, // index[155] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10 - 4'b 0001, // index[156] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11 - 4'b 0001, // index[157] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12 - 4'b 0001, // index[158] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13 - 4'b 0001, // index[159] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14 - 4'b 0001, // index[160] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15 - 4'b 0001, // index[161] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16 - 4'b 0001, // index[162] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17 - 4'b 0001, // index[163] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18 - 4'b 0001, // index[164] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19 - 4'b 0001, // index[165] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20 - 4'b 0001, // index[166] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21 - 4'b 0001, // index[167] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22 - 4'b 0001, // index[168] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23 - 4'b 0001, // index[169] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24 - 4'b 0001, // index[170] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25 - 4'b 0001, // index[171] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26 - 4'b 0001, // index[172] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27 - 4'b 0001, // index[173] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28 - 4'b 0001, // index[174] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29 - 4'b 0001, // index[175] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30 - 4'b 0001, // index[176] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31 - 4'b 0001, // index[177] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32 - 4'b 0001, // index[178] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33 - 4'b 0001, // index[179] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34 - 4'b 0001, // index[180] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35 - 4'b 0001, // index[181] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36 - 4'b 0001, // index[182] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37 - 4'b 0001, // index[183] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38 - 4'b 0001, // index[184] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39 - 4'b 0001, // index[185] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40 - 4'b 0001, // index[186] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41 - 4'b 0001, // index[187] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42 - 4'b 0001, // index[188] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43 - 4'b 0001, // index[189] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44 - 4'b 0001, // index[190] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45 - 4'b 0001, // index[191] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46 - 4'b 0001, // index[192] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47 - 4'b 0001, // index[193] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48 - 4'b 0001, // index[194] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49 - 4'b 0001, // index[195] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50 - 4'b 0001, // index[196] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51 - 4'b 0001, // index[197] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52 - 4'b 0001, // index[198] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53 - 4'b 0001, // index[199] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54 - 4'b 0001, // index[200] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55 - 4'b 0001, // index[201] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56 - 4'b 0001, // index[202] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57 - 4'b 0001, // index[203] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58 - 4'b 0001, // index[204] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59 - 4'b 0001, // index[205] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60 - 4'b 0001, // index[206] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61 - 4'b 0001, // index[207] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62 - 4'b 0001, // index[208] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63 - 4'b 0001, // index[209] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0 - 4'b 0001, // index[210] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1 - 4'b 0001, // index[211] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2 - 4'b 0001, // index[212] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3 - 4'b 0001, // index[213] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4 - 4'b 0001, // index[214] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5 - 4'b 0001, // index[215] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6 - 4'b 0001, // index[216] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7 - 4'b 0001, // index[217] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8 - 4'b 0001, // index[218] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9 - 4'b 0001, // index[219] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10 - 4'b 0001, // index[220] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11 - 4'b 0001, // index[221] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12 - 4'b 0001, // index[222] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13 - 4'b 0001, // index[223] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14 - 4'b 0001, // index[224] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15 - 4'b 0001, // index[225] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16 - 4'b 0001, // index[226] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17 - 4'b 0001, // index[227] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18 - 4'b 0001, // index[228] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19 - 4'b 0001, // index[229] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20 - 4'b 0001, // index[230] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21 - 4'b 0001, // index[231] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22 - 4'b 0001, // index[232] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23 - 4'b 0001, // index[233] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24 - 4'b 0001, // index[234] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25 - 4'b 0001, // index[235] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26 - 4'b 0001, // index[236] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27 - 4'b 0001, // index[237] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28 - 4'b 0001, // index[238] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29 - 4'b 0001, // index[239] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30 - 4'b 0001, // index[240] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31 - 4'b 0001, // index[241] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32 - 4'b 0001, // index[242] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33 - 4'b 0001, // index[243] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34 - 4'b 0001, // index[244] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35 - 4'b 0001, // index[245] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36 - 4'b 0001, // index[246] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37 - 4'b 0001, // index[247] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38 - 4'b 0001, // index[248] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39 - 4'b 0001, // index[249] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40 - 4'b 0001, // index[250] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41 - 4'b 0001, // index[251] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42 - 4'b 0001, // index[252] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43 - 4'b 0001, // index[253] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44 - 4'b 0001, // index[254] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45 - 4'b 0001, // index[255] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46 - 4'b 0001, // index[256] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47 - 4'b 0001, // index[257] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48 - 4'b 0001, // index[258] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49 - 4'b 0001, // index[259] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50 - 4'b 0001, // index[260] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51 - 4'b 0001, // index[261] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52 - 4'b 0001, // index[262] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53 - 4'b 0001, // index[263] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54 - 4'b 0001, // index[264] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55 - 4'b 0001, // index[265] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56 - 4'b 0001, // index[266] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57 - 4'b 0001, // index[267] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58 - 4'b 0001, // index[268] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59 - 4'b 0001, // index[269] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60 - 4'b 0001, // index[270] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61 - 4'b 0001, // index[271] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62 - 4'b 0001 // index[272] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63 + parameter logic [3:0] CACHEPOOL_PERIPHERAL_PERMIT [1041] = '{ + 4'b 1111, // index[ 0] CACHEPOOL_PERIPHERAL_HW_BARRIER + 4'b 0001, // index[ 1] CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE + 4'b 0001, // index[ 2] CACHEPOOL_PERIPHERAL_SPATZ_STATUS + 4'b 1111, // index[ 3] CACHEPOOL_PERIPHERAL_SPATZ_CYCLE + 4'b 1111, // index[ 4] CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL + 4'b 0001, // index[ 5] CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT + 4'b 0011, // index[ 6] CACHEPOOL_PERIPHERAL_CFG_L1D_SPM + 4'b 0001, // index[ 7] CACHEPOOL_PERIPHERAL_CFG_L1D_INSN + 4'b 1111, // index[ 8] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0 + 4'b 1111, // index[ 9] CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1 + 4'b 0001, // index[ 10] CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT + 4'b 0001, // index[ 11] CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT + 4'b 0001, // index[ 12] CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS + 4'b 0001, // index[ 13] CACHEPOOL_PERIPHERAL_L1D_PRIVATE + 4'b 1111, // index[ 14] CACHEPOOL_PERIPHERAL_L1D_ADDR + 4'b 0001, // index[ 15] CACHEPOOL_PERIPHERAL_XBAR_OFFSET + 4'b 0001, // index[ 16] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT + 4'b 0001, // index[ 17] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0 + 4'b 0001, // index[ 18] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1 + 4'b 0001, // index[ 19] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2 + 4'b 0001, // index[ 20] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3 + 4'b 0001, // index[ 21] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4 + 4'b 0001, // index[ 22] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5 + 4'b 0001, // index[ 23] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6 + 4'b 0001, // index[ 24] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7 + 4'b 0001, // index[ 25] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8 + 4'b 0001, // index[ 26] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9 + 4'b 0001, // index[ 27] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10 + 4'b 0001, // index[ 28] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11 + 4'b 0001, // index[ 29] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12 + 4'b 0001, // index[ 30] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13 + 4'b 0001, // index[ 31] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14 + 4'b 0001, // index[ 32] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15 + 4'b 0001, // index[ 33] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16 + 4'b 0001, // index[ 34] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17 + 4'b 0001, // index[ 35] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18 + 4'b 0001, // index[ 36] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19 + 4'b 0001, // index[ 37] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20 + 4'b 0001, // index[ 38] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21 + 4'b 0001, // index[ 39] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22 + 4'b 0001, // index[ 40] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23 + 4'b 0001, // index[ 41] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24 + 4'b 0001, // index[ 42] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25 + 4'b 0001, // index[ 43] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26 + 4'b 0001, // index[ 44] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27 + 4'b 0001, // index[ 45] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28 + 4'b 0001, // index[ 46] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29 + 4'b 0001, // index[ 47] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30 + 4'b 0001, // index[ 48] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31 + 4'b 0001, // index[ 49] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32 + 4'b 0001, // index[ 50] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33 + 4'b 0001, // index[ 51] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34 + 4'b 0001, // index[ 52] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35 + 4'b 0001, // index[ 53] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36 + 4'b 0001, // index[ 54] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37 + 4'b 0001, // index[ 55] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38 + 4'b 0001, // index[ 56] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39 + 4'b 0001, // index[ 57] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40 + 4'b 0001, // index[ 58] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41 + 4'b 0001, // index[ 59] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42 + 4'b 0001, // index[ 60] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43 + 4'b 0001, // index[ 61] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44 + 4'b 0001, // index[ 62] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45 + 4'b 0001, // index[ 63] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46 + 4'b 0001, // index[ 64] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47 + 4'b 0001, // index[ 65] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48 + 4'b 0001, // index[ 66] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49 + 4'b 0001, // index[ 67] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50 + 4'b 0001, // index[ 68] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51 + 4'b 0001, // index[ 69] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52 + 4'b 0001, // index[ 70] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53 + 4'b 0001, // index[ 71] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54 + 4'b 0001, // index[ 72] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55 + 4'b 0001, // index[ 73] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56 + 4'b 0001, // index[ 74] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57 + 4'b 0001, // index[ 75] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58 + 4'b 0001, // index[ 76] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59 + 4'b 0001, // index[ 77] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60 + 4'b 0001, // index[ 78] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61 + 4'b 0001, // index[ 79] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62 + 4'b 0001, // index[ 80] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63 + 4'b 0001, // index[ 81] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_64 + 4'b 0001, // index[ 82] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_65 + 4'b 0001, // index[ 83] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_66 + 4'b 0001, // index[ 84] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_67 + 4'b 0001, // index[ 85] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_68 + 4'b 0001, // index[ 86] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_69 + 4'b 0001, // index[ 87] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_70 + 4'b 0001, // index[ 88] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_71 + 4'b 0001, // index[ 89] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_72 + 4'b 0001, // index[ 90] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_73 + 4'b 0001, // index[ 91] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_74 + 4'b 0001, // index[ 92] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_75 + 4'b 0001, // index[ 93] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_76 + 4'b 0001, // index[ 94] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_77 + 4'b 0001, // index[ 95] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_78 + 4'b 0001, // index[ 96] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_79 + 4'b 0001, // index[ 97] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_80 + 4'b 0001, // index[ 98] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_81 + 4'b 0001, // index[ 99] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_82 + 4'b 0001, // index[ 100] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_83 + 4'b 0001, // index[ 101] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_84 + 4'b 0001, // index[ 102] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_85 + 4'b 0001, // index[ 103] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_86 + 4'b 0001, // index[ 104] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_87 + 4'b 0001, // index[ 105] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_88 + 4'b 0001, // index[ 106] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_89 + 4'b 0001, // index[ 107] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_90 + 4'b 0001, // index[ 108] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_91 + 4'b 0001, // index[ 109] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_92 + 4'b 0001, // index[ 110] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_93 + 4'b 0001, // index[ 111] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_94 + 4'b 0001, // index[ 112] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_95 + 4'b 0001, // index[ 113] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_96 + 4'b 0001, // index[ 114] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_97 + 4'b 0001, // index[ 115] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_98 + 4'b 0001, // index[ 116] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_99 + 4'b 0001, // index[ 117] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_100 + 4'b 0001, // index[ 118] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_101 + 4'b 0001, // index[ 119] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_102 + 4'b 0001, // index[ 120] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_103 + 4'b 0001, // index[ 121] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_104 + 4'b 0001, // index[ 122] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_105 + 4'b 0001, // index[ 123] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_106 + 4'b 0001, // index[ 124] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_107 + 4'b 0001, // index[ 125] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_108 + 4'b 0001, // index[ 126] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_109 + 4'b 0001, // index[ 127] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_110 + 4'b 0001, // index[ 128] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_111 + 4'b 0001, // index[ 129] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_112 + 4'b 0001, // index[ 130] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_113 + 4'b 0001, // index[ 131] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_114 + 4'b 0001, // index[ 132] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_115 + 4'b 0001, // index[ 133] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_116 + 4'b 0001, // index[ 134] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_117 + 4'b 0001, // index[ 135] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_118 + 4'b 0001, // index[ 136] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_119 + 4'b 0001, // index[ 137] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_120 + 4'b 0001, // index[ 138] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_121 + 4'b 0001, // index[ 139] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_122 + 4'b 0001, // index[ 140] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_123 + 4'b 0001, // index[ 141] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_124 + 4'b 0001, // index[ 142] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_125 + 4'b 0001, // index[ 143] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_126 + 4'b 0001, // index[ 144] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_127 + 4'b 0001, // index[ 145] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_128 + 4'b 0001, // index[ 146] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_129 + 4'b 0001, // index[ 147] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_130 + 4'b 0001, // index[ 148] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_131 + 4'b 0001, // index[ 149] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_132 + 4'b 0001, // index[ 150] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_133 + 4'b 0001, // index[ 151] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_134 + 4'b 0001, // index[ 152] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_135 + 4'b 0001, // index[ 153] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_136 + 4'b 0001, // index[ 154] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_137 + 4'b 0001, // index[ 155] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_138 + 4'b 0001, // index[ 156] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_139 + 4'b 0001, // index[ 157] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_140 + 4'b 0001, // index[ 158] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_141 + 4'b 0001, // index[ 159] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_142 + 4'b 0001, // index[ 160] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_143 + 4'b 0001, // index[ 161] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_144 + 4'b 0001, // index[ 162] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_145 + 4'b 0001, // index[ 163] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_146 + 4'b 0001, // index[ 164] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_147 + 4'b 0001, // index[ 165] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_148 + 4'b 0001, // index[ 166] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_149 + 4'b 0001, // index[ 167] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_150 + 4'b 0001, // index[ 168] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_151 + 4'b 0001, // index[ 169] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_152 + 4'b 0001, // index[ 170] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_153 + 4'b 0001, // index[ 171] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_154 + 4'b 0001, // index[ 172] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_155 + 4'b 0001, // index[ 173] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_156 + 4'b 0001, // index[ 174] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_157 + 4'b 0001, // index[ 175] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_158 + 4'b 0001, // index[ 176] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_159 + 4'b 0001, // index[ 177] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_160 + 4'b 0001, // index[ 178] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_161 + 4'b 0001, // index[ 179] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_162 + 4'b 0001, // index[ 180] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_163 + 4'b 0001, // index[ 181] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_164 + 4'b 0001, // index[ 182] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_165 + 4'b 0001, // index[ 183] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_166 + 4'b 0001, // index[ 184] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_167 + 4'b 0001, // index[ 185] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_168 + 4'b 0001, // index[ 186] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_169 + 4'b 0001, // index[ 187] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_170 + 4'b 0001, // index[ 188] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_171 + 4'b 0001, // index[ 189] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_172 + 4'b 0001, // index[ 190] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_173 + 4'b 0001, // index[ 191] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_174 + 4'b 0001, // index[ 192] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_175 + 4'b 0001, // index[ 193] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_176 + 4'b 0001, // index[ 194] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_177 + 4'b 0001, // index[ 195] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_178 + 4'b 0001, // index[ 196] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_179 + 4'b 0001, // index[ 197] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_180 + 4'b 0001, // index[ 198] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_181 + 4'b 0001, // index[ 199] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_182 + 4'b 0001, // index[ 200] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_183 + 4'b 0001, // index[ 201] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_184 + 4'b 0001, // index[ 202] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_185 + 4'b 0001, // index[ 203] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_186 + 4'b 0001, // index[ 204] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_187 + 4'b 0001, // index[ 205] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_188 + 4'b 0001, // index[ 206] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_189 + 4'b 0001, // index[ 207] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_190 + 4'b 0001, // index[ 208] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_191 + 4'b 0001, // index[ 209] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_192 + 4'b 0001, // index[ 210] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_193 + 4'b 0001, // index[ 211] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_194 + 4'b 0001, // index[ 212] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_195 + 4'b 0001, // index[ 213] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_196 + 4'b 0001, // index[ 214] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_197 + 4'b 0001, // index[ 215] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_198 + 4'b 0001, // index[ 216] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_199 + 4'b 0001, // index[ 217] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_200 + 4'b 0001, // index[ 218] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_201 + 4'b 0001, // index[ 219] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_202 + 4'b 0001, // index[ 220] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_203 + 4'b 0001, // index[ 221] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_204 + 4'b 0001, // index[ 222] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_205 + 4'b 0001, // index[ 223] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_206 + 4'b 0001, // index[ 224] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_207 + 4'b 0001, // index[ 225] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_208 + 4'b 0001, // index[ 226] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_209 + 4'b 0001, // index[ 227] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_210 + 4'b 0001, // index[ 228] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_211 + 4'b 0001, // index[ 229] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_212 + 4'b 0001, // index[ 230] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_213 + 4'b 0001, // index[ 231] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_214 + 4'b 0001, // index[ 232] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_215 + 4'b 0001, // index[ 233] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_216 + 4'b 0001, // index[ 234] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_217 + 4'b 0001, // index[ 235] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_218 + 4'b 0001, // index[ 236] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_219 + 4'b 0001, // index[ 237] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_220 + 4'b 0001, // index[ 238] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_221 + 4'b 0001, // index[ 239] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_222 + 4'b 0001, // index[ 240] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_223 + 4'b 0001, // index[ 241] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_224 + 4'b 0001, // index[ 242] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_225 + 4'b 0001, // index[ 243] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_226 + 4'b 0001, // index[ 244] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_227 + 4'b 0001, // index[ 245] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_228 + 4'b 0001, // index[ 246] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_229 + 4'b 0001, // index[ 247] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_230 + 4'b 0001, // index[ 248] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_231 + 4'b 0001, // index[ 249] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_232 + 4'b 0001, // index[ 250] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_233 + 4'b 0001, // index[ 251] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_234 + 4'b 0001, // index[ 252] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_235 + 4'b 0001, // index[ 253] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_236 + 4'b 0001, // index[ 254] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_237 + 4'b 0001, // index[ 255] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_238 + 4'b 0001, // index[ 256] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_239 + 4'b 0001, // index[ 257] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_240 + 4'b 0001, // index[ 258] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_241 + 4'b 0001, // index[ 259] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_242 + 4'b 0001, // index[ 260] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_243 + 4'b 0001, // index[ 261] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_244 + 4'b 0001, // index[ 262] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_245 + 4'b 0001, // index[ 263] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_246 + 4'b 0001, // index[ 264] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_247 + 4'b 0001, // index[ 265] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_248 + 4'b 0001, // index[ 266] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_249 + 4'b 0001, // index[ 267] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_250 + 4'b 0001, // index[ 268] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_251 + 4'b 0001, // index[ 269] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_252 + 4'b 0001, // index[ 270] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_253 + 4'b 0001, // index[ 271] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_254 + 4'b 0001, // index[ 272] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_255 + 4'b 1111, // index[ 273] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0 + 4'b 1111, // index[ 274] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1 + 4'b 1111, // index[ 275] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2 + 4'b 1111, // index[ 276] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3 + 4'b 1111, // index[ 277] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4 + 4'b 1111, // index[ 278] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5 + 4'b 1111, // index[ 279] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6 + 4'b 1111, // index[ 280] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7 + 4'b 1111, // index[ 281] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8 + 4'b 1111, // index[ 282] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9 + 4'b 1111, // index[ 283] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10 + 4'b 1111, // index[ 284] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11 + 4'b 1111, // index[ 285] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12 + 4'b 1111, // index[ 286] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13 + 4'b 1111, // index[ 287] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14 + 4'b 1111, // index[ 288] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15 + 4'b 1111, // index[ 289] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16 + 4'b 1111, // index[ 290] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17 + 4'b 1111, // index[ 291] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18 + 4'b 1111, // index[ 292] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19 + 4'b 1111, // index[ 293] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20 + 4'b 1111, // index[ 294] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21 + 4'b 1111, // index[ 295] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22 + 4'b 1111, // index[ 296] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23 + 4'b 1111, // index[ 297] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24 + 4'b 1111, // index[ 298] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25 + 4'b 1111, // index[ 299] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26 + 4'b 1111, // index[ 300] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27 + 4'b 1111, // index[ 301] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28 + 4'b 1111, // index[ 302] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29 + 4'b 1111, // index[ 303] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30 + 4'b 1111, // index[ 304] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31 + 4'b 1111, // index[ 305] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32 + 4'b 1111, // index[ 306] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33 + 4'b 1111, // index[ 307] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34 + 4'b 1111, // index[ 308] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35 + 4'b 1111, // index[ 309] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36 + 4'b 1111, // index[ 310] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37 + 4'b 1111, // index[ 311] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38 + 4'b 1111, // index[ 312] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39 + 4'b 1111, // index[ 313] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40 + 4'b 1111, // index[ 314] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41 + 4'b 1111, // index[ 315] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42 + 4'b 1111, // index[ 316] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43 + 4'b 1111, // index[ 317] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44 + 4'b 1111, // index[ 318] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45 + 4'b 1111, // index[ 319] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46 + 4'b 1111, // index[ 320] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47 + 4'b 1111, // index[ 321] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48 + 4'b 1111, // index[ 322] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49 + 4'b 1111, // index[ 323] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50 + 4'b 1111, // index[ 324] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51 + 4'b 1111, // index[ 325] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52 + 4'b 1111, // index[ 326] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53 + 4'b 1111, // index[ 327] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54 + 4'b 1111, // index[ 328] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55 + 4'b 1111, // index[ 329] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56 + 4'b 1111, // index[ 330] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57 + 4'b 1111, // index[ 331] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58 + 4'b 1111, // index[ 332] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59 + 4'b 1111, // index[ 333] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60 + 4'b 1111, // index[ 334] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61 + 4'b 1111, // index[ 335] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62 + 4'b 1111, // index[ 336] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63 + 4'b 1111, // index[ 337] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_64 + 4'b 1111, // index[ 338] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_65 + 4'b 1111, // index[ 339] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_66 + 4'b 1111, // index[ 340] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_67 + 4'b 1111, // index[ 341] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_68 + 4'b 1111, // index[ 342] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_69 + 4'b 1111, // index[ 343] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_70 + 4'b 1111, // index[ 344] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_71 + 4'b 1111, // index[ 345] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_72 + 4'b 1111, // index[ 346] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_73 + 4'b 1111, // index[ 347] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_74 + 4'b 1111, // index[ 348] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_75 + 4'b 1111, // index[ 349] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_76 + 4'b 1111, // index[ 350] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_77 + 4'b 1111, // index[ 351] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_78 + 4'b 1111, // index[ 352] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_79 + 4'b 1111, // index[ 353] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_80 + 4'b 1111, // index[ 354] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_81 + 4'b 1111, // index[ 355] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_82 + 4'b 1111, // index[ 356] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_83 + 4'b 1111, // index[ 357] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_84 + 4'b 1111, // index[ 358] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_85 + 4'b 1111, // index[ 359] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_86 + 4'b 1111, // index[ 360] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_87 + 4'b 1111, // index[ 361] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_88 + 4'b 1111, // index[ 362] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_89 + 4'b 1111, // index[ 363] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_90 + 4'b 1111, // index[ 364] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_91 + 4'b 1111, // index[ 365] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_92 + 4'b 1111, // index[ 366] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_93 + 4'b 1111, // index[ 367] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_94 + 4'b 1111, // index[ 368] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_95 + 4'b 1111, // index[ 369] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_96 + 4'b 1111, // index[ 370] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_97 + 4'b 1111, // index[ 371] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_98 + 4'b 1111, // index[ 372] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_99 + 4'b 1111, // index[ 373] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_100 + 4'b 1111, // index[ 374] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_101 + 4'b 1111, // index[ 375] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_102 + 4'b 1111, // index[ 376] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_103 + 4'b 1111, // index[ 377] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_104 + 4'b 1111, // index[ 378] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_105 + 4'b 1111, // index[ 379] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_106 + 4'b 1111, // index[ 380] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_107 + 4'b 1111, // index[ 381] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_108 + 4'b 1111, // index[ 382] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_109 + 4'b 1111, // index[ 383] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_110 + 4'b 1111, // index[ 384] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_111 + 4'b 1111, // index[ 385] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_112 + 4'b 1111, // index[ 386] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_113 + 4'b 1111, // index[ 387] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_114 + 4'b 1111, // index[ 388] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_115 + 4'b 1111, // index[ 389] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_116 + 4'b 1111, // index[ 390] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_117 + 4'b 1111, // index[ 391] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_118 + 4'b 1111, // index[ 392] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_119 + 4'b 1111, // index[ 393] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_120 + 4'b 1111, // index[ 394] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_121 + 4'b 1111, // index[ 395] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_122 + 4'b 1111, // index[ 396] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_123 + 4'b 1111, // index[ 397] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_124 + 4'b 1111, // index[ 398] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_125 + 4'b 1111, // index[ 399] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_126 + 4'b 1111, // index[ 400] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_127 + 4'b 1111, // index[ 401] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_128 + 4'b 1111, // index[ 402] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_129 + 4'b 1111, // index[ 403] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_130 + 4'b 1111, // index[ 404] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_131 + 4'b 1111, // index[ 405] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_132 + 4'b 1111, // index[ 406] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_133 + 4'b 1111, // index[ 407] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_134 + 4'b 1111, // index[ 408] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_135 + 4'b 1111, // index[ 409] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_136 + 4'b 1111, // index[ 410] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_137 + 4'b 1111, // index[ 411] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_138 + 4'b 1111, // index[ 412] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_139 + 4'b 1111, // index[ 413] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_140 + 4'b 1111, // index[ 414] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_141 + 4'b 1111, // index[ 415] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_142 + 4'b 1111, // index[ 416] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_143 + 4'b 1111, // index[ 417] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_144 + 4'b 1111, // index[ 418] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_145 + 4'b 1111, // index[ 419] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_146 + 4'b 1111, // index[ 420] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_147 + 4'b 1111, // index[ 421] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_148 + 4'b 1111, // index[ 422] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_149 + 4'b 1111, // index[ 423] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_150 + 4'b 1111, // index[ 424] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_151 + 4'b 1111, // index[ 425] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_152 + 4'b 1111, // index[ 426] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_153 + 4'b 1111, // index[ 427] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_154 + 4'b 1111, // index[ 428] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_155 + 4'b 1111, // index[ 429] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_156 + 4'b 1111, // index[ 430] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_157 + 4'b 1111, // index[ 431] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_158 + 4'b 1111, // index[ 432] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_159 + 4'b 1111, // index[ 433] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_160 + 4'b 1111, // index[ 434] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_161 + 4'b 1111, // index[ 435] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_162 + 4'b 1111, // index[ 436] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_163 + 4'b 1111, // index[ 437] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_164 + 4'b 1111, // index[ 438] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_165 + 4'b 1111, // index[ 439] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_166 + 4'b 1111, // index[ 440] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_167 + 4'b 1111, // index[ 441] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_168 + 4'b 1111, // index[ 442] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_169 + 4'b 1111, // index[ 443] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_170 + 4'b 1111, // index[ 444] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_171 + 4'b 1111, // index[ 445] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_172 + 4'b 1111, // index[ 446] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_173 + 4'b 1111, // index[ 447] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_174 + 4'b 1111, // index[ 448] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_175 + 4'b 1111, // index[ 449] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_176 + 4'b 1111, // index[ 450] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_177 + 4'b 1111, // index[ 451] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_178 + 4'b 1111, // index[ 452] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_179 + 4'b 1111, // index[ 453] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_180 + 4'b 1111, // index[ 454] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_181 + 4'b 1111, // index[ 455] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_182 + 4'b 1111, // index[ 456] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_183 + 4'b 1111, // index[ 457] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_184 + 4'b 1111, // index[ 458] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_185 + 4'b 1111, // index[ 459] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_186 + 4'b 1111, // index[ 460] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_187 + 4'b 1111, // index[ 461] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_188 + 4'b 1111, // index[ 462] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_189 + 4'b 1111, // index[ 463] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_190 + 4'b 1111, // index[ 464] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_191 + 4'b 1111, // index[ 465] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_192 + 4'b 1111, // index[ 466] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_193 + 4'b 1111, // index[ 467] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_194 + 4'b 1111, // index[ 468] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_195 + 4'b 1111, // index[ 469] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_196 + 4'b 1111, // index[ 470] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_197 + 4'b 1111, // index[ 471] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_198 + 4'b 1111, // index[ 472] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_199 + 4'b 1111, // index[ 473] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_200 + 4'b 1111, // index[ 474] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_201 + 4'b 1111, // index[ 475] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_202 + 4'b 1111, // index[ 476] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_203 + 4'b 1111, // index[ 477] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_204 + 4'b 1111, // index[ 478] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_205 + 4'b 1111, // index[ 479] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_206 + 4'b 1111, // index[ 480] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_207 + 4'b 1111, // index[ 481] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_208 + 4'b 1111, // index[ 482] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_209 + 4'b 1111, // index[ 483] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_210 + 4'b 1111, // index[ 484] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_211 + 4'b 1111, // index[ 485] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_212 + 4'b 1111, // index[ 486] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_213 + 4'b 1111, // index[ 487] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_214 + 4'b 1111, // index[ 488] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_215 + 4'b 1111, // index[ 489] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_216 + 4'b 1111, // index[ 490] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_217 + 4'b 1111, // index[ 491] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_218 + 4'b 1111, // index[ 492] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_219 + 4'b 1111, // index[ 493] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_220 + 4'b 1111, // index[ 494] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_221 + 4'b 1111, // index[ 495] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_222 + 4'b 1111, // index[ 496] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_223 + 4'b 1111, // index[ 497] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_224 + 4'b 1111, // index[ 498] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_225 + 4'b 1111, // index[ 499] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_226 + 4'b 1111, // index[ 500] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_227 + 4'b 1111, // index[ 501] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_228 + 4'b 1111, // index[ 502] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_229 + 4'b 1111, // index[ 503] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_230 + 4'b 1111, // index[ 504] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_231 + 4'b 1111, // index[ 505] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_232 + 4'b 1111, // index[ 506] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_233 + 4'b 1111, // index[ 507] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_234 + 4'b 1111, // index[ 508] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_235 + 4'b 1111, // index[ 509] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_236 + 4'b 1111, // index[ 510] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_237 + 4'b 1111, // index[ 511] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_238 + 4'b 1111, // index[ 512] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_239 + 4'b 1111, // index[ 513] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_240 + 4'b 1111, // index[ 514] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_241 + 4'b 1111, // index[ 515] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_242 + 4'b 1111, // index[ 516] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_243 + 4'b 1111, // index[ 517] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_244 + 4'b 1111, // index[ 518] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_245 + 4'b 1111, // index[ 519] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_246 + 4'b 1111, // index[ 520] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_247 + 4'b 1111, // index[ 521] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_248 + 4'b 1111, // index[ 522] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_249 + 4'b 1111, // index[ 523] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_250 + 4'b 1111, // index[ 524] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_251 + 4'b 1111, // index[ 525] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_252 + 4'b 1111, // index[ 526] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_253 + 4'b 1111, // index[ 527] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_254 + 4'b 1111, // index[ 528] CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_255 + 4'b 0001, // index[ 529] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0 + 4'b 0001, // index[ 530] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1 + 4'b 0001, // index[ 531] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2 + 4'b 0001, // index[ 532] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3 + 4'b 0001, // index[ 533] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4 + 4'b 0001, // index[ 534] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5 + 4'b 0001, // index[ 535] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6 + 4'b 0001, // index[ 536] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7 + 4'b 0001, // index[ 537] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8 + 4'b 0001, // index[ 538] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9 + 4'b 0001, // index[ 539] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10 + 4'b 0001, // index[ 540] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11 + 4'b 0001, // index[ 541] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12 + 4'b 0001, // index[ 542] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13 + 4'b 0001, // index[ 543] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14 + 4'b 0001, // index[ 544] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15 + 4'b 0001, // index[ 545] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16 + 4'b 0001, // index[ 546] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17 + 4'b 0001, // index[ 547] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18 + 4'b 0001, // index[ 548] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19 + 4'b 0001, // index[ 549] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20 + 4'b 0001, // index[ 550] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21 + 4'b 0001, // index[ 551] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22 + 4'b 0001, // index[ 552] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23 + 4'b 0001, // index[ 553] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24 + 4'b 0001, // index[ 554] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25 + 4'b 0001, // index[ 555] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26 + 4'b 0001, // index[ 556] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27 + 4'b 0001, // index[ 557] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28 + 4'b 0001, // index[ 558] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29 + 4'b 0001, // index[ 559] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30 + 4'b 0001, // index[ 560] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31 + 4'b 0001, // index[ 561] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32 + 4'b 0001, // index[ 562] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33 + 4'b 0001, // index[ 563] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34 + 4'b 0001, // index[ 564] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35 + 4'b 0001, // index[ 565] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36 + 4'b 0001, // index[ 566] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37 + 4'b 0001, // index[ 567] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38 + 4'b 0001, // index[ 568] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39 + 4'b 0001, // index[ 569] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40 + 4'b 0001, // index[ 570] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41 + 4'b 0001, // index[ 571] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42 + 4'b 0001, // index[ 572] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43 + 4'b 0001, // index[ 573] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44 + 4'b 0001, // index[ 574] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45 + 4'b 0001, // index[ 575] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46 + 4'b 0001, // index[ 576] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47 + 4'b 0001, // index[ 577] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48 + 4'b 0001, // index[ 578] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49 + 4'b 0001, // index[ 579] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50 + 4'b 0001, // index[ 580] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51 + 4'b 0001, // index[ 581] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52 + 4'b 0001, // index[ 582] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53 + 4'b 0001, // index[ 583] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54 + 4'b 0001, // index[ 584] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55 + 4'b 0001, // index[ 585] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56 + 4'b 0001, // index[ 586] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57 + 4'b 0001, // index[ 587] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58 + 4'b 0001, // index[ 588] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59 + 4'b 0001, // index[ 589] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60 + 4'b 0001, // index[ 590] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61 + 4'b 0001, // index[ 591] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62 + 4'b 0001, // index[ 592] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63 + 4'b 0001, // index[ 593] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_64 + 4'b 0001, // index[ 594] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_65 + 4'b 0001, // index[ 595] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_66 + 4'b 0001, // index[ 596] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_67 + 4'b 0001, // index[ 597] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_68 + 4'b 0001, // index[ 598] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_69 + 4'b 0001, // index[ 599] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_70 + 4'b 0001, // index[ 600] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_71 + 4'b 0001, // index[ 601] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_72 + 4'b 0001, // index[ 602] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_73 + 4'b 0001, // index[ 603] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_74 + 4'b 0001, // index[ 604] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_75 + 4'b 0001, // index[ 605] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_76 + 4'b 0001, // index[ 606] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_77 + 4'b 0001, // index[ 607] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_78 + 4'b 0001, // index[ 608] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_79 + 4'b 0001, // index[ 609] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_80 + 4'b 0001, // index[ 610] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_81 + 4'b 0001, // index[ 611] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_82 + 4'b 0001, // index[ 612] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_83 + 4'b 0001, // index[ 613] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_84 + 4'b 0001, // index[ 614] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_85 + 4'b 0001, // index[ 615] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_86 + 4'b 0001, // index[ 616] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_87 + 4'b 0001, // index[ 617] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_88 + 4'b 0001, // index[ 618] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_89 + 4'b 0001, // index[ 619] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_90 + 4'b 0001, // index[ 620] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_91 + 4'b 0001, // index[ 621] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_92 + 4'b 0001, // index[ 622] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_93 + 4'b 0001, // index[ 623] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_94 + 4'b 0001, // index[ 624] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_95 + 4'b 0001, // index[ 625] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_96 + 4'b 0001, // index[ 626] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_97 + 4'b 0001, // index[ 627] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_98 + 4'b 0001, // index[ 628] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_99 + 4'b 0001, // index[ 629] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_100 + 4'b 0001, // index[ 630] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_101 + 4'b 0001, // index[ 631] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_102 + 4'b 0001, // index[ 632] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_103 + 4'b 0001, // index[ 633] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_104 + 4'b 0001, // index[ 634] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_105 + 4'b 0001, // index[ 635] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_106 + 4'b 0001, // index[ 636] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_107 + 4'b 0001, // index[ 637] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_108 + 4'b 0001, // index[ 638] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_109 + 4'b 0001, // index[ 639] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_110 + 4'b 0001, // index[ 640] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_111 + 4'b 0001, // index[ 641] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_112 + 4'b 0001, // index[ 642] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_113 + 4'b 0001, // index[ 643] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_114 + 4'b 0001, // index[ 644] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_115 + 4'b 0001, // index[ 645] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_116 + 4'b 0001, // index[ 646] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_117 + 4'b 0001, // index[ 647] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_118 + 4'b 0001, // index[ 648] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_119 + 4'b 0001, // index[ 649] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_120 + 4'b 0001, // index[ 650] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_121 + 4'b 0001, // index[ 651] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_122 + 4'b 0001, // index[ 652] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_123 + 4'b 0001, // index[ 653] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_124 + 4'b 0001, // index[ 654] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_125 + 4'b 0001, // index[ 655] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_126 + 4'b 0001, // index[ 656] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_127 + 4'b 0001, // index[ 657] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_128 + 4'b 0001, // index[ 658] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_129 + 4'b 0001, // index[ 659] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_130 + 4'b 0001, // index[ 660] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_131 + 4'b 0001, // index[ 661] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_132 + 4'b 0001, // index[ 662] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_133 + 4'b 0001, // index[ 663] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_134 + 4'b 0001, // index[ 664] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_135 + 4'b 0001, // index[ 665] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_136 + 4'b 0001, // index[ 666] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_137 + 4'b 0001, // index[ 667] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_138 + 4'b 0001, // index[ 668] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_139 + 4'b 0001, // index[ 669] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_140 + 4'b 0001, // index[ 670] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_141 + 4'b 0001, // index[ 671] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_142 + 4'b 0001, // index[ 672] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_143 + 4'b 0001, // index[ 673] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_144 + 4'b 0001, // index[ 674] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_145 + 4'b 0001, // index[ 675] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_146 + 4'b 0001, // index[ 676] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_147 + 4'b 0001, // index[ 677] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_148 + 4'b 0001, // index[ 678] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_149 + 4'b 0001, // index[ 679] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_150 + 4'b 0001, // index[ 680] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_151 + 4'b 0001, // index[ 681] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_152 + 4'b 0001, // index[ 682] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_153 + 4'b 0001, // index[ 683] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_154 + 4'b 0001, // index[ 684] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_155 + 4'b 0001, // index[ 685] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_156 + 4'b 0001, // index[ 686] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_157 + 4'b 0001, // index[ 687] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_158 + 4'b 0001, // index[ 688] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_159 + 4'b 0001, // index[ 689] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_160 + 4'b 0001, // index[ 690] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_161 + 4'b 0001, // index[ 691] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_162 + 4'b 0001, // index[ 692] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_163 + 4'b 0001, // index[ 693] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_164 + 4'b 0001, // index[ 694] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_165 + 4'b 0001, // index[ 695] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_166 + 4'b 0001, // index[ 696] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_167 + 4'b 0001, // index[ 697] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_168 + 4'b 0001, // index[ 698] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_169 + 4'b 0001, // index[ 699] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_170 + 4'b 0001, // index[ 700] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_171 + 4'b 0001, // index[ 701] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_172 + 4'b 0001, // index[ 702] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_173 + 4'b 0001, // index[ 703] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_174 + 4'b 0001, // index[ 704] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_175 + 4'b 0001, // index[ 705] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_176 + 4'b 0001, // index[ 706] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_177 + 4'b 0001, // index[ 707] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_178 + 4'b 0001, // index[ 708] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_179 + 4'b 0001, // index[ 709] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_180 + 4'b 0001, // index[ 710] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_181 + 4'b 0001, // index[ 711] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_182 + 4'b 0001, // index[ 712] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_183 + 4'b 0001, // index[ 713] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_184 + 4'b 0001, // index[ 714] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_185 + 4'b 0001, // index[ 715] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_186 + 4'b 0001, // index[ 716] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_187 + 4'b 0001, // index[ 717] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_188 + 4'b 0001, // index[ 718] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_189 + 4'b 0001, // index[ 719] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_190 + 4'b 0001, // index[ 720] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_191 + 4'b 0001, // index[ 721] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_192 + 4'b 0001, // index[ 722] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_193 + 4'b 0001, // index[ 723] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_194 + 4'b 0001, // index[ 724] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_195 + 4'b 0001, // index[ 725] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_196 + 4'b 0001, // index[ 726] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_197 + 4'b 0001, // index[ 727] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_198 + 4'b 0001, // index[ 728] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_199 + 4'b 0001, // index[ 729] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_200 + 4'b 0001, // index[ 730] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_201 + 4'b 0001, // index[ 731] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_202 + 4'b 0001, // index[ 732] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_203 + 4'b 0001, // index[ 733] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_204 + 4'b 0001, // index[ 734] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_205 + 4'b 0001, // index[ 735] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_206 + 4'b 0001, // index[ 736] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_207 + 4'b 0001, // index[ 737] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_208 + 4'b 0001, // index[ 738] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_209 + 4'b 0001, // index[ 739] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_210 + 4'b 0001, // index[ 740] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_211 + 4'b 0001, // index[ 741] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_212 + 4'b 0001, // index[ 742] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_213 + 4'b 0001, // index[ 743] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_214 + 4'b 0001, // index[ 744] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_215 + 4'b 0001, // index[ 745] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_216 + 4'b 0001, // index[ 746] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_217 + 4'b 0001, // index[ 747] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_218 + 4'b 0001, // index[ 748] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_219 + 4'b 0001, // index[ 749] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_220 + 4'b 0001, // index[ 750] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_221 + 4'b 0001, // index[ 751] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_222 + 4'b 0001, // index[ 752] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_223 + 4'b 0001, // index[ 753] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_224 + 4'b 0001, // index[ 754] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_225 + 4'b 0001, // index[ 755] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_226 + 4'b 0001, // index[ 756] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_227 + 4'b 0001, // index[ 757] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_228 + 4'b 0001, // index[ 758] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_229 + 4'b 0001, // index[ 759] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_230 + 4'b 0001, // index[ 760] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_231 + 4'b 0001, // index[ 761] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_232 + 4'b 0001, // index[ 762] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_233 + 4'b 0001, // index[ 763] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_234 + 4'b 0001, // index[ 764] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_235 + 4'b 0001, // index[ 765] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_236 + 4'b 0001, // index[ 766] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_237 + 4'b 0001, // index[ 767] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_238 + 4'b 0001, // index[ 768] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_239 + 4'b 0001, // index[ 769] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_240 + 4'b 0001, // index[ 770] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_241 + 4'b 0001, // index[ 771] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_242 + 4'b 0001, // index[ 772] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_243 + 4'b 0001, // index[ 773] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_244 + 4'b 0001, // index[ 774] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_245 + 4'b 0001, // index[ 775] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_246 + 4'b 0001, // index[ 776] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_247 + 4'b 0001, // index[ 777] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_248 + 4'b 0001, // index[ 778] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_249 + 4'b 0001, // index[ 779] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_250 + 4'b 0001, // index[ 780] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_251 + 4'b 0001, // index[ 781] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_252 + 4'b 0001, // index[ 782] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_253 + 4'b 0001, // index[ 783] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_254 + 4'b 0001, // index[ 784] CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_255 + 4'b 0001, // index[ 785] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0 + 4'b 0001, // index[ 786] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1 + 4'b 0001, // index[ 787] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2 + 4'b 0001, // index[ 788] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3 + 4'b 0001, // index[ 789] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4 + 4'b 0001, // index[ 790] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5 + 4'b 0001, // index[ 791] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6 + 4'b 0001, // index[ 792] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7 + 4'b 0001, // index[ 793] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8 + 4'b 0001, // index[ 794] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9 + 4'b 0001, // index[ 795] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10 + 4'b 0001, // index[ 796] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11 + 4'b 0001, // index[ 797] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12 + 4'b 0001, // index[ 798] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13 + 4'b 0001, // index[ 799] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14 + 4'b 0001, // index[ 800] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15 + 4'b 0001, // index[ 801] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16 + 4'b 0001, // index[ 802] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17 + 4'b 0001, // index[ 803] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18 + 4'b 0001, // index[ 804] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19 + 4'b 0001, // index[ 805] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20 + 4'b 0001, // index[ 806] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21 + 4'b 0001, // index[ 807] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22 + 4'b 0001, // index[ 808] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23 + 4'b 0001, // index[ 809] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24 + 4'b 0001, // index[ 810] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25 + 4'b 0001, // index[ 811] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26 + 4'b 0001, // index[ 812] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27 + 4'b 0001, // index[ 813] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28 + 4'b 0001, // index[ 814] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29 + 4'b 0001, // index[ 815] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30 + 4'b 0001, // index[ 816] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31 + 4'b 0001, // index[ 817] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32 + 4'b 0001, // index[ 818] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33 + 4'b 0001, // index[ 819] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34 + 4'b 0001, // index[ 820] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35 + 4'b 0001, // index[ 821] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36 + 4'b 0001, // index[ 822] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37 + 4'b 0001, // index[ 823] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38 + 4'b 0001, // index[ 824] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39 + 4'b 0001, // index[ 825] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40 + 4'b 0001, // index[ 826] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41 + 4'b 0001, // index[ 827] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42 + 4'b 0001, // index[ 828] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43 + 4'b 0001, // index[ 829] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44 + 4'b 0001, // index[ 830] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45 + 4'b 0001, // index[ 831] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46 + 4'b 0001, // index[ 832] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47 + 4'b 0001, // index[ 833] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48 + 4'b 0001, // index[ 834] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49 + 4'b 0001, // index[ 835] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50 + 4'b 0001, // index[ 836] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51 + 4'b 0001, // index[ 837] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52 + 4'b 0001, // index[ 838] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53 + 4'b 0001, // index[ 839] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54 + 4'b 0001, // index[ 840] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55 + 4'b 0001, // index[ 841] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56 + 4'b 0001, // index[ 842] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57 + 4'b 0001, // index[ 843] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58 + 4'b 0001, // index[ 844] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59 + 4'b 0001, // index[ 845] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60 + 4'b 0001, // index[ 846] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61 + 4'b 0001, // index[ 847] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62 + 4'b 0001, // index[ 848] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63 + 4'b 0001, // index[ 849] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_64 + 4'b 0001, // index[ 850] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_65 + 4'b 0001, // index[ 851] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_66 + 4'b 0001, // index[ 852] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_67 + 4'b 0001, // index[ 853] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_68 + 4'b 0001, // index[ 854] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_69 + 4'b 0001, // index[ 855] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_70 + 4'b 0001, // index[ 856] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_71 + 4'b 0001, // index[ 857] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_72 + 4'b 0001, // index[ 858] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_73 + 4'b 0001, // index[ 859] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_74 + 4'b 0001, // index[ 860] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_75 + 4'b 0001, // index[ 861] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_76 + 4'b 0001, // index[ 862] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_77 + 4'b 0001, // index[ 863] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_78 + 4'b 0001, // index[ 864] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_79 + 4'b 0001, // index[ 865] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_80 + 4'b 0001, // index[ 866] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_81 + 4'b 0001, // index[ 867] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_82 + 4'b 0001, // index[ 868] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_83 + 4'b 0001, // index[ 869] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_84 + 4'b 0001, // index[ 870] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_85 + 4'b 0001, // index[ 871] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_86 + 4'b 0001, // index[ 872] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_87 + 4'b 0001, // index[ 873] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_88 + 4'b 0001, // index[ 874] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_89 + 4'b 0001, // index[ 875] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_90 + 4'b 0001, // index[ 876] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_91 + 4'b 0001, // index[ 877] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_92 + 4'b 0001, // index[ 878] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_93 + 4'b 0001, // index[ 879] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_94 + 4'b 0001, // index[ 880] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_95 + 4'b 0001, // index[ 881] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_96 + 4'b 0001, // index[ 882] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_97 + 4'b 0001, // index[ 883] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_98 + 4'b 0001, // index[ 884] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_99 + 4'b 0001, // index[ 885] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_100 + 4'b 0001, // index[ 886] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_101 + 4'b 0001, // index[ 887] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_102 + 4'b 0001, // index[ 888] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_103 + 4'b 0001, // index[ 889] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_104 + 4'b 0001, // index[ 890] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_105 + 4'b 0001, // index[ 891] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_106 + 4'b 0001, // index[ 892] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_107 + 4'b 0001, // index[ 893] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_108 + 4'b 0001, // index[ 894] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_109 + 4'b 0001, // index[ 895] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_110 + 4'b 0001, // index[ 896] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_111 + 4'b 0001, // index[ 897] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_112 + 4'b 0001, // index[ 898] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_113 + 4'b 0001, // index[ 899] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_114 + 4'b 0001, // index[ 900] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_115 + 4'b 0001, // index[ 901] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_116 + 4'b 0001, // index[ 902] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_117 + 4'b 0001, // index[ 903] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_118 + 4'b 0001, // index[ 904] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_119 + 4'b 0001, // index[ 905] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_120 + 4'b 0001, // index[ 906] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_121 + 4'b 0001, // index[ 907] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_122 + 4'b 0001, // index[ 908] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_123 + 4'b 0001, // index[ 909] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_124 + 4'b 0001, // index[ 910] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_125 + 4'b 0001, // index[ 911] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_126 + 4'b 0001, // index[ 912] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_127 + 4'b 0001, // index[ 913] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_128 + 4'b 0001, // index[ 914] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_129 + 4'b 0001, // index[ 915] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_130 + 4'b 0001, // index[ 916] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_131 + 4'b 0001, // index[ 917] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_132 + 4'b 0001, // index[ 918] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_133 + 4'b 0001, // index[ 919] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_134 + 4'b 0001, // index[ 920] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_135 + 4'b 0001, // index[ 921] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_136 + 4'b 0001, // index[ 922] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_137 + 4'b 0001, // index[ 923] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_138 + 4'b 0001, // index[ 924] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_139 + 4'b 0001, // index[ 925] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_140 + 4'b 0001, // index[ 926] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_141 + 4'b 0001, // index[ 927] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_142 + 4'b 0001, // index[ 928] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_143 + 4'b 0001, // index[ 929] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_144 + 4'b 0001, // index[ 930] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_145 + 4'b 0001, // index[ 931] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_146 + 4'b 0001, // index[ 932] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_147 + 4'b 0001, // index[ 933] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_148 + 4'b 0001, // index[ 934] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_149 + 4'b 0001, // index[ 935] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_150 + 4'b 0001, // index[ 936] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_151 + 4'b 0001, // index[ 937] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_152 + 4'b 0001, // index[ 938] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_153 + 4'b 0001, // index[ 939] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_154 + 4'b 0001, // index[ 940] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_155 + 4'b 0001, // index[ 941] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_156 + 4'b 0001, // index[ 942] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_157 + 4'b 0001, // index[ 943] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_158 + 4'b 0001, // index[ 944] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_159 + 4'b 0001, // index[ 945] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_160 + 4'b 0001, // index[ 946] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_161 + 4'b 0001, // index[ 947] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_162 + 4'b 0001, // index[ 948] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_163 + 4'b 0001, // index[ 949] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_164 + 4'b 0001, // index[ 950] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_165 + 4'b 0001, // index[ 951] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_166 + 4'b 0001, // index[ 952] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_167 + 4'b 0001, // index[ 953] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_168 + 4'b 0001, // index[ 954] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_169 + 4'b 0001, // index[ 955] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_170 + 4'b 0001, // index[ 956] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_171 + 4'b 0001, // index[ 957] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_172 + 4'b 0001, // index[ 958] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_173 + 4'b 0001, // index[ 959] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_174 + 4'b 0001, // index[ 960] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_175 + 4'b 0001, // index[ 961] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_176 + 4'b 0001, // index[ 962] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_177 + 4'b 0001, // index[ 963] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_178 + 4'b 0001, // index[ 964] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_179 + 4'b 0001, // index[ 965] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_180 + 4'b 0001, // index[ 966] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_181 + 4'b 0001, // index[ 967] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_182 + 4'b 0001, // index[ 968] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_183 + 4'b 0001, // index[ 969] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_184 + 4'b 0001, // index[ 970] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_185 + 4'b 0001, // index[ 971] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_186 + 4'b 0001, // index[ 972] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_187 + 4'b 0001, // index[ 973] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_188 + 4'b 0001, // index[ 974] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_189 + 4'b 0001, // index[ 975] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_190 + 4'b 0001, // index[ 976] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_191 + 4'b 0001, // index[ 977] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_192 + 4'b 0001, // index[ 978] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_193 + 4'b 0001, // index[ 979] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_194 + 4'b 0001, // index[ 980] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_195 + 4'b 0001, // index[ 981] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_196 + 4'b 0001, // index[ 982] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_197 + 4'b 0001, // index[ 983] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_198 + 4'b 0001, // index[ 984] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_199 + 4'b 0001, // index[ 985] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_200 + 4'b 0001, // index[ 986] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_201 + 4'b 0001, // index[ 987] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_202 + 4'b 0001, // index[ 988] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_203 + 4'b 0001, // index[ 989] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_204 + 4'b 0001, // index[ 990] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_205 + 4'b 0001, // index[ 991] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_206 + 4'b 0001, // index[ 992] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_207 + 4'b 0001, // index[ 993] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_208 + 4'b 0001, // index[ 994] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_209 + 4'b 0001, // index[ 995] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_210 + 4'b 0001, // index[ 996] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_211 + 4'b 0001, // index[ 997] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_212 + 4'b 0001, // index[ 998] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_213 + 4'b 0001, // index[ 999] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_214 + 4'b 0001, // index[1000] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_215 + 4'b 0001, // index[1001] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_216 + 4'b 0001, // index[1002] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_217 + 4'b 0001, // index[1003] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_218 + 4'b 0001, // index[1004] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_219 + 4'b 0001, // index[1005] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_220 + 4'b 0001, // index[1006] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_221 + 4'b 0001, // index[1007] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_222 + 4'b 0001, // index[1008] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_223 + 4'b 0001, // index[1009] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_224 + 4'b 0001, // index[1010] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_225 + 4'b 0001, // index[1011] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_226 + 4'b 0001, // index[1012] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_227 + 4'b 0001, // index[1013] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_228 + 4'b 0001, // index[1014] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_229 + 4'b 0001, // index[1015] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_230 + 4'b 0001, // index[1016] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_231 + 4'b 0001, // index[1017] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_232 + 4'b 0001, // index[1018] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_233 + 4'b 0001, // index[1019] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_234 + 4'b 0001, // index[1020] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_235 + 4'b 0001, // index[1021] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_236 + 4'b 0001, // index[1022] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_237 + 4'b 0001, // index[1023] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_238 + 4'b 0001, // index[1024] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_239 + 4'b 0001, // index[1025] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_240 + 4'b 0001, // index[1026] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_241 + 4'b 0001, // index[1027] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_242 + 4'b 0001, // index[1028] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_243 + 4'b 0001, // index[1029] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_244 + 4'b 0001, // index[1030] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_245 + 4'b 0001, // index[1031] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_246 + 4'b 0001, // index[1032] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_247 + 4'b 0001, // index[1033] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_248 + 4'b 0001, // index[1034] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_249 + 4'b 0001, // index[1035] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_250 + 4'b 0001, // index[1036] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_251 + 4'b 0001, // index[1037] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_252 + 4'b 0001, // index[1038] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_253 + 4'b 0001, // index[1039] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_254 + 4'b 0001 // index[1040] CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_255 }; endpackage diff --git a/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv b/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv index 5cda172..053680a 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv +++ b/hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv @@ -10,7 +10,7 @@ module cachepool_peripheral_reg_top #( parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, - parameter int AW = 11 + parameter int AW = 13 ) ( input logic clk_i, input logic rst_ni, @@ -307,6 +307,582 @@ module cachepool_peripheral_reg_top #( logic [2:0] cfg_lp1_cmo_63_qs; logic [2:0] cfg_lp1_cmo_63_wd; logic cfg_lp1_cmo_63_we; + logic [2:0] cfg_lp1_cmo_64_qs; + logic [2:0] cfg_lp1_cmo_64_wd; + logic cfg_lp1_cmo_64_we; + logic [2:0] cfg_lp1_cmo_65_qs; + logic [2:0] cfg_lp1_cmo_65_wd; + logic cfg_lp1_cmo_65_we; + logic [2:0] cfg_lp1_cmo_66_qs; + logic [2:0] cfg_lp1_cmo_66_wd; + logic cfg_lp1_cmo_66_we; + logic [2:0] cfg_lp1_cmo_67_qs; + logic [2:0] cfg_lp1_cmo_67_wd; + logic cfg_lp1_cmo_67_we; + logic [2:0] cfg_lp1_cmo_68_qs; + logic [2:0] cfg_lp1_cmo_68_wd; + logic cfg_lp1_cmo_68_we; + logic [2:0] cfg_lp1_cmo_69_qs; + logic [2:0] cfg_lp1_cmo_69_wd; + logic cfg_lp1_cmo_69_we; + logic [2:0] cfg_lp1_cmo_70_qs; + logic [2:0] cfg_lp1_cmo_70_wd; + logic cfg_lp1_cmo_70_we; + logic [2:0] cfg_lp1_cmo_71_qs; + logic [2:0] cfg_lp1_cmo_71_wd; + logic cfg_lp1_cmo_71_we; + logic [2:0] cfg_lp1_cmo_72_qs; + logic [2:0] cfg_lp1_cmo_72_wd; + logic cfg_lp1_cmo_72_we; + logic [2:0] cfg_lp1_cmo_73_qs; + logic [2:0] cfg_lp1_cmo_73_wd; + logic cfg_lp1_cmo_73_we; + logic [2:0] cfg_lp1_cmo_74_qs; + logic [2:0] cfg_lp1_cmo_74_wd; + logic cfg_lp1_cmo_74_we; + logic [2:0] cfg_lp1_cmo_75_qs; + logic [2:0] cfg_lp1_cmo_75_wd; + logic cfg_lp1_cmo_75_we; + logic [2:0] cfg_lp1_cmo_76_qs; + logic [2:0] cfg_lp1_cmo_76_wd; + logic cfg_lp1_cmo_76_we; + logic [2:0] cfg_lp1_cmo_77_qs; + logic [2:0] cfg_lp1_cmo_77_wd; + logic cfg_lp1_cmo_77_we; + logic [2:0] cfg_lp1_cmo_78_qs; + logic [2:0] cfg_lp1_cmo_78_wd; + logic cfg_lp1_cmo_78_we; + logic [2:0] cfg_lp1_cmo_79_qs; + logic [2:0] cfg_lp1_cmo_79_wd; + logic cfg_lp1_cmo_79_we; + logic [2:0] cfg_lp1_cmo_80_qs; + logic [2:0] cfg_lp1_cmo_80_wd; + logic cfg_lp1_cmo_80_we; + logic [2:0] cfg_lp1_cmo_81_qs; + logic [2:0] cfg_lp1_cmo_81_wd; + logic cfg_lp1_cmo_81_we; + logic [2:0] cfg_lp1_cmo_82_qs; + logic [2:0] cfg_lp1_cmo_82_wd; + logic cfg_lp1_cmo_82_we; + logic [2:0] cfg_lp1_cmo_83_qs; + logic [2:0] cfg_lp1_cmo_83_wd; + logic cfg_lp1_cmo_83_we; + logic [2:0] cfg_lp1_cmo_84_qs; + logic [2:0] cfg_lp1_cmo_84_wd; + logic cfg_lp1_cmo_84_we; + logic [2:0] cfg_lp1_cmo_85_qs; + logic [2:0] cfg_lp1_cmo_85_wd; + logic cfg_lp1_cmo_85_we; + logic [2:0] cfg_lp1_cmo_86_qs; + logic [2:0] cfg_lp1_cmo_86_wd; + logic cfg_lp1_cmo_86_we; + logic [2:0] cfg_lp1_cmo_87_qs; + logic [2:0] cfg_lp1_cmo_87_wd; + logic cfg_lp1_cmo_87_we; + logic [2:0] cfg_lp1_cmo_88_qs; + logic [2:0] cfg_lp1_cmo_88_wd; + logic cfg_lp1_cmo_88_we; + logic [2:0] cfg_lp1_cmo_89_qs; + logic [2:0] cfg_lp1_cmo_89_wd; + logic cfg_lp1_cmo_89_we; + logic [2:0] cfg_lp1_cmo_90_qs; + logic [2:0] cfg_lp1_cmo_90_wd; + logic cfg_lp1_cmo_90_we; + logic [2:0] cfg_lp1_cmo_91_qs; + logic [2:0] cfg_lp1_cmo_91_wd; + logic cfg_lp1_cmo_91_we; + logic [2:0] cfg_lp1_cmo_92_qs; + logic [2:0] cfg_lp1_cmo_92_wd; + logic cfg_lp1_cmo_92_we; + logic [2:0] cfg_lp1_cmo_93_qs; + logic [2:0] cfg_lp1_cmo_93_wd; + logic cfg_lp1_cmo_93_we; + logic [2:0] cfg_lp1_cmo_94_qs; + logic [2:0] cfg_lp1_cmo_94_wd; + logic cfg_lp1_cmo_94_we; + logic [2:0] cfg_lp1_cmo_95_qs; + logic [2:0] cfg_lp1_cmo_95_wd; + logic cfg_lp1_cmo_95_we; + logic [2:0] cfg_lp1_cmo_96_qs; + logic [2:0] cfg_lp1_cmo_96_wd; + logic cfg_lp1_cmo_96_we; + logic [2:0] cfg_lp1_cmo_97_qs; + logic [2:0] cfg_lp1_cmo_97_wd; + logic cfg_lp1_cmo_97_we; + logic [2:0] cfg_lp1_cmo_98_qs; + logic [2:0] cfg_lp1_cmo_98_wd; + logic cfg_lp1_cmo_98_we; + logic [2:0] cfg_lp1_cmo_99_qs; + logic [2:0] cfg_lp1_cmo_99_wd; + logic cfg_lp1_cmo_99_we; + logic [2:0] cfg_lp1_cmo_100_qs; + logic [2:0] cfg_lp1_cmo_100_wd; + logic cfg_lp1_cmo_100_we; + logic [2:0] cfg_lp1_cmo_101_qs; + logic [2:0] cfg_lp1_cmo_101_wd; + logic cfg_lp1_cmo_101_we; + logic [2:0] cfg_lp1_cmo_102_qs; + logic [2:0] cfg_lp1_cmo_102_wd; + logic cfg_lp1_cmo_102_we; + logic [2:0] cfg_lp1_cmo_103_qs; + logic [2:0] cfg_lp1_cmo_103_wd; + logic cfg_lp1_cmo_103_we; + logic [2:0] cfg_lp1_cmo_104_qs; + logic [2:0] cfg_lp1_cmo_104_wd; + logic cfg_lp1_cmo_104_we; + logic [2:0] cfg_lp1_cmo_105_qs; + logic [2:0] cfg_lp1_cmo_105_wd; + logic cfg_lp1_cmo_105_we; + logic [2:0] cfg_lp1_cmo_106_qs; + logic [2:0] cfg_lp1_cmo_106_wd; + logic cfg_lp1_cmo_106_we; + logic [2:0] cfg_lp1_cmo_107_qs; + logic [2:0] cfg_lp1_cmo_107_wd; + logic cfg_lp1_cmo_107_we; + logic [2:0] cfg_lp1_cmo_108_qs; + logic [2:0] cfg_lp1_cmo_108_wd; + logic cfg_lp1_cmo_108_we; + logic [2:0] cfg_lp1_cmo_109_qs; + logic [2:0] cfg_lp1_cmo_109_wd; + logic cfg_lp1_cmo_109_we; + logic [2:0] cfg_lp1_cmo_110_qs; + logic [2:0] cfg_lp1_cmo_110_wd; + logic cfg_lp1_cmo_110_we; + logic [2:0] cfg_lp1_cmo_111_qs; + logic [2:0] cfg_lp1_cmo_111_wd; + logic cfg_lp1_cmo_111_we; + logic [2:0] cfg_lp1_cmo_112_qs; + logic [2:0] cfg_lp1_cmo_112_wd; + logic cfg_lp1_cmo_112_we; + logic [2:0] cfg_lp1_cmo_113_qs; + logic [2:0] cfg_lp1_cmo_113_wd; + logic cfg_lp1_cmo_113_we; + logic [2:0] cfg_lp1_cmo_114_qs; + logic [2:0] cfg_lp1_cmo_114_wd; + logic cfg_lp1_cmo_114_we; + logic [2:0] cfg_lp1_cmo_115_qs; + logic [2:0] cfg_lp1_cmo_115_wd; + logic cfg_lp1_cmo_115_we; + logic [2:0] cfg_lp1_cmo_116_qs; + logic [2:0] cfg_lp1_cmo_116_wd; + logic cfg_lp1_cmo_116_we; + logic [2:0] cfg_lp1_cmo_117_qs; + logic [2:0] cfg_lp1_cmo_117_wd; + logic cfg_lp1_cmo_117_we; + logic [2:0] cfg_lp1_cmo_118_qs; + logic [2:0] cfg_lp1_cmo_118_wd; + logic cfg_lp1_cmo_118_we; + logic [2:0] cfg_lp1_cmo_119_qs; + logic [2:0] cfg_lp1_cmo_119_wd; + logic cfg_lp1_cmo_119_we; + logic [2:0] cfg_lp1_cmo_120_qs; + logic [2:0] cfg_lp1_cmo_120_wd; + logic cfg_lp1_cmo_120_we; + logic [2:0] cfg_lp1_cmo_121_qs; + logic [2:0] cfg_lp1_cmo_121_wd; + logic cfg_lp1_cmo_121_we; + logic [2:0] cfg_lp1_cmo_122_qs; + logic [2:0] cfg_lp1_cmo_122_wd; + logic cfg_lp1_cmo_122_we; + logic [2:0] cfg_lp1_cmo_123_qs; + logic [2:0] cfg_lp1_cmo_123_wd; + logic cfg_lp1_cmo_123_we; + logic [2:0] cfg_lp1_cmo_124_qs; + logic [2:0] cfg_lp1_cmo_124_wd; + logic cfg_lp1_cmo_124_we; + logic [2:0] cfg_lp1_cmo_125_qs; + logic [2:0] cfg_lp1_cmo_125_wd; + logic cfg_lp1_cmo_125_we; + logic [2:0] cfg_lp1_cmo_126_qs; + logic [2:0] cfg_lp1_cmo_126_wd; + logic cfg_lp1_cmo_126_we; + logic [2:0] cfg_lp1_cmo_127_qs; + logic [2:0] cfg_lp1_cmo_127_wd; + logic cfg_lp1_cmo_127_we; + logic [2:0] cfg_lp1_cmo_128_qs; + logic [2:0] cfg_lp1_cmo_128_wd; + logic cfg_lp1_cmo_128_we; + logic [2:0] cfg_lp1_cmo_129_qs; + logic [2:0] cfg_lp1_cmo_129_wd; + logic cfg_lp1_cmo_129_we; + logic [2:0] cfg_lp1_cmo_130_qs; + logic [2:0] cfg_lp1_cmo_130_wd; + logic cfg_lp1_cmo_130_we; + logic [2:0] cfg_lp1_cmo_131_qs; + logic [2:0] cfg_lp1_cmo_131_wd; + logic cfg_lp1_cmo_131_we; + logic [2:0] cfg_lp1_cmo_132_qs; + logic [2:0] cfg_lp1_cmo_132_wd; + logic cfg_lp1_cmo_132_we; + logic [2:0] cfg_lp1_cmo_133_qs; + logic [2:0] cfg_lp1_cmo_133_wd; + logic cfg_lp1_cmo_133_we; + logic [2:0] cfg_lp1_cmo_134_qs; + logic [2:0] cfg_lp1_cmo_134_wd; + logic cfg_lp1_cmo_134_we; + logic [2:0] cfg_lp1_cmo_135_qs; + logic [2:0] cfg_lp1_cmo_135_wd; + logic cfg_lp1_cmo_135_we; + logic [2:0] cfg_lp1_cmo_136_qs; + logic [2:0] cfg_lp1_cmo_136_wd; + logic cfg_lp1_cmo_136_we; + logic [2:0] cfg_lp1_cmo_137_qs; + logic [2:0] cfg_lp1_cmo_137_wd; + logic cfg_lp1_cmo_137_we; + logic [2:0] cfg_lp1_cmo_138_qs; + logic [2:0] cfg_lp1_cmo_138_wd; + logic cfg_lp1_cmo_138_we; + logic [2:0] cfg_lp1_cmo_139_qs; + logic [2:0] cfg_lp1_cmo_139_wd; + logic cfg_lp1_cmo_139_we; + logic [2:0] cfg_lp1_cmo_140_qs; + logic [2:0] cfg_lp1_cmo_140_wd; + logic cfg_lp1_cmo_140_we; + logic [2:0] cfg_lp1_cmo_141_qs; + logic [2:0] cfg_lp1_cmo_141_wd; + logic cfg_lp1_cmo_141_we; + logic [2:0] cfg_lp1_cmo_142_qs; + logic [2:0] cfg_lp1_cmo_142_wd; + logic cfg_lp1_cmo_142_we; + logic [2:0] cfg_lp1_cmo_143_qs; + logic [2:0] cfg_lp1_cmo_143_wd; + logic cfg_lp1_cmo_143_we; + logic [2:0] cfg_lp1_cmo_144_qs; + logic [2:0] cfg_lp1_cmo_144_wd; + logic cfg_lp1_cmo_144_we; + logic [2:0] cfg_lp1_cmo_145_qs; + logic [2:0] cfg_lp1_cmo_145_wd; + logic cfg_lp1_cmo_145_we; + logic [2:0] cfg_lp1_cmo_146_qs; + logic [2:0] cfg_lp1_cmo_146_wd; + logic cfg_lp1_cmo_146_we; + logic [2:0] cfg_lp1_cmo_147_qs; + logic [2:0] cfg_lp1_cmo_147_wd; + logic cfg_lp1_cmo_147_we; + logic [2:0] cfg_lp1_cmo_148_qs; + logic [2:0] cfg_lp1_cmo_148_wd; + logic cfg_lp1_cmo_148_we; + logic [2:0] cfg_lp1_cmo_149_qs; + logic [2:0] cfg_lp1_cmo_149_wd; + logic cfg_lp1_cmo_149_we; + logic [2:0] cfg_lp1_cmo_150_qs; + logic [2:0] cfg_lp1_cmo_150_wd; + logic cfg_lp1_cmo_150_we; + logic [2:0] cfg_lp1_cmo_151_qs; + logic [2:0] cfg_lp1_cmo_151_wd; + logic cfg_lp1_cmo_151_we; + logic [2:0] cfg_lp1_cmo_152_qs; + logic [2:0] cfg_lp1_cmo_152_wd; + logic cfg_lp1_cmo_152_we; + logic [2:0] cfg_lp1_cmo_153_qs; + logic [2:0] cfg_lp1_cmo_153_wd; + logic cfg_lp1_cmo_153_we; + logic [2:0] cfg_lp1_cmo_154_qs; + logic [2:0] cfg_lp1_cmo_154_wd; + logic cfg_lp1_cmo_154_we; + logic [2:0] cfg_lp1_cmo_155_qs; + logic [2:0] cfg_lp1_cmo_155_wd; + logic cfg_lp1_cmo_155_we; + logic [2:0] cfg_lp1_cmo_156_qs; + logic [2:0] cfg_lp1_cmo_156_wd; + logic cfg_lp1_cmo_156_we; + logic [2:0] cfg_lp1_cmo_157_qs; + logic [2:0] cfg_lp1_cmo_157_wd; + logic cfg_lp1_cmo_157_we; + logic [2:0] cfg_lp1_cmo_158_qs; + logic [2:0] cfg_lp1_cmo_158_wd; + logic cfg_lp1_cmo_158_we; + logic [2:0] cfg_lp1_cmo_159_qs; + logic [2:0] cfg_lp1_cmo_159_wd; + logic cfg_lp1_cmo_159_we; + logic [2:0] cfg_lp1_cmo_160_qs; + logic [2:0] cfg_lp1_cmo_160_wd; + logic cfg_lp1_cmo_160_we; + logic [2:0] cfg_lp1_cmo_161_qs; + logic [2:0] cfg_lp1_cmo_161_wd; + logic cfg_lp1_cmo_161_we; + logic [2:0] cfg_lp1_cmo_162_qs; + logic [2:0] cfg_lp1_cmo_162_wd; + logic cfg_lp1_cmo_162_we; + logic [2:0] cfg_lp1_cmo_163_qs; + logic [2:0] cfg_lp1_cmo_163_wd; + logic cfg_lp1_cmo_163_we; + logic [2:0] cfg_lp1_cmo_164_qs; + logic [2:0] cfg_lp1_cmo_164_wd; + logic cfg_lp1_cmo_164_we; + logic [2:0] cfg_lp1_cmo_165_qs; + logic [2:0] cfg_lp1_cmo_165_wd; + logic cfg_lp1_cmo_165_we; + logic [2:0] cfg_lp1_cmo_166_qs; + logic [2:0] cfg_lp1_cmo_166_wd; + logic cfg_lp1_cmo_166_we; + logic [2:0] cfg_lp1_cmo_167_qs; + logic [2:0] cfg_lp1_cmo_167_wd; + logic cfg_lp1_cmo_167_we; + logic [2:0] cfg_lp1_cmo_168_qs; + logic [2:0] cfg_lp1_cmo_168_wd; + logic cfg_lp1_cmo_168_we; + logic [2:0] cfg_lp1_cmo_169_qs; + logic [2:0] cfg_lp1_cmo_169_wd; + logic cfg_lp1_cmo_169_we; + logic [2:0] cfg_lp1_cmo_170_qs; + logic [2:0] cfg_lp1_cmo_170_wd; + logic cfg_lp1_cmo_170_we; + logic [2:0] cfg_lp1_cmo_171_qs; + logic [2:0] cfg_lp1_cmo_171_wd; + logic cfg_lp1_cmo_171_we; + logic [2:0] cfg_lp1_cmo_172_qs; + logic [2:0] cfg_lp1_cmo_172_wd; + logic cfg_lp1_cmo_172_we; + logic [2:0] cfg_lp1_cmo_173_qs; + logic [2:0] cfg_lp1_cmo_173_wd; + logic cfg_lp1_cmo_173_we; + logic [2:0] cfg_lp1_cmo_174_qs; + logic [2:0] cfg_lp1_cmo_174_wd; + logic cfg_lp1_cmo_174_we; + logic [2:0] cfg_lp1_cmo_175_qs; + logic [2:0] cfg_lp1_cmo_175_wd; + logic cfg_lp1_cmo_175_we; + logic [2:0] cfg_lp1_cmo_176_qs; + logic [2:0] cfg_lp1_cmo_176_wd; + logic cfg_lp1_cmo_176_we; + logic [2:0] cfg_lp1_cmo_177_qs; + logic [2:0] cfg_lp1_cmo_177_wd; + logic cfg_lp1_cmo_177_we; + logic [2:0] cfg_lp1_cmo_178_qs; + logic [2:0] cfg_lp1_cmo_178_wd; + logic cfg_lp1_cmo_178_we; + logic [2:0] cfg_lp1_cmo_179_qs; + logic [2:0] cfg_lp1_cmo_179_wd; + logic cfg_lp1_cmo_179_we; + logic [2:0] cfg_lp1_cmo_180_qs; + logic [2:0] cfg_lp1_cmo_180_wd; + logic cfg_lp1_cmo_180_we; + logic [2:0] cfg_lp1_cmo_181_qs; + logic [2:0] cfg_lp1_cmo_181_wd; + logic cfg_lp1_cmo_181_we; + logic [2:0] cfg_lp1_cmo_182_qs; + logic [2:0] cfg_lp1_cmo_182_wd; + logic cfg_lp1_cmo_182_we; + logic [2:0] cfg_lp1_cmo_183_qs; + logic [2:0] cfg_lp1_cmo_183_wd; + logic cfg_lp1_cmo_183_we; + logic [2:0] cfg_lp1_cmo_184_qs; + logic [2:0] cfg_lp1_cmo_184_wd; + logic cfg_lp1_cmo_184_we; + logic [2:0] cfg_lp1_cmo_185_qs; + logic [2:0] cfg_lp1_cmo_185_wd; + logic cfg_lp1_cmo_185_we; + logic [2:0] cfg_lp1_cmo_186_qs; + logic [2:0] cfg_lp1_cmo_186_wd; + logic cfg_lp1_cmo_186_we; + logic [2:0] cfg_lp1_cmo_187_qs; + logic [2:0] cfg_lp1_cmo_187_wd; + logic cfg_lp1_cmo_187_we; + logic [2:0] cfg_lp1_cmo_188_qs; + logic [2:0] cfg_lp1_cmo_188_wd; + logic cfg_lp1_cmo_188_we; + logic [2:0] cfg_lp1_cmo_189_qs; + logic [2:0] cfg_lp1_cmo_189_wd; + logic cfg_lp1_cmo_189_we; + logic [2:0] cfg_lp1_cmo_190_qs; + logic [2:0] cfg_lp1_cmo_190_wd; + logic cfg_lp1_cmo_190_we; + logic [2:0] cfg_lp1_cmo_191_qs; + logic [2:0] cfg_lp1_cmo_191_wd; + logic cfg_lp1_cmo_191_we; + logic [2:0] cfg_lp1_cmo_192_qs; + logic [2:0] cfg_lp1_cmo_192_wd; + logic cfg_lp1_cmo_192_we; + logic [2:0] cfg_lp1_cmo_193_qs; + logic [2:0] cfg_lp1_cmo_193_wd; + logic cfg_lp1_cmo_193_we; + logic [2:0] cfg_lp1_cmo_194_qs; + logic [2:0] cfg_lp1_cmo_194_wd; + logic cfg_lp1_cmo_194_we; + logic [2:0] cfg_lp1_cmo_195_qs; + logic [2:0] cfg_lp1_cmo_195_wd; + logic cfg_lp1_cmo_195_we; + logic [2:0] cfg_lp1_cmo_196_qs; + logic [2:0] cfg_lp1_cmo_196_wd; + logic cfg_lp1_cmo_196_we; + logic [2:0] cfg_lp1_cmo_197_qs; + logic [2:0] cfg_lp1_cmo_197_wd; + logic cfg_lp1_cmo_197_we; + logic [2:0] cfg_lp1_cmo_198_qs; + logic [2:0] cfg_lp1_cmo_198_wd; + logic cfg_lp1_cmo_198_we; + logic [2:0] cfg_lp1_cmo_199_qs; + logic [2:0] cfg_lp1_cmo_199_wd; + logic cfg_lp1_cmo_199_we; + logic [2:0] cfg_lp1_cmo_200_qs; + logic [2:0] cfg_lp1_cmo_200_wd; + logic cfg_lp1_cmo_200_we; + logic [2:0] cfg_lp1_cmo_201_qs; + logic [2:0] cfg_lp1_cmo_201_wd; + logic cfg_lp1_cmo_201_we; + logic [2:0] cfg_lp1_cmo_202_qs; + logic [2:0] cfg_lp1_cmo_202_wd; + logic cfg_lp1_cmo_202_we; + logic [2:0] cfg_lp1_cmo_203_qs; + logic [2:0] cfg_lp1_cmo_203_wd; + logic cfg_lp1_cmo_203_we; + logic [2:0] cfg_lp1_cmo_204_qs; + logic [2:0] cfg_lp1_cmo_204_wd; + logic cfg_lp1_cmo_204_we; + logic [2:0] cfg_lp1_cmo_205_qs; + logic [2:0] cfg_lp1_cmo_205_wd; + logic cfg_lp1_cmo_205_we; + logic [2:0] cfg_lp1_cmo_206_qs; + logic [2:0] cfg_lp1_cmo_206_wd; + logic cfg_lp1_cmo_206_we; + logic [2:0] cfg_lp1_cmo_207_qs; + logic [2:0] cfg_lp1_cmo_207_wd; + logic cfg_lp1_cmo_207_we; + logic [2:0] cfg_lp1_cmo_208_qs; + logic [2:0] cfg_lp1_cmo_208_wd; + logic cfg_lp1_cmo_208_we; + logic [2:0] cfg_lp1_cmo_209_qs; + logic [2:0] cfg_lp1_cmo_209_wd; + logic cfg_lp1_cmo_209_we; + logic [2:0] cfg_lp1_cmo_210_qs; + logic [2:0] cfg_lp1_cmo_210_wd; + logic cfg_lp1_cmo_210_we; + logic [2:0] cfg_lp1_cmo_211_qs; + logic [2:0] cfg_lp1_cmo_211_wd; + logic cfg_lp1_cmo_211_we; + logic [2:0] cfg_lp1_cmo_212_qs; + logic [2:0] cfg_lp1_cmo_212_wd; + logic cfg_lp1_cmo_212_we; + logic [2:0] cfg_lp1_cmo_213_qs; + logic [2:0] cfg_lp1_cmo_213_wd; + logic cfg_lp1_cmo_213_we; + logic [2:0] cfg_lp1_cmo_214_qs; + logic [2:0] cfg_lp1_cmo_214_wd; + logic cfg_lp1_cmo_214_we; + logic [2:0] cfg_lp1_cmo_215_qs; + logic [2:0] cfg_lp1_cmo_215_wd; + logic cfg_lp1_cmo_215_we; + logic [2:0] cfg_lp1_cmo_216_qs; + logic [2:0] cfg_lp1_cmo_216_wd; + logic cfg_lp1_cmo_216_we; + logic [2:0] cfg_lp1_cmo_217_qs; + logic [2:0] cfg_lp1_cmo_217_wd; + logic cfg_lp1_cmo_217_we; + logic [2:0] cfg_lp1_cmo_218_qs; + logic [2:0] cfg_lp1_cmo_218_wd; + logic cfg_lp1_cmo_218_we; + logic [2:0] cfg_lp1_cmo_219_qs; + logic [2:0] cfg_lp1_cmo_219_wd; + logic cfg_lp1_cmo_219_we; + logic [2:0] cfg_lp1_cmo_220_qs; + logic [2:0] cfg_lp1_cmo_220_wd; + logic cfg_lp1_cmo_220_we; + logic [2:0] cfg_lp1_cmo_221_qs; + logic [2:0] cfg_lp1_cmo_221_wd; + logic cfg_lp1_cmo_221_we; + logic [2:0] cfg_lp1_cmo_222_qs; + logic [2:0] cfg_lp1_cmo_222_wd; + logic cfg_lp1_cmo_222_we; + logic [2:0] cfg_lp1_cmo_223_qs; + logic [2:0] cfg_lp1_cmo_223_wd; + logic cfg_lp1_cmo_223_we; + logic [2:0] cfg_lp1_cmo_224_qs; + logic [2:0] cfg_lp1_cmo_224_wd; + logic cfg_lp1_cmo_224_we; + logic [2:0] cfg_lp1_cmo_225_qs; + logic [2:0] cfg_lp1_cmo_225_wd; + logic cfg_lp1_cmo_225_we; + logic [2:0] cfg_lp1_cmo_226_qs; + logic [2:0] cfg_lp1_cmo_226_wd; + logic cfg_lp1_cmo_226_we; + logic [2:0] cfg_lp1_cmo_227_qs; + logic [2:0] cfg_lp1_cmo_227_wd; + logic cfg_lp1_cmo_227_we; + logic [2:0] cfg_lp1_cmo_228_qs; + logic [2:0] cfg_lp1_cmo_228_wd; + logic cfg_lp1_cmo_228_we; + logic [2:0] cfg_lp1_cmo_229_qs; + logic [2:0] cfg_lp1_cmo_229_wd; + logic cfg_lp1_cmo_229_we; + logic [2:0] cfg_lp1_cmo_230_qs; + logic [2:0] cfg_lp1_cmo_230_wd; + logic cfg_lp1_cmo_230_we; + logic [2:0] cfg_lp1_cmo_231_qs; + logic [2:0] cfg_lp1_cmo_231_wd; + logic cfg_lp1_cmo_231_we; + logic [2:0] cfg_lp1_cmo_232_qs; + logic [2:0] cfg_lp1_cmo_232_wd; + logic cfg_lp1_cmo_232_we; + logic [2:0] cfg_lp1_cmo_233_qs; + logic [2:0] cfg_lp1_cmo_233_wd; + logic cfg_lp1_cmo_233_we; + logic [2:0] cfg_lp1_cmo_234_qs; + logic [2:0] cfg_lp1_cmo_234_wd; + logic cfg_lp1_cmo_234_we; + logic [2:0] cfg_lp1_cmo_235_qs; + logic [2:0] cfg_lp1_cmo_235_wd; + logic cfg_lp1_cmo_235_we; + logic [2:0] cfg_lp1_cmo_236_qs; + logic [2:0] cfg_lp1_cmo_236_wd; + logic cfg_lp1_cmo_236_we; + logic [2:0] cfg_lp1_cmo_237_qs; + logic [2:0] cfg_lp1_cmo_237_wd; + logic cfg_lp1_cmo_237_we; + logic [2:0] cfg_lp1_cmo_238_qs; + logic [2:0] cfg_lp1_cmo_238_wd; + logic cfg_lp1_cmo_238_we; + logic [2:0] cfg_lp1_cmo_239_qs; + logic [2:0] cfg_lp1_cmo_239_wd; + logic cfg_lp1_cmo_239_we; + logic [2:0] cfg_lp1_cmo_240_qs; + logic [2:0] cfg_lp1_cmo_240_wd; + logic cfg_lp1_cmo_240_we; + logic [2:0] cfg_lp1_cmo_241_qs; + logic [2:0] cfg_lp1_cmo_241_wd; + logic cfg_lp1_cmo_241_we; + logic [2:0] cfg_lp1_cmo_242_qs; + logic [2:0] cfg_lp1_cmo_242_wd; + logic cfg_lp1_cmo_242_we; + logic [2:0] cfg_lp1_cmo_243_qs; + logic [2:0] cfg_lp1_cmo_243_wd; + logic cfg_lp1_cmo_243_we; + logic [2:0] cfg_lp1_cmo_244_qs; + logic [2:0] cfg_lp1_cmo_244_wd; + logic cfg_lp1_cmo_244_we; + logic [2:0] cfg_lp1_cmo_245_qs; + logic [2:0] cfg_lp1_cmo_245_wd; + logic cfg_lp1_cmo_245_we; + logic [2:0] cfg_lp1_cmo_246_qs; + logic [2:0] cfg_lp1_cmo_246_wd; + logic cfg_lp1_cmo_246_we; + logic [2:0] cfg_lp1_cmo_247_qs; + logic [2:0] cfg_lp1_cmo_247_wd; + logic cfg_lp1_cmo_247_we; + logic [2:0] cfg_lp1_cmo_248_qs; + logic [2:0] cfg_lp1_cmo_248_wd; + logic cfg_lp1_cmo_248_we; + logic [2:0] cfg_lp1_cmo_249_qs; + logic [2:0] cfg_lp1_cmo_249_wd; + logic cfg_lp1_cmo_249_we; + logic [2:0] cfg_lp1_cmo_250_qs; + logic [2:0] cfg_lp1_cmo_250_wd; + logic cfg_lp1_cmo_250_we; + logic [2:0] cfg_lp1_cmo_251_qs; + logic [2:0] cfg_lp1_cmo_251_wd; + logic cfg_lp1_cmo_251_we; + logic [2:0] cfg_lp1_cmo_252_qs; + logic [2:0] cfg_lp1_cmo_252_wd; + logic cfg_lp1_cmo_252_we; + logic [2:0] cfg_lp1_cmo_253_qs; + logic [2:0] cfg_lp1_cmo_253_wd; + logic cfg_lp1_cmo_253_we; + logic [2:0] cfg_lp1_cmo_254_qs; + logic [2:0] cfg_lp1_cmo_254_wd; + logic cfg_lp1_cmo_254_we; + logic [2:0] cfg_lp1_cmo_255_qs; + logic [2:0] cfg_lp1_cmo_255_wd; + logic cfg_lp1_cmo_255_we; logic [31:0] cfg_lp1_cmo_addr_0_qs; logic [31:0] cfg_lp1_cmo_addr_0_wd; logic cfg_lp1_cmo_addr_0_we; @@ -499,6 +1075,582 @@ module cachepool_peripheral_reg_top #( logic [31:0] cfg_lp1_cmo_addr_63_qs; logic [31:0] cfg_lp1_cmo_addr_63_wd; logic cfg_lp1_cmo_addr_63_we; + logic [31:0] cfg_lp1_cmo_addr_64_qs; + logic [31:0] cfg_lp1_cmo_addr_64_wd; + logic cfg_lp1_cmo_addr_64_we; + logic [31:0] cfg_lp1_cmo_addr_65_qs; + logic [31:0] cfg_lp1_cmo_addr_65_wd; + logic cfg_lp1_cmo_addr_65_we; + logic [31:0] cfg_lp1_cmo_addr_66_qs; + logic [31:0] cfg_lp1_cmo_addr_66_wd; + logic cfg_lp1_cmo_addr_66_we; + logic [31:0] cfg_lp1_cmo_addr_67_qs; + logic [31:0] cfg_lp1_cmo_addr_67_wd; + logic cfg_lp1_cmo_addr_67_we; + logic [31:0] cfg_lp1_cmo_addr_68_qs; + logic [31:0] cfg_lp1_cmo_addr_68_wd; + logic cfg_lp1_cmo_addr_68_we; + logic [31:0] cfg_lp1_cmo_addr_69_qs; + logic [31:0] cfg_lp1_cmo_addr_69_wd; + logic cfg_lp1_cmo_addr_69_we; + logic [31:0] cfg_lp1_cmo_addr_70_qs; + logic [31:0] cfg_lp1_cmo_addr_70_wd; + logic cfg_lp1_cmo_addr_70_we; + logic [31:0] cfg_lp1_cmo_addr_71_qs; + logic [31:0] cfg_lp1_cmo_addr_71_wd; + logic cfg_lp1_cmo_addr_71_we; + logic [31:0] cfg_lp1_cmo_addr_72_qs; + logic [31:0] cfg_lp1_cmo_addr_72_wd; + logic cfg_lp1_cmo_addr_72_we; + logic [31:0] cfg_lp1_cmo_addr_73_qs; + logic [31:0] cfg_lp1_cmo_addr_73_wd; + logic cfg_lp1_cmo_addr_73_we; + logic [31:0] cfg_lp1_cmo_addr_74_qs; + logic [31:0] cfg_lp1_cmo_addr_74_wd; + logic cfg_lp1_cmo_addr_74_we; + logic [31:0] cfg_lp1_cmo_addr_75_qs; + logic [31:0] cfg_lp1_cmo_addr_75_wd; + logic cfg_lp1_cmo_addr_75_we; + logic [31:0] cfg_lp1_cmo_addr_76_qs; + logic [31:0] cfg_lp1_cmo_addr_76_wd; + logic cfg_lp1_cmo_addr_76_we; + logic [31:0] cfg_lp1_cmo_addr_77_qs; + logic [31:0] cfg_lp1_cmo_addr_77_wd; + logic cfg_lp1_cmo_addr_77_we; + logic [31:0] cfg_lp1_cmo_addr_78_qs; + logic [31:0] cfg_lp1_cmo_addr_78_wd; + logic cfg_lp1_cmo_addr_78_we; + logic [31:0] cfg_lp1_cmo_addr_79_qs; + logic [31:0] cfg_lp1_cmo_addr_79_wd; + logic cfg_lp1_cmo_addr_79_we; + logic [31:0] cfg_lp1_cmo_addr_80_qs; + logic [31:0] cfg_lp1_cmo_addr_80_wd; + logic cfg_lp1_cmo_addr_80_we; + logic [31:0] cfg_lp1_cmo_addr_81_qs; + logic [31:0] cfg_lp1_cmo_addr_81_wd; + logic cfg_lp1_cmo_addr_81_we; + logic [31:0] cfg_lp1_cmo_addr_82_qs; + logic [31:0] cfg_lp1_cmo_addr_82_wd; + logic cfg_lp1_cmo_addr_82_we; + logic [31:0] cfg_lp1_cmo_addr_83_qs; + logic [31:0] cfg_lp1_cmo_addr_83_wd; + logic cfg_lp1_cmo_addr_83_we; + logic [31:0] cfg_lp1_cmo_addr_84_qs; + logic [31:0] cfg_lp1_cmo_addr_84_wd; + logic cfg_lp1_cmo_addr_84_we; + logic [31:0] cfg_lp1_cmo_addr_85_qs; + logic [31:0] cfg_lp1_cmo_addr_85_wd; + logic cfg_lp1_cmo_addr_85_we; + logic [31:0] cfg_lp1_cmo_addr_86_qs; + logic [31:0] cfg_lp1_cmo_addr_86_wd; + logic cfg_lp1_cmo_addr_86_we; + logic [31:0] cfg_lp1_cmo_addr_87_qs; + logic [31:0] cfg_lp1_cmo_addr_87_wd; + logic cfg_lp1_cmo_addr_87_we; + logic [31:0] cfg_lp1_cmo_addr_88_qs; + logic [31:0] cfg_lp1_cmo_addr_88_wd; + logic cfg_lp1_cmo_addr_88_we; + logic [31:0] cfg_lp1_cmo_addr_89_qs; + logic [31:0] cfg_lp1_cmo_addr_89_wd; + logic cfg_lp1_cmo_addr_89_we; + logic [31:0] cfg_lp1_cmo_addr_90_qs; + logic [31:0] cfg_lp1_cmo_addr_90_wd; + logic cfg_lp1_cmo_addr_90_we; + logic [31:0] cfg_lp1_cmo_addr_91_qs; + logic [31:0] cfg_lp1_cmo_addr_91_wd; + logic cfg_lp1_cmo_addr_91_we; + logic [31:0] cfg_lp1_cmo_addr_92_qs; + logic [31:0] cfg_lp1_cmo_addr_92_wd; + logic cfg_lp1_cmo_addr_92_we; + logic [31:0] cfg_lp1_cmo_addr_93_qs; + logic [31:0] cfg_lp1_cmo_addr_93_wd; + logic cfg_lp1_cmo_addr_93_we; + logic [31:0] cfg_lp1_cmo_addr_94_qs; + logic [31:0] cfg_lp1_cmo_addr_94_wd; + logic cfg_lp1_cmo_addr_94_we; + logic [31:0] cfg_lp1_cmo_addr_95_qs; + logic [31:0] cfg_lp1_cmo_addr_95_wd; + logic cfg_lp1_cmo_addr_95_we; + logic [31:0] cfg_lp1_cmo_addr_96_qs; + logic [31:0] cfg_lp1_cmo_addr_96_wd; + logic cfg_lp1_cmo_addr_96_we; + logic [31:0] cfg_lp1_cmo_addr_97_qs; + logic [31:0] cfg_lp1_cmo_addr_97_wd; + logic cfg_lp1_cmo_addr_97_we; + logic [31:0] cfg_lp1_cmo_addr_98_qs; + logic [31:0] cfg_lp1_cmo_addr_98_wd; + logic cfg_lp1_cmo_addr_98_we; + logic [31:0] cfg_lp1_cmo_addr_99_qs; + logic [31:0] cfg_lp1_cmo_addr_99_wd; + logic cfg_lp1_cmo_addr_99_we; + logic [31:0] cfg_lp1_cmo_addr_100_qs; + logic [31:0] cfg_lp1_cmo_addr_100_wd; + logic cfg_lp1_cmo_addr_100_we; + logic [31:0] cfg_lp1_cmo_addr_101_qs; + logic [31:0] cfg_lp1_cmo_addr_101_wd; + logic cfg_lp1_cmo_addr_101_we; + logic [31:0] cfg_lp1_cmo_addr_102_qs; + logic [31:0] cfg_lp1_cmo_addr_102_wd; + logic cfg_lp1_cmo_addr_102_we; + logic [31:0] cfg_lp1_cmo_addr_103_qs; + logic [31:0] cfg_lp1_cmo_addr_103_wd; + logic cfg_lp1_cmo_addr_103_we; + logic [31:0] cfg_lp1_cmo_addr_104_qs; + logic [31:0] cfg_lp1_cmo_addr_104_wd; + logic cfg_lp1_cmo_addr_104_we; + logic [31:0] cfg_lp1_cmo_addr_105_qs; + logic [31:0] cfg_lp1_cmo_addr_105_wd; + logic cfg_lp1_cmo_addr_105_we; + logic [31:0] cfg_lp1_cmo_addr_106_qs; + logic [31:0] cfg_lp1_cmo_addr_106_wd; + logic cfg_lp1_cmo_addr_106_we; + logic [31:0] cfg_lp1_cmo_addr_107_qs; + logic [31:0] cfg_lp1_cmo_addr_107_wd; + logic cfg_lp1_cmo_addr_107_we; + logic [31:0] cfg_lp1_cmo_addr_108_qs; + logic [31:0] cfg_lp1_cmo_addr_108_wd; + logic cfg_lp1_cmo_addr_108_we; + logic [31:0] cfg_lp1_cmo_addr_109_qs; + logic [31:0] cfg_lp1_cmo_addr_109_wd; + logic cfg_lp1_cmo_addr_109_we; + logic [31:0] cfg_lp1_cmo_addr_110_qs; + logic [31:0] cfg_lp1_cmo_addr_110_wd; + logic cfg_lp1_cmo_addr_110_we; + logic [31:0] cfg_lp1_cmo_addr_111_qs; + logic [31:0] cfg_lp1_cmo_addr_111_wd; + logic cfg_lp1_cmo_addr_111_we; + logic [31:0] cfg_lp1_cmo_addr_112_qs; + logic [31:0] cfg_lp1_cmo_addr_112_wd; + logic cfg_lp1_cmo_addr_112_we; + logic [31:0] cfg_lp1_cmo_addr_113_qs; + logic [31:0] cfg_lp1_cmo_addr_113_wd; + logic cfg_lp1_cmo_addr_113_we; + logic [31:0] cfg_lp1_cmo_addr_114_qs; + logic [31:0] cfg_lp1_cmo_addr_114_wd; + logic cfg_lp1_cmo_addr_114_we; + logic [31:0] cfg_lp1_cmo_addr_115_qs; + logic [31:0] cfg_lp1_cmo_addr_115_wd; + logic cfg_lp1_cmo_addr_115_we; + logic [31:0] cfg_lp1_cmo_addr_116_qs; + logic [31:0] cfg_lp1_cmo_addr_116_wd; + logic cfg_lp1_cmo_addr_116_we; + logic [31:0] cfg_lp1_cmo_addr_117_qs; + logic [31:0] cfg_lp1_cmo_addr_117_wd; + logic cfg_lp1_cmo_addr_117_we; + logic [31:0] cfg_lp1_cmo_addr_118_qs; + logic [31:0] cfg_lp1_cmo_addr_118_wd; + logic cfg_lp1_cmo_addr_118_we; + logic [31:0] cfg_lp1_cmo_addr_119_qs; + logic [31:0] cfg_lp1_cmo_addr_119_wd; + logic cfg_lp1_cmo_addr_119_we; + logic [31:0] cfg_lp1_cmo_addr_120_qs; + logic [31:0] cfg_lp1_cmo_addr_120_wd; + logic cfg_lp1_cmo_addr_120_we; + logic [31:0] cfg_lp1_cmo_addr_121_qs; + logic [31:0] cfg_lp1_cmo_addr_121_wd; + logic cfg_lp1_cmo_addr_121_we; + logic [31:0] cfg_lp1_cmo_addr_122_qs; + logic [31:0] cfg_lp1_cmo_addr_122_wd; + logic cfg_lp1_cmo_addr_122_we; + logic [31:0] cfg_lp1_cmo_addr_123_qs; + logic [31:0] cfg_lp1_cmo_addr_123_wd; + logic cfg_lp1_cmo_addr_123_we; + logic [31:0] cfg_lp1_cmo_addr_124_qs; + logic [31:0] cfg_lp1_cmo_addr_124_wd; + logic cfg_lp1_cmo_addr_124_we; + logic [31:0] cfg_lp1_cmo_addr_125_qs; + logic [31:0] cfg_lp1_cmo_addr_125_wd; + logic cfg_lp1_cmo_addr_125_we; + logic [31:0] cfg_lp1_cmo_addr_126_qs; + logic [31:0] cfg_lp1_cmo_addr_126_wd; + logic cfg_lp1_cmo_addr_126_we; + logic [31:0] cfg_lp1_cmo_addr_127_qs; + logic [31:0] cfg_lp1_cmo_addr_127_wd; + logic cfg_lp1_cmo_addr_127_we; + logic [31:0] cfg_lp1_cmo_addr_128_qs; + logic [31:0] cfg_lp1_cmo_addr_128_wd; + logic cfg_lp1_cmo_addr_128_we; + logic [31:0] cfg_lp1_cmo_addr_129_qs; + logic [31:0] cfg_lp1_cmo_addr_129_wd; + logic cfg_lp1_cmo_addr_129_we; + logic [31:0] cfg_lp1_cmo_addr_130_qs; + logic [31:0] cfg_lp1_cmo_addr_130_wd; + logic cfg_lp1_cmo_addr_130_we; + logic [31:0] cfg_lp1_cmo_addr_131_qs; + logic [31:0] cfg_lp1_cmo_addr_131_wd; + logic cfg_lp1_cmo_addr_131_we; + logic [31:0] cfg_lp1_cmo_addr_132_qs; + logic [31:0] cfg_lp1_cmo_addr_132_wd; + logic cfg_lp1_cmo_addr_132_we; + logic [31:0] cfg_lp1_cmo_addr_133_qs; + logic [31:0] cfg_lp1_cmo_addr_133_wd; + logic cfg_lp1_cmo_addr_133_we; + logic [31:0] cfg_lp1_cmo_addr_134_qs; + logic [31:0] cfg_lp1_cmo_addr_134_wd; + logic cfg_lp1_cmo_addr_134_we; + logic [31:0] cfg_lp1_cmo_addr_135_qs; + logic [31:0] cfg_lp1_cmo_addr_135_wd; + logic cfg_lp1_cmo_addr_135_we; + logic [31:0] cfg_lp1_cmo_addr_136_qs; + logic [31:0] cfg_lp1_cmo_addr_136_wd; + logic cfg_lp1_cmo_addr_136_we; + logic [31:0] cfg_lp1_cmo_addr_137_qs; + logic [31:0] cfg_lp1_cmo_addr_137_wd; + logic cfg_lp1_cmo_addr_137_we; + logic [31:0] cfg_lp1_cmo_addr_138_qs; + logic [31:0] cfg_lp1_cmo_addr_138_wd; + logic cfg_lp1_cmo_addr_138_we; + logic [31:0] cfg_lp1_cmo_addr_139_qs; + logic [31:0] cfg_lp1_cmo_addr_139_wd; + logic cfg_lp1_cmo_addr_139_we; + logic [31:0] cfg_lp1_cmo_addr_140_qs; + logic [31:0] cfg_lp1_cmo_addr_140_wd; + logic cfg_lp1_cmo_addr_140_we; + logic [31:0] cfg_lp1_cmo_addr_141_qs; + logic [31:0] cfg_lp1_cmo_addr_141_wd; + logic cfg_lp1_cmo_addr_141_we; + logic [31:0] cfg_lp1_cmo_addr_142_qs; + logic [31:0] cfg_lp1_cmo_addr_142_wd; + logic cfg_lp1_cmo_addr_142_we; + logic [31:0] cfg_lp1_cmo_addr_143_qs; + logic [31:0] cfg_lp1_cmo_addr_143_wd; + logic cfg_lp1_cmo_addr_143_we; + logic [31:0] cfg_lp1_cmo_addr_144_qs; + logic [31:0] cfg_lp1_cmo_addr_144_wd; + logic cfg_lp1_cmo_addr_144_we; + logic [31:0] cfg_lp1_cmo_addr_145_qs; + logic [31:0] cfg_lp1_cmo_addr_145_wd; + logic cfg_lp1_cmo_addr_145_we; + logic [31:0] cfg_lp1_cmo_addr_146_qs; + logic [31:0] cfg_lp1_cmo_addr_146_wd; + logic cfg_lp1_cmo_addr_146_we; + logic [31:0] cfg_lp1_cmo_addr_147_qs; + logic [31:0] cfg_lp1_cmo_addr_147_wd; + logic cfg_lp1_cmo_addr_147_we; + logic [31:0] cfg_lp1_cmo_addr_148_qs; + logic [31:0] cfg_lp1_cmo_addr_148_wd; + logic cfg_lp1_cmo_addr_148_we; + logic [31:0] cfg_lp1_cmo_addr_149_qs; + logic [31:0] cfg_lp1_cmo_addr_149_wd; + logic cfg_lp1_cmo_addr_149_we; + logic [31:0] cfg_lp1_cmo_addr_150_qs; + logic [31:0] cfg_lp1_cmo_addr_150_wd; + logic cfg_lp1_cmo_addr_150_we; + logic [31:0] cfg_lp1_cmo_addr_151_qs; + logic [31:0] cfg_lp1_cmo_addr_151_wd; + logic cfg_lp1_cmo_addr_151_we; + logic [31:0] cfg_lp1_cmo_addr_152_qs; + logic [31:0] cfg_lp1_cmo_addr_152_wd; + logic cfg_lp1_cmo_addr_152_we; + logic [31:0] cfg_lp1_cmo_addr_153_qs; + logic [31:0] cfg_lp1_cmo_addr_153_wd; + logic cfg_lp1_cmo_addr_153_we; + logic [31:0] cfg_lp1_cmo_addr_154_qs; + logic [31:0] cfg_lp1_cmo_addr_154_wd; + logic cfg_lp1_cmo_addr_154_we; + logic [31:0] cfg_lp1_cmo_addr_155_qs; + logic [31:0] cfg_lp1_cmo_addr_155_wd; + logic cfg_lp1_cmo_addr_155_we; + logic [31:0] cfg_lp1_cmo_addr_156_qs; + logic [31:0] cfg_lp1_cmo_addr_156_wd; + logic cfg_lp1_cmo_addr_156_we; + logic [31:0] cfg_lp1_cmo_addr_157_qs; + logic [31:0] cfg_lp1_cmo_addr_157_wd; + logic cfg_lp1_cmo_addr_157_we; + logic [31:0] cfg_lp1_cmo_addr_158_qs; + logic [31:0] cfg_lp1_cmo_addr_158_wd; + logic cfg_lp1_cmo_addr_158_we; + logic [31:0] cfg_lp1_cmo_addr_159_qs; + logic [31:0] cfg_lp1_cmo_addr_159_wd; + logic cfg_lp1_cmo_addr_159_we; + logic [31:0] cfg_lp1_cmo_addr_160_qs; + logic [31:0] cfg_lp1_cmo_addr_160_wd; + logic cfg_lp1_cmo_addr_160_we; + logic [31:0] cfg_lp1_cmo_addr_161_qs; + logic [31:0] cfg_lp1_cmo_addr_161_wd; + logic cfg_lp1_cmo_addr_161_we; + logic [31:0] cfg_lp1_cmo_addr_162_qs; + logic [31:0] cfg_lp1_cmo_addr_162_wd; + logic cfg_lp1_cmo_addr_162_we; + logic [31:0] cfg_lp1_cmo_addr_163_qs; + logic [31:0] cfg_lp1_cmo_addr_163_wd; + logic cfg_lp1_cmo_addr_163_we; + logic [31:0] cfg_lp1_cmo_addr_164_qs; + logic [31:0] cfg_lp1_cmo_addr_164_wd; + logic cfg_lp1_cmo_addr_164_we; + logic [31:0] cfg_lp1_cmo_addr_165_qs; + logic [31:0] cfg_lp1_cmo_addr_165_wd; + logic cfg_lp1_cmo_addr_165_we; + logic [31:0] cfg_lp1_cmo_addr_166_qs; + logic [31:0] cfg_lp1_cmo_addr_166_wd; + logic cfg_lp1_cmo_addr_166_we; + logic [31:0] cfg_lp1_cmo_addr_167_qs; + logic [31:0] cfg_lp1_cmo_addr_167_wd; + logic cfg_lp1_cmo_addr_167_we; + logic [31:0] cfg_lp1_cmo_addr_168_qs; + logic [31:0] cfg_lp1_cmo_addr_168_wd; + logic cfg_lp1_cmo_addr_168_we; + logic [31:0] cfg_lp1_cmo_addr_169_qs; + logic [31:0] cfg_lp1_cmo_addr_169_wd; + logic cfg_lp1_cmo_addr_169_we; + logic [31:0] cfg_lp1_cmo_addr_170_qs; + logic [31:0] cfg_lp1_cmo_addr_170_wd; + logic cfg_lp1_cmo_addr_170_we; + logic [31:0] cfg_lp1_cmo_addr_171_qs; + logic [31:0] cfg_lp1_cmo_addr_171_wd; + logic cfg_lp1_cmo_addr_171_we; + logic [31:0] cfg_lp1_cmo_addr_172_qs; + logic [31:0] cfg_lp1_cmo_addr_172_wd; + logic cfg_lp1_cmo_addr_172_we; + logic [31:0] cfg_lp1_cmo_addr_173_qs; + logic [31:0] cfg_lp1_cmo_addr_173_wd; + logic cfg_lp1_cmo_addr_173_we; + logic [31:0] cfg_lp1_cmo_addr_174_qs; + logic [31:0] cfg_lp1_cmo_addr_174_wd; + logic cfg_lp1_cmo_addr_174_we; + logic [31:0] cfg_lp1_cmo_addr_175_qs; + logic [31:0] cfg_lp1_cmo_addr_175_wd; + logic cfg_lp1_cmo_addr_175_we; + logic [31:0] cfg_lp1_cmo_addr_176_qs; + logic [31:0] cfg_lp1_cmo_addr_176_wd; + logic cfg_lp1_cmo_addr_176_we; + logic [31:0] cfg_lp1_cmo_addr_177_qs; + logic [31:0] cfg_lp1_cmo_addr_177_wd; + logic cfg_lp1_cmo_addr_177_we; + logic [31:0] cfg_lp1_cmo_addr_178_qs; + logic [31:0] cfg_lp1_cmo_addr_178_wd; + logic cfg_lp1_cmo_addr_178_we; + logic [31:0] cfg_lp1_cmo_addr_179_qs; + logic [31:0] cfg_lp1_cmo_addr_179_wd; + logic cfg_lp1_cmo_addr_179_we; + logic [31:0] cfg_lp1_cmo_addr_180_qs; + logic [31:0] cfg_lp1_cmo_addr_180_wd; + logic cfg_lp1_cmo_addr_180_we; + logic [31:0] cfg_lp1_cmo_addr_181_qs; + logic [31:0] cfg_lp1_cmo_addr_181_wd; + logic cfg_lp1_cmo_addr_181_we; + logic [31:0] cfg_lp1_cmo_addr_182_qs; + logic [31:0] cfg_lp1_cmo_addr_182_wd; + logic cfg_lp1_cmo_addr_182_we; + logic [31:0] cfg_lp1_cmo_addr_183_qs; + logic [31:0] cfg_lp1_cmo_addr_183_wd; + logic cfg_lp1_cmo_addr_183_we; + logic [31:0] cfg_lp1_cmo_addr_184_qs; + logic [31:0] cfg_lp1_cmo_addr_184_wd; + logic cfg_lp1_cmo_addr_184_we; + logic [31:0] cfg_lp1_cmo_addr_185_qs; + logic [31:0] cfg_lp1_cmo_addr_185_wd; + logic cfg_lp1_cmo_addr_185_we; + logic [31:0] cfg_lp1_cmo_addr_186_qs; + logic [31:0] cfg_lp1_cmo_addr_186_wd; + logic cfg_lp1_cmo_addr_186_we; + logic [31:0] cfg_lp1_cmo_addr_187_qs; + logic [31:0] cfg_lp1_cmo_addr_187_wd; + logic cfg_lp1_cmo_addr_187_we; + logic [31:0] cfg_lp1_cmo_addr_188_qs; + logic [31:0] cfg_lp1_cmo_addr_188_wd; + logic cfg_lp1_cmo_addr_188_we; + logic [31:0] cfg_lp1_cmo_addr_189_qs; + logic [31:0] cfg_lp1_cmo_addr_189_wd; + logic cfg_lp1_cmo_addr_189_we; + logic [31:0] cfg_lp1_cmo_addr_190_qs; + logic [31:0] cfg_lp1_cmo_addr_190_wd; + logic cfg_lp1_cmo_addr_190_we; + logic [31:0] cfg_lp1_cmo_addr_191_qs; + logic [31:0] cfg_lp1_cmo_addr_191_wd; + logic cfg_lp1_cmo_addr_191_we; + logic [31:0] cfg_lp1_cmo_addr_192_qs; + logic [31:0] cfg_lp1_cmo_addr_192_wd; + logic cfg_lp1_cmo_addr_192_we; + logic [31:0] cfg_lp1_cmo_addr_193_qs; + logic [31:0] cfg_lp1_cmo_addr_193_wd; + logic cfg_lp1_cmo_addr_193_we; + logic [31:0] cfg_lp1_cmo_addr_194_qs; + logic [31:0] cfg_lp1_cmo_addr_194_wd; + logic cfg_lp1_cmo_addr_194_we; + logic [31:0] cfg_lp1_cmo_addr_195_qs; + logic [31:0] cfg_lp1_cmo_addr_195_wd; + logic cfg_lp1_cmo_addr_195_we; + logic [31:0] cfg_lp1_cmo_addr_196_qs; + logic [31:0] cfg_lp1_cmo_addr_196_wd; + logic cfg_lp1_cmo_addr_196_we; + logic [31:0] cfg_lp1_cmo_addr_197_qs; + logic [31:0] cfg_lp1_cmo_addr_197_wd; + logic cfg_lp1_cmo_addr_197_we; + logic [31:0] cfg_lp1_cmo_addr_198_qs; + logic [31:0] cfg_lp1_cmo_addr_198_wd; + logic cfg_lp1_cmo_addr_198_we; + logic [31:0] cfg_lp1_cmo_addr_199_qs; + logic [31:0] cfg_lp1_cmo_addr_199_wd; + logic cfg_lp1_cmo_addr_199_we; + logic [31:0] cfg_lp1_cmo_addr_200_qs; + logic [31:0] cfg_lp1_cmo_addr_200_wd; + logic cfg_lp1_cmo_addr_200_we; + logic [31:0] cfg_lp1_cmo_addr_201_qs; + logic [31:0] cfg_lp1_cmo_addr_201_wd; + logic cfg_lp1_cmo_addr_201_we; + logic [31:0] cfg_lp1_cmo_addr_202_qs; + logic [31:0] cfg_lp1_cmo_addr_202_wd; + logic cfg_lp1_cmo_addr_202_we; + logic [31:0] cfg_lp1_cmo_addr_203_qs; + logic [31:0] cfg_lp1_cmo_addr_203_wd; + logic cfg_lp1_cmo_addr_203_we; + logic [31:0] cfg_lp1_cmo_addr_204_qs; + logic [31:0] cfg_lp1_cmo_addr_204_wd; + logic cfg_lp1_cmo_addr_204_we; + logic [31:0] cfg_lp1_cmo_addr_205_qs; + logic [31:0] cfg_lp1_cmo_addr_205_wd; + logic cfg_lp1_cmo_addr_205_we; + logic [31:0] cfg_lp1_cmo_addr_206_qs; + logic [31:0] cfg_lp1_cmo_addr_206_wd; + logic cfg_lp1_cmo_addr_206_we; + logic [31:0] cfg_lp1_cmo_addr_207_qs; + logic [31:0] cfg_lp1_cmo_addr_207_wd; + logic cfg_lp1_cmo_addr_207_we; + logic [31:0] cfg_lp1_cmo_addr_208_qs; + logic [31:0] cfg_lp1_cmo_addr_208_wd; + logic cfg_lp1_cmo_addr_208_we; + logic [31:0] cfg_lp1_cmo_addr_209_qs; + logic [31:0] cfg_lp1_cmo_addr_209_wd; + logic cfg_lp1_cmo_addr_209_we; + logic [31:0] cfg_lp1_cmo_addr_210_qs; + logic [31:0] cfg_lp1_cmo_addr_210_wd; + logic cfg_lp1_cmo_addr_210_we; + logic [31:0] cfg_lp1_cmo_addr_211_qs; + logic [31:0] cfg_lp1_cmo_addr_211_wd; + logic cfg_lp1_cmo_addr_211_we; + logic [31:0] cfg_lp1_cmo_addr_212_qs; + logic [31:0] cfg_lp1_cmo_addr_212_wd; + logic cfg_lp1_cmo_addr_212_we; + logic [31:0] cfg_lp1_cmo_addr_213_qs; + logic [31:0] cfg_lp1_cmo_addr_213_wd; + logic cfg_lp1_cmo_addr_213_we; + logic [31:0] cfg_lp1_cmo_addr_214_qs; + logic [31:0] cfg_lp1_cmo_addr_214_wd; + logic cfg_lp1_cmo_addr_214_we; + logic [31:0] cfg_lp1_cmo_addr_215_qs; + logic [31:0] cfg_lp1_cmo_addr_215_wd; + logic cfg_lp1_cmo_addr_215_we; + logic [31:0] cfg_lp1_cmo_addr_216_qs; + logic [31:0] cfg_lp1_cmo_addr_216_wd; + logic cfg_lp1_cmo_addr_216_we; + logic [31:0] cfg_lp1_cmo_addr_217_qs; + logic [31:0] cfg_lp1_cmo_addr_217_wd; + logic cfg_lp1_cmo_addr_217_we; + logic [31:0] cfg_lp1_cmo_addr_218_qs; + logic [31:0] cfg_lp1_cmo_addr_218_wd; + logic cfg_lp1_cmo_addr_218_we; + logic [31:0] cfg_lp1_cmo_addr_219_qs; + logic [31:0] cfg_lp1_cmo_addr_219_wd; + logic cfg_lp1_cmo_addr_219_we; + logic [31:0] cfg_lp1_cmo_addr_220_qs; + logic [31:0] cfg_lp1_cmo_addr_220_wd; + logic cfg_lp1_cmo_addr_220_we; + logic [31:0] cfg_lp1_cmo_addr_221_qs; + logic [31:0] cfg_lp1_cmo_addr_221_wd; + logic cfg_lp1_cmo_addr_221_we; + logic [31:0] cfg_lp1_cmo_addr_222_qs; + logic [31:0] cfg_lp1_cmo_addr_222_wd; + logic cfg_lp1_cmo_addr_222_we; + logic [31:0] cfg_lp1_cmo_addr_223_qs; + logic [31:0] cfg_lp1_cmo_addr_223_wd; + logic cfg_lp1_cmo_addr_223_we; + logic [31:0] cfg_lp1_cmo_addr_224_qs; + logic [31:0] cfg_lp1_cmo_addr_224_wd; + logic cfg_lp1_cmo_addr_224_we; + logic [31:0] cfg_lp1_cmo_addr_225_qs; + logic [31:0] cfg_lp1_cmo_addr_225_wd; + logic cfg_lp1_cmo_addr_225_we; + logic [31:0] cfg_lp1_cmo_addr_226_qs; + logic [31:0] cfg_lp1_cmo_addr_226_wd; + logic cfg_lp1_cmo_addr_226_we; + logic [31:0] cfg_lp1_cmo_addr_227_qs; + logic [31:0] cfg_lp1_cmo_addr_227_wd; + logic cfg_lp1_cmo_addr_227_we; + logic [31:0] cfg_lp1_cmo_addr_228_qs; + logic [31:0] cfg_lp1_cmo_addr_228_wd; + logic cfg_lp1_cmo_addr_228_we; + logic [31:0] cfg_lp1_cmo_addr_229_qs; + logic [31:0] cfg_lp1_cmo_addr_229_wd; + logic cfg_lp1_cmo_addr_229_we; + logic [31:0] cfg_lp1_cmo_addr_230_qs; + logic [31:0] cfg_lp1_cmo_addr_230_wd; + logic cfg_lp1_cmo_addr_230_we; + logic [31:0] cfg_lp1_cmo_addr_231_qs; + logic [31:0] cfg_lp1_cmo_addr_231_wd; + logic cfg_lp1_cmo_addr_231_we; + logic [31:0] cfg_lp1_cmo_addr_232_qs; + logic [31:0] cfg_lp1_cmo_addr_232_wd; + logic cfg_lp1_cmo_addr_232_we; + logic [31:0] cfg_lp1_cmo_addr_233_qs; + logic [31:0] cfg_lp1_cmo_addr_233_wd; + logic cfg_lp1_cmo_addr_233_we; + logic [31:0] cfg_lp1_cmo_addr_234_qs; + logic [31:0] cfg_lp1_cmo_addr_234_wd; + logic cfg_lp1_cmo_addr_234_we; + logic [31:0] cfg_lp1_cmo_addr_235_qs; + logic [31:0] cfg_lp1_cmo_addr_235_wd; + logic cfg_lp1_cmo_addr_235_we; + logic [31:0] cfg_lp1_cmo_addr_236_qs; + logic [31:0] cfg_lp1_cmo_addr_236_wd; + logic cfg_lp1_cmo_addr_236_we; + logic [31:0] cfg_lp1_cmo_addr_237_qs; + logic [31:0] cfg_lp1_cmo_addr_237_wd; + logic cfg_lp1_cmo_addr_237_we; + logic [31:0] cfg_lp1_cmo_addr_238_qs; + logic [31:0] cfg_lp1_cmo_addr_238_wd; + logic cfg_lp1_cmo_addr_238_we; + logic [31:0] cfg_lp1_cmo_addr_239_qs; + logic [31:0] cfg_lp1_cmo_addr_239_wd; + logic cfg_lp1_cmo_addr_239_we; + logic [31:0] cfg_lp1_cmo_addr_240_qs; + logic [31:0] cfg_lp1_cmo_addr_240_wd; + logic cfg_lp1_cmo_addr_240_we; + logic [31:0] cfg_lp1_cmo_addr_241_qs; + logic [31:0] cfg_lp1_cmo_addr_241_wd; + logic cfg_lp1_cmo_addr_241_we; + logic [31:0] cfg_lp1_cmo_addr_242_qs; + logic [31:0] cfg_lp1_cmo_addr_242_wd; + logic cfg_lp1_cmo_addr_242_we; + logic [31:0] cfg_lp1_cmo_addr_243_qs; + logic [31:0] cfg_lp1_cmo_addr_243_wd; + logic cfg_lp1_cmo_addr_243_we; + logic [31:0] cfg_lp1_cmo_addr_244_qs; + logic [31:0] cfg_lp1_cmo_addr_244_wd; + logic cfg_lp1_cmo_addr_244_we; + logic [31:0] cfg_lp1_cmo_addr_245_qs; + logic [31:0] cfg_lp1_cmo_addr_245_wd; + logic cfg_lp1_cmo_addr_245_we; + logic [31:0] cfg_lp1_cmo_addr_246_qs; + logic [31:0] cfg_lp1_cmo_addr_246_wd; + logic cfg_lp1_cmo_addr_246_we; + logic [31:0] cfg_lp1_cmo_addr_247_qs; + logic [31:0] cfg_lp1_cmo_addr_247_wd; + logic cfg_lp1_cmo_addr_247_we; + logic [31:0] cfg_lp1_cmo_addr_248_qs; + logic [31:0] cfg_lp1_cmo_addr_248_wd; + logic cfg_lp1_cmo_addr_248_we; + logic [31:0] cfg_lp1_cmo_addr_249_qs; + logic [31:0] cfg_lp1_cmo_addr_249_wd; + logic cfg_lp1_cmo_addr_249_we; + logic [31:0] cfg_lp1_cmo_addr_250_qs; + logic [31:0] cfg_lp1_cmo_addr_250_wd; + logic cfg_lp1_cmo_addr_250_we; + logic [31:0] cfg_lp1_cmo_addr_251_qs; + logic [31:0] cfg_lp1_cmo_addr_251_wd; + logic cfg_lp1_cmo_addr_251_we; + logic [31:0] cfg_lp1_cmo_addr_252_qs; + logic [31:0] cfg_lp1_cmo_addr_252_wd; + logic cfg_lp1_cmo_addr_252_we; + logic [31:0] cfg_lp1_cmo_addr_253_qs; + logic [31:0] cfg_lp1_cmo_addr_253_wd; + logic cfg_lp1_cmo_addr_253_we; + logic [31:0] cfg_lp1_cmo_addr_254_qs; + logic [31:0] cfg_lp1_cmo_addr_254_wd; + logic cfg_lp1_cmo_addr_254_we; + logic [31:0] cfg_lp1_cmo_addr_255_qs; + logic [31:0] cfg_lp1_cmo_addr_255_wd; + logic cfg_lp1_cmo_addr_255_we; logic lp1_cmo_commit_0_qs; logic lp1_cmo_commit_0_wd; logic lp1_cmo_commit_0_we; @@ -691,6 +1843,582 @@ module cachepool_peripheral_reg_top #( logic lp1_cmo_commit_63_qs; logic lp1_cmo_commit_63_wd; logic lp1_cmo_commit_63_we; + logic lp1_cmo_commit_64_qs; + logic lp1_cmo_commit_64_wd; + logic lp1_cmo_commit_64_we; + logic lp1_cmo_commit_65_qs; + logic lp1_cmo_commit_65_wd; + logic lp1_cmo_commit_65_we; + logic lp1_cmo_commit_66_qs; + logic lp1_cmo_commit_66_wd; + logic lp1_cmo_commit_66_we; + logic lp1_cmo_commit_67_qs; + logic lp1_cmo_commit_67_wd; + logic lp1_cmo_commit_67_we; + logic lp1_cmo_commit_68_qs; + logic lp1_cmo_commit_68_wd; + logic lp1_cmo_commit_68_we; + logic lp1_cmo_commit_69_qs; + logic lp1_cmo_commit_69_wd; + logic lp1_cmo_commit_69_we; + logic lp1_cmo_commit_70_qs; + logic lp1_cmo_commit_70_wd; + logic lp1_cmo_commit_70_we; + logic lp1_cmo_commit_71_qs; + logic lp1_cmo_commit_71_wd; + logic lp1_cmo_commit_71_we; + logic lp1_cmo_commit_72_qs; + logic lp1_cmo_commit_72_wd; + logic lp1_cmo_commit_72_we; + logic lp1_cmo_commit_73_qs; + logic lp1_cmo_commit_73_wd; + logic lp1_cmo_commit_73_we; + logic lp1_cmo_commit_74_qs; + logic lp1_cmo_commit_74_wd; + logic lp1_cmo_commit_74_we; + logic lp1_cmo_commit_75_qs; + logic lp1_cmo_commit_75_wd; + logic lp1_cmo_commit_75_we; + logic lp1_cmo_commit_76_qs; + logic lp1_cmo_commit_76_wd; + logic lp1_cmo_commit_76_we; + logic lp1_cmo_commit_77_qs; + logic lp1_cmo_commit_77_wd; + logic lp1_cmo_commit_77_we; + logic lp1_cmo_commit_78_qs; + logic lp1_cmo_commit_78_wd; + logic lp1_cmo_commit_78_we; + logic lp1_cmo_commit_79_qs; + logic lp1_cmo_commit_79_wd; + logic lp1_cmo_commit_79_we; + logic lp1_cmo_commit_80_qs; + logic lp1_cmo_commit_80_wd; + logic lp1_cmo_commit_80_we; + logic lp1_cmo_commit_81_qs; + logic lp1_cmo_commit_81_wd; + logic lp1_cmo_commit_81_we; + logic lp1_cmo_commit_82_qs; + logic lp1_cmo_commit_82_wd; + logic lp1_cmo_commit_82_we; + logic lp1_cmo_commit_83_qs; + logic lp1_cmo_commit_83_wd; + logic lp1_cmo_commit_83_we; + logic lp1_cmo_commit_84_qs; + logic lp1_cmo_commit_84_wd; + logic lp1_cmo_commit_84_we; + logic lp1_cmo_commit_85_qs; + logic lp1_cmo_commit_85_wd; + logic lp1_cmo_commit_85_we; + logic lp1_cmo_commit_86_qs; + logic lp1_cmo_commit_86_wd; + logic lp1_cmo_commit_86_we; + logic lp1_cmo_commit_87_qs; + logic lp1_cmo_commit_87_wd; + logic lp1_cmo_commit_87_we; + logic lp1_cmo_commit_88_qs; + logic lp1_cmo_commit_88_wd; + logic lp1_cmo_commit_88_we; + logic lp1_cmo_commit_89_qs; + logic lp1_cmo_commit_89_wd; + logic lp1_cmo_commit_89_we; + logic lp1_cmo_commit_90_qs; + logic lp1_cmo_commit_90_wd; + logic lp1_cmo_commit_90_we; + logic lp1_cmo_commit_91_qs; + logic lp1_cmo_commit_91_wd; + logic lp1_cmo_commit_91_we; + logic lp1_cmo_commit_92_qs; + logic lp1_cmo_commit_92_wd; + logic lp1_cmo_commit_92_we; + logic lp1_cmo_commit_93_qs; + logic lp1_cmo_commit_93_wd; + logic lp1_cmo_commit_93_we; + logic lp1_cmo_commit_94_qs; + logic lp1_cmo_commit_94_wd; + logic lp1_cmo_commit_94_we; + logic lp1_cmo_commit_95_qs; + logic lp1_cmo_commit_95_wd; + logic lp1_cmo_commit_95_we; + logic lp1_cmo_commit_96_qs; + logic lp1_cmo_commit_96_wd; + logic lp1_cmo_commit_96_we; + logic lp1_cmo_commit_97_qs; + logic lp1_cmo_commit_97_wd; + logic lp1_cmo_commit_97_we; + logic lp1_cmo_commit_98_qs; + logic lp1_cmo_commit_98_wd; + logic lp1_cmo_commit_98_we; + logic lp1_cmo_commit_99_qs; + logic lp1_cmo_commit_99_wd; + logic lp1_cmo_commit_99_we; + logic lp1_cmo_commit_100_qs; + logic lp1_cmo_commit_100_wd; + logic lp1_cmo_commit_100_we; + logic lp1_cmo_commit_101_qs; + logic lp1_cmo_commit_101_wd; + logic lp1_cmo_commit_101_we; + logic lp1_cmo_commit_102_qs; + logic lp1_cmo_commit_102_wd; + logic lp1_cmo_commit_102_we; + logic lp1_cmo_commit_103_qs; + logic lp1_cmo_commit_103_wd; + logic lp1_cmo_commit_103_we; + logic lp1_cmo_commit_104_qs; + logic lp1_cmo_commit_104_wd; + logic lp1_cmo_commit_104_we; + logic lp1_cmo_commit_105_qs; + logic lp1_cmo_commit_105_wd; + logic lp1_cmo_commit_105_we; + logic lp1_cmo_commit_106_qs; + logic lp1_cmo_commit_106_wd; + logic lp1_cmo_commit_106_we; + logic lp1_cmo_commit_107_qs; + logic lp1_cmo_commit_107_wd; + logic lp1_cmo_commit_107_we; + logic lp1_cmo_commit_108_qs; + logic lp1_cmo_commit_108_wd; + logic lp1_cmo_commit_108_we; + logic lp1_cmo_commit_109_qs; + logic lp1_cmo_commit_109_wd; + logic lp1_cmo_commit_109_we; + logic lp1_cmo_commit_110_qs; + logic lp1_cmo_commit_110_wd; + logic lp1_cmo_commit_110_we; + logic lp1_cmo_commit_111_qs; + logic lp1_cmo_commit_111_wd; + logic lp1_cmo_commit_111_we; + logic lp1_cmo_commit_112_qs; + logic lp1_cmo_commit_112_wd; + logic lp1_cmo_commit_112_we; + logic lp1_cmo_commit_113_qs; + logic lp1_cmo_commit_113_wd; + logic lp1_cmo_commit_113_we; + logic lp1_cmo_commit_114_qs; + logic lp1_cmo_commit_114_wd; + logic lp1_cmo_commit_114_we; + logic lp1_cmo_commit_115_qs; + logic lp1_cmo_commit_115_wd; + logic lp1_cmo_commit_115_we; + logic lp1_cmo_commit_116_qs; + logic lp1_cmo_commit_116_wd; + logic lp1_cmo_commit_116_we; + logic lp1_cmo_commit_117_qs; + logic lp1_cmo_commit_117_wd; + logic lp1_cmo_commit_117_we; + logic lp1_cmo_commit_118_qs; + logic lp1_cmo_commit_118_wd; + logic lp1_cmo_commit_118_we; + logic lp1_cmo_commit_119_qs; + logic lp1_cmo_commit_119_wd; + logic lp1_cmo_commit_119_we; + logic lp1_cmo_commit_120_qs; + logic lp1_cmo_commit_120_wd; + logic lp1_cmo_commit_120_we; + logic lp1_cmo_commit_121_qs; + logic lp1_cmo_commit_121_wd; + logic lp1_cmo_commit_121_we; + logic lp1_cmo_commit_122_qs; + logic lp1_cmo_commit_122_wd; + logic lp1_cmo_commit_122_we; + logic lp1_cmo_commit_123_qs; + logic lp1_cmo_commit_123_wd; + logic lp1_cmo_commit_123_we; + logic lp1_cmo_commit_124_qs; + logic lp1_cmo_commit_124_wd; + logic lp1_cmo_commit_124_we; + logic lp1_cmo_commit_125_qs; + logic lp1_cmo_commit_125_wd; + logic lp1_cmo_commit_125_we; + logic lp1_cmo_commit_126_qs; + logic lp1_cmo_commit_126_wd; + logic lp1_cmo_commit_126_we; + logic lp1_cmo_commit_127_qs; + logic lp1_cmo_commit_127_wd; + logic lp1_cmo_commit_127_we; + logic lp1_cmo_commit_128_qs; + logic lp1_cmo_commit_128_wd; + logic lp1_cmo_commit_128_we; + logic lp1_cmo_commit_129_qs; + logic lp1_cmo_commit_129_wd; + logic lp1_cmo_commit_129_we; + logic lp1_cmo_commit_130_qs; + logic lp1_cmo_commit_130_wd; + logic lp1_cmo_commit_130_we; + logic lp1_cmo_commit_131_qs; + logic lp1_cmo_commit_131_wd; + logic lp1_cmo_commit_131_we; + logic lp1_cmo_commit_132_qs; + logic lp1_cmo_commit_132_wd; + logic lp1_cmo_commit_132_we; + logic lp1_cmo_commit_133_qs; + logic lp1_cmo_commit_133_wd; + logic lp1_cmo_commit_133_we; + logic lp1_cmo_commit_134_qs; + logic lp1_cmo_commit_134_wd; + logic lp1_cmo_commit_134_we; + logic lp1_cmo_commit_135_qs; + logic lp1_cmo_commit_135_wd; + logic lp1_cmo_commit_135_we; + logic lp1_cmo_commit_136_qs; + logic lp1_cmo_commit_136_wd; + logic lp1_cmo_commit_136_we; + logic lp1_cmo_commit_137_qs; + logic lp1_cmo_commit_137_wd; + logic lp1_cmo_commit_137_we; + logic lp1_cmo_commit_138_qs; + logic lp1_cmo_commit_138_wd; + logic lp1_cmo_commit_138_we; + logic lp1_cmo_commit_139_qs; + logic lp1_cmo_commit_139_wd; + logic lp1_cmo_commit_139_we; + logic lp1_cmo_commit_140_qs; + logic lp1_cmo_commit_140_wd; + logic lp1_cmo_commit_140_we; + logic lp1_cmo_commit_141_qs; + logic lp1_cmo_commit_141_wd; + logic lp1_cmo_commit_141_we; + logic lp1_cmo_commit_142_qs; + logic lp1_cmo_commit_142_wd; + logic lp1_cmo_commit_142_we; + logic lp1_cmo_commit_143_qs; + logic lp1_cmo_commit_143_wd; + logic lp1_cmo_commit_143_we; + logic lp1_cmo_commit_144_qs; + logic lp1_cmo_commit_144_wd; + logic lp1_cmo_commit_144_we; + logic lp1_cmo_commit_145_qs; + logic lp1_cmo_commit_145_wd; + logic lp1_cmo_commit_145_we; + logic lp1_cmo_commit_146_qs; + logic lp1_cmo_commit_146_wd; + logic lp1_cmo_commit_146_we; + logic lp1_cmo_commit_147_qs; + logic lp1_cmo_commit_147_wd; + logic lp1_cmo_commit_147_we; + logic lp1_cmo_commit_148_qs; + logic lp1_cmo_commit_148_wd; + logic lp1_cmo_commit_148_we; + logic lp1_cmo_commit_149_qs; + logic lp1_cmo_commit_149_wd; + logic lp1_cmo_commit_149_we; + logic lp1_cmo_commit_150_qs; + logic lp1_cmo_commit_150_wd; + logic lp1_cmo_commit_150_we; + logic lp1_cmo_commit_151_qs; + logic lp1_cmo_commit_151_wd; + logic lp1_cmo_commit_151_we; + logic lp1_cmo_commit_152_qs; + logic lp1_cmo_commit_152_wd; + logic lp1_cmo_commit_152_we; + logic lp1_cmo_commit_153_qs; + logic lp1_cmo_commit_153_wd; + logic lp1_cmo_commit_153_we; + logic lp1_cmo_commit_154_qs; + logic lp1_cmo_commit_154_wd; + logic lp1_cmo_commit_154_we; + logic lp1_cmo_commit_155_qs; + logic lp1_cmo_commit_155_wd; + logic lp1_cmo_commit_155_we; + logic lp1_cmo_commit_156_qs; + logic lp1_cmo_commit_156_wd; + logic lp1_cmo_commit_156_we; + logic lp1_cmo_commit_157_qs; + logic lp1_cmo_commit_157_wd; + logic lp1_cmo_commit_157_we; + logic lp1_cmo_commit_158_qs; + logic lp1_cmo_commit_158_wd; + logic lp1_cmo_commit_158_we; + logic lp1_cmo_commit_159_qs; + logic lp1_cmo_commit_159_wd; + logic lp1_cmo_commit_159_we; + logic lp1_cmo_commit_160_qs; + logic lp1_cmo_commit_160_wd; + logic lp1_cmo_commit_160_we; + logic lp1_cmo_commit_161_qs; + logic lp1_cmo_commit_161_wd; + logic lp1_cmo_commit_161_we; + logic lp1_cmo_commit_162_qs; + logic lp1_cmo_commit_162_wd; + logic lp1_cmo_commit_162_we; + logic lp1_cmo_commit_163_qs; + logic lp1_cmo_commit_163_wd; + logic lp1_cmo_commit_163_we; + logic lp1_cmo_commit_164_qs; + logic lp1_cmo_commit_164_wd; + logic lp1_cmo_commit_164_we; + logic lp1_cmo_commit_165_qs; + logic lp1_cmo_commit_165_wd; + logic lp1_cmo_commit_165_we; + logic lp1_cmo_commit_166_qs; + logic lp1_cmo_commit_166_wd; + logic lp1_cmo_commit_166_we; + logic lp1_cmo_commit_167_qs; + logic lp1_cmo_commit_167_wd; + logic lp1_cmo_commit_167_we; + logic lp1_cmo_commit_168_qs; + logic lp1_cmo_commit_168_wd; + logic lp1_cmo_commit_168_we; + logic lp1_cmo_commit_169_qs; + logic lp1_cmo_commit_169_wd; + logic lp1_cmo_commit_169_we; + logic lp1_cmo_commit_170_qs; + logic lp1_cmo_commit_170_wd; + logic lp1_cmo_commit_170_we; + logic lp1_cmo_commit_171_qs; + logic lp1_cmo_commit_171_wd; + logic lp1_cmo_commit_171_we; + logic lp1_cmo_commit_172_qs; + logic lp1_cmo_commit_172_wd; + logic lp1_cmo_commit_172_we; + logic lp1_cmo_commit_173_qs; + logic lp1_cmo_commit_173_wd; + logic lp1_cmo_commit_173_we; + logic lp1_cmo_commit_174_qs; + logic lp1_cmo_commit_174_wd; + logic lp1_cmo_commit_174_we; + logic lp1_cmo_commit_175_qs; + logic lp1_cmo_commit_175_wd; + logic lp1_cmo_commit_175_we; + logic lp1_cmo_commit_176_qs; + logic lp1_cmo_commit_176_wd; + logic lp1_cmo_commit_176_we; + logic lp1_cmo_commit_177_qs; + logic lp1_cmo_commit_177_wd; + logic lp1_cmo_commit_177_we; + logic lp1_cmo_commit_178_qs; + logic lp1_cmo_commit_178_wd; + logic lp1_cmo_commit_178_we; + logic lp1_cmo_commit_179_qs; + logic lp1_cmo_commit_179_wd; + logic lp1_cmo_commit_179_we; + logic lp1_cmo_commit_180_qs; + logic lp1_cmo_commit_180_wd; + logic lp1_cmo_commit_180_we; + logic lp1_cmo_commit_181_qs; + logic lp1_cmo_commit_181_wd; + logic lp1_cmo_commit_181_we; + logic lp1_cmo_commit_182_qs; + logic lp1_cmo_commit_182_wd; + logic lp1_cmo_commit_182_we; + logic lp1_cmo_commit_183_qs; + logic lp1_cmo_commit_183_wd; + logic lp1_cmo_commit_183_we; + logic lp1_cmo_commit_184_qs; + logic lp1_cmo_commit_184_wd; + logic lp1_cmo_commit_184_we; + logic lp1_cmo_commit_185_qs; + logic lp1_cmo_commit_185_wd; + logic lp1_cmo_commit_185_we; + logic lp1_cmo_commit_186_qs; + logic lp1_cmo_commit_186_wd; + logic lp1_cmo_commit_186_we; + logic lp1_cmo_commit_187_qs; + logic lp1_cmo_commit_187_wd; + logic lp1_cmo_commit_187_we; + logic lp1_cmo_commit_188_qs; + logic lp1_cmo_commit_188_wd; + logic lp1_cmo_commit_188_we; + logic lp1_cmo_commit_189_qs; + logic lp1_cmo_commit_189_wd; + logic lp1_cmo_commit_189_we; + logic lp1_cmo_commit_190_qs; + logic lp1_cmo_commit_190_wd; + logic lp1_cmo_commit_190_we; + logic lp1_cmo_commit_191_qs; + logic lp1_cmo_commit_191_wd; + logic lp1_cmo_commit_191_we; + logic lp1_cmo_commit_192_qs; + logic lp1_cmo_commit_192_wd; + logic lp1_cmo_commit_192_we; + logic lp1_cmo_commit_193_qs; + logic lp1_cmo_commit_193_wd; + logic lp1_cmo_commit_193_we; + logic lp1_cmo_commit_194_qs; + logic lp1_cmo_commit_194_wd; + logic lp1_cmo_commit_194_we; + logic lp1_cmo_commit_195_qs; + logic lp1_cmo_commit_195_wd; + logic lp1_cmo_commit_195_we; + logic lp1_cmo_commit_196_qs; + logic lp1_cmo_commit_196_wd; + logic lp1_cmo_commit_196_we; + logic lp1_cmo_commit_197_qs; + logic lp1_cmo_commit_197_wd; + logic lp1_cmo_commit_197_we; + logic lp1_cmo_commit_198_qs; + logic lp1_cmo_commit_198_wd; + logic lp1_cmo_commit_198_we; + logic lp1_cmo_commit_199_qs; + logic lp1_cmo_commit_199_wd; + logic lp1_cmo_commit_199_we; + logic lp1_cmo_commit_200_qs; + logic lp1_cmo_commit_200_wd; + logic lp1_cmo_commit_200_we; + logic lp1_cmo_commit_201_qs; + logic lp1_cmo_commit_201_wd; + logic lp1_cmo_commit_201_we; + logic lp1_cmo_commit_202_qs; + logic lp1_cmo_commit_202_wd; + logic lp1_cmo_commit_202_we; + logic lp1_cmo_commit_203_qs; + logic lp1_cmo_commit_203_wd; + logic lp1_cmo_commit_203_we; + logic lp1_cmo_commit_204_qs; + logic lp1_cmo_commit_204_wd; + logic lp1_cmo_commit_204_we; + logic lp1_cmo_commit_205_qs; + logic lp1_cmo_commit_205_wd; + logic lp1_cmo_commit_205_we; + logic lp1_cmo_commit_206_qs; + logic lp1_cmo_commit_206_wd; + logic lp1_cmo_commit_206_we; + logic lp1_cmo_commit_207_qs; + logic lp1_cmo_commit_207_wd; + logic lp1_cmo_commit_207_we; + logic lp1_cmo_commit_208_qs; + logic lp1_cmo_commit_208_wd; + logic lp1_cmo_commit_208_we; + logic lp1_cmo_commit_209_qs; + logic lp1_cmo_commit_209_wd; + logic lp1_cmo_commit_209_we; + logic lp1_cmo_commit_210_qs; + logic lp1_cmo_commit_210_wd; + logic lp1_cmo_commit_210_we; + logic lp1_cmo_commit_211_qs; + logic lp1_cmo_commit_211_wd; + logic lp1_cmo_commit_211_we; + logic lp1_cmo_commit_212_qs; + logic lp1_cmo_commit_212_wd; + logic lp1_cmo_commit_212_we; + logic lp1_cmo_commit_213_qs; + logic lp1_cmo_commit_213_wd; + logic lp1_cmo_commit_213_we; + logic lp1_cmo_commit_214_qs; + logic lp1_cmo_commit_214_wd; + logic lp1_cmo_commit_214_we; + logic lp1_cmo_commit_215_qs; + logic lp1_cmo_commit_215_wd; + logic lp1_cmo_commit_215_we; + logic lp1_cmo_commit_216_qs; + logic lp1_cmo_commit_216_wd; + logic lp1_cmo_commit_216_we; + logic lp1_cmo_commit_217_qs; + logic lp1_cmo_commit_217_wd; + logic lp1_cmo_commit_217_we; + logic lp1_cmo_commit_218_qs; + logic lp1_cmo_commit_218_wd; + logic lp1_cmo_commit_218_we; + logic lp1_cmo_commit_219_qs; + logic lp1_cmo_commit_219_wd; + logic lp1_cmo_commit_219_we; + logic lp1_cmo_commit_220_qs; + logic lp1_cmo_commit_220_wd; + logic lp1_cmo_commit_220_we; + logic lp1_cmo_commit_221_qs; + logic lp1_cmo_commit_221_wd; + logic lp1_cmo_commit_221_we; + logic lp1_cmo_commit_222_qs; + logic lp1_cmo_commit_222_wd; + logic lp1_cmo_commit_222_we; + logic lp1_cmo_commit_223_qs; + logic lp1_cmo_commit_223_wd; + logic lp1_cmo_commit_223_we; + logic lp1_cmo_commit_224_qs; + logic lp1_cmo_commit_224_wd; + logic lp1_cmo_commit_224_we; + logic lp1_cmo_commit_225_qs; + logic lp1_cmo_commit_225_wd; + logic lp1_cmo_commit_225_we; + logic lp1_cmo_commit_226_qs; + logic lp1_cmo_commit_226_wd; + logic lp1_cmo_commit_226_we; + logic lp1_cmo_commit_227_qs; + logic lp1_cmo_commit_227_wd; + logic lp1_cmo_commit_227_we; + logic lp1_cmo_commit_228_qs; + logic lp1_cmo_commit_228_wd; + logic lp1_cmo_commit_228_we; + logic lp1_cmo_commit_229_qs; + logic lp1_cmo_commit_229_wd; + logic lp1_cmo_commit_229_we; + logic lp1_cmo_commit_230_qs; + logic lp1_cmo_commit_230_wd; + logic lp1_cmo_commit_230_we; + logic lp1_cmo_commit_231_qs; + logic lp1_cmo_commit_231_wd; + logic lp1_cmo_commit_231_we; + logic lp1_cmo_commit_232_qs; + logic lp1_cmo_commit_232_wd; + logic lp1_cmo_commit_232_we; + logic lp1_cmo_commit_233_qs; + logic lp1_cmo_commit_233_wd; + logic lp1_cmo_commit_233_we; + logic lp1_cmo_commit_234_qs; + logic lp1_cmo_commit_234_wd; + logic lp1_cmo_commit_234_we; + logic lp1_cmo_commit_235_qs; + logic lp1_cmo_commit_235_wd; + logic lp1_cmo_commit_235_we; + logic lp1_cmo_commit_236_qs; + logic lp1_cmo_commit_236_wd; + logic lp1_cmo_commit_236_we; + logic lp1_cmo_commit_237_qs; + logic lp1_cmo_commit_237_wd; + logic lp1_cmo_commit_237_we; + logic lp1_cmo_commit_238_qs; + logic lp1_cmo_commit_238_wd; + logic lp1_cmo_commit_238_we; + logic lp1_cmo_commit_239_qs; + logic lp1_cmo_commit_239_wd; + logic lp1_cmo_commit_239_we; + logic lp1_cmo_commit_240_qs; + logic lp1_cmo_commit_240_wd; + logic lp1_cmo_commit_240_we; + logic lp1_cmo_commit_241_qs; + logic lp1_cmo_commit_241_wd; + logic lp1_cmo_commit_241_we; + logic lp1_cmo_commit_242_qs; + logic lp1_cmo_commit_242_wd; + logic lp1_cmo_commit_242_we; + logic lp1_cmo_commit_243_qs; + logic lp1_cmo_commit_243_wd; + logic lp1_cmo_commit_243_we; + logic lp1_cmo_commit_244_qs; + logic lp1_cmo_commit_244_wd; + logic lp1_cmo_commit_244_we; + logic lp1_cmo_commit_245_qs; + logic lp1_cmo_commit_245_wd; + logic lp1_cmo_commit_245_we; + logic lp1_cmo_commit_246_qs; + logic lp1_cmo_commit_246_wd; + logic lp1_cmo_commit_246_we; + logic lp1_cmo_commit_247_qs; + logic lp1_cmo_commit_247_wd; + logic lp1_cmo_commit_247_we; + logic lp1_cmo_commit_248_qs; + logic lp1_cmo_commit_248_wd; + logic lp1_cmo_commit_248_we; + logic lp1_cmo_commit_249_qs; + logic lp1_cmo_commit_249_wd; + logic lp1_cmo_commit_249_we; + logic lp1_cmo_commit_250_qs; + logic lp1_cmo_commit_250_wd; + logic lp1_cmo_commit_250_we; + logic lp1_cmo_commit_251_qs; + logic lp1_cmo_commit_251_wd; + logic lp1_cmo_commit_251_we; + logic lp1_cmo_commit_252_qs; + logic lp1_cmo_commit_252_wd; + logic lp1_cmo_commit_252_we; + logic lp1_cmo_commit_253_qs; + logic lp1_cmo_commit_253_wd; + logic lp1_cmo_commit_253_we; + logic lp1_cmo_commit_254_qs; + logic lp1_cmo_commit_254_wd; + logic lp1_cmo_commit_254_we; + logic lp1_cmo_commit_255_qs; + logic lp1_cmo_commit_255_wd; + logic lp1_cmo_commit_255_we; logic lp1_cmo_status_0_qs; logic lp1_cmo_status_0_re; logic lp1_cmo_status_1_qs; @@ -819,6 +2547,390 @@ module cachepool_peripheral_reg_top #( logic lp1_cmo_status_62_re; logic lp1_cmo_status_63_qs; logic lp1_cmo_status_63_re; + logic lp1_cmo_status_64_qs; + logic lp1_cmo_status_64_re; + logic lp1_cmo_status_65_qs; + logic lp1_cmo_status_65_re; + logic lp1_cmo_status_66_qs; + logic lp1_cmo_status_66_re; + logic lp1_cmo_status_67_qs; + logic lp1_cmo_status_67_re; + logic lp1_cmo_status_68_qs; + logic lp1_cmo_status_68_re; + logic lp1_cmo_status_69_qs; + logic lp1_cmo_status_69_re; + logic lp1_cmo_status_70_qs; + logic lp1_cmo_status_70_re; + logic lp1_cmo_status_71_qs; + logic lp1_cmo_status_71_re; + logic lp1_cmo_status_72_qs; + logic lp1_cmo_status_72_re; + logic lp1_cmo_status_73_qs; + logic lp1_cmo_status_73_re; + logic lp1_cmo_status_74_qs; + logic lp1_cmo_status_74_re; + logic lp1_cmo_status_75_qs; + logic lp1_cmo_status_75_re; + logic lp1_cmo_status_76_qs; + logic lp1_cmo_status_76_re; + logic lp1_cmo_status_77_qs; + logic lp1_cmo_status_77_re; + logic lp1_cmo_status_78_qs; + logic lp1_cmo_status_78_re; + logic lp1_cmo_status_79_qs; + logic lp1_cmo_status_79_re; + logic lp1_cmo_status_80_qs; + logic lp1_cmo_status_80_re; + logic lp1_cmo_status_81_qs; + logic lp1_cmo_status_81_re; + logic lp1_cmo_status_82_qs; + logic lp1_cmo_status_82_re; + logic lp1_cmo_status_83_qs; + logic lp1_cmo_status_83_re; + logic lp1_cmo_status_84_qs; + logic lp1_cmo_status_84_re; + logic lp1_cmo_status_85_qs; + logic lp1_cmo_status_85_re; + logic lp1_cmo_status_86_qs; + logic lp1_cmo_status_86_re; + logic lp1_cmo_status_87_qs; + logic lp1_cmo_status_87_re; + logic lp1_cmo_status_88_qs; + logic lp1_cmo_status_88_re; + logic lp1_cmo_status_89_qs; + logic lp1_cmo_status_89_re; + logic lp1_cmo_status_90_qs; + logic lp1_cmo_status_90_re; + logic lp1_cmo_status_91_qs; + logic lp1_cmo_status_91_re; + logic lp1_cmo_status_92_qs; + logic lp1_cmo_status_92_re; + logic lp1_cmo_status_93_qs; + logic lp1_cmo_status_93_re; + logic lp1_cmo_status_94_qs; + logic lp1_cmo_status_94_re; + logic lp1_cmo_status_95_qs; + logic lp1_cmo_status_95_re; + logic lp1_cmo_status_96_qs; + logic lp1_cmo_status_96_re; + logic lp1_cmo_status_97_qs; + logic lp1_cmo_status_97_re; + logic lp1_cmo_status_98_qs; + logic lp1_cmo_status_98_re; + logic lp1_cmo_status_99_qs; + logic lp1_cmo_status_99_re; + logic lp1_cmo_status_100_qs; + logic lp1_cmo_status_100_re; + logic lp1_cmo_status_101_qs; + logic lp1_cmo_status_101_re; + logic lp1_cmo_status_102_qs; + logic lp1_cmo_status_102_re; + logic lp1_cmo_status_103_qs; + logic lp1_cmo_status_103_re; + logic lp1_cmo_status_104_qs; + logic lp1_cmo_status_104_re; + logic lp1_cmo_status_105_qs; + logic lp1_cmo_status_105_re; + logic lp1_cmo_status_106_qs; + logic lp1_cmo_status_106_re; + logic lp1_cmo_status_107_qs; + logic lp1_cmo_status_107_re; + logic lp1_cmo_status_108_qs; + logic lp1_cmo_status_108_re; + logic lp1_cmo_status_109_qs; + logic lp1_cmo_status_109_re; + logic lp1_cmo_status_110_qs; + logic lp1_cmo_status_110_re; + logic lp1_cmo_status_111_qs; + logic lp1_cmo_status_111_re; + logic lp1_cmo_status_112_qs; + logic lp1_cmo_status_112_re; + logic lp1_cmo_status_113_qs; + logic lp1_cmo_status_113_re; + logic lp1_cmo_status_114_qs; + logic lp1_cmo_status_114_re; + logic lp1_cmo_status_115_qs; + logic lp1_cmo_status_115_re; + logic lp1_cmo_status_116_qs; + logic lp1_cmo_status_116_re; + logic lp1_cmo_status_117_qs; + logic lp1_cmo_status_117_re; + logic lp1_cmo_status_118_qs; + logic lp1_cmo_status_118_re; + logic lp1_cmo_status_119_qs; + logic lp1_cmo_status_119_re; + logic lp1_cmo_status_120_qs; + logic lp1_cmo_status_120_re; + logic lp1_cmo_status_121_qs; + logic lp1_cmo_status_121_re; + logic lp1_cmo_status_122_qs; + logic lp1_cmo_status_122_re; + logic lp1_cmo_status_123_qs; + logic lp1_cmo_status_123_re; + logic lp1_cmo_status_124_qs; + logic lp1_cmo_status_124_re; + logic lp1_cmo_status_125_qs; + logic lp1_cmo_status_125_re; + logic lp1_cmo_status_126_qs; + logic lp1_cmo_status_126_re; + logic lp1_cmo_status_127_qs; + logic lp1_cmo_status_127_re; + logic lp1_cmo_status_128_qs; + logic lp1_cmo_status_128_re; + logic lp1_cmo_status_129_qs; + logic lp1_cmo_status_129_re; + logic lp1_cmo_status_130_qs; + logic lp1_cmo_status_130_re; + logic lp1_cmo_status_131_qs; + logic lp1_cmo_status_131_re; + logic lp1_cmo_status_132_qs; + logic lp1_cmo_status_132_re; + logic lp1_cmo_status_133_qs; + logic lp1_cmo_status_133_re; + logic lp1_cmo_status_134_qs; + logic lp1_cmo_status_134_re; + logic lp1_cmo_status_135_qs; + logic lp1_cmo_status_135_re; + logic lp1_cmo_status_136_qs; + logic lp1_cmo_status_136_re; + logic lp1_cmo_status_137_qs; + logic lp1_cmo_status_137_re; + logic lp1_cmo_status_138_qs; + logic lp1_cmo_status_138_re; + logic lp1_cmo_status_139_qs; + logic lp1_cmo_status_139_re; + logic lp1_cmo_status_140_qs; + logic lp1_cmo_status_140_re; + logic lp1_cmo_status_141_qs; + logic lp1_cmo_status_141_re; + logic lp1_cmo_status_142_qs; + logic lp1_cmo_status_142_re; + logic lp1_cmo_status_143_qs; + logic lp1_cmo_status_143_re; + logic lp1_cmo_status_144_qs; + logic lp1_cmo_status_144_re; + logic lp1_cmo_status_145_qs; + logic lp1_cmo_status_145_re; + logic lp1_cmo_status_146_qs; + logic lp1_cmo_status_146_re; + logic lp1_cmo_status_147_qs; + logic lp1_cmo_status_147_re; + logic lp1_cmo_status_148_qs; + logic lp1_cmo_status_148_re; + logic lp1_cmo_status_149_qs; + logic lp1_cmo_status_149_re; + logic lp1_cmo_status_150_qs; + logic lp1_cmo_status_150_re; + logic lp1_cmo_status_151_qs; + logic lp1_cmo_status_151_re; + logic lp1_cmo_status_152_qs; + logic lp1_cmo_status_152_re; + logic lp1_cmo_status_153_qs; + logic lp1_cmo_status_153_re; + logic lp1_cmo_status_154_qs; + logic lp1_cmo_status_154_re; + logic lp1_cmo_status_155_qs; + logic lp1_cmo_status_155_re; + logic lp1_cmo_status_156_qs; + logic lp1_cmo_status_156_re; + logic lp1_cmo_status_157_qs; + logic lp1_cmo_status_157_re; + logic lp1_cmo_status_158_qs; + logic lp1_cmo_status_158_re; + logic lp1_cmo_status_159_qs; + logic lp1_cmo_status_159_re; + logic lp1_cmo_status_160_qs; + logic lp1_cmo_status_160_re; + logic lp1_cmo_status_161_qs; + logic lp1_cmo_status_161_re; + logic lp1_cmo_status_162_qs; + logic lp1_cmo_status_162_re; + logic lp1_cmo_status_163_qs; + logic lp1_cmo_status_163_re; + logic lp1_cmo_status_164_qs; + logic lp1_cmo_status_164_re; + logic lp1_cmo_status_165_qs; + logic lp1_cmo_status_165_re; + logic lp1_cmo_status_166_qs; + logic lp1_cmo_status_166_re; + logic lp1_cmo_status_167_qs; + logic lp1_cmo_status_167_re; + logic lp1_cmo_status_168_qs; + logic lp1_cmo_status_168_re; + logic lp1_cmo_status_169_qs; + logic lp1_cmo_status_169_re; + logic lp1_cmo_status_170_qs; + logic lp1_cmo_status_170_re; + logic lp1_cmo_status_171_qs; + logic lp1_cmo_status_171_re; + logic lp1_cmo_status_172_qs; + logic lp1_cmo_status_172_re; + logic lp1_cmo_status_173_qs; + logic lp1_cmo_status_173_re; + logic lp1_cmo_status_174_qs; + logic lp1_cmo_status_174_re; + logic lp1_cmo_status_175_qs; + logic lp1_cmo_status_175_re; + logic lp1_cmo_status_176_qs; + logic lp1_cmo_status_176_re; + logic lp1_cmo_status_177_qs; + logic lp1_cmo_status_177_re; + logic lp1_cmo_status_178_qs; + logic lp1_cmo_status_178_re; + logic lp1_cmo_status_179_qs; + logic lp1_cmo_status_179_re; + logic lp1_cmo_status_180_qs; + logic lp1_cmo_status_180_re; + logic lp1_cmo_status_181_qs; + logic lp1_cmo_status_181_re; + logic lp1_cmo_status_182_qs; + logic lp1_cmo_status_182_re; + logic lp1_cmo_status_183_qs; + logic lp1_cmo_status_183_re; + logic lp1_cmo_status_184_qs; + logic lp1_cmo_status_184_re; + logic lp1_cmo_status_185_qs; + logic lp1_cmo_status_185_re; + logic lp1_cmo_status_186_qs; + logic lp1_cmo_status_186_re; + logic lp1_cmo_status_187_qs; + logic lp1_cmo_status_187_re; + logic lp1_cmo_status_188_qs; + logic lp1_cmo_status_188_re; + logic lp1_cmo_status_189_qs; + logic lp1_cmo_status_189_re; + logic lp1_cmo_status_190_qs; + logic lp1_cmo_status_190_re; + logic lp1_cmo_status_191_qs; + logic lp1_cmo_status_191_re; + logic lp1_cmo_status_192_qs; + logic lp1_cmo_status_192_re; + logic lp1_cmo_status_193_qs; + logic lp1_cmo_status_193_re; + logic lp1_cmo_status_194_qs; + logic lp1_cmo_status_194_re; + logic lp1_cmo_status_195_qs; + logic lp1_cmo_status_195_re; + logic lp1_cmo_status_196_qs; + logic lp1_cmo_status_196_re; + logic lp1_cmo_status_197_qs; + logic lp1_cmo_status_197_re; + logic lp1_cmo_status_198_qs; + logic lp1_cmo_status_198_re; + logic lp1_cmo_status_199_qs; + logic lp1_cmo_status_199_re; + logic lp1_cmo_status_200_qs; + logic lp1_cmo_status_200_re; + logic lp1_cmo_status_201_qs; + logic lp1_cmo_status_201_re; + logic lp1_cmo_status_202_qs; + logic lp1_cmo_status_202_re; + logic lp1_cmo_status_203_qs; + logic lp1_cmo_status_203_re; + logic lp1_cmo_status_204_qs; + logic lp1_cmo_status_204_re; + logic lp1_cmo_status_205_qs; + logic lp1_cmo_status_205_re; + logic lp1_cmo_status_206_qs; + logic lp1_cmo_status_206_re; + logic lp1_cmo_status_207_qs; + logic lp1_cmo_status_207_re; + logic lp1_cmo_status_208_qs; + logic lp1_cmo_status_208_re; + logic lp1_cmo_status_209_qs; + logic lp1_cmo_status_209_re; + logic lp1_cmo_status_210_qs; + logic lp1_cmo_status_210_re; + logic lp1_cmo_status_211_qs; + logic lp1_cmo_status_211_re; + logic lp1_cmo_status_212_qs; + logic lp1_cmo_status_212_re; + logic lp1_cmo_status_213_qs; + logic lp1_cmo_status_213_re; + logic lp1_cmo_status_214_qs; + logic lp1_cmo_status_214_re; + logic lp1_cmo_status_215_qs; + logic lp1_cmo_status_215_re; + logic lp1_cmo_status_216_qs; + logic lp1_cmo_status_216_re; + logic lp1_cmo_status_217_qs; + logic lp1_cmo_status_217_re; + logic lp1_cmo_status_218_qs; + logic lp1_cmo_status_218_re; + logic lp1_cmo_status_219_qs; + logic lp1_cmo_status_219_re; + logic lp1_cmo_status_220_qs; + logic lp1_cmo_status_220_re; + logic lp1_cmo_status_221_qs; + logic lp1_cmo_status_221_re; + logic lp1_cmo_status_222_qs; + logic lp1_cmo_status_222_re; + logic lp1_cmo_status_223_qs; + logic lp1_cmo_status_223_re; + logic lp1_cmo_status_224_qs; + logic lp1_cmo_status_224_re; + logic lp1_cmo_status_225_qs; + logic lp1_cmo_status_225_re; + logic lp1_cmo_status_226_qs; + logic lp1_cmo_status_226_re; + logic lp1_cmo_status_227_qs; + logic lp1_cmo_status_227_re; + logic lp1_cmo_status_228_qs; + logic lp1_cmo_status_228_re; + logic lp1_cmo_status_229_qs; + logic lp1_cmo_status_229_re; + logic lp1_cmo_status_230_qs; + logic lp1_cmo_status_230_re; + logic lp1_cmo_status_231_qs; + logic lp1_cmo_status_231_re; + logic lp1_cmo_status_232_qs; + logic lp1_cmo_status_232_re; + logic lp1_cmo_status_233_qs; + logic lp1_cmo_status_233_re; + logic lp1_cmo_status_234_qs; + logic lp1_cmo_status_234_re; + logic lp1_cmo_status_235_qs; + logic lp1_cmo_status_235_re; + logic lp1_cmo_status_236_qs; + logic lp1_cmo_status_236_re; + logic lp1_cmo_status_237_qs; + logic lp1_cmo_status_237_re; + logic lp1_cmo_status_238_qs; + logic lp1_cmo_status_238_re; + logic lp1_cmo_status_239_qs; + logic lp1_cmo_status_239_re; + logic lp1_cmo_status_240_qs; + logic lp1_cmo_status_240_re; + logic lp1_cmo_status_241_qs; + logic lp1_cmo_status_241_re; + logic lp1_cmo_status_242_qs; + logic lp1_cmo_status_242_re; + logic lp1_cmo_status_243_qs; + logic lp1_cmo_status_243_re; + logic lp1_cmo_status_244_qs; + logic lp1_cmo_status_244_re; + logic lp1_cmo_status_245_qs; + logic lp1_cmo_status_245_re; + logic lp1_cmo_status_246_qs; + logic lp1_cmo_status_246_re; + logic lp1_cmo_status_247_qs; + logic lp1_cmo_status_247_re; + logic lp1_cmo_status_248_qs; + logic lp1_cmo_status_248_re; + logic lp1_cmo_status_249_qs; + logic lp1_cmo_status_249_re; + logic lp1_cmo_status_250_qs; + logic lp1_cmo_status_250_re; + logic lp1_cmo_status_251_qs; + logic lp1_cmo_status_251_re; + logic lp1_cmo_status_252_qs; + logic lp1_cmo_status_252_re; + logic lp1_cmo_status_253_qs; + logic lp1_cmo_status_253_re; + logic lp1_cmo_status_254_qs; + logic lp1_cmo_status_254_re; + logic lp1_cmo_status_255_qs; + logic lp1_cmo_status_255_re; // Register instances // R[hw_barrier]: V(True) @@ -2987,22 +5099,20 @@ module cachepool_peripheral_reg_top #( .qs (cfg_lp1_cmo_63_qs) ); - - - // Subregister 0 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_0]: V(False) + // Subregister 64 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_64]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_0 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_64 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_0_we), - .wd (cfg_lp1_cmo_addr_0_wd), + .we (cfg_lp1_cmo_64_we), + .wd (cfg_lp1_cmo_64_wd), // from internal hardware .de (1'b0), @@ -3010,26 +5120,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[0].q ), + .q (reg2hw.cfg_lp1_cmo[64].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_0_qs) + .qs (cfg_lp1_cmo_64_qs) ); - // Subregister 1 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_1]: V(False) + // Subregister 65 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_65]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_1 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_65 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_1_we), - .wd (cfg_lp1_cmo_addr_1_wd), + .we (cfg_lp1_cmo_65_we), + .wd (cfg_lp1_cmo_65_wd), // from internal hardware .de (1'b0), @@ -3037,26 +5147,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[1].q ), + .q (reg2hw.cfg_lp1_cmo[65].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_1_qs) + .qs (cfg_lp1_cmo_65_qs) ); - // Subregister 2 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_2]: V(False) + // Subregister 66 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_66]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_2 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_66 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_2_we), - .wd (cfg_lp1_cmo_addr_2_wd), + .we (cfg_lp1_cmo_66_we), + .wd (cfg_lp1_cmo_66_wd), // from internal hardware .de (1'b0), @@ -3064,26 +5174,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[2].q ), + .q (reg2hw.cfg_lp1_cmo[66].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_2_qs) + .qs (cfg_lp1_cmo_66_qs) ); - // Subregister 3 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_3]: V(False) + // Subregister 67 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_67]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_3 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_67 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_3_we), - .wd (cfg_lp1_cmo_addr_3_wd), + .we (cfg_lp1_cmo_67_we), + .wd (cfg_lp1_cmo_67_wd), // from internal hardware .de (1'b0), @@ -3091,26 +5201,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[3].q ), + .q (reg2hw.cfg_lp1_cmo[67].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_3_qs) + .qs (cfg_lp1_cmo_67_qs) ); - // Subregister 4 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_4]: V(False) + // Subregister 68 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_68]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_4 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_68 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_4_we), - .wd (cfg_lp1_cmo_addr_4_wd), + .we (cfg_lp1_cmo_68_we), + .wd (cfg_lp1_cmo_68_wd), // from internal hardware .de (1'b0), @@ -3118,26 +5228,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[4].q ), + .q (reg2hw.cfg_lp1_cmo[68].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_4_qs) + .qs (cfg_lp1_cmo_68_qs) ); - // Subregister 5 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_5]: V(False) + // Subregister 69 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_69]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_5 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_69 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_5_we), - .wd (cfg_lp1_cmo_addr_5_wd), + .we (cfg_lp1_cmo_69_we), + .wd (cfg_lp1_cmo_69_wd), // from internal hardware .de (1'b0), @@ -3145,26 +5255,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[5].q ), + .q (reg2hw.cfg_lp1_cmo[69].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_5_qs) + .qs (cfg_lp1_cmo_69_qs) ); - // Subregister 6 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_6]: V(False) + // Subregister 70 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_70]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_6 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_70 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_6_we), - .wd (cfg_lp1_cmo_addr_6_wd), + .we (cfg_lp1_cmo_70_we), + .wd (cfg_lp1_cmo_70_wd), // from internal hardware .de (1'b0), @@ -3172,26 +5282,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[6].q ), + .q (reg2hw.cfg_lp1_cmo[70].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_6_qs) + .qs (cfg_lp1_cmo_70_qs) ); - // Subregister 7 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_7]: V(False) + // Subregister 71 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_71]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_7 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_71 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_7_we), - .wd (cfg_lp1_cmo_addr_7_wd), + .we (cfg_lp1_cmo_71_we), + .wd (cfg_lp1_cmo_71_wd), // from internal hardware .de (1'b0), @@ -3199,26 +5309,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[7].q ), + .q (reg2hw.cfg_lp1_cmo[71].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_7_qs) + .qs (cfg_lp1_cmo_71_qs) ); - // Subregister 8 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_8]: V(False) + // Subregister 72 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_72]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_8 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_72 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_8_we), - .wd (cfg_lp1_cmo_addr_8_wd), + .we (cfg_lp1_cmo_72_we), + .wd (cfg_lp1_cmo_72_wd), // from internal hardware .de (1'b0), @@ -3226,26 +5336,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[8].q ), + .q (reg2hw.cfg_lp1_cmo[72].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_8_qs) + .qs (cfg_lp1_cmo_72_qs) ); - // Subregister 9 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_9]: V(False) + // Subregister 73 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_73]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_9 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_73 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_9_we), - .wd (cfg_lp1_cmo_addr_9_wd), + .we (cfg_lp1_cmo_73_we), + .wd (cfg_lp1_cmo_73_wd), // from internal hardware .de (1'b0), @@ -3253,26 +5363,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[9].q ), + .q (reg2hw.cfg_lp1_cmo[73].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_9_qs) + .qs (cfg_lp1_cmo_73_qs) ); - // Subregister 10 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_10]: V(False) + // Subregister 74 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_74]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_10 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_74 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_10_we), - .wd (cfg_lp1_cmo_addr_10_wd), + .we (cfg_lp1_cmo_74_we), + .wd (cfg_lp1_cmo_74_wd), // from internal hardware .de (1'b0), @@ -3280,26 +5390,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[10].q ), + .q (reg2hw.cfg_lp1_cmo[74].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_10_qs) + .qs (cfg_lp1_cmo_74_qs) ); - // Subregister 11 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_11]: V(False) + // Subregister 75 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_75]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_11 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_75 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_11_we), - .wd (cfg_lp1_cmo_addr_11_wd), + .we (cfg_lp1_cmo_75_we), + .wd (cfg_lp1_cmo_75_wd), // from internal hardware .de (1'b0), @@ -3307,26 +5417,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[11].q ), + .q (reg2hw.cfg_lp1_cmo[75].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_11_qs) + .qs (cfg_lp1_cmo_75_qs) ); - // Subregister 12 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_12]: V(False) + // Subregister 76 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_76]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_12 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_76 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_12_we), - .wd (cfg_lp1_cmo_addr_12_wd), + .we (cfg_lp1_cmo_76_we), + .wd (cfg_lp1_cmo_76_wd), // from internal hardware .de (1'b0), @@ -3334,26 +5444,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[12].q ), + .q (reg2hw.cfg_lp1_cmo[76].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_12_qs) + .qs (cfg_lp1_cmo_76_qs) ); - // Subregister 13 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_13]: V(False) + // Subregister 77 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_77]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_13 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_77 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_13_we), - .wd (cfg_lp1_cmo_addr_13_wd), + .we (cfg_lp1_cmo_77_we), + .wd (cfg_lp1_cmo_77_wd), // from internal hardware .de (1'b0), @@ -3361,26 +5471,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[13].q ), + .q (reg2hw.cfg_lp1_cmo[77].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_13_qs) + .qs (cfg_lp1_cmo_77_qs) ); - // Subregister 14 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_14]: V(False) + // Subregister 78 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_78]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_14 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_78 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_14_we), - .wd (cfg_lp1_cmo_addr_14_wd), + .we (cfg_lp1_cmo_78_we), + .wd (cfg_lp1_cmo_78_wd), // from internal hardware .de (1'b0), @@ -3388,26 +5498,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[14].q ), + .q (reg2hw.cfg_lp1_cmo[78].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_14_qs) + .qs (cfg_lp1_cmo_78_qs) ); - // Subregister 15 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_15]: V(False) + // Subregister 79 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_79]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_15 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_79 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_15_we), - .wd (cfg_lp1_cmo_addr_15_wd), + .we (cfg_lp1_cmo_79_we), + .wd (cfg_lp1_cmo_79_wd), // from internal hardware .de (1'b0), @@ -3415,26 +5525,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[15].q ), + .q (reg2hw.cfg_lp1_cmo[79].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_15_qs) + .qs (cfg_lp1_cmo_79_qs) ); - // Subregister 16 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_16]: V(False) + // Subregister 80 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_80]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_16 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_80 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_16_we), - .wd (cfg_lp1_cmo_addr_16_wd), + .we (cfg_lp1_cmo_80_we), + .wd (cfg_lp1_cmo_80_wd), // from internal hardware .de (1'b0), @@ -3442,26 +5552,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[16].q ), + .q (reg2hw.cfg_lp1_cmo[80].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_16_qs) + .qs (cfg_lp1_cmo_80_qs) ); - // Subregister 17 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_17]: V(False) + // Subregister 81 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_81]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_17 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_81 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_17_we), - .wd (cfg_lp1_cmo_addr_17_wd), + .we (cfg_lp1_cmo_81_we), + .wd (cfg_lp1_cmo_81_wd), // from internal hardware .de (1'b0), @@ -3469,26 +5579,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[17].q ), + .q (reg2hw.cfg_lp1_cmo[81].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_17_qs) + .qs (cfg_lp1_cmo_81_qs) ); - // Subregister 18 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_18]: V(False) + // Subregister 82 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_82]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_18 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_82 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_18_we), - .wd (cfg_lp1_cmo_addr_18_wd), + .we (cfg_lp1_cmo_82_we), + .wd (cfg_lp1_cmo_82_wd), // from internal hardware .de (1'b0), @@ -3496,26 +5606,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[18].q ), + .q (reg2hw.cfg_lp1_cmo[82].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_18_qs) + .qs (cfg_lp1_cmo_82_qs) ); - // Subregister 19 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_19]: V(False) + // Subregister 83 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_83]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_19 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_83 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_19_we), - .wd (cfg_lp1_cmo_addr_19_wd), + .we (cfg_lp1_cmo_83_we), + .wd (cfg_lp1_cmo_83_wd), // from internal hardware .de (1'b0), @@ -3523,26 +5633,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[19].q ), + .q (reg2hw.cfg_lp1_cmo[83].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_19_qs) + .qs (cfg_lp1_cmo_83_qs) ); - // Subregister 20 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_20]: V(False) + // Subregister 84 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_84]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_20 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_84 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_20_we), - .wd (cfg_lp1_cmo_addr_20_wd), + .we (cfg_lp1_cmo_84_we), + .wd (cfg_lp1_cmo_84_wd), // from internal hardware .de (1'b0), @@ -3550,26 +5660,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[20].q ), + .q (reg2hw.cfg_lp1_cmo[84].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_20_qs) + .qs (cfg_lp1_cmo_84_qs) ); - // Subregister 21 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_21]: V(False) + // Subregister 85 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_85]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_21 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_85 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_21_we), - .wd (cfg_lp1_cmo_addr_21_wd), + .we (cfg_lp1_cmo_85_we), + .wd (cfg_lp1_cmo_85_wd), // from internal hardware .de (1'b0), @@ -3577,26 +5687,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[21].q ), + .q (reg2hw.cfg_lp1_cmo[85].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_21_qs) + .qs (cfg_lp1_cmo_85_qs) ); - // Subregister 22 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_22]: V(False) + // Subregister 86 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_86]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_22 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_86 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_22_we), - .wd (cfg_lp1_cmo_addr_22_wd), + .we (cfg_lp1_cmo_86_we), + .wd (cfg_lp1_cmo_86_wd), // from internal hardware .de (1'b0), @@ -3604,26 +5714,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[22].q ), + .q (reg2hw.cfg_lp1_cmo[86].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_22_qs) + .qs (cfg_lp1_cmo_86_qs) ); - // Subregister 23 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_23]: V(False) + // Subregister 87 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_87]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_23 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_87 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_23_we), - .wd (cfg_lp1_cmo_addr_23_wd), + .we (cfg_lp1_cmo_87_we), + .wd (cfg_lp1_cmo_87_wd), // from internal hardware .de (1'b0), @@ -3631,26 +5741,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[23].q ), + .q (reg2hw.cfg_lp1_cmo[87].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_23_qs) + .qs (cfg_lp1_cmo_87_qs) ); - // Subregister 24 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_24]: V(False) + // Subregister 88 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_88]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_24 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_88 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_24_we), - .wd (cfg_lp1_cmo_addr_24_wd), + .we (cfg_lp1_cmo_88_we), + .wd (cfg_lp1_cmo_88_wd), // from internal hardware .de (1'b0), @@ -3658,26 +5768,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[24].q ), + .q (reg2hw.cfg_lp1_cmo[88].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_24_qs) + .qs (cfg_lp1_cmo_88_qs) ); - // Subregister 25 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_25]: V(False) + // Subregister 89 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_89]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_25 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_89 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_25_we), - .wd (cfg_lp1_cmo_addr_25_wd), + .we (cfg_lp1_cmo_89_we), + .wd (cfg_lp1_cmo_89_wd), // from internal hardware .de (1'b0), @@ -3685,26 +5795,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[25].q ), + .q (reg2hw.cfg_lp1_cmo[89].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_25_qs) + .qs (cfg_lp1_cmo_89_qs) ); - // Subregister 26 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_26]: V(False) + // Subregister 90 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_90]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_26 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_90 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_26_we), - .wd (cfg_lp1_cmo_addr_26_wd), + .we (cfg_lp1_cmo_90_we), + .wd (cfg_lp1_cmo_90_wd), // from internal hardware .de (1'b0), @@ -3712,26 +5822,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[26].q ), + .q (reg2hw.cfg_lp1_cmo[90].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_26_qs) + .qs (cfg_lp1_cmo_90_qs) ); - // Subregister 27 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_27]: V(False) + // Subregister 91 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_91]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_27 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_91 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_27_we), - .wd (cfg_lp1_cmo_addr_27_wd), + .we (cfg_lp1_cmo_91_we), + .wd (cfg_lp1_cmo_91_wd), // from internal hardware .de (1'b0), @@ -3739,26 +5849,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[27].q ), + .q (reg2hw.cfg_lp1_cmo[91].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_27_qs) + .qs (cfg_lp1_cmo_91_qs) ); - // Subregister 28 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_28]: V(False) + // Subregister 92 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_92]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_28 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_92 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_28_we), - .wd (cfg_lp1_cmo_addr_28_wd), + .we (cfg_lp1_cmo_92_we), + .wd (cfg_lp1_cmo_92_wd), // from internal hardware .de (1'b0), @@ -3766,26 +5876,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[28].q ), + .q (reg2hw.cfg_lp1_cmo[92].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_28_qs) + .qs (cfg_lp1_cmo_92_qs) ); - // Subregister 29 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_29]: V(False) + // Subregister 93 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_93]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_29 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_93 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_29_we), - .wd (cfg_lp1_cmo_addr_29_wd), + .we (cfg_lp1_cmo_93_we), + .wd (cfg_lp1_cmo_93_wd), // from internal hardware .de (1'b0), @@ -3793,26 +5903,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[29].q ), + .q (reg2hw.cfg_lp1_cmo[93].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_29_qs) + .qs (cfg_lp1_cmo_93_qs) ); - // Subregister 30 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_30]: V(False) + // Subregister 94 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_94]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_30 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_94 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_30_we), - .wd (cfg_lp1_cmo_addr_30_wd), + .we (cfg_lp1_cmo_94_we), + .wd (cfg_lp1_cmo_94_wd), // from internal hardware .de (1'b0), @@ -3820,26 +5930,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[30].q ), + .q (reg2hw.cfg_lp1_cmo[94].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_30_qs) + .qs (cfg_lp1_cmo_94_qs) ); - // Subregister 31 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_31]: V(False) + // Subregister 95 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_95]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_31 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_95 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_31_we), - .wd (cfg_lp1_cmo_addr_31_wd), + .we (cfg_lp1_cmo_95_we), + .wd (cfg_lp1_cmo_95_wd), // from internal hardware .de (1'b0), @@ -3847,26 +5957,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[31].q ), + .q (reg2hw.cfg_lp1_cmo[95].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_31_qs) + .qs (cfg_lp1_cmo_95_qs) ); - // Subregister 32 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_32]: V(False) + // Subregister 96 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_96]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_32 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_96 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_32_we), - .wd (cfg_lp1_cmo_addr_32_wd), + .we (cfg_lp1_cmo_96_we), + .wd (cfg_lp1_cmo_96_wd), // from internal hardware .de (1'b0), @@ -3874,26 +5984,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[32].q ), + .q (reg2hw.cfg_lp1_cmo[96].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_32_qs) + .qs (cfg_lp1_cmo_96_qs) ); - // Subregister 33 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_33]: V(False) + // Subregister 97 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_97]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_33 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_97 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_33_we), - .wd (cfg_lp1_cmo_addr_33_wd), + .we (cfg_lp1_cmo_97_we), + .wd (cfg_lp1_cmo_97_wd), // from internal hardware .de (1'b0), @@ -3901,26 +6011,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[33].q ), + .q (reg2hw.cfg_lp1_cmo[97].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_33_qs) + .qs (cfg_lp1_cmo_97_qs) ); - // Subregister 34 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_34]: V(False) + // Subregister 98 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_98]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_34 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_98 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_34_we), - .wd (cfg_lp1_cmo_addr_34_wd), + .we (cfg_lp1_cmo_98_we), + .wd (cfg_lp1_cmo_98_wd), // from internal hardware .de (1'b0), @@ -3928,26 +6038,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[34].q ), + .q (reg2hw.cfg_lp1_cmo[98].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_34_qs) + .qs (cfg_lp1_cmo_98_qs) ); - // Subregister 35 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_35]: V(False) + // Subregister 99 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_99]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_35 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_99 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_35_we), - .wd (cfg_lp1_cmo_addr_35_wd), + .we (cfg_lp1_cmo_99_we), + .wd (cfg_lp1_cmo_99_wd), // from internal hardware .de (1'b0), @@ -3955,26 +6065,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[35].q ), + .q (reg2hw.cfg_lp1_cmo[99].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_35_qs) + .qs (cfg_lp1_cmo_99_qs) ); - // Subregister 36 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_36]: V(False) + // Subregister 100 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_100]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_36 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_100 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_36_we), - .wd (cfg_lp1_cmo_addr_36_wd), + .we (cfg_lp1_cmo_100_we), + .wd (cfg_lp1_cmo_100_wd), // from internal hardware .de (1'b0), @@ -3982,26 +6092,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[36].q ), + .q (reg2hw.cfg_lp1_cmo[100].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_36_qs) + .qs (cfg_lp1_cmo_100_qs) ); - // Subregister 37 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_37]: V(False) + // Subregister 101 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_101]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_37 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_101 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_37_we), - .wd (cfg_lp1_cmo_addr_37_wd), + .we (cfg_lp1_cmo_101_we), + .wd (cfg_lp1_cmo_101_wd), // from internal hardware .de (1'b0), @@ -4009,26 +6119,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[37].q ), + .q (reg2hw.cfg_lp1_cmo[101].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_37_qs) + .qs (cfg_lp1_cmo_101_qs) ); - // Subregister 38 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_38]: V(False) + // Subregister 102 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_102]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_38 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_102 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_38_we), - .wd (cfg_lp1_cmo_addr_38_wd), + .we (cfg_lp1_cmo_102_we), + .wd (cfg_lp1_cmo_102_wd), // from internal hardware .de (1'b0), @@ -4036,26 +6146,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[38].q ), + .q (reg2hw.cfg_lp1_cmo[102].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_38_qs) + .qs (cfg_lp1_cmo_102_qs) ); - // Subregister 39 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_39]: V(False) + // Subregister 103 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_103]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_39 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_103 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_39_we), - .wd (cfg_lp1_cmo_addr_39_wd), + .we (cfg_lp1_cmo_103_we), + .wd (cfg_lp1_cmo_103_wd), // from internal hardware .de (1'b0), @@ -4063,26 +6173,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[39].q ), + .q (reg2hw.cfg_lp1_cmo[103].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_39_qs) + .qs (cfg_lp1_cmo_103_qs) ); - // Subregister 40 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_40]: V(False) + // Subregister 104 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_104]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_40 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_104 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_40_we), - .wd (cfg_lp1_cmo_addr_40_wd), + .we (cfg_lp1_cmo_104_we), + .wd (cfg_lp1_cmo_104_wd), // from internal hardware .de (1'b0), @@ -4090,26 +6200,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[40].q ), + .q (reg2hw.cfg_lp1_cmo[104].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_40_qs) + .qs (cfg_lp1_cmo_104_qs) ); - // Subregister 41 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_41]: V(False) + // Subregister 105 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_105]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_41 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_105 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_41_we), - .wd (cfg_lp1_cmo_addr_41_wd), + .we (cfg_lp1_cmo_105_we), + .wd (cfg_lp1_cmo_105_wd), // from internal hardware .de (1'b0), @@ -4117,26 +6227,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[41].q ), + .q (reg2hw.cfg_lp1_cmo[105].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_41_qs) + .qs (cfg_lp1_cmo_105_qs) ); - // Subregister 42 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_42]: V(False) + // Subregister 106 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_106]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_42 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_106 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_42_we), - .wd (cfg_lp1_cmo_addr_42_wd), + .we (cfg_lp1_cmo_106_we), + .wd (cfg_lp1_cmo_106_wd), // from internal hardware .de (1'b0), @@ -4144,26 +6254,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[42].q ), + .q (reg2hw.cfg_lp1_cmo[106].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_42_qs) + .qs (cfg_lp1_cmo_106_qs) ); - // Subregister 43 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_43]: V(False) + // Subregister 107 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_107]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_43 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_107 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_43_we), - .wd (cfg_lp1_cmo_addr_43_wd), + .we (cfg_lp1_cmo_107_we), + .wd (cfg_lp1_cmo_107_wd), // from internal hardware .de (1'b0), @@ -4171,26 +6281,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[43].q ), + .q (reg2hw.cfg_lp1_cmo[107].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_43_qs) + .qs (cfg_lp1_cmo_107_qs) ); - // Subregister 44 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_44]: V(False) + // Subregister 108 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_108]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_44 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_108 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_44_we), - .wd (cfg_lp1_cmo_addr_44_wd), + .we (cfg_lp1_cmo_108_we), + .wd (cfg_lp1_cmo_108_wd), // from internal hardware .de (1'b0), @@ -4198,26 +6308,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[44].q ), + .q (reg2hw.cfg_lp1_cmo[108].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_44_qs) + .qs (cfg_lp1_cmo_108_qs) ); - // Subregister 45 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_45]: V(False) + // Subregister 109 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_109]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_45 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_109 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_45_we), - .wd (cfg_lp1_cmo_addr_45_wd), + .we (cfg_lp1_cmo_109_we), + .wd (cfg_lp1_cmo_109_wd), // from internal hardware .de (1'b0), @@ -4225,26 +6335,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[45].q ), + .q (reg2hw.cfg_lp1_cmo[109].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_45_qs) + .qs (cfg_lp1_cmo_109_qs) ); - // Subregister 46 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_46]: V(False) + // Subregister 110 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_110]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_46 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_110 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_46_we), - .wd (cfg_lp1_cmo_addr_46_wd), + .we (cfg_lp1_cmo_110_we), + .wd (cfg_lp1_cmo_110_wd), // from internal hardware .de (1'b0), @@ -4252,26 +6362,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[46].q ), + .q (reg2hw.cfg_lp1_cmo[110].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_46_qs) + .qs (cfg_lp1_cmo_110_qs) ); - // Subregister 47 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_47]: V(False) + // Subregister 111 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_111]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_47 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_111 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_47_we), - .wd (cfg_lp1_cmo_addr_47_wd), + .we (cfg_lp1_cmo_111_we), + .wd (cfg_lp1_cmo_111_wd), // from internal hardware .de (1'b0), @@ -4279,26 +6389,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[47].q ), + .q (reg2hw.cfg_lp1_cmo[111].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_47_qs) + .qs (cfg_lp1_cmo_111_qs) ); - // Subregister 48 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_48]: V(False) + // Subregister 112 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_112]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_48 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_112 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_48_we), - .wd (cfg_lp1_cmo_addr_48_wd), + .we (cfg_lp1_cmo_112_we), + .wd (cfg_lp1_cmo_112_wd), // from internal hardware .de (1'b0), @@ -4306,26 +6416,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[48].q ), + .q (reg2hw.cfg_lp1_cmo[112].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_48_qs) + .qs (cfg_lp1_cmo_112_qs) ); - // Subregister 49 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_49]: V(False) + // Subregister 113 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_113]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_49 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_113 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_49_we), - .wd (cfg_lp1_cmo_addr_49_wd), + .we (cfg_lp1_cmo_113_we), + .wd (cfg_lp1_cmo_113_wd), // from internal hardware .de (1'b0), @@ -4333,26 +6443,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[49].q ), + .q (reg2hw.cfg_lp1_cmo[113].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_49_qs) + .qs (cfg_lp1_cmo_113_qs) ); - // Subregister 50 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_50]: V(False) + // Subregister 114 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_114]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_50 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_114 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_50_we), - .wd (cfg_lp1_cmo_addr_50_wd), + .we (cfg_lp1_cmo_114_we), + .wd (cfg_lp1_cmo_114_wd), // from internal hardware .de (1'b0), @@ -4360,26 +6470,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[50].q ), + .q (reg2hw.cfg_lp1_cmo[114].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_50_qs) + .qs (cfg_lp1_cmo_114_qs) ); - // Subregister 51 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_51]: V(False) + // Subregister 115 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_115]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_51 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_115 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_51_we), - .wd (cfg_lp1_cmo_addr_51_wd), + .we (cfg_lp1_cmo_115_we), + .wd (cfg_lp1_cmo_115_wd), // from internal hardware .de (1'b0), @@ -4387,26 +6497,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[51].q ), + .q (reg2hw.cfg_lp1_cmo[115].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_51_qs) + .qs (cfg_lp1_cmo_115_qs) ); - // Subregister 52 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_52]: V(False) + // Subregister 116 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_116]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_52 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_116 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_52_we), - .wd (cfg_lp1_cmo_addr_52_wd), + .we (cfg_lp1_cmo_116_we), + .wd (cfg_lp1_cmo_116_wd), // from internal hardware .de (1'b0), @@ -4414,26 +6524,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[52].q ), + .q (reg2hw.cfg_lp1_cmo[116].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_52_qs) + .qs (cfg_lp1_cmo_116_qs) ); - // Subregister 53 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_53]: V(False) + // Subregister 117 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_117]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_53 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_117 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_53_we), - .wd (cfg_lp1_cmo_addr_53_wd), + .we (cfg_lp1_cmo_117_we), + .wd (cfg_lp1_cmo_117_wd), // from internal hardware .de (1'b0), @@ -4441,26 +6551,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[53].q ), + .q (reg2hw.cfg_lp1_cmo[117].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_53_qs) + .qs (cfg_lp1_cmo_117_qs) ); - // Subregister 54 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_54]: V(False) + // Subregister 118 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_118]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_54 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_118 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_54_we), - .wd (cfg_lp1_cmo_addr_54_wd), + .we (cfg_lp1_cmo_118_we), + .wd (cfg_lp1_cmo_118_wd), // from internal hardware .de (1'b0), @@ -4468,26 +6578,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[54].q ), + .q (reg2hw.cfg_lp1_cmo[118].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_54_qs) + .qs (cfg_lp1_cmo_118_qs) ); - // Subregister 55 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_55]: V(False) + // Subregister 119 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_119]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_55 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_119 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_55_we), - .wd (cfg_lp1_cmo_addr_55_wd), + .we (cfg_lp1_cmo_119_we), + .wd (cfg_lp1_cmo_119_wd), // from internal hardware .de (1'b0), @@ -4495,26 +6605,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[55].q ), + .q (reg2hw.cfg_lp1_cmo[119].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_55_qs) + .qs (cfg_lp1_cmo_119_qs) ); - // Subregister 56 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_56]: V(False) + // Subregister 120 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_120]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_56 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_120 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_56_we), - .wd (cfg_lp1_cmo_addr_56_wd), + .we (cfg_lp1_cmo_120_we), + .wd (cfg_lp1_cmo_120_wd), // from internal hardware .de (1'b0), @@ -4522,26 +6632,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[56].q ), + .q (reg2hw.cfg_lp1_cmo[120].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_56_qs) + .qs (cfg_lp1_cmo_120_qs) ); - // Subregister 57 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_57]: V(False) + // Subregister 121 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_121]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_57 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_121 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_57_we), - .wd (cfg_lp1_cmo_addr_57_wd), + .we (cfg_lp1_cmo_121_we), + .wd (cfg_lp1_cmo_121_wd), // from internal hardware .de (1'b0), @@ -4549,26 +6659,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[57].q ), + .q (reg2hw.cfg_lp1_cmo[121].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_57_qs) + .qs (cfg_lp1_cmo_121_qs) ); - // Subregister 58 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_58]: V(False) + // Subregister 122 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_122]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_58 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_122 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_58_we), - .wd (cfg_lp1_cmo_addr_58_wd), + .we (cfg_lp1_cmo_122_we), + .wd (cfg_lp1_cmo_122_wd), // from internal hardware .de (1'b0), @@ -4576,26 +6686,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[58].q ), + .q (reg2hw.cfg_lp1_cmo[122].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_58_qs) + .qs (cfg_lp1_cmo_122_qs) ); - // Subregister 59 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_59]: V(False) + // Subregister 123 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_123]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_59 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_123 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_59_we), - .wd (cfg_lp1_cmo_addr_59_wd), + .we (cfg_lp1_cmo_123_we), + .wd (cfg_lp1_cmo_123_wd), // from internal hardware .de (1'b0), @@ -4603,26 +6713,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[59].q ), + .q (reg2hw.cfg_lp1_cmo[123].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_59_qs) + .qs (cfg_lp1_cmo_123_qs) ); - // Subregister 60 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_60]: V(False) + // Subregister 124 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_124]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_60 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_124 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_60_we), - .wd (cfg_lp1_cmo_addr_60_wd), + .we (cfg_lp1_cmo_124_we), + .wd (cfg_lp1_cmo_124_wd), // from internal hardware .de (1'b0), @@ -4630,26 +6740,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[60].q ), + .q (reg2hw.cfg_lp1_cmo[124].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_60_qs) + .qs (cfg_lp1_cmo_124_qs) ); - // Subregister 61 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_61]: V(False) + // Subregister 125 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_125]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_61 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_125 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_61_we), - .wd (cfg_lp1_cmo_addr_61_wd), + .we (cfg_lp1_cmo_125_we), + .wd (cfg_lp1_cmo_125_wd), // from internal hardware .de (1'b0), @@ -4657,26 +6767,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[61].q ), + .q (reg2hw.cfg_lp1_cmo[125].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_61_qs) + .qs (cfg_lp1_cmo_125_qs) ); - // Subregister 62 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_62]: V(False) + // Subregister 126 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_126]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_62 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_126 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_62_we), - .wd (cfg_lp1_cmo_addr_62_wd), + .we (cfg_lp1_cmo_126_we), + .wd (cfg_lp1_cmo_126_wd), // from internal hardware .de (1'b0), @@ -4684,26 +6794,26 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[62].q ), + .q (reg2hw.cfg_lp1_cmo[126].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_62_qs) + .qs (cfg_lp1_cmo_126_qs) ); - // Subregister 63 of Multireg cfg_lp1_cmo_addr - // R[cfg_lp1_cmo_addr_63]: V(False) + // Subregister 127 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_127]: V(False) prim_subreg #( - .DW (32), + .DW (3), .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_cfg_lp1_cmo_addr_63 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_127 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (cfg_lp1_cmo_addr_63_we), - .wd (cfg_lp1_cmo_addr_63_wd), + .we (cfg_lp1_cmo_127_we), + .wd (cfg_lp1_cmo_127_wd), // from internal hardware .de (1'b0), @@ -4711,5176 +6821,30522 @@ module cachepool_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.cfg_lp1_cmo_addr[63].q ), + .q (reg2hw.cfg_lp1_cmo[127].q ), // to register interface (read) - .qs (cfg_lp1_cmo_addr_63_qs) + .qs (cfg_lp1_cmo_127_qs) ); - - - // Subregister 0 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_0]: V(False) + // Subregister 128 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_128]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_0 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_128 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_0_we), - .wd (lp1_cmo_commit_0_wd), + .we (cfg_lp1_cmo_128_we), + .wd (cfg_lp1_cmo_128_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[0].de), - .d (hw2reg.lp1_cmo_commit[0].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[0].q ), + .q (reg2hw.cfg_lp1_cmo[128].q ), // to register interface (read) - .qs (lp1_cmo_commit_0_qs) + .qs (cfg_lp1_cmo_128_qs) ); - // Subregister 1 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_1]: V(False) + // Subregister 129 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_129]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_1 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_129 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_1_we), - .wd (lp1_cmo_commit_1_wd), + .we (cfg_lp1_cmo_129_we), + .wd (cfg_lp1_cmo_129_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[1].de), - .d (hw2reg.lp1_cmo_commit[1].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[1].q ), + .q (reg2hw.cfg_lp1_cmo[129].q ), // to register interface (read) - .qs (lp1_cmo_commit_1_qs) + .qs (cfg_lp1_cmo_129_qs) ); - // Subregister 2 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_2]: V(False) + // Subregister 130 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_130]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_2 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_130 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_2_we), - .wd (lp1_cmo_commit_2_wd), + .we (cfg_lp1_cmo_130_we), + .wd (cfg_lp1_cmo_130_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[2].de), - .d (hw2reg.lp1_cmo_commit[2].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[2].q ), + .q (reg2hw.cfg_lp1_cmo[130].q ), // to register interface (read) - .qs (lp1_cmo_commit_2_qs) + .qs (cfg_lp1_cmo_130_qs) ); - // Subregister 3 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_3]: V(False) + // Subregister 131 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_131]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_3 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_131 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_3_we), - .wd (lp1_cmo_commit_3_wd), + .we (cfg_lp1_cmo_131_we), + .wd (cfg_lp1_cmo_131_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[3].de), - .d (hw2reg.lp1_cmo_commit[3].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[3].q ), + .q (reg2hw.cfg_lp1_cmo[131].q ), // to register interface (read) - .qs (lp1_cmo_commit_3_qs) + .qs (cfg_lp1_cmo_131_qs) ); - // Subregister 4 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_4]: V(False) + // Subregister 132 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_132]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_4 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_132 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_4_we), - .wd (lp1_cmo_commit_4_wd), + .we (cfg_lp1_cmo_132_we), + .wd (cfg_lp1_cmo_132_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[4].de), - .d (hw2reg.lp1_cmo_commit[4].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[4].q ), + .q (reg2hw.cfg_lp1_cmo[132].q ), // to register interface (read) - .qs (lp1_cmo_commit_4_qs) + .qs (cfg_lp1_cmo_132_qs) ); - // Subregister 5 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_5]: V(False) + // Subregister 133 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_133]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_5 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_133 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_5_we), - .wd (lp1_cmo_commit_5_wd), + .we (cfg_lp1_cmo_133_we), + .wd (cfg_lp1_cmo_133_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[5].de), - .d (hw2reg.lp1_cmo_commit[5].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[5].q ), + .q (reg2hw.cfg_lp1_cmo[133].q ), // to register interface (read) - .qs (lp1_cmo_commit_5_qs) + .qs (cfg_lp1_cmo_133_qs) ); - // Subregister 6 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_6]: V(False) + // Subregister 134 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_134]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_6 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_134 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_6_we), - .wd (lp1_cmo_commit_6_wd), + .we (cfg_lp1_cmo_134_we), + .wd (cfg_lp1_cmo_134_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[6].de), - .d (hw2reg.lp1_cmo_commit[6].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[6].q ), + .q (reg2hw.cfg_lp1_cmo[134].q ), // to register interface (read) - .qs (lp1_cmo_commit_6_qs) + .qs (cfg_lp1_cmo_134_qs) ); - // Subregister 7 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_7]: V(False) + // Subregister 135 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_135]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_7 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_135 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_7_we), - .wd (lp1_cmo_commit_7_wd), + .we (cfg_lp1_cmo_135_we), + .wd (cfg_lp1_cmo_135_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[7].de), - .d (hw2reg.lp1_cmo_commit[7].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[7].q ), + .q (reg2hw.cfg_lp1_cmo[135].q ), // to register interface (read) - .qs (lp1_cmo_commit_7_qs) + .qs (cfg_lp1_cmo_135_qs) ); - // Subregister 8 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_8]: V(False) + // Subregister 136 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_136]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_8 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_136 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_8_we), - .wd (lp1_cmo_commit_8_wd), + .we (cfg_lp1_cmo_136_we), + .wd (cfg_lp1_cmo_136_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[8].de), - .d (hw2reg.lp1_cmo_commit[8].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[8].q ), + .q (reg2hw.cfg_lp1_cmo[136].q ), // to register interface (read) - .qs (lp1_cmo_commit_8_qs) + .qs (cfg_lp1_cmo_136_qs) ); - // Subregister 9 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_9]: V(False) + // Subregister 137 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_137]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_9 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_137 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_9_we), - .wd (lp1_cmo_commit_9_wd), + .we (cfg_lp1_cmo_137_we), + .wd (cfg_lp1_cmo_137_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[9].de), - .d (hw2reg.lp1_cmo_commit[9].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[9].q ), + .q (reg2hw.cfg_lp1_cmo[137].q ), // to register interface (read) - .qs (lp1_cmo_commit_9_qs) + .qs (cfg_lp1_cmo_137_qs) ); - // Subregister 10 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_10]: V(False) + // Subregister 138 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_138]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_10 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_138 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_10_we), - .wd (lp1_cmo_commit_10_wd), + .we (cfg_lp1_cmo_138_we), + .wd (cfg_lp1_cmo_138_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[10].de), - .d (hw2reg.lp1_cmo_commit[10].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[10].q ), + .q (reg2hw.cfg_lp1_cmo[138].q ), // to register interface (read) - .qs (lp1_cmo_commit_10_qs) + .qs (cfg_lp1_cmo_138_qs) ); - // Subregister 11 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_11]: V(False) + // Subregister 139 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_139]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_11 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_139 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_11_we), - .wd (lp1_cmo_commit_11_wd), + .we (cfg_lp1_cmo_139_we), + .wd (cfg_lp1_cmo_139_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[11].de), - .d (hw2reg.lp1_cmo_commit[11].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[11].q ), + .q (reg2hw.cfg_lp1_cmo[139].q ), // to register interface (read) - .qs (lp1_cmo_commit_11_qs) + .qs (cfg_lp1_cmo_139_qs) ); - // Subregister 12 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_12]: V(False) + // Subregister 140 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_140]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_12 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_140 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_12_we), - .wd (lp1_cmo_commit_12_wd), + .we (cfg_lp1_cmo_140_we), + .wd (cfg_lp1_cmo_140_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[12].de), - .d (hw2reg.lp1_cmo_commit[12].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[12].q ), + .q (reg2hw.cfg_lp1_cmo[140].q ), // to register interface (read) - .qs (lp1_cmo_commit_12_qs) + .qs (cfg_lp1_cmo_140_qs) ); - // Subregister 13 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_13]: V(False) + // Subregister 141 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_141]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_13 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_141 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_13_we), - .wd (lp1_cmo_commit_13_wd), + .we (cfg_lp1_cmo_141_we), + .wd (cfg_lp1_cmo_141_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[13].de), - .d (hw2reg.lp1_cmo_commit[13].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[13].q ), + .q (reg2hw.cfg_lp1_cmo[141].q ), // to register interface (read) - .qs (lp1_cmo_commit_13_qs) + .qs (cfg_lp1_cmo_141_qs) ); - // Subregister 14 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_14]: V(False) + // Subregister 142 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_142]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_14 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_142 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_14_we), - .wd (lp1_cmo_commit_14_wd), + .we (cfg_lp1_cmo_142_we), + .wd (cfg_lp1_cmo_142_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[14].de), - .d (hw2reg.lp1_cmo_commit[14].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[14].q ), + .q (reg2hw.cfg_lp1_cmo[142].q ), // to register interface (read) - .qs (lp1_cmo_commit_14_qs) + .qs (cfg_lp1_cmo_142_qs) ); - // Subregister 15 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_15]: V(False) + // Subregister 143 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_143]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_15 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_143 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_15_we), - .wd (lp1_cmo_commit_15_wd), + .we (cfg_lp1_cmo_143_we), + .wd (cfg_lp1_cmo_143_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[15].de), - .d (hw2reg.lp1_cmo_commit[15].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[15].q ), + .q (reg2hw.cfg_lp1_cmo[143].q ), // to register interface (read) - .qs (lp1_cmo_commit_15_qs) + .qs (cfg_lp1_cmo_143_qs) ); - // Subregister 16 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_16]: V(False) + // Subregister 144 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_144]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_16 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_144 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_16_we), - .wd (lp1_cmo_commit_16_wd), + .we (cfg_lp1_cmo_144_we), + .wd (cfg_lp1_cmo_144_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[16].de), - .d (hw2reg.lp1_cmo_commit[16].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[16].q ), + .q (reg2hw.cfg_lp1_cmo[144].q ), // to register interface (read) - .qs (lp1_cmo_commit_16_qs) + .qs (cfg_lp1_cmo_144_qs) ); - // Subregister 17 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_17]: V(False) + // Subregister 145 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_145]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_17 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_145 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_17_we), - .wd (lp1_cmo_commit_17_wd), + .we (cfg_lp1_cmo_145_we), + .wd (cfg_lp1_cmo_145_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[17].de), - .d (hw2reg.lp1_cmo_commit[17].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[17].q ), + .q (reg2hw.cfg_lp1_cmo[145].q ), // to register interface (read) - .qs (lp1_cmo_commit_17_qs) + .qs (cfg_lp1_cmo_145_qs) ); - // Subregister 18 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_18]: V(False) + // Subregister 146 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_146]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_18 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_146 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_18_we), - .wd (lp1_cmo_commit_18_wd), + .we (cfg_lp1_cmo_146_we), + .wd (cfg_lp1_cmo_146_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[18].de), - .d (hw2reg.lp1_cmo_commit[18].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[18].q ), + .q (reg2hw.cfg_lp1_cmo[146].q ), // to register interface (read) - .qs (lp1_cmo_commit_18_qs) + .qs (cfg_lp1_cmo_146_qs) ); - // Subregister 19 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_19]: V(False) + // Subregister 147 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_147]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_19 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_147 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_19_we), - .wd (lp1_cmo_commit_19_wd), + .we (cfg_lp1_cmo_147_we), + .wd (cfg_lp1_cmo_147_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[19].de), - .d (hw2reg.lp1_cmo_commit[19].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[19].q ), + .q (reg2hw.cfg_lp1_cmo[147].q ), // to register interface (read) - .qs (lp1_cmo_commit_19_qs) + .qs (cfg_lp1_cmo_147_qs) ); - // Subregister 20 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_20]: V(False) + // Subregister 148 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_148]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_20 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_148 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_20_we), - .wd (lp1_cmo_commit_20_wd), + .we (cfg_lp1_cmo_148_we), + .wd (cfg_lp1_cmo_148_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[20].de), - .d (hw2reg.lp1_cmo_commit[20].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[20].q ), + .q (reg2hw.cfg_lp1_cmo[148].q ), // to register interface (read) - .qs (lp1_cmo_commit_20_qs) + .qs (cfg_lp1_cmo_148_qs) ); - // Subregister 21 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_21]: V(False) + // Subregister 149 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_149]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_21 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_149 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_21_we), - .wd (lp1_cmo_commit_21_wd), + .we (cfg_lp1_cmo_149_we), + .wd (cfg_lp1_cmo_149_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[21].de), - .d (hw2reg.lp1_cmo_commit[21].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[21].q ), + .q (reg2hw.cfg_lp1_cmo[149].q ), // to register interface (read) - .qs (lp1_cmo_commit_21_qs) + .qs (cfg_lp1_cmo_149_qs) ); - // Subregister 22 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_22]: V(False) + // Subregister 150 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_150]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_22 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_150 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_22_we), - .wd (lp1_cmo_commit_22_wd), + .we (cfg_lp1_cmo_150_we), + .wd (cfg_lp1_cmo_150_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[22].de), - .d (hw2reg.lp1_cmo_commit[22].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[22].q ), + .q (reg2hw.cfg_lp1_cmo[150].q ), // to register interface (read) - .qs (lp1_cmo_commit_22_qs) + .qs (cfg_lp1_cmo_150_qs) ); - // Subregister 23 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_23]: V(False) + // Subregister 151 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_151]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_23 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_151 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_23_we), - .wd (lp1_cmo_commit_23_wd), + .we (cfg_lp1_cmo_151_we), + .wd (cfg_lp1_cmo_151_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[23].de), - .d (hw2reg.lp1_cmo_commit[23].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[23].q ), + .q (reg2hw.cfg_lp1_cmo[151].q ), // to register interface (read) - .qs (lp1_cmo_commit_23_qs) + .qs (cfg_lp1_cmo_151_qs) ); - // Subregister 24 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_24]: V(False) + // Subregister 152 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_152]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_24 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_152 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_24_we), - .wd (lp1_cmo_commit_24_wd), + .we (cfg_lp1_cmo_152_we), + .wd (cfg_lp1_cmo_152_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[24].de), - .d (hw2reg.lp1_cmo_commit[24].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[24].q ), + .q (reg2hw.cfg_lp1_cmo[152].q ), // to register interface (read) - .qs (lp1_cmo_commit_24_qs) + .qs (cfg_lp1_cmo_152_qs) ); - // Subregister 25 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_25]: V(False) + // Subregister 153 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_153]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_25 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_153 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_25_we), - .wd (lp1_cmo_commit_25_wd), + .we (cfg_lp1_cmo_153_we), + .wd (cfg_lp1_cmo_153_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[25].de), - .d (hw2reg.lp1_cmo_commit[25].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[25].q ), + .q (reg2hw.cfg_lp1_cmo[153].q ), // to register interface (read) - .qs (lp1_cmo_commit_25_qs) + .qs (cfg_lp1_cmo_153_qs) ); - // Subregister 26 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_26]: V(False) + // Subregister 154 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_154]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_26 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_154 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_26_we), - .wd (lp1_cmo_commit_26_wd), + .we (cfg_lp1_cmo_154_we), + .wd (cfg_lp1_cmo_154_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[26].de), - .d (hw2reg.lp1_cmo_commit[26].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[26].q ), + .q (reg2hw.cfg_lp1_cmo[154].q ), // to register interface (read) - .qs (lp1_cmo_commit_26_qs) + .qs (cfg_lp1_cmo_154_qs) ); - // Subregister 27 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_27]: V(False) + // Subregister 155 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_155]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_27 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_155 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_27_we), - .wd (lp1_cmo_commit_27_wd), + .we (cfg_lp1_cmo_155_we), + .wd (cfg_lp1_cmo_155_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[27].de), - .d (hw2reg.lp1_cmo_commit[27].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[27].q ), + .q (reg2hw.cfg_lp1_cmo[155].q ), // to register interface (read) - .qs (lp1_cmo_commit_27_qs) + .qs (cfg_lp1_cmo_155_qs) ); - // Subregister 28 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_28]: V(False) + // Subregister 156 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_156]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_28 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_156 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_28_we), - .wd (lp1_cmo_commit_28_wd), + .we (cfg_lp1_cmo_156_we), + .wd (cfg_lp1_cmo_156_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[28].de), - .d (hw2reg.lp1_cmo_commit[28].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[28].q ), + .q (reg2hw.cfg_lp1_cmo[156].q ), // to register interface (read) - .qs (lp1_cmo_commit_28_qs) + .qs (cfg_lp1_cmo_156_qs) ); - // Subregister 29 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_29]: V(False) + // Subregister 157 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_157]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_29 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_157 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_29_we), - .wd (lp1_cmo_commit_29_wd), + .we (cfg_lp1_cmo_157_we), + .wd (cfg_lp1_cmo_157_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[29].de), - .d (hw2reg.lp1_cmo_commit[29].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[29].q ), + .q (reg2hw.cfg_lp1_cmo[157].q ), // to register interface (read) - .qs (lp1_cmo_commit_29_qs) + .qs (cfg_lp1_cmo_157_qs) ); - // Subregister 30 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_30]: V(False) + // Subregister 158 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_158]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_30 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_158 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_30_we), - .wd (lp1_cmo_commit_30_wd), + .we (cfg_lp1_cmo_158_we), + .wd (cfg_lp1_cmo_158_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[30].de), - .d (hw2reg.lp1_cmo_commit[30].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[30].q ), + .q (reg2hw.cfg_lp1_cmo[158].q ), // to register interface (read) - .qs (lp1_cmo_commit_30_qs) + .qs (cfg_lp1_cmo_158_qs) ); - // Subregister 31 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_31]: V(False) + // Subregister 159 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_159]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_31 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_159 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_31_we), - .wd (lp1_cmo_commit_31_wd), + .we (cfg_lp1_cmo_159_we), + .wd (cfg_lp1_cmo_159_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[31].de), - .d (hw2reg.lp1_cmo_commit[31].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[31].q ), + .q (reg2hw.cfg_lp1_cmo[159].q ), // to register interface (read) - .qs (lp1_cmo_commit_31_qs) + .qs (cfg_lp1_cmo_159_qs) ); - // Subregister 32 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_32]: V(False) + // Subregister 160 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_160]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_32 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_160 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_32_we), - .wd (lp1_cmo_commit_32_wd), + .we (cfg_lp1_cmo_160_we), + .wd (cfg_lp1_cmo_160_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[32].de), - .d (hw2reg.lp1_cmo_commit[32].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[32].q ), + .q (reg2hw.cfg_lp1_cmo[160].q ), // to register interface (read) - .qs (lp1_cmo_commit_32_qs) + .qs (cfg_lp1_cmo_160_qs) ); - // Subregister 33 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_33]: V(False) + // Subregister 161 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_161]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_33 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_161 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_33_we), - .wd (lp1_cmo_commit_33_wd), + .we (cfg_lp1_cmo_161_we), + .wd (cfg_lp1_cmo_161_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[33].de), - .d (hw2reg.lp1_cmo_commit[33].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[33].q ), + .q (reg2hw.cfg_lp1_cmo[161].q ), // to register interface (read) - .qs (lp1_cmo_commit_33_qs) + .qs (cfg_lp1_cmo_161_qs) ); - // Subregister 34 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_34]: V(False) + // Subregister 162 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_162]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_34 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_162 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_34_we), - .wd (lp1_cmo_commit_34_wd), + .we (cfg_lp1_cmo_162_we), + .wd (cfg_lp1_cmo_162_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[34].de), - .d (hw2reg.lp1_cmo_commit[34].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[34].q ), + .q (reg2hw.cfg_lp1_cmo[162].q ), // to register interface (read) - .qs (lp1_cmo_commit_34_qs) + .qs (cfg_lp1_cmo_162_qs) ); - // Subregister 35 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_35]: V(False) + // Subregister 163 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_163]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_35 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_163 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_35_we), - .wd (lp1_cmo_commit_35_wd), + .we (cfg_lp1_cmo_163_we), + .wd (cfg_lp1_cmo_163_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[35].de), - .d (hw2reg.lp1_cmo_commit[35].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[35].q ), + .q (reg2hw.cfg_lp1_cmo[163].q ), // to register interface (read) - .qs (lp1_cmo_commit_35_qs) + .qs (cfg_lp1_cmo_163_qs) ); - // Subregister 36 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_36]: V(False) + // Subregister 164 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_164]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_36 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_164 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_36_we), - .wd (lp1_cmo_commit_36_wd), + .we (cfg_lp1_cmo_164_we), + .wd (cfg_lp1_cmo_164_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[36].de), - .d (hw2reg.lp1_cmo_commit[36].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[36].q ), + .q (reg2hw.cfg_lp1_cmo[164].q ), // to register interface (read) - .qs (lp1_cmo_commit_36_qs) + .qs (cfg_lp1_cmo_164_qs) ); - // Subregister 37 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_37]: V(False) + // Subregister 165 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_165]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_37 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_165 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_37_we), - .wd (lp1_cmo_commit_37_wd), + .we (cfg_lp1_cmo_165_we), + .wd (cfg_lp1_cmo_165_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[37].de), - .d (hw2reg.lp1_cmo_commit[37].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[37].q ), + .q (reg2hw.cfg_lp1_cmo[165].q ), // to register interface (read) - .qs (lp1_cmo_commit_37_qs) + .qs (cfg_lp1_cmo_165_qs) ); - // Subregister 38 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_38]: V(False) + // Subregister 166 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_166]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_38 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_166 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_38_we), - .wd (lp1_cmo_commit_38_wd), + .we (cfg_lp1_cmo_166_we), + .wd (cfg_lp1_cmo_166_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[38].de), - .d (hw2reg.lp1_cmo_commit[38].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[38].q ), + .q (reg2hw.cfg_lp1_cmo[166].q ), // to register interface (read) - .qs (lp1_cmo_commit_38_qs) + .qs (cfg_lp1_cmo_166_qs) ); - // Subregister 39 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_39]: V(False) + // Subregister 167 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_167]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_39 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_167 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_39_we), - .wd (lp1_cmo_commit_39_wd), + .we (cfg_lp1_cmo_167_we), + .wd (cfg_lp1_cmo_167_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[39].de), - .d (hw2reg.lp1_cmo_commit[39].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[39].q ), + .q (reg2hw.cfg_lp1_cmo[167].q ), // to register interface (read) - .qs (lp1_cmo_commit_39_qs) + .qs (cfg_lp1_cmo_167_qs) ); - // Subregister 40 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_40]: V(False) + // Subregister 168 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_168]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_40 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_168 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_40_we), - .wd (lp1_cmo_commit_40_wd), + .we (cfg_lp1_cmo_168_we), + .wd (cfg_lp1_cmo_168_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[40].de), - .d (hw2reg.lp1_cmo_commit[40].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[40].q ), + .q (reg2hw.cfg_lp1_cmo[168].q ), // to register interface (read) - .qs (lp1_cmo_commit_40_qs) + .qs (cfg_lp1_cmo_168_qs) ); - // Subregister 41 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_41]: V(False) + // Subregister 169 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_169]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_41 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_169 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_41_we), - .wd (lp1_cmo_commit_41_wd), + .we (cfg_lp1_cmo_169_we), + .wd (cfg_lp1_cmo_169_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[41].de), - .d (hw2reg.lp1_cmo_commit[41].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[41].q ), + .q (reg2hw.cfg_lp1_cmo[169].q ), // to register interface (read) - .qs (lp1_cmo_commit_41_qs) + .qs (cfg_lp1_cmo_169_qs) ); - // Subregister 42 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_42]: V(False) + // Subregister 170 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_170]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_42 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_170 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_42_we), - .wd (lp1_cmo_commit_42_wd), + .we (cfg_lp1_cmo_170_we), + .wd (cfg_lp1_cmo_170_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[42].de), - .d (hw2reg.lp1_cmo_commit[42].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[42].q ), + .q (reg2hw.cfg_lp1_cmo[170].q ), // to register interface (read) - .qs (lp1_cmo_commit_42_qs) + .qs (cfg_lp1_cmo_170_qs) ); - // Subregister 43 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_43]: V(False) + // Subregister 171 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_171]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_43 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_171 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_43_we), - .wd (lp1_cmo_commit_43_wd), + .we (cfg_lp1_cmo_171_we), + .wd (cfg_lp1_cmo_171_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[43].de), - .d (hw2reg.lp1_cmo_commit[43].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[43].q ), + .q (reg2hw.cfg_lp1_cmo[171].q ), // to register interface (read) - .qs (lp1_cmo_commit_43_qs) + .qs (cfg_lp1_cmo_171_qs) ); - // Subregister 44 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_44]: V(False) + // Subregister 172 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_172]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_44 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_172 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_44_we), - .wd (lp1_cmo_commit_44_wd), + .we (cfg_lp1_cmo_172_we), + .wd (cfg_lp1_cmo_172_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[44].de), - .d (hw2reg.lp1_cmo_commit[44].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[44].q ), + .q (reg2hw.cfg_lp1_cmo[172].q ), // to register interface (read) - .qs (lp1_cmo_commit_44_qs) + .qs (cfg_lp1_cmo_172_qs) ); - // Subregister 45 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_45]: V(False) + // Subregister 173 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_173]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_45 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_173 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_45_we), - .wd (lp1_cmo_commit_45_wd), + .we (cfg_lp1_cmo_173_we), + .wd (cfg_lp1_cmo_173_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[45].de), - .d (hw2reg.lp1_cmo_commit[45].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[45].q ), + .q (reg2hw.cfg_lp1_cmo[173].q ), // to register interface (read) - .qs (lp1_cmo_commit_45_qs) + .qs (cfg_lp1_cmo_173_qs) ); - // Subregister 46 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_46]: V(False) + // Subregister 174 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_174]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_46 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_174 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_46_we), - .wd (lp1_cmo_commit_46_wd), + .we (cfg_lp1_cmo_174_we), + .wd (cfg_lp1_cmo_174_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[46].de), - .d (hw2reg.lp1_cmo_commit[46].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[46].q ), + .q (reg2hw.cfg_lp1_cmo[174].q ), // to register interface (read) - .qs (lp1_cmo_commit_46_qs) + .qs (cfg_lp1_cmo_174_qs) ); - // Subregister 47 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_47]: V(False) + // Subregister 175 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_175]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_47 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_175 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_47_we), - .wd (lp1_cmo_commit_47_wd), + .we (cfg_lp1_cmo_175_we), + .wd (cfg_lp1_cmo_175_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[47].de), - .d (hw2reg.lp1_cmo_commit[47].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[47].q ), + .q (reg2hw.cfg_lp1_cmo[175].q ), // to register interface (read) - .qs (lp1_cmo_commit_47_qs) + .qs (cfg_lp1_cmo_175_qs) ); - // Subregister 48 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_48]: V(False) + // Subregister 176 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_176]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_48 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_176 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_48_we), - .wd (lp1_cmo_commit_48_wd), + .we (cfg_lp1_cmo_176_we), + .wd (cfg_lp1_cmo_176_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[48].de), - .d (hw2reg.lp1_cmo_commit[48].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[48].q ), + .q (reg2hw.cfg_lp1_cmo[176].q ), // to register interface (read) - .qs (lp1_cmo_commit_48_qs) + .qs (cfg_lp1_cmo_176_qs) ); - // Subregister 49 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_49]: V(False) + // Subregister 177 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_177]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_49 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_177 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_49_we), - .wd (lp1_cmo_commit_49_wd), + .we (cfg_lp1_cmo_177_we), + .wd (cfg_lp1_cmo_177_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[49].de), - .d (hw2reg.lp1_cmo_commit[49].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[49].q ), + .q (reg2hw.cfg_lp1_cmo[177].q ), // to register interface (read) - .qs (lp1_cmo_commit_49_qs) + .qs (cfg_lp1_cmo_177_qs) ); - // Subregister 50 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_50]: V(False) + // Subregister 178 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_178]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_50 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_178 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_50_we), - .wd (lp1_cmo_commit_50_wd), + .we (cfg_lp1_cmo_178_we), + .wd (cfg_lp1_cmo_178_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[50].de), - .d (hw2reg.lp1_cmo_commit[50].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[50].q ), + .q (reg2hw.cfg_lp1_cmo[178].q ), // to register interface (read) - .qs (lp1_cmo_commit_50_qs) + .qs (cfg_lp1_cmo_178_qs) ); - // Subregister 51 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_51]: V(False) + // Subregister 179 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_179]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_51 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_179 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_51_we), - .wd (lp1_cmo_commit_51_wd), + .we (cfg_lp1_cmo_179_we), + .wd (cfg_lp1_cmo_179_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[51].de), - .d (hw2reg.lp1_cmo_commit[51].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[51].q ), + .q (reg2hw.cfg_lp1_cmo[179].q ), // to register interface (read) - .qs (lp1_cmo_commit_51_qs) + .qs (cfg_lp1_cmo_179_qs) ); - // Subregister 52 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_52]: V(False) + // Subregister 180 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_180]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_52 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_180 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_52_we), - .wd (lp1_cmo_commit_52_wd), + .we (cfg_lp1_cmo_180_we), + .wd (cfg_lp1_cmo_180_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[52].de), - .d (hw2reg.lp1_cmo_commit[52].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[52].q ), + .q (reg2hw.cfg_lp1_cmo[180].q ), // to register interface (read) - .qs (lp1_cmo_commit_52_qs) + .qs (cfg_lp1_cmo_180_qs) ); - // Subregister 53 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_53]: V(False) + // Subregister 181 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_181]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_53 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_181 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_53_we), - .wd (lp1_cmo_commit_53_wd), + .we (cfg_lp1_cmo_181_we), + .wd (cfg_lp1_cmo_181_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[53].de), - .d (hw2reg.lp1_cmo_commit[53].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[53].q ), + .q (reg2hw.cfg_lp1_cmo[181].q ), // to register interface (read) - .qs (lp1_cmo_commit_53_qs) + .qs (cfg_lp1_cmo_181_qs) ); - // Subregister 54 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_54]: V(False) + // Subregister 182 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_182]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_54 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_182 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_54_we), - .wd (lp1_cmo_commit_54_wd), + .we (cfg_lp1_cmo_182_we), + .wd (cfg_lp1_cmo_182_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[54].de), - .d (hw2reg.lp1_cmo_commit[54].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[54].q ), + .q (reg2hw.cfg_lp1_cmo[182].q ), // to register interface (read) - .qs (lp1_cmo_commit_54_qs) + .qs (cfg_lp1_cmo_182_qs) ); - // Subregister 55 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_55]: V(False) + // Subregister 183 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_183]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_55 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_183 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_55_we), - .wd (lp1_cmo_commit_55_wd), + .we (cfg_lp1_cmo_183_we), + .wd (cfg_lp1_cmo_183_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[55].de), - .d (hw2reg.lp1_cmo_commit[55].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[55].q ), + .q (reg2hw.cfg_lp1_cmo[183].q ), // to register interface (read) - .qs (lp1_cmo_commit_55_qs) + .qs (cfg_lp1_cmo_183_qs) ); - // Subregister 56 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_56]: V(False) + // Subregister 184 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_184]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_56 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_184 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_56_we), - .wd (lp1_cmo_commit_56_wd), + .we (cfg_lp1_cmo_184_we), + .wd (cfg_lp1_cmo_184_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[56].de), - .d (hw2reg.lp1_cmo_commit[56].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[56].q ), + .q (reg2hw.cfg_lp1_cmo[184].q ), // to register interface (read) - .qs (lp1_cmo_commit_56_qs) + .qs (cfg_lp1_cmo_184_qs) ); - // Subregister 57 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_57]: V(False) + // Subregister 185 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_185]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_57 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_185 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_57_we), - .wd (lp1_cmo_commit_57_wd), + .we (cfg_lp1_cmo_185_we), + .wd (cfg_lp1_cmo_185_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[57].de), - .d (hw2reg.lp1_cmo_commit[57].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[57].q ), + .q (reg2hw.cfg_lp1_cmo[185].q ), // to register interface (read) - .qs (lp1_cmo_commit_57_qs) + .qs (cfg_lp1_cmo_185_qs) ); - // Subregister 58 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_58]: V(False) + // Subregister 186 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_186]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_58 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_186 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_58_we), - .wd (lp1_cmo_commit_58_wd), + .we (cfg_lp1_cmo_186_we), + .wd (cfg_lp1_cmo_186_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[58].de), - .d (hw2reg.lp1_cmo_commit[58].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[58].q ), + .q (reg2hw.cfg_lp1_cmo[186].q ), // to register interface (read) - .qs (lp1_cmo_commit_58_qs) + .qs (cfg_lp1_cmo_186_qs) ); - // Subregister 59 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_59]: V(False) + // Subregister 187 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_187]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_59 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_187 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_59_we), - .wd (lp1_cmo_commit_59_wd), + .we (cfg_lp1_cmo_187_we), + .wd (cfg_lp1_cmo_187_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[59].de), - .d (hw2reg.lp1_cmo_commit[59].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[59].q ), + .q (reg2hw.cfg_lp1_cmo[187].q ), // to register interface (read) - .qs (lp1_cmo_commit_59_qs) + .qs (cfg_lp1_cmo_187_qs) ); - // Subregister 60 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_60]: V(False) + // Subregister 188 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_188]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_60 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_188 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_60_we), - .wd (lp1_cmo_commit_60_wd), + .we (cfg_lp1_cmo_188_we), + .wd (cfg_lp1_cmo_188_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[60].de), - .d (hw2reg.lp1_cmo_commit[60].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[60].q ), + .q (reg2hw.cfg_lp1_cmo[188].q ), // to register interface (read) - .qs (lp1_cmo_commit_60_qs) + .qs (cfg_lp1_cmo_188_qs) ); - // Subregister 61 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_61]: V(False) + // Subregister 189 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_189]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_61 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_189 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_61_we), - .wd (lp1_cmo_commit_61_wd), + .we (cfg_lp1_cmo_189_we), + .wd (cfg_lp1_cmo_189_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[61].de), - .d (hw2reg.lp1_cmo_commit[61].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[61].q ), + .q (reg2hw.cfg_lp1_cmo[189].q ), // to register interface (read) - .qs (lp1_cmo_commit_61_qs) + .qs (cfg_lp1_cmo_189_qs) ); - // Subregister 62 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_62]: V(False) + // Subregister 190 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_190]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_62 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_190 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_62_we), - .wd (lp1_cmo_commit_62_wd), + .we (cfg_lp1_cmo_190_we), + .wd (cfg_lp1_cmo_190_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[62].de), - .d (hw2reg.lp1_cmo_commit[62].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[62].q ), + .q (reg2hw.cfg_lp1_cmo[190].q ), // to register interface (read) - .qs (lp1_cmo_commit_62_qs) + .qs (cfg_lp1_cmo_190_qs) ); - // Subregister 63 of Multireg lp1_cmo_commit - // R[lp1_cmo_commit_63]: V(False) + // Subregister 191 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_191]: V(False) prim_subreg #( - .DW (1), + .DW (3), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_lp1_cmo_commit_63 ( + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_191 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (lp1_cmo_commit_63_we), - .wd (lp1_cmo_commit_63_wd), + .we (cfg_lp1_cmo_191_we), + .wd (cfg_lp1_cmo_191_wd), // from internal hardware - .de (hw2reg.lp1_cmo_commit[63].de), - .d (hw2reg.lp1_cmo_commit[63].d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (reg2hw.lp1_cmo_commit[63].q ), + .q (reg2hw.cfg_lp1_cmo[191].q ), // to register interface (read) - .qs (lp1_cmo_commit_63_qs) + .qs (cfg_lp1_cmo_191_qs) ); + // Subregister 192 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_192]: V(False) + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_192 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 0 of Multireg lp1_cmo_status - // R[lp1_cmo_status_0]: V(True) + // from register interface + .we (cfg_lp1_cmo_192_we), + .wd (cfg_lp1_cmo_192_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_0 ( - .re (lp1_cmo_status_0_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[0].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_0_qs) + .q (reg2hw.cfg_lp1_cmo[192].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_192_qs) ); - // Subregister 1 of Multireg lp1_cmo_status - // R[lp1_cmo_status_1]: V(True) + // Subregister 193 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_193]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_1 ( - .re (lp1_cmo_status_1_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[1].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_1_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_193 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 2 of Multireg lp1_cmo_status - // R[lp1_cmo_status_2]: V(True) + // from register interface + .we (cfg_lp1_cmo_193_we), + .wd (cfg_lp1_cmo_193_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_2 ( - .re (lp1_cmo_status_2_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[2].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_2_qs) + .q (reg2hw.cfg_lp1_cmo[193].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_193_qs) ); - // Subregister 3 of Multireg lp1_cmo_status - // R[lp1_cmo_status_3]: V(True) + // Subregister 194 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_194]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_3 ( - .re (lp1_cmo_status_3_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[3].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_194 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_194_we), + .wd (cfg_lp1_cmo_194_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_3_qs) + .q (reg2hw.cfg_lp1_cmo[194].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_194_qs) ); - // Subregister 4 of Multireg lp1_cmo_status - // R[lp1_cmo_status_4]: V(True) + // Subregister 195 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_195]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_4 ( - .re (lp1_cmo_status_4_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[4].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_195 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_195_we), + .wd (cfg_lp1_cmo_195_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_4_qs) + .q (reg2hw.cfg_lp1_cmo[195].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_195_qs) ); - // Subregister 5 of Multireg lp1_cmo_status - // R[lp1_cmo_status_5]: V(True) + // Subregister 196 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_196]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_5 ( - .re (lp1_cmo_status_5_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[5].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_5_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_196 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 6 of Multireg lp1_cmo_status - // R[lp1_cmo_status_6]: V(True) + // from register interface + .we (cfg_lp1_cmo_196_we), + .wd (cfg_lp1_cmo_196_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_6 ( - .re (lp1_cmo_status_6_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[6].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_6_qs) + .q (reg2hw.cfg_lp1_cmo[196].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_196_qs) ); - // Subregister 7 of Multireg lp1_cmo_status - // R[lp1_cmo_status_7]: V(True) + // Subregister 197 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_197]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_7 ( - .re (lp1_cmo_status_7_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[7].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_7_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_197 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 8 of Multireg lp1_cmo_status - // R[lp1_cmo_status_8]: V(True) + // from register interface + .we (cfg_lp1_cmo_197_we), + .wd (cfg_lp1_cmo_197_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_8 ( - .re (lp1_cmo_status_8_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[8].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_8_qs) + .q (reg2hw.cfg_lp1_cmo[197].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_197_qs) ); - // Subregister 9 of Multireg lp1_cmo_status - // R[lp1_cmo_status_9]: V(True) + // Subregister 198 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_198]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_9 ( - .re (lp1_cmo_status_9_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[9].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_9_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_198 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 10 of Multireg lp1_cmo_status - // R[lp1_cmo_status_10]: V(True) + // from register interface + .we (cfg_lp1_cmo_198_we), + .wd (cfg_lp1_cmo_198_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_10 ( - .re (lp1_cmo_status_10_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[10].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_10_qs) + .q (reg2hw.cfg_lp1_cmo[198].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_198_qs) ); - // Subregister 11 of Multireg lp1_cmo_status - // R[lp1_cmo_status_11]: V(True) + // Subregister 199 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_199]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_11 ( - .re (lp1_cmo_status_11_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[11].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_11_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_199 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 12 of Multireg lp1_cmo_status - // R[lp1_cmo_status_12]: V(True) + // from register interface + .we (cfg_lp1_cmo_199_we), + .wd (cfg_lp1_cmo_199_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_12 ( - .re (lp1_cmo_status_12_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[12].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_12_qs) + .q (reg2hw.cfg_lp1_cmo[199].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_199_qs) ); - // Subregister 13 of Multireg lp1_cmo_status - // R[lp1_cmo_status_13]: V(True) + // Subregister 200 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_200]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_13 ( - .re (lp1_cmo_status_13_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[13].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_13_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_200 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 14 of Multireg lp1_cmo_status - // R[lp1_cmo_status_14]: V(True) + // from register interface + .we (cfg_lp1_cmo_200_we), + .wd (cfg_lp1_cmo_200_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_14 ( - .re (lp1_cmo_status_14_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[14].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_14_qs) + .q (reg2hw.cfg_lp1_cmo[200].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_200_qs) ); - // Subregister 15 of Multireg lp1_cmo_status - // R[lp1_cmo_status_15]: V(True) + // Subregister 201 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_201]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_15 ( - .re (lp1_cmo_status_15_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[15].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_201 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_201_we), + .wd (cfg_lp1_cmo_201_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_15_qs) + .q (reg2hw.cfg_lp1_cmo[201].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_201_qs) ); - // Subregister 16 of Multireg lp1_cmo_status - // R[lp1_cmo_status_16]: V(True) + // Subregister 202 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_202]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_16 ( - .re (lp1_cmo_status_16_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[16].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_202 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_202_we), + .wd (cfg_lp1_cmo_202_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_16_qs) + .q (reg2hw.cfg_lp1_cmo[202].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_202_qs) ); - // Subregister 17 of Multireg lp1_cmo_status - // R[lp1_cmo_status_17]: V(True) + // Subregister 203 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_203]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_17 ( - .re (lp1_cmo_status_17_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[17].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_17_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_203 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 18 of Multireg lp1_cmo_status - // R[lp1_cmo_status_18]: V(True) + // from register interface + .we (cfg_lp1_cmo_203_we), + .wd (cfg_lp1_cmo_203_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_18 ( - .re (lp1_cmo_status_18_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[18].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_18_qs) + .q (reg2hw.cfg_lp1_cmo[203].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_203_qs) ); - // Subregister 19 of Multireg lp1_cmo_status - // R[lp1_cmo_status_19]: V(True) + // Subregister 204 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_204]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_19 ( - .re (lp1_cmo_status_19_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[19].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_19_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_204 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 20 of Multireg lp1_cmo_status - // R[lp1_cmo_status_20]: V(True) + // from register interface + .we (cfg_lp1_cmo_204_we), + .wd (cfg_lp1_cmo_204_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_20 ( - .re (lp1_cmo_status_20_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[20].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_20_qs) + .q (reg2hw.cfg_lp1_cmo[204].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_204_qs) ); - // Subregister 21 of Multireg lp1_cmo_status - // R[lp1_cmo_status_21]: V(True) + // Subregister 205 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_205]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_21 ( - .re (lp1_cmo_status_21_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[21].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_21_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_205 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 22 of Multireg lp1_cmo_status - // R[lp1_cmo_status_22]: V(True) + // from register interface + .we (cfg_lp1_cmo_205_we), + .wd (cfg_lp1_cmo_205_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_22 ( - .re (lp1_cmo_status_22_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[22].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_22_qs) + .q (reg2hw.cfg_lp1_cmo[205].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_205_qs) ); - // Subregister 23 of Multireg lp1_cmo_status - // R[lp1_cmo_status_23]: V(True) + // Subregister 206 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_206]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_23 ( - .re (lp1_cmo_status_23_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[23].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_23_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_206 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 24 of Multireg lp1_cmo_status - // R[lp1_cmo_status_24]: V(True) + // from register interface + .we (cfg_lp1_cmo_206_we), + .wd (cfg_lp1_cmo_206_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_24 ( - .re (lp1_cmo_status_24_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[24].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_24_qs) + .q (reg2hw.cfg_lp1_cmo[206].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_206_qs) ); - // Subregister 25 of Multireg lp1_cmo_status - // R[lp1_cmo_status_25]: V(True) + // Subregister 207 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_207]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_25 ( - .re (lp1_cmo_status_25_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[25].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_25_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_207 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 26 of Multireg lp1_cmo_status - // R[lp1_cmo_status_26]: V(True) + // from register interface + .we (cfg_lp1_cmo_207_we), + .wd (cfg_lp1_cmo_207_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_26 ( - .re (lp1_cmo_status_26_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[26].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_26_qs) + .q (reg2hw.cfg_lp1_cmo[207].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_207_qs) ); - // Subregister 27 of Multireg lp1_cmo_status - // R[lp1_cmo_status_27]: V(True) + // Subregister 208 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_208]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_27 ( - .re (lp1_cmo_status_27_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[27].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_208 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_208_we), + .wd (cfg_lp1_cmo_208_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_27_qs) + .q (reg2hw.cfg_lp1_cmo[208].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_208_qs) ); - // Subregister 28 of Multireg lp1_cmo_status - // R[lp1_cmo_status_28]: V(True) + // Subregister 209 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_209]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_28 ( - .re (lp1_cmo_status_28_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[28].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_209 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_209_we), + .wd (cfg_lp1_cmo_209_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_28_qs) + .q (reg2hw.cfg_lp1_cmo[209].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_209_qs) ); - // Subregister 29 of Multireg lp1_cmo_status - // R[lp1_cmo_status_29]: V(True) + // Subregister 210 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_210]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_29 ( - .re (lp1_cmo_status_29_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[29].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_29_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_210 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 30 of Multireg lp1_cmo_status - // R[lp1_cmo_status_30]: V(True) + // from register interface + .we (cfg_lp1_cmo_210_we), + .wd (cfg_lp1_cmo_210_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_30 ( - .re (lp1_cmo_status_30_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[30].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_30_qs) + .q (reg2hw.cfg_lp1_cmo[210].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_210_qs) ); - // Subregister 31 of Multireg lp1_cmo_status - // R[lp1_cmo_status_31]: V(True) + // Subregister 211 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_211]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_31 ( - .re (lp1_cmo_status_31_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[31].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_31_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_211 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 32 of Multireg lp1_cmo_status - // R[lp1_cmo_status_32]: V(True) + // from register interface + .we (cfg_lp1_cmo_211_we), + .wd (cfg_lp1_cmo_211_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_32 ( - .re (lp1_cmo_status_32_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[32].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_32_qs) + .q (reg2hw.cfg_lp1_cmo[211].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_211_qs) ); - // Subregister 33 of Multireg lp1_cmo_status - // R[lp1_cmo_status_33]: V(True) + // Subregister 212 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_212]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_33 ( - .re (lp1_cmo_status_33_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[33].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_33_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_212 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 34 of Multireg lp1_cmo_status - // R[lp1_cmo_status_34]: V(True) + // from register interface + .we (cfg_lp1_cmo_212_we), + .wd (cfg_lp1_cmo_212_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_34 ( - .re (lp1_cmo_status_34_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[34].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_34_qs) + .q (reg2hw.cfg_lp1_cmo[212].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_212_qs) ); - // Subregister 35 of Multireg lp1_cmo_status - // R[lp1_cmo_status_35]: V(True) + // Subregister 213 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_213]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_35 ( - .re (lp1_cmo_status_35_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[35].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_35_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_213 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 36 of Multireg lp1_cmo_status - // R[lp1_cmo_status_36]: V(True) + // from register interface + .we (cfg_lp1_cmo_213_we), + .wd (cfg_lp1_cmo_213_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_36 ( - .re (lp1_cmo_status_36_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[36].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_36_qs) + .q (reg2hw.cfg_lp1_cmo[213].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_213_qs) ); - // Subregister 37 of Multireg lp1_cmo_status - // R[lp1_cmo_status_37]: V(True) + // Subregister 214 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_214]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_37 ( - .re (lp1_cmo_status_37_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[37].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_37_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_214 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 38 of Multireg lp1_cmo_status - // R[lp1_cmo_status_38]: V(True) + // from register interface + .we (cfg_lp1_cmo_214_we), + .wd (cfg_lp1_cmo_214_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_38 ( - .re (lp1_cmo_status_38_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[38].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_38_qs) + .q (reg2hw.cfg_lp1_cmo[214].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_214_qs) ); - // Subregister 39 of Multireg lp1_cmo_status - // R[lp1_cmo_status_39]: V(True) + // Subregister 215 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_215]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_39 ( - .re (lp1_cmo_status_39_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[39].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_215 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_215_we), + .wd (cfg_lp1_cmo_215_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_39_qs) + .q (reg2hw.cfg_lp1_cmo[215].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_215_qs) ); - // Subregister 40 of Multireg lp1_cmo_status - // R[lp1_cmo_status_40]: V(True) + // Subregister 216 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_216]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_40 ( - .re (lp1_cmo_status_40_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[40].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_216 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_216_we), + .wd (cfg_lp1_cmo_216_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_40_qs) + .q (reg2hw.cfg_lp1_cmo[216].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_216_qs) ); - // Subregister 41 of Multireg lp1_cmo_status - // R[lp1_cmo_status_41]: V(True) + // Subregister 217 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_217]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_41 ( - .re (lp1_cmo_status_41_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[41].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_41_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_217 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 42 of Multireg lp1_cmo_status - // R[lp1_cmo_status_42]: V(True) + // from register interface + .we (cfg_lp1_cmo_217_we), + .wd (cfg_lp1_cmo_217_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_42 ( - .re (lp1_cmo_status_42_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[42].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_42_qs) + .q (reg2hw.cfg_lp1_cmo[217].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_217_qs) ); - // Subregister 43 of Multireg lp1_cmo_status - // R[lp1_cmo_status_43]: V(True) + // Subregister 218 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_218]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_43 ( - .re (lp1_cmo_status_43_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[43].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_43_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_218 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 44 of Multireg lp1_cmo_status - // R[lp1_cmo_status_44]: V(True) + // from register interface + .we (cfg_lp1_cmo_218_we), + .wd (cfg_lp1_cmo_218_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_44 ( - .re (lp1_cmo_status_44_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[44].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_44_qs) + .q (reg2hw.cfg_lp1_cmo[218].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_218_qs) ); - // Subregister 45 of Multireg lp1_cmo_status - // R[lp1_cmo_status_45]: V(True) + // Subregister 219 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_219]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_45 ( - .re (lp1_cmo_status_45_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[45].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_45_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_219 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 46 of Multireg lp1_cmo_status - // R[lp1_cmo_status_46]: V(True) + // from register interface + .we (cfg_lp1_cmo_219_we), + .wd (cfg_lp1_cmo_219_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_46 ( - .re (lp1_cmo_status_46_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[46].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_46_qs) + .q (reg2hw.cfg_lp1_cmo[219].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_219_qs) ); - // Subregister 47 of Multireg lp1_cmo_status - // R[lp1_cmo_status_47]: V(True) + // Subregister 220 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_220]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_47 ( - .re (lp1_cmo_status_47_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[47].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_47_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_220 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 48 of Multireg lp1_cmo_status - // R[lp1_cmo_status_48]: V(True) + // from register interface + .we (cfg_lp1_cmo_220_we), + .wd (cfg_lp1_cmo_220_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_48 ( - .re (lp1_cmo_status_48_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[48].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_48_qs) + .q (reg2hw.cfg_lp1_cmo[220].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_220_qs) ); - // Subregister 49 of Multireg lp1_cmo_status - // R[lp1_cmo_status_49]: V(True) + // Subregister 221 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_221]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_49 ( - .re (lp1_cmo_status_49_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[49].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_49_qs) - ); + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_221 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - // Subregister 50 of Multireg lp1_cmo_status - // R[lp1_cmo_status_50]: V(True) + // from register interface + .we (cfg_lp1_cmo_221_we), + .wd (cfg_lp1_cmo_221_wd), - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_50 ( - .re (lp1_cmo_status_50_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[50].d), - .qre (), + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_50_qs) + .q (reg2hw.cfg_lp1_cmo[221].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_221_qs) ); - // Subregister 51 of Multireg lp1_cmo_status - // R[lp1_cmo_status_51]: V(True) + // Subregister 222 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_222]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_51 ( - .re (lp1_cmo_status_51_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[51].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_222 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_222_we), + .wd (cfg_lp1_cmo_222_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_51_qs) + .q (reg2hw.cfg_lp1_cmo[222].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_222_qs) ); - // Subregister 52 of Multireg lp1_cmo_status - // R[lp1_cmo_status_52]: V(True) + // Subregister 223 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_223]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_52 ( - .re (lp1_cmo_status_52_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[52].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_223 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_223_we), + .wd (cfg_lp1_cmo_223_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_52_qs) + .q (reg2hw.cfg_lp1_cmo[223].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_223_qs) ); - // Subregister 53 of Multireg lp1_cmo_status - // R[lp1_cmo_status_53]: V(True) + // Subregister 224 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_224]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_53 ( - .re (lp1_cmo_status_53_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[53].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_224 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_224_we), + .wd (cfg_lp1_cmo_224_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_53_qs) + .q (reg2hw.cfg_lp1_cmo[224].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_224_qs) ); - // Subregister 54 of Multireg lp1_cmo_status - // R[lp1_cmo_status_54]: V(True) + // Subregister 225 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_225]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_54 ( - .re (lp1_cmo_status_54_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[54].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_225 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_225_we), + .wd (cfg_lp1_cmo_225_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_54_qs) + .q (reg2hw.cfg_lp1_cmo[225].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_225_qs) ); - // Subregister 55 of Multireg lp1_cmo_status - // R[lp1_cmo_status_55]: V(True) + // Subregister 226 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_226]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_55 ( - .re (lp1_cmo_status_55_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[55].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_226 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_226_we), + .wd (cfg_lp1_cmo_226_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_55_qs) + .q (reg2hw.cfg_lp1_cmo[226].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_226_qs) ); - // Subregister 56 of Multireg lp1_cmo_status - // R[lp1_cmo_status_56]: V(True) + // Subregister 227 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_227]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_56 ( - .re (lp1_cmo_status_56_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[56].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_227 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_227_we), + .wd (cfg_lp1_cmo_227_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_56_qs) + .q (reg2hw.cfg_lp1_cmo[227].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_227_qs) ); - // Subregister 57 of Multireg lp1_cmo_status - // R[lp1_cmo_status_57]: V(True) + // Subregister 228 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_228]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_57 ( - .re (lp1_cmo_status_57_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[57].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_228 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_228_we), + .wd (cfg_lp1_cmo_228_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_57_qs) + .q (reg2hw.cfg_lp1_cmo[228].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_228_qs) ); - // Subregister 58 of Multireg lp1_cmo_status - // R[lp1_cmo_status_58]: V(True) + // Subregister 229 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_229]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_58 ( - .re (lp1_cmo_status_58_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[58].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_229 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_229_we), + .wd (cfg_lp1_cmo_229_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_58_qs) + .q (reg2hw.cfg_lp1_cmo[229].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_229_qs) ); - // Subregister 59 of Multireg lp1_cmo_status - // R[lp1_cmo_status_59]: V(True) + // Subregister 230 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_230]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_59 ( - .re (lp1_cmo_status_59_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[59].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_230 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_230_we), + .wd (cfg_lp1_cmo_230_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_59_qs) + .q (reg2hw.cfg_lp1_cmo[230].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_230_qs) ); - // Subregister 60 of Multireg lp1_cmo_status - // R[lp1_cmo_status_60]: V(True) + // Subregister 231 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_231]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_60 ( - .re (lp1_cmo_status_60_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[60].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_231 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_231_we), + .wd (cfg_lp1_cmo_231_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_60_qs) + .q (reg2hw.cfg_lp1_cmo[231].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_231_qs) ); - // Subregister 61 of Multireg lp1_cmo_status - // R[lp1_cmo_status_61]: V(True) + // Subregister 232 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_232]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_61 ( - .re (lp1_cmo_status_61_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[61].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_232 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_232_we), + .wd (cfg_lp1_cmo_232_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_61_qs) + .q (reg2hw.cfg_lp1_cmo[232].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_232_qs) ); - // Subregister 62 of Multireg lp1_cmo_status - // R[lp1_cmo_status_62]: V(True) + // Subregister 233 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_233]: V(False) - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_62 ( - .re (lp1_cmo_status_62_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[62].d), - .qre (), + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_233 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_233_we), + .wd (cfg_lp1_cmo_233_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware .qe (), - .q (), - .qs (lp1_cmo_status_62_qs) + .q (reg2hw.cfg_lp1_cmo[233].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_233_qs) + ); + + // Subregister 234 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_234]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_234 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_234_we), + .wd (cfg_lp1_cmo_234_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[234].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_234_qs) + ); + + // Subregister 235 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_235]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_235 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_235_we), + .wd (cfg_lp1_cmo_235_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[235].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_235_qs) + ); + + // Subregister 236 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_236]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_236 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_236_we), + .wd (cfg_lp1_cmo_236_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[236].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_236_qs) + ); + + // Subregister 237 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_237]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_237 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_237_we), + .wd (cfg_lp1_cmo_237_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[237].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_237_qs) + ); + + // Subregister 238 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_238]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_238 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_238_we), + .wd (cfg_lp1_cmo_238_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[238].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_238_qs) + ); + + // Subregister 239 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_239]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_239 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_239_we), + .wd (cfg_lp1_cmo_239_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[239].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_239_qs) + ); + + // Subregister 240 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_240]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_240 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_240_we), + .wd (cfg_lp1_cmo_240_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[240].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_240_qs) + ); + + // Subregister 241 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_241]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_241 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_241_we), + .wd (cfg_lp1_cmo_241_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[241].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_241_qs) + ); + + // Subregister 242 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_242]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_242 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_242_we), + .wd (cfg_lp1_cmo_242_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[242].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_242_qs) + ); + + // Subregister 243 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_243]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_243 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_243_we), + .wd (cfg_lp1_cmo_243_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[243].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_243_qs) + ); + + // Subregister 244 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_244]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_244 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_244_we), + .wd (cfg_lp1_cmo_244_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[244].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_244_qs) ); - // Subregister 63 of Multireg lp1_cmo_status - // R[lp1_cmo_status_63]: V(True) + // Subregister 245 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_245]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_245 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_245_we), + .wd (cfg_lp1_cmo_245_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[245].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_245_qs) + ); + + // Subregister 246 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_246]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_246 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_246_we), + .wd (cfg_lp1_cmo_246_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[246].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_246_qs) + ); + + // Subregister 247 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_247]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_247 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_247_we), + .wd (cfg_lp1_cmo_247_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[247].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_247_qs) + ); + + // Subregister 248 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_248]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_248 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_248_we), + .wd (cfg_lp1_cmo_248_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[248].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_248_qs) + ); + + // Subregister 249 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_249]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_249 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_249_we), + .wd (cfg_lp1_cmo_249_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[249].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_249_qs) + ); + + // Subregister 250 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_250]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_250 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_250_we), + .wd (cfg_lp1_cmo_250_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[250].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_250_qs) + ); + + // Subregister 251 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_251]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_251 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_251_we), + .wd (cfg_lp1_cmo_251_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[251].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_251_qs) + ); + + // Subregister 252 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_252]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_252 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_252_we), + .wd (cfg_lp1_cmo_252_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[252].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_252_qs) + ); + + // Subregister 253 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_253]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_253 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_253_we), + .wd (cfg_lp1_cmo_253_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[253].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_253_qs) + ); + + // Subregister 254 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_254]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_254 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_254_we), + .wd (cfg_lp1_cmo_254_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[254].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_254_qs) + ); + + // Subregister 255 of Multireg cfg_lp1_cmo + // R[cfg_lp1_cmo_255]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h0) + ) u_cfg_lp1_cmo_255 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_255_we), + .wd (cfg_lp1_cmo_255_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo[255].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_255_qs) + ); + + + + // Subregister 0 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_0]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_0_we), + .wd (cfg_lp1_cmo_addr_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[0].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_0_qs) + ); + + // Subregister 1 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_1]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_1_we), + .wd (cfg_lp1_cmo_addr_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[1].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_1_qs) + ); + + // Subregister 2 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_2]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_2_we), + .wd (cfg_lp1_cmo_addr_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[2].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_2_qs) + ); + + // Subregister 3 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_3]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_3_we), + .wd (cfg_lp1_cmo_addr_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[3].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_3_qs) + ); + + // Subregister 4 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_4]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_4_we), + .wd (cfg_lp1_cmo_addr_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[4].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_4_qs) + ); + + // Subregister 5 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_5]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_5_we), + .wd (cfg_lp1_cmo_addr_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[5].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_5_qs) + ); + + // Subregister 6 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_6]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_6_we), + .wd (cfg_lp1_cmo_addr_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[6].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_6_qs) + ); + + // Subregister 7 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_7]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_7_we), + .wd (cfg_lp1_cmo_addr_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[7].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_7_qs) + ); + + // Subregister 8 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_8]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_8_we), + .wd (cfg_lp1_cmo_addr_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[8].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_8_qs) + ); + + // Subregister 9 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_9]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_9_we), + .wd (cfg_lp1_cmo_addr_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[9].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_9_qs) + ); + + // Subregister 10 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_10]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_10_we), + .wd (cfg_lp1_cmo_addr_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[10].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_10_qs) + ); + + // Subregister 11 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_11]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_11_we), + .wd (cfg_lp1_cmo_addr_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[11].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_11_qs) + ); + + // Subregister 12 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_12]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_12_we), + .wd (cfg_lp1_cmo_addr_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[12].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_12_qs) + ); + + // Subregister 13 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_13]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_13_we), + .wd (cfg_lp1_cmo_addr_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[13].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_13_qs) + ); + + // Subregister 14 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_14]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_14_we), + .wd (cfg_lp1_cmo_addr_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[14].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_14_qs) + ); + + // Subregister 15 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_15]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_15_we), + .wd (cfg_lp1_cmo_addr_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[15].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_15_qs) + ); + + // Subregister 16 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_16]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_16_we), + .wd (cfg_lp1_cmo_addr_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[16].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_16_qs) + ); + + // Subregister 17 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_17]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_17_we), + .wd (cfg_lp1_cmo_addr_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[17].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_17_qs) + ); + + // Subregister 18 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_18]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_18_we), + .wd (cfg_lp1_cmo_addr_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[18].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_18_qs) + ); + + // Subregister 19 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_19]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_19_we), + .wd (cfg_lp1_cmo_addr_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[19].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_19_qs) + ); + + // Subregister 20 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_20]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_20_we), + .wd (cfg_lp1_cmo_addr_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[20].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_20_qs) + ); + + // Subregister 21 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_21]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_21_we), + .wd (cfg_lp1_cmo_addr_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[21].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_21_qs) + ); + + // Subregister 22 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_22]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_22_we), + .wd (cfg_lp1_cmo_addr_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[22].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_22_qs) + ); + + // Subregister 23 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_23]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_23_we), + .wd (cfg_lp1_cmo_addr_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[23].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_23_qs) + ); + + // Subregister 24 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_24]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_24_we), + .wd (cfg_lp1_cmo_addr_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[24].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_24_qs) + ); + + // Subregister 25 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_25]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_25_we), + .wd (cfg_lp1_cmo_addr_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[25].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_25_qs) + ); + + // Subregister 26 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_26]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_26_we), + .wd (cfg_lp1_cmo_addr_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[26].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_26_qs) + ); + + // Subregister 27 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_27]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_27_we), + .wd (cfg_lp1_cmo_addr_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[27].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_27_qs) + ); + + // Subregister 28 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_28]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_28_we), + .wd (cfg_lp1_cmo_addr_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[28].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_28_qs) + ); + + // Subregister 29 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_29]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_29_we), + .wd (cfg_lp1_cmo_addr_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[29].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_29_qs) + ); + + // Subregister 30 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_30]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_30_we), + .wd (cfg_lp1_cmo_addr_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[30].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_30_qs) + ); + + // Subregister 31 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_31]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_31_we), + .wd (cfg_lp1_cmo_addr_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[31].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_31_qs) + ); + + // Subregister 32 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_32]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_32_we), + .wd (cfg_lp1_cmo_addr_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[32].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_32_qs) + ); + + // Subregister 33 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_33]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_33_we), + .wd (cfg_lp1_cmo_addr_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[33].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_33_qs) + ); + + // Subregister 34 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_34]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_34_we), + .wd (cfg_lp1_cmo_addr_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[34].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_34_qs) + ); + + // Subregister 35 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_35]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_35 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_35_we), + .wd (cfg_lp1_cmo_addr_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[35].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_35_qs) + ); + + // Subregister 36 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_36]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_36 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_36_we), + .wd (cfg_lp1_cmo_addr_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[36].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_36_qs) + ); + + // Subregister 37 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_37]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_37 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_37_we), + .wd (cfg_lp1_cmo_addr_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[37].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_37_qs) + ); + + // Subregister 38 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_38]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_38 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_38_we), + .wd (cfg_lp1_cmo_addr_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[38].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_38_qs) + ); + + // Subregister 39 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_39]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_39 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_39_we), + .wd (cfg_lp1_cmo_addr_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[39].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_39_qs) + ); + + // Subregister 40 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_40]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_40 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_40_we), + .wd (cfg_lp1_cmo_addr_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[40].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_40_qs) + ); + + // Subregister 41 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_41]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_41 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_41_we), + .wd (cfg_lp1_cmo_addr_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[41].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_41_qs) + ); + + // Subregister 42 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_42]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_42 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_42_we), + .wd (cfg_lp1_cmo_addr_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[42].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_42_qs) + ); + + // Subregister 43 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_43]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_43 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_43_we), + .wd (cfg_lp1_cmo_addr_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[43].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_43_qs) + ); + + // Subregister 44 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_44]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_44 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_44_we), + .wd (cfg_lp1_cmo_addr_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[44].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_44_qs) + ); + + // Subregister 45 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_45]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_45 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_45_we), + .wd (cfg_lp1_cmo_addr_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[45].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_45_qs) + ); + + // Subregister 46 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_46]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_46 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_46_we), + .wd (cfg_lp1_cmo_addr_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[46].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_46_qs) + ); + + // Subregister 47 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_47]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_47 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_47_we), + .wd (cfg_lp1_cmo_addr_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[47].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_47_qs) + ); + + // Subregister 48 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_48]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_48 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_48_we), + .wd (cfg_lp1_cmo_addr_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[48].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_48_qs) + ); + + // Subregister 49 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_49]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_49 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_49_we), + .wd (cfg_lp1_cmo_addr_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[49].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_49_qs) + ); + + // Subregister 50 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_50]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_50 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_50_we), + .wd (cfg_lp1_cmo_addr_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[50].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_50_qs) + ); + + // Subregister 51 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_51]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_51 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_51_we), + .wd (cfg_lp1_cmo_addr_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[51].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_51_qs) + ); + + // Subregister 52 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_52]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_52 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_52_we), + .wd (cfg_lp1_cmo_addr_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[52].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_52_qs) + ); + + // Subregister 53 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_53]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_53 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_53_we), + .wd (cfg_lp1_cmo_addr_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[53].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_53_qs) + ); + + // Subregister 54 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_54]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_54 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_54_we), + .wd (cfg_lp1_cmo_addr_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[54].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_54_qs) + ); + + // Subregister 55 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_55]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_55 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_55_we), + .wd (cfg_lp1_cmo_addr_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[55].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_55_qs) + ); + + // Subregister 56 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_56]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_56 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_56_we), + .wd (cfg_lp1_cmo_addr_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[56].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_56_qs) + ); + + // Subregister 57 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_57]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_57 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_57_we), + .wd (cfg_lp1_cmo_addr_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[57].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_57_qs) + ); + + // Subregister 58 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_58]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_58 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_58_we), + .wd (cfg_lp1_cmo_addr_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[58].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_58_qs) + ); + + // Subregister 59 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_59]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_59 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_59_we), + .wd (cfg_lp1_cmo_addr_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[59].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_59_qs) + ); + + // Subregister 60 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_60]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_60 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_60_we), + .wd (cfg_lp1_cmo_addr_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[60].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_60_qs) + ); + + // Subregister 61 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_61]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_61 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_61_we), + .wd (cfg_lp1_cmo_addr_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[61].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_61_qs) + ); + + // Subregister 62 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_62]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_62 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_62_we), + .wd (cfg_lp1_cmo_addr_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[62].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_62_qs) + ); + + // Subregister 63 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_63]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_63 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_63_we), + .wd (cfg_lp1_cmo_addr_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[63].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_63_qs) + ); + + // Subregister 64 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_64]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_64 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_64_we), + .wd (cfg_lp1_cmo_addr_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[64].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_64_qs) + ); + + // Subregister 65 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_65]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_65 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_65_we), + .wd (cfg_lp1_cmo_addr_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[65].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_65_qs) + ); + + // Subregister 66 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_66]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_66 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_66_we), + .wd (cfg_lp1_cmo_addr_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[66].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_66_qs) + ); + + // Subregister 67 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_67]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_67 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_67_we), + .wd (cfg_lp1_cmo_addr_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[67].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_67_qs) + ); + + // Subregister 68 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_68]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_68 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_68_we), + .wd (cfg_lp1_cmo_addr_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[68].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_68_qs) + ); + + // Subregister 69 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_69]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_69 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_69_we), + .wd (cfg_lp1_cmo_addr_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[69].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_69_qs) + ); + + // Subregister 70 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_70]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_70 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_70_we), + .wd (cfg_lp1_cmo_addr_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[70].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_70_qs) + ); + + // Subregister 71 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_71]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_71 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_71_we), + .wd (cfg_lp1_cmo_addr_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[71].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_71_qs) + ); + + // Subregister 72 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_72]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_72 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_72_we), + .wd (cfg_lp1_cmo_addr_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[72].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_72_qs) + ); + + // Subregister 73 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_73]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_73 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_73_we), + .wd (cfg_lp1_cmo_addr_73_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[73].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_73_qs) + ); + + // Subregister 74 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_74]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_74 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_74_we), + .wd (cfg_lp1_cmo_addr_74_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[74].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_74_qs) + ); + + // Subregister 75 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_75]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_75 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_75_we), + .wd (cfg_lp1_cmo_addr_75_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[75].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_75_qs) + ); + + // Subregister 76 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_76]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_76 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_76_we), + .wd (cfg_lp1_cmo_addr_76_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[76].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_76_qs) + ); + + // Subregister 77 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_77]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_77 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_77_we), + .wd (cfg_lp1_cmo_addr_77_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[77].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_77_qs) + ); + + // Subregister 78 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_78]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_78 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_78_we), + .wd (cfg_lp1_cmo_addr_78_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[78].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_78_qs) + ); + + // Subregister 79 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_79]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_79 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_79_we), + .wd (cfg_lp1_cmo_addr_79_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[79].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_79_qs) + ); + + // Subregister 80 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_80]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_80 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_80_we), + .wd (cfg_lp1_cmo_addr_80_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[80].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_80_qs) + ); + + // Subregister 81 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_81]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_81 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_81_we), + .wd (cfg_lp1_cmo_addr_81_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[81].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_81_qs) + ); + + // Subregister 82 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_82]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_82 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_82_we), + .wd (cfg_lp1_cmo_addr_82_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[82].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_82_qs) + ); + + // Subregister 83 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_83]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_83 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_83_we), + .wd (cfg_lp1_cmo_addr_83_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[83].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_83_qs) + ); + + // Subregister 84 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_84]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_84 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_84_we), + .wd (cfg_lp1_cmo_addr_84_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[84].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_84_qs) + ); + + // Subregister 85 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_85]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_85 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_85_we), + .wd (cfg_lp1_cmo_addr_85_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[85].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_85_qs) + ); + + // Subregister 86 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_86]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_86 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_86_we), + .wd (cfg_lp1_cmo_addr_86_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[86].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_86_qs) + ); + + // Subregister 87 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_87]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_87 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_87_we), + .wd (cfg_lp1_cmo_addr_87_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[87].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_87_qs) + ); + + // Subregister 88 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_88]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_88 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_88_we), + .wd (cfg_lp1_cmo_addr_88_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[88].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_88_qs) + ); + + // Subregister 89 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_89]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_89 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_89_we), + .wd (cfg_lp1_cmo_addr_89_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[89].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_89_qs) + ); + + // Subregister 90 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_90]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_90 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_90_we), + .wd (cfg_lp1_cmo_addr_90_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[90].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_90_qs) + ); + + // Subregister 91 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_91]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_91 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_91_we), + .wd (cfg_lp1_cmo_addr_91_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[91].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_91_qs) + ); + + // Subregister 92 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_92]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_92 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_92_we), + .wd (cfg_lp1_cmo_addr_92_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[92].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_92_qs) + ); + + // Subregister 93 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_93]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_93 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_93_we), + .wd (cfg_lp1_cmo_addr_93_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[93].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_93_qs) + ); + + // Subregister 94 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_94]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_94 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_94_we), + .wd (cfg_lp1_cmo_addr_94_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[94].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_94_qs) + ); + + // Subregister 95 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_95]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_95 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_95_we), + .wd (cfg_lp1_cmo_addr_95_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[95].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_95_qs) + ); + + // Subregister 96 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_96]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_96 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_96_we), + .wd (cfg_lp1_cmo_addr_96_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[96].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_96_qs) + ); + + // Subregister 97 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_97]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_97 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_97_we), + .wd (cfg_lp1_cmo_addr_97_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[97].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_97_qs) + ); + + // Subregister 98 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_98]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_98 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_98_we), + .wd (cfg_lp1_cmo_addr_98_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[98].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_98_qs) + ); + + // Subregister 99 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_99]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_99 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_99_we), + .wd (cfg_lp1_cmo_addr_99_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[99].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_99_qs) + ); + + // Subregister 100 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_100]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_100 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_100_we), + .wd (cfg_lp1_cmo_addr_100_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[100].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_100_qs) + ); + + // Subregister 101 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_101]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_101 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_101_we), + .wd (cfg_lp1_cmo_addr_101_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[101].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_101_qs) + ); + + // Subregister 102 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_102]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_102 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_102_we), + .wd (cfg_lp1_cmo_addr_102_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[102].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_102_qs) + ); + + // Subregister 103 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_103]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_103 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_103_we), + .wd (cfg_lp1_cmo_addr_103_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[103].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_103_qs) + ); + + // Subregister 104 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_104]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_104 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_104_we), + .wd (cfg_lp1_cmo_addr_104_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[104].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_104_qs) + ); + + // Subregister 105 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_105]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_105 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_105_we), + .wd (cfg_lp1_cmo_addr_105_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[105].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_105_qs) + ); + + // Subregister 106 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_106]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_106 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_106_we), + .wd (cfg_lp1_cmo_addr_106_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[106].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_106_qs) + ); + + // Subregister 107 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_107]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_107 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_107_we), + .wd (cfg_lp1_cmo_addr_107_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[107].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_107_qs) + ); + + // Subregister 108 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_108]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_108 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_108_we), + .wd (cfg_lp1_cmo_addr_108_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[108].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_108_qs) + ); + + // Subregister 109 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_109]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_109 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_109_we), + .wd (cfg_lp1_cmo_addr_109_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[109].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_109_qs) + ); + + // Subregister 110 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_110]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_110 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_110_we), + .wd (cfg_lp1_cmo_addr_110_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[110].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_110_qs) + ); + + // Subregister 111 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_111]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_111 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_111_we), + .wd (cfg_lp1_cmo_addr_111_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[111].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_111_qs) + ); + + // Subregister 112 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_112]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_112 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_112_we), + .wd (cfg_lp1_cmo_addr_112_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[112].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_112_qs) + ); + + // Subregister 113 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_113]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_113 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_113_we), + .wd (cfg_lp1_cmo_addr_113_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[113].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_113_qs) + ); + + // Subregister 114 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_114]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_114 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_114_we), + .wd (cfg_lp1_cmo_addr_114_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[114].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_114_qs) + ); + + // Subregister 115 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_115]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_115 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_115_we), + .wd (cfg_lp1_cmo_addr_115_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[115].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_115_qs) + ); + + // Subregister 116 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_116]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_116 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_116_we), + .wd (cfg_lp1_cmo_addr_116_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[116].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_116_qs) + ); + + // Subregister 117 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_117]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_117 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_117_we), + .wd (cfg_lp1_cmo_addr_117_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[117].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_117_qs) + ); + + // Subregister 118 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_118]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_118 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_118_we), + .wd (cfg_lp1_cmo_addr_118_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[118].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_118_qs) + ); + + // Subregister 119 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_119]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_119 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_119_we), + .wd (cfg_lp1_cmo_addr_119_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[119].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_119_qs) + ); + + // Subregister 120 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_120]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_120 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_120_we), + .wd (cfg_lp1_cmo_addr_120_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[120].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_120_qs) + ); + + // Subregister 121 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_121]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_121 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_121_we), + .wd (cfg_lp1_cmo_addr_121_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[121].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_121_qs) + ); + + // Subregister 122 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_122]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_122 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_122_we), + .wd (cfg_lp1_cmo_addr_122_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[122].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_122_qs) + ); + + // Subregister 123 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_123]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_123 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_123_we), + .wd (cfg_lp1_cmo_addr_123_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[123].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_123_qs) + ); + + // Subregister 124 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_124]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_124 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_124_we), + .wd (cfg_lp1_cmo_addr_124_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[124].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_124_qs) + ); + + // Subregister 125 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_125]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_125 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_125_we), + .wd (cfg_lp1_cmo_addr_125_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[125].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_125_qs) + ); + + // Subregister 126 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_126]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_126 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_126_we), + .wd (cfg_lp1_cmo_addr_126_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[126].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_126_qs) + ); + + // Subregister 127 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_127]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_127 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_127_we), + .wd (cfg_lp1_cmo_addr_127_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[127].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_127_qs) + ); + + // Subregister 128 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_128]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_128 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_128_we), + .wd (cfg_lp1_cmo_addr_128_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[128].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_128_qs) + ); + + // Subregister 129 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_129]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_129 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_129_we), + .wd (cfg_lp1_cmo_addr_129_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[129].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_129_qs) + ); + + // Subregister 130 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_130]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_130 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_130_we), + .wd (cfg_lp1_cmo_addr_130_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[130].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_130_qs) + ); + + // Subregister 131 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_131]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_131 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_131_we), + .wd (cfg_lp1_cmo_addr_131_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[131].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_131_qs) + ); + + // Subregister 132 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_132]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_132 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_132_we), + .wd (cfg_lp1_cmo_addr_132_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[132].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_132_qs) + ); + + // Subregister 133 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_133]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_133 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_133_we), + .wd (cfg_lp1_cmo_addr_133_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[133].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_133_qs) + ); + + // Subregister 134 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_134]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_134 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_134_we), + .wd (cfg_lp1_cmo_addr_134_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[134].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_134_qs) + ); + + // Subregister 135 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_135]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_135 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_135_we), + .wd (cfg_lp1_cmo_addr_135_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[135].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_135_qs) + ); + + // Subregister 136 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_136]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_136 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_136_we), + .wd (cfg_lp1_cmo_addr_136_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[136].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_136_qs) + ); + + // Subregister 137 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_137]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_137 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_137_we), + .wd (cfg_lp1_cmo_addr_137_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[137].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_137_qs) + ); + + // Subregister 138 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_138]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_138 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_138_we), + .wd (cfg_lp1_cmo_addr_138_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[138].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_138_qs) + ); + + // Subregister 139 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_139]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_139 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_139_we), + .wd (cfg_lp1_cmo_addr_139_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[139].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_139_qs) + ); + + // Subregister 140 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_140]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_140 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_140_we), + .wd (cfg_lp1_cmo_addr_140_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[140].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_140_qs) + ); + + // Subregister 141 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_141]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_141 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_141_we), + .wd (cfg_lp1_cmo_addr_141_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[141].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_141_qs) + ); + + // Subregister 142 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_142]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_142 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_142_we), + .wd (cfg_lp1_cmo_addr_142_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[142].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_142_qs) + ); + + // Subregister 143 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_143]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_143 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_143_we), + .wd (cfg_lp1_cmo_addr_143_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[143].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_143_qs) + ); + + // Subregister 144 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_144]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_144 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_144_we), + .wd (cfg_lp1_cmo_addr_144_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[144].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_144_qs) + ); + + // Subregister 145 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_145]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_145 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_145_we), + .wd (cfg_lp1_cmo_addr_145_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[145].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_145_qs) + ); + + // Subregister 146 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_146]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_146 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_146_we), + .wd (cfg_lp1_cmo_addr_146_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[146].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_146_qs) + ); + + // Subregister 147 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_147]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_147 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_147_we), + .wd (cfg_lp1_cmo_addr_147_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[147].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_147_qs) + ); + + // Subregister 148 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_148]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_148 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_148_we), + .wd (cfg_lp1_cmo_addr_148_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[148].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_148_qs) + ); + + // Subregister 149 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_149]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_149 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_149_we), + .wd (cfg_lp1_cmo_addr_149_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[149].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_149_qs) + ); + + // Subregister 150 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_150]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_150 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_150_we), + .wd (cfg_lp1_cmo_addr_150_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[150].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_150_qs) + ); + + // Subregister 151 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_151]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_151 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_151_we), + .wd (cfg_lp1_cmo_addr_151_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[151].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_151_qs) + ); + + // Subregister 152 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_152]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_152 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_152_we), + .wd (cfg_lp1_cmo_addr_152_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[152].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_152_qs) + ); + + // Subregister 153 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_153]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_153 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_153_we), + .wd (cfg_lp1_cmo_addr_153_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[153].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_153_qs) + ); + + // Subregister 154 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_154]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_154 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_154_we), + .wd (cfg_lp1_cmo_addr_154_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[154].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_154_qs) + ); + + // Subregister 155 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_155]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_155 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_155_we), + .wd (cfg_lp1_cmo_addr_155_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[155].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_155_qs) + ); + + // Subregister 156 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_156]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_156 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_156_we), + .wd (cfg_lp1_cmo_addr_156_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[156].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_156_qs) + ); + + // Subregister 157 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_157]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_157 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_157_we), + .wd (cfg_lp1_cmo_addr_157_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[157].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_157_qs) + ); + + // Subregister 158 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_158]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_158 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_158_we), + .wd (cfg_lp1_cmo_addr_158_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[158].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_158_qs) + ); + + // Subregister 159 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_159]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_159 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_159_we), + .wd (cfg_lp1_cmo_addr_159_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[159].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_159_qs) + ); + + // Subregister 160 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_160]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_160 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_160_we), + .wd (cfg_lp1_cmo_addr_160_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[160].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_160_qs) + ); + + // Subregister 161 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_161]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_161 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_161_we), + .wd (cfg_lp1_cmo_addr_161_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[161].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_161_qs) + ); + + // Subregister 162 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_162]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_162 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_162_we), + .wd (cfg_lp1_cmo_addr_162_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[162].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_162_qs) + ); + + // Subregister 163 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_163]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_163 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_163_we), + .wd (cfg_lp1_cmo_addr_163_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[163].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_163_qs) + ); + + // Subregister 164 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_164]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_164 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_164_we), + .wd (cfg_lp1_cmo_addr_164_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[164].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_164_qs) + ); + + // Subregister 165 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_165]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_165 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_165_we), + .wd (cfg_lp1_cmo_addr_165_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[165].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_165_qs) + ); + + // Subregister 166 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_166]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_166 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_166_we), + .wd (cfg_lp1_cmo_addr_166_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[166].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_166_qs) + ); + + // Subregister 167 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_167]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_167 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_167_we), + .wd (cfg_lp1_cmo_addr_167_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[167].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_167_qs) + ); + + // Subregister 168 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_168]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_168 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_168_we), + .wd (cfg_lp1_cmo_addr_168_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[168].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_168_qs) + ); + + // Subregister 169 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_169]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_169 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_169_we), + .wd (cfg_lp1_cmo_addr_169_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[169].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_169_qs) + ); + + // Subregister 170 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_170]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_170 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_170_we), + .wd (cfg_lp1_cmo_addr_170_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[170].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_170_qs) + ); + + // Subregister 171 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_171]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_171 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_171_we), + .wd (cfg_lp1_cmo_addr_171_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[171].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_171_qs) + ); + + // Subregister 172 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_172]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_172 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_172_we), + .wd (cfg_lp1_cmo_addr_172_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[172].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_172_qs) + ); + + // Subregister 173 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_173]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_173 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_173_we), + .wd (cfg_lp1_cmo_addr_173_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[173].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_173_qs) + ); + + // Subregister 174 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_174]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_174 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_174_we), + .wd (cfg_lp1_cmo_addr_174_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[174].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_174_qs) + ); + + // Subregister 175 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_175]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_175 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_175_we), + .wd (cfg_lp1_cmo_addr_175_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[175].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_175_qs) + ); + + // Subregister 176 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_176]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_176 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_176_we), + .wd (cfg_lp1_cmo_addr_176_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[176].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_176_qs) + ); + + // Subregister 177 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_177]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_177 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_177_we), + .wd (cfg_lp1_cmo_addr_177_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[177].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_177_qs) + ); + + // Subregister 178 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_178]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_178 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_178_we), + .wd (cfg_lp1_cmo_addr_178_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[178].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_178_qs) + ); + + // Subregister 179 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_179]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_179 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_179_we), + .wd (cfg_lp1_cmo_addr_179_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[179].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_179_qs) + ); + + // Subregister 180 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_180]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_180 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_180_we), + .wd (cfg_lp1_cmo_addr_180_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[180].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_180_qs) + ); + + // Subregister 181 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_181]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_181 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_181_we), + .wd (cfg_lp1_cmo_addr_181_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[181].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_181_qs) + ); + + // Subregister 182 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_182]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_182 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_182_we), + .wd (cfg_lp1_cmo_addr_182_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[182].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_182_qs) + ); + + // Subregister 183 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_183]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_183 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_183_we), + .wd (cfg_lp1_cmo_addr_183_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[183].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_183_qs) + ); + + // Subregister 184 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_184]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_184 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_184_we), + .wd (cfg_lp1_cmo_addr_184_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[184].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_184_qs) + ); + + // Subregister 185 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_185]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_185 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_185_we), + .wd (cfg_lp1_cmo_addr_185_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[185].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_185_qs) + ); + + // Subregister 186 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_186]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_186 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_186_we), + .wd (cfg_lp1_cmo_addr_186_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[186].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_186_qs) + ); + + // Subregister 187 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_187]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_187 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_187_we), + .wd (cfg_lp1_cmo_addr_187_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[187].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_187_qs) + ); + + // Subregister 188 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_188]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_188 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_188_we), + .wd (cfg_lp1_cmo_addr_188_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[188].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_188_qs) + ); + + // Subregister 189 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_189]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_189 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_189_we), + .wd (cfg_lp1_cmo_addr_189_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[189].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_189_qs) + ); + + // Subregister 190 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_190]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_190 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_190_we), + .wd (cfg_lp1_cmo_addr_190_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[190].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_190_qs) + ); + + // Subregister 191 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_191]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_191 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_191_we), + .wd (cfg_lp1_cmo_addr_191_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[191].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_191_qs) + ); + + // Subregister 192 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_192]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_192 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_192_we), + .wd (cfg_lp1_cmo_addr_192_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[192].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_192_qs) + ); + + // Subregister 193 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_193]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_193 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_193_we), + .wd (cfg_lp1_cmo_addr_193_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[193].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_193_qs) + ); + + // Subregister 194 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_194]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_194 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_194_we), + .wd (cfg_lp1_cmo_addr_194_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[194].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_194_qs) + ); + + // Subregister 195 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_195]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_195 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_195_we), + .wd (cfg_lp1_cmo_addr_195_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[195].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_195_qs) + ); + + // Subregister 196 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_196]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_196 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_196_we), + .wd (cfg_lp1_cmo_addr_196_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[196].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_196_qs) + ); + + // Subregister 197 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_197]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_197 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_197_we), + .wd (cfg_lp1_cmo_addr_197_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[197].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_197_qs) + ); + + // Subregister 198 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_198]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_198 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_198_we), + .wd (cfg_lp1_cmo_addr_198_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[198].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_198_qs) + ); + + // Subregister 199 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_199]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_199 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_199_we), + .wd (cfg_lp1_cmo_addr_199_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[199].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_199_qs) + ); + + // Subregister 200 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_200]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_200 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_200_we), + .wd (cfg_lp1_cmo_addr_200_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[200].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_200_qs) + ); + + // Subregister 201 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_201]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_201 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_201_we), + .wd (cfg_lp1_cmo_addr_201_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[201].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_201_qs) + ); + + // Subregister 202 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_202]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_202 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_202_we), + .wd (cfg_lp1_cmo_addr_202_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[202].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_202_qs) + ); + + // Subregister 203 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_203]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_203 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_203_we), + .wd (cfg_lp1_cmo_addr_203_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[203].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_203_qs) + ); + + // Subregister 204 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_204]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_204 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_204_we), + .wd (cfg_lp1_cmo_addr_204_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[204].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_204_qs) + ); + + // Subregister 205 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_205]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_205 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_205_we), + .wd (cfg_lp1_cmo_addr_205_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[205].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_205_qs) + ); + + // Subregister 206 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_206]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_206 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_206_we), + .wd (cfg_lp1_cmo_addr_206_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[206].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_206_qs) + ); + + // Subregister 207 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_207]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_207 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_207_we), + .wd (cfg_lp1_cmo_addr_207_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[207].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_207_qs) + ); + + // Subregister 208 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_208]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_208 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_208_we), + .wd (cfg_lp1_cmo_addr_208_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[208].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_208_qs) + ); + + // Subregister 209 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_209]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_209 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_209_we), + .wd (cfg_lp1_cmo_addr_209_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[209].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_209_qs) + ); + + // Subregister 210 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_210]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_210 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_210_we), + .wd (cfg_lp1_cmo_addr_210_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[210].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_210_qs) + ); + + // Subregister 211 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_211]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_211 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_211_we), + .wd (cfg_lp1_cmo_addr_211_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[211].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_211_qs) + ); + + // Subregister 212 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_212]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_212 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_212_we), + .wd (cfg_lp1_cmo_addr_212_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[212].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_212_qs) + ); + + // Subregister 213 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_213]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_213 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_213_we), + .wd (cfg_lp1_cmo_addr_213_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[213].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_213_qs) + ); + + // Subregister 214 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_214]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_214 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_214_we), + .wd (cfg_lp1_cmo_addr_214_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[214].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_214_qs) + ); + + // Subregister 215 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_215]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_215 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_215_we), + .wd (cfg_lp1_cmo_addr_215_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[215].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_215_qs) + ); + + // Subregister 216 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_216]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_216 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_216_we), + .wd (cfg_lp1_cmo_addr_216_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[216].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_216_qs) + ); + + // Subregister 217 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_217]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_217 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_217_we), + .wd (cfg_lp1_cmo_addr_217_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[217].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_217_qs) + ); + + // Subregister 218 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_218]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_218 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_218_we), + .wd (cfg_lp1_cmo_addr_218_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[218].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_218_qs) + ); + + // Subregister 219 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_219]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_219 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_219_we), + .wd (cfg_lp1_cmo_addr_219_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[219].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_219_qs) + ); + + // Subregister 220 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_220]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_220 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_220_we), + .wd (cfg_lp1_cmo_addr_220_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[220].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_220_qs) + ); + + // Subregister 221 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_221]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_221 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_221_we), + .wd (cfg_lp1_cmo_addr_221_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[221].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_221_qs) + ); + + // Subregister 222 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_222]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_222 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_222_we), + .wd (cfg_lp1_cmo_addr_222_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[222].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_222_qs) + ); + + // Subregister 223 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_223]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_223 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_223_we), + .wd (cfg_lp1_cmo_addr_223_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[223].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_223_qs) + ); + + // Subregister 224 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_224]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_224 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_224_we), + .wd (cfg_lp1_cmo_addr_224_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[224].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_224_qs) + ); + + // Subregister 225 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_225]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_225 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_225_we), + .wd (cfg_lp1_cmo_addr_225_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[225].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_225_qs) + ); + + // Subregister 226 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_226]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_226 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_226_we), + .wd (cfg_lp1_cmo_addr_226_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[226].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_226_qs) + ); + + // Subregister 227 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_227]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_227 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_227_we), + .wd (cfg_lp1_cmo_addr_227_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[227].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_227_qs) + ); + + // Subregister 228 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_228]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_228 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_228_we), + .wd (cfg_lp1_cmo_addr_228_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[228].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_228_qs) + ); + + // Subregister 229 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_229]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_229 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_229_we), + .wd (cfg_lp1_cmo_addr_229_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[229].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_229_qs) + ); + + // Subregister 230 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_230]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_230 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_230_we), + .wd (cfg_lp1_cmo_addr_230_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[230].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_230_qs) + ); + + // Subregister 231 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_231]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_231 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_231_we), + .wd (cfg_lp1_cmo_addr_231_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[231].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_231_qs) + ); + + // Subregister 232 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_232]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_232 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_232_we), + .wd (cfg_lp1_cmo_addr_232_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[232].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_232_qs) + ); + + // Subregister 233 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_233]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_233 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_233_we), + .wd (cfg_lp1_cmo_addr_233_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[233].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_233_qs) + ); + + // Subregister 234 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_234]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_234 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_234_we), + .wd (cfg_lp1_cmo_addr_234_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[234].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_234_qs) + ); + + // Subregister 235 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_235]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_235 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_235_we), + .wd (cfg_lp1_cmo_addr_235_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[235].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_235_qs) + ); + + // Subregister 236 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_236]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_236 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_236_we), + .wd (cfg_lp1_cmo_addr_236_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[236].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_236_qs) + ); + + // Subregister 237 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_237]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_237 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_237_we), + .wd (cfg_lp1_cmo_addr_237_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[237].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_237_qs) + ); + + // Subregister 238 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_238]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_238 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_238_we), + .wd (cfg_lp1_cmo_addr_238_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[238].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_238_qs) + ); + + // Subregister 239 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_239]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_239 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_239_we), + .wd (cfg_lp1_cmo_addr_239_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[239].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_239_qs) + ); + + // Subregister 240 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_240]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_240 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_240_we), + .wd (cfg_lp1_cmo_addr_240_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[240].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_240_qs) + ); + + // Subregister 241 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_241]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_241 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_241_we), + .wd (cfg_lp1_cmo_addr_241_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[241].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_241_qs) + ); + + // Subregister 242 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_242]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_242 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_242_we), + .wd (cfg_lp1_cmo_addr_242_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[242].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_242_qs) + ); + + // Subregister 243 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_243]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_243 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_243_we), + .wd (cfg_lp1_cmo_addr_243_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[243].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_243_qs) + ); + + // Subregister 244 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_244]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_244 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_244_we), + .wd (cfg_lp1_cmo_addr_244_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[244].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_244_qs) + ); + + // Subregister 245 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_245]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_245 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_245_we), + .wd (cfg_lp1_cmo_addr_245_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[245].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_245_qs) + ); + + // Subregister 246 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_246]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_246 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_246_we), + .wd (cfg_lp1_cmo_addr_246_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[246].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_246_qs) + ); + + // Subregister 247 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_247]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_247 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_247_we), + .wd (cfg_lp1_cmo_addr_247_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[247].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_247_qs) + ); + + // Subregister 248 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_248]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_248 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_248_we), + .wd (cfg_lp1_cmo_addr_248_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[248].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_248_qs) + ); + + // Subregister 249 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_249]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_249 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_249_we), + .wd (cfg_lp1_cmo_addr_249_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[249].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_249_qs) + ); + + // Subregister 250 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_250]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_250 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_250_we), + .wd (cfg_lp1_cmo_addr_250_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[250].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_250_qs) + ); + + // Subregister 251 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_251]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_251 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_251_we), + .wd (cfg_lp1_cmo_addr_251_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[251].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_251_qs) + ); + + // Subregister 252 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_252]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_252 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_252_we), + .wd (cfg_lp1_cmo_addr_252_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[252].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_252_qs) + ); + + // Subregister 253 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_253]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_253 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_253_we), + .wd (cfg_lp1_cmo_addr_253_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[253].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_253_qs) + ); + + // Subregister 254 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_254]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_254 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_254_we), + .wd (cfg_lp1_cmo_addr_254_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[254].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_254_qs) + ); + + // Subregister 255 of Multireg cfg_lp1_cmo_addr + // R[cfg_lp1_cmo_addr_255]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_cfg_lp1_cmo_addr_255 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_lp1_cmo_addr_255_we), + .wd (cfg_lp1_cmo_addr_255_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg_lp1_cmo_addr[255].q ), + + // to register interface (read) + .qs (cfg_lp1_cmo_addr_255_qs) + ); + + + + // Subregister 0 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_0]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_0_we), + .wd (lp1_cmo_commit_0_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[0].de), + .d (hw2reg.lp1_cmo_commit[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[0].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_0_qs) + ); + + // Subregister 1 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_1]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_1_we), + .wd (lp1_cmo_commit_1_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[1].de), + .d (hw2reg.lp1_cmo_commit[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[1].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_1_qs) + ); + + // Subregister 2 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_2]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_2_we), + .wd (lp1_cmo_commit_2_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[2].de), + .d (hw2reg.lp1_cmo_commit[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[2].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_2_qs) + ); + + // Subregister 3 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_3]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_3_we), + .wd (lp1_cmo_commit_3_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[3].de), + .d (hw2reg.lp1_cmo_commit[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[3].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_3_qs) + ); + + // Subregister 4 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_4]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_4_we), + .wd (lp1_cmo_commit_4_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[4].de), + .d (hw2reg.lp1_cmo_commit[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[4].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_4_qs) + ); + + // Subregister 5 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_5]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_5_we), + .wd (lp1_cmo_commit_5_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[5].de), + .d (hw2reg.lp1_cmo_commit[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[5].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_5_qs) + ); + + // Subregister 6 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_6]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_6_we), + .wd (lp1_cmo_commit_6_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[6].de), + .d (hw2reg.lp1_cmo_commit[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[6].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_6_qs) + ); + + // Subregister 7 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_7]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_7_we), + .wd (lp1_cmo_commit_7_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[7].de), + .d (hw2reg.lp1_cmo_commit[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[7].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_7_qs) + ); + + // Subregister 8 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_8]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_8_we), + .wd (lp1_cmo_commit_8_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[8].de), + .d (hw2reg.lp1_cmo_commit[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[8].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_8_qs) + ); + + // Subregister 9 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_9]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_9_we), + .wd (lp1_cmo_commit_9_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[9].de), + .d (hw2reg.lp1_cmo_commit[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[9].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_9_qs) + ); + + // Subregister 10 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_10]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_10_we), + .wd (lp1_cmo_commit_10_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[10].de), + .d (hw2reg.lp1_cmo_commit[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[10].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_10_qs) + ); + + // Subregister 11 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_11]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_11_we), + .wd (lp1_cmo_commit_11_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[11].de), + .d (hw2reg.lp1_cmo_commit[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[11].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_11_qs) + ); + + // Subregister 12 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_12]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_12_we), + .wd (lp1_cmo_commit_12_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[12].de), + .d (hw2reg.lp1_cmo_commit[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[12].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_12_qs) + ); + + // Subregister 13 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_13]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_13_we), + .wd (lp1_cmo_commit_13_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[13].de), + .d (hw2reg.lp1_cmo_commit[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[13].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_13_qs) + ); + + // Subregister 14 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_14]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_14_we), + .wd (lp1_cmo_commit_14_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[14].de), + .d (hw2reg.lp1_cmo_commit[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[14].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_14_qs) + ); + + // Subregister 15 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_15]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_15_we), + .wd (lp1_cmo_commit_15_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[15].de), + .d (hw2reg.lp1_cmo_commit[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[15].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_15_qs) + ); + + // Subregister 16 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_16]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_16_we), + .wd (lp1_cmo_commit_16_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[16].de), + .d (hw2reg.lp1_cmo_commit[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[16].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_16_qs) + ); + + // Subregister 17 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_17]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_17_we), + .wd (lp1_cmo_commit_17_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[17].de), + .d (hw2reg.lp1_cmo_commit[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[17].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_17_qs) + ); + + // Subregister 18 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_18]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_18_we), + .wd (lp1_cmo_commit_18_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[18].de), + .d (hw2reg.lp1_cmo_commit[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[18].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_18_qs) + ); + + // Subregister 19 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_19]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_19_we), + .wd (lp1_cmo_commit_19_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[19].de), + .d (hw2reg.lp1_cmo_commit[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[19].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_19_qs) + ); + + // Subregister 20 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_20]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_20_we), + .wd (lp1_cmo_commit_20_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[20].de), + .d (hw2reg.lp1_cmo_commit[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[20].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_20_qs) + ); + + // Subregister 21 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_21]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_21_we), + .wd (lp1_cmo_commit_21_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[21].de), + .d (hw2reg.lp1_cmo_commit[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[21].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_21_qs) + ); + + // Subregister 22 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_22]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_22_we), + .wd (lp1_cmo_commit_22_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[22].de), + .d (hw2reg.lp1_cmo_commit[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[22].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_22_qs) + ); + + // Subregister 23 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_23]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_23_we), + .wd (lp1_cmo_commit_23_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[23].de), + .d (hw2reg.lp1_cmo_commit[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[23].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_23_qs) + ); + + // Subregister 24 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_24]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_24_we), + .wd (lp1_cmo_commit_24_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[24].de), + .d (hw2reg.lp1_cmo_commit[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[24].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_24_qs) + ); + + // Subregister 25 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_25]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_25_we), + .wd (lp1_cmo_commit_25_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[25].de), + .d (hw2reg.lp1_cmo_commit[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[25].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_25_qs) + ); + + // Subregister 26 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_26]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_26_we), + .wd (lp1_cmo_commit_26_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[26].de), + .d (hw2reg.lp1_cmo_commit[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[26].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_26_qs) + ); + + // Subregister 27 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_27]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_27_we), + .wd (lp1_cmo_commit_27_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[27].de), + .d (hw2reg.lp1_cmo_commit[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[27].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_27_qs) + ); + + // Subregister 28 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_28]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_28_we), + .wd (lp1_cmo_commit_28_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[28].de), + .d (hw2reg.lp1_cmo_commit[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[28].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_28_qs) + ); + + // Subregister 29 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_29]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_29_we), + .wd (lp1_cmo_commit_29_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[29].de), + .d (hw2reg.lp1_cmo_commit[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[29].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_29_qs) + ); + + // Subregister 30 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_30]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_30_we), + .wd (lp1_cmo_commit_30_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[30].de), + .d (hw2reg.lp1_cmo_commit[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[30].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_30_qs) + ); + + // Subregister 31 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_31]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_31_we), + .wd (lp1_cmo_commit_31_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[31].de), + .d (hw2reg.lp1_cmo_commit[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[31].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_31_qs) + ); + + // Subregister 32 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_32]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_32_we), + .wd (lp1_cmo_commit_32_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[32].de), + .d (hw2reg.lp1_cmo_commit[32].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[32].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_32_qs) + ); + + // Subregister 33 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_33]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_33_we), + .wd (lp1_cmo_commit_33_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[33].de), + .d (hw2reg.lp1_cmo_commit[33].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[33].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_33_qs) + ); + + // Subregister 34 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_34]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_34_we), + .wd (lp1_cmo_commit_34_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[34].de), + .d (hw2reg.lp1_cmo_commit[34].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[34].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_34_qs) + ); + + // Subregister 35 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_35]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_35 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_35_we), + .wd (lp1_cmo_commit_35_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[35].de), + .d (hw2reg.lp1_cmo_commit[35].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[35].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_35_qs) + ); + + // Subregister 36 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_36]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_36 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_36_we), + .wd (lp1_cmo_commit_36_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[36].de), + .d (hw2reg.lp1_cmo_commit[36].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[36].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_36_qs) + ); + + // Subregister 37 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_37]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_37 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_37_we), + .wd (lp1_cmo_commit_37_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[37].de), + .d (hw2reg.lp1_cmo_commit[37].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[37].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_37_qs) + ); + + // Subregister 38 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_38]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_38 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_38_we), + .wd (lp1_cmo_commit_38_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[38].de), + .d (hw2reg.lp1_cmo_commit[38].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[38].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_38_qs) + ); + + // Subregister 39 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_39]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_39 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_39_we), + .wd (lp1_cmo_commit_39_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[39].de), + .d (hw2reg.lp1_cmo_commit[39].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[39].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_39_qs) + ); + + // Subregister 40 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_40]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_40 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_40_we), + .wd (lp1_cmo_commit_40_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[40].de), + .d (hw2reg.lp1_cmo_commit[40].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[40].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_40_qs) + ); + + // Subregister 41 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_41]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_41 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_41_we), + .wd (lp1_cmo_commit_41_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[41].de), + .d (hw2reg.lp1_cmo_commit[41].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[41].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_41_qs) + ); + + // Subregister 42 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_42]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_42 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_42_we), + .wd (lp1_cmo_commit_42_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[42].de), + .d (hw2reg.lp1_cmo_commit[42].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[42].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_42_qs) + ); + + // Subregister 43 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_43]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_43 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_43_we), + .wd (lp1_cmo_commit_43_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[43].de), + .d (hw2reg.lp1_cmo_commit[43].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[43].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_43_qs) + ); + + // Subregister 44 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_44]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_44 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_44_we), + .wd (lp1_cmo_commit_44_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[44].de), + .d (hw2reg.lp1_cmo_commit[44].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[44].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_44_qs) + ); + + // Subregister 45 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_45]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_45 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_45_we), + .wd (lp1_cmo_commit_45_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[45].de), + .d (hw2reg.lp1_cmo_commit[45].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[45].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_45_qs) + ); + + // Subregister 46 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_46]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_46 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_46_we), + .wd (lp1_cmo_commit_46_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[46].de), + .d (hw2reg.lp1_cmo_commit[46].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[46].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_46_qs) + ); + + // Subregister 47 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_47]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_47 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_47_we), + .wd (lp1_cmo_commit_47_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[47].de), + .d (hw2reg.lp1_cmo_commit[47].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[47].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_47_qs) + ); + + // Subregister 48 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_48]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_48 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_48_we), + .wd (lp1_cmo_commit_48_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[48].de), + .d (hw2reg.lp1_cmo_commit[48].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[48].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_48_qs) + ); + + // Subregister 49 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_49]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_49 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_49_we), + .wd (lp1_cmo_commit_49_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[49].de), + .d (hw2reg.lp1_cmo_commit[49].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[49].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_49_qs) + ); + + // Subregister 50 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_50]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_50 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_50_we), + .wd (lp1_cmo_commit_50_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[50].de), + .d (hw2reg.lp1_cmo_commit[50].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[50].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_50_qs) + ); + + // Subregister 51 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_51]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_51 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_51_we), + .wd (lp1_cmo_commit_51_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[51].de), + .d (hw2reg.lp1_cmo_commit[51].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[51].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_51_qs) + ); + + // Subregister 52 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_52]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_52 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_52_we), + .wd (lp1_cmo_commit_52_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[52].de), + .d (hw2reg.lp1_cmo_commit[52].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[52].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_52_qs) + ); + + // Subregister 53 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_53]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_53 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_53_we), + .wd (lp1_cmo_commit_53_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[53].de), + .d (hw2reg.lp1_cmo_commit[53].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[53].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_53_qs) + ); + + // Subregister 54 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_54]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_54 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_54_we), + .wd (lp1_cmo_commit_54_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[54].de), + .d (hw2reg.lp1_cmo_commit[54].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[54].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_54_qs) + ); + + // Subregister 55 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_55]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_55 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_55_we), + .wd (lp1_cmo_commit_55_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[55].de), + .d (hw2reg.lp1_cmo_commit[55].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[55].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_55_qs) + ); + + // Subregister 56 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_56]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_56 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_56_we), + .wd (lp1_cmo_commit_56_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[56].de), + .d (hw2reg.lp1_cmo_commit[56].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[56].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_56_qs) + ); + + // Subregister 57 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_57]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_57 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_57_we), + .wd (lp1_cmo_commit_57_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[57].de), + .d (hw2reg.lp1_cmo_commit[57].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[57].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_57_qs) + ); + + // Subregister 58 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_58]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_58 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_58_we), + .wd (lp1_cmo_commit_58_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[58].de), + .d (hw2reg.lp1_cmo_commit[58].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[58].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_58_qs) + ); + + // Subregister 59 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_59]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_59 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_59_we), + .wd (lp1_cmo_commit_59_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[59].de), + .d (hw2reg.lp1_cmo_commit[59].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[59].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_59_qs) + ); + + // Subregister 60 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_60]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_60 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_60_we), + .wd (lp1_cmo_commit_60_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[60].de), + .d (hw2reg.lp1_cmo_commit[60].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[60].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_60_qs) + ); + + // Subregister 61 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_61]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_61 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_61_we), + .wd (lp1_cmo_commit_61_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[61].de), + .d (hw2reg.lp1_cmo_commit[61].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[61].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_61_qs) + ); + + // Subregister 62 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_62]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_62 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_62_we), + .wd (lp1_cmo_commit_62_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[62].de), + .d (hw2reg.lp1_cmo_commit[62].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[62].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_62_qs) + ); + + // Subregister 63 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_63]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_63 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_63_we), + .wd (lp1_cmo_commit_63_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[63].de), + .d (hw2reg.lp1_cmo_commit[63].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[63].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_63_qs) + ); + + // Subregister 64 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_64]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_64 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_64_we), + .wd (lp1_cmo_commit_64_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[64].de), + .d (hw2reg.lp1_cmo_commit[64].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[64].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_64_qs) + ); + + // Subregister 65 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_65]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_65 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_65_we), + .wd (lp1_cmo_commit_65_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[65].de), + .d (hw2reg.lp1_cmo_commit[65].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[65].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_65_qs) + ); + + // Subregister 66 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_66]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_66 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_66_we), + .wd (lp1_cmo_commit_66_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[66].de), + .d (hw2reg.lp1_cmo_commit[66].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[66].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_66_qs) + ); + + // Subregister 67 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_67]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_67 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_67_we), + .wd (lp1_cmo_commit_67_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[67].de), + .d (hw2reg.lp1_cmo_commit[67].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[67].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_67_qs) + ); + + // Subregister 68 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_68]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_68 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_68_we), + .wd (lp1_cmo_commit_68_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[68].de), + .d (hw2reg.lp1_cmo_commit[68].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[68].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_68_qs) + ); + + // Subregister 69 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_69]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_69 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_69_we), + .wd (lp1_cmo_commit_69_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[69].de), + .d (hw2reg.lp1_cmo_commit[69].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[69].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_69_qs) + ); + + // Subregister 70 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_70]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_70 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_70_we), + .wd (lp1_cmo_commit_70_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[70].de), + .d (hw2reg.lp1_cmo_commit[70].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[70].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_70_qs) + ); + + // Subregister 71 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_71]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_71 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_71_we), + .wd (lp1_cmo_commit_71_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[71].de), + .d (hw2reg.lp1_cmo_commit[71].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[71].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_71_qs) + ); + + // Subregister 72 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_72]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_72 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_72_we), + .wd (lp1_cmo_commit_72_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[72].de), + .d (hw2reg.lp1_cmo_commit[72].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[72].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_72_qs) + ); + + // Subregister 73 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_73]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_73 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_73_we), + .wd (lp1_cmo_commit_73_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[73].de), + .d (hw2reg.lp1_cmo_commit[73].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[73].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_73_qs) + ); + + // Subregister 74 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_74]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_74 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_74_we), + .wd (lp1_cmo_commit_74_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[74].de), + .d (hw2reg.lp1_cmo_commit[74].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[74].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_74_qs) + ); + + // Subregister 75 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_75]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_75 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_75_we), + .wd (lp1_cmo_commit_75_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[75].de), + .d (hw2reg.lp1_cmo_commit[75].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[75].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_75_qs) + ); + + // Subregister 76 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_76]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_76 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_76_we), + .wd (lp1_cmo_commit_76_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[76].de), + .d (hw2reg.lp1_cmo_commit[76].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[76].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_76_qs) + ); + + // Subregister 77 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_77]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_77 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_77_we), + .wd (lp1_cmo_commit_77_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[77].de), + .d (hw2reg.lp1_cmo_commit[77].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[77].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_77_qs) + ); + + // Subregister 78 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_78]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_78 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_78_we), + .wd (lp1_cmo_commit_78_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[78].de), + .d (hw2reg.lp1_cmo_commit[78].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[78].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_78_qs) + ); + + // Subregister 79 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_79]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_79 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_79_we), + .wd (lp1_cmo_commit_79_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[79].de), + .d (hw2reg.lp1_cmo_commit[79].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[79].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_79_qs) + ); + + // Subregister 80 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_80]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_80 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_80_we), + .wd (lp1_cmo_commit_80_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[80].de), + .d (hw2reg.lp1_cmo_commit[80].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[80].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_80_qs) + ); + + // Subregister 81 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_81]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_81 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_81_we), + .wd (lp1_cmo_commit_81_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[81].de), + .d (hw2reg.lp1_cmo_commit[81].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[81].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_81_qs) + ); + + // Subregister 82 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_82]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_82 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_82_we), + .wd (lp1_cmo_commit_82_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[82].de), + .d (hw2reg.lp1_cmo_commit[82].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[82].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_82_qs) + ); + + // Subregister 83 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_83]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_83 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_83_we), + .wd (lp1_cmo_commit_83_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[83].de), + .d (hw2reg.lp1_cmo_commit[83].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[83].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_83_qs) + ); + + // Subregister 84 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_84]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_84 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_84_we), + .wd (lp1_cmo_commit_84_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[84].de), + .d (hw2reg.lp1_cmo_commit[84].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[84].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_84_qs) + ); + + // Subregister 85 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_85]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_85 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_85_we), + .wd (lp1_cmo_commit_85_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[85].de), + .d (hw2reg.lp1_cmo_commit[85].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[85].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_85_qs) + ); + + // Subregister 86 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_86]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_86 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_86_we), + .wd (lp1_cmo_commit_86_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[86].de), + .d (hw2reg.lp1_cmo_commit[86].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[86].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_86_qs) + ); + + // Subregister 87 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_87]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_87 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_87_we), + .wd (lp1_cmo_commit_87_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[87].de), + .d (hw2reg.lp1_cmo_commit[87].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[87].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_87_qs) + ); + + // Subregister 88 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_88]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_88 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_88_we), + .wd (lp1_cmo_commit_88_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[88].de), + .d (hw2reg.lp1_cmo_commit[88].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[88].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_88_qs) + ); + + // Subregister 89 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_89]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_89 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_89_we), + .wd (lp1_cmo_commit_89_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[89].de), + .d (hw2reg.lp1_cmo_commit[89].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[89].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_89_qs) + ); + + // Subregister 90 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_90]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_90 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_90_we), + .wd (lp1_cmo_commit_90_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[90].de), + .d (hw2reg.lp1_cmo_commit[90].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[90].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_90_qs) + ); + + // Subregister 91 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_91]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_91 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_91_we), + .wd (lp1_cmo_commit_91_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[91].de), + .d (hw2reg.lp1_cmo_commit[91].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[91].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_91_qs) + ); + + // Subregister 92 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_92]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_92 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_92_we), + .wd (lp1_cmo_commit_92_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[92].de), + .d (hw2reg.lp1_cmo_commit[92].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[92].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_92_qs) + ); + + // Subregister 93 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_93]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_93 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_93_we), + .wd (lp1_cmo_commit_93_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[93].de), + .d (hw2reg.lp1_cmo_commit[93].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[93].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_93_qs) + ); + + // Subregister 94 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_94]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_94 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_94_we), + .wd (lp1_cmo_commit_94_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[94].de), + .d (hw2reg.lp1_cmo_commit[94].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[94].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_94_qs) + ); + + // Subregister 95 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_95]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_95 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_95_we), + .wd (lp1_cmo_commit_95_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[95].de), + .d (hw2reg.lp1_cmo_commit[95].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[95].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_95_qs) + ); + + // Subregister 96 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_96]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_96 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_96_we), + .wd (lp1_cmo_commit_96_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[96].de), + .d (hw2reg.lp1_cmo_commit[96].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[96].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_96_qs) + ); + + // Subregister 97 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_97]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_97 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_97_we), + .wd (lp1_cmo_commit_97_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[97].de), + .d (hw2reg.lp1_cmo_commit[97].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[97].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_97_qs) + ); + + // Subregister 98 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_98]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_98 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_98_we), + .wd (lp1_cmo_commit_98_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[98].de), + .d (hw2reg.lp1_cmo_commit[98].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[98].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_98_qs) + ); + + // Subregister 99 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_99]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_99 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_99_we), + .wd (lp1_cmo_commit_99_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[99].de), + .d (hw2reg.lp1_cmo_commit[99].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[99].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_99_qs) + ); + + // Subregister 100 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_100]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_100 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_100_we), + .wd (lp1_cmo_commit_100_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[100].de), + .d (hw2reg.lp1_cmo_commit[100].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[100].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_100_qs) + ); + + // Subregister 101 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_101]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_101 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_101_we), + .wd (lp1_cmo_commit_101_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[101].de), + .d (hw2reg.lp1_cmo_commit[101].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[101].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_101_qs) + ); + + // Subregister 102 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_102]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_102 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_102_we), + .wd (lp1_cmo_commit_102_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[102].de), + .d (hw2reg.lp1_cmo_commit[102].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[102].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_102_qs) + ); + + // Subregister 103 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_103]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_103 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_103_we), + .wd (lp1_cmo_commit_103_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[103].de), + .d (hw2reg.lp1_cmo_commit[103].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[103].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_103_qs) + ); + + // Subregister 104 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_104]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_104 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_104_we), + .wd (lp1_cmo_commit_104_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[104].de), + .d (hw2reg.lp1_cmo_commit[104].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[104].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_104_qs) + ); + + // Subregister 105 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_105]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_105 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_105_we), + .wd (lp1_cmo_commit_105_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[105].de), + .d (hw2reg.lp1_cmo_commit[105].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[105].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_105_qs) + ); + + // Subregister 106 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_106]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_106 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_106_we), + .wd (lp1_cmo_commit_106_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[106].de), + .d (hw2reg.lp1_cmo_commit[106].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[106].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_106_qs) + ); + + // Subregister 107 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_107]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_107 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_107_we), + .wd (lp1_cmo_commit_107_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[107].de), + .d (hw2reg.lp1_cmo_commit[107].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[107].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_107_qs) + ); + + // Subregister 108 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_108]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_108 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_108_we), + .wd (lp1_cmo_commit_108_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[108].de), + .d (hw2reg.lp1_cmo_commit[108].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[108].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_108_qs) + ); + + // Subregister 109 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_109]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_109 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_109_we), + .wd (lp1_cmo_commit_109_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[109].de), + .d (hw2reg.lp1_cmo_commit[109].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[109].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_109_qs) + ); + + // Subregister 110 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_110]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_110 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_110_we), + .wd (lp1_cmo_commit_110_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[110].de), + .d (hw2reg.lp1_cmo_commit[110].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[110].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_110_qs) + ); + + // Subregister 111 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_111]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_111 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_111_we), + .wd (lp1_cmo_commit_111_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[111].de), + .d (hw2reg.lp1_cmo_commit[111].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[111].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_111_qs) + ); + + // Subregister 112 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_112]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_112 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_112_we), + .wd (lp1_cmo_commit_112_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[112].de), + .d (hw2reg.lp1_cmo_commit[112].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[112].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_112_qs) + ); + + // Subregister 113 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_113]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_113 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_113_we), + .wd (lp1_cmo_commit_113_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[113].de), + .d (hw2reg.lp1_cmo_commit[113].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[113].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_113_qs) + ); + + // Subregister 114 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_114]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_114 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_114_we), + .wd (lp1_cmo_commit_114_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[114].de), + .d (hw2reg.lp1_cmo_commit[114].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[114].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_114_qs) + ); + + // Subregister 115 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_115]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_115 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_115_we), + .wd (lp1_cmo_commit_115_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[115].de), + .d (hw2reg.lp1_cmo_commit[115].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[115].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_115_qs) + ); + + // Subregister 116 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_116]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_116 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_116_we), + .wd (lp1_cmo_commit_116_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[116].de), + .d (hw2reg.lp1_cmo_commit[116].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[116].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_116_qs) + ); + + // Subregister 117 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_117]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_117 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_117_we), + .wd (lp1_cmo_commit_117_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[117].de), + .d (hw2reg.lp1_cmo_commit[117].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[117].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_117_qs) + ); + + // Subregister 118 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_118]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_118 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_118_we), + .wd (lp1_cmo_commit_118_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[118].de), + .d (hw2reg.lp1_cmo_commit[118].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[118].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_118_qs) + ); + + // Subregister 119 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_119]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_119 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_119_we), + .wd (lp1_cmo_commit_119_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[119].de), + .d (hw2reg.lp1_cmo_commit[119].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[119].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_119_qs) + ); + + // Subregister 120 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_120]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_120 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_120_we), + .wd (lp1_cmo_commit_120_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[120].de), + .d (hw2reg.lp1_cmo_commit[120].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[120].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_120_qs) + ); + + // Subregister 121 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_121]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_121 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_121_we), + .wd (lp1_cmo_commit_121_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[121].de), + .d (hw2reg.lp1_cmo_commit[121].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[121].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_121_qs) + ); + + // Subregister 122 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_122]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_122 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_122_we), + .wd (lp1_cmo_commit_122_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[122].de), + .d (hw2reg.lp1_cmo_commit[122].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[122].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_122_qs) + ); + + // Subregister 123 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_123]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_123 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_123_we), + .wd (lp1_cmo_commit_123_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[123].de), + .d (hw2reg.lp1_cmo_commit[123].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[123].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_123_qs) + ); + + // Subregister 124 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_124]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_124 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_124_we), + .wd (lp1_cmo_commit_124_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[124].de), + .d (hw2reg.lp1_cmo_commit[124].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[124].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_124_qs) + ); + + // Subregister 125 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_125]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_125 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_125_we), + .wd (lp1_cmo_commit_125_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[125].de), + .d (hw2reg.lp1_cmo_commit[125].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[125].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_125_qs) + ); + + // Subregister 126 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_126]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_126 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_126_we), + .wd (lp1_cmo_commit_126_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[126].de), + .d (hw2reg.lp1_cmo_commit[126].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[126].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_126_qs) + ); + + // Subregister 127 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_127]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_127 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_127_we), + .wd (lp1_cmo_commit_127_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[127].de), + .d (hw2reg.lp1_cmo_commit[127].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[127].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_127_qs) + ); + + // Subregister 128 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_128]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_128 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_128_we), + .wd (lp1_cmo_commit_128_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[128].de), + .d (hw2reg.lp1_cmo_commit[128].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[128].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_128_qs) + ); + + // Subregister 129 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_129]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_129 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_129_we), + .wd (lp1_cmo_commit_129_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[129].de), + .d (hw2reg.lp1_cmo_commit[129].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[129].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_129_qs) + ); + + // Subregister 130 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_130]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_130 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_130_we), + .wd (lp1_cmo_commit_130_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[130].de), + .d (hw2reg.lp1_cmo_commit[130].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[130].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_130_qs) + ); + + // Subregister 131 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_131]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_131 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_131_we), + .wd (lp1_cmo_commit_131_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[131].de), + .d (hw2reg.lp1_cmo_commit[131].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[131].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_131_qs) + ); + + // Subregister 132 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_132]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_132 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_132_we), + .wd (lp1_cmo_commit_132_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[132].de), + .d (hw2reg.lp1_cmo_commit[132].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[132].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_132_qs) + ); + + // Subregister 133 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_133]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_133 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_133_we), + .wd (lp1_cmo_commit_133_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[133].de), + .d (hw2reg.lp1_cmo_commit[133].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[133].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_133_qs) + ); + + // Subregister 134 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_134]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_134 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_134_we), + .wd (lp1_cmo_commit_134_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[134].de), + .d (hw2reg.lp1_cmo_commit[134].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[134].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_134_qs) + ); + + // Subregister 135 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_135]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_135 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_135_we), + .wd (lp1_cmo_commit_135_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[135].de), + .d (hw2reg.lp1_cmo_commit[135].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[135].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_135_qs) + ); + + // Subregister 136 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_136]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_136 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_136_we), + .wd (lp1_cmo_commit_136_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[136].de), + .d (hw2reg.lp1_cmo_commit[136].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[136].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_136_qs) + ); + + // Subregister 137 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_137]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_137 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_137_we), + .wd (lp1_cmo_commit_137_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[137].de), + .d (hw2reg.lp1_cmo_commit[137].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[137].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_137_qs) + ); + + // Subregister 138 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_138]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_138 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_138_we), + .wd (lp1_cmo_commit_138_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[138].de), + .d (hw2reg.lp1_cmo_commit[138].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[138].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_138_qs) + ); + + // Subregister 139 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_139]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_139 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_139_we), + .wd (lp1_cmo_commit_139_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[139].de), + .d (hw2reg.lp1_cmo_commit[139].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[139].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_139_qs) + ); + + // Subregister 140 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_140]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_140 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_140_we), + .wd (lp1_cmo_commit_140_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[140].de), + .d (hw2reg.lp1_cmo_commit[140].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[140].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_140_qs) + ); + + // Subregister 141 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_141]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_141 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_141_we), + .wd (lp1_cmo_commit_141_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[141].de), + .d (hw2reg.lp1_cmo_commit[141].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[141].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_141_qs) + ); + + // Subregister 142 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_142]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_142 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_142_we), + .wd (lp1_cmo_commit_142_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[142].de), + .d (hw2reg.lp1_cmo_commit[142].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[142].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_142_qs) + ); + + // Subregister 143 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_143]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_143 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_143_we), + .wd (lp1_cmo_commit_143_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[143].de), + .d (hw2reg.lp1_cmo_commit[143].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[143].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_143_qs) + ); + + // Subregister 144 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_144]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_144 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_144_we), + .wd (lp1_cmo_commit_144_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[144].de), + .d (hw2reg.lp1_cmo_commit[144].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[144].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_144_qs) + ); + + // Subregister 145 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_145]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_145 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_145_we), + .wd (lp1_cmo_commit_145_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[145].de), + .d (hw2reg.lp1_cmo_commit[145].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[145].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_145_qs) + ); + + // Subregister 146 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_146]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_146 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_146_we), + .wd (lp1_cmo_commit_146_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[146].de), + .d (hw2reg.lp1_cmo_commit[146].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[146].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_146_qs) + ); + + // Subregister 147 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_147]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_147 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_147_we), + .wd (lp1_cmo_commit_147_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[147].de), + .d (hw2reg.lp1_cmo_commit[147].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[147].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_147_qs) + ); + + // Subregister 148 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_148]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_148 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_148_we), + .wd (lp1_cmo_commit_148_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[148].de), + .d (hw2reg.lp1_cmo_commit[148].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[148].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_148_qs) + ); + + // Subregister 149 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_149]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_149 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_149_we), + .wd (lp1_cmo_commit_149_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[149].de), + .d (hw2reg.lp1_cmo_commit[149].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[149].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_149_qs) + ); + + // Subregister 150 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_150]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_150 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_150_we), + .wd (lp1_cmo_commit_150_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[150].de), + .d (hw2reg.lp1_cmo_commit[150].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[150].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_150_qs) + ); + + // Subregister 151 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_151]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_151 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_151_we), + .wd (lp1_cmo_commit_151_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[151].de), + .d (hw2reg.lp1_cmo_commit[151].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[151].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_151_qs) + ); + + // Subregister 152 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_152]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_152 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_152_we), + .wd (lp1_cmo_commit_152_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[152].de), + .d (hw2reg.lp1_cmo_commit[152].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[152].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_152_qs) + ); + + // Subregister 153 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_153]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_153 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_153_we), + .wd (lp1_cmo_commit_153_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[153].de), + .d (hw2reg.lp1_cmo_commit[153].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[153].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_153_qs) + ); + + // Subregister 154 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_154]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_154 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_154_we), + .wd (lp1_cmo_commit_154_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[154].de), + .d (hw2reg.lp1_cmo_commit[154].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[154].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_154_qs) + ); + + // Subregister 155 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_155]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_155 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_155_we), + .wd (lp1_cmo_commit_155_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[155].de), + .d (hw2reg.lp1_cmo_commit[155].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[155].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_155_qs) + ); + + // Subregister 156 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_156]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_156 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_156_we), + .wd (lp1_cmo_commit_156_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[156].de), + .d (hw2reg.lp1_cmo_commit[156].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[156].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_156_qs) + ); + + // Subregister 157 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_157]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_157 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_157_we), + .wd (lp1_cmo_commit_157_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[157].de), + .d (hw2reg.lp1_cmo_commit[157].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[157].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_157_qs) + ); + + // Subregister 158 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_158]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_158 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_158_we), + .wd (lp1_cmo_commit_158_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[158].de), + .d (hw2reg.lp1_cmo_commit[158].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[158].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_158_qs) + ); + + // Subregister 159 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_159]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_159 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_159_we), + .wd (lp1_cmo_commit_159_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[159].de), + .d (hw2reg.lp1_cmo_commit[159].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[159].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_159_qs) + ); + + // Subregister 160 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_160]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_160 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_160_we), + .wd (lp1_cmo_commit_160_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[160].de), + .d (hw2reg.lp1_cmo_commit[160].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[160].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_160_qs) + ); + + // Subregister 161 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_161]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_161 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_161_we), + .wd (lp1_cmo_commit_161_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[161].de), + .d (hw2reg.lp1_cmo_commit[161].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[161].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_161_qs) + ); + + // Subregister 162 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_162]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_162 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_162_we), + .wd (lp1_cmo_commit_162_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[162].de), + .d (hw2reg.lp1_cmo_commit[162].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[162].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_162_qs) + ); + + // Subregister 163 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_163]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_163 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_163_we), + .wd (lp1_cmo_commit_163_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[163].de), + .d (hw2reg.lp1_cmo_commit[163].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[163].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_163_qs) + ); + + // Subregister 164 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_164]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_164 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_164_we), + .wd (lp1_cmo_commit_164_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[164].de), + .d (hw2reg.lp1_cmo_commit[164].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[164].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_164_qs) + ); + + // Subregister 165 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_165]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_165 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_165_we), + .wd (lp1_cmo_commit_165_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[165].de), + .d (hw2reg.lp1_cmo_commit[165].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[165].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_165_qs) + ); + + // Subregister 166 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_166]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_166 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_166_we), + .wd (lp1_cmo_commit_166_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[166].de), + .d (hw2reg.lp1_cmo_commit[166].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[166].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_166_qs) + ); + + // Subregister 167 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_167]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_167 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_167_we), + .wd (lp1_cmo_commit_167_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[167].de), + .d (hw2reg.lp1_cmo_commit[167].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[167].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_167_qs) + ); + + // Subregister 168 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_168]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_168 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_168_we), + .wd (lp1_cmo_commit_168_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[168].de), + .d (hw2reg.lp1_cmo_commit[168].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[168].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_168_qs) + ); + + // Subregister 169 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_169]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_169 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_169_we), + .wd (lp1_cmo_commit_169_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[169].de), + .d (hw2reg.lp1_cmo_commit[169].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[169].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_169_qs) + ); + + // Subregister 170 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_170]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_170 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_170_we), + .wd (lp1_cmo_commit_170_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[170].de), + .d (hw2reg.lp1_cmo_commit[170].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[170].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_170_qs) + ); + + // Subregister 171 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_171]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_171 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_171_we), + .wd (lp1_cmo_commit_171_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[171].de), + .d (hw2reg.lp1_cmo_commit[171].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[171].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_171_qs) + ); + + // Subregister 172 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_172]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_172 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_172_we), + .wd (lp1_cmo_commit_172_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[172].de), + .d (hw2reg.lp1_cmo_commit[172].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[172].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_172_qs) + ); + + // Subregister 173 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_173]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_173 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_173_we), + .wd (lp1_cmo_commit_173_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[173].de), + .d (hw2reg.lp1_cmo_commit[173].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[173].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_173_qs) + ); + + // Subregister 174 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_174]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_174 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_174_we), + .wd (lp1_cmo_commit_174_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[174].de), + .d (hw2reg.lp1_cmo_commit[174].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[174].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_174_qs) + ); + + // Subregister 175 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_175]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_175 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_175_we), + .wd (lp1_cmo_commit_175_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[175].de), + .d (hw2reg.lp1_cmo_commit[175].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[175].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_175_qs) + ); + + // Subregister 176 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_176]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_176 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_176_we), + .wd (lp1_cmo_commit_176_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[176].de), + .d (hw2reg.lp1_cmo_commit[176].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[176].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_176_qs) + ); + + // Subregister 177 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_177]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_177 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_177_we), + .wd (lp1_cmo_commit_177_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[177].de), + .d (hw2reg.lp1_cmo_commit[177].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[177].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_177_qs) + ); + + // Subregister 178 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_178]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_178 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_178_we), + .wd (lp1_cmo_commit_178_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[178].de), + .d (hw2reg.lp1_cmo_commit[178].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[178].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_178_qs) + ); + + // Subregister 179 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_179]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_179 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_179_we), + .wd (lp1_cmo_commit_179_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[179].de), + .d (hw2reg.lp1_cmo_commit[179].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[179].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_179_qs) + ); + + // Subregister 180 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_180]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_180 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_180_we), + .wd (lp1_cmo_commit_180_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[180].de), + .d (hw2reg.lp1_cmo_commit[180].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[180].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_180_qs) + ); + + // Subregister 181 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_181]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_181 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_181_we), + .wd (lp1_cmo_commit_181_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[181].de), + .d (hw2reg.lp1_cmo_commit[181].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[181].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_181_qs) + ); + + // Subregister 182 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_182]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_182 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_182_we), + .wd (lp1_cmo_commit_182_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[182].de), + .d (hw2reg.lp1_cmo_commit[182].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[182].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_182_qs) + ); + + // Subregister 183 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_183]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_183 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_183_we), + .wd (lp1_cmo_commit_183_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[183].de), + .d (hw2reg.lp1_cmo_commit[183].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[183].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_183_qs) + ); + + // Subregister 184 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_184]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_184 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_184_we), + .wd (lp1_cmo_commit_184_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[184].de), + .d (hw2reg.lp1_cmo_commit[184].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[184].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_184_qs) + ); + + // Subregister 185 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_185]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_185 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_185_we), + .wd (lp1_cmo_commit_185_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[185].de), + .d (hw2reg.lp1_cmo_commit[185].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[185].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_185_qs) + ); + + // Subregister 186 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_186]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_186 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_186_we), + .wd (lp1_cmo_commit_186_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[186].de), + .d (hw2reg.lp1_cmo_commit[186].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[186].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_186_qs) + ); + + // Subregister 187 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_187]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_187 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_187_we), + .wd (lp1_cmo_commit_187_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[187].de), + .d (hw2reg.lp1_cmo_commit[187].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[187].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_187_qs) + ); + + // Subregister 188 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_188]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_188 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_188_we), + .wd (lp1_cmo_commit_188_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[188].de), + .d (hw2reg.lp1_cmo_commit[188].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[188].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_188_qs) + ); + + // Subregister 189 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_189]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_189 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_189_we), + .wd (lp1_cmo_commit_189_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[189].de), + .d (hw2reg.lp1_cmo_commit[189].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[189].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_189_qs) + ); + + // Subregister 190 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_190]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_190 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_190_we), + .wd (lp1_cmo_commit_190_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[190].de), + .d (hw2reg.lp1_cmo_commit[190].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[190].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_190_qs) + ); + + // Subregister 191 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_191]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_191 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_191_we), + .wd (lp1_cmo_commit_191_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[191].de), + .d (hw2reg.lp1_cmo_commit[191].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[191].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_191_qs) + ); + + // Subregister 192 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_192]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_192 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_192_we), + .wd (lp1_cmo_commit_192_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[192].de), + .d (hw2reg.lp1_cmo_commit[192].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[192].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_192_qs) + ); + + // Subregister 193 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_193]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_193 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_193_we), + .wd (lp1_cmo_commit_193_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[193].de), + .d (hw2reg.lp1_cmo_commit[193].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[193].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_193_qs) + ); + + // Subregister 194 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_194]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_194 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_194_we), + .wd (lp1_cmo_commit_194_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[194].de), + .d (hw2reg.lp1_cmo_commit[194].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[194].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_194_qs) + ); + + // Subregister 195 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_195]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_195 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_195_we), + .wd (lp1_cmo_commit_195_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[195].de), + .d (hw2reg.lp1_cmo_commit[195].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[195].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_195_qs) + ); + + // Subregister 196 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_196]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_196 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_196_we), + .wd (lp1_cmo_commit_196_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[196].de), + .d (hw2reg.lp1_cmo_commit[196].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[196].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_196_qs) + ); + + // Subregister 197 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_197]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_197 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_197_we), + .wd (lp1_cmo_commit_197_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[197].de), + .d (hw2reg.lp1_cmo_commit[197].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[197].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_197_qs) + ); + + // Subregister 198 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_198]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_198 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_198_we), + .wd (lp1_cmo_commit_198_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[198].de), + .d (hw2reg.lp1_cmo_commit[198].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[198].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_198_qs) + ); + + // Subregister 199 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_199]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_199 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_199_we), + .wd (lp1_cmo_commit_199_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[199].de), + .d (hw2reg.lp1_cmo_commit[199].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[199].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_199_qs) + ); + + // Subregister 200 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_200]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_200 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_200_we), + .wd (lp1_cmo_commit_200_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[200].de), + .d (hw2reg.lp1_cmo_commit[200].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[200].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_200_qs) + ); + + // Subregister 201 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_201]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_201 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_201_we), + .wd (lp1_cmo_commit_201_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[201].de), + .d (hw2reg.lp1_cmo_commit[201].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[201].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_201_qs) + ); + + // Subregister 202 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_202]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_202 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_202_we), + .wd (lp1_cmo_commit_202_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[202].de), + .d (hw2reg.lp1_cmo_commit[202].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[202].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_202_qs) + ); + + // Subregister 203 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_203]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_203 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_203_we), + .wd (lp1_cmo_commit_203_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[203].de), + .d (hw2reg.lp1_cmo_commit[203].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[203].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_203_qs) + ); + + // Subregister 204 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_204]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_204 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_204_we), + .wd (lp1_cmo_commit_204_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[204].de), + .d (hw2reg.lp1_cmo_commit[204].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[204].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_204_qs) + ); + + // Subregister 205 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_205]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_205 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_205_we), + .wd (lp1_cmo_commit_205_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[205].de), + .d (hw2reg.lp1_cmo_commit[205].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[205].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_205_qs) + ); + + // Subregister 206 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_206]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_206 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_206_we), + .wd (lp1_cmo_commit_206_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[206].de), + .d (hw2reg.lp1_cmo_commit[206].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[206].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_206_qs) + ); + + // Subregister 207 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_207]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_207 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_207_we), + .wd (lp1_cmo_commit_207_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[207].de), + .d (hw2reg.lp1_cmo_commit[207].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[207].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_207_qs) + ); + + // Subregister 208 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_208]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_208 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_208_we), + .wd (lp1_cmo_commit_208_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[208].de), + .d (hw2reg.lp1_cmo_commit[208].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[208].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_208_qs) + ); + + // Subregister 209 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_209]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_209 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_209_we), + .wd (lp1_cmo_commit_209_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[209].de), + .d (hw2reg.lp1_cmo_commit[209].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[209].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_209_qs) + ); + + // Subregister 210 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_210]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_210 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_210_we), + .wd (lp1_cmo_commit_210_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[210].de), + .d (hw2reg.lp1_cmo_commit[210].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[210].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_210_qs) + ); + + // Subregister 211 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_211]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_211 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_211_we), + .wd (lp1_cmo_commit_211_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[211].de), + .d (hw2reg.lp1_cmo_commit[211].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[211].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_211_qs) + ); + + // Subregister 212 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_212]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_212 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_212_we), + .wd (lp1_cmo_commit_212_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[212].de), + .d (hw2reg.lp1_cmo_commit[212].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[212].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_212_qs) + ); + + // Subregister 213 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_213]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_213 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_213_we), + .wd (lp1_cmo_commit_213_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[213].de), + .d (hw2reg.lp1_cmo_commit[213].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[213].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_213_qs) + ); + + // Subregister 214 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_214]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_214 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_214_we), + .wd (lp1_cmo_commit_214_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[214].de), + .d (hw2reg.lp1_cmo_commit[214].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[214].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_214_qs) + ); + + // Subregister 215 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_215]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_215 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_215_we), + .wd (lp1_cmo_commit_215_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[215].de), + .d (hw2reg.lp1_cmo_commit[215].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[215].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_215_qs) + ); + + // Subregister 216 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_216]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_216 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_216_we), + .wd (lp1_cmo_commit_216_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[216].de), + .d (hw2reg.lp1_cmo_commit[216].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[216].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_216_qs) + ); + + // Subregister 217 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_217]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_217 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_217_we), + .wd (lp1_cmo_commit_217_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[217].de), + .d (hw2reg.lp1_cmo_commit[217].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[217].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_217_qs) + ); + + // Subregister 218 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_218]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_218 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_218_we), + .wd (lp1_cmo_commit_218_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[218].de), + .d (hw2reg.lp1_cmo_commit[218].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[218].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_218_qs) + ); + + // Subregister 219 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_219]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_219 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_219_we), + .wd (lp1_cmo_commit_219_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[219].de), + .d (hw2reg.lp1_cmo_commit[219].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[219].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_219_qs) + ); + + // Subregister 220 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_220]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_220 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_220_we), + .wd (lp1_cmo_commit_220_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[220].de), + .d (hw2reg.lp1_cmo_commit[220].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[220].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_220_qs) + ); + + // Subregister 221 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_221]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_221 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_221_we), + .wd (lp1_cmo_commit_221_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[221].de), + .d (hw2reg.lp1_cmo_commit[221].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[221].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_221_qs) + ); + + // Subregister 222 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_222]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_222 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_222_we), + .wd (lp1_cmo_commit_222_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[222].de), + .d (hw2reg.lp1_cmo_commit[222].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[222].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_222_qs) + ); + + // Subregister 223 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_223]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_223 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_223_we), + .wd (lp1_cmo_commit_223_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[223].de), + .d (hw2reg.lp1_cmo_commit[223].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[223].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_223_qs) + ); + + // Subregister 224 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_224]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_224 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_224_we), + .wd (lp1_cmo_commit_224_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[224].de), + .d (hw2reg.lp1_cmo_commit[224].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[224].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_224_qs) + ); + + // Subregister 225 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_225]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_225 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_225_we), + .wd (lp1_cmo_commit_225_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[225].de), + .d (hw2reg.lp1_cmo_commit[225].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[225].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_225_qs) + ); + + // Subregister 226 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_226]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_226 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_226_we), + .wd (lp1_cmo_commit_226_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[226].de), + .d (hw2reg.lp1_cmo_commit[226].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[226].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_226_qs) + ); + + // Subregister 227 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_227]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_227 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_227_we), + .wd (lp1_cmo_commit_227_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[227].de), + .d (hw2reg.lp1_cmo_commit[227].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[227].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_227_qs) + ); + + // Subregister 228 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_228]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_228 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_228_we), + .wd (lp1_cmo_commit_228_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[228].de), + .d (hw2reg.lp1_cmo_commit[228].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[228].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_228_qs) + ); + + // Subregister 229 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_229]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_229 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_229_we), + .wd (lp1_cmo_commit_229_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[229].de), + .d (hw2reg.lp1_cmo_commit[229].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[229].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_229_qs) + ); + + // Subregister 230 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_230]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_230 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_230_we), + .wd (lp1_cmo_commit_230_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[230].de), + .d (hw2reg.lp1_cmo_commit[230].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[230].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_230_qs) + ); + + // Subregister 231 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_231]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_231 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_231_we), + .wd (lp1_cmo_commit_231_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[231].de), + .d (hw2reg.lp1_cmo_commit[231].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[231].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_231_qs) + ); + + // Subregister 232 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_232]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_232 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_232_we), + .wd (lp1_cmo_commit_232_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[232].de), + .d (hw2reg.lp1_cmo_commit[232].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[232].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_232_qs) + ); + + // Subregister 233 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_233]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_233 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_233_we), + .wd (lp1_cmo_commit_233_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[233].de), + .d (hw2reg.lp1_cmo_commit[233].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[233].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_233_qs) + ); + + // Subregister 234 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_234]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_234 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_234_we), + .wd (lp1_cmo_commit_234_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[234].de), + .d (hw2reg.lp1_cmo_commit[234].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[234].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_234_qs) + ); + + // Subregister 235 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_235]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_235 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_235_we), + .wd (lp1_cmo_commit_235_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[235].de), + .d (hw2reg.lp1_cmo_commit[235].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[235].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_235_qs) + ); + + // Subregister 236 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_236]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_236 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_236_we), + .wd (lp1_cmo_commit_236_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[236].de), + .d (hw2reg.lp1_cmo_commit[236].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[236].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_236_qs) + ); + + // Subregister 237 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_237]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_237 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_237_we), + .wd (lp1_cmo_commit_237_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[237].de), + .d (hw2reg.lp1_cmo_commit[237].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[237].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_237_qs) + ); + + // Subregister 238 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_238]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_238 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_238_we), + .wd (lp1_cmo_commit_238_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[238].de), + .d (hw2reg.lp1_cmo_commit[238].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[238].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_238_qs) + ); + + // Subregister 239 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_239]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_239 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_239_we), + .wd (lp1_cmo_commit_239_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[239].de), + .d (hw2reg.lp1_cmo_commit[239].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[239].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_239_qs) + ); + + // Subregister 240 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_240]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_240 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_240_we), + .wd (lp1_cmo_commit_240_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[240].de), + .d (hw2reg.lp1_cmo_commit[240].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[240].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_240_qs) + ); + + // Subregister 241 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_241]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_241 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_241_we), + .wd (lp1_cmo_commit_241_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[241].de), + .d (hw2reg.lp1_cmo_commit[241].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[241].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_241_qs) + ); + + // Subregister 242 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_242]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_242 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_242_we), + .wd (lp1_cmo_commit_242_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[242].de), + .d (hw2reg.lp1_cmo_commit[242].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[242].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_242_qs) + ); + + // Subregister 243 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_243]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_243 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_243_we), + .wd (lp1_cmo_commit_243_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[243].de), + .d (hw2reg.lp1_cmo_commit[243].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[243].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_243_qs) + ); + + // Subregister 244 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_244]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_244 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_244_we), + .wd (lp1_cmo_commit_244_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[244].de), + .d (hw2reg.lp1_cmo_commit[244].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[244].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_244_qs) + ); + + // Subregister 245 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_245]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_245 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_245_we), + .wd (lp1_cmo_commit_245_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[245].de), + .d (hw2reg.lp1_cmo_commit[245].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[245].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_245_qs) + ); + + // Subregister 246 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_246]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_246 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_246_we), + .wd (lp1_cmo_commit_246_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[246].de), + .d (hw2reg.lp1_cmo_commit[246].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[246].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_246_qs) + ); + + // Subregister 247 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_247]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_247 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_247_we), + .wd (lp1_cmo_commit_247_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[247].de), + .d (hw2reg.lp1_cmo_commit[247].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[247].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_247_qs) + ); + + // Subregister 248 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_248]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_248 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_248_we), + .wd (lp1_cmo_commit_248_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[248].de), + .d (hw2reg.lp1_cmo_commit[248].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[248].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_248_qs) + ); + + // Subregister 249 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_249]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_249 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_249_we), + .wd (lp1_cmo_commit_249_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[249].de), + .d (hw2reg.lp1_cmo_commit[249].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[249].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_249_qs) + ); + + // Subregister 250 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_250]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_250 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_250_we), + .wd (lp1_cmo_commit_250_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[250].de), + .d (hw2reg.lp1_cmo_commit[250].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[250].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_250_qs) + ); + + // Subregister 251 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_251]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_251 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_251_we), + .wd (lp1_cmo_commit_251_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[251].de), + .d (hw2reg.lp1_cmo_commit[251].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[251].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_251_qs) + ); + + // Subregister 252 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_252]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_252 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_252_we), + .wd (lp1_cmo_commit_252_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[252].de), + .d (hw2reg.lp1_cmo_commit[252].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[252].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_252_qs) + ); + + // Subregister 253 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_253]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_253 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_253_we), + .wd (lp1_cmo_commit_253_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[253].de), + .d (hw2reg.lp1_cmo_commit[253].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[253].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_253_qs) + ); + + // Subregister 254 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_254]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_254 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_254_we), + .wd (lp1_cmo_commit_254_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[254].de), + .d (hw2reg.lp1_cmo_commit[254].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[254].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_254_qs) + ); + + // Subregister 255 of Multireg lp1_cmo_commit + // R[lp1_cmo_commit_255]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_lp1_cmo_commit_255 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (lp1_cmo_commit_255_we), + .wd (lp1_cmo_commit_255_wd), + + // from internal hardware + .de (hw2reg.lp1_cmo_commit[255].de), + .d (hw2reg.lp1_cmo_commit[255].d ), + + // to internal hardware + .qe (), + .q (reg2hw.lp1_cmo_commit[255].q ), + + // to register interface (read) + .qs (lp1_cmo_commit_255_qs) + ); + + + + // Subregister 0 of Multireg lp1_cmo_status + // R[lp1_cmo_status_0]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_0 ( + .re (lp1_cmo_status_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[0].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_0_qs) + ); + + // Subregister 1 of Multireg lp1_cmo_status + // R[lp1_cmo_status_1]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_1 ( + .re (lp1_cmo_status_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[1].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_1_qs) + ); + + // Subregister 2 of Multireg lp1_cmo_status + // R[lp1_cmo_status_2]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_2 ( + .re (lp1_cmo_status_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[2].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_2_qs) + ); + + // Subregister 3 of Multireg lp1_cmo_status + // R[lp1_cmo_status_3]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_3 ( + .re (lp1_cmo_status_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[3].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_3_qs) + ); + + // Subregister 4 of Multireg lp1_cmo_status + // R[lp1_cmo_status_4]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_4 ( + .re (lp1_cmo_status_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[4].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_4_qs) + ); + + // Subregister 5 of Multireg lp1_cmo_status + // R[lp1_cmo_status_5]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_5 ( + .re (lp1_cmo_status_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[5].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_5_qs) + ); + + // Subregister 6 of Multireg lp1_cmo_status + // R[lp1_cmo_status_6]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_6 ( + .re (lp1_cmo_status_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[6].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_6_qs) + ); + + // Subregister 7 of Multireg lp1_cmo_status + // R[lp1_cmo_status_7]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_7 ( + .re (lp1_cmo_status_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[7].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_7_qs) + ); + + // Subregister 8 of Multireg lp1_cmo_status + // R[lp1_cmo_status_8]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_8 ( + .re (lp1_cmo_status_8_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[8].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_8_qs) + ); + + // Subregister 9 of Multireg lp1_cmo_status + // R[lp1_cmo_status_9]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_9 ( + .re (lp1_cmo_status_9_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[9].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_9_qs) + ); + + // Subregister 10 of Multireg lp1_cmo_status + // R[lp1_cmo_status_10]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_10 ( + .re (lp1_cmo_status_10_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[10].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_10_qs) + ); + + // Subregister 11 of Multireg lp1_cmo_status + // R[lp1_cmo_status_11]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_11 ( + .re (lp1_cmo_status_11_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[11].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_11_qs) + ); + + // Subregister 12 of Multireg lp1_cmo_status + // R[lp1_cmo_status_12]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_12 ( + .re (lp1_cmo_status_12_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[12].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_12_qs) + ); + + // Subregister 13 of Multireg lp1_cmo_status + // R[lp1_cmo_status_13]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_13 ( + .re (lp1_cmo_status_13_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[13].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_13_qs) + ); + + // Subregister 14 of Multireg lp1_cmo_status + // R[lp1_cmo_status_14]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_14 ( + .re (lp1_cmo_status_14_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[14].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_14_qs) + ); + + // Subregister 15 of Multireg lp1_cmo_status + // R[lp1_cmo_status_15]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_15 ( + .re (lp1_cmo_status_15_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[15].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_15_qs) + ); + + // Subregister 16 of Multireg lp1_cmo_status + // R[lp1_cmo_status_16]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_16 ( + .re (lp1_cmo_status_16_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[16].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_16_qs) + ); + + // Subregister 17 of Multireg lp1_cmo_status + // R[lp1_cmo_status_17]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_17 ( + .re (lp1_cmo_status_17_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[17].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_17_qs) + ); + + // Subregister 18 of Multireg lp1_cmo_status + // R[lp1_cmo_status_18]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_18 ( + .re (lp1_cmo_status_18_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[18].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_18_qs) + ); + + // Subregister 19 of Multireg lp1_cmo_status + // R[lp1_cmo_status_19]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_19 ( + .re (lp1_cmo_status_19_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[19].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_19_qs) + ); + + // Subregister 20 of Multireg lp1_cmo_status + // R[lp1_cmo_status_20]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_20 ( + .re (lp1_cmo_status_20_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[20].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_20_qs) + ); + + // Subregister 21 of Multireg lp1_cmo_status + // R[lp1_cmo_status_21]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_21 ( + .re (lp1_cmo_status_21_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[21].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_21_qs) + ); + + // Subregister 22 of Multireg lp1_cmo_status + // R[lp1_cmo_status_22]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_22 ( + .re (lp1_cmo_status_22_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[22].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_22_qs) + ); + + // Subregister 23 of Multireg lp1_cmo_status + // R[lp1_cmo_status_23]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_23 ( + .re (lp1_cmo_status_23_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[23].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_23_qs) + ); + + // Subregister 24 of Multireg lp1_cmo_status + // R[lp1_cmo_status_24]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_24 ( + .re (lp1_cmo_status_24_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[24].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_24_qs) + ); + + // Subregister 25 of Multireg lp1_cmo_status + // R[lp1_cmo_status_25]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_25 ( + .re (lp1_cmo_status_25_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[25].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_25_qs) + ); + + // Subregister 26 of Multireg lp1_cmo_status + // R[lp1_cmo_status_26]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_26 ( + .re (lp1_cmo_status_26_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[26].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_26_qs) + ); + + // Subregister 27 of Multireg lp1_cmo_status + // R[lp1_cmo_status_27]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_27 ( + .re (lp1_cmo_status_27_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[27].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_27_qs) + ); + + // Subregister 28 of Multireg lp1_cmo_status + // R[lp1_cmo_status_28]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_28 ( + .re (lp1_cmo_status_28_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[28].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_28_qs) + ); + + // Subregister 29 of Multireg lp1_cmo_status + // R[lp1_cmo_status_29]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_29 ( + .re (lp1_cmo_status_29_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[29].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_29_qs) + ); + + // Subregister 30 of Multireg lp1_cmo_status + // R[lp1_cmo_status_30]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_30 ( + .re (lp1_cmo_status_30_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[30].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_30_qs) + ); + + // Subregister 31 of Multireg lp1_cmo_status + // R[lp1_cmo_status_31]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_31 ( + .re (lp1_cmo_status_31_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[31].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_31_qs) + ); + + // Subregister 32 of Multireg lp1_cmo_status + // R[lp1_cmo_status_32]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_32 ( + .re (lp1_cmo_status_32_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[32].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_32_qs) + ); + + // Subregister 33 of Multireg lp1_cmo_status + // R[lp1_cmo_status_33]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_33 ( + .re (lp1_cmo_status_33_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[33].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_33_qs) + ); + + // Subregister 34 of Multireg lp1_cmo_status + // R[lp1_cmo_status_34]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_34 ( + .re (lp1_cmo_status_34_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[34].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_34_qs) + ); + + // Subregister 35 of Multireg lp1_cmo_status + // R[lp1_cmo_status_35]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_35 ( + .re (lp1_cmo_status_35_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[35].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_35_qs) + ); + + // Subregister 36 of Multireg lp1_cmo_status + // R[lp1_cmo_status_36]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_36 ( + .re (lp1_cmo_status_36_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[36].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_36_qs) + ); + + // Subregister 37 of Multireg lp1_cmo_status + // R[lp1_cmo_status_37]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_37 ( + .re (lp1_cmo_status_37_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[37].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_37_qs) + ); + + // Subregister 38 of Multireg lp1_cmo_status + // R[lp1_cmo_status_38]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_38 ( + .re (lp1_cmo_status_38_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[38].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_38_qs) + ); + + // Subregister 39 of Multireg lp1_cmo_status + // R[lp1_cmo_status_39]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_39 ( + .re (lp1_cmo_status_39_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[39].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_39_qs) + ); + + // Subregister 40 of Multireg lp1_cmo_status + // R[lp1_cmo_status_40]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_40 ( + .re (lp1_cmo_status_40_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[40].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_40_qs) + ); + + // Subregister 41 of Multireg lp1_cmo_status + // R[lp1_cmo_status_41]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_41 ( + .re (lp1_cmo_status_41_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[41].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_41_qs) + ); + + // Subregister 42 of Multireg lp1_cmo_status + // R[lp1_cmo_status_42]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_42 ( + .re (lp1_cmo_status_42_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[42].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_42_qs) + ); + + // Subregister 43 of Multireg lp1_cmo_status + // R[lp1_cmo_status_43]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_43 ( + .re (lp1_cmo_status_43_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[43].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_43_qs) + ); + + // Subregister 44 of Multireg lp1_cmo_status + // R[lp1_cmo_status_44]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_44 ( + .re (lp1_cmo_status_44_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[44].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_44_qs) + ); + + // Subregister 45 of Multireg lp1_cmo_status + // R[lp1_cmo_status_45]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_45 ( + .re (lp1_cmo_status_45_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[45].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_45_qs) + ); + + // Subregister 46 of Multireg lp1_cmo_status + // R[lp1_cmo_status_46]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_46 ( + .re (lp1_cmo_status_46_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[46].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_46_qs) + ); + + // Subregister 47 of Multireg lp1_cmo_status + // R[lp1_cmo_status_47]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_47 ( + .re (lp1_cmo_status_47_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[47].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_47_qs) + ); + + // Subregister 48 of Multireg lp1_cmo_status + // R[lp1_cmo_status_48]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_48 ( + .re (lp1_cmo_status_48_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[48].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_48_qs) + ); + + // Subregister 49 of Multireg lp1_cmo_status + // R[lp1_cmo_status_49]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_49 ( + .re (lp1_cmo_status_49_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[49].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_49_qs) + ); + + // Subregister 50 of Multireg lp1_cmo_status + // R[lp1_cmo_status_50]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_50 ( + .re (lp1_cmo_status_50_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[50].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_50_qs) + ); + + // Subregister 51 of Multireg lp1_cmo_status + // R[lp1_cmo_status_51]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_51 ( + .re (lp1_cmo_status_51_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[51].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_51_qs) + ); + + // Subregister 52 of Multireg lp1_cmo_status + // R[lp1_cmo_status_52]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_52 ( + .re (lp1_cmo_status_52_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[52].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_52_qs) + ); + + // Subregister 53 of Multireg lp1_cmo_status + // R[lp1_cmo_status_53]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_53 ( + .re (lp1_cmo_status_53_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[53].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_53_qs) + ); + + // Subregister 54 of Multireg lp1_cmo_status + // R[lp1_cmo_status_54]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_54 ( + .re (lp1_cmo_status_54_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[54].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_54_qs) + ); + + // Subregister 55 of Multireg lp1_cmo_status + // R[lp1_cmo_status_55]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_55 ( + .re (lp1_cmo_status_55_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[55].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_55_qs) + ); + + // Subregister 56 of Multireg lp1_cmo_status + // R[lp1_cmo_status_56]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_56 ( + .re (lp1_cmo_status_56_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[56].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_56_qs) + ); + + // Subregister 57 of Multireg lp1_cmo_status + // R[lp1_cmo_status_57]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_57 ( + .re (lp1_cmo_status_57_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[57].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_57_qs) + ); + + // Subregister 58 of Multireg lp1_cmo_status + // R[lp1_cmo_status_58]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_58 ( + .re (lp1_cmo_status_58_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[58].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_58_qs) + ); + + // Subregister 59 of Multireg lp1_cmo_status + // R[lp1_cmo_status_59]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_59 ( + .re (lp1_cmo_status_59_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[59].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_59_qs) + ); + + // Subregister 60 of Multireg lp1_cmo_status + // R[lp1_cmo_status_60]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_60 ( + .re (lp1_cmo_status_60_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[60].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_60_qs) + ); + + // Subregister 61 of Multireg lp1_cmo_status + // R[lp1_cmo_status_61]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_61 ( + .re (lp1_cmo_status_61_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[61].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_61_qs) + ); + + // Subregister 62 of Multireg lp1_cmo_status + // R[lp1_cmo_status_62]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_62 ( + .re (lp1_cmo_status_62_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[62].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_62_qs) + ); + + // Subregister 63 of Multireg lp1_cmo_status + // R[lp1_cmo_status_63]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_63 ( + .re (lp1_cmo_status_63_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[63].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_63_qs) + ); + + // Subregister 64 of Multireg lp1_cmo_status + // R[lp1_cmo_status_64]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_64 ( + .re (lp1_cmo_status_64_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[64].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_64_qs) + ); + + // Subregister 65 of Multireg lp1_cmo_status + // R[lp1_cmo_status_65]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_65 ( + .re (lp1_cmo_status_65_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[65].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_65_qs) + ); + + // Subregister 66 of Multireg lp1_cmo_status + // R[lp1_cmo_status_66]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_66 ( + .re (lp1_cmo_status_66_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[66].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_66_qs) + ); + + // Subregister 67 of Multireg lp1_cmo_status + // R[lp1_cmo_status_67]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_67 ( + .re (lp1_cmo_status_67_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[67].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_67_qs) + ); + + // Subregister 68 of Multireg lp1_cmo_status + // R[lp1_cmo_status_68]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_68 ( + .re (lp1_cmo_status_68_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[68].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_68_qs) + ); + + // Subregister 69 of Multireg lp1_cmo_status + // R[lp1_cmo_status_69]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_69 ( + .re (lp1_cmo_status_69_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[69].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_69_qs) + ); + + // Subregister 70 of Multireg lp1_cmo_status + // R[lp1_cmo_status_70]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_70 ( + .re (lp1_cmo_status_70_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[70].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_70_qs) + ); + + // Subregister 71 of Multireg lp1_cmo_status + // R[lp1_cmo_status_71]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_71 ( + .re (lp1_cmo_status_71_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[71].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_71_qs) + ); + + // Subregister 72 of Multireg lp1_cmo_status + // R[lp1_cmo_status_72]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_72 ( + .re (lp1_cmo_status_72_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[72].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_72_qs) + ); + + // Subregister 73 of Multireg lp1_cmo_status + // R[lp1_cmo_status_73]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_73 ( + .re (lp1_cmo_status_73_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[73].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_73_qs) + ); + + // Subregister 74 of Multireg lp1_cmo_status + // R[lp1_cmo_status_74]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_74 ( + .re (lp1_cmo_status_74_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[74].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_74_qs) + ); + + // Subregister 75 of Multireg lp1_cmo_status + // R[lp1_cmo_status_75]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_75 ( + .re (lp1_cmo_status_75_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[75].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_75_qs) + ); + + // Subregister 76 of Multireg lp1_cmo_status + // R[lp1_cmo_status_76]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_76 ( + .re (lp1_cmo_status_76_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[76].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_76_qs) + ); + + // Subregister 77 of Multireg lp1_cmo_status + // R[lp1_cmo_status_77]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_77 ( + .re (lp1_cmo_status_77_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[77].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_77_qs) + ); + + // Subregister 78 of Multireg lp1_cmo_status + // R[lp1_cmo_status_78]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_78 ( + .re (lp1_cmo_status_78_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[78].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_78_qs) + ); + + // Subregister 79 of Multireg lp1_cmo_status + // R[lp1_cmo_status_79]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_79 ( + .re (lp1_cmo_status_79_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[79].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_79_qs) + ); + + // Subregister 80 of Multireg lp1_cmo_status + // R[lp1_cmo_status_80]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_80 ( + .re (lp1_cmo_status_80_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[80].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_80_qs) + ); + + // Subregister 81 of Multireg lp1_cmo_status + // R[lp1_cmo_status_81]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_81 ( + .re (lp1_cmo_status_81_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[81].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_81_qs) + ); + + // Subregister 82 of Multireg lp1_cmo_status + // R[lp1_cmo_status_82]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_82 ( + .re (lp1_cmo_status_82_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[82].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_82_qs) + ); + + // Subregister 83 of Multireg lp1_cmo_status + // R[lp1_cmo_status_83]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_83 ( + .re (lp1_cmo_status_83_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[83].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_83_qs) + ); + + // Subregister 84 of Multireg lp1_cmo_status + // R[lp1_cmo_status_84]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_84 ( + .re (lp1_cmo_status_84_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[84].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_84_qs) + ); + + // Subregister 85 of Multireg lp1_cmo_status + // R[lp1_cmo_status_85]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_85 ( + .re (lp1_cmo_status_85_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[85].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_85_qs) + ); + + // Subregister 86 of Multireg lp1_cmo_status + // R[lp1_cmo_status_86]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_86 ( + .re (lp1_cmo_status_86_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[86].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_86_qs) + ); + + // Subregister 87 of Multireg lp1_cmo_status + // R[lp1_cmo_status_87]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_87 ( + .re (lp1_cmo_status_87_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[87].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_87_qs) + ); + + // Subregister 88 of Multireg lp1_cmo_status + // R[lp1_cmo_status_88]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_88 ( + .re (lp1_cmo_status_88_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[88].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_88_qs) + ); + + // Subregister 89 of Multireg lp1_cmo_status + // R[lp1_cmo_status_89]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_89 ( + .re (lp1_cmo_status_89_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[89].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_89_qs) + ); + + // Subregister 90 of Multireg lp1_cmo_status + // R[lp1_cmo_status_90]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_90 ( + .re (lp1_cmo_status_90_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[90].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_90_qs) + ); + + // Subregister 91 of Multireg lp1_cmo_status + // R[lp1_cmo_status_91]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_91 ( + .re (lp1_cmo_status_91_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[91].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_91_qs) + ); + + // Subregister 92 of Multireg lp1_cmo_status + // R[lp1_cmo_status_92]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_92 ( + .re (lp1_cmo_status_92_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[92].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_92_qs) + ); + + // Subregister 93 of Multireg lp1_cmo_status + // R[lp1_cmo_status_93]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_93 ( + .re (lp1_cmo_status_93_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[93].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_93_qs) + ); + + // Subregister 94 of Multireg lp1_cmo_status + // R[lp1_cmo_status_94]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_94 ( + .re (lp1_cmo_status_94_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[94].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_94_qs) + ); + + // Subregister 95 of Multireg lp1_cmo_status + // R[lp1_cmo_status_95]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_95 ( + .re (lp1_cmo_status_95_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[95].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_95_qs) + ); + + // Subregister 96 of Multireg lp1_cmo_status + // R[lp1_cmo_status_96]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_96 ( + .re (lp1_cmo_status_96_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[96].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_96_qs) + ); + + // Subregister 97 of Multireg lp1_cmo_status + // R[lp1_cmo_status_97]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_97 ( + .re (lp1_cmo_status_97_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[97].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_97_qs) + ); + + // Subregister 98 of Multireg lp1_cmo_status + // R[lp1_cmo_status_98]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_98 ( + .re (lp1_cmo_status_98_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[98].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_98_qs) + ); + + // Subregister 99 of Multireg lp1_cmo_status + // R[lp1_cmo_status_99]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_99 ( + .re (lp1_cmo_status_99_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[99].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_99_qs) + ); + + // Subregister 100 of Multireg lp1_cmo_status + // R[lp1_cmo_status_100]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_100 ( + .re (lp1_cmo_status_100_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[100].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_100_qs) + ); + + // Subregister 101 of Multireg lp1_cmo_status + // R[lp1_cmo_status_101]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_101 ( + .re (lp1_cmo_status_101_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[101].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_101_qs) + ); + + // Subregister 102 of Multireg lp1_cmo_status + // R[lp1_cmo_status_102]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_102 ( + .re (lp1_cmo_status_102_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[102].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_102_qs) + ); + + // Subregister 103 of Multireg lp1_cmo_status + // R[lp1_cmo_status_103]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_103 ( + .re (lp1_cmo_status_103_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[103].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_103_qs) + ); + + // Subregister 104 of Multireg lp1_cmo_status + // R[lp1_cmo_status_104]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_104 ( + .re (lp1_cmo_status_104_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[104].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_104_qs) + ); + + // Subregister 105 of Multireg lp1_cmo_status + // R[lp1_cmo_status_105]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_105 ( + .re (lp1_cmo_status_105_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[105].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_105_qs) + ); + + // Subregister 106 of Multireg lp1_cmo_status + // R[lp1_cmo_status_106]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_106 ( + .re (lp1_cmo_status_106_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[106].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_106_qs) + ); + + // Subregister 107 of Multireg lp1_cmo_status + // R[lp1_cmo_status_107]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_107 ( + .re (lp1_cmo_status_107_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[107].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_107_qs) + ); + + // Subregister 108 of Multireg lp1_cmo_status + // R[lp1_cmo_status_108]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_108 ( + .re (lp1_cmo_status_108_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[108].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_108_qs) + ); + + // Subregister 109 of Multireg lp1_cmo_status + // R[lp1_cmo_status_109]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_109 ( + .re (lp1_cmo_status_109_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[109].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_109_qs) + ); + + // Subregister 110 of Multireg lp1_cmo_status + // R[lp1_cmo_status_110]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_110 ( + .re (lp1_cmo_status_110_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[110].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_110_qs) + ); + + // Subregister 111 of Multireg lp1_cmo_status + // R[lp1_cmo_status_111]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_111 ( + .re (lp1_cmo_status_111_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[111].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_111_qs) + ); + + // Subregister 112 of Multireg lp1_cmo_status + // R[lp1_cmo_status_112]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_112 ( + .re (lp1_cmo_status_112_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[112].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_112_qs) + ); + + // Subregister 113 of Multireg lp1_cmo_status + // R[lp1_cmo_status_113]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_113 ( + .re (lp1_cmo_status_113_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[113].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_113_qs) + ); + + // Subregister 114 of Multireg lp1_cmo_status + // R[lp1_cmo_status_114]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_114 ( + .re (lp1_cmo_status_114_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[114].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_114_qs) + ); + + // Subregister 115 of Multireg lp1_cmo_status + // R[lp1_cmo_status_115]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_115 ( + .re (lp1_cmo_status_115_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[115].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_115_qs) + ); + + // Subregister 116 of Multireg lp1_cmo_status + // R[lp1_cmo_status_116]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_116 ( + .re (lp1_cmo_status_116_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[116].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_116_qs) + ); + + // Subregister 117 of Multireg lp1_cmo_status + // R[lp1_cmo_status_117]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_117 ( + .re (lp1_cmo_status_117_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[117].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_117_qs) + ); + + // Subregister 118 of Multireg lp1_cmo_status + // R[lp1_cmo_status_118]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_118 ( + .re (lp1_cmo_status_118_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[118].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_118_qs) + ); + + // Subregister 119 of Multireg lp1_cmo_status + // R[lp1_cmo_status_119]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_119 ( + .re (lp1_cmo_status_119_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[119].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_119_qs) + ); + + // Subregister 120 of Multireg lp1_cmo_status + // R[lp1_cmo_status_120]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_120 ( + .re (lp1_cmo_status_120_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[120].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_120_qs) + ); + + // Subregister 121 of Multireg lp1_cmo_status + // R[lp1_cmo_status_121]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_121 ( + .re (lp1_cmo_status_121_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[121].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_121_qs) + ); + + // Subregister 122 of Multireg lp1_cmo_status + // R[lp1_cmo_status_122]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_122 ( + .re (lp1_cmo_status_122_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[122].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_122_qs) + ); + + // Subregister 123 of Multireg lp1_cmo_status + // R[lp1_cmo_status_123]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_123 ( + .re (lp1_cmo_status_123_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[123].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_123_qs) + ); + + // Subregister 124 of Multireg lp1_cmo_status + // R[lp1_cmo_status_124]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_124 ( + .re (lp1_cmo_status_124_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[124].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_124_qs) + ); + + // Subregister 125 of Multireg lp1_cmo_status + // R[lp1_cmo_status_125]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_125 ( + .re (lp1_cmo_status_125_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[125].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_125_qs) + ); + + // Subregister 126 of Multireg lp1_cmo_status + // R[lp1_cmo_status_126]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_126 ( + .re (lp1_cmo_status_126_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[126].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_126_qs) + ); + + // Subregister 127 of Multireg lp1_cmo_status + // R[lp1_cmo_status_127]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_127 ( + .re (lp1_cmo_status_127_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[127].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_127_qs) + ); + + // Subregister 128 of Multireg lp1_cmo_status + // R[lp1_cmo_status_128]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_128 ( + .re (lp1_cmo_status_128_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[128].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_128_qs) + ); + + // Subregister 129 of Multireg lp1_cmo_status + // R[lp1_cmo_status_129]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_129 ( + .re (lp1_cmo_status_129_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[129].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_129_qs) + ); + + // Subregister 130 of Multireg lp1_cmo_status + // R[lp1_cmo_status_130]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_130 ( + .re (lp1_cmo_status_130_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[130].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_130_qs) + ); + + // Subregister 131 of Multireg lp1_cmo_status + // R[lp1_cmo_status_131]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_131 ( + .re (lp1_cmo_status_131_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[131].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_131_qs) + ); + + // Subregister 132 of Multireg lp1_cmo_status + // R[lp1_cmo_status_132]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_132 ( + .re (lp1_cmo_status_132_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[132].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_132_qs) + ); + + // Subregister 133 of Multireg lp1_cmo_status + // R[lp1_cmo_status_133]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_133 ( + .re (lp1_cmo_status_133_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[133].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_133_qs) + ); + + // Subregister 134 of Multireg lp1_cmo_status + // R[lp1_cmo_status_134]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_134 ( + .re (lp1_cmo_status_134_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[134].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_134_qs) + ); + + // Subregister 135 of Multireg lp1_cmo_status + // R[lp1_cmo_status_135]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_135 ( + .re (lp1_cmo_status_135_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[135].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_135_qs) + ); + + // Subregister 136 of Multireg lp1_cmo_status + // R[lp1_cmo_status_136]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_136 ( + .re (lp1_cmo_status_136_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[136].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_136_qs) + ); + + // Subregister 137 of Multireg lp1_cmo_status + // R[lp1_cmo_status_137]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_137 ( + .re (lp1_cmo_status_137_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[137].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_137_qs) + ); + + // Subregister 138 of Multireg lp1_cmo_status + // R[lp1_cmo_status_138]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_138 ( + .re (lp1_cmo_status_138_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[138].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_138_qs) + ); + + // Subregister 139 of Multireg lp1_cmo_status + // R[lp1_cmo_status_139]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_139 ( + .re (lp1_cmo_status_139_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[139].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_139_qs) + ); + + // Subregister 140 of Multireg lp1_cmo_status + // R[lp1_cmo_status_140]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_140 ( + .re (lp1_cmo_status_140_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[140].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_140_qs) + ); + + // Subregister 141 of Multireg lp1_cmo_status + // R[lp1_cmo_status_141]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_141 ( + .re (lp1_cmo_status_141_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[141].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_141_qs) + ); + + // Subregister 142 of Multireg lp1_cmo_status + // R[lp1_cmo_status_142]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_142 ( + .re (lp1_cmo_status_142_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[142].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_142_qs) + ); + + // Subregister 143 of Multireg lp1_cmo_status + // R[lp1_cmo_status_143]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_143 ( + .re (lp1_cmo_status_143_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[143].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_143_qs) + ); + + // Subregister 144 of Multireg lp1_cmo_status + // R[lp1_cmo_status_144]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_144 ( + .re (lp1_cmo_status_144_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[144].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_144_qs) + ); + + // Subregister 145 of Multireg lp1_cmo_status + // R[lp1_cmo_status_145]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_145 ( + .re (lp1_cmo_status_145_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[145].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_145_qs) + ); + + // Subregister 146 of Multireg lp1_cmo_status + // R[lp1_cmo_status_146]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_146 ( + .re (lp1_cmo_status_146_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[146].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_146_qs) + ); + + // Subregister 147 of Multireg lp1_cmo_status + // R[lp1_cmo_status_147]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_147 ( + .re (lp1_cmo_status_147_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[147].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_147_qs) + ); + + // Subregister 148 of Multireg lp1_cmo_status + // R[lp1_cmo_status_148]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_148 ( + .re (lp1_cmo_status_148_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[148].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_148_qs) + ); + + // Subregister 149 of Multireg lp1_cmo_status + // R[lp1_cmo_status_149]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_149 ( + .re (lp1_cmo_status_149_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[149].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_149_qs) + ); + + // Subregister 150 of Multireg lp1_cmo_status + // R[lp1_cmo_status_150]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_150 ( + .re (lp1_cmo_status_150_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[150].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_150_qs) + ); + + // Subregister 151 of Multireg lp1_cmo_status + // R[lp1_cmo_status_151]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_151 ( + .re (lp1_cmo_status_151_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[151].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_151_qs) + ); + + // Subregister 152 of Multireg lp1_cmo_status + // R[lp1_cmo_status_152]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_152 ( + .re (lp1_cmo_status_152_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[152].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_152_qs) + ); + + // Subregister 153 of Multireg lp1_cmo_status + // R[lp1_cmo_status_153]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_153 ( + .re (lp1_cmo_status_153_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[153].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_153_qs) + ); + + // Subregister 154 of Multireg lp1_cmo_status + // R[lp1_cmo_status_154]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_154 ( + .re (lp1_cmo_status_154_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[154].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_154_qs) + ); + + // Subregister 155 of Multireg lp1_cmo_status + // R[lp1_cmo_status_155]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_155 ( + .re (lp1_cmo_status_155_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[155].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_155_qs) + ); + + // Subregister 156 of Multireg lp1_cmo_status + // R[lp1_cmo_status_156]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_156 ( + .re (lp1_cmo_status_156_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[156].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_156_qs) + ); + + // Subregister 157 of Multireg lp1_cmo_status + // R[lp1_cmo_status_157]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_157 ( + .re (lp1_cmo_status_157_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[157].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_157_qs) + ); + + // Subregister 158 of Multireg lp1_cmo_status + // R[lp1_cmo_status_158]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_158 ( + .re (lp1_cmo_status_158_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[158].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_158_qs) + ); + + // Subregister 159 of Multireg lp1_cmo_status + // R[lp1_cmo_status_159]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_159 ( + .re (lp1_cmo_status_159_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[159].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_159_qs) + ); + + // Subregister 160 of Multireg lp1_cmo_status + // R[lp1_cmo_status_160]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_160 ( + .re (lp1_cmo_status_160_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[160].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_160_qs) + ); + + // Subregister 161 of Multireg lp1_cmo_status + // R[lp1_cmo_status_161]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_161 ( + .re (lp1_cmo_status_161_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[161].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_161_qs) + ); + + // Subregister 162 of Multireg lp1_cmo_status + // R[lp1_cmo_status_162]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_162 ( + .re (lp1_cmo_status_162_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[162].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_162_qs) + ); + + // Subregister 163 of Multireg lp1_cmo_status + // R[lp1_cmo_status_163]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_163 ( + .re (lp1_cmo_status_163_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[163].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_163_qs) + ); + + // Subregister 164 of Multireg lp1_cmo_status + // R[lp1_cmo_status_164]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_164 ( + .re (lp1_cmo_status_164_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[164].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_164_qs) + ); + + // Subregister 165 of Multireg lp1_cmo_status + // R[lp1_cmo_status_165]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_165 ( + .re (lp1_cmo_status_165_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[165].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_165_qs) + ); + + // Subregister 166 of Multireg lp1_cmo_status + // R[lp1_cmo_status_166]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_166 ( + .re (lp1_cmo_status_166_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[166].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_166_qs) + ); + + // Subregister 167 of Multireg lp1_cmo_status + // R[lp1_cmo_status_167]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_167 ( + .re (lp1_cmo_status_167_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[167].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_167_qs) + ); + + // Subregister 168 of Multireg lp1_cmo_status + // R[lp1_cmo_status_168]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_168 ( + .re (lp1_cmo_status_168_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[168].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_168_qs) + ); + + // Subregister 169 of Multireg lp1_cmo_status + // R[lp1_cmo_status_169]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_169 ( + .re (lp1_cmo_status_169_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[169].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_169_qs) + ); + + // Subregister 170 of Multireg lp1_cmo_status + // R[lp1_cmo_status_170]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_170 ( + .re (lp1_cmo_status_170_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[170].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_170_qs) + ); + + // Subregister 171 of Multireg lp1_cmo_status + // R[lp1_cmo_status_171]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_171 ( + .re (lp1_cmo_status_171_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[171].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_171_qs) + ); + + // Subregister 172 of Multireg lp1_cmo_status + // R[lp1_cmo_status_172]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_172 ( + .re (lp1_cmo_status_172_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[172].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_172_qs) + ); + + // Subregister 173 of Multireg lp1_cmo_status + // R[lp1_cmo_status_173]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_173 ( + .re (lp1_cmo_status_173_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[173].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_173_qs) + ); + + // Subregister 174 of Multireg lp1_cmo_status + // R[lp1_cmo_status_174]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_174 ( + .re (lp1_cmo_status_174_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[174].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_174_qs) + ); + + // Subregister 175 of Multireg lp1_cmo_status + // R[lp1_cmo_status_175]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_175 ( + .re (lp1_cmo_status_175_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[175].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_175_qs) + ); + + // Subregister 176 of Multireg lp1_cmo_status + // R[lp1_cmo_status_176]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_176 ( + .re (lp1_cmo_status_176_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[176].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_176_qs) + ); + + // Subregister 177 of Multireg lp1_cmo_status + // R[lp1_cmo_status_177]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_177 ( + .re (lp1_cmo_status_177_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[177].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_177_qs) + ); + + // Subregister 178 of Multireg lp1_cmo_status + // R[lp1_cmo_status_178]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_178 ( + .re (lp1_cmo_status_178_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[178].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_178_qs) + ); + + // Subregister 179 of Multireg lp1_cmo_status + // R[lp1_cmo_status_179]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_179 ( + .re (lp1_cmo_status_179_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[179].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_179_qs) + ); + + // Subregister 180 of Multireg lp1_cmo_status + // R[lp1_cmo_status_180]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_180 ( + .re (lp1_cmo_status_180_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[180].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_180_qs) + ); + + // Subregister 181 of Multireg lp1_cmo_status + // R[lp1_cmo_status_181]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_181 ( + .re (lp1_cmo_status_181_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[181].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_181_qs) + ); + + // Subregister 182 of Multireg lp1_cmo_status + // R[lp1_cmo_status_182]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_182 ( + .re (lp1_cmo_status_182_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[182].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_182_qs) + ); + + // Subregister 183 of Multireg lp1_cmo_status + // R[lp1_cmo_status_183]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_183 ( + .re (lp1_cmo_status_183_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[183].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_183_qs) + ); + + // Subregister 184 of Multireg lp1_cmo_status + // R[lp1_cmo_status_184]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_184 ( + .re (lp1_cmo_status_184_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[184].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_184_qs) + ); + + // Subregister 185 of Multireg lp1_cmo_status + // R[lp1_cmo_status_185]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_185 ( + .re (lp1_cmo_status_185_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[185].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_185_qs) + ); + + // Subregister 186 of Multireg lp1_cmo_status + // R[lp1_cmo_status_186]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_186 ( + .re (lp1_cmo_status_186_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[186].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_186_qs) + ); + + // Subregister 187 of Multireg lp1_cmo_status + // R[lp1_cmo_status_187]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_187 ( + .re (lp1_cmo_status_187_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[187].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_187_qs) + ); + + // Subregister 188 of Multireg lp1_cmo_status + // R[lp1_cmo_status_188]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_188 ( + .re (lp1_cmo_status_188_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[188].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_188_qs) + ); + + // Subregister 189 of Multireg lp1_cmo_status + // R[lp1_cmo_status_189]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_189 ( + .re (lp1_cmo_status_189_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[189].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_189_qs) + ); + + // Subregister 190 of Multireg lp1_cmo_status + // R[lp1_cmo_status_190]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_190 ( + .re (lp1_cmo_status_190_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[190].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_190_qs) + ); + + // Subregister 191 of Multireg lp1_cmo_status + // R[lp1_cmo_status_191]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_191 ( + .re (lp1_cmo_status_191_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[191].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_191_qs) + ); + + // Subregister 192 of Multireg lp1_cmo_status + // R[lp1_cmo_status_192]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_192 ( + .re (lp1_cmo_status_192_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[192].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_192_qs) + ); + + // Subregister 193 of Multireg lp1_cmo_status + // R[lp1_cmo_status_193]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_193 ( + .re (lp1_cmo_status_193_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[193].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_193_qs) + ); + + // Subregister 194 of Multireg lp1_cmo_status + // R[lp1_cmo_status_194]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_194 ( + .re (lp1_cmo_status_194_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[194].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_194_qs) + ); + + // Subregister 195 of Multireg lp1_cmo_status + // R[lp1_cmo_status_195]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_195 ( + .re (lp1_cmo_status_195_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[195].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_195_qs) + ); + + // Subregister 196 of Multireg lp1_cmo_status + // R[lp1_cmo_status_196]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_196 ( + .re (lp1_cmo_status_196_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[196].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_196_qs) + ); + + // Subregister 197 of Multireg lp1_cmo_status + // R[lp1_cmo_status_197]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_197 ( + .re (lp1_cmo_status_197_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[197].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_197_qs) + ); + + // Subregister 198 of Multireg lp1_cmo_status + // R[lp1_cmo_status_198]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_198 ( + .re (lp1_cmo_status_198_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[198].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_198_qs) + ); + + // Subregister 199 of Multireg lp1_cmo_status + // R[lp1_cmo_status_199]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_199 ( + .re (lp1_cmo_status_199_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[199].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_199_qs) + ); + + // Subregister 200 of Multireg lp1_cmo_status + // R[lp1_cmo_status_200]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_200 ( + .re (lp1_cmo_status_200_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[200].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_200_qs) + ); + + // Subregister 201 of Multireg lp1_cmo_status + // R[lp1_cmo_status_201]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_201 ( + .re (lp1_cmo_status_201_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[201].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_201_qs) + ); + + // Subregister 202 of Multireg lp1_cmo_status + // R[lp1_cmo_status_202]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_202 ( + .re (lp1_cmo_status_202_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[202].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_202_qs) + ); + + // Subregister 203 of Multireg lp1_cmo_status + // R[lp1_cmo_status_203]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_203 ( + .re (lp1_cmo_status_203_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[203].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_203_qs) + ); + + // Subregister 204 of Multireg lp1_cmo_status + // R[lp1_cmo_status_204]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_204 ( + .re (lp1_cmo_status_204_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[204].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_204_qs) + ); + + // Subregister 205 of Multireg lp1_cmo_status + // R[lp1_cmo_status_205]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_205 ( + .re (lp1_cmo_status_205_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[205].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_205_qs) + ); + + // Subregister 206 of Multireg lp1_cmo_status + // R[lp1_cmo_status_206]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_206 ( + .re (lp1_cmo_status_206_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[206].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_206_qs) + ); + + // Subregister 207 of Multireg lp1_cmo_status + // R[lp1_cmo_status_207]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_207 ( + .re (lp1_cmo_status_207_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[207].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_207_qs) + ); + + // Subregister 208 of Multireg lp1_cmo_status + // R[lp1_cmo_status_208]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_208 ( + .re (lp1_cmo_status_208_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[208].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_208_qs) + ); + + // Subregister 209 of Multireg lp1_cmo_status + // R[lp1_cmo_status_209]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_209 ( + .re (lp1_cmo_status_209_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[209].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_209_qs) + ); + + // Subregister 210 of Multireg lp1_cmo_status + // R[lp1_cmo_status_210]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_210 ( + .re (lp1_cmo_status_210_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[210].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_210_qs) + ); + + // Subregister 211 of Multireg lp1_cmo_status + // R[lp1_cmo_status_211]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_211 ( + .re (lp1_cmo_status_211_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[211].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_211_qs) + ); + + // Subregister 212 of Multireg lp1_cmo_status + // R[lp1_cmo_status_212]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_212 ( + .re (lp1_cmo_status_212_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[212].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_212_qs) + ); + + // Subregister 213 of Multireg lp1_cmo_status + // R[lp1_cmo_status_213]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_213 ( + .re (lp1_cmo_status_213_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[213].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_213_qs) + ); + + // Subregister 214 of Multireg lp1_cmo_status + // R[lp1_cmo_status_214]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_214 ( + .re (lp1_cmo_status_214_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[214].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_214_qs) + ); + + // Subregister 215 of Multireg lp1_cmo_status + // R[lp1_cmo_status_215]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_215 ( + .re (lp1_cmo_status_215_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[215].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_215_qs) + ); + + // Subregister 216 of Multireg lp1_cmo_status + // R[lp1_cmo_status_216]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_216 ( + .re (lp1_cmo_status_216_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[216].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_216_qs) + ); + + // Subregister 217 of Multireg lp1_cmo_status + // R[lp1_cmo_status_217]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_217 ( + .re (lp1_cmo_status_217_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[217].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_217_qs) + ); + + // Subregister 218 of Multireg lp1_cmo_status + // R[lp1_cmo_status_218]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_218 ( + .re (lp1_cmo_status_218_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[218].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_218_qs) + ); + + // Subregister 219 of Multireg lp1_cmo_status + // R[lp1_cmo_status_219]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_219 ( + .re (lp1_cmo_status_219_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[219].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_219_qs) + ); + + // Subregister 220 of Multireg lp1_cmo_status + // R[lp1_cmo_status_220]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_220 ( + .re (lp1_cmo_status_220_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[220].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_220_qs) + ); + + // Subregister 221 of Multireg lp1_cmo_status + // R[lp1_cmo_status_221]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_221 ( + .re (lp1_cmo_status_221_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[221].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_221_qs) + ); + + // Subregister 222 of Multireg lp1_cmo_status + // R[lp1_cmo_status_222]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_222 ( + .re (lp1_cmo_status_222_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[222].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_222_qs) + ); + + // Subregister 223 of Multireg lp1_cmo_status + // R[lp1_cmo_status_223]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_223 ( + .re (lp1_cmo_status_223_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[223].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_223_qs) + ); + + // Subregister 224 of Multireg lp1_cmo_status + // R[lp1_cmo_status_224]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_224 ( + .re (lp1_cmo_status_224_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[224].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_224_qs) + ); + + // Subregister 225 of Multireg lp1_cmo_status + // R[lp1_cmo_status_225]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_225 ( + .re (lp1_cmo_status_225_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[225].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_225_qs) + ); + + // Subregister 226 of Multireg lp1_cmo_status + // R[lp1_cmo_status_226]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_226 ( + .re (lp1_cmo_status_226_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[226].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_226_qs) + ); + + // Subregister 227 of Multireg lp1_cmo_status + // R[lp1_cmo_status_227]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_227 ( + .re (lp1_cmo_status_227_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[227].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_227_qs) + ); + + // Subregister 228 of Multireg lp1_cmo_status + // R[lp1_cmo_status_228]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_228 ( + .re (lp1_cmo_status_228_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[228].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_228_qs) + ); + + // Subregister 229 of Multireg lp1_cmo_status + // R[lp1_cmo_status_229]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_229 ( + .re (lp1_cmo_status_229_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[229].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_229_qs) + ); + + // Subregister 230 of Multireg lp1_cmo_status + // R[lp1_cmo_status_230]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_230 ( + .re (lp1_cmo_status_230_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[230].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_230_qs) + ); + + // Subregister 231 of Multireg lp1_cmo_status + // R[lp1_cmo_status_231]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_231 ( + .re (lp1_cmo_status_231_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[231].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_231_qs) + ); + + // Subregister 232 of Multireg lp1_cmo_status + // R[lp1_cmo_status_232]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_232 ( + .re (lp1_cmo_status_232_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[232].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_232_qs) + ); + + // Subregister 233 of Multireg lp1_cmo_status + // R[lp1_cmo_status_233]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_233 ( + .re (lp1_cmo_status_233_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[233].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_233_qs) + ); + + // Subregister 234 of Multireg lp1_cmo_status + // R[lp1_cmo_status_234]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_234 ( + .re (lp1_cmo_status_234_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[234].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_234_qs) + ); + + // Subregister 235 of Multireg lp1_cmo_status + // R[lp1_cmo_status_235]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_235 ( + .re (lp1_cmo_status_235_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[235].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_235_qs) + ); + + // Subregister 236 of Multireg lp1_cmo_status + // R[lp1_cmo_status_236]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_236 ( + .re (lp1_cmo_status_236_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[236].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_236_qs) + ); + + // Subregister 237 of Multireg lp1_cmo_status + // R[lp1_cmo_status_237]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_237 ( + .re (lp1_cmo_status_237_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[237].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_237_qs) + ); + + // Subregister 238 of Multireg lp1_cmo_status + // R[lp1_cmo_status_238]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_238 ( + .re (lp1_cmo_status_238_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[238].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_238_qs) + ); + + // Subregister 239 of Multireg lp1_cmo_status + // R[lp1_cmo_status_239]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_239 ( + .re (lp1_cmo_status_239_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[239].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_239_qs) + ); + + // Subregister 240 of Multireg lp1_cmo_status + // R[lp1_cmo_status_240]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_240 ( + .re (lp1_cmo_status_240_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[240].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_240_qs) + ); + + // Subregister 241 of Multireg lp1_cmo_status + // R[lp1_cmo_status_241]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_241 ( + .re (lp1_cmo_status_241_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[241].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_241_qs) + ); + + // Subregister 242 of Multireg lp1_cmo_status + // R[lp1_cmo_status_242]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_242 ( + .re (lp1_cmo_status_242_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[242].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_242_qs) + ); + + // Subregister 243 of Multireg lp1_cmo_status + // R[lp1_cmo_status_243]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_243 ( + .re (lp1_cmo_status_243_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[243].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_243_qs) + ); + + // Subregister 244 of Multireg lp1_cmo_status + // R[lp1_cmo_status_244]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_244 ( + .re (lp1_cmo_status_244_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[244].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_244_qs) + ); + + // Subregister 245 of Multireg lp1_cmo_status + // R[lp1_cmo_status_245]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_245 ( + .re (lp1_cmo_status_245_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[245].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_245_qs) + ); + + // Subregister 246 of Multireg lp1_cmo_status + // R[lp1_cmo_status_246]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_246 ( + .re (lp1_cmo_status_246_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[246].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_246_qs) + ); + + // Subregister 247 of Multireg lp1_cmo_status + // R[lp1_cmo_status_247]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_247 ( + .re (lp1_cmo_status_247_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[247].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_247_qs) + ); + + // Subregister 248 of Multireg lp1_cmo_status + // R[lp1_cmo_status_248]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_248 ( + .re (lp1_cmo_status_248_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[248].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_248_qs) + ); + + // Subregister 249 of Multireg lp1_cmo_status + // R[lp1_cmo_status_249]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_249 ( + .re (lp1_cmo_status_249_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[249].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_249_qs) + ); + + // Subregister 250 of Multireg lp1_cmo_status + // R[lp1_cmo_status_250]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_250 ( + .re (lp1_cmo_status_250_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[250].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_250_qs) + ); + + // Subregister 251 of Multireg lp1_cmo_status + // R[lp1_cmo_status_251]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_251 ( + .re (lp1_cmo_status_251_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[251].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_251_qs) + ); + + // Subregister 252 of Multireg lp1_cmo_status + // R[lp1_cmo_status_252]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_252 ( + .re (lp1_cmo_status_252_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[252].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_252_qs) + ); + + // Subregister 253 of Multireg lp1_cmo_status + // R[lp1_cmo_status_253]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_253 ( + .re (lp1_cmo_status_253_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[253].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_253_qs) + ); + + // Subregister 254 of Multireg lp1_cmo_status + // R[lp1_cmo_status_254]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_254 ( + .re (lp1_cmo_status_254_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[254].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_254_qs) + ); + + // Subregister 255 of Multireg lp1_cmo_status + // R[lp1_cmo_status_255]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_lp1_cmo_status_255 ( + .re (lp1_cmo_status_255_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.lp1_cmo_status[255].d), + .qre (), + .qe (), + .q (), + .qs (lp1_cmo_status_255_qs) + ); + + + + + logic [1040:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET); + addr_hit[ 1] = (reg_addr == CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET); + addr_hit[ 3] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET); + addr_hit[ 4] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET); + addr_hit[ 5] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET); + addr_hit[ 6] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET); + addr_hit[ 7] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET); + addr_hit[ 8] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_OFFSET); + addr_hit[ 9] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_OFFSET); + addr_hit[ 10] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET); + addr_hit[ 11] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET); + addr_hit[ 12] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET); + addr_hit[ 13] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET); + addr_hit[ 14] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET); + addr_hit[ 15] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET); + addr_hit[ 16] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET); + addr_hit[ 17] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_OFFSET); + addr_hit[ 18] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_OFFSET); + addr_hit[ 19] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_OFFSET); + addr_hit[ 20] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_OFFSET); + addr_hit[ 21] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_OFFSET); + addr_hit[ 22] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_OFFSET); + addr_hit[ 23] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_OFFSET); + addr_hit[ 24] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_OFFSET); + addr_hit[ 25] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_OFFSET); + addr_hit[ 26] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_OFFSET); + addr_hit[ 27] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_OFFSET); + addr_hit[ 28] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_OFFSET); + addr_hit[ 29] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_OFFSET); + addr_hit[ 30] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_OFFSET); + addr_hit[ 31] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_OFFSET); + addr_hit[ 32] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_OFFSET); + addr_hit[ 33] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_OFFSET); + addr_hit[ 34] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_OFFSET); + addr_hit[ 35] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_OFFSET); + addr_hit[ 36] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_OFFSET); + addr_hit[ 37] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_OFFSET); + addr_hit[ 38] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_OFFSET); + addr_hit[ 39] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_OFFSET); + addr_hit[ 40] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_OFFSET); + addr_hit[ 41] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_OFFSET); + addr_hit[ 42] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_OFFSET); + addr_hit[ 43] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_OFFSET); + addr_hit[ 44] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_OFFSET); + addr_hit[ 45] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_OFFSET); + addr_hit[ 46] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_OFFSET); + addr_hit[ 47] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_OFFSET); + addr_hit[ 48] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_OFFSET); + addr_hit[ 49] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_OFFSET); + addr_hit[ 50] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_OFFSET); + addr_hit[ 51] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_OFFSET); + addr_hit[ 52] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_OFFSET); + addr_hit[ 53] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_OFFSET); + addr_hit[ 54] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_OFFSET); + addr_hit[ 55] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_OFFSET); + addr_hit[ 56] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_OFFSET); + addr_hit[ 57] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_OFFSET); + addr_hit[ 58] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_OFFSET); + addr_hit[ 59] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_OFFSET); + addr_hit[ 60] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_OFFSET); + addr_hit[ 61] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_OFFSET); + addr_hit[ 62] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_OFFSET); + addr_hit[ 63] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_OFFSET); + addr_hit[ 64] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_OFFSET); + addr_hit[ 65] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_OFFSET); + addr_hit[ 66] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_OFFSET); + addr_hit[ 67] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_OFFSET); + addr_hit[ 68] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_OFFSET); + addr_hit[ 69] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_OFFSET); + addr_hit[ 70] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_OFFSET); + addr_hit[ 71] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_OFFSET); + addr_hit[ 72] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_OFFSET); + addr_hit[ 73] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_OFFSET); + addr_hit[ 74] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_OFFSET); + addr_hit[ 75] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_OFFSET); + addr_hit[ 76] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_OFFSET); + addr_hit[ 77] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_OFFSET); + addr_hit[ 78] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_OFFSET); + addr_hit[ 79] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_OFFSET); + addr_hit[ 80] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OFFSET); + addr_hit[ 81] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_64_OFFSET); + addr_hit[ 82] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_65_OFFSET); + addr_hit[ 83] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_66_OFFSET); + addr_hit[ 84] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_67_OFFSET); + addr_hit[ 85] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_68_OFFSET); + addr_hit[ 86] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_69_OFFSET); + addr_hit[ 87] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_70_OFFSET); + addr_hit[ 88] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_71_OFFSET); + addr_hit[ 89] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_72_OFFSET); + addr_hit[ 90] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_73_OFFSET); + addr_hit[ 91] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_74_OFFSET); + addr_hit[ 92] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_75_OFFSET); + addr_hit[ 93] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_76_OFFSET); + addr_hit[ 94] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_77_OFFSET); + addr_hit[ 95] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_78_OFFSET); + addr_hit[ 96] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_79_OFFSET); + addr_hit[ 97] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_80_OFFSET); + addr_hit[ 98] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_81_OFFSET); + addr_hit[ 99] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_82_OFFSET); + addr_hit[ 100] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_83_OFFSET); + addr_hit[ 101] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_84_OFFSET); + addr_hit[ 102] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_85_OFFSET); + addr_hit[ 103] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_86_OFFSET); + addr_hit[ 104] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_87_OFFSET); + addr_hit[ 105] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_88_OFFSET); + addr_hit[ 106] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_89_OFFSET); + addr_hit[ 107] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_90_OFFSET); + addr_hit[ 108] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_91_OFFSET); + addr_hit[ 109] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_92_OFFSET); + addr_hit[ 110] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_93_OFFSET); + addr_hit[ 111] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_94_OFFSET); + addr_hit[ 112] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_95_OFFSET); + addr_hit[ 113] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_96_OFFSET); + addr_hit[ 114] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_97_OFFSET); + addr_hit[ 115] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_98_OFFSET); + addr_hit[ 116] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_99_OFFSET); + addr_hit[ 117] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_100_OFFSET); + addr_hit[ 118] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_101_OFFSET); + addr_hit[ 119] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_102_OFFSET); + addr_hit[ 120] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_103_OFFSET); + addr_hit[ 121] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_104_OFFSET); + addr_hit[ 122] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_105_OFFSET); + addr_hit[ 123] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_106_OFFSET); + addr_hit[ 124] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_107_OFFSET); + addr_hit[ 125] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_108_OFFSET); + addr_hit[ 126] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_109_OFFSET); + addr_hit[ 127] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_110_OFFSET); + addr_hit[ 128] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_111_OFFSET); + addr_hit[ 129] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_112_OFFSET); + addr_hit[ 130] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_113_OFFSET); + addr_hit[ 131] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_114_OFFSET); + addr_hit[ 132] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_115_OFFSET); + addr_hit[ 133] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_116_OFFSET); + addr_hit[ 134] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_117_OFFSET); + addr_hit[ 135] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_118_OFFSET); + addr_hit[ 136] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_119_OFFSET); + addr_hit[ 137] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_120_OFFSET); + addr_hit[ 138] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_121_OFFSET); + addr_hit[ 139] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_122_OFFSET); + addr_hit[ 140] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_123_OFFSET); + addr_hit[ 141] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_124_OFFSET); + addr_hit[ 142] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_125_OFFSET); + addr_hit[ 143] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_126_OFFSET); + addr_hit[ 144] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_127_OFFSET); + addr_hit[ 145] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_128_OFFSET); + addr_hit[ 146] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_129_OFFSET); + addr_hit[ 147] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_130_OFFSET); + addr_hit[ 148] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_131_OFFSET); + addr_hit[ 149] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_132_OFFSET); + addr_hit[ 150] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_133_OFFSET); + addr_hit[ 151] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_134_OFFSET); + addr_hit[ 152] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_135_OFFSET); + addr_hit[ 153] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_136_OFFSET); + addr_hit[ 154] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_137_OFFSET); + addr_hit[ 155] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_138_OFFSET); + addr_hit[ 156] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_139_OFFSET); + addr_hit[ 157] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_140_OFFSET); + addr_hit[ 158] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_141_OFFSET); + addr_hit[ 159] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_142_OFFSET); + addr_hit[ 160] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_143_OFFSET); + addr_hit[ 161] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_144_OFFSET); + addr_hit[ 162] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_145_OFFSET); + addr_hit[ 163] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_146_OFFSET); + addr_hit[ 164] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_147_OFFSET); + addr_hit[ 165] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_148_OFFSET); + addr_hit[ 166] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_149_OFFSET); + addr_hit[ 167] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_150_OFFSET); + addr_hit[ 168] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_151_OFFSET); + addr_hit[ 169] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_152_OFFSET); + addr_hit[ 170] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_153_OFFSET); + addr_hit[ 171] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_154_OFFSET); + addr_hit[ 172] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_155_OFFSET); + addr_hit[ 173] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_156_OFFSET); + addr_hit[ 174] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_157_OFFSET); + addr_hit[ 175] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_158_OFFSET); + addr_hit[ 176] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_159_OFFSET); + addr_hit[ 177] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_160_OFFSET); + addr_hit[ 178] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_161_OFFSET); + addr_hit[ 179] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_162_OFFSET); + addr_hit[ 180] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_163_OFFSET); + addr_hit[ 181] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_164_OFFSET); + addr_hit[ 182] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_165_OFFSET); + addr_hit[ 183] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_166_OFFSET); + addr_hit[ 184] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_167_OFFSET); + addr_hit[ 185] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_168_OFFSET); + addr_hit[ 186] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_169_OFFSET); + addr_hit[ 187] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_170_OFFSET); + addr_hit[ 188] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_171_OFFSET); + addr_hit[ 189] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_172_OFFSET); + addr_hit[ 190] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_173_OFFSET); + addr_hit[ 191] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_174_OFFSET); + addr_hit[ 192] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_175_OFFSET); + addr_hit[ 193] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_176_OFFSET); + addr_hit[ 194] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_177_OFFSET); + addr_hit[ 195] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_178_OFFSET); + addr_hit[ 196] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_179_OFFSET); + addr_hit[ 197] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_180_OFFSET); + addr_hit[ 198] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_181_OFFSET); + addr_hit[ 199] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_182_OFFSET); + addr_hit[ 200] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_183_OFFSET); + addr_hit[ 201] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_184_OFFSET); + addr_hit[ 202] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_185_OFFSET); + addr_hit[ 203] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_186_OFFSET); + addr_hit[ 204] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_187_OFFSET); + addr_hit[ 205] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_188_OFFSET); + addr_hit[ 206] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_189_OFFSET); + addr_hit[ 207] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_190_OFFSET); + addr_hit[ 208] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_191_OFFSET); + addr_hit[ 209] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_192_OFFSET); + addr_hit[ 210] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_193_OFFSET); + addr_hit[ 211] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_194_OFFSET); + addr_hit[ 212] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_195_OFFSET); + addr_hit[ 213] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_196_OFFSET); + addr_hit[ 214] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_197_OFFSET); + addr_hit[ 215] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_198_OFFSET); + addr_hit[ 216] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_199_OFFSET); + addr_hit[ 217] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_200_OFFSET); + addr_hit[ 218] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_201_OFFSET); + addr_hit[ 219] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_202_OFFSET); + addr_hit[ 220] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_203_OFFSET); + addr_hit[ 221] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_204_OFFSET); + addr_hit[ 222] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_205_OFFSET); + addr_hit[ 223] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_206_OFFSET); + addr_hit[ 224] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_207_OFFSET); + addr_hit[ 225] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_208_OFFSET); + addr_hit[ 226] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_209_OFFSET); + addr_hit[ 227] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_210_OFFSET); + addr_hit[ 228] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_211_OFFSET); + addr_hit[ 229] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_212_OFFSET); + addr_hit[ 230] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_213_OFFSET); + addr_hit[ 231] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_214_OFFSET); + addr_hit[ 232] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_215_OFFSET); + addr_hit[ 233] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_216_OFFSET); + addr_hit[ 234] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_217_OFFSET); + addr_hit[ 235] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_218_OFFSET); + addr_hit[ 236] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_219_OFFSET); + addr_hit[ 237] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_220_OFFSET); + addr_hit[ 238] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_221_OFFSET); + addr_hit[ 239] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_222_OFFSET); + addr_hit[ 240] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_223_OFFSET); + addr_hit[ 241] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_224_OFFSET); + addr_hit[ 242] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_225_OFFSET); + addr_hit[ 243] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_226_OFFSET); + addr_hit[ 244] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_227_OFFSET); + addr_hit[ 245] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_228_OFFSET); + addr_hit[ 246] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_229_OFFSET); + addr_hit[ 247] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_230_OFFSET); + addr_hit[ 248] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_231_OFFSET); + addr_hit[ 249] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_232_OFFSET); + addr_hit[ 250] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_233_OFFSET); + addr_hit[ 251] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_234_OFFSET); + addr_hit[ 252] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_235_OFFSET); + addr_hit[ 253] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_236_OFFSET); + addr_hit[ 254] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_237_OFFSET); + addr_hit[ 255] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_238_OFFSET); + addr_hit[ 256] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_239_OFFSET); + addr_hit[ 257] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_240_OFFSET); + addr_hit[ 258] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_241_OFFSET); + addr_hit[ 259] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_242_OFFSET); + addr_hit[ 260] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_243_OFFSET); + addr_hit[ 261] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_244_OFFSET); + addr_hit[ 262] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_245_OFFSET); + addr_hit[ 263] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_246_OFFSET); + addr_hit[ 264] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_247_OFFSET); + addr_hit[ 265] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_248_OFFSET); + addr_hit[ 266] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_249_OFFSET); + addr_hit[ 267] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_250_OFFSET); + addr_hit[ 268] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_251_OFFSET); + addr_hit[ 269] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_252_OFFSET); + addr_hit[ 270] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_253_OFFSET); + addr_hit[ 271] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_254_OFFSET); + addr_hit[ 272] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_255_OFFSET); + addr_hit[ 273] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0_OFFSET); + addr_hit[ 274] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1_OFFSET); + addr_hit[ 275] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2_OFFSET); + addr_hit[ 276] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3_OFFSET); + addr_hit[ 277] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4_OFFSET); + addr_hit[ 278] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5_OFFSET); + addr_hit[ 279] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6_OFFSET); + addr_hit[ 280] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7_OFFSET); + addr_hit[ 281] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8_OFFSET); + addr_hit[ 282] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9_OFFSET); + addr_hit[ 283] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10_OFFSET); + addr_hit[ 284] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11_OFFSET); + addr_hit[ 285] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12_OFFSET); + addr_hit[ 286] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13_OFFSET); + addr_hit[ 287] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14_OFFSET); + addr_hit[ 288] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15_OFFSET); + addr_hit[ 289] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16_OFFSET); + addr_hit[ 290] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17_OFFSET); + addr_hit[ 291] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18_OFFSET); + addr_hit[ 292] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19_OFFSET); + addr_hit[ 293] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20_OFFSET); + addr_hit[ 294] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21_OFFSET); + addr_hit[ 295] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22_OFFSET); + addr_hit[ 296] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23_OFFSET); + addr_hit[ 297] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24_OFFSET); + addr_hit[ 298] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25_OFFSET); + addr_hit[ 299] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26_OFFSET); + addr_hit[ 300] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27_OFFSET); + addr_hit[ 301] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28_OFFSET); + addr_hit[ 302] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29_OFFSET); + addr_hit[ 303] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30_OFFSET); + addr_hit[ 304] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31_OFFSET); + addr_hit[ 305] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32_OFFSET); + addr_hit[ 306] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33_OFFSET); + addr_hit[ 307] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34_OFFSET); + addr_hit[ 308] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35_OFFSET); + addr_hit[ 309] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36_OFFSET); + addr_hit[ 310] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37_OFFSET); + addr_hit[ 311] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38_OFFSET); + addr_hit[ 312] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39_OFFSET); + addr_hit[ 313] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40_OFFSET); + addr_hit[ 314] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41_OFFSET); + addr_hit[ 315] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42_OFFSET); + addr_hit[ 316] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43_OFFSET); + addr_hit[ 317] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44_OFFSET); + addr_hit[ 318] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45_OFFSET); + addr_hit[ 319] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46_OFFSET); + addr_hit[ 320] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47_OFFSET); + addr_hit[ 321] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48_OFFSET); + addr_hit[ 322] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49_OFFSET); + addr_hit[ 323] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50_OFFSET); + addr_hit[ 324] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51_OFFSET); + addr_hit[ 325] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52_OFFSET); + addr_hit[ 326] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53_OFFSET); + addr_hit[ 327] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54_OFFSET); + addr_hit[ 328] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55_OFFSET); + addr_hit[ 329] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56_OFFSET); + addr_hit[ 330] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57_OFFSET); + addr_hit[ 331] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58_OFFSET); + addr_hit[ 332] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59_OFFSET); + addr_hit[ 333] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60_OFFSET); + addr_hit[ 334] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61_OFFSET); + addr_hit[ 335] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62_OFFSET); + addr_hit[ 336] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63_OFFSET); + addr_hit[ 337] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_64_OFFSET); + addr_hit[ 338] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_65_OFFSET); + addr_hit[ 339] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_66_OFFSET); + addr_hit[ 340] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_67_OFFSET); + addr_hit[ 341] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_68_OFFSET); + addr_hit[ 342] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_69_OFFSET); + addr_hit[ 343] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_70_OFFSET); + addr_hit[ 344] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_71_OFFSET); + addr_hit[ 345] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_72_OFFSET); + addr_hit[ 346] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_73_OFFSET); + addr_hit[ 347] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_74_OFFSET); + addr_hit[ 348] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_75_OFFSET); + addr_hit[ 349] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_76_OFFSET); + addr_hit[ 350] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_77_OFFSET); + addr_hit[ 351] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_78_OFFSET); + addr_hit[ 352] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_79_OFFSET); + addr_hit[ 353] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_80_OFFSET); + addr_hit[ 354] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_81_OFFSET); + addr_hit[ 355] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_82_OFFSET); + addr_hit[ 356] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_83_OFFSET); + addr_hit[ 357] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_84_OFFSET); + addr_hit[ 358] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_85_OFFSET); + addr_hit[ 359] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_86_OFFSET); + addr_hit[ 360] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_87_OFFSET); + addr_hit[ 361] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_88_OFFSET); + addr_hit[ 362] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_89_OFFSET); + addr_hit[ 363] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_90_OFFSET); + addr_hit[ 364] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_91_OFFSET); + addr_hit[ 365] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_92_OFFSET); + addr_hit[ 366] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_93_OFFSET); + addr_hit[ 367] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_94_OFFSET); + addr_hit[ 368] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_95_OFFSET); + addr_hit[ 369] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_96_OFFSET); + addr_hit[ 370] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_97_OFFSET); + addr_hit[ 371] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_98_OFFSET); + addr_hit[ 372] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_99_OFFSET); + addr_hit[ 373] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_100_OFFSET); + addr_hit[ 374] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_101_OFFSET); + addr_hit[ 375] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_102_OFFSET); + addr_hit[ 376] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_103_OFFSET); + addr_hit[ 377] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_104_OFFSET); + addr_hit[ 378] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_105_OFFSET); + addr_hit[ 379] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_106_OFFSET); + addr_hit[ 380] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_107_OFFSET); + addr_hit[ 381] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_108_OFFSET); + addr_hit[ 382] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_109_OFFSET); + addr_hit[ 383] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_110_OFFSET); + addr_hit[ 384] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_111_OFFSET); + addr_hit[ 385] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_112_OFFSET); + addr_hit[ 386] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_113_OFFSET); + addr_hit[ 387] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_114_OFFSET); + addr_hit[ 388] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_115_OFFSET); + addr_hit[ 389] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_116_OFFSET); + addr_hit[ 390] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_117_OFFSET); + addr_hit[ 391] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_118_OFFSET); + addr_hit[ 392] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_119_OFFSET); + addr_hit[ 393] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_120_OFFSET); + addr_hit[ 394] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_121_OFFSET); + addr_hit[ 395] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_122_OFFSET); + addr_hit[ 396] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_123_OFFSET); + addr_hit[ 397] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_124_OFFSET); + addr_hit[ 398] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_125_OFFSET); + addr_hit[ 399] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_126_OFFSET); + addr_hit[ 400] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_127_OFFSET); + addr_hit[ 401] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_128_OFFSET); + addr_hit[ 402] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_129_OFFSET); + addr_hit[ 403] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_130_OFFSET); + addr_hit[ 404] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_131_OFFSET); + addr_hit[ 405] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_132_OFFSET); + addr_hit[ 406] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_133_OFFSET); + addr_hit[ 407] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_134_OFFSET); + addr_hit[ 408] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_135_OFFSET); + addr_hit[ 409] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_136_OFFSET); + addr_hit[ 410] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_137_OFFSET); + addr_hit[ 411] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_138_OFFSET); + addr_hit[ 412] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_139_OFFSET); + addr_hit[ 413] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_140_OFFSET); + addr_hit[ 414] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_141_OFFSET); + addr_hit[ 415] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_142_OFFSET); + addr_hit[ 416] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_143_OFFSET); + addr_hit[ 417] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_144_OFFSET); + addr_hit[ 418] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_145_OFFSET); + addr_hit[ 419] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_146_OFFSET); + addr_hit[ 420] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_147_OFFSET); + addr_hit[ 421] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_148_OFFSET); + addr_hit[ 422] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_149_OFFSET); + addr_hit[ 423] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_150_OFFSET); + addr_hit[ 424] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_151_OFFSET); + addr_hit[ 425] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_152_OFFSET); + addr_hit[ 426] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_153_OFFSET); + addr_hit[ 427] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_154_OFFSET); + addr_hit[ 428] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_155_OFFSET); + addr_hit[ 429] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_156_OFFSET); + addr_hit[ 430] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_157_OFFSET); + addr_hit[ 431] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_158_OFFSET); + addr_hit[ 432] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_159_OFFSET); + addr_hit[ 433] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_160_OFFSET); + addr_hit[ 434] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_161_OFFSET); + addr_hit[ 435] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_162_OFFSET); + addr_hit[ 436] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_163_OFFSET); + addr_hit[ 437] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_164_OFFSET); + addr_hit[ 438] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_165_OFFSET); + addr_hit[ 439] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_166_OFFSET); + addr_hit[ 440] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_167_OFFSET); + addr_hit[ 441] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_168_OFFSET); + addr_hit[ 442] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_169_OFFSET); + addr_hit[ 443] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_170_OFFSET); + addr_hit[ 444] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_171_OFFSET); + addr_hit[ 445] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_172_OFFSET); + addr_hit[ 446] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_173_OFFSET); + addr_hit[ 447] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_174_OFFSET); + addr_hit[ 448] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_175_OFFSET); + addr_hit[ 449] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_176_OFFSET); + addr_hit[ 450] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_177_OFFSET); + addr_hit[ 451] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_178_OFFSET); + addr_hit[ 452] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_179_OFFSET); + addr_hit[ 453] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_180_OFFSET); + addr_hit[ 454] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_181_OFFSET); + addr_hit[ 455] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_182_OFFSET); + addr_hit[ 456] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_183_OFFSET); + addr_hit[ 457] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_184_OFFSET); + addr_hit[ 458] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_185_OFFSET); + addr_hit[ 459] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_186_OFFSET); + addr_hit[ 460] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_187_OFFSET); + addr_hit[ 461] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_188_OFFSET); + addr_hit[ 462] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_189_OFFSET); + addr_hit[ 463] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_190_OFFSET); + addr_hit[ 464] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_191_OFFSET); + addr_hit[ 465] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_192_OFFSET); + addr_hit[ 466] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_193_OFFSET); + addr_hit[ 467] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_194_OFFSET); + addr_hit[ 468] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_195_OFFSET); + addr_hit[ 469] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_196_OFFSET); + addr_hit[ 470] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_197_OFFSET); + addr_hit[ 471] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_198_OFFSET); + addr_hit[ 472] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_199_OFFSET); + addr_hit[ 473] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_200_OFFSET); + addr_hit[ 474] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_201_OFFSET); + addr_hit[ 475] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_202_OFFSET); + addr_hit[ 476] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_203_OFFSET); + addr_hit[ 477] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_204_OFFSET); + addr_hit[ 478] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_205_OFFSET); + addr_hit[ 479] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_206_OFFSET); + addr_hit[ 480] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_207_OFFSET); + addr_hit[ 481] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_208_OFFSET); + addr_hit[ 482] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_209_OFFSET); + addr_hit[ 483] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_210_OFFSET); + addr_hit[ 484] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_211_OFFSET); + addr_hit[ 485] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_212_OFFSET); + addr_hit[ 486] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_213_OFFSET); + addr_hit[ 487] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_214_OFFSET); + addr_hit[ 488] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_215_OFFSET); + addr_hit[ 489] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_216_OFFSET); + addr_hit[ 490] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_217_OFFSET); + addr_hit[ 491] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_218_OFFSET); + addr_hit[ 492] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_219_OFFSET); + addr_hit[ 493] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_220_OFFSET); + addr_hit[ 494] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_221_OFFSET); + addr_hit[ 495] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_222_OFFSET); + addr_hit[ 496] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_223_OFFSET); + addr_hit[ 497] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_224_OFFSET); + addr_hit[ 498] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_225_OFFSET); + addr_hit[ 499] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_226_OFFSET); + addr_hit[ 500] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_227_OFFSET); + addr_hit[ 501] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_228_OFFSET); + addr_hit[ 502] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_229_OFFSET); + addr_hit[ 503] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_230_OFFSET); + addr_hit[ 504] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_231_OFFSET); + addr_hit[ 505] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_232_OFFSET); + addr_hit[ 506] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_233_OFFSET); + addr_hit[ 507] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_234_OFFSET); + addr_hit[ 508] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_235_OFFSET); + addr_hit[ 509] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_236_OFFSET); + addr_hit[ 510] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_237_OFFSET); + addr_hit[ 511] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_238_OFFSET); + addr_hit[ 512] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_239_OFFSET); + addr_hit[ 513] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_240_OFFSET); + addr_hit[ 514] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_241_OFFSET); + addr_hit[ 515] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_242_OFFSET); + addr_hit[ 516] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_243_OFFSET); + addr_hit[ 517] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_244_OFFSET); + addr_hit[ 518] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_245_OFFSET); + addr_hit[ 519] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_246_OFFSET); + addr_hit[ 520] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_247_OFFSET); + addr_hit[ 521] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_248_OFFSET); + addr_hit[ 522] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_249_OFFSET); + addr_hit[ 523] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_250_OFFSET); + addr_hit[ 524] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_251_OFFSET); + addr_hit[ 525] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_252_OFFSET); + addr_hit[ 526] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_253_OFFSET); + addr_hit[ 527] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_254_OFFSET); + addr_hit[ 528] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_255_OFFSET); + addr_hit[ 529] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_OFFSET); + addr_hit[ 530] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_OFFSET); + addr_hit[ 531] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_OFFSET); + addr_hit[ 532] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_OFFSET); + addr_hit[ 533] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_OFFSET); + addr_hit[ 534] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_OFFSET); + addr_hit[ 535] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_OFFSET); + addr_hit[ 536] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_OFFSET); + addr_hit[ 537] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_OFFSET); + addr_hit[ 538] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_OFFSET); + addr_hit[ 539] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_OFFSET); + addr_hit[ 540] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_OFFSET); + addr_hit[ 541] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_OFFSET); + addr_hit[ 542] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_OFFSET); + addr_hit[ 543] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_OFFSET); + addr_hit[ 544] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_OFFSET); + addr_hit[ 545] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_OFFSET); + addr_hit[ 546] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_OFFSET); + addr_hit[ 547] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_OFFSET); + addr_hit[ 548] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_OFFSET); + addr_hit[ 549] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_OFFSET); + addr_hit[ 550] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_OFFSET); + addr_hit[ 551] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_OFFSET); + addr_hit[ 552] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_OFFSET); + addr_hit[ 553] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_OFFSET); + addr_hit[ 554] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_OFFSET); + addr_hit[ 555] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_OFFSET); + addr_hit[ 556] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_OFFSET); + addr_hit[ 557] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_OFFSET); + addr_hit[ 558] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_OFFSET); + addr_hit[ 559] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_OFFSET); + addr_hit[ 560] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_OFFSET); + addr_hit[ 561] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_OFFSET); + addr_hit[ 562] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_OFFSET); + addr_hit[ 563] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_OFFSET); + addr_hit[ 564] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_OFFSET); + addr_hit[ 565] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_OFFSET); + addr_hit[ 566] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_OFFSET); + addr_hit[ 567] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_OFFSET); + addr_hit[ 568] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_OFFSET); + addr_hit[ 569] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_OFFSET); + addr_hit[ 570] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_OFFSET); + addr_hit[ 571] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_OFFSET); + addr_hit[ 572] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_OFFSET); + addr_hit[ 573] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_OFFSET); + addr_hit[ 574] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_OFFSET); + addr_hit[ 575] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_OFFSET); + addr_hit[ 576] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_OFFSET); + addr_hit[ 577] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_OFFSET); + addr_hit[ 578] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_OFFSET); + addr_hit[ 579] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_OFFSET); + addr_hit[ 580] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_OFFSET); + addr_hit[ 581] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_OFFSET); + addr_hit[ 582] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_OFFSET); + addr_hit[ 583] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_OFFSET); + addr_hit[ 584] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_OFFSET); + addr_hit[ 585] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_OFFSET); + addr_hit[ 586] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_OFFSET); + addr_hit[ 587] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_OFFSET); + addr_hit[ 588] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_OFFSET); + addr_hit[ 589] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_OFFSET); + addr_hit[ 590] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_OFFSET); + addr_hit[ 591] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_OFFSET); + addr_hit[ 592] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_OFFSET); + addr_hit[ 593] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_64_OFFSET); + addr_hit[ 594] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_65_OFFSET); + addr_hit[ 595] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_66_OFFSET); + addr_hit[ 596] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_67_OFFSET); + addr_hit[ 597] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_68_OFFSET); + addr_hit[ 598] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_69_OFFSET); + addr_hit[ 599] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_70_OFFSET); + addr_hit[ 600] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_71_OFFSET); + addr_hit[ 601] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_72_OFFSET); + addr_hit[ 602] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_73_OFFSET); + addr_hit[ 603] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_74_OFFSET); + addr_hit[ 604] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_75_OFFSET); + addr_hit[ 605] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_76_OFFSET); + addr_hit[ 606] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_77_OFFSET); + addr_hit[ 607] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_78_OFFSET); + addr_hit[ 608] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_79_OFFSET); + addr_hit[ 609] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_80_OFFSET); + addr_hit[ 610] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_81_OFFSET); + addr_hit[ 611] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_82_OFFSET); + addr_hit[ 612] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_83_OFFSET); + addr_hit[ 613] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_84_OFFSET); + addr_hit[ 614] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_85_OFFSET); + addr_hit[ 615] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_86_OFFSET); + addr_hit[ 616] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_87_OFFSET); + addr_hit[ 617] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_88_OFFSET); + addr_hit[ 618] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_89_OFFSET); + addr_hit[ 619] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_90_OFFSET); + addr_hit[ 620] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_91_OFFSET); + addr_hit[ 621] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_92_OFFSET); + addr_hit[ 622] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_93_OFFSET); + addr_hit[ 623] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_94_OFFSET); + addr_hit[ 624] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_95_OFFSET); + addr_hit[ 625] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_96_OFFSET); + addr_hit[ 626] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_97_OFFSET); + addr_hit[ 627] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_98_OFFSET); + addr_hit[ 628] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_99_OFFSET); + addr_hit[ 629] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_100_OFFSET); + addr_hit[ 630] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_101_OFFSET); + addr_hit[ 631] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_102_OFFSET); + addr_hit[ 632] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_103_OFFSET); + addr_hit[ 633] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_104_OFFSET); + addr_hit[ 634] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_105_OFFSET); + addr_hit[ 635] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_106_OFFSET); + addr_hit[ 636] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_107_OFFSET); + addr_hit[ 637] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_108_OFFSET); + addr_hit[ 638] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_109_OFFSET); + addr_hit[ 639] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_110_OFFSET); + addr_hit[ 640] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_111_OFFSET); + addr_hit[ 641] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_112_OFFSET); + addr_hit[ 642] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_113_OFFSET); + addr_hit[ 643] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_114_OFFSET); + addr_hit[ 644] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_115_OFFSET); + addr_hit[ 645] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_116_OFFSET); + addr_hit[ 646] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_117_OFFSET); + addr_hit[ 647] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_118_OFFSET); + addr_hit[ 648] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_119_OFFSET); + addr_hit[ 649] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_120_OFFSET); + addr_hit[ 650] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_121_OFFSET); + addr_hit[ 651] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_122_OFFSET); + addr_hit[ 652] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_123_OFFSET); + addr_hit[ 653] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_124_OFFSET); + addr_hit[ 654] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_125_OFFSET); + addr_hit[ 655] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_126_OFFSET); + addr_hit[ 656] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_127_OFFSET); + addr_hit[ 657] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_128_OFFSET); + addr_hit[ 658] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_129_OFFSET); + addr_hit[ 659] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_130_OFFSET); + addr_hit[ 660] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_131_OFFSET); + addr_hit[ 661] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_132_OFFSET); + addr_hit[ 662] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_133_OFFSET); + addr_hit[ 663] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_134_OFFSET); + addr_hit[ 664] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_135_OFFSET); + addr_hit[ 665] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_136_OFFSET); + addr_hit[ 666] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_137_OFFSET); + addr_hit[ 667] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_138_OFFSET); + addr_hit[ 668] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_139_OFFSET); + addr_hit[ 669] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_140_OFFSET); + addr_hit[ 670] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_141_OFFSET); + addr_hit[ 671] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_142_OFFSET); + addr_hit[ 672] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_143_OFFSET); + addr_hit[ 673] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_144_OFFSET); + addr_hit[ 674] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_145_OFFSET); + addr_hit[ 675] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_146_OFFSET); + addr_hit[ 676] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_147_OFFSET); + addr_hit[ 677] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_148_OFFSET); + addr_hit[ 678] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_149_OFFSET); + addr_hit[ 679] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_150_OFFSET); + addr_hit[ 680] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_151_OFFSET); + addr_hit[ 681] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_152_OFFSET); + addr_hit[ 682] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_153_OFFSET); + addr_hit[ 683] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_154_OFFSET); + addr_hit[ 684] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_155_OFFSET); + addr_hit[ 685] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_156_OFFSET); + addr_hit[ 686] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_157_OFFSET); + addr_hit[ 687] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_158_OFFSET); + addr_hit[ 688] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_159_OFFSET); + addr_hit[ 689] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_160_OFFSET); + addr_hit[ 690] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_161_OFFSET); + addr_hit[ 691] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_162_OFFSET); + addr_hit[ 692] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_163_OFFSET); + addr_hit[ 693] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_164_OFFSET); + addr_hit[ 694] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_165_OFFSET); + addr_hit[ 695] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_166_OFFSET); + addr_hit[ 696] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_167_OFFSET); + addr_hit[ 697] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_168_OFFSET); + addr_hit[ 698] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_169_OFFSET); + addr_hit[ 699] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_170_OFFSET); + addr_hit[ 700] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_171_OFFSET); + addr_hit[ 701] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_172_OFFSET); + addr_hit[ 702] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_173_OFFSET); + addr_hit[ 703] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_174_OFFSET); + addr_hit[ 704] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_175_OFFSET); + addr_hit[ 705] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_176_OFFSET); + addr_hit[ 706] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_177_OFFSET); + addr_hit[ 707] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_178_OFFSET); + addr_hit[ 708] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_179_OFFSET); + addr_hit[ 709] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_180_OFFSET); + addr_hit[ 710] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_181_OFFSET); + addr_hit[ 711] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_182_OFFSET); + addr_hit[ 712] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_183_OFFSET); + addr_hit[ 713] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_184_OFFSET); + addr_hit[ 714] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_185_OFFSET); + addr_hit[ 715] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_186_OFFSET); + addr_hit[ 716] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_187_OFFSET); + addr_hit[ 717] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_188_OFFSET); + addr_hit[ 718] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_189_OFFSET); + addr_hit[ 719] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_190_OFFSET); + addr_hit[ 720] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_191_OFFSET); + addr_hit[ 721] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_192_OFFSET); + addr_hit[ 722] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_193_OFFSET); + addr_hit[ 723] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_194_OFFSET); + addr_hit[ 724] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_195_OFFSET); + addr_hit[ 725] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_196_OFFSET); + addr_hit[ 726] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_197_OFFSET); + addr_hit[ 727] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_198_OFFSET); + addr_hit[ 728] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_199_OFFSET); + addr_hit[ 729] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_200_OFFSET); + addr_hit[ 730] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_201_OFFSET); + addr_hit[ 731] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_202_OFFSET); + addr_hit[ 732] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_203_OFFSET); + addr_hit[ 733] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_204_OFFSET); + addr_hit[ 734] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_205_OFFSET); + addr_hit[ 735] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_206_OFFSET); + addr_hit[ 736] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_207_OFFSET); + addr_hit[ 737] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_208_OFFSET); + addr_hit[ 738] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_209_OFFSET); + addr_hit[ 739] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_210_OFFSET); + addr_hit[ 740] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_211_OFFSET); + addr_hit[ 741] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_212_OFFSET); + addr_hit[ 742] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_213_OFFSET); + addr_hit[ 743] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_214_OFFSET); + addr_hit[ 744] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_215_OFFSET); + addr_hit[ 745] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_216_OFFSET); + addr_hit[ 746] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_217_OFFSET); + addr_hit[ 747] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_218_OFFSET); + addr_hit[ 748] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_219_OFFSET); + addr_hit[ 749] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_220_OFFSET); + addr_hit[ 750] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_221_OFFSET); + addr_hit[ 751] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_222_OFFSET); + addr_hit[ 752] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_223_OFFSET); + addr_hit[ 753] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_224_OFFSET); + addr_hit[ 754] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_225_OFFSET); + addr_hit[ 755] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_226_OFFSET); + addr_hit[ 756] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_227_OFFSET); + addr_hit[ 757] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_228_OFFSET); + addr_hit[ 758] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_229_OFFSET); + addr_hit[ 759] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_230_OFFSET); + addr_hit[ 760] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_231_OFFSET); + addr_hit[ 761] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_232_OFFSET); + addr_hit[ 762] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_233_OFFSET); + addr_hit[ 763] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_234_OFFSET); + addr_hit[ 764] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_235_OFFSET); + addr_hit[ 765] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_236_OFFSET); + addr_hit[ 766] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_237_OFFSET); + addr_hit[ 767] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_238_OFFSET); + addr_hit[ 768] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_239_OFFSET); + addr_hit[ 769] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_240_OFFSET); + addr_hit[ 770] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_241_OFFSET); + addr_hit[ 771] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_242_OFFSET); + addr_hit[ 772] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_243_OFFSET); + addr_hit[ 773] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_244_OFFSET); + addr_hit[ 774] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_245_OFFSET); + addr_hit[ 775] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_246_OFFSET); + addr_hit[ 776] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_247_OFFSET); + addr_hit[ 777] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_248_OFFSET); + addr_hit[ 778] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_249_OFFSET); + addr_hit[ 779] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_250_OFFSET); + addr_hit[ 780] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_251_OFFSET); + addr_hit[ 781] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_252_OFFSET); + addr_hit[ 782] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_253_OFFSET); + addr_hit[ 783] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_254_OFFSET); + addr_hit[ 784] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_255_OFFSET); + addr_hit[ 785] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_OFFSET); + addr_hit[ 786] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_OFFSET); + addr_hit[ 787] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_OFFSET); + addr_hit[ 788] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_OFFSET); + addr_hit[ 789] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_OFFSET); + addr_hit[ 790] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_OFFSET); + addr_hit[ 791] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_OFFSET); + addr_hit[ 792] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_OFFSET); + addr_hit[ 793] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_OFFSET); + addr_hit[ 794] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_OFFSET); + addr_hit[ 795] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_OFFSET); + addr_hit[ 796] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_OFFSET); + addr_hit[ 797] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_OFFSET); + addr_hit[ 798] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_OFFSET); + addr_hit[ 799] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_OFFSET); + addr_hit[ 800] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_OFFSET); + addr_hit[ 801] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_OFFSET); + addr_hit[ 802] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_OFFSET); + addr_hit[ 803] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_OFFSET); + addr_hit[ 804] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_OFFSET); + addr_hit[ 805] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_OFFSET); + addr_hit[ 806] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_OFFSET); + addr_hit[ 807] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_OFFSET); + addr_hit[ 808] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_OFFSET); + addr_hit[ 809] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_OFFSET); + addr_hit[ 810] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_OFFSET); + addr_hit[ 811] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_OFFSET); + addr_hit[ 812] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_OFFSET); + addr_hit[ 813] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_OFFSET); + addr_hit[ 814] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_OFFSET); + addr_hit[ 815] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_OFFSET); + addr_hit[ 816] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_OFFSET); + addr_hit[ 817] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_OFFSET); + addr_hit[ 818] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_OFFSET); + addr_hit[ 819] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_OFFSET); + addr_hit[ 820] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_OFFSET); + addr_hit[ 821] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_OFFSET); + addr_hit[ 822] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_OFFSET); + addr_hit[ 823] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_OFFSET); + addr_hit[ 824] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_OFFSET); + addr_hit[ 825] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_OFFSET); + addr_hit[ 826] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_OFFSET); + addr_hit[ 827] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_OFFSET); + addr_hit[ 828] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_OFFSET); + addr_hit[ 829] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_OFFSET); + addr_hit[ 830] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_OFFSET); + addr_hit[ 831] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_OFFSET); + addr_hit[ 832] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_OFFSET); + addr_hit[ 833] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_OFFSET); + addr_hit[ 834] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_OFFSET); + addr_hit[ 835] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_OFFSET); + addr_hit[ 836] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_OFFSET); + addr_hit[ 837] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_OFFSET); + addr_hit[ 838] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_OFFSET); + addr_hit[ 839] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_OFFSET); + addr_hit[ 840] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_OFFSET); + addr_hit[ 841] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_OFFSET); + addr_hit[ 842] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_OFFSET); + addr_hit[ 843] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_OFFSET); + addr_hit[ 844] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_OFFSET); + addr_hit[ 845] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_OFFSET); + addr_hit[ 846] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_OFFSET); + addr_hit[ 847] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_OFFSET); + addr_hit[ 848] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_OFFSET); + addr_hit[ 849] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_64_OFFSET); + addr_hit[ 850] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_65_OFFSET); + addr_hit[ 851] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_66_OFFSET); + addr_hit[ 852] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_67_OFFSET); + addr_hit[ 853] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_68_OFFSET); + addr_hit[ 854] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_69_OFFSET); + addr_hit[ 855] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_70_OFFSET); + addr_hit[ 856] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_71_OFFSET); + addr_hit[ 857] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_72_OFFSET); + addr_hit[ 858] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_73_OFFSET); + addr_hit[ 859] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_74_OFFSET); + addr_hit[ 860] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_75_OFFSET); + addr_hit[ 861] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_76_OFFSET); + addr_hit[ 862] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_77_OFFSET); + addr_hit[ 863] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_78_OFFSET); + addr_hit[ 864] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_79_OFFSET); + addr_hit[ 865] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_80_OFFSET); + addr_hit[ 866] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_81_OFFSET); + addr_hit[ 867] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_82_OFFSET); + addr_hit[ 868] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_83_OFFSET); + addr_hit[ 869] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_84_OFFSET); + addr_hit[ 870] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_85_OFFSET); + addr_hit[ 871] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_86_OFFSET); + addr_hit[ 872] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_87_OFFSET); + addr_hit[ 873] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_88_OFFSET); + addr_hit[ 874] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_89_OFFSET); + addr_hit[ 875] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_90_OFFSET); + addr_hit[ 876] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_91_OFFSET); + addr_hit[ 877] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_92_OFFSET); + addr_hit[ 878] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_93_OFFSET); + addr_hit[ 879] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_94_OFFSET); + addr_hit[ 880] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_95_OFFSET); + addr_hit[ 881] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_96_OFFSET); + addr_hit[ 882] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_97_OFFSET); + addr_hit[ 883] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_98_OFFSET); + addr_hit[ 884] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_99_OFFSET); + addr_hit[ 885] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_100_OFFSET); + addr_hit[ 886] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_101_OFFSET); + addr_hit[ 887] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_102_OFFSET); + addr_hit[ 888] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_103_OFFSET); + addr_hit[ 889] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_104_OFFSET); + addr_hit[ 890] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_105_OFFSET); + addr_hit[ 891] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_106_OFFSET); + addr_hit[ 892] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_107_OFFSET); + addr_hit[ 893] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_108_OFFSET); + addr_hit[ 894] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_109_OFFSET); + addr_hit[ 895] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_110_OFFSET); + addr_hit[ 896] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_111_OFFSET); + addr_hit[ 897] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_112_OFFSET); + addr_hit[ 898] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_113_OFFSET); + addr_hit[ 899] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_114_OFFSET); + addr_hit[ 900] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_115_OFFSET); + addr_hit[ 901] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_116_OFFSET); + addr_hit[ 902] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_117_OFFSET); + addr_hit[ 903] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_118_OFFSET); + addr_hit[ 904] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_119_OFFSET); + addr_hit[ 905] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_120_OFFSET); + addr_hit[ 906] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_121_OFFSET); + addr_hit[ 907] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_122_OFFSET); + addr_hit[ 908] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_123_OFFSET); + addr_hit[ 909] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_124_OFFSET); + addr_hit[ 910] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_125_OFFSET); + addr_hit[ 911] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_126_OFFSET); + addr_hit[ 912] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_127_OFFSET); + addr_hit[ 913] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_128_OFFSET); + addr_hit[ 914] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_129_OFFSET); + addr_hit[ 915] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_130_OFFSET); + addr_hit[ 916] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_131_OFFSET); + addr_hit[ 917] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_132_OFFSET); + addr_hit[ 918] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_133_OFFSET); + addr_hit[ 919] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_134_OFFSET); + addr_hit[ 920] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_135_OFFSET); + addr_hit[ 921] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_136_OFFSET); + addr_hit[ 922] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_137_OFFSET); + addr_hit[ 923] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_138_OFFSET); + addr_hit[ 924] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_139_OFFSET); + addr_hit[ 925] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_140_OFFSET); + addr_hit[ 926] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_141_OFFSET); + addr_hit[ 927] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_142_OFFSET); + addr_hit[ 928] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_143_OFFSET); + addr_hit[ 929] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_144_OFFSET); + addr_hit[ 930] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_145_OFFSET); + addr_hit[ 931] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_146_OFFSET); + addr_hit[ 932] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_147_OFFSET); + addr_hit[ 933] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_148_OFFSET); + addr_hit[ 934] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_149_OFFSET); + addr_hit[ 935] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_150_OFFSET); + addr_hit[ 936] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_151_OFFSET); + addr_hit[ 937] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_152_OFFSET); + addr_hit[ 938] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_153_OFFSET); + addr_hit[ 939] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_154_OFFSET); + addr_hit[ 940] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_155_OFFSET); + addr_hit[ 941] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_156_OFFSET); + addr_hit[ 942] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_157_OFFSET); + addr_hit[ 943] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_158_OFFSET); + addr_hit[ 944] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_159_OFFSET); + addr_hit[ 945] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_160_OFFSET); + addr_hit[ 946] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_161_OFFSET); + addr_hit[ 947] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_162_OFFSET); + addr_hit[ 948] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_163_OFFSET); + addr_hit[ 949] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_164_OFFSET); + addr_hit[ 950] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_165_OFFSET); + addr_hit[ 951] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_166_OFFSET); + addr_hit[ 952] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_167_OFFSET); + addr_hit[ 953] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_168_OFFSET); + addr_hit[ 954] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_169_OFFSET); + addr_hit[ 955] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_170_OFFSET); + addr_hit[ 956] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_171_OFFSET); + addr_hit[ 957] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_172_OFFSET); + addr_hit[ 958] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_173_OFFSET); + addr_hit[ 959] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_174_OFFSET); + addr_hit[ 960] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_175_OFFSET); + addr_hit[ 961] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_176_OFFSET); + addr_hit[ 962] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_177_OFFSET); + addr_hit[ 963] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_178_OFFSET); + addr_hit[ 964] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_179_OFFSET); + addr_hit[ 965] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_180_OFFSET); + addr_hit[ 966] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_181_OFFSET); + addr_hit[ 967] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_182_OFFSET); + addr_hit[ 968] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_183_OFFSET); + addr_hit[ 969] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_184_OFFSET); + addr_hit[ 970] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_185_OFFSET); + addr_hit[ 971] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_186_OFFSET); + addr_hit[ 972] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_187_OFFSET); + addr_hit[ 973] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_188_OFFSET); + addr_hit[ 974] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_189_OFFSET); + addr_hit[ 975] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_190_OFFSET); + addr_hit[ 976] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_191_OFFSET); + addr_hit[ 977] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_192_OFFSET); + addr_hit[ 978] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_193_OFFSET); + addr_hit[ 979] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_194_OFFSET); + addr_hit[ 980] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_195_OFFSET); + addr_hit[ 981] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_196_OFFSET); + addr_hit[ 982] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_197_OFFSET); + addr_hit[ 983] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_198_OFFSET); + addr_hit[ 984] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_199_OFFSET); + addr_hit[ 985] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_200_OFFSET); + addr_hit[ 986] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_201_OFFSET); + addr_hit[ 987] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_202_OFFSET); + addr_hit[ 988] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_203_OFFSET); + addr_hit[ 989] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_204_OFFSET); + addr_hit[ 990] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_205_OFFSET); + addr_hit[ 991] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_206_OFFSET); + addr_hit[ 992] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_207_OFFSET); + addr_hit[ 993] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_208_OFFSET); + addr_hit[ 994] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_209_OFFSET); + addr_hit[ 995] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_210_OFFSET); + addr_hit[ 996] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_211_OFFSET); + addr_hit[ 997] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_212_OFFSET); + addr_hit[ 998] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_213_OFFSET); + addr_hit[ 999] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_214_OFFSET); + addr_hit[1000] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_215_OFFSET); + addr_hit[1001] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_216_OFFSET); + addr_hit[1002] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_217_OFFSET); + addr_hit[1003] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_218_OFFSET); + addr_hit[1004] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_219_OFFSET); + addr_hit[1005] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_220_OFFSET); + addr_hit[1006] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_221_OFFSET); + addr_hit[1007] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_222_OFFSET); + addr_hit[1008] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_223_OFFSET); + addr_hit[1009] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_224_OFFSET); + addr_hit[1010] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_225_OFFSET); + addr_hit[1011] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_226_OFFSET); + addr_hit[1012] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_227_OFFSET); + addr_hit[1013] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_228_OFFSET); + addr_hit[1014] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_229_OFFSET); + addr_hit[1015] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_230_OFFSET); + addr_hit[1016] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_231_OFFSET); + addr_hit[1017] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_232_OFFSET); + addr_hit[1018] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_233_OFFSET); + addr_hit[1019] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_234_OFFSET); + addr_hit[1020] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_235_OFFSET); + addr_hit[1021] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_236_OFFSET); + addr_hit[1022] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_237_OFFSET); + addr_hit[1023] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_238_OFFSET); + addr_hit[1024] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_239_OFFSET); + addr_hit[1025] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_240_OFFSET); + addr_hit[1026] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_241_OFFSET); + addr_hit[1027] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_242_OFFSET); + addr_hit[1028] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_243_OFFSET); + addr_hit[1029] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_244_OFFSET); + addr_hit[1030] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_245_OFFSET); + addr_hit[1031] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_246_OFFSET); + addr_hit[1032] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_247_OFFSET); + addr_hit[1033] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_248_OFFSET); + addr_hit[1034] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_249_OFFSET); + addr_hit[1035] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_250_OFFSET); + addr_hit[1036] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_251_OFFSET); + addr_hit[1037] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_252_OFFSET); + addr_hit[1038] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_253_OFFSET); + addr_hit[1039] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_254_OFFSET); + addr_hit[1040] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_255_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 9] & ~reg_be))) | + (addr_hit[ 10] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 10] & ~reg_be))) | + (addr_hit[ 11] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 11] & ~reg_be))) | + (addr_hit[ 12] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 12] & ~reg_be))) | + (addr_hit[ 13] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 13] & ~reg_be))) | + (addr_hit[ 14] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 14] & ~reg_be))) | + (addr_hit[ 15] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 15] & ~reg_be))) | + (addr_hit[ 16] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 16] & ~reg_be))) | + (addr_hit[ 17] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 17] & ~reg_be))) | + (addr_hit[ 18] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 18] & ~reg_be))) | + (addr_hit[ 19] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 19] & ~reg_be))) | + (addr_hit[ 20] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 20] & ~reg_be))) | + (addr_hit[ 21] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 21] & ~reg_be))) | + (addr_hit[ 22] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 22] & ~reg_be))) | + (addr_hit[ 23] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 23] & ~reg_be))) | + (addr_hit[ 24] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 24] & ~reg_be))) | + (addr_hit[ 25] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 25] & ~reg_be))) | + (addr_hit[ 26] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 26] & ~reg_be))) | + (addr_hit[ 27] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 27] & ~reg_be))) | + (addr_hit[ 28] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 28] & ~reg_be))) | + (addr_hit[ 29] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 29] & ~reg_be))) | + (addr_hit[ 30] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 30] & ~reg_be))) | + (addr_hit[ 31] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 31] & ~reg_be))) | + (addr_hit[ 32] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 32] & ~reg_be))) | + (addr_hit[ 33] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 33] & ~reg_be))) | + (addr_hit[ 34] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 34] & ~reg_be))) | + (addr_hit[ 35] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 35] & ~reg_be))) | + (addr_hit[ 36] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 36] & ~reg_be))) | + (addr_hit[ 37] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 37] & ~reg_be))) | + (addr_hit[ 38] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 38] & ~reg_be))) | + (addr_hit[ 39] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 39] & ~reg_be))) | + (addr_hit[ 40] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 40] & ~reg_be))) | + (addr_hit[ 41] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 41] & ~reg_be))) | + (addr_hit[ 42] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 42] & ~reg_be))) | + (addr_hit[ 43] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 43] & ~reg_be))) | + (addr_hit[ 44] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 44] & ~reg_be))) | + (addr_hit[ 45] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 45] & ~reg_be))) | + (addr_hit[ 46] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 46] & ~reg_be))) | + (addr_hit[ 47] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 47] & ~reg_be))) | + (addr_hit[ 48] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 48] & ~reg_be))) | + (addr_hit[ 49] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 49] & ~reg_be))) | + (addr_hit[ 50] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 50] & ~reg_be))) | + (addr_hit[ 51] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 51] & ~reg_be))) | + (addr_hit[ 52] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 52] & ~reg_be))) | + (addr_hit[ 53] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 53] & ~reg_be))) | + (addr_hit[ 54] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 54] & ~reg_be))) | + (addr_hit[ 55] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 55] & ~reg_be))) | + (addr_hit[ 56] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 56] & ~reg_be))) | + (addr_hit[ 57] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 57] & ~reg_be))) | + (addr_hit[ 58] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 58] & ~reg_be))) | + (addr_hit[ 59] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 59] & ~reg_be))) | + (addr_hit[ 60] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 60] & ~reg_be))) | + (addr_hit[ 61] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 61] & ~reg_be))) | + (addr_hit[ 62] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 62] & ~reg_be))) | + (addr_hit[ 63] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 63] & ~reg_be))) | + (addr_hit[ 64] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 64] & ~reg_be))) | + (addr_hit[ 65] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 65] & ~reg_be))) | + (addr_hit[ 66] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 66] & ~reg_be))) | + (addr_hit[ 67] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 67] & ~reg_be))) | + (addr_hit[ 68] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 68] & ~reg_be))) | + (addr_hit[ 69] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 69] & ~reg_be))) | + (addr_hit[ 70] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 70] & ~reg_be))) | + (addr_hit[ 71] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 71] & ~reg_be))) | + (addr_hit[ 72] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 72] & ~reg_be))) | + (addr_hit[ 73] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 73] & ~reg_be))) | + (addr_hit[ 74] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 74] & ~reg_be))) | + (addr_hit[ 75] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 75] & ~reg_be))) | + (addr_hit[ 76] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 76] & ~reg_be))) | + (addr_hit[ 77] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 77] & ~reg_be))) | + (addr_hit[ 78] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 78] & ~reg_be))) | + (addr_hit[ 79] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 79] & ~reg_be))) | + (addr_hit[ 80] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 80] & ~reg_be))) | + (addr_hit[ 81] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 81] & ~reg_be))) | + (addr_hit[ 82] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 82] & ~reg_be))) | + (addr_hit[ 83] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 83] & ~reg_be))) | + (addr_hit[ 84] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 84] & ~reg_be))) | + (addr_hit[ 85] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 85] & ~reg_be))) | + (addr_hit[ 86] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 86] & ~reg_be))) | + (addr_hit[ 87] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 87] & ~reg_be))) | + (addr_hit[ 88] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 88] & ~reg_be))) | + (addr_hit[ 89] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 89] & ~reg_be))) | + (addr_hit[ 90] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 90] & ~reg_be))) | + (addr_hit[ 91] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 91] & ~reg_be))) | + (addr_hit[ 92] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 92] & ~reg_be))) | + (addr_hit[ 93] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 93] & ~reg_be))) | + (addr_hit[ 94] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 94] & ~reg_be))) | + (addr_hit[ 95] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 95] & ~reg_be))) | + (addr_hit[ 96] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 96] & ~reg_be))) | + (addr_hit[ 97] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 97] & ~reg_be))) | + (addr_hit[ 98] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 98] & ~reg_be))) | + (addr_hit[ 99] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 99] & ~reg_be))) | + (addr_hit[ 100] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 100] & ~reg_be))) | + (addr_hit[ 101] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 101] & ~reg_be))) | + (addr_hit[ 102] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 102] & ~reg_be))) | + (addr_hit[ 103] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 103] & ~reg_be))) | + (addr_hit[ 104] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 104] & ~reg_be))) | + (addr_hit[ 105] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 105] & ~reg_be))) | + (addr_hit[ 106] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 106] & ~reg_be))) | + (addr_hit[ 107] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 107] & ~reg_be))) | + (addr_hit[ 108] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 108] & ~reg_be))) | + (addr_hit[ 109] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 109] & ~reg_be))) | + (addr_hit[ 110] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 110] & ~reg_be))) | + (addr_hit[ 111] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 111] & ~reg_be))) | + (addr_hit[ 112] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 112] & ~reg_be))) | + (addr_hit[ 113] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 113] & ~reg_be))) | + (addr_hit[ 114] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 114] & ~reg_be))) | + (addr_hit[ 115] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 115] & ~reg_be))) | + (addr_hit[ 116] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 116] & ~reg_be))) | + (addr_hit[ 117] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 117] & ~reg_be))) | + (addr_hit[ 118] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 118] & ~reg_be))) | + (addr_hit[ 119] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 119] & ~reg_be))) | + (addr_hit[ 120] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 120] & ~reg_be))) | + (addr_hit[ 121] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 121] & ~reg_be))) | + (addr_hit[ 122] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 122] & ~reg_be))) | + (addr_hit[ 123] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 123] & ~reg_be))) | + (addr_hit[ 124] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 124] & ~reg_be))) | + (addr_hit[ 125] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 125] & ~reg_be))) | + (addr_hit[ 126] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 126] & ~reg_be))) | + (addr_hit[ 127] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 127] & ~reg_be))) | + (addr_hit[ 128] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 128] & ~reg_be))) | + (addr_hit[ 129] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 129] & ~reg_be))) | + (addr_hit[ 130] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 130] & ~reg_be))) | + (addr_hit[ 131] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 131] & ~reg_be))) | + (addr_hit[ 132] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 132] & ~reg_be))) | + (addr_hit[ 133] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 133] & ~reg_be))) | + (addr_hit[ 134] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 134] & ~reg_be))) | + (addr_hit[ 135] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 135] & ~reg_be))) | + (addr_hit[ 136] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 136] & ~reg_be))) | + (addr_hit[ 137] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 137] & ~reg_be))) | + (addr_hit[ 138] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 138] & ~reg_be))) | + (addr_hit[ 139] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 139] & ~reg_be))) | + (addr_hit[ 140] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 140] & ~reg_be))) | + (addr_hit[ 141] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 141] & ~reg_be))) | + (addr_hit[ 142] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 142] & ~reg_be))) | + (addr_hit[ 143] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 143] & ~reg_be))) | + (addr_hit[ 144] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 144] & ~reg_be))) | + (addr_hit[ 145] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 145] & ~reg_be))) | + (addr_hit[ 146] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 146] & ~reg_be))) | + (addr_hit[ 147] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 147] & ~reg_be))) | + (addr_hit[ 148] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 148] & ~reg_be))) | + (addr_hit[ 149] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 149] & ~reg_be))) | + (addr_hit[ 150] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 150] & ~reg_be))) | + (addr_hit[ 151] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 151] & ~reg_be))) | + (addr_hit[ 152] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 152] & ~reg_be))) | + (addr_hit[ 153] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 153] & ~reg_be))) | + (addr_hit[ 154] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 154] & ~reg_be))) | + (addr_hit[ 155] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 155] & ~reg_be))) | + (addr_hit[ 156] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 156] & ~reg_be))) | + (addr_hit[ 157] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 157] & ~reg_be))) | + (addr_hit[ 158] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 158] & ~reg_be))) | + (addr_hit[ 159] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 159] & ~reg_be))) | + (addr_hit[ 160] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 160] & ~reg_be))) | + (addr_hit[ 161] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 161] & ~reg_be))) | + (addr_hit[ 162] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 162] & ~reg_be))) | + (addr_hit[ 163] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 163] & ~reg_be))) | + (addr_hit[ 164] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 164] & ~reg_be))) | + (addr_hit[ 165] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 165] & ~reg_be))) | + (addr_hit[ 166] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 166] & ~reg_be))) | + (addr_hit[ 167] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 167] & ~reg_be))) | + (addr_hit[ 168] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 168] & ~reg_be))) | + (addr_hit[ 169] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 169] & ~reg_be))) | + (addr_hit[ 170] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 170] & ~reg_be))) | + (addr_hit[ 171] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 171] & ~reg_be))) | + (addr_hit[ 172] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 172] & ~reg_be))) | + (addr_hit[ 173] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 173] & ~reg_be))) | + (addr_hit[ 174] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 174] & ~reg_be))) | + (addr_hit[ 175] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 175] & ~reg_be))) | + (addr_hit[ 176] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 176] & ~reg_be))) | + (addr_hit[ 177] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 177] & ~reg_be))) | + (addr_hit[ 178] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 178] & ~reg_be))) | + (addr_hit[ 179] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 179] & ~reg_be))) | + (addr_hit[ 180] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 180] & ~reg_be))) | + (addr_hit[ 181] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 181] & ~reg_be))) | + (addr_hit[ 182] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 182] & ~reg_be))) | + (addr_hit[ 183] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 183] & ~reg_be))) | + (addr_hit[ 184] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 184] & ~reg_be))) | + (addr_hit[ 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985] & ~reg_be))) | + (addr_hit[ 986] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 986] & ~reg_be))) | + (addr_hit[ 987] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 987] & ~reg_be))) | + (addr_hit[ 988] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 988] & ~reg_be))) | + (addr_hit[ 989] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 989] & ~reg_be))) | + (addr_hit[ 990] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 990] & ~reg_be))) | + (addr_hit[ 991] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 991] & ~reg_be))) | + (addr_hit[ 992] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 992] & ~reg_be))) | + (addr_hit[ 993] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 993] & ~reg_be))) | + (addr_hit[ 994] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 994] & ~reg_be))) | + (addr_hit[ 995] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 995] & ~reg_be))) | + (addr_hit[ 996] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 996] & ~reg_be))) | + (addr_hit[ 997] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 997] & ~reg_be))) | + (addr_hit[ 998] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 998] & ~reg_be))) | + (addr_hit[ 999] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 999] & ~reg_be))) | + (addr_hit[1000] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1000] & ~reg_be))) | + (addr_hit[1001] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1001] & ~reg_be))) | + (addr_hit[1002] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1002] & ~reg_be))) | + (addr_hit[1003] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1003] & ~reg_be))) | + (addr_hit[1004] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1004] & ~reg_be))) | + (addr_hit[1005] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1005] & ~reg_be))) | + (addr_hit[1006] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1006] & ~reg_be))) | + (addr_hit[1007] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1007] & ~reg_be))) | + (addr_hit[1008] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1008] & ~reg_be))) | + (addr_hit[1009] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1009] & ~reg_be))) | + (addr_hit[1010] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1010] & ~reg_be))) | + (addr_hit[1011] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1011] & ~reg_be))) | + (addr_hit[1012] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1012] & ~reg_be))) | + (addr_hit[1013] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1013] & ~reg_be))) | + (addr_hit[1014] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1014] & ~reg_be))) | + (addr_hit[1015] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1015] & ~reg_be))) | + (addr_hit[1016] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1016] & ~reg_be))) | + (addr_hit[1017] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1017] & ~reg_be))) | + (addr_hit[1018] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1018] & ~reg_be))) | + (addr_hit[1019] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1019] & ~reg_be))) | + (addr_hit[1020] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1020] & ~reg_be))) | + (addr_hit[1021] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1021] & ~reg_be))) | + (addr_hit[1022] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1022] & ~reg_be))) | + (addr_hit[1023] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1023] & ~reg_be))) | + (addr_hit[1024] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1024] & ~reg_be))) | + (addr_hit[1025] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1025] & ~reg_be))) | + (addr_hit[1026] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1026] & ~reg_be))) | + (addr_hit[1027] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1027] & ~reg_be))) | + (addr_hit[1028] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1028] & ~reg_be))) | + (addr_hit[1029] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1029] & ~reg_be))) | + (addr_hit[1030] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1030] & ~reg_be))) | + (addr_hit[1031] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1031] & ~reg_be))) | + (addr_hit[1032] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1032] & ~reg_be))) | + (addr_hit[1033] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1033] & ~reg_be))) | + (addr_hit[1034] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1034] & ~reg_be))) | + (addr_hit[1035] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1035] & ~reg_be))) | + (addr_hit[1036] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1036] & ~reg_be))) | + (addr_hit[1037] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1037] & ~reg_be))) | + (addr_hit[1038] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1038] & ~reg_be))) | + (addr_hit[1039] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1039] & ~reg_be))) | + (addr_hit[1040] & (|(CACHEPOOL_PERIPHERAL_PERMIT[1040] & ~reg_be))))); + end + + assign hw_barrier_re = addr_hit[0] & reg_re & !reg_error; + + assign icache_prefetch_enable_we = addr_hit[1] & reg_we & !reg_error; + assign icache_prefetch_enable_wd = reg_wdata[0]; + + assign spatz_status_we = addr_hit[2] & reg_we & !reg_error; + assign spatz_status_wd = reg_wdata[0]; + + assign spatz_cycle_we = addr_hit[3] & reg_we & !reg_error; + assign spatz_cycle_wd = reg_wdata[31:0]; + + assign cluster_boot_control_we = addr_hit[4] & reg_we & !reg_error; + assign cluster_boot_control_wd = reg_wdata[31:0]; + + assign cluster_eoc_exit_we = addr_hit[5] & reg_we & !reg_error; + assign cluster_eoc_exit_wd = reg_wdata[3:0]; + + assign cfg_l1d_spm_we = addr_hit[6] & reg_we & !reg_error; + assign cfg_l1d_spm_wd = reg_wdata[9:0]; + + assign cfg_l1d_insn_we = addr_hit[7] & reg_we & !reg_error; + assign cfg_l1d_insn_wd = reg_wdata[1:0]; + + assign cfg_l1d_tile_sel_0_we = addr_hit[8] & reg_we & !reg_error; + assign cfg_l1d_tile_sel_0_wd = reg_wdata[31:0]; + + assign cfg_l1d_tile_sel_1_we = addr_hit[9] & reg_we & !reg_error; + assign cfg_l1d_tile_sel_1_wd = reg_wdata[31:0]; + + assign l1d_spm_commit_we = addr_hit[10] & reg_we & !reg_error; + assign l1d_spm_commit_wd = reg_wdata[0]; + + assign l1d_insn_commit_we = addr_hit[11] & reg_we & !reg_error; + assign l1d_insn_commit_wd = reg_wdata[0]; + + assign l1d_flush_status_re = addr_hit[12] & reg_re & !reg_error; + + assign l1d_private_we = addr_hit[13] & reg_we & !reg_error; + assign l1d_private_wd = reg_wdata[3:0]; + + assign l1d_addr_we = addr_hit[14] & reg_we & !reg_error; + assign l1d_addr_wd = reg_wdata[31:0]; + + assign xbar_offset_we = addr_hit[15] & reg_we & !reg_error; + assign xbar_offset_wd = reg_wdata[4:0]; + + assign xbar_offset_commit_we = addr_hit[16] & reg_we & !reg_error; + assign xbar_offset_commit_wd = reg_wdata[0]; + + assign cfg_lp1_cmo_0_we = addr_hit[17] & reg_we & !reg_error; + assign cfg_lp1_cmo_0_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_1_we = addr_hit[18] & reg_we & !reg_error; + assign cfg_lp1_cmo_1_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_2_we = addr_hit[19] & reg_we & !reg_error; + assign cfg_lp1_cmo_2_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_3_we = addr_hit[20] & reg_we & !reg_error; + assign cfg_lp1_cmo_3_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_4_we = addr_hit[21] & reg_we & !reg_error; + assign cfg_lp1_cmo_4_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_5_we = addr_hit[22] & reg_we & !reg_error; + assign cfg_lp1_cmo_5_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_6_we = addr_hit[23] & reg_we & !reg_error; + assign cfg_lp1_cmo_6_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_7_we = addr_hit[24] & reg_we & !reg_error; + assign cfg_lp1_cmo_7_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_8_we = addr_hit[25] & reg_we & !reg_error; + assign cfg_lp1_cmo_8_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_9_we = addr_hit[26] & reg_we & !reg_error; + assign cfg_lp1_cmo_9_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_10_we = addr_hit[27] & reg_we & !reg_error; + assign cfg_lp1_cmo_10_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_11_we = addr_hit[28] & reg_we & !reg_error; + assign cfg_lp1_cmo_11_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_12_we = addr_hit[29] & reg_we & !reg_error; + assign cfg_lp1_cmo_12_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_13_we = addr_hit[30] & reg_we & !reg_error; + assign cfg_lp1_cmo_13_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_14_we = addr_hit[31] & reg_we & !reg_error; + assign cfg_lp1_cmo_14_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_15_we = addr_hit[32] & reg_we & !reg_error; + assign cfg_lp1_cmo_15_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_16_we = addr_hit[33] & reg_we & !reg_error; + assign cfg_lp1_cmo_16_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_17_we = addr_hit[34] & reg_we & !reg_error; + assign cfg_lp1_cmo_17_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_18_we = addr_hit[35] & reg_we & !reg_error; + assign cfg_lp1_cmo_18_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_19_we = addr_hit[36] & reg_we & !reg_error; + assign cfg_lp1_cmo_19_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_20_we = addr_hit[37] & reg_we & !reg_error; + assign cfg_lp1_cmo_20_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_21_we = addr_hit[38] & reg_we & !reg_error; + assign cfg_lp1_cmo_21_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_22_we = addr_hit[39] & reg_we & !reg_error; + assign cfg_lp1_cmo_22_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_23_we = addr_hit[40] & reg_we & !reg_error; + assign cfg_lp1_cmo_23_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_24_we = addr_hit[41] & reg_we & !reg_error; + assign cfg_lp1_cmo_24_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_25_we = addr_hit[42] & reg_we & !reg_error; + assign cfg_lp1_cmo_25_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_26_we = addr_hit[43] & reg_we & !reg_error; + assign cfg_lp1_cmo_26_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_27_we = addr_hit[44] & reg_we & !reg_error; + assign cfg_lp1_cmo_27_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_28_we = addr_hit[45] & reg_we & !reg_error; + assign cfg_lp1_cmo_28_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_29_we = addr_hit[46] & reg_we & !reg_error; + assign cfg_lp1_cmo_29_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_30_we = addr_hit[47] & reg_we & !reg_error; + assign cfg_lp1_cmo_30_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_31_we = addr_hit[48] & reg_we & !reg_error; + assign cfg_lp1_cmo_31_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_32_we = addr_hit[49] & reg_we & !reg_error; + assign cfg_lp1_cmo_32_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_33_we = addr_hit[50] & reg_we & !reg_error; + assign cfg_lp1_cmo_33_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_34_we = addr_hit[51] & reg_we & !reg_error; + assign cfg_lp1_cmo_34_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_35_we = addr_hit[52] & reg_we & !reg_error; + assign cfg_lp1_cmo_35_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_36_we = addr_hit[53] & reg_we & !reg_error; + assign cfg_lp1_cmo_36_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_37_we = addr_hit[54] & reg_we & !reg_error; + assign cfg_lp1_cmo_37_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_38_we = addr_hit[55] & reg_we & !reg_error; + assign cfg_lp1_cmo_38_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_39_we = addr_hit[56] & reg_we & !reg_error; + assign cfg_lp1_cmo_39_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_40_we = addr_hit[57] & reg_we & !reg_error; + assign cfg_lp1_cmo_40_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_41_we = addr_hit[58] & reg_we & !reg_error; + assign cfg_lp1_cmo_41_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_42_we = addr_hit[59] & reg_we & !reg_error; + assign cfg_lp1_cmo_42_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_43_we = addr_hit[60] & reg_we & !reg_error; + assign cfg_lp1_cmo_43_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_44_we = addr_hit[61] & reg_we & !reg_error; + assign cfg_lp1_cmo_44_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_45_we = addr_hit[62] & reg_we & !reg_error; + assign cfg_lp1_cmo_45_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_46_we = addr_hit[63] & reg_we & !reg_error; + assign cfg_lp1_cmo_46_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_47_we = addr_hit[64] & reg_we & !reg_error; + assign cfg_lp1_cmo_47_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_48_we = addr_hit[65] & reg_we & !reg_error; + assign cfg_lp1_cmo_48_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_49_we = addr_hit[66] & reg_we & !reg_error; + assign cfg_lp1_cmo_49_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_50_we = addr_hit[67] & reg_we & !reg_error; + assign cfg_lp1_cmo_50_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_51_we = addr_hit[68] & reg_we & !reg_error; + assign cfg_lp1_cmo_51_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_52_we = addr_hit[69] & reg_we & !reg_error; + assign cfg_lp1_cmo_52_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_53_we = addr_hit[70] & reg_we & !reg_error; + assign cfg_lp1_cmo_53_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_54_we = addr_hit[71] & reg_we & !reg_error; + assign cfg_lp1_cmo_54_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_55_we = addr_hit[72] & reg_we & !reg_error; + assign cfg_lp1_cmo_55_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_56_we = addr_hit[73] & reg_we & !reg_error; + assign cfg_lp1_cmo_56_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_57_we = addr_hit[74] & reg_we & !reg_error; + assign cfg_lp1_cmo_57_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_58_we = addr_hit[75] & reg_we & !reg_error; + assign cfg_lp1_cmo_58_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_59_we = addr_hit[76] & reg_we & !reg_error; + assign cfg_lp1_cmo_59_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_60_we = addr_hit[77] & reg_we & !reg_error; + assign cfg_lp1_cmo_60_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_61_we = addr_hit[78] & reg_we & !reg_error; + assign cfg_lp1_cmo_61_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_62_we = addr_hit[79] & reg_we & !reg_error; + assign cfg_lp1_cmo_62_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_63_we = addr_hit[80] & reg_we & !reg_error; + assign cfg_lp1_cmo_63_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_64_we = addr_hit[81] & reg_we & !reg_error; + assign cfg_lp1_cmo_64_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_65_we = addr_hit[82] & reg_we & !reg_error; + assign cfg_lp1_cmo_65_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_66_we = addr_hit[83] & reg_we & !reg_error; + assign cfg_lp1_cmo_66_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_67_we = addr_hit[84] & reg_we & !reg_error; + assign cfg_lp1_cmo_67_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_68_we = addr_hit[85] & reg_we & !reg_error; + assign cfg_lp1_cmo_68_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_69_we = addr_hit[86] & reg_we & !reg_error; + assign cfg_lp1_cmo_69_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_70_we = addr_hit[87] & reg_we & !reg_error; + assign cfg_lp1_cmo_70_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_71_we = addr_hit[88] & reg_we & !reg_error; + assign cfg_lp1_cmo_71_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_72_we = addr_hit[89] & reg_we & !reg_error; + assign cfg_lp1_cmo_72_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_73_we = addr_hit[90] & reg_we & !reg_error; + assign cfg_lp1_cmo_73_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_74_we = addr_hit[91] & reg_we & !reg_error; + assign cfg_lp1_cmo_74_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_75_we = addr_hit[92] & reg_we & !reg_error; + assign cfg_lp1_cmo_75_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_76_we = addr_hit[93] & reg_we & !reg_error; + assign cfg_lp1_cmo_76_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_77_we = addr_hit[94] & reg_we & !reg_error; + assign cfg_lp1_cmo_77_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_78_we = addr_hit[95] & reg_we & !reg_error; + assign cfg_lp1_cmo_78_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_79_we = addr_hit[96] & reg_we & !reg_error; + assign cfg_lp1_cmo_79_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_80_we = addr_hit[97] & reg_we & !reg_error; + assign cfg_lp1_cmo_80_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_81_we = addr_hit[98] & reg_we & !reg_error; + assign cfg_lp1_cmo_81_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_82_we = addr_hit[99] & reg_we & !reg_error; + assign cfg_lp1_cmo_82_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_83_we = addr_hit[100] & reg_we & !reg_error; + assign cfg_lp1_cmo_83_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_84_we = addr_hit[101] & reg_we & !reg_error; + assign cfg_lp1_cmo_84_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_85_we = addr_hit[102] & reg_we & !reg_error; + assign cfg_lp1_cmo_85_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_86_we = addr_hit[103] & reg_we & !reg_error; + assign cfg_lp1_cmo_86_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_87_we = addr_hit[104] & reg_we & !reg_error; + assign cfg_lp1_cmo_87_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_88_we = addr_hit[105] & reg_we & !reg_error; + assign cfg_lp1_cmo_88_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_89_we = addr_hit[106] & reg_we & !reg_error; + assign cfg_lp1_cmo_89_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_90_we = addr_hit[107] & reg_we & !reg_error; + assign cfg_lp1_cmo_90_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_91_we = addr_hit[108] & reg_we & !reg_error; + assign cfg_lp1_cmo_91_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_92_we = addr_hit[109] & reg_we & !reg_error; + assign cfg_lp1_cmo_92_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_93_we = addr_hit[110] & reg_we & !reg_error; + assign cfg_lp1_cmo_93_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_94_we = addr_hit[111] & reg_we & !reg_error; + assign cfg_lp1_cmo_94_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_95_we = addr_hit[112] & reg_we & !reg_error; + assign cfg_lp1_cmo_95_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_96_we = addr_hit[113] & reg_we & !reg_error; + assign cfg_lp1_cmo_96_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_97_we = addr_hit[114] & reg_we & !reg_error; + assign cfg_lp1_cmo_97_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_98_we = addr_hit[115] & reg_we & !reg_error; + assign cfg_lp1_cmo_98_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_99_we = addr_hit[116] & reg_we & !reg_error; + assign cfg_lp1_cmo_99_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_100_we = addr_hit[117] & reg_we & !reg_error; + assign cfg_lp1_cmo_100_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_101_we = addr_hit[118] & reg_we & !reg_error; + assign cfg_lp1_cmo_101_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_102_we = addr_hit[119] & reg_we & !reg_error; + assign cfg_lp1_cmo_102_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_103_we = addr_hit[120] & reg_we & !reg_error; + assign cfg_lp1_cmo_103_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_104_we = addr_hit[121] & reg_we & !reg_error; + assign cfg_lp1_cmo_104_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_105_we = addr_hit[122] & reg_we & !reg_error; + assign cfg_lp1_cmo_105_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_106_we = addr_hit[123] & reg_we & !reg_error; + assign cfg_lp1_cmo_106_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_107_we = addr_hit[124] & reg_we & !reg_error; + assign cfg_lp1_cmo_107_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_108_we = addr_hit[125] & reg_we & !reg_error; + assign cfg_lp1_cmo_108_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_109_we = addr_hit[126] & reg_we & !reg_error; + assign cfg_lp1_cmo_109_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_110_we = addr_hit[127] & reg_we & !reg_error; + assign cfg_lp1_cmo_110_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_111_we = addr_hit[128] & reg_we & !reg_error; + assign cfg_lp1_cmo_111_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_112_we = addr_hit[129] & reg_we & !reg_error; + assign cfg_lp1_cmo_112_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_113_we = addr_hit[130] & reg_we & !reg_error; + assign cfg_lp1_cmo_113_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_114_we = addr_hit[131] & reg_we & !reg_error; + assign cfg_lp1_cmo_114_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_115_we = addr_hit[132] & reg_we & !reg_error; + assign cfg_lp1_cmo_115_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_116_we = addr_hit[133] & reg_we & !reg_error; + assign cfg_lp1_cmo_116_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_117_we = addr_hit[134] & reg_we & !reg_error; + assign cfg_lp1_cmo_117_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_118_we = addr_hit[135] & reg_we & !reg_error; + assign cfg_lp1_cmo_118_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_119_we = addr_hit[136] & reg_we & !reg_error; + assign cfg_lp1_cmo_119_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_120_we = addr_hit[137] & reg_we & !reg_error; + assign cfg_lp1_cmo_120_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_121_we = addr_hit[138] & reg_we & !reg_error; + assign cfg_lp1_cmo_121_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_122_we = addr_hit[139] & reg_we & !reg_error; + assign cfg_lp1_cmo_122_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_123_we = addr_hit[140] & reg_we & !reg_error; + assign cfg_lp1_cmo_123_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_124_we = addr_hit[141] & reg_we & !reg_error; + assign cfg_lp1_cmo_124_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_125_we = addr_hit[142] & reg_we & !reg_error; + assign cfg_lp1_cmo_125_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_126_we = addr_hit[143] & reg_we & !reg_error; + assign cfg_lp1_cmo_126_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_127_we = addr_hit[144] & reg_we & !reg_error; + assign cfg_lp1_cmo_127_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_128_we = addr_hit[145] & reg_we & !reg_error; + assign cfg_lp1_cmo_128_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_129_we = addr_hit[146] & reg_we & !reg_error; + assign cfg_lp1_cmo_129_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_130_we = addr_hit[147] & reg_we & !reg_error; + assign cfg_lp1_cmo_130_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_131_we = addr_hit[148] & reg_we & !reg_error; + assign cfg_lp1_cmo_131_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_132_we = addr_hit[149] & reg_we & !reg_error; + assign cfg_lp1_cmo_132_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_133_we = addr_hit[150] & reg_we & !reg_error; + assign cfg_lp1_cmo_133_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_134_we = addr_hit[151] & reg_we & !reg_error; + assign cfg_lp1_cmo_134_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_135_we = addr_hit[152] & reg_we & !reg_error; + assign cfg_lp1_cmo_135_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_136_we = addr_hit[153] & reg_we & !reg_error; + assign cfg_lp1_cmo_136_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_137_we = addr_hit[154] & reg_we & !reg_error; + assign cfg_lp1_cmo_137_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_138_we = addr_hit[155] & reg_we & !reg_error; + assign cfg_lp1_cmo_138_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_139_we = addr_hit[156] & reg_we & !reg_error; + assign cfg_lp1_cmo_139_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_140_we = addr_hit[157] & reg_we & !reg_error; + assign cfg_lp1_cmo_140_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_141_we = addr_hit[158] & reg_we & !reg_error; + assign cfg_lp1_cmo_141_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_142_we = addr_hit[159] & reg_we & !reg_error; + assign cfg_lp1_cmo_142_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_143_we = addr_hit[160] & reg_we & !reg_error; + assign cfg_lp1_cmo_143_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_144_we = addr_hit[161] & reg_we & !reg_error; + assign cfg_lp1_cmo_144_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_145_we = addr_hit[162] & reg_we & !reg_error; + assign cfg_lp1_cmo_145_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_146_we = addr_hit[163] & reg_we & !reg_error; + assign cfg_lp1_cmo_146_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_147_we = addr_hit[164] & reg_we & !reg_error; + assign cfg_lp1_cmo_147_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_148_we = addr_hit[165] & reg_we & !reg_error; + assign cfg_lp1_cmo_148_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_149_we = addr_hit[166] & reg_we & !reg_error; + assign cfg_lp1_cmo_149_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_150_we = addr_hit[167] & reg_we & !reg_error; + assign cfg_lp1_cmo_150_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_151_we = addr_hit[168] & reg_we & !reg_error; + assign cfg_lp1_cmo_151_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_152_we = addr_hit[169] & reg_we & !reg_error; + assign cfg_lp1_cmo_152_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_153_we = addr_hit[170] & reg_we & !reg_error; + assign cfg_lp1_cmo_153_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_154_we = addr_hit[171] & reg_we & !reg_error; + assign cfg_lp1_cmo_154_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_155_we = addr_hit[172] & reg_we & !reg_error; + assign cfg_lp1_cmo_155_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_156_we = addr_hit[173] & reg_we & !reg_error; + assign cfg_lp1_cmo_156_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_157_we = addr_hit[174] & reg_we & !reg_error; + assign cfg_lp1_cmo_157_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_158_we = addr_hit[175] & reg_we & !reg_error; + assign cfg_lp1_cmo_158_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_159_we = addr_hit[176] & reg_we & !reg_error; + assign cfg_lp1_cmo_159_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_160_we = addr_hit[177] & reg_we & !reg_error; + assign cfg_lp1_cmo_160_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_161_we = addr_hit[178] & reg_we & !reg_error; + assign cfg_lp1_cmo_161_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_162_we = addr_hit[179] & reg_we & !reg_error; + assign cfg_lp1_cmo_162_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_163_we = addr_hit[180] & reg_we & !reg_error; + assign cfg_lp1_cmo_163_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_164_we = addr_hit[181] & reg_we & !reg_error; + assign cfg_lp1_cmo_164_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_165_we = addr_hit[182] & reg_we & !reg_error; + assign cfg_lp1_cmo_165_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_166_we = addr_hit[183] & reg_we & !reg_error; + assign cfg_lp1_cmo_166_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_167_we = addr_hit[184] & reg_we & !reg_error; + assign cfg_lp1_cmo_167_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_168_we = addr_hit[185] & reg_we & !reg_error; + assign cfg_lp1_cmo_168_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_169_we = addr_hit[186] & reg_we & !reg_error; + assign cfg_lp1_cmo_169_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_170_we = addr_hit[187] & reg_we & !reg_error; + assign cfg_lp1_cmo_170_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_171_we = addr_hit[188] & reg_we & !reg_error; + assign cfg_lp1_cmo_171_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_172_we = addr_hit[189] & reg_we & !reg_error; + assign cfg_lp1_cmo_172_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_173_we = addr_hit[190] & reg_we & !reg_error; + assign cfg_lp1_cmo_173_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_174_we = addr_hit[191] & reg_we & !reg_error; + assign cfg_lp1_cmo_174_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_175_we = addr_hit[192] & reg_we & !reg_error; + assign cfg_lp1_cmo_175_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_176_we = addr_hit[193] & reg_we & !reg_error; + assign cfg_lp1_cmo_176_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_177_we = addr_hit[194] & reg_we & !reg_error; + assign cfg_lp1_cmo_177_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_178_we = addr_hit[195] & reg_we & !reg_error; + assign cfg_lp1_cmo_178_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_179_we = addr_hit[196] & reg_we & !reg_error; + assign cfg_lp1_cmo_179_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_180_we = addr_hit[197] & reg_we & !reg_error; + assign cfg_lp1_cmo_180_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_181_we = addr_hit[198] & reg_we & !reg_error; + assign cfg_lp1_cmo_181_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_182_we = addr_hit[199] & reg_we & !reg_error; + assign cfg_lp1_cmo_182_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_183_we = addr_hit[200] & reg_we & !reg_error; + assign cfg_lp1_cmo_183_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_184_we = addr_hit[201] & reg_we & !reg_error; + assign cfg_lp1_cmo_184_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_185_we = addr_hit[202] & reg_we & !reg_error; + assign cfg_lp1_cmo_185_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_186_we = addr_hit[203] & reg_we & !reg_error; + assign cfg_lp1_cmo_186_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_187_we = addr_hit[204] & reg_we & !reg_error; + assign cfg_lp1_cmo_187_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_188_we = addr_hit[205] & reg_we & !reg_error; + assign cfg_lp1_cmo_188_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_189_we = addr_hit[206] & reg_we & !reg_error; + assign cfg_lp1_cmo_189_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_190_we = addr_hit[207] & reg_we & !reg_error; + assign cfg_lp1_cmo_190_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_191_we = addr_hit[208] & reg_we & !reg_error; + assign cfg_lp1_cmo_191_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_192_we = addr_hit[209] & reg_we & !reg_error; + assign cfg_lp1_cmo_192_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_193_we = addr_hit[210] & reg_we & !reg_error; + assign cfg_lp1_cmo_193_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_194_we = addr_hit[211] & reg_we & !reg_error; + assign cfg_lp1_cmo_194_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_195_we = addr_hit[212] & reg_we & !reg_error; + assign cfg_lp1_cmo_195_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_196_we = addr_hit[213] & reg_we & !reg_error; + assign cfg_lp1_cmo_196_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_197_we = addr_hit[214] & reg_we & !reg_error; + assign cfg_lp1_cmo_197_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_198_we = addr_hit[215] & reg_we & !reg_error; + assign cfg_lp1_cmo_198_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_199_we = addr_hit[216] & reg_we & !reg_error; + assign cfg_lp1_cmo_199_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_200_we = addr_hit[217] & reg_we & !reg_error; + assign cfg_lp1_cmo_200_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_201_we = addr_hit[218] & reg_we & !reg_error; + assign cfg_lp1_cmo_201_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_202_we = addr_hit[219] & reg_we & !reg_error; + assign cfg_lp1_cmo_202_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_203_we = addr_hit[220] & reg_we & !reg_error; + assign cfg_lp1_cmo_203_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_204_we = addr_hit[221] & reg_we & !reg_error; + assign cfg_lp1_cmo_204_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_205_we = addr_hit[222] & reg_we & !reg_error; + assign cfg_lp1_cmo_205_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_206_we = addr_hit[223] & reg_we & !reg_error; + assign cfg_lp1_cmo_206_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_207_we = addr_hit[224] & reg_we & !reg_error; + assign cfg_lp1_cmo_207_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_208_we = addr_hit[225] & reg_we & !reg_error; + assign cfg_lp1_cmo_208_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_209_we = addr_hit[226] & reg_we & !reg_error; + assign cfg_lp1_cmo_209_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_210_we = addr_hit[227] & reg_we & !reg_error; + assign cfg_lp1_cmo_210_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_211_we = addr_hit[228] & reg_we & !reg_error; + assign cfg_lp1_cmo_211_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_212_we = addr_hit[229] & reg_we & !reg_error; + assign cfg_lp1_cmo_212_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_213_we = addr_hit[230] & reg_we & !reg_error; + assign cfg_lp1_cmo_213_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_214_we = addr_hit[231] & reg_we & !reg_error; + assign cfg_lp1_cmo_214_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_215_we = addr_hit[232] & reg_we & !reg_error; + assign cfg_lp1_cmo_215_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_216_we = addr_hit[233] & reg_we & !reg_error; + assign cfg_lp1_cmo_216_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_217_we = addr_hit[234] & reg_we & !reg_error; + assign cfg_lp1_cmo_217_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_218_we = addr_hit[235] & reg_we & !reg_error; + assign cfg_lp1_cmo_218_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_219_we = addr_hit[236] & reg_we & !reg_error; + assign cfg_lp1_cmo_219_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_220_we = addr_hit[237] & reg_we & !reg_error; + assign cfg_lp1_cmo_220_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_221_we = addr_hit[238] & reg_we & !reg_error; + assign cfg_lp1_cmo_221_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_222_we = addr_hit[239] & reg_we & !reg_error; + assign cfg_lp1_cmo_222_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_223_we = addr_hit[240] & reg_we & !reg_error; + assign cfg_lp1_cmo_223_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_224_we = addr_hit[241] & reg_we & !reg_error; + assign cfg_lp1_cmo_224_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_225_we = addr_hit[242] & reg_we & !reg_error; + assign cfg_lp1_cmo_225_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_226_we = addr_hit[243] & reg_we & !reg_error; + assign cfg_lp1_cmo_226_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_227_we = addr_hit[244] & reg_we & !reg_error; + assign cfg_lp1_cmo_227_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_228_we = addr_hit[245] & reg_we & !reg_error; + assign cfg_lp1_cmo_228_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_229_we = addr_hit[246] & reg_we & !reg_error; + assign cfg_lp1_cmo_229_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_230_we = addr_hit[247] & reg_we & !reg_error; + assign cfg_lp1_cmo_230_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_231_we = addr_hit[248] & reg_we & !reg_error; + assign cfg_lp1_cmo_231_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_232_we = addr_hit[249] & reg_we & !reg_error; + assign cfg_lp1_cmo_232_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_233_we = addr_hit[250] & reg_we & !reg_error; + assign cfg_lp1_cmo_233_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_234_we = addr_hit[251] & reg_we & !reg_error; + assign cfg_lp1_cmo_234_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_235_we = addr_hit[252] & reg_we & !reg_error; + assign cfg_lp1_cmo_235_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_236_we = addr_hit[253] & reg_we & !reg_error; + assign cfg_lp1_cmo_236_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_237_we = addr_hit[254] & reg_we & !reg_error; + assign cfg_lp1_cmo_237_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_238_we = addr_hit[255] & reg_we & !reg_error; + assign cfg_lp1_cmo_238_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_239_we = addr_hit[256] & reg_we & !reg_error; + assign cfg_lp1_cmo_239_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_240_we = addr_hit[257] & reg_we & !reg_error; + assign cfg_lp1_cmo_240_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_241_we = addr_hit[258] & reg_we & !reg_error; + assign cfg_lp1_cmo_241_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_242_we = addr_hit[259] & reg_we & !reg_error; + assign cfg_lp1_cmo_242_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_243_we = addr_hit[260] & reg_we & !reg_error; + assign cfg_lp1_cmo_243_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_244_we = addr_hit[261] & reg_we & !reg_error; + assign cfg_lp1_cmo_244_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_245_we = addr_hit[262] & reg_we & !reg_error; + assign cfg_lp1_cmo_245_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_246_we = addr_hit[263] & reg_we & !reg_error; + assign cfg_lp1_cmo_246_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_247_we = addr_hit[264] & reg_we & !reg_error; + assign cfg_lp1_cmo_247_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_248_we = addr_hit[265] & reg_we & !reg_error; + assign cfg_lp1_cmo_248_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_249_we = addr_hit[266] & reg_we & !reg_error; + assign cfg_lp1_cmo_249_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_250_we = addr_hit[267] & reg_we & !reg_error; + assign cfg_lp1_cmo_250_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_251_we = addr_hit[268] & reg_we & !reg_error; + assign cfg_lp1_cmo_251_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_252_we = addr_hit[269] & reg_we & !reg_error; + assign cfg_lp1_cmo_252_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_253_we = addr_hit[270] & reg_we & !reg_error; + assign cfg_lp1_cmo_253_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_254_we = addr_hit[271] & reg_we & !reg_error; + assign cfg_lp1_cmo_254_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_255_we = addr_hit[272] & reg_we & !reg_error; + assign cfg_lp1_cmo_255_wd = reg_wdata[2:0]; + + assign cfg_lp1_cmo_addr_0_we = addr_hit[273] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_0_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_1_we = addr_hit[274] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_1_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_2_we = addr_hit[275] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_2_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_3_we = addr_hit[276] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_3_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_4_we = addr_hit[277] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_4_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_5_we = addr_hit[278] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_5_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_6_we = addr_hit[279] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_6_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_7_we = addr_hit[280] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_7_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_8_we = addr_hit[281] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_8_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_9_we = addr_hit[282] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_9_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_10_we = addr_hit[283] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_10_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_11_we = addr_hit[284] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_11_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_12_we = addr_hit[285] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_12_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_13_we = addr_hit[286] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_13_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_14_we = addr_hit[287] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_14_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_15_we = addr_hit[288] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_15_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_16_we = addr_hit[289] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_16_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_17_we = addr_hit[290] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_17_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_18_we = addr_hit[291] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_18_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_19_we = addr_hit[292] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_19_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_20_we = addr_hit[293] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_20_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_21_we = addr_hit[294] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_21_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_22_we = addr_hit[295] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_22_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_23_we = addr_hit[296] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_23_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_24_we = addr_hit[297] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_24_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_25_we = addr_hit[298] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_25_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_26_we = addr_hit[299] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_26_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_27_we = addr_hit[300] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_27_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_28_we = addr_hit[301] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_28_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_29_we = addr_hit[302] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_29_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_30_we = addr_hit[303] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_30_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_31_we = addr_hit[304] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_31_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_32_we = addr_hit[305] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_32_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_33_we = addr_hit[306] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_33_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_34_we = addr_hit[307] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_34_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_35_we = addr_hit[308] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_35_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_36_we = addr_hit[309] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_36_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_37_we = addr_hit[310] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_37_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_38_we = addr_hit[311] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_38_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_39_we = addr_hit[312] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_39_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_40_we = addr_hit[313] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_40_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_41_we = addr_hit[314] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_41_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_42_we = addr_hit[315] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_42_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_43_we = addr_hit[316] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_43_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_44_we = addr_hit[317] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_44_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_45_we = addr_hit[318] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_45_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_46_we = addr_hit[319] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_46_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_47_we = addr_hit[320] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_47_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_48_we = addr_hit[321] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_48_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_49_we = addr_hit[322] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_49_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_50_we = addr_hit[323] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_50_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_51_we = addr_hit[324] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_51_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_52_we = addr_hit[325] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_52_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_53_we = addr_hit[326] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_53_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_54_we = addr_hit[327] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_54_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_55_we = addr_hit[328] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_55_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_56_we = addr_hit[329] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_56_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_57_we = addr_hit[330] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_57_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_58_we = addr_hit[331] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_58_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_59_we = addr_hit[332] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_59_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_60_we = addr_hit[333] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_60_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_61_we = addr_hit[334] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_61_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_62_we = addr_hit[335] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_62_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_63_we = addr_hit[336] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_63_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_64_we = addr_hit[337] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_64_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_65_we = addr_hit[338] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_65_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_66_we = addr_hit[339] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_66_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_67_we = addr_hit[340] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_67_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_68_we = addr_hit[341] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_68_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_69_we = addr_hit[342] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_69_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_70_we = addr_hit[343] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_70_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_71_we = addr_hit[344] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_71_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_72_we = addr_hit[345] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_72_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_73_we = addr_hit[346] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_73_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_74_we = addr_hit[347] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_74_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_75_we = addr_hit[348] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_75_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_76_we = addr_hit[349] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_76_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_77_we = addr_hit[350] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_77_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_78_we = addr_hit[351] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_78_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_79_we = addr_hit[352] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_79_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_80_we = addr_hit[353] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_80_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_81_we = addr_hit[354] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_81_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_82_we = addr_hit[355] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_82_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_83_we = addr_hit[356] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_83_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_84_we = addr_hit[357] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_84_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_85_we = addr_hit[358] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_85_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_86_we = addr_hit[359] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_86_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_87_we = addr_hit[360] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_87_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_88_we = addr_hit[361] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_88_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_89_we = addr_hit[362] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_89_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_90_we = addr_hit[363] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_90_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_91_we = addr_hit[364] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_91_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_92_we = addr_hit[365] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_92_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_93_we = addr_hit[366] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_93_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_94_we = addr_hit[367] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_94_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_95_we = addr_hit[368] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_95_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_96_we = addr_hit[369] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_96_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_97_we = addr_hit[370] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_97_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_98_we = addr_hit[371] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_98_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_99_we = addr_hit[372] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_99_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_100_we = addr_hit[373] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_100_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_101_we = addr_hit[374] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_101_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_102_we = addr_hit[375] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_102_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_103_we = addr_hit[376] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_103_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_104_we = addr_hit[377] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_104_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_105_we = addr_hit[378] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_105_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_106_we = addr_hit[379] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_106_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_107_we = addr_hit[380] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_107_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_108_we = addr_hit[381] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_108_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_109_we = addr_hit[382] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_109_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_110_we = addr_hit[383] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_110_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_111_we = addr_hit[384] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_111_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_112_we = addr_hit[385] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_112_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_113_we = addr_hit[386] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_113_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_114_we = addr_hit[387] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_114_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_115_we = addr_hit[388] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_115_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_116_we = addr_hit[389] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_116_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_117_we = addr_hit[390] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_117_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_118_we = addr_hit[391] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_118_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_119_we = addr_hit[392] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_119_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_120_we = addr_hit[393] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_120_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_121_we = addr_hit[394] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_121_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_122_we = addr_hit[395] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_122_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_123_we = addr_hit[396] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_123_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_124_we = addr_hit[397] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_124_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_125_we = addr_hit[398] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_125_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_126_we = addr_hit[399] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_126_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_127_we = addr_hit[400] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_127_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_128_we = addr_hit[401] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_128_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_129_we = addr_hit[402] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_129_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_130_we = addr_hit[403] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_130_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_131_we = addr_hit[404] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_131_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_132_we = addr_hit[405] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_132_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_133_we = addr_hit[406] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_133_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_134_we = addr_hit[407] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_134_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_135_we = addr_hit[408] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_135_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_136_we = addr_hit[409] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_136_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_137_we = addr_hit[410] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_137_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_138_we = addr_hit[411] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_138_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_139_we = addr_hit[412] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_139_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_140_we = addr_hit[413] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_140_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_141_we = addr_hit[414] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_141_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_142_we = addr_hit[415] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_142_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_143_we = addr_hit[416] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_143_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_144_we = addr_hit[417] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_144_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_145_we = addr_hit[418] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_145_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_146_we = addr_hit[419] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_146_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_147_we = addr_hit[420] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_147_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_148_we = addr_hit[421] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_148_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_149_we = addr_hit[422] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_149_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_150_we = addr_hit[423] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_150_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_151_we = addr_hit[424] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_151_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_152_we = addr_hit[425] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_152_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_153_we = addr_hit[426] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_153_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_154_we = addr_hit[427] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_154_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_155_we = addr_hit[428] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_155_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_156_we = addr_hit[429] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_156_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_157_we = addr_hit[430] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_157_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_158_we = addr_hit[431] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_158_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_159_we = addr_hit[432] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_159_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_160_we = addr_hit[433] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_160_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_161_we = addr_hit[434] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_161_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_162_we = addr_hit[435] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_162_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_163_we = addr_hit[436] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_163_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_164_we = addr_hit[437] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_164_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_165_we = addr_hit[438] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_165_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_166_we = addr_hit[439] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_166_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_167_we = addr_hit[440] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_167_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_168_we = addr_hit[441] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_168_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_169_we = addr_hit[442] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_169_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_170_we = addr_hit[443] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_170_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_171_we = addr_hit[444] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_171_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_172_we = addr_hit[445] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_172_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_173_we = addr_hit[446] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_173_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_174_we = addr_hit[447] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_174_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_175_we = addr_hit[448] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_175_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_176_we = addr_hit[449] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_176_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_177_we = addr_hit[450] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_177_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_178_we = addr_hit[451] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_178_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_179_we = addr_hit[452] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_179_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_180_we = addr_hit[453] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_180_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_181_we = addr_hit[454] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_181_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_182_we = addr_hit[455] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_182_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_183_we = addr_hit[456] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_183_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_184_we = addr_hit[457] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_184_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_185_we = addr_hit[458] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_185_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_186_we = addr_hit[459] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_186_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_187_we = addr_hit[460] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_187_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_188_we = addr_hit[461] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_188_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_189_we = addr_hit[462] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_189_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_190_we = addr_hit[463] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_190_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_191_we = addr_hit[464] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_191_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_192_we = addr_hit[465] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_192_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_193_we = addr_hit[466] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_193_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_194_we = addr_hit[467] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_194_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_195_we = addr_hit[468] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_195_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_196_we = addr_hit[469] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_196_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_197_we = addr_hit[470] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_197_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_198_we = addr_hit[471] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_198_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_199_we = addr_hit[472] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_199_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_200_we = addr_hit[473] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_200_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_201_we = addr_hit[474] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_201_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_202_we = addr_hit[475] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_202_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_203_we = addr_hit[476] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_203_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_204_we = addr_hit[477] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_204_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_205_we = addr_hit[478] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_205_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_206_we = addr_hit[479] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_206_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_207_we = addr_hit[480] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_207_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_208_we = addr_hit[481] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_208_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_209_we = addr_hit[482] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_209_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_210_we = addr_hit[483] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_210_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_211_we = addr_hit[484] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_211_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_212_we = addr_hit[485] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_212_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_213_we = addr_hit[486] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_213_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_214_we = addr_hit[487] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_214_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_215_we = addr_hit[488] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_215_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_216_we = addr_hit[489] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_216_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_217_we = addr_hit[490] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_217_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_218_we = addr_hit[491] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_218_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_219_we = addr_hit[492] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_219_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_220_we = addr_hit[493] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_220_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_221_we = addr_hit[494] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_221_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_222_we = addr_hit[495] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_222_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_223_we = addr_hit[496] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_223_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_224_we = addr_hit[497] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_224_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_225_we = addr_hit[498] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_225_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_226_we = addr_hit[499] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_226_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_227_we = addr_hit[500] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_227_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_228_we = addr_hit[501] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_228_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_229_we = addr_hit[502] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_229_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_230_we = addr_hit[503] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_230_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_231_we = addr_hit[504] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_231_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_232_we = addr_hit[505] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_232_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_233_we = addr_hit[506] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_233_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_234_we = addr_hit[507] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_234_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_235_we = addr_hit[508] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_235_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_236_we = addr_hit[509] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_236_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_237_we = addr_hit[510] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_237_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_238_we = addr_hit[511] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_238_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_239_we = addr_hit[512] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_239_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_240_we = addr_hit[513] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_240_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_241_we = addr_hit[514] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_241_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_242_we = addr_hit[515] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_242_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_243_we = addr_hit[516] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_243_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_244_we = addr_hit[517] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_244_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_245_we = addr_hit[518] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_245_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_246_we = addr_hit[519] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_246_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_247_we = addr_hit[520] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_247_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_248_we = addr_hit[521] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_248_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_249_we = addr_hit[522] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_249_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_250_we = addr_hit[523] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_250_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_251_we = addr_hit[524] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_251_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_252_we = addr_hit[525] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_252_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_253_we = addr_hit[526] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_253_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_254_we = addr_hit[527] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_254_wd = reg_wdata[31:0]; + + assign cfg_lp1_cmo_addr_255_we = addr_hit[528] & reg_we & !reg_error; + assign cfg_lp1_cmo_addr_255_wd = reg_wdata[31:0]; + + assign lp1_cmo_commit_0_we = addr_hit[529] & reg_we & !reg_error; + assign lp1_cmo_commit_0_wd = reg_wdata[0]; + + assign lp1_cmo_commit_1_we = addr_hit[530] & reg_we & !reg_error; + assign lp1_cmo_commit_1_wd = reg_wdata[0]; + + assign lp1_cmo_commit_2_we = addr_hit[531] & reg_we & !reg_error; + assign lp1_cmo_commit_2_wd = reg_wdata[0]; + + assign lp1_cmo_commit_3_we = addr_hit[532] & reg_we & !reg_error; + assign lp1_cmo_commit_3_wd = reg_wdata[0]; + + assign lp1_cmo_commit_4_we = addr_hit[533] & reg_we & !reg_error; + assign lp1_cmo_commit_4_wd = reg_wdata[0]; + + assign lp1_cmo_commit_5_we = addr_hit[534] & reg_we & !reg_error; + assign lp1_cmo_commit_5_wd = reg_wdata[0]; + + assign lp1_cmo_commit_6_we = addr_hit[535] & reg_we & !reg_error; + assign lp1_cmo_commit_6_wd = reg_wdata[0]; + + assign lp1_cmo_commit_7_we = addr_hit[536] & reg_we & !reg_error; + assign lp1_cmo_commit_7_wd = reg_wdata[0]; + + assign lp1_cmo_commit_8_we = addr_hit[537] & reg_we & !reg_error; + assign lp1_cmo_commit_8_wd = reg_wdata[0]; + + assign lp1_cmo_commit_9_we = addr_hit[538] & reg_we & !reg_error; + assign lp1_cmo_commit_9_wd = reg_wdata[0]; + + assign lp1_cmo_commit_10_we = addr_hit[539] & reg_we & !reg_error; + assign lp1_cmo_commit_10_wd = reg_wdata[0]; + + assign lp1_cmo_commit_11_we = addr_hit[540] & reg_we & !reg_error; + assign lp1_cmo_commit_11_wd = reg_wdata[0]; + + assign lp1_cmo_commit_12_we = addr_hit[541] & reg_we & !reg_error; + assign lp1_cmo_commit_12_wd = reg_wdata[0]; + + assign lp1_cmo_commit_13_we = addr_hit[542] & reg_we & !reg_error; + assign lp1_cmo_commit_13_wd = reg_wdata[0]; + + assign lp1_cmo_commit_14_we = addr_hit[543] & reg_we & !reg_error; + assign lp1_cmo_commit_14_wd = reg_wdata[0]; + + assign lp1_cmo_commit_15_we = addr_hit[544] & reg_we & !reg_error; + assign lp1_cmo_commit_15_wd = reg_wdata[0]; + + assign lp1_cmo_commit_16_we = addr_hit[545] & reg_we & !reg_error; + assign lp1_cmo_commit_16_wd = reg_wdata[0]; + + assign lp1_cmo_commit_17_we = addr_hit[546] & reg_we & !reg_error; + assign lp1_cmo_commit_17_wd = reg_wdata[0]; + + assign lp1_cmo_commit_18_we = addr_hit[547] & reg_we & !reg_error; + assign lp1_cmo_commit_18_wd = reg_wdata[0]; + + assign lp1_cmo_commit_19_we = addr_hit[548] & reg_we & !reg_error; + assign lp1_cmo_commit_19_wd = reg_wdata[0]; + + assign lp1_cmo_commit_20_we = addr_hit[549] & reg_we & !reg_error; + assign lp1_cmo_commit_20_wd = reg_wdata[0]; + + assign lp1_cmo_commit_21_we = addr_hit[550] & reg_we & !reg_error; + assign lp1_cmo_commit_21_wd = reg_wdata[0]; + + assign lp1_cmo_commit_22_we = addr_hit[551] & reg_we & !reg_error; + assign lp1_cmo_commit_22_wd = reg_wdata[0]; + + assign lp1_cmo_commit_23_we = addr_hit[552] & reg_we & !reg_error; + assign lp1_cmo_commit_23_wd = reg_wdata[0]; + + assign lp1_cmo_commit_24_we = addr_hit[553] & reg_we & !reg_error; + assign lp1_cmo_commit_24_wd = reg_wdata[0]; + + assign lp1_cmo_commit_25_we = addr_hit[554] & reg_we & !reg_error; + assign lp1_cmo_commit_25_wd = reg_wdata[0]; + + assign lp1_cmo_commit_26_we = addr_hit[555] & reg_we & !reg_error; + assign lp1_cmo_commit_26_wd = reg_wdata[0]; + + assign lp1_cmo_commit_27_we = addr_hit[556] & reg_we & !reg_error; + assign lp1_cmo_commit_27_wd = reg_wdata[0]; + + assign lp1_cmo_commit_28_we = addr_hit[557] & reg_we & !reg_error; + assign lp1_cmo_commit_28_wd = reg_wdata[0]; + + assign lp1_cmo_commit_29_we = addr_hit[558] & reg_we & !reg_error; + assign lp1_cmo_commit_29_wd = reg_wdata[0]; + + assign lp1_cmo_commit_30_we = addr_hit[559] & reg_we & !reg_error; + assign lp1_cmo_commit_30_wd = reg_wdata[0]; + + assign lp1_cmo_commit_31_we = addr_hit[560] & reg_we & !reg_error; + assign lp1_cmo_commit_31_wd = reg_wdata[0]; + + assign lp1_cmo_commit_32_we = addr_hit[561] & reg_we & !reg_error; + assign lp1_cmo_commit_32_wd = reg_wdata[0]; + + assign lp1_cmo_commit_33_we = addr_hit[562] & reg_we & !reg_error; + assign lp1_cmo_commit_33_wd = reg_wdata[0]; + + assign lp1_cmo_commit_34_we = addr_hit[563] & reg_we & !reg_error; + assign lp1_cmo_commit_34_wd = reg_wdata[0]; + + assign lp1_cmo_commit_35_we = addr_hit[564] & reg_we & !reg_error; + assign lp1_cmo_commit_35_wd = reg_wdata[0]; + + assign lp1_cmo_commit_36_we = addr_hit[565] & reg_we & !reg_error; + assign lp1_cmo_commit_36_wd = reg_wdata[0]; + + assign lp1_cmo_commit_37_we = addr_hit[566] & reg_we & !reg_error; + assign lp1_cmo_commit_37_wd = reg_wdata[0]; + + assign lp1_cmo_commit_38_we = addr_hit[567] & reg_we & !reg_error; + assign lp1_cmo_commit_38_wd = reg_wdata[0]; + + assign lp1_cmo_commit_39_we = addr_hit[568] & reg_we & !reg_error; + assign lp1_cmo_commit_39_wd = reg_wdata[0]; + + assign lp1_cmo_commit_40_we = addr_hit[569] & reg_we & !reg_error; + assign lp1_cmo_commit_40_wd = reg_wdata[0]; + + assign lp1_cmo_commit_41_we = addr_hit[570] & reg_we & !reg_error; + assign lp1_cmo_commit_41_wd = reg_wdata[0]; + + assign lp1_cmo_commit_42_we = addr_hit[571] & reg_we & !reg_error; + assign lp1_cmo_commit_42_wd = reg_wdata[0]; + + assign lp1_cmo_commit_43_we = addr_hit[572] & reg_we & !reg_error; + assign lp1_cmo_commit_43_wd = reg_wdata[0]; + + assign lp1_cmo_commit_44_we = addr_hit[573] & reg_we & !reg_error; + assign lp1_cmo_commit_44_wd = reg_wdata[0]; + + assign lp1_cmo_commit_45_we = addr_hit[574] & reg_we & !reg_error; + assign lp1_cmo_commit_45_wd = reg_wdata[0]; + + assign lp1_cmo_commit_46_we = addr_hit[575] & reg_we & !reg_error; + assign lp1_cmo_commit_46_wd = reg_wdata[0]; + + assign lp1_cmo_commit_47_we = addr_hit[576] & reg_we & !reg_error; + assign lp1_cmo_commit_47_wd = reg_wdata[0]; + + assign lp1_cmo_commit_48_we = addr_hit[577] & reg_we & !reg_error; + assign lp1_cmo_commit_48_wd = reg_wdata[0]; + + assign lp1_cmo_commit_49_we = addr_hit[578] & reg_we & !reg_error; + assign lp1_cmo_commit_49_wd = reg_wdata[0]; + + assign lp1_cmo_commit_50_we = addr_hit[579] & reg_we & !reg_error; + assign lp1_cmo_commit_50_wd = reg_wdata[0]; + + assign lp1_cmo_commit_51_we = addr_hit[580] & reg_we & !reg_error; + assign lp1_cmo_commit_51_wd = reg_wdata[0]; + + assign lp1_cmo_commit_52_we = addr_hit[581] & reg_we & !reg_error; + assign lp1_cmo_commit_52_wd = reg_wdata[0]; + + assign lp1_cmo_commit_53_we = addr_hit[582] & reg_we & !reg_error; + assign lp1_cmo_commit_53_wd = reg_wdata[0]; + + assign lp1_cmo_commit_54_we = addr_hit[583] & reg_we & !reg_error; + assign lp1_cmo_commit_54_wd = reg_wdata[0]; + + assign lp1_cmo_commit_55_we = addr_hit[584] & reg_we & !reg_error; + assign lp1_cmo_commit_55_wd = reg_wdata[0]; + + assign lp1_cmo_commit_56_we = addr_hit[585] & reg_we & !reg_error; + assign lp1_cmo_commit_56_wd = reg_wdata[0]; + + assign lp1_cmo_commit_57_we = addr_hit[586] & reg_we & !reg_error; + assign lp1_cmo_commit_57_wd = reg_wdata[0]; + + assign lp1_cmo_commit_58_we = addr_hit[587] & reg_we & !reg_error; + assign lp1_cmo_commit_58_wd = reg_wdata[0]; + + assign lp1_cmo_commit_59_we = addr_hit[588] & reg_we & !reg_error; + assign lp1_cmo_commit_59_wd = reg_wdata[0]; + + assign lp1_cmo_commit_60_we = addr_hit[589] & reg_we & !reg_error; + assign lp1_cmo_commit_60_wd = reg_wdata[0]; + + assign lp1_cmo_commit_61_we = addr_hit[590] & reg_we & !reg_error; + assign lp1_cmo_commit_61_wd = reg_wdata[0]; + + assign lp1_cmo_commit_62_we = addr_hit[591] & reg_we & !reg_error; + assign lp1_cmo_commit_62_wd = reg_wdata[0]; + + assign lp1_cmo_commit_63_we = addr_hit[592] & reg_we & !reg_error; + assign lp1_cmo_commit_63_wd = reg_wdata[0]; + + assign lp1_cmo_commit_64_we = addr_hit[593] & reg_we & !reg_error; + assign lp1_cmo_commit_64_wd = reg_wdata[0]; + + assign lp1_cmo_commit_65_we = addr_hit[594] & reg_we & !reg_error; + assign lp1_cmo_commit_65_wd = reg_wdata[0]; + + assign lp1_cmo_commit_66_we = addr_hit[595] & reg_we & !reg_error; + assign lp1_cmo_commit_66_wd = reg_wdata[0]; + + assign lp1_cmo_commit_67_we = addr_hit[596] & reg_we & !reg_error; + assign lp1_cmo_commit_67_wd = reg_wdata[0]; + + assign lp1_cmo_commit_68_we = addr_hit[597] & reg_we & !reg_error; + assign lp1_cmo_commit_68_wd = reg_wdata[0]; + + assign lp1_cmo_commit_69_we = addr_hit[598] & reg_we & !reg_error; + assign lp1_cmo_commit_69_wd = reg_wdata[0]; + + assign lp1_cmo_commit_70_we = addr_hit[599] & reg_we & !reg_error; + assign lp1_cmo_commit_70_wd = reg_wdata[0]; + + assign lp1_cmo_commit_71_we = addr_hit[600] & reg_we & !reg_error; + assign lp1_cmo_commit_71_wd = reg_wdata[0]; + + assign lp1_cmo_commit_72_we = addr_hit[601] & reg_we & !reg_error; + assign lp1_cmo_commit_72_wd = reg_wdata[0]; + + assign lp1_cmo_commit_73_we = addr_hit[602] & reg_we & !reg_error; + assign lp1_cmo_commit_73_wd = reg_wdata[0]; + + assign lp1_cmo_commit_74_we = addr_hit[603] & reg_we & !reg_error; + assign lp1_cmo_commit_74_wd = reg_wdata[0]; + + assign lp1_cmo_commit_75_we = addr_hit[604] & reg_we & !reg_error; + assign lp1_cmo_commit_75_wd = reg_wdata[0]; + + assign lp1_cmo_commit_76_we = addr_hit[605] & reg_we & !reg_error; + assign lp1_cmo_commit_76_wd = reg_wdata[0]; + + assign lp1_cmo_commit_77_we = addr_hit[606] & reg_we & !reg_error; + assign lp1_cmo_commit_77_wd = reg_wdata[0]; + + assign lp1_cmo_commit_78_we = addr_hit[607] & reg_we & !reg_error; + assign lp1_cmo_commit_78_wd = reg_wdata[0]; + + assign lp1_cmo_commit_79_we = addr_hit[608] & reg_we & !reg_error; + assign lp1_cmo_commit_79_wd = reg_wdata[0]; + + assign lp1_cmo_commit_80_we = addr_hit[609] & reg_we & !reg_error; + assign lp1_cmo_commit_80_wd = reg_wdata[0]; + + assign lp1_cmo_commit_81_we = addr_hit[610] & reg_we & !reg_error; + assign lp1_cmo_commit_81_wd = reg_wdata[0]; + + assign lp1_cmo_commit_82_we = addr_hit[611] & reg_we & !reg_error; + assign lp1_cmo_commit_82_wd = reg_wdata[0]; + + assign lp1_cmo_commit_83_we = addr_hit[612] & reg_we & !reg_error; + assign lp1_cmo_commit_83_wd = reg_wdata[0]; + + assign lp1_cmo_commit_84_we = addr_hit[613] & reg_we & !reg_error; + assign lp1_cmo_commit_84_wd = reg_wdata[0]; + + assign lp1_cmo_commit_85_we = addr_hit[614] & reg_we & !reg_error; + assign lp1_cmo_commit_85_wd = reg_wdata[0]; + + assign lp1_cmo_commit_86_we = addr_hit[615] & reg_we & !reg_error; + assign lp1_cmo_commit_86_wd = reg_wdata[0]; + + assign lp1_cmo_commit_87_we = addr_hit[616] & reg_we & !reg_error; + assign lp1_cmo_commit_87_wd = reg_wdata[0]; + + assign lp1_cmo_commit_88_we = addr_hit[617] & reg_we & !reg_error; + assign lp1_cmo_commit_88_wd = reg_wdata[0]; + + assign lp1_cmo_commit_89_we = addr_hit[618] & reg_we & !reg_error; + assign lp1_cmo_commit_89_wd = reg_wdata[0]; + + assign lp1_cmo_commit_90_we = addr_hit[619] & reg_we & !reg_error; + assign lp1_cmo_commit_90_wd = reg_wdata[0]; + + assign lp1_cmo_commit_91_we = addr_hit[620] & reg_we & !reg_error; + assign lp1_cmo_commit_91_wd = reg_wdata[0]; + + assign lp1_cmo_commit_92_we = addr_hit[621] & reg_we & !reg_error; + assign lp1_cmo_commit_92_wd = reg_wdata[0]; + + assign lp1_cmo_commit_93_we = addr_hit[622] & reg_we & !reg_error; + assign lp1_cmo_commit_93_wd = reg_wdata[0]; + + assign lp1_cmo_commit_94_we = addr_hit[623] & reg_we & !reg_error; + assign lp1_cmo_commit_94_wd = reg_wdata[0]; + + assign lp1_cmo_commit_95_we = addr_hit[624] & reg_we & !reg_error; + assign lp1_cmo_commit_95_wd = reg_wdata[0]; + + assign lp1_cmo_commit_96_we = addr_hit[625] & reg_we & !reg_error; + assign lp1_cmo_commit_96_wd = reg_wdata[0]; + + assign lp1_cmo_commit_97_we = addr_hit[626] & reg_we & !reg_error; + assign lp1_cmo_commit_97_wd = reg_wdata[0]; + + assign lp1_cmo_commit_98_we = addr_hit[627] & reg_we & !reg_error; + assign lp1_cmo_commit_98_wd = reg_wdata[0]; + + assign lp1_cmo_commit_99_we = addr_hit[628] & reg_we & !reg_error; + assign lp1_cmo_commit_99_wd = reg_wdata[0]; + + assign lp1_cmo_commit_100_we = addr_hit[629] & reg_we & !reg_error; + assign lp1_cmo_commit_100_wd = reg_wdata[0]; + + assign lp1_cmo_commit_101_we = addr_hit[630] & reg_we & !reg_error; + assign lp1_cmo_commit_101_wd = reg_wdata[0]; + + assign lp1_cmo_commit_102_we = addr_hit[631] & reg_we & !reg_error; + assign lp1_cmo_commit_102_wd = reg_wdata[0]; + + assign lp1_cmo_commit_103_we = addr_hit[632] & reg_we & !reg_error; + assign lp1_cmo_commit_103_wd = reg_wdata[0]; + + assign lp1_cmo_commit_104_we = addr_hit[633] & reg_we & !reg_error; + assign lp1_cmo_commit_104_wd = reg_wdata[0]; + + assign lp1_cmo_commit_105_we = addr_hit[634] & reg_we & !reg_error; + assign lp1_cmo_commit_105_wd = reg_wdata[0]; + + assign lp1_cmo_commit_106_we = addr_hit[635] & reg_we & !reg_error; + assign lp1_cmo_commit_106_wd = reg_wdata[0]; + + assign lp1_cmo_commit_107_we = addr_hit[636] & reg_we & !reg_error; + assign lp1_cmo_commit_107_wd = reg_wdata[0]; + + assign lp1_cmo_commit_108_we = addr_hit[637] & reg_we & !reg_error; + assign lp1_cmo_commit_108_wd = reg_wdata[0]; + + assign lp1_cmo_commit_109_we = addr_hit[638] & reg_we & !reg_error; + assign lp1_cmo_commit_109_wd = reg_wdata[0]; + + assign lp1_cmo_commit_110_we = addr_hit[639] & reg_we & !reg_error; + assign lp1_cmo_commit_110_wd = reg_wdata[0]; + + assign lp1_cmo_commit_111_we = addr_hit[640] & reg_we & !reg_error; + assign lp1_cmo_commit_111_wd = reg_wdata[0]; + + assign lp1_cmo_commit_112_we = addr_hit[641] & reg_we & !reg_error; + assign lp1_cmo_commit_112_wd = reg_wdata[0]; + + assign lp1_cmo_commit_113_we = addr_hit[642] & reg_we & !reg_error; + assign lp1_cmo_commit_113_wd = reg_wdata[0]; + + assign lp1_cmo_commit_114_we = addr_hit[643] & reg_we & !reg_error; + assign lp1_cmo_commit_114_wd = reg_wdata[0]; + + assign lp1_cmo_commit_115_we = addr_hit[644] & reg_we & !reg_error; + assign lp1_cmo_commit_115_wd = reg_wdata[0]; + + assign lp1_cmo_commit_116_we = addr_hit[645] & reg_we & !reg_error; + assign lp1_cmo_commit_116_wd = reg_wdata[0]; + + assign lp1_cmo_commit_117_we = addr_hit[646] & reg_we & !reg_error; + assign lp1_cmo_commit_117_wd = reg_wdata[0]; + + assign lp1_cmo_commit_118_we = addr_hit[647] & reg_we & !reg_error; + assign lp1_cmo_commit_118_wd = reg_wdata[0]; + + assign lp1_cmo_commit_119_we = addr_hit[648] & reg_we & !reg_error; + assign lp1_cmo_commit_119_wd = reg_wdata[0]; + + assign lp1_cmo_commit_120_we = addr_hit[649] & reg_we & !reg_error; + assign lp1_cmo_commit_120_wd = reg_wdata[0]; + + assign lp1_cmo_commit_121_we = addr_hit[650] & reg_we & !reg_error; + assign lp1_cmo_commit_121_wd = reg_wdata[0]; + + assign lp1_cmo_commit_122_we = addr_hit[651] & reg_we & !reg_error; + assign lp1_cmo_commit_122_wd = reg_wdata[0]; + + assign lp1_cmo_commit_123_we = addr_hit[652] & reg_we & !reg_error; + assign lp1_cmo_commit_123_wd = reg_wdata[0]; + + assign lp1_cmo_commit_124_we = addr_hit[653] & reg_we & !reg_error; + assign lp1_cmo_commit_124_wd = reg_wdata[0]; + + assign lp1_cmo_commit_125_we = addr_hit[654] & reg_we & !reg_error; + assign lp1_cmo_commit_125_wd = reg_wdata[0]; + + assign lp1_cmo_commit_126_we = addr_hit[655] & reg_we & !reg_error; + assign lp1_cmo_commit_126_wd = reg_wdata[0]; + + assign lp1_cmo_commit_127_we = addr_hit[656] & reg_we & !reg_error; + assign lp1_cmo_commit_127_wd = reg_wdata[0]; + + assign lp1_cmo_commit_128_we = addr_hit[657] & reg_we & !reg_error; + assign lp1_cmo_commit_128_wd = reg_wdata[0]; + + assign lp1_cmo_commit_129_we = addr_hit[658] & reg_we & !reg_error; + assign lp1_cmo_commit_129_wd = reg_wdata[0]; + + assign lp1_cmo_commit_130_we = addr_hit[659] & reg_we & !reg_error; + assign lp1_cmo_commit_130_wd = reg_wdata[0]; + + assign lp1_cmo_commit_131_we = addr_hit[660] & reg_we & !reg_error; + assign lp1_cmo_commit_131_wd = reg_wdata[0]; + + assign lp1_cmo_commit_132_we = addr_hit[661] & reg_we & !reg_error; + assign lp1_cmo_commit_132_wd = reg_wdata[0]; + + assign lp1_cmo_commit_133_we = addr_hit[662] & reg_we & !reg_error; + assign lp1_cmo_commit_133_wd = reg_wdata[0]; + + assign lp1_cmo_commit_134_we = addr_hit[663] & reg_we & !reg_error; + assign lp1_cmo_commit_134_wd = reg_wdata[0]; + + assign lp1_cmo_commit_135_we = addr_hit[664] & reg_we & !reg_error; + assign lp1_cmo_commit_135_wd = reg_wdata[0]; + + assign lp1_cmo_commit_136_we = addr_hit[665] & reg_we & !reg_error; + assign lp1_cmo_commit_136_wd = reg_wdata[0]; + + assign lp1_cmo_commit_137_we = addr_hit[666] & reg_we & !reg_error; + assign lp1_cmo_commit_137_wd = reg_wdata[0]; + + assign lp1_cmo_commit_138_we = addr_hit[667] & reg_we & !reg_error; + assign lp1_cmo_commit_138_wd = reg_wdata[0]; + + assign lp1_cmo_commit_139_we = addr_hit[668] & reg_we & !reg_error; + assign lp1_cmo_commit_139_wd = reg_wdata[0]; + + assign lp1_cmo_commit_140_we = addr_hit[669] & reg_we & !reg_error; + assign lp1_cmo_commit_140_wd = reg_wdata[0]; + + assign lp1_cmo_commit_141_we = addr_hit[670] & reg_we & !reg_error; + assign lp1_cmo_commit_141_wd = reg_wdata[0]; + + assign lp1_cmo_commit_142_we = addr_hit[671] & reg_we & !reg_error; + assign lp1_cmo_commit_142_wd = reg_wdata[0]; + + assign lp1_cmo_commit_143_we = addr_hit[672] & reg_we & !reg_error; + assign lp1_cmo_commit_143_wd = reg_wdata[0]; + + assign lp1_cmo_commit_144_we = addr_hit[673] & reg_we & !reg_error; + assign lp1_cmo_commit_144_wd = reg_wdata[0]; + + assign lp1_cmo_commit_145_we = addr_hit[674] & reg_we & !reg_error; + assign lp1_cmo_commit_145_wd = reg_wdata[0]; + + assign lp1_cmo_commit_146_we = addr_hit[675] & reg_we & !reg_error; + assign lp1_cmo_commit_146_wd = reg_wdata[0]; + + assign lp1_cmo_commit_147_we = addr_hit[676] & reg_we & !reg_error; + assign lp1_cmo_commit_147_wd = reg_wdata[0]; + + assign lp1_cmo_commit_148_we = addr_hit[677] & reg_we & !reg_error; + assign lp1_cmo_commit_148_wd = reg_wdata[0]; + + assign lp1_cmo_commit_149_we = addr_hit[678] & reg_we & !reg_error; + assign lp1_cmo_commit_149_wd = reg_wdata[0]; + + assign lp1_cmo_commit_150_we = addr_hit[679] & reg_we & !reg_error; + assign lp1_cmo_commit_150_wd = reg_wdata[0]; + + assign lp1_cmo_commit_151_we = addr_hit[680] & reg_we & !reg_error; + assign lp1_cmo_commit_151_wd = reg_wdata[0]; + + assign lp1_cmo_commit_152_we = addr_hit[681] & reg_we & !reg_error; + assign lp1_cmo_commit_152_wd = reg_wdata[0]; + + assign lp1_cmo_commit_153_we = addr_hit[682] & reg_we & !reg_error; + assign lp1_cmo_commit_153_wd = reg_wdata[0]; + + assign lp1_cmo_commit_154_we = addr_hit[683] & reg_we & !reg_error; + assign lp1_cmo_commit_154_wd = reg_wdata[0]; + + assign lp1_cmo_commit_155_we = addr_hit[684] & reg_we & !reg_error; + assign lp1_cmo_commit_155_wd = reg_wdata[0]; + + assign lp1_cmo_commit_156_we = addr_hit[685] & reg_we & !reg_error; + assign lp1_cmo_commit_156_wd = reg_wdata[0]; + + assign lp1_cmo_commit_157_we = addr_hit[686] & reg_we & !reg_error; + assign lp1_cmo_commit_157_wd = reg_wdata[0]; + + assign lp1_cmo_commit_158_we = addr_hit[687] & reg_we & !reg_error; + assign lp1_cmo_commit_158_wd = reg_wdata[0]; + + assign lp1_cmo_commit_159_we = addr_hit[688] & reg_we & !reg_error; + assign lp1_cmo_commit_159_wd = reg_wdata[0]; + + assign lp1_cmo_commit_160_we = addr_hit[689] & reg_we & !reg_error; + assign lp1_cmo_commit_160_wd = reg_wdata[0]; + + assign lp1_cmo_commit_161_we = addr_hit[690] & reg_we & !reg_error; + assign lp1_cmo_commit_161_wd = reg_wdata[0]; + + assign lp1_cmo_commit_162_we = addr_hit[691] & reg_we & !reg_error; + assign lp1_cmo_commit_162_wd = reg_wdata[0]; + + assign lp1_cmo_commit_163_we = addr_hit[692] & reg_we & !reg_error; + assign lp1_cmo_commit_163_wd = reg_wdata[0]; + + assign lp1_cmo_commit_164_we = addr_hit[693] & reg_we & !reg_error; + assign lp1_cmo_commit_164_wd = reg_wdata[0]; + + assign lp1_cmo_commit_165_we = addr_hit[694] & reg_we & !reg_error; + assign lp1_cmo_commit_165_wd = reg_wdata[0]; + + assign lp1_cmo_commit_166_we = addr_hit[695] & reg_we & !reg_error; + assign lp1_cmo_commit_166_wd = reg_wdata[0]; + + assign lp1_cmo_commit_167_we = addr_hit[696] & reg_we & !reg_error; + assign lp1_cmo_commit_167_wd = reg_wdata[0]; + + assign lp1_cmo_commit_168_we = addr_hit[697] & reg_we & !reg_error; + assign lp1_cmo_commit_168_wd = reg_wdata[0]; + + assign lp1_cmo_commit_169_we = addr_hit[698] & reg_we & !reg_error; + assign lp1_cmo_commit_169_wd = reg_wdata[0]; + + assign lp1_cmo_commit_170_we = addr_hit[699] & reg_we & !reg_error; + assign lp1_cmo_commit_170_wd = reg_wdata[0]; + + assign lp1_cmo_commit_171_we = addr_hit[700] & reg_we & !reg_error; + assign lp1_cmo_commit_171_wd = reg_wdata[0]; + + assign lp1_cmo_commit_172_we = addr_hit[701] & reg_we & !reg_error; + assign lp1_cmo_commit_172_wd = reg_wdata[0]; + + assign lp1_cmo_commit_173_we = addr_hit[702] & reg_we & !reg_error; + assign lp1_cmo_commit_173_wd = reg_wdata[0]; + + assign lp1_cmo_commit_174_we = addr_hit[703] & reg_we & !reg_error; + assign lp1_cmo_commit_174_wd = reg_wdata[0]; + + assign lp1_cmo_commit_175_we = addr_hit[704] & reg_we & !reg_error; + assign lp1_cmo_commit_175_wd = reg_wdata[0]; + + assign lp1_cmo_commit_176_we = addr_hit[705] & reg_we & !reg_error; + assign lp1_cmo_commit_176_wd = reg_wdata[0]; + + assign lp1_cmo_commit_177_we = addr_hit[706] & reg_we & !reg_error; + assign lp1_cmo_commit_177_wd = reg_wdata[0]; + + assign lp1_cmo_commit_178_we = addr_hit[707] & reg_we & !reg_error; + assign lp1_cmo_commit_178_wd = reg_wdata[0]; + + assign lp1_cmo_commit_179_we = addr_hit[708] & reg_we & !reg_error; + assign lp1_cmo_commit_179_wd = reg_wdata[0]; + + assign lp1_cmo_commit_180_we = addr_hit[709] & reg_we & !reg_error; + assign lp1_cmo_commit_180_wd = reg_wdata[0]; + + assign lp1_cmo_commit_181_we = addr_hit[710] & reg_we & !reg_error; + assign lp1_cmo_commit_181_wd = reg_wdata[0]; + + assign lp1_cmo_commit_182_we = addr_hit[711] & reg_we & !reg_error; + assign lp1_cmo_commit_182_wd = reg_wdata[0]; + + assign lp1_cmo_commit_183_we = addr_hit[712] & reg_we & !reg_error; + assign lp1_cmo_commit_183_wd = reg_wdata[0]; + + assign lp1_cmo_commit_184_we = addr_hit[713] & reg_we & !reg_error; + assign lp1_cmo_commit_184_wd = reg_wdata[0]; + + assign lp1_cmo_commit_185_we = addr_hit[714] & reg_we & !reg_error; + assign lp1_cmo_commit_185_wd = reg_wdata[0]; + + assign lp1_cmo_commit_186_we = addr_hit[715] & reg_we & !reg_error; + assign lp1_cmo_commit_186_wd = reg_wdata[0]; + + assign lp1_cmo_commit_187_we = addr_hit[716] & reg_we & !reg_error; + assign lp1_cmo_commit_187_wd = reg_wdata[0]; + + assign lp1_cmo_commit_188_we = addr_hit[717] & reg_we & !reg_error; + assign lp1_cmo_commit_188_wd = reg_wdata[0]; + + assign lp1_cmo_commit_189_we = addr_hit[718] & reg_we & !reg_error; + assign lp1_cmo_commit_189_wd = reg_wdata[0]; + + assign lp1_cmo_commit_190_we = addr_hit[719] & reg_we & !reg_error; + assign lp1_cmo_commit_190_wd = reg_wdata[0]; + + assign lp1_cmo_commit_191_we = addr_hit[720] & reg_we & !reg_error; + assign lp1_cmo_commit_191_wd = reg_wdata[0]; + + assign lp1_cmo_commit_192_we = addr_hit[721] & reg_we & !reg_error; + assign lp1_cmo_commit_192_wd = reg_wdata[0]; + + assign lp1_cmo_commit_193_we = addr_hit[722] & reg_we & !reg_error; + assign lp1_cmo_commit_193_wd = reg_wdata[0]; + + assign lp1_cmo_commit_194_we = addr_hit[723] & reg_we & !reg_error; + assign lp1_cmo_commit_194_wd = reg_wdata[0]; + + assign lp1_cmo_commit_195_we = addr_hit[724] & reg_we & !reg_error; + assign lp1_cmo_commit_195_wd = reg_wdata[0]; + + assign lp1_cmo_commit_196_we = addr_hit[725] & reg_we & !reg_error; + assign lp1_cmo_commit_196_wd = reg_wdata[0]; + + assign lp1_cmo_commit_197_we = addr_hit[726] & reg_we & !reg_error; + assign lp1_cmo_commit_197_wd = reg_wdata[0]; + + assign lp1_cmo_commit_198_we = addr_hit[727] & reg_we & !reg_error; + assign lp1_cmo_commit_198_wd = reg_wdata[0]; + + assign lp1_cmo_commit_199_we = addr_hit[728] & reg_we & !reg_error; + assign lp1_cmo_commit_199_wd = reg_wdata[0]; + + assign lp1_cmo_commit_200_we = addr_hit[729] & reg_we & !reg_error; + assign lp1_cmo_commit_200_wd = reg_wdata[0]; + + assign lp1_cmo_commit_201_we = addr_hit[730] & reg_we & !reg_error; + assign lp1_cmo_commit_201_wd = reg_wdata[0]; + + assign lp1_cmo_commit_202_we = addr_hit[731] & reg_we & !reg_error; + assign lp1_cmo_commit_202_wd = reg_wdata[0]; + + assign lp1_cmo_commit_203_we = addr_hit[732] & reg_we & !reg_error; + assign lp1_cmo_commit_203_wd = reg_wdata[0]; + + assign lp1_cmo_commit_204_we = addr_hit[733] & reg_we & !reg_error; + assign lp1_cmo_commit_204_wd = reg_wdata[0]; + + assign lp1_cmo_commit_205_we = addr_hit[734] & reg_we & !reg_error; + assign lp1_cmo_commit_205_wd = reg_wdata[0]; + + assign lp1_cmo_commit_206_we = addr_hit[735] & reg_we & !reg_error; + assign lp1_cmo_commit_206_wd = reg_wdata[0]; + + assign lp1_cmo_commit_207_we = addr_hit[736] & reg_we & !reg_error; + assign lp1_cmo_commit_207_wd = reg_wdata[0]; + + assign lp1_cmo_commit_208_we = addr_hit[737] & reg_we & !reg_error; + assign lp1_cmo_commit_208_wd = reg_wdata[0]; + + assign lp1_cmo_commit_209_we = addr_hit[738] & reg_we & !reg_error; + assign lp1_cmo_commit_209_wd = reg_wdata[0]; + + assign lp1_cmo_commit_210_we = addr_hit[739] & reg_we & !reg_error; + assign lp1_cmo_commit_210_wd = reg_wdata[0]; + + assign lp1_cmo_commit_211_we = addr_hit[740] & reg_we & !reg_error; + assign lp1_cmo_commit_211_wd = reg_wdata[0]; + + assign lp1_cmo_commit_212_we = addr_hit[741] & reg_we & !reg_error; + assign lp1_cmo_commit_212_wd = reg_wdata[0]; + + assign lp1_cmo_commit_213_we = addr_hit[742] & reg_we & !reg_error; + assign lp1_cmo_commit_213_wd = reg_wdata[0]; + + assign lp1_cmo_commit_214_we = addr_hit[743] & reg_we & !reg_error; + assign lp1_cmo_commit_214_wd = reg_wdata[0]; + + assign lp1_cmo_commit_215_we = addr_hit[744] & reg_we & !reg_error; + assign lp1_cmo_commit_215_wd = reg_wdata[0]; + + assign lp1_cmo_commit_216_we = addr_hit[745] & reg_we & !reg_error; + assign lp1_cmo_commit_216_wd = reg_wdata[0]; + + assign lp1_cmo_commit_217_we = addr_hit[746] & reg_we & !reg_error; + assign lp1_cmo_commit_217_wd = reg_wdata[0]; + + assign lp1_cmo_commit_218_we = addr_hit[747] & reg_we & !reg_error; + assign lp1_cmo_commit_218_wd = reg_wdata[0]; + + assign lp1_cmo_commit_219_we = addr_hit[748] & reg_we & !reg_error; + assign lp1_cmo_commit_219_wd = reg_wdata[0]; + + assign lp1_cmo_commit_220_we = addr_hit[749] & reg_we & !reg_error; + assign lp1_cmo_commit_220_wd = reg_wdata[0]; + + assign lp1_cmo_commit_221_we = addr_hit[750] & reg_we & !reg_error; + assign lp1_cmo_commit_221_wd = reg_wdata[0]; + + assign lp1_cmo_commit_222_we = addr_hit[751] & reg_we & !reg_error; + assign lp1_cmo_commit_222_wd = reg_wdata[0]; + + assign lp1_cmo_commit_223_we = addr_hit[752] & reg_we & !reg_error; + assign lp1_cmo_commit_223_wd = reg_wdata[0]; + + assign lp1_cmo_commit_224_we = addr_hit[753] & reg_we & !reg_error; + assign lp1_cmo_commit_224_wd = reg_wdata[0]; + + assign lp1_cmo_commit_225_we = addr_hit[754] & reg_we & !reg_error; + assign lp1_cmo_commit_225_wd = reg_wdata[0]; + + assign lp1_cmo_commit_226_we = addr_hit[755] & reg_we & !reg_error; + assign lp1_cmo_commit_226_wd = reg_wdata[0]; + + assign lp1_cmo_commit_227_we = addr_hit[756] & reg_we & !reg_error; + assign lp1_cmo_commit_227_wd = reg_wdata[0]; + + assign lp1_cmo_commit_228_we = addr_hit[757] & reg_we & !reg_error; + assign lp1_cmo_commit_228_wd = reg_wdata[0]; + + assign lp1_cmo_commit_229_we = addr_hit[758] & reg_we & !reg_error; + assign lp1_cmo_commit_229_wd = reg_wdata[0]; + + assign lp1_cmo_commit_230_we = addr_hit[759] & reg_we & !reg_error; + assign lp1_cmo_commit_230_wd = reg_wdata[0]; + + assign lp1_cmo_commit_231_we = addr_hit[760] & reg_we & !reg_error; + assign lp1_cmo_commit_231_wd = reg_wdata[0]; + + assign lp1_cmo_commit_232_we = addr_hit[761] & reg_we & !reg_error; + assign lp1_cmo_commit_232_wd = reg_wdata[0]; + + assign lp1_cmo_commit_233_we = addr_hit[762] & reg_we & !reg_error; + assign lp1_cmo_commit_233_wd = reg_wdata[0]; + + assign lp1_cmo_commit_234_we = addr_hit[763] & reg_we & !reg_error; + assign lp1_cmo_commit_234_wd = reg_wdata[0]; + + assign lp1_cmo_commit_235_we = addr_hit[764] & reg_we & !reg_error; + assign lp1_cmo_commit_235_wd = reg_wdata[0]; + + assign lp1_cmo_commit_236_we = addr_hit[765] & reg_we & !reg_error; + assign lp1_cmo_commit_236_wd = reg_wdata[0]; + + assign lp1_cmo_commit_237_we = addr_hit[766] & reg_we & !reg_error; + assign lp1_cmo_commit_237_wd = reg_wdata[0]; + + assign lp1_cmo_commit_238_we = addr_hit[767] & reg_we & !reg_error; + assign lp1_cmo_commit_238_wd = reg_wdata[0]; + + assign lp1_cmo_commit_239_we = addr_hit[768] & reg_we & !reg_error; + assign lp1_cmo_commit_239_wd = reg_wdata[0]; + + assign lp1_cmo_commit_240_we = addr_hit[769] & reg_we & !reg_error; + assign lp1_cmo_commit_240_wd = reg_wdata[0]; + + assign lp1_cmo_commit_241_we = addr_hit[770] & reg_we & !reg_error; + assign lp1_cmo_commit_241_wd = reg_wdata[0]; + + assign lp1_cmo_commit_242_we = addr_hit[771] & reg_we & !reg_error; + assign lp1_cmo_commit_242_wd = reg_wdata[0]; + + assign lp1_cmo_commit_243_we = addr_hit[772] & reg_we & !reg_error; + assign lp1_cmo_commit_243_wd = reg_wdata[0]; + + assign lp1_cmo_commit_244_we = addr_hit[773] & reg_we & !reg_error; + assign lp1_cmo_commit_244_wd = reg_wdata[0]; + + assign lp1_cmo_commit_245_we = addr_hit[774] & reg_we & !reg_error; + assign lp1_cmo_commit_245_wd = reg_wdata[0]; + + assign lp1_cmo_commit_246_we = addr_hit[775] & reg_we & !reg_error; + assign lp1_cmo_commit_246_wd = reg_wdata[0]; + + assign lp1_cmo_commit_247_we = addr_hit[776] & reg_we & !reg_error; + assign lp1_cmo_commit_247_wd = reg_wdata[0]; + + assign lp1_cmo_commit_248_we = addr_hit[777] & reg_we & !reg_error; + assign lp1_cmo_commit_248_wd = reg_wdata[0]; + + assign lp1_cmo_commit_249_we = addr_hit[778] & reg_we & !reg_error; + assign lp1_cmo_commit_249_wd = reg_wdata[0]; + + assign lp1_cmo_commit_250_we = addr_hit[779] & reg_we & !reg_error; + assign lp1_cmo_commit_250_wd = reg_wdata[0]; + + assign lp1_cmo_commit_251_we = addr_hit[780] & reg_we & !reg_error; + assign lp1_cmo_commit_251_wd = reg_wdata[0]; + + assign lp1_cmo_commit_252_we = addr_hit[781] & reg_we & !reg_error; + assign lp1_cmo_commit_252_wd = reg_wdata[0]; + + assign lp1_cmo_commit_253_we = addr_hit[782] & reg_we & !reg_error; + assign lp1_cmo_commit_253_wd = reg_wdata[0]; + + assign lp1_cmo_commit_254_we = addr_hit[783] & reg_we & !reg_error; + assign lp1_cmo_commit_254_wd = reg_wdata[0]; + + assign lp1_cmo_commit_255_we = addr_hit[784] & reg_we & !reg_error; + assign lp1_cmo_commit_255_wd = reg_wdata[0]; + + assign lp1_cmo_status_0_re = addr_hit[785] & reg_re & !reg_error; + + assign lp1_cmo_status_1_re = addr_hit[786] & reg_re & !reg_error; + + assign lp1_cmo_status_2_re = addr_hit[787] & reg_re & !reg_error; + + assign lp1_cmo_status_3_re = addr_hit[788] & reg_re & !reg_error; + + assign lp1_cmo_status_4_re = addr_hit[789] & reg_re & !reg_error; + + assign lp1_cmo_status_5_re = addr_hit[790] & reg_re & !reg_error; + + assign lp1_cmo_status_6_re = addr_hit[791] & reg_re & !reg_error; + + assign lp1_cmo_status_7_re = addr_hit[792] & reg_re & !reg_error; + + assign lp1_cmo_status_8_re = addr_hit[793] & reg_re & !reg_error; + + assign lp1_cmo_status_9_re = addr_hit[794] & reg_re & !reg_error; + + assign lp1_cmo_status_10_re = addr_hit[795] & reg_re & !reg_error; + + assign lp1_cmo_status_11_re = addr_hit[796] & reg_re & !reg_error; + + assign lp1_cmo_status_12_re = addr_hit[797] & reg_re & !reg_error; + + assign lp1_cmo_status_13_re = addr_hit[798] & reg_re & !reg_error; + + assign lp1_cmo_status_14_re = addr_hit[799] & reg_re & !reg_error; + + assign lp1_cmo_status_15_re = addr_hit[800] & reg_re & !reg_error; + + assign lp1_cmo_status_16_re = addr_hit[801] & reg_re & !reg_error; + + assign lp1_cmo_status_17_re = addr_hit[802] & reg_re & !reg_error; + + assign lp1_cmo_status_18_re = addr_hit[803] & reg_re & !reg_error; + + assign lp1_cmo_status_19_re = addr_hit[804] & reg_re & !reg_error; + + assign lp1_cmo_status_20_re = addr_hit[805] & reg_re & !reg_error; + + assign lp1_cmo_status_21_re = addr_hit[806] & reg_re & !reg_error; + + assign lp1_cmo_status_22_re = addr_hit[807] & reg_re & !reg_error; + + assign lp1_cmo_status_23_re = addr_hit[808] & reg_re & !reg_error; + + assign lp1_cmo_status_24_re = addr_hit[809] & reg_re & !reg_error; + + assign lp1_cmo_status_25_re = addr_hit[810] & reg_re & !reg_error; + + assign lp1_cmo_status_26_re = addr_hit[811] & reg_re & !reg_error; + + assign lp1_cmo_status_27_re = addr_hit[812] & reg_re & !reg_error; + + assign lp1_cmo_status_28_re = addr_hit[813] & reg_re & !reg_error; + + assign lp1_cmo_status_29_re = addr_hit[814] & reg_re & !reg_error; + + assign lp1_cmo_status_30_re = addr_hit[815] & reg_re & !reg_error; + + assign lp1_cmo_status_31_re = addr_hit[816] & reg_re & !reg_error; + + assign lp1_cmo_status_32_re = addr_hit[817] & reg_re & !reg_error; + + assign lp1_cmo_status_33_re = addr_hit[818] & reg_re & !reg_error; + + assign lp1_cmo_status_34_re = addr_hit[819] & reg_re & !reg_error; + + assign lp1_cmo_status_35_re = addr_hit[820] & reg_re & !reg_error; + + assign lp1_cmo_status_36_re = addr_hit[821] & reg_re & !reg_error; + + assign lp1_cmo_status_37_re = addr_hit[822] & reg_re & !reg_error; + + assign lp1_cmo_status_38_re = addr_hit[823] & reg_re & !reg_error; + + assign lp1_cmo_status_39_re = addr_hit[824] & reg_re & !reg_error; + + assign lp1_cmo_status_40_re = addr_hit[825] & reg_re & !reg_error; + + assign lp1_cmo_status_41_re = addr_hit[826] & reg_re & !reg_error; + + assign lp1_cmo_status_42_re = addr_hit[827] & reg_re & !reg_error; + + assign lp1_cmo_status_43_re = addr_hit[828] & reg_re & !reg_error; + + assign lp1_cmo_status_44_re = addr_hit[829] & reg_re & !reg_error; + + assign lp1_cmo_status_45_re = addr_hit[830] & reg_re & !reg_error; + + assign lp1_cmo_status_46_re = addr_hit[831] & reg_re & !reg_error; + + assign lp1_cmo_status_47_re = addr_hit[832] & reg_re & !reg_error; + + assign lp1_cmo_status_48_re = addr_hit[833] & reg_re & !reg_error; + + assign lp1_cmo_status_49_re = addr_hit[834] & reg_re & !reg_error; + + assign lp1_cmo_status_50_re = addr_hit[835] & reg_re & !reg_error; + + assign lp1_cmo_status_51_re = addr_hit[836] & reg_re & !reg_error; + + assign lp1_cmo_status_52_re = addr_hit[837] & reg_re & !reg_error; + + assign lp1_cmo_status_53_re = addr_hit[838] & reg_re & !reg_error; + + assign lp1_cmo_status_54_re = addr_hit[839] & reg_re & !reg_error; + + assign lp1_cmo_status_55_re = addr_hit[840] & reg_re & !reg_error; + + assign lp1_cmo_status_56_re = addr_hit[841] & reg_re & !reg_error; + + assign lp1_cmo_status_57_re = addr_hit[842] & reg_re & !reg_error; + + assign lp1_cmo_status_58_re = addr_hit[843] & reg_re & !reg_error; + + assign lp1_cmo_status_59_re = addr_hit[844] & reg_re & !reg_error; + + assign lp1_cmo_status_60_re = addr_hit[845] & reg_re & !reg_error; + + assign lp1_cmo_status_61_re = addr_hit[846] & reg_re & !reg_error; + + assign lp1_cmo_status_62_re = addr_hit[847] & reg_re & !reg_error; + + assign lp1_cmo_status_63_re = addr_hit[848] & reg_re & !reg_error; + + assign lp1_cmo_status_64_re = addr_hit[849] & reg_re & !reg_error; + + assign lp1_cmo_status_65_re = addr_hit[850] & reg_re & !reg_error; + + assign lp1_cmo_status_66_re = addr_hit[851] & reg_re & !reg_error; + + assign lp1_cmo_status_67_re = addr_hit[852] & reg_re & !reg_error; + + assign lp1_cmo_status_68_re = addr_hit[853] & reg_re & !reg_error; + + assign lp1_cmo_status_69_re = addr_hit[854] & reg_re & !reg_error; + + assign lp1_cmo_status_70_re = addr_hit[855] & reg_re & !reg_error; + + assign lp1_cmo_status_71_re = addr_hit[856] & reg_re & !reg_error; + + assign lp1_cmo_status_72_re = addr_hit[857] & reg_re & !reg_error; + + assign lp1_cmo_status_73_re = addr_hit[858] & reg_re & !reg_error; + + assign lp1_cmo_status_74_re = addr_hit[859] & reg_re & !reg_error; + + assign lp1_cmo_status_75_re = addr_hit[860] & reg_re & !reg_error; + + assign lp1_cmo_status_76_re = addr_hit[861] & reg_re & !reg_error; + + assign lp1_cmo_status_77_re = addr_hit[862] & reg_re & !reg_error; + + assign lp1_cmo_status_78_re = addr_hit[863] & reg_re & !reg_error; + + assign lp1_cmo_status_79_re = addr_hit[864] & reg_re & !reg_error; + + assign lp1_cmo_status_80_re = addr_hit[865] & reg_re & !reg_error; + + assign lp1_cmo_status_81_re = addr_hit[866] & reg_re & !reg_error; + + assign lp1_cmo_status_82_re = addr_hit[867] & reg_re & !reg_error; + + assign lp1_cmo_status_83_re = addr_hit[868] & reg_re & !reg_error; + + assign lp1_cmo_status_84_re = addr_hit[869] & reg_re & !reg_error; + + assign lp1_cmo_status_85_re = addr_hit[870] & reg_re & !reg_error; + + assign lp1_cmo_status_86_re = addr_hit[871] & reg_re & !reg_error; + + assign lp1_cmo_status_87_re = addr_hit[872] & reg_re & !reg_error; + + assign lp1_cmo_status_88_re = addr_hit[873] & reg_re & !reg_error; + + assign lp1_cmo_status_89_re = addr_hit[874] & reg_re & !reg_error; + + assign lp1_cmo_status_90_re = addr_hit[875] & reg_re & !reg_error; + + assign lp1_cmo_status_91_re = addr_hit[876] & reg_re & !reg_error; + + assign lp1_cmo_status_92_re = addr_hit[877] & reg_re & !reg_error; + + assign lp1_cmo_status_93_re = addr_hit[878] & reg_re & !reg_error; + + assign lp1_cmo_status_94_re = addr_hit[879] & reg_re & !reg_error; + + assign lp1_cmo_status_95_re = addr_hit[880] & reg_re & !reg_error; + + assign lp1_cmo_status_96_re = addr_hit[881] & reg_re & !reg_error; + + assign lp1_cmo_status_97_re = addr_hit[882] & reg_re & !reg_error; + + assign lp1_cmo_status_98_re = addr_hit[883] & reg_re & !reg_error; + + assign lp1_cmo_status_99_re = addr_hit[884] & reg_re & !reg_error; + + assign lp1_cmo_status_100_re = addr_hit[885] & reg_re & !reg_error; + + assign lp1_cmo_status_101_re = addr_hit[886] & reg_re & !reg_error; + + assign lp1_cmo_status_102_re = addr_hit[887] & reg_re & !reg_error; + + assign lp1_cmo_status_103_re = addr_hit[888] & reg_re & !reg_error; + + assign lp1_cmo_status_104_re = addr_hit[889] & reg_re & !reg_error; + + assign lp1_cmo_status_105_re = addr_hit[890] & reg_re & !reg_error; + + assign lp1_cmo_status_106_re = addr_hit[891] & reg_re & !reg_error; + + assign lp1_cmo_status_107_re = addr_hit[892] & reg_re & !reg_error; + + assign lp1_cmo_status_108_re = addr_hit[893] & reg_re & !reg_error; + + assign lp1_cmo_status_109_re = addr_hit[894] & reg_re & !reg_error; + + assign lp1_cmo_status_110_re = addr_hit[895] & reg_re & !reg_error; + + assign lp1_cmo_status_111_re = addr_hit[896] & reg_re & !reg_error; + + assign lp1_cmo_status_112_re = addr_hit[897] & reg_re & !reg_error; + + assign lp1_cmo_status_113_re = addr_hit[898] & reg_re & !reg_error; + + assign lp1_cmo_status_114_re = addr_hit[899] & reg_re & !reg_error; + + assign lp1_cmo_status_115_re = addr_hit[900] & reg_re & !reg_error; + + assign lp1_cmo_status_116_re = addr_hit[901] & reg_re & !reg_error; + + assign lp1_cmo_status_117_re = addr_hit[902] & reg_re & !reg_error; + + assign lp1_cmo_status_118_re = addr_hit[903] & reg_re & !reg_error; + + assign lp1_cmo_status_119_re = addr_hit[904] & reg_re & !reg_error; + + assign lp1_cmo_status_120_re = addr_hit[905] & reg_re & !reg_error; + + assign lp1_cmo_status_121_re = addr_hit[906] & reg_re & !reg_error; + + assign lp1_cmo_status_122_re = addr_hit[907] & reg_re & !reg_error; + + assign lp1_cmo_status_123_re = addr_hit[908] & reg_re & !reg_error; + + assign lp1_cmo_status_124_re = addr_hit[909] & reg_re & !reg_error; + + assign lp1_cmo_status_125_re = addr_hit[910] & reg_re & !reg_error; + + assign lp1_cmo_status_126_re = addr_hit[911] & reg_re & !reg_error; + + assign lp1_cmo_status_127_re = addr_hit[912] & reg_re & !reg_error; + + assign lp1_cmo_status_128_re = addr_hit[913] & reg_re & !reg_error; + + assign lp1_cmo_status_129_re = addr_hit[914] & reg_re & !reg_error; + + assign lp1_cmo_status_130_re = addr_hit[915] & reg_re & !reg_error; + + assign lp1_cmo_status_131_re = addr_hit[916] & reg_re & !reg_error; + + assign lp1_cmo_status_132_re = addr_hit[917] & reg_re & !reg_error; + + assign lp1_cmo_status_133_re = addr_hit[918] & reg_re & !reg_error; + + assign lp1_cmo_status_134_re = addr_hit[919] & reg_re & !reg_error; + + assign lp1_cmo_status_135_re = addr_hit[920] & reg_re & !reg_error; + + assign lp1_cmo_status_136_re = addr_hit[921] & reg_re & !reg_error; + + assign lp1_cmo_status_137_re = addr_hit[922] & reg_re & !reg_error; + + assign lp1_cmo_status_138_re = addr_hit[923] & reg_re & !reg_error; + + assign lp1_cmo_status_139_re = addr_hit[924] & reg_re & !reg_error; + + assign lp1_cmo_status_140_re = addr_hit[925] & reg_re & !reg_error; + + assign lp1_cmo_status_141_re = addr_hit[926] & reg_re & !reg_error; + + assign lp1_cmo_status_142_re = addr_hit[927] & reg_re & !reg_error; + + assign lp1_cmo_status_143_re = addr_hit[928] & reg_re & !reg_error; + + assign lp1_cmo_status_144_re = addr_hit[929] & reg_re & !reg_error; + + assign lp1_cmo_status_145_re = addr_hit[930] & reg_re & !reg_error; + + assign lp1_cmo_status_146_re = addr_hit[931] & reg_re & !reg_error; + + assign lp1_cmo_status_147_re = addr_hit[932] & reg_re & !reg_error; + + assign lp1_cmo_status_148_re = addr_hit[933] & reg_re & !reg_error; + + assign lp1_cmo_status_149_re = addr_hit[934] & reg_re & !reg_error; + + assign lp1_cmo_status_150_re = addr_hit[935] & reg_re & !reg_error; + + assign lp1_cmo_status_151_re = addr_hit[936] & reg_re & !reg_error; + + assign lp1_cmo_status_152_re = addr_hit[937] & reg_re & !reg_error; + + assign lp1_cmo_status_153_re = addr_hit[938] & reg_re & !reg_error; + + assign lp1_cmo_status_154_re = addr_hit[939] & reg_re & !reg_error; + + assign lp1_cmo_status_155_re = addr_hit[940] & reg_re & !reg_error; + + assign lp1_cmo_status_156_re = addr_hit[941] & reg_re & !reg_error; + + assign lp1_cmo_status_157_re = addr_hit[942] & reg_re & !reg_error; + + assign lp1_cmo_status_158_re = addr_hit[943] & reg_re & !reg_error; + + assign lp1_cmo_status_159_re = addr_hit[944] & reg_re & !reg_error; + + assign lp1_cmo_status_160_re = addr_hit[945] & reg_re & !reg_error; + + assign lp1_cmo_status_161_re = addr_hit[946] & reg_re & !reg_error; + + assign lp1_cmo_status_162_re = addr_hit[947] & reg_re & !reg_error; + + assign lp1_cmo_status_163_re = addr_hit[948] & reg_re & !reg_error; + + assign lp1_cmo_status_164_re = addr_hit[949] & reg_re & !reg_error; + + assign lp1_cmo_status_165_re = addr_hit[950] & reg_re & !reg_error; + + assign lp1_cmo_status_166_re = addr_hit[951] & reg_re & !reg_error; + + assign lp1_cmo_status_167_re = addr_hit[952] & reg_re & !reg_error; + + assign lp1_cmo_status_168_re = addr_hit[953] & reg_re & !reg_error; + + assign lp1_cmo_status_169_re = addr_hit[954] & reg_re & !reg_error; + + assign lp1_cmo_status_170_re = addr_hit[955] & reg_re & !reg_error; + + assign lp1_cmo_status_171_re = addr_hit[956] & reg_re & !reg_error; + + assign lp1_cmo_status_172_re = addr_hit[957] & reg_re & !reg_error; + + assign lp1_cmo_status_173_re = addr_hit[958] & reg_re & !reg_error; + + assign lp1_cmo_status_174_re = addr_hit[959] & reg_re & !reg_error; + + assign lp1_cmo_status_175_re = addr_hit[960] & reg_re & !reg_error; + + assign lp1_cmo_status_176_re = addr_hit[961] & reg_re & !reg_error; + + assign lp1_cmo_status_177_re = addr_hit[962] & reg_re & !reg_error; + + assign lp1_cmo_status_178_re = addr_hit[963] & reg_re & !reg_error; + + assign lp1_cmo_status_179_re = addr_hit[964] & reg_re & !reg_error; + + assign lp1_cmo_status_180_re = addr_hit[965] & reg_re & !reg_error; + + assign lp1_cmo_status_181_re = addr_hit[966] & reg_re & !reg_error; + + assign lp1_cmo_status_182_re = addr_hit[967] & reg_re & !reg_error; + + assign lp1_cmo_status_183_re = addr_hit[968] & reg_re & !reg_error; + + assign lp1_cmo_status_184_re = addr_hit[969] & reg_re & !reg_error; + + assign lp1_cmo_status_185_re = addr_hit[970] & reg_re & !reg_error; + + assign lp1_cmo_status_186_re = addr_hit[971] & reg_re & !reg_error; + + assign lp1_cmo_status_187_re = addr_hit[972] & reg_re & !reg_error; + + assign lp1_cmo_status_188_re = addr_hit[973] & reg_re & !reg_error; + + assign lp1_cmo_status_189_re = addr_hit[974] & reg_re & !reg_error; + + assign lp1_cmo_status_190_re = addr_hit[975] & reg_re & !reg_error; + + assign lp1_cmo_status_191_re = addr_hit[976] & reg_re & !reg_error; + + assign lp1_cmo_status_192_re = addr_hit[977] & reg_re & !reg_error; + + assign lp1_cmo_status_193_re = addr_hit[978] & reg_re & !reg_error; + + assign lp1_cmo_status_194_re = addr_hit[979] & reg_re & !reg_error; + + assign lp1_cmo_status_195_re = addr_hit[980] & reg_re & !reg_error; + + assign lp1_cmo_status_196_re = addr_hit[981] & reg_re & !reg_error; + + assign lp1_cmo_status_197_re = addr_hit[982] & reg_re & !reg_error; + + assign lp1_cmo_status_198_re = addr_hit[983] & reg_re & !reg_error; + + assign lp1_cmo_status_199_re = addr_hit[984] & reg_re & !reg_error; + + assign lp1_cmo_status_200_re = addr_hit[985] & reg_re & !reg_error; + + assign lp1_cmo_status_201_re = addr_hit[986] & reg_re & !reg_error; + + assign lp1_cmo_status_202_re = addr_hit[987] & reg_re & !reg_error; + + assign lp1_cmo_status_203_re = addr_hit[988] & reg_re & !reg_error; + + assign lp1_cmo_status_204_re = addr_hit[989] & reg_re & !reg_error; + + assign lp1_cmo_status_205_re = addr_hit[990] & reg_re & !reg_error; + + assign lp1_cmo_status_206_re = addr_hit[991] & reg_re & !reg_error; + + assign lp1_cmo_status_207_re = addr_hit[992] & reg_re & !reg_error; + + assign lp1_cmo_status_208_re = addr_hit[993] & reg_re & !reg_error; + + assign lp1_cmo_status_209_re = addr_hit[994] & reg_re & !reg_error; + + assign lp1_cmo_status_210_re = addr_hit[995] & reg_re & !reg_error; + + assign lp1_cmo_status_211_re = addr_hit[996] & reg_re & !reg_error; + + assign lp1_cmo_status_212_re = addr_hit[997] & reg_re & !reg_error; + + assign lp1_cmo_status_213_re = addr_hit[998] & reg_re & !reg_error; + + assign lp1_cmo_status_214_re = addr_hit[999] & reg_re & !reg_error; + + assign lp1_cmo_status_215_re = addr_hit[1000] & reg_re & !reg_error; + + assign lp1_cmo_status_216_re = addr_hit[1001] & reg_re & !reg_error; + + assign lp1_cmo_status_217_re = addr_hit[1002] & reg_re & !reg_error; + + assign lp1_cmo_status_218_re = addr_hit[1003] & reg_re & !reg_error; + + assign lp1_cmo_status_219_re = addr_hit[1004] & reg_re & !reg_error; + + assign lp1_cmo_status_220_re = addr_hit[1005] & reg_re & !reg_error; + + assign lp1_cmo_status_221_re = addr_hit[1006] & reg_re & !reg_error; + + assign lp1_cmo_status_222_re = addr_hit[1007] & reg_re & !reg_error; + + assign lp1_cmo_status_223_re = addr_hit[1008] & reg_re & !reg_error; + + assign lp1_cmo_status_224_re = addr_hit[1009] & reg_re & !reg_error; + + assign lp1_cmo_status_225_re = addr_hit[1010] & reg_re & !reg_error; + + assign lp1_cmo_status_226_re = addr_hit[1011] & reg_re & !reg_error; + + assign lp1_cmo_status_227_re = addr_hit[1012] & reg_re & !reg_error; + + assign lp1_cmo_status_228_re = addr_hit[1013] & reg_re & !reg_error; + + assign lp1_cmo_status_229_re = addr_hit[1014] & reg_re & !reg_error; + + assign lp1_cmo_status_230_re = addr_hit[1015] & reg_re & !reg_error; + + assign lp1_cmo_status_231_re = addr_hit[1016] & reg_re & !reg_error; + + assign lp1_cmo_status_232_re = addr_hit[1017] & reg_re & !reg_error; + + assign lp1_cmo_status_233_re = addr_hit[1018] & reg_re & !reg_error; + + assign lp1_cmo_status_234_re = addr_hit[1019] & reg_re & !reg_error; + + assign lp1_cmo_status_235_re = addr_hit[1020] & reg_re & !reg_error; + + assign lp1_cmo_status_236_re = addr_hit[1021] & reg_re & !reg_error; + + assign lp1_cmo_status_237_re = addr_hit[1022] & reg_re & !reg_error; + + assign lp1_cmo_status_238_re = addr_hit[1023] & reg_re & !reg_error; + + assign lp1_cmo_status_239_re = addr_hit[1024] & reg_re & !reg_error; + + assign lp1_cmo_status_240_re = addr_hit[1025] & reg_re & !reg_error; + + assign lp1_cmo_status_241_re = addr_hit[1026] & reg_re & !reg_error; + + assign lp1_cmo_status_242_re = addr_hit[1027] & reg_re & !reg_error; + + assign lp1_cmo_status_243_re = addr_hit[1028] & reg_re & !reg_error; + + assign lp1_cmo_status_244_re = addr_hit[1029] & reg_re & !reg_error; + + assign lp1_cmo_status_245_re = addr_hit[1030] & reg_re & !reg_error; + + assign lp1_cmo_status_246_re = addr_hit[1031] & reg_re & !reg_error; + + assign lp1_cmo_status_247_re = addr_hit[1032] & reg_re & !reg_error; + + assign lp1_cmo_status_248_re = addr_hit[1033] & reg_re & !reg_error; + + assign lp1_cmo_status_249_re = addr_hit[1034] & reg_re & !reg_error; + + assign lp1_cmo_status_250_re = addr_hit[1035] & reg_re & !reg_error; + + assign lp1_cmo_status_251_re = addr_hit[1036] & reg_re & !reg_error; + + assign lp1_cmo_status_252_re = addr_hit[1037] & reg_re & !reg_error; + + assign lp1_cmo_status_253_re = addr_hit[1038] & reg_re & !reg_error; + + assign lp1_cmo_status_254_re = addr_hit[1039] & reg_re & !reg_error; + + assign lp1_cmo_status_255_re = addr_hit[1040] & reg_re & !reg_error; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[31:0] = hw_barrier_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[31:0] = spatz_cycle_qs; + end + + addr_hit[4]: begin + reg_rdata_next[31:0] = cluster_boot_control_qs; + end + + addr_hit[5]: begin + reg_rdata_next[3:0] = cluster_eoc_exit_qs; + end + + addr_hit[6]: begin + reg_rdata_next[9:0] = cfg_l1d_spm_qs; + end + + addr_hit[7]: begin + reg_rdata_next[1:0] = cfg_l1d_insn_qs; + end + + addr_hit[8]: begin + reg_rdata_next[31:0] = cfg_l1d_tile_sel_0_qs; + end + + addr_hit[9]: begin + reg_rdata_next[31:0] = cfg_l1d_tile_sel_1_qs; + end + + addr_hit[10]: begin + reg_rdata_next[0] = l1d_spm_commit_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = l1d_insn_commit_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = l1d_flush_status_qs; + end + + addr_hit[13]: begin + reg_rdata_next[3:0] = l1d_private_qs; + end + + addr_hit[14]: begin + reg_rdata_next[31:0] = l1d_addr_qs; + end + + addr_hit[15]: begin + reg_rdata_next[4:0] = xbar_offset_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = xbar_offset_commit_qs; + end + + addr_hit[17]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_0_qs; + end + + addr_hit[18]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_1_qs; + end + + addr_hit[19]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_2_qs; + end + + addr_hit[20]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_3_qs; + end + + addr_hit[21]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_4_qs; + end + + addr_hit[22]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_5_qs; + end + + addr_hit[23]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_6_qs; + end + + addr_hit[24]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_7_qs; + end + + addr_hit[25]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_8_qs; + end + + addr_hit[26]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_9_qs; + end + + addr_hit[27]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_10_qs; + end + + addr_hit[28]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_11_qs; + end + + addr_hit[29]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_12_qs; + end + + addr_hit[30]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_13_qs; + end + + addr_hit[31]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_14_qs; + end + + addr_hit[32]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_15_qs; + end + + addr_hit[33]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_16_qs; + end + + addr_hit[34]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_17_qs; + end + + addr_hit[35]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_18_qs; + end + + addr_hit[36]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_19_qs; + end + + addr_hit[37]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_20_qs; + end + + addr_hit[38]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_21_qs; + end + + addr_hit[39]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_22_qs; + end + + addr_hit[40]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_23_qs; + end + + addr_hit[41]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_24_qs; + end + + addr_hit[42]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_25_qs; + end + + addr_hit[43]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_26_qs; + end + + addr_hit[44]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_27_qs; + end + + addr_hit[45]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_28_qs; + end + + addr_hit[46]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_29_qs; + end + + addr_hit[47]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_30_qs; + end + + addr_hit[48]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_31_qs; + end + + addr_hit[49]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_32_qs; + end + + addr_hit[50]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_33_qs; + end + + addr_hit[51]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_34_qs; + end + + addr_hit[52]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_35_qs; + end + + addr_hit[53]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_36_qs; + end + + addr_hit[54]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_37_qs; + end + + addr_hit[55]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_38_qs; + end + + addr_hit[56]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_39_qs; + end + + addr_hit[57]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_40_qs; + end + + addr_hit[58]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_41_qs; + end + + addr_hit[59]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_42_qs; + end + + addr_hit[60]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_43_qs; + end + + addr_hit[61]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_44_qs; + end + + addr_hit[62]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_45_qs; + end + + addr_hit[63]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_46_qs; + end + + addr_hit[64]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_47_qs; + end + + addr_hit[65]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_48_qs; + end + + addr_hit[66]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_49_qs; + end + + addr_hit[67]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_50_qs; + end + + addr_hit[68]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_51_qs; + end + + addr_hit[69]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_52_qs; + end + + addr_hit[70]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_53_qs; + end + + addr_hit[71]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_54_qs; + end + + addr_hit[72]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_55_qs; + end + + addr_hit[73]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_56_qs; + end + + addr_hit[74]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_57_qs; + end + + addr_hit[75]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_58_qs; + end + + addr_hit[76]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_59_qs; + end + + addr_hit[77]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_60_qs; + end + + addr_hit[78]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_61_qs; + end + + addr_hit[79]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_62_qs; + end + + addr_hit[80]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_63_qs; + end + + addr_hit[81]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_64_qs; + end + + addr_hit[82]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_65_qs; + end + + addr_hit[83]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_66_qs; + end + + addr_hit[84]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_67_qs; + end + + addr_hit[85]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_68_qs; + end + + addr_hit[86]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_69_qs; + end + + addr_hit[87]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_70_qs; + end + + addr_hit[88]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_71_qs; + end + + addr_hit[89]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_72_qs; + end + + addr_hit[90]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_73_qs; + end + + addr_hit[91]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_74_qs; + end + + addr_hit[92]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_75_qs; + end + + addr_hit[93]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_76_qs; + end + + addr_hit[94]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_77_qs; + end + + addr_hit[95]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_78_qs; + end + + addr_hit[96]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_79_qs; + end + + addr_hit[97]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_80_qs; + end + + addr_hit[98]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_81_qs; + end + + addr_hit[99]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_82_qs; + end + + addr_hit[100]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_83_qs; + end + + addr_hit[101]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_84_qs; + end + + addr_hit[102]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_85_qs; + end + + addr_hit[103]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_86_qs; + end + + addr_hit[104]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_87_qs; + end + + addr_hit[105]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_88_qs; + end + + addr_hit[106]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_89_qs; + end + + addr_hit[107]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_90_qs; + end + + addr_hit[108]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_91_qs; + end + + addr_hit[109]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_92_qs; + end + + addr_hit[110]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_93_qs; + end + + addr_hit[111]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_94_qs; + end + + addr_hit[112]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_95_qs; + end + + addr_hit[113]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_96_qs; + end + + addr_hit[114]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_97_qs; + end + + addr_hit[115]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_98_qs; + end + + addr_hit[116]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_99_qs; + end + + addr_hit[117]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_100_qs; + end + + addr_hit[118]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_101_qs; + end + + addr_hit[119]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_102_qs; + end + + addr_hit[120]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_103_qs; + end + + addr_hit[121]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_104_qs; + end + + addr_hit[122]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_105_qs; + end + + addr_hit[123]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_106_qs; + end + + addr_hit[124]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_107_qs; + end + + addr_hit[125]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_108_qs; + end + + addr_hit[126]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_109_qs; + end + + addr_hit[127]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_110_qs; + end + + addr_hit[128]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_111_qs; + end + + addr_hit[129]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_112_qs; + end + + addr_hit[130]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_113_qs; + end + + addr_hit[131]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_114_qs; + end + + addr_hit[132]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_115_qs; + end + + addr_hit[133]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_116_qs; + end + + addr_hit[134]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_117_qs; + end + + addr_hit[135]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_118_qs; + end + + addr_hit[136]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_119_qs; + end + + addr_hit[137]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_120_qs; + end + + addr_hit[138]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_121_qs; + end + + addr_hit[139]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_122_qs; + end + + addr_hit[140]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_123_qs; + end + + addr_hit[141]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_124_qs; + end + + addr_hit[142]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_125_qs; + end + + addr_hit[143]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_126_qs; + end + + addr_hit[144]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_127_qs; + end + + addr_hit[145]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_128_qs; + end + + addr_hit[146]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_129_qs; + end + + addr_hit[147]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_130_qs; + end + + addr_hit[148]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_131_qs; + end + + addr_hit[149]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_132_qs; + end + + addr_hit[150]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_133_qs; + end + + addr_hit[151]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_134_qs; + end + + addr_hit[152]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_135_qs; + end + + addr_hit[153]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_136_qs; + end + + addr_hit[154]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_137_qs; + end + + addr_hit[155]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_138_qs; + end + + addr_hit[156]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_139_qs; + end + + addr_hit[157]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_140_qs; + end + + addr_hit[158]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_141_qs; + end + + addr_hit[159]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_142_qs; + end + + addr_hit[160]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_143_qs; + end + + addr_hit[161]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_144_qs; + end + + addr_hit[162]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_145_qs; + end + + addr_hit[163]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_146_qs; + end + + addr_hit[164]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_147_qs; + end + + addr_hit[165]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_148_qs; + end + + addr_hit[166]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_149_qs; + end + + addr_hit[167]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_150_qs; + end + + addr_hit[168]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_151_qs; + end + + addr_hit[169]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_152_qs; + end + + addr_hit[170]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_153_qs; + end + + addr_hit[171]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_154_qs; + end + + addr_hit[172]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_155_qs; + end + + addr_hit[173]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_156_qs; + end + + addr_hit[174]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_157_qs; + end + + addr_hit[175]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_158_qs; + end + + addr_hit[176]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_159_qs; + end + + addr_hit[177]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_160_qs; + end + + addr_hit[178]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_161_qs; + end + + addr_hit[179]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_162_qs; + end + + addr_hit[180]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_163_qs; + end + + addr_hit[181]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_164_qs; + end + + addr_hit[182]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_165_qs; + end + + addr_hit[183]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_166_qs; + end + + addr_hit[184]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_167_qs; + end + + addr_hit[185]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_168_qs; + end + + addr_hit[186]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_169_qs; + end + + addr_hit[187]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_170_qs; + end + + addr_hit[188]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_171_qs; + end + + addr_hit[189]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_172_qs; + end + + addr_hit[190]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_173_qs; + end + + addr_hit[191]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_174_qs; + end + + addr_hit[192]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_175_qs; + end + + addr_hit[193]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_176_qs; + end + + addr_hit[194]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_177_qs; + end + + addr_hit[195]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_178_qs; + end + + addr_hit[196]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_179_qs; + end + + addr_hit[197]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_180_qs; + end + + addr_hit[198]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_181_qs; + end + + addr_hit[199]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_182_qs; + end + + addr_hit[200]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_183_qs; + end + + addr_hit[201]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_184_qs; + end + + addr_hit[202]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_185_qs; + end + + addr_hit[203]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_186_qs; + end + + addr_hit[204]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_187_qs; + end + + addr_hit[205]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_188_qs; + end + + addr_hit[206]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_189_qs; + end + + addr_hit[207]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_190_qs; + end + + addr_hit[208]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_191_qs; + end + + addr_hit[209]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_192_qs; + end + + addr_hit[210]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_193_qs; + end + + addr_hit[211]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_194_qs; + end + + addr_hit[212]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_195_qs; + end + + addr_hit[213]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_196_qs; + end + + addr_hit[214]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_197_qs; + end + + addr_hit[215]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_198_qs; + end + + addr_hit[216]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_199_qs; + end + + addr_hit[217]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_200_qs; + end + + addr_hit[218]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_201_qs; + end + + addr_hit[219]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_202_qs; + end + + addr_hit[220]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_203_qs; + end + + addr_hit[221]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_204_qs; + end + + addr_hit[222]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_205_qs; + end + + addr_hit[223]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_206_qs; + end + + addr_hit[224]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_207_qs; + end + + addr_hit[225]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_208_qs; + end + + addr_hit[226]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_209_qs; + end + + addr_hit[227]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_210_qs; + end + + addr_hit[228]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_211_qs; + end + + addr_hit[229]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_212_qs; + end + + addr_hit[230]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_213_qs; + end + + addr_hit[231]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_214_qs; + end + + addr_hit[232]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_215_qs; + end + + addr_hit[233]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_216_qs; + end + + addr_hit[234]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_217_qs; + end + + addr_hit[235]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_218_qs; + end + + addr_hit[236]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_219_qs; + end + + addr_hit[237]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_220_qs; + end + + addr_hit[238]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_221_qs; + end + + addr_hit[239]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_222_qs; + end + + addr_hit[240]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_223_qs; + end + + addr_hit[241]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_224_qs; + end + + addr_hit[242]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_225_qs; + end + + addr_hit[243]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_226_qs; + end + + addr_hit[244]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_227_qs; + end + + addr_hit[245]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_228_qs; + end + + addr_hit[246]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_229_qs; + end + + addr_hit[247]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_230_qs; + end + + addr_hit[248]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_231_qs; + end + + addr_hit[249]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_232_qs; + end + + addr_hit[250]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_233_qs; + end + + addr_hit[251]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_234_qs; + end + + addr_hit[252]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_235_qs; + end + + addr_hit[253]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_236_qs; + end + + addr_hit[254]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_237_qs; + end + + addr_hit[255]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_238_qs; + end + + addr_hit[256]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_239_qs; + end + + addr_hit[257]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_240_qs; + end + + addr_hit[258]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_241_qs; + end + + addr_hit[259]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_242_qs; + end + + addr_hit[260]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_243_qs; + end + + addr_hit[261]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_244_qs; + end + + addr_hit[262]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_245_qs; + end + + addr_hit[263]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_246_qs; + end + + addr_hit[264]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_247_qs; + end + + addr_hit[265]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_248_qs; + end + + addr_hit[266]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_249_qs; + end + + addr_hit[267]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_250_qs; + end + + addr_hit[268]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_251_qs; + end + + addr_hit[269]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_252_qs; + end + + addr_hit[270]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_253_qs; + end + + addr_hit[271]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_254_qs; + end + + addr_hit[272]: begin + reg_rdata_next[2:0] = cfg_lp1_cmo_255_qs; + end + + addr_hit[273]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_0_qs; + end + + addr_hit[274]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_1_qs; + end + + addr_hit[275]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_2_qs; + end + + addr_hit[276]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_3_qs; + end + + addr_hit[277]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_4_qs; + end + + addr_hit[278]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_5_qs; + end + + addr_hit[279]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_6_qs; + end + + addr_hit[280]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_7_qs; + end + + addr_hit[281]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_8_qs; + end + + addr_hit[282]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_9_qs; + end + + addr_hit[283]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_10_qs; + end + + addr_hit[284]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_11_qs; + end + + addr_hit[285]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_12_qs; + end + + addr_hit[286]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_13_qs; + end + + addr_hit[287]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_14_qs; + end + + addr_hit[288]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_15_qs; + end + + addr_hit[289]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_16_qs; + end + + addr_hit[290]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_17_qs; + end + + addr_hit[291]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_18_qs; + end + + addr_hit[292]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_19_qs; + end + + addr_hit[293]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_20_qs; + end + + addr_hit[294]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_21_qs; + end + + addr_hit[295]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_22_qs; + end + + addr_hit[296]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_23_qs; + end + + addr_hit[297]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_24_qs; + end + + addr_hit[298]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_25_qs; + end + + addr_hit[299]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_26_qs; + end + + addr_hit[300]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_27_qs; + end + + addr_hit[301]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_28_qs; + end + + addr_hit[302]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_29_qs; + end + + addr_hit[303]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_30_qs; + end + + addr_hit[304]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_31_qs; + end + + addr_hit[305]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_32_qs; + end + + addr_hit[306]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_33_qs; + end + + addr_hit[307]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_34_qs; + end + + addr_hit[308]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_35_qs; + end + + addr_hit[309]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_36_qs; + end + + addr_hit[310]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_37_qs; + end + + addr_hit[311]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_38_qs; + end + + addr_hit[312]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_39_qs; + end + + addr_hit[313]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_40_qs; + end + + addr_hit[314]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_41_qs; + end + + addr_hit[315]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_42_qs; + end + + addr_hit[316]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_43_qs; + end + + addr_hit[317]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_44_qs; + end + + addr_hit[318]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_45_qs; + end + + addr_hit[319]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_46_qs; + end + + addr_hit[320]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_47_qs; + end + + addr_hit[321]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_48_qs; + end + + addr_hit[322]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_49_qs; + end + + addr_hit[323]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_50_qs; + end + + addr_hit[324]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_51_qs; + end + + addr_hit[325]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_52_qs; + end + + addr_hit[326]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_53_qs; + end + + addr_hit[327]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_54_qs; + end + + addr_hit[328]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_55_qs; + end + + addr_hit[329]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_56_qs; + end + + addr_hit[330]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_57_qs; + end + + addr_hit[331]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_58_qs; + end + + addr_hit[332]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_59_qs; + end + + addr_hit[333]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_60_qs; + end + + addr_hit[334]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_61_qs; + end + + addr_hit[335]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_62_qs; + end + + addr_hit[336]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_63_qs; + end + + addr_hit[337]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_64_qs; + end + + addr_hit[338]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_65_qs; + end + + addr_hit[339]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_66_qs; + end + + addr_hit[340]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_67_qs; + end + + addr_hit[341]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_68_qs; + end + + addr_hit[342]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_69_qs; + end + + addr_hit[343]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_70_qs; + end + + addr_hit[344]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_71_qs; + end + + addr_hit[345]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_72_qs; + end + + addr_hit[346]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_73_qs; + end + + addr_hit[347]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_74_qs; + end + + addr_hit[348]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_75_qs; + end + + addr_hit[349]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_76_qs; + end + + addr_hit[350]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_77_qs; + end + + addr_hit[351]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_78_qs; + end + + addr_hit[352]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_79_qs; + end + + addr_hit[353]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_80_qs; + end + + addr_hit[354]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_81_qs; + end + + addr_hit[355]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_82_qs; + end + + addr_hit[356]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_83_qs; + end + + addr_hit[357]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_84_qs; + end + + addr_hit[358]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_85_qs; + end + + addr_hit[359]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_86_qs; + end + + addr_hit[360]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_87_qs; + end + + addr_hit[361]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_88_qs; + end + + addr_hit[362]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_89_qs; + end + + addr_hit[363]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_90_qs; + end + + addr_hit[364]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_91_qs; + end + + addr_hit[365]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_92_qs; + end + + addr_hit[366]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_93_qs; + end + + addr_hit[367]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_94_qs; + end + + addr_hit[368]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_95_qs; + end + + addr_hit[369]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_96_qs; + end + + addr_hit[370]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_97_qs; + end + + addr_hit[371]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_98_qs; + end + + addr_hit[372]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_99_qs; + end + + addr_hit[373]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_100_qs; + end + + addr_hit[374]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_101_qs; + end + + addr_hit[375]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_102_qs; + end + + addr_hit[376]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_103_qs; + end + + addr_hit[377]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_104_qs; + end + + addr_hit[378]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_105_qs; + end + + addr_hit[379]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_106_qs; + end + + addr_hit[380]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_107_qs; + end + + addr_hit[381]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_108_qs; + end + + addr_hit[382]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_109_qs; + end + + addr_hit[383]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_110_qs; + end + + addr_hit[384]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_111_qs; + end + + addr_hit[385]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_112_qs; + end + + addr_hit[386]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_113_qs; + end + + addr_hit[387]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_114_qs; + end + + addr_hit[388]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_115_qs; + end + + addr_hit[389]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_116_qs; + end + + addr_hit[390]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_117_qs; + end + + addr_hit[391]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_118_qs; + end + + addr_hit[392]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_119_qs; + end + + addr_hit[393]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_120_qs; + end + + addr_hit[394]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_121_qs; + end + + addr_hit[395]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_122_qs; + end + + addr_hit[396]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_123_qs; + end + + addr_hit[397]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_124_qs; + end + + addr_hit[398]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_125_qs; + end + + addr_hit[399]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_126_qs; + end + + addr_hit[400]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_127_qs; + end + + addr_hit[401]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_128_qs; + end + + addr_hit[402]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_129_qs; + end + + addr_hit[403]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_130_qs; + end + + addr_hit[404]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_131_qs; + end + + addr_hit[405]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_132_qs; + end + + addr_hit[406]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_133_qs; + end + + addr_hit[407]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_134_qs; + end + + addr_hit[408]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_135_qs; + end + + addr_hit[409]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_136_qs; + end + + addr_hit[410]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_137_qs; + end + + addr_hit[411]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_138_qs; + end + + addr_hit[412]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_139_qs; + end + + addr_hit[413]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_140_qs; + end + + addr_hit[414]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_141_qs; + end + + addr_hit[415]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_142_qs; + end + + addr_hit[416]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_143_qs; + end + + addr_hit[417]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_144_qs; + end + + addr_hit[418]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_145_qs; + end + + addr_hit[419]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_146_qs; + end + + addr_hit[420]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_147_qs; + end + + addr_hit[421]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_148_qs; + end + + addr_hit[422]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_149_qs; + end + + addr_hit[423]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_150_qs; + end + + addr_hit[424]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_151_qs; + end + + addr_hit[425]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_152_qs; + end + + addr_hit[426]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_153_qs; + end + + addr_hit[427]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_154_qs; + end + + addr_hit[428]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_155_qs; + end + + addr_hit[429]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_156_qs; + end + + addr_hit[430]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_157_qs; + end + + addr_hit[431]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_158_qs; + end + + addr_hit[432]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_159_qs; + end + + addr_hit[433]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_160_qs; + end + + addr_hit[434]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_161_qs; + end + + addr_hit[435]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_162_qs; + end + + addr_hit[436]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_163_qs; + end + + addr_hit[437]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_164_qs; + end + + addr_hit[438]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_165_qs; + end + + addr_hit[439]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_166_qs; + end + + addr_hit[440]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_167_qs; + end + + addr_hit[441]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_168_qs; + end + + addr_hit[442]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_169_qs; + end + + addr_hit[443]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_170_qs; + end + + addr_hit[444]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_171_qs; + end + + addr_hit[445]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_172_qs; + end + + addr_hit[446]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_173_qs; + end + + addr_hit[447]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_174_qs; + end + + addr_hit[448]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_175_qs; + end + + addr_hit[449]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_176_qs; + end + + addr_hit[450]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_177_qs; + end + + addr_hit[451]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_178_qs; + end + + addr_hit[452]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_179_qs; + end + + addr_hit[453]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_180_qs; + end + + addr_hit[454]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_181_qs; + end + + addr_hit[455]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_182_qs; + end + + addr_hit[456]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_183_qs; + end + + addr_hit[457]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_184_qs; + end + + addr_hit[458]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_185_qs; + end + + addr_hit[459]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_186_qs; + end + + addr_hit[460]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_187_qs; + end + + addr_hit[461]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_188_qs; + end + + addr_hit[462]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_189_qs; + end + + addr_hit[463]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_190_qs; + end + + addr_hit[464]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_191_qs; + end + + addr_hit[465]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_192_qs; + end + + addr_hit[466]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_193_qs; + end + + addr_hit[467]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_194_qs; + end + + addr_hit[468]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_195_qs; + end + + addr_hit[469]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_196_qs; + end + + addr_hit[470]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_197_qs; + end + + addr_hit[471]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_198_qs; + end + + addr_hit[472]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_199_qs; + end + + addr_hit[473]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_200_qs; + end + + addr_hit[474]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_201_qs; + end + + addr_hit[475]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_202_qs; + end + + addr_hit[476]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_203_qs; + end + + addr_hit[477]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_204_qs; + end + + addr_hit[478]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_205_qs; + end + + addr_hit[479]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_206_qs; + end + + addr_hit[480]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_207_qs; + end + + addr_hit[481]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_208_qs; + end + + addr_hit[482]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_209_qs; + end - prim_subreg_ext #( - .DW (1) - ) u_lp1_cmo_status_63 ( - .re (lp1_cmo_status_63_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.lp1_cmo_status[63].d), - .qre (), - .qe (), - .q (), - .qs (lp1_cmo_status_63_qs) - ); + addr_hit[483]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_210_qs; + end + addr_hit[484]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_211_qs; + end + addr_hit[485]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_212_qs; + end + addr_hit[486]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_213_qs; + end - logic [272:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[ 0] = (reg_addr == CACHEPOOL_PERIPHERAL_HW_BARRIER_OFFSET); - addr_hit[ 1] = (reg_addr == CACHEPOOL_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); - addr_hit[ 2] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_STATUS_OFFSET); - addr_hit[ 3] = (reg_addr == CACHEPOOL_PERIPHERAL_SPATZ_CYCLE_OFFSET); - addr_hit[ 4] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET); - addr_hit[ 5] = (reg_addr == CACHEPOOL_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET); - addr_hit[ 6] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_SPM_OFFSET); - addr_hit[ 7] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_INSN_OFFSET); - addr_hit[ 8] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_0_OFFSET); - addr_hit[ 9] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_L1D_TILE_SEL_1_OFFSET); - addr_hit[ 10] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_SPM_COMMIT_OFFSET); - addr_hit[ 11] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_INSN_COMMIT_OFFSET); - addr_hit[ 12] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET); - addr_hit[ 13] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_PRIVATE_OFFSET); - addr_hit[ 14] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET); - addr_hit[ 15] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET); - addr_hit[ 16] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET); - addr_hit[ 17] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_OFFSET); - addr_hit[ 18] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_1_OFFSET); - addr_hit[ 19] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_2_OFFSET); - addr_hit[ 20] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_3_OFFSET); - addr_hit[ 21] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_4_OFFSET); - addr_hit[ 22] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_5_OFFSET); - addr_hit[ 23] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_6_OFFSET); - addr_hit[ 24] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_7_OFFSET); - addr_hit[ 25] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_8_OFFSET); - addr_hit[ 26] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_9_OFFSET); - addr_hit[ 27] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_10_OFFSET); - addr_hit[ 28] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_11_OFFSET); - addr_hit[ 29] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_12_OFFSET); - addr_hit[ 30] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_13_OFFSET); - addr_hit[ 31] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_14_OFFSET); - addr_hit[ 32] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_15_OFFSET); - addr_hit[ 33] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_16_OFFSET); - addr_hit[ 34] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_17_OFFSET); - addr_hit[ 35] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_18_OFFSET); - addr_hit[ 36] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_19_OFFSET); - addr_hit[ 37] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_20_OFFSET); - addr_hit[ 38] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_21_OFFSET); - addr_hit[ 39] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_22_OFFSET); - addr_hit[ 40] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_23_OFFSET); - addr_hit[ 41] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_24_OFFSET); - addr_hit[ 42] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_25_OFFSET); - addr_hit[ 43] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_26_OFFSET); - addr_hit[ 44] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_27_OFFSET); - addr_hit[ 45] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_28_OFFSET); - addr_hit[ 46] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_29_OFFSET); - addr_hit[ 47] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_30_OFFSET); - addr_hit[ 48] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_31_OFFSET); - addr_hit[ 49] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_32_OFFSET); - addr_hit[ 50] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_33_OFFSET); - addr_hit[ 51] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_34_OFFSET); - addr_hit[ 52] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_35_OFFSET); - addr_hit[ 53] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_36_OFFSET); - addr_hit[ 54] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_37_OFFSET); - addr_hit[ 55] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_38_OFFSET); - addr_hit[ 56] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_39_OFFSET); - addr_hit[ 57] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_40_OFFSET); - addr_hit[ 58] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_41_OFFSET); - addr_hit[ 59] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_42_OFFSET); - addr_hit[ 60] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_43_OFFSET); - addr_hit[ 61] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_44_OFFSET); - addr_hit[ 62] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_45_OFFSET); - addr_hit[ 63] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_46_OFFSET); - addr_hit[ 64] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_47_OFFSET); - addr_hit[ 65] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_48_OFFSET); - addr_hit[ 66] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_49_OFFSET); - addr_hit[ 67] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_50_OFFSET); - addr_hit[ 68] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_51_OFFSET); - addr_hit[ 69] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_52_OFFSET); - addr_hit[ 70] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_53_OFFSET); - addr_hit[ 71] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_54_OFFSET); - addr_hit[ 72] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_55_OFFSET); - addr_hit[ 73] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_56_OFFSET); - addr_hit[ 74] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_57_OFFSET); - addr_hit[ 75] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_58_OFFSET); - addr_hit[ 76] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_59_OFFSET); - addr_hit[ 77] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_60_OFFSET); - addr_hit[ 78] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_61_OFFSET); - addr_hit[ 79] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_62_OFFSET); - addr_hit[ 80] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OFFSET); - addr_hit[ 81] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0_OFFSET); - addr_hit[ 82] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1_OFFSET); - addr_hit[ 83] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2_OFFSET); - addr_hit[ 84] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3_OFFSET); - addr_hit[ 85] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4_OFFSET); - addr_hit[ 86] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5_OFFSET); - addr_hit[ 87] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6_OFFSET); - addr_hit[ 88] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7_OFFSET); - addr_hit[ 89] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8_OFFSET); - addr_hit[ 90] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9_OFFSET); - addr_hit[ 91] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10_OFFSET); - addr_hit[ 92] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11_OFFSET); - addr_hit[ 93] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12_OFFSET); - addr_hit[ 94] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13_OFFSET); - addr_hit[ 95] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14_OFFSET); - addr_hit[ 96] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15_OFFSET); - addr_hit[ 97] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16_OFFSET); - addr_hit[ 98] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17_OFFSET); - addr_hit[ 99] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18_OFFSET); - addr_hit[100] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19_OFFSET); - addr_hit[101] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20_OFFSET); - addr_hit[102] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21_OFFSET); - addr_hit[103] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22_OFFSET); - addr_hit[104] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23_OFFSET); - addr_hit[105] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24_OFFSET); - addr_hit[106] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25_OFFSET); - addr_hit[107] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26_OFFSET); - addr_hit[108] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27_OFFSET); - addr_hit[109] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28_OFFSET); - addr_hit[110] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29_OFFSET); - addr_hit[111] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30_OFFSET); - addr_hit[112] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31_OFFSET); - addr_hit[113] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32_OFFSET); - addr_hit[114] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33_OFFSET); - addr_hit[115] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34_OFFSET); - addr_hit[116] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35_OFFSET); - addr_hit[117] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36_OFFSET); - addr_hit[118] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37_OFFSET); - addr_hit[119] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38_OFFSET); - addr_hit[120] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39_OFFSET); - addr_hit[121] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40_OFFSET); - addr_hit[122] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41_OFFSET); - addr_hit[123] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42_OFFSET); - addr_hit[124] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43_OFFSET); - addr_hit[125] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44_OFFSET); - addr_hit[126] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45_OFFSET); - addr_hit[127] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46_OFFSET); - addr_hit[128] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47_OFFSET); - addr_hit[129] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48_OFFSET); - addr_hit[130] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49_OFFSET); - addr_hit[131] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50_OFFSET); - addr_hit[132] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51_OFFSET); - addr_hit[133] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52_OFFSET); - addr_hit[134] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53_OFFSET); - addr_hit[135] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54_OFFSET); - addr_hit[136] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55_OFFSET); - addr_hit[137] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56_OFFSET); - addr_hit[138] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57_OFFSET); - addr_hit[139] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58_OFFSET); - addr_hit[140] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59_OFFSET); - addr_hit[141] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60_OFFSET); - addr_hit[142] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61_OFFSET); - addr_hit[143] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62_OFFSET); - addr_hit[144] = (reg_addr == CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63_OFFSET); - addr_hit[145] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_OFFSET); - addr_hit[146] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_OFFSET); - addr_hit[147] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_OFFSET); - addr_hit[148] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_OFFSET); - addr_hit[149] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_OFFSET); - addr_hit[150] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_OFFSET); - addr_hit[151] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_OFFSET); - addr_hit[152] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_OFFSET); - addr_hit[153] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_OFFSET); - addr_hit[154] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_OFFSET); - addr_hit[155] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_OFFSET); - addr_hit[156] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_OFFSET); - addr_hit[157] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_OFFSET); - addr_hit[158] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_OFFSET); - addr_hit[159] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_OFFSET); - addr_hit[160] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_OFFSET); - addr_hit[161] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_OFFSET); - addr_hit[162] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_OFFSET); - addr_hit[163] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_OFFSET); - addr_hit[164] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_OFFSET); - addr_hit[165] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_OFFSET); - addr_hit[166] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_OFFSET); - addr_hit[167] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_OFFSET); - addr_hit[168] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_OFFSET); - addr_hit[169] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_OFFSET); - addr_hit[170] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_OFFSET); - addr_hit[171] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_OFFSET); - addr_hit[172] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_OFFSET); - addr_hit[173] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_OFFSET); - addr_hit[174] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_OFFSET); - addr_hit[175] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_OFFSET); - addr_hit[176] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_OFFSET); - addr_hit[177] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_OFFSET); - addr_hit[178] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_OFFSET); - addr_hit[179] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_OFFSET); - addr_hit[180] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_OFFSET); - addr_hit[181] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_OFFSET); - addr_hit[182] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_OFFSET); - addr_hit[183] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_OFFSET); - addr_hit[184] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_OFFSET); - addr_hit[185] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_OFFSET); - addr_hit[186] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_OFFSET); - addr_hit[187] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_OFFSET); - addr_hit[188] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_OFFSET); - addr_hit[189] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_OFFSET); - addr_hit[190] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_OFFSET); - addr_hit[191] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_OFFSET); - addr_hit[192] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_OFFSET); - addr_hit[193] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_OFFSET); - addr_hit[194] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_OFFSET); - addr_hit[195] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_OFFSET); - addr_hit[196] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_OFFSET); - addr_hit[197] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_OFFSET); - addr_hit[198] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_OFFSET); - addr_hit[199] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_OFFSET); - addr_hit[200] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_OFFSET); - addr_hit[201] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_OFFSET); - addr_hit[202] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_OFFSET); - addr_hit[203] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_OFFSET); - addr_hit[204] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_OFFSET); - addr_hit[205] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_OFFSET); - addr_hit[206] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_OFFSET); - addr_hit[207] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_OFFSET); - addr_hit[208] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_OFFSET); - addr_hit[209] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_OFFSET); - addr_hit[210] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_OFFSET); - addr_hit[211] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_OFFSET); - addr_hit[212] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_OFFSET); - addr_hit[213] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_OFFSET); - addr_hit[214] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_OFFSET); - addr_hit[215] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_OFFSET); - addr_hit[216] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_OFFSET); - addr_hit[217] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_OFFSET); - addr_hit[218] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_OFFSET); - addr_hit[219] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_OFFSET); - addr_hit[220] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_OFFSET); - addr_hit[221] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_OFFSET); - addr_hit[222] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_OFFSET); - addr_hit[223] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_OFFSET); - addr_hit[224] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_OFFSET); - addr_hit[225] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_OFFSET); - addr_hit[226] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_OFFSET); - addr_hit[227] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_OFFSET); - addr_hit[228] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_OFFSET); - addr_hit[229] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_OFFSET); - addr_hit[230] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_OFFSET); - addr_hit[231] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_OFFSET); - addr_hit[232] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_OFFSET); - addr_hit[233] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_OFFSET); - addr_hit[234] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_OFFSET); - addr_hit[235] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_OFFSET); - addr_hit[236] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_OFFSET); - addr_hit[237] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_OFFSET); - addr_hit[238] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_OFFSET); - addr_hit[239] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_OFFSET); - addr_hit[240] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_OFFSET); - addr_hit[241] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_OFFSET); - addr_hit[242] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_OFFSET); - addr_hit[243] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_OFFSET); - addr_hit[244] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_OFFSET); - addr_hit[245] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_OFFSET); - addr_hit[246] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_OFFSET); - addr_hit[247] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_OFFSET); - addr_hit[248] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_OFFSET); - addr_hit[249] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_OFFSET); - addr_hit[250] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_OFFSET); - addr_hit[251] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_OFFSET); - addr_hit[252] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_OFFSET); - addr_hit[253] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_OFFSET); - addr_hit[254] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_OFFSET); - addr_hit[255] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_OFFSET); - addr_hit[256] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_OFFSET); - addr_hit[257] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_OFFSET); - addr_hit[258] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_OFFSET); - addr_hit[259] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_OFFSET); - addr_hit[260] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_OFFSET); - addr_hit[261] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_OFFSET); - addr_hit[262] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_OFFSET); - addr_hit[263] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_OFFSET); - addr_hit[264] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_OFFSET); - addr_hit[265] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_OFFSET); - addr_hit[266] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_OFFSET); - addr_hit[267] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_OFFSET); - addr_hit[268] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_OFFSET); - addr_hit[269] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_OFFSET); - addr_hit[270] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_OFFSET); - addr_hit[271] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_OFFSET); - addr_hit[272] = (reg_addr == CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_OFFSET); - end + addr_hit[487]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_214_qs; + end - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + addr_hit[488]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_215_qs; + end - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[ 0] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 9] & ~reg_be))) | - (addr_hit[ 10] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 10] & ~reg_be))) | - (addr_hit[ 11] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 11] & ~reg_be))) | - (addr_hit[ 12] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 12] & ~reg_be))) | - (addr_hit[ 13] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 13] & ~reg_be))) | - (addr_hit[ 14] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 14] & ~reg_be))) | - (addr_hit[ 15] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 15] & ~reg_be))) | - (addr_hit[ 16] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 16] & ~reg_be))) | - (addr_hit[ 17] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 17] & ~reg_be))) | - (addr_hit[ 18] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 18] & ~reg_be))) | - (addr_hit[ 19] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 19] & ~reg_be))) | - (addr_hit[ 20] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 20] & ~reg_be))) | - (addr_hit[ 21] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 21] & ~reg_be))) | - (addr_hit[ 22] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 22] & ~reg_be))) | - (addr_hit[ 23] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 23] & ~reg_be))) | - (addr_hit[ 24] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 24] & ~reg_be))) | - (addr_hit[ 25] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 25] & ~reg_be))) | - (addr_hit[ 26] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 26] & ~reg_be))) | - (addr_hit[ 27] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 27] & ~reg_be))) | - (addr_hit[ 28] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 28] & ~reg_be))) | - (addr_hit[ 29] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 29] & ~reg_be))) | - (addr_hit[ 30] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 30] & ~reg_be))) | - (addr_hit[ 31] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 31] & ~reg_be))) | - (addr_hit[ 32] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 32] & ~reg_be))) | - (addr_hit[ 33] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 33] & ~reg_be))) | - (addr_hit[ 34] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 34] & ~reg_be))) | - (addr_hit[ 35] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 35] & ~reg_be))) | - (addr_hit[ 36] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 36] & ~reg_be))) | - (addr_hit[ 37] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 37] & ~reg_be))) | - (addr_hit[ 38] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 38] & ~reg_be))) | - (addr_hit[ 39] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 39] & ~reg_be))) | - (addr_hit[ 40] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 40] & ~reg_be))) | - (addr_hit[ 41] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 41] & ~reg_be))) | - (addr_hit[ 42] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 42] & ~reg_be))) | - (addr_hit[ 43] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 43] & ~reg_be))) | - (addr_hit[ 44] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 44] & ~reg_be))) | - (addr_hit[ 45] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 45] & ~reg_be))) | - (addr_hit[ 46] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 46] & ~reg_be))) | - (addr_hit[ 47] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 47] & ~reg_be))) | - (addr_hit[ 48] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 48] & ~reg_be))) | - (addr_hit[ 49] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 49] & ~reg_be))) | - (addr_hit[ 50] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 50] & ~reg_be))) | - (addr_hit[ 51] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 51] & ~reg_be))) | - (addr_hit[ 52] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 52] & ~reg_be))) | - (addr_hit[ 53] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 53] & ~reg_be))) | - (addr_hit[ 54] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 54] & ~reg_be))) | - (addr_hit[ 55] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 55] & ~reg_be))) | - (addr_hit[ 56] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 56] & ~reg_be))) | - (addr_hit[ 57] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 57] & ~reg_be))) | - (addr_hit[ 58] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 58] & ~reg_be))) | - (addr_hit[ 59] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 59] & ~reg_be))) | - (addr_hit[ 60] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 60] & ~reg_be))) | - (addr_hit[ 61] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 61] & ~reg_be))) | - (addr_hit[ 62] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 62] & ~reg_be))) | - (addr_hit[ 63] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 63] & ~reg_be))) | - (addr_hit[ 64] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 64] & ~reg_be))) | - (addr_hit[ 65] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 65] & ~reg_be))) | - (addr_hit[ 66] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 66] & ~reg_be))) | - (addr_hit[ 67] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 67] & ~reg_be))) | - (addr_hit[ 68] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 68] & ~reg_be))) | - (addr_hit[ 69] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 69] & ~reg_be))) | - (addr_hit[ 70] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 70] & ~reg_be))) | - (addr_hit[ 71] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 71] & ~reg_be))) | - (addr_hit[ 72] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 72] & ~reg_be))) | - (addr_hit[ 73] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 73] & ~reg_be))) | - (addr_hit[ 74] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 74] & ~reg_be))) | - (addr_hit[ 75] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 75] & ~reg_be))) | - (addr_hit[ 76] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 76] & ~reg_be))) | - (addr_hit[ 77] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 77] & ~reg_be))) | - (addr_hit[ 78] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 78] & ~reg_be))) | - (addr_hit[ 79] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 79] & ~reg_be))) | - (addr_hit[ 80] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 80] & ~reg_be))) | - (addr_hit[ 81] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 81] & ~reg_be))) | - (addr_hit[ 82] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 82] & ~reg_be))) | - (addr_hit[ 83] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 83] & ~reg_be))) | - (addr_hit[ 84] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 84] & ~reg_be))) | - (addr_hit[ 85] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 85] & ~reg_be))) | - (addr_hit[ 86] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 86] & ~reg_be))) | - (addr_hit[ 87] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 87] & ~reg_be))) | - (addr_hit[ 88] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 88] & ~reg_be))) | - (addr_hit[ 89] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 89] & ~reg_be))) | - (addr_hit[ 90] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 90] & ~reg_be))) | - (addr_hit[ 91] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 91] & ~reg_be))) | - (addr_hit[ 92] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 92] & ~reg_be))) | - (addr_hit[ 93] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 93] & ~reg_be))) | - (addr_hit[ 94] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 94] & ~reg_be))) | - (addr_hit[ 95] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 95] & ~reg_be))) | - (addr_hit[ 96] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 96] & ~reg_be))) | - (addr_hit[ 97] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 97] & ~reg_be))) | - (addr_hit[ 98] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 98] & ~reg_be))) | - (addr_hit[ 99] & (|(CACHEPOOL_PERIPHERAL_PERMIT[ 99] & ~reg_be))) | - (addr_hit[100] & (|(CACHEPOOL_PERIPHERAL_PERMIT[100] & ~reg_be))) | - (addr_hit[101] & (|(CACHEPOOL_PERIPHERAL_PERMIT[101] & ~reg_be))) | - (addr_hit[102] & (|(CACHEPOOL_PERIPHERAL_PERMIT[102] & ~reg_be))) | - (addr_hit[103] & (|(CACHEPOOL_PERIPHERAL_PERMIT[103] & ~reg_be))) | - (addr_hit[104] & (|(CACHEPOOL_PERIPHERAL_PERMIT[104] & ~reg_be))) | - (addr_hit[105] & (|(CACHEPOOL_PERIPHERAL_PERMIT[105] & ~reg_be))) | - (addr_hit[106] & (|(CACHEPOOL_PERIPHERAL_PERMIT[106] & ~reg_be))) | - (addr_hit[107] & (|(CACHEPOOL_PERIPHERAL_PERMIT[107] & ~reg_be))) | - (addr_hit[108] & (|(CACHEPOOL_PERIPHERAL_PERMIT[108] & ~reg_be))) | - (addr_hit[109] & (|(CACHEPOOL_PERIPHERAL_PERMIT[109] & ~reg_be))) | - (addr_hit[110] & (|(CACHEPOOL_PERIPHERAL_PERMIT[110] & ~reg_be))) | - (addr_hit[111] & (|(CACHEPOOL_PERIPHERAL_PERMIT[111] & ~reg_be))) | - (addr_hit[112] & (|(CACHEPOOL_PERIPHERAL_PERMIT[112] & ~reg_be))) | - (addr_hit[113] & (|(CACHEPOOL_PERIPHERAL_PERMIT[113] & ~reg_be))) | - (addr_hit[114] & (|(CACHEPOOL_PERIPHERAL_PERMIT[114] & ~reg_be))) | - (addr_hit[115] & (|(CACHEPOOL_PERIPHERAL_PERMIT[115] & ~reg_be))) | - (addr_hit[116] & (|(CACHEPOOL_PERIPHERAL_PERMIT[116] & ~reg_be))) | - (addr_hit[117] & (|(CACHEPOOL_PERIPHERAL_PERMIT[117] & ~reg_be))) | - (addr_hit[118] & (|(CACHEPOOL_PERIPHERAL_PERMIT[118] & ~reg_be))) | - (addr_hit[119] & (|(CACHEPOOL_PERIPHERAL_PERMIT[119] & ~reg_be))) | - (addr_hit[120] & (|(CACHEPOOL_PERIPHERAL_PERMIT[120] & ~reg_be))) | - (addr_hit[121] & (|(CACHEPOOL_PERIPHERAL_PERMIT[121] & ~reg_be))) | - (addr_hit[122] & (|(CACHEPOOL_PERIPHERAL_PERMIT[122] & ~reg_be))) | - (addr_hit[123] & (|(CACHEPOOL_PERIPHERAL_PERMIT[123] & ~reg_be))) | - (addr_hit[124] & (|(CACHEPOOL_PERIPHERAL_PERMIT[124] & ~reg_be))) | - (addr_hit[125] & (|(CACHEPOOL_PERIPHERAL_PERMIT[125] & ~reg_be))) | - (addr_hit[126] & (|(CACHEPOOL_PERIPHERAL_PERMIT[126] & ~reg_be))) | - (addr_hit[127] & (|(CACHEPOOL_PERIPHERAL_PERMIT[127] & ~reg_be))) | - (addr_hit[128] & (|(CACHEPOOL_PERIPHERAL_PERMIT[128] & ~reg_be))) | - (addr_hit[129] & (|(CACHEPOOL_PERIPHERAL_PERMIT[129] & ~reg_be))) | - (addr_hit[130] & (|(CACHEPOOL_PERIPHERAL_PERMIT[130] & ~reg_be))) | - (addr_hit[131] & (|(CACHEPOOL_PERIPHERAL_PERMIT[131] & ~reg_be))) | - (addr_hit[132] & (|(CACHEPOOL_PERIPHERAL_PERMIT[132] & ~reg_be))) | - (addr_hit[133] & (|(CACHEPOOL_PERIPHERAL_PERMIT[133] & ~reg_be))) | - (addr_hit[134] & (|(CACHEPOOL_PERIPHERAL_PERMIT[134] & ~reg_be))) | - (addr_hit[135] & (|(CACHEPOOL_PERIPHERAL_PERMIT[135] & ~reg_be))) | - (addr_hit[136] & (|(CACHEPOOL_PERIPHERAL_PERMIT[136] & ~reg_be))) | - (addr_hit[137] & (|(CACHEPOOL_PERIPHERAL_PERMIT[137] & ~reg_be))) | - (addr_hit[138] & (|(CACHEPOOL_PERIPHERAL_PERMIT[138] & ~reg_be))) | - (addr_hit[139] & (|(CACHEPOOL_PERIPHERAL_PERMIT[139] & ~reg_be))) | - (addr_hit[140] & (|(CACHEPOOL_PERIPHERAL_PERMIT[140] & ~reg_be))) | - (addr_hit[141] & (|(CACHEPOOL_PERIPHERAL_PERMIT[141] & ~reg_be))) | - (addr_hit[142] & (|(CACHEPOOL_PERIPHERAL_PERMIT[142] & ~reg_be))) | - (addr_hit[143] & (|(CACHEPOOL_PERIPHERAL_PERMIT[143] & ~reg_be))) | - (addr_hit[144] & (|(CACHEPOOL_PERIPHERAL_PERMIT[144] & ~reg_be))) | - (addr_hit[145] & (|(CACHEPOOL_PERIPHERAL_PERMIT[145] & ~reg_be))) | - (addr_hit[146] & (|(CACHEPOOL_PERIPHERAL_PERMIT[146] & ~reg_be))) | - (addr_hit[147] & (|(CACHEPOOL_PERIPHERAL_PERMIT[147] & ~reg_be))) | - (addr_hit[148] & (|(CACHEPOOL_PERIPHERAL_PERMIT[148] & ~reg_be))) | - (addr_hit[149] & (|(CACHEPOOL_PERIPHERAL_PERMIT[149] & ~reg_be))) | - (addr_hit[150] & (|(CACHEPOOL_PERIPHERAL_PERMIT[150] & ~reg_be))) | - (addr_hit[151] & (|(CACHEPOOL_PERIPHERAL_PERMIT[151] & ~reg_be))) | - (addr_hit[152] & (|(CACHEPOOL_PERIPHERAL_PERMIT[152] & ~reg_be))) | - (addr_hit[153] & (|(CACHEPOOL_PERIPHERAL_PERMIT[153] & ~reg_be))) | - (addr_hit[154] & (|(CACHEPOOL_PERIPHERAL_PERMIT[154] & ~reg_be))) | - (addr_hit[155] & (|(CACHEPOOL_PERIPHERAL_PERMIT[155] & ~reg_be))) | - (addr_hit[156] & (|(CACHEPOOL_PERIPHERAL_PERMIT[156] & ~reg_be))) | - (addr_hit[157] & (|(CACHEPOOL_PERIPHERAL_PERMIT[157] & ~reg_be))) | - (addr_hit[158] & (|(CACHEPOOL_PERIPHERAL_PERMIT[158] & ~reg_be))) | - (addr_hit[159] & (|(CACHEPOOL_PERIPHERAL_PERMIT[159] & ~reg_be))) | - (addr_hit[160] & (|(CACHEPOOL_PERIPHERAL_PERMIT[160] & ~reg_be))) | - (addr_hit[161] & (|(CACHEPOOL_PERIPHERAL_PERMIT[161] & ~reg_be))) | - (addr_hit[162] & (|(CACHEPOOL_PERIPHERAL_PERMIT[162] & ~reg_be))) | - (addr_hit[163] & (|(CACHEPOOL_PERIPHERAL_PERMIT[163] & ~reg_be))) | - (addr_hit[164] & (|(CACHEPOOL_PERIPHERAL_PERMIT[164] & ~reg_be))) | - (addr_hit[165] & (|(CACHEPOOL_PERIPHERAL_PERMIT[165] & ~reg_be))) | - (addr_hit[166] & (|(CACHEPOOL_PERIPHERAL_PERMIT[166] & ~reg_be))) | - (addr_hit[167] & (|(CACHEPOOL_PERIPHERAL_PERMIT[167] & ~reg_be))) | - (addr_hit[168] & (|(CACHEPOOL_PERIPHERAL_PERMIT[168] & ~reg_be))) | - (addr_hit[169] & (|(CACHEPOOL_PERIPHERAL_PERMIT[169] & ~reg_be))) | - (addr_hit[170] & (|(CACHEPOOL_PERIPHERAL_PERMIT[170] & ~reg_be))) | - (addr_hit[171] & (|(CACHEPOOL_PERIPHERAL_PERMIT[171] & ~reg_be))) | - (addr_hit[172] & (|(CACHEPOOL_PERIPHERAL_PERMIT[172] & ~reg_be))) | - (addr_hit[173] & (|(CACHEPOOL_PERIPHERAL_PERMIT[173] & ~reg_be))) | - (addr_hit[174] & (|(CACHEPOOL_PERIPHERAL_PERMIT[174] & ~reg_be))) | - (addr_hit[175] & (|(CACHEPOOL_PERIPHERAL_PERMIT[175] & ~reg_be))) | - (addr_hit[176] & (|(CACHEPOOL_PERIPHERAL_PERMIT[176] & ~reg_be))) | - (addr_hit[177] & (|(CACHEPOOL_PERIPHERAL_PERMIT[177] & ~reg_be))) | - (addr_hit[178] & (|(CACHEPOOL_PERIPHERAL_PERMIT[178] & ~reg_be))) | - (addr_hit[179] & (|(CACHEPOOL_PERIPHERAL_PERMIT[179] & ~reg_be))) | - (addr_hit[180] & (|(CACHEPOOL_PERIPHERAL_PERMIT[180] & ~reg_be))) | - (addr_hit[181] & (|(CACHEPOOL_PERIPHERAL_PERMIT[181] & ~reg_be))) | - (addr_hit[182] & (|(CACHEPOOL_PERIPHERAL_PERMIT[182] & ~reg_be))) | - (addr_hit[183] & (|(CACHEPOOL_PERIPHERAL_PERMIT[183] & ~reg_be))) | - (addr_hit[184] & (|(CACHEPOOL_PERIPHERAL_PERMIT[184] & ~reg_be))) | - (addr_hit[185] & (|(CACHEPOOL_PERIPHERAL_PERMIT[185] & ~reg_be))) | - (addr_hit[186] & (|(CACHEPOOL_PERIPHERAL_PERMIT[186] & ~reg_be))) | - (addr_hit[187] & (|(CACHEPOOL_PERIPHERAL_PERMIT[187] & ~reg_be))) | - (addr_hit[188] & (|(CACHEPOOL_PERIPHERAL_PERMIT[188] & ~reg_be))) | - (addr_hit[189] & (|(CACHEPOOL_PERIPHERAL_PERMIT[189] & ~reg_be))) | - (addr_hit[190] & (|(CACHEPOOL_PERIPHERAL_PERMIT[190] & ~reg_be))) | - (addr_hit[191] & (|(CACHEPOOL_PERIPHERAL_PERMIT[191] & ~reg_be))) | - (addr_hit[192] & (|(CACHEPOOL_PERIPHERAL_PERMIT[192] & ~reg_be))) | - (addr_hit[193] & (|(CACHEPOOL_PERIPHERAL_PERMIT[193] & ~reg_be))) | - (addr_hit[194] & (|(CACHEPOOL_PERIPHERAL_PERMIT[194] & ~reg_be))) | - (addr_hit[195] & (|(CACHEPOOL_PERIPHERAL_PERMIT[195] & ~reg_be))) | - (addr_hit[196] & (|(CACHEPOOL_PERIPHERAL_PERMIT[196] & ~reg_be))) | - (addr_hit[197] & (|(CACHEPOOL_PERIPHERAL_PERMIT[197] & ~reg_be))) | - (addr_hit[198] & (|(CACHEPOOL_PERIPHERAL_PERMIT[198] & ~reg_be))) | - (addr_hit[199] & (|(CACHEPOOL_PERIPHERAL_PERMIT[199] & ~reg_be))) | - (addr_hit[200] & (|(CACHEPOOL_PERIPHERAL_PERMIT[200] & ~reg_be))) | - (addr_hit[201] & (|(CACHEPOOL_PERIPHERAL_PERMIT[201] & ~reg_be))) | - (addr_hit[202] & (|(CACHEPOOL_PERIPHERAL_PERMIT[202] & ~reg_be))) | - (addr_hit[203] & (|(CACHEPOOL_PERIPHERAL_PERMIT[203] & ~reg_be))) | - (addr_hit[204] & (|(CACHEPOOL_PERIPHERAL_PERMIT[204] & ~reg_be))) | - (addr_hit[205] & (|(CACHEPOOL_PERIPHERAL_PERMIT[205] & ~reg_be))) | - (addr_hit[206] & (|(CACHEPOOL_PERIPHERAL_PERMIT[206] & ~reg_be))) | - (addr_hit[207] & (|(CACHEPOOL_PERIPHERAL_PERMIT[207] & ~reg_be))) | - (addr_hit[208] & (|(CACHEPOOL_PERIPHERAL_PERMIT[208] & ~reg_be))) | - (addr_hit[209] & (|(CACHEPOOL_PERIPHERAL_PERMIT[209] & ~reg_be))) | - (addr_hit[210] & (|(CACHEPOOL_PERIPHERAL_PERMIT[210] & ~reg_be))) | - (addr_hit[211] & (|(CACHEPOOL_PERIPHERAL_PERMIT[211] & ~reg_be))) | - (addr_hit[212] & (|(CACHEPOOL_PERIPHERAL_PERMIT[212] & ~reg_be))) | - (addr_hit[213] & (|(CACHEPOOL_PERIPHERAL_PERMIT[213] & ~reg_be))) | - (addr_hit[214] & (|(CACHEPOOL_PERIPHERAL_PERMIT[214] & ~reg_be))) | - (addr_hit[215] & (|(CACHEPOOL_PERIPHERAL_PERMIT[215] & ~reg_be))) | - (addr_hit[216] & (|(CACHEPOOL_PERIPHERAL_PERMIT[216] & ~reg_be))) | - (addr_hit[217] & (|(CACHEPOOL_PERIPHERAL_PERMIT[217] & ~reg_be))) | - (addr_hit[218] & (|(CACHEPOOL_PERIPHERAL_PERMIT[218] & ~reg_be))) | - (addr_hit[219] & (|(CACHEPOOL_PERIPHERAL_PERMIT[219] & ~reg_be))) | - (addr_hit[220] & (|(CACHEPOOL_PERIPHERAL_PERMIT[220] & ~reg_be))) | - (addr_hit[221] & (|(CACHEPOOL_PERIPHERAL_PERMIT[221] & ~reg_be))) | - (addr_hit[222] & (|(CACHEPOOL_PERIPHERAL_PERMIT[222] & ~reg_be))) | - (addr_hit[223] & (|(CACHEPOOL_PERIPHERAL_PERMIT[223] & ~reg_be))) | - (addr_hit[224] & (|(CACHEPOOL_PERIPHERAL_PERMIT[224] & ~reg_be))) | - (addr_hit[225] & (|(CACHEPOOL_PERIPHERAL_PERMIT[225] & ~reg_be))) | - (addr_hit[226] & (|(CACHEPOOL_PERIPHERAL_PERMIT[226] & ~reg_be))) | - (addr_hit[227] & (|(CACHEPOOL_PERIPHERAL_PERMIT[227] & ~reg_be))) | - (addr_hit[228] & (|(CACHEPOOL_PERIPHERAL_PERMIT[228] & ~reg_be))) | - (addr_hit[229] & (|(CACHEPOOL_PERIPHERAL_PERMIT[229] & ~reg_be))) | - (addr_hit[230] & (|(CACHEPOOL_PERIPHERAL_PERMIT[230] & ~reg_be))) | - (addr_hit[231] & (|(CACHEPOOL_PERIPHERAL_PERMIT[231] & ~reg_be))) | - (addr_hit[232] & (|(CACHEPOOL_PERIPHERAL_PERMIT[232] & ~reg_be))) | - (addr_hit[233] & (|(CACHEPOOL_PERIPHERAL_PERMIT[233] & ~reg_be))) | - (addr_hit[234] & (|(CACHEPOOL_PERIPHERAL_PERMIT[234] & ~reg_be))) | - (addr_hit[235] & (|(CACHEPOOL_PERIPHERAL_PERMIT[235] & ~reg_be))) | - (addr_hit[236] & (|(CACHEPOOL_PERIPHERAL_PERMIT[236] & ~reg_be))) | - (addr_hit[237] & (|(CACHEPOOL_PERIPHERAL_PERMIT[237] & ~reg_be))) | - (addr_hit[238] & (|(CACHEPOOL_PERIPHERAL_PERMIT[238] & ~reg_be))) | - (addr_hit[239] & (|(CACHEPOOL_PERIPHERAL_PERMIT[239] & ~reg_be))) | - (addr_hit[240] & (|(CACHEPOOL_PERIPHERAL_PERMIT[240] & ~reg_be))) | - (addr_hit[241] & (|(CACHEPOOL_PERIPHERAL_PERMIT[241] & ~reg_be))) | - (addr_hit[242] & (|(CACHEPOOL_PERIPHERAL_PERMIT[242] & ~reg_be))) | - (addr_hit[243] & (|(CACHEPOOL_PERIPHERAL_PERMIT[243] & ~reg_be))) | - (addr_hit[244] & (|(CACHEPOOL_PERIPHERAL_PERMIT[244] & ~reg_be))) | - (addr_hit[245] & (|(CACHEPOOL_PERIPHERAL_PERMIT[245] & ~reg_be))) | - (addr_hit[246] & (|(CACHEPOOL_PERIPHERAL_PERMIT[246] & ~reg_be))) | - (addr_hit[247] & (|(CACHEPOOL_PERIPHERAL_PERMIT[247] & ~reg_be))) | - (addr_hit[248] & (|(CACHEPOOL_PERIPHERAL_PERMIT[248] & ~reg_be))) | - (addr_hit[249] & (|(CACHEPOOL_PERIPHERAL_PERMIT[249] & ~reg_be))) | - (addr_hit[250] & (|(CACHEPOOL_PERIPHERAL_PERMIT[250] & ~reg_be))) | - (addr_hit[251] & (|(CACHEPOOL_PERIPHERAL_PERMIT[251] & ~reg_be))) | - (addr_hit[252] & (|(CACHEPOOL_PERIPHERAL_PERMIT[252] & ~reg_be))) | - (addr_hit[253] & (|(CACHEPOOL_PERIPHERAL_PERMIT[253] & ~reg_be))) | - (addr_hit[254] & (|(CACHEPOOL_PERIPHERAL_PERMIT[254] & ~reg_be))) | - (addr_hit[255] & (|(CACHEPOOL_PERIPHERAL_PERMIT[255] & ~reg_be))) | - (addr_hit[256] & (|(CACHEPOOL_PERIPHERAL_PERMIT[256] & ~reg_be))) | - (addr_hit[257] & (|(CACHEPOOL_PERIPHERAL_PERMIT[257] & ~reg_be))) | - (addr_hit[258] & (|(CACHEPOOL_PERIPHERAL_PERMIT[258] & ~reg_be))) | - (addr_hit[259] & (|(CACHEPOOL_PERIPHERAL_PERMIT[259] & ~reg_be))) | - (addr_hit[260] & (|(CACHEPOOL_PERIPHERAL_PERMIT[260] & ~reg_be))) | - (addr_hit[261] & (|(CACHEPOOL_PERIPHERAL_PERMIT[261] & ~reg_be))) | - (addr_hit[262] & (|(CACHEPOOL_PERIPHERAL_PERMIT[262] & ~reg_be))) | - (addr_hit[263] & (|(CACHEPOOL_PERIPHERAL_PERMIT[263] & ~reg_be))) | - (addr_hit[264] & (|(CACHEPOOL_PERIPHERAL_PERMIT[264] & ~reg_be))) | - (addr_hit[265] & (|(CACHEPOOL_PERIPHERAL_PERMIT[265] & ~reg_be))) | - (addr_hit[266] & (|(CACHEPOOL_PERIPHERAL_PERMIT[266] & ~reg_be))) | - (addr_hit[267] & (|(CACHEPOOL_PERIPHERAL_PERMIT[267] & ~reg_be))) | - (addr_hit[268] & (|(CACHEPOOL_PERIPHERAL_PERMIT[268] & ~reg_be))) | - (addr_hit[269] & (|(CACHEPOOL_PERIPHERAL_PERMIT[269] & ~reg_be))) | - (addr_hit[270] & (|(CACHEPOOL_PERIPHERAL_PERMIT[270] & ~reg_be))) | - (addr_hit[271] & (|(CACHEPOOL_PERIPHERAL_PERMIT[271] & ~reg_be))) | - (addr_hit[272] & (|(CACHEPOOL_PERIPHERAL_PERMIT[272] & ~reg_be))))); - end + addr_hit[489]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_216_qs; + end - assign hw_barrier_re = addr_hit[0] & reg_re & !reg_error; + addr_hit[490]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_217_qs; + end - assign icache_prefetch_enable_we = addr_hit[1] & reg_we & !reg_error; - assign icache_prefetch_enable_wd = reg_wdata[0]; + addr_hit[491]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_218_qs; + end - assign spatz_status_we = addr_hit[2] & reg_we & !reg_error; - assign spatz_status_wd = reg_wdata[0]; + addr_hit[492]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_219_qs; + end - assign spatz_cycle_we = addr_hit[3] & reg_we & !reg_error; - assign spatz_cycle_wd = reg_wdata[31:0]; + addr_hit[493]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_220_qs; + end - assign cluster_boot_control_we = addr_hit[4] & reg_we & !reg_error; - assign cluster_boot_control_wd = reg_wdata[31:0]; + addr_hit[494]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_221_qs; + end - assign cluster_eoc_exit_we = addr_hit[5] & reg_we & !reg_error; - assign cluster_eoc_exit_wd = reg_wdata[3:0]; + addr_hit[495]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_222_qs; + end - assign cfg_l1d_spm_we = addr_hit[6] & reg_we & !reg_error; - assign cfg_l1d_spm_wd = reg_wdata[9:0]; + addr_hit[496]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_223_qs; + end - assign cfg_l1d_insn_we = addr_hit[7] & reg_we & !reg_error; - assign cfg_l1d_insn_wd = reg_wdata[1:0]; + addr_hit[497]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_224_qs; + end - assign cfg_l1d_tile_sel_0_we = addr_hit[8] & reg_we & !reg_error; - assign cfg_l1d_tile_sel_0_wd = reg_wdata[31:0]; + addr_hit[498]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_225_qs; + end - assign cfg_l1d_tile_sel_1_we = addr_hit[9] & reg_we & !reg_error; - assign cfg_l1d_tile_sel_1_wd = reg_wdata[31:0]; + addr_hit[499]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_226_qs; + end - assign l1d_spm_commit_we = addr_hit[10] & reg_we & !reg_error; - assign l1d_spm_commit_wd = reg_wdata[0]; + addr_hit[500]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_227_qs; + end - assign l1d_insn_commit_we = addr_hit[11] & reg_we & !reg_error; - assign l1d_insn_commit_wd = reg_wdata[0]; + addr_hit[501]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_228_qs; + end - assign l1d_flush_status_re = addr_hit[12] & reg_re & !reg_error; + addr_hit[502]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_229_qs; + end - assign l1d_private_we = addr_hit[13] & reg_we & !reg_error; - assign l1d_private_wd = reg_wdata[3:0]; + addr_hit[503]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_230_qs; + end - assign l1d_addr_we = addr_hit[14] & reg_we & !reg_error; - assign l1d_addr_wd = reg_wdata[31:0]; + addr_hit[504]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_231_qs; + end - assign xbar_offset_we = addr_hit[15] & reg_we & !reg_error; - assign xbar_offset_wd = reg_wdata[4:0]; + addr_hit[505]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_232_qs; + end - assign xbar_offset_commit_we = addr_hit[16] & reg_we & !reg_error; - assign xbar_offset_commit_wd = reg_wdata[0]; + addr_hit[506]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_233_qs; + end - assign cfg_lp1_cmo_0_we = addr_hit[17] & reg_we & !reg_error; - assign cfg_lp1_cmo_0_wd = reg_wdata[2:0]; + addr_hit[507]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_234_qs; + end - assign cfg_lp1_cmo_1_we = addr_hit[18] & reg_we & !reg_error; - assign cfg_lp1_cmo_1_wd = reg_wdata[2:0]; + addr_hit[508]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_235_qs; + end - assign cfg_lp1_cmo_2_we = addr_hit[19] & reg_we & !reg_error; - assign cfg_lp1_cmo_2_wd = reg_wdata[2:0]; + addr_hit[509]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_236_qs; + end - assign cfg_lp1_cmo_3_we = addr_hit[20] & reg_we & !reg_error; - assign cfg_lp1_cmo_3_wd = reg_wdata[2:0]; + addr_hit[510]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_237_qs; + end - assign cfg_lp1_cmo_4_we = addr_hit[21] & reg_we & !reg_error; - assign cfg_lp1_cmo_4_wd = reg_wdata[2:0]; + addr_hit[511]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_238_qs; + end - assign cfg_lp1_cmo_5_we = addr_hit[22] & reg_we & !reg_error; - assign cfg_lp1_cmo_5_wd = reg_wdata[2:0]; + addr_hit[512]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_239_qs; + end - assign cfg_lp1_cmo_6_we = addr_hit[23] & reg_we & !reg_error; - assign cfg_lp1_cmo_6_wd = reg_wdata[2:0]; + addr_hit[513]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_240_qs; + end - assign cfg_lp1_cmo_7_we = addr_hit[24] & reg_we & !reg_error; - assign cfg_lp1_cmo_7_wd = reg_wdata[2:0]; + addr_hit[514]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_241_qs; + end - assign cfg_lp1_cmo_8_we = addr_hit[25] & reg_we & !reg_error; - assign cfg_lp1_cmo_8_wd = reg_wdata[2:0]; + addr_hit[515]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_242_qs; + end - assign cfg_lp1_cmo_9_we = addr_hit[26] & reg_we & !reg_error; - assign cfg_lp1_cmo_9_wd = reg_wdata[2:0]; + addr_hit[516]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_243_qs; + end - assign cfg_lp1_cmo_10_we = addr_hit[27] & reg_we & !reg_error; - assign cfg_lp1_cmo_10_wd = reg_wdata[2:0]; + addr_hit[517]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_244_qs; + end - assign cfg_lp1_cmo_11_we = addr_hit[28] & reg_we & !reg_error; - assign cfg_lp1_cmo_11_wd = reg_wdata[2:0]; + addr_hit[518]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_245_qs; + end - assign cfg_lp1_cmo_12_we = addr_hit[29] & reg_we & !reg_error; - assign cfg_lp1_cmo_12_wd = reg_wdata[2:0]; + addr_hit[519]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_246_qs; + end - assign cfg_lp1_cmo_13_we = addr_hit[30] & reg_we & !reg_error; - assign cfg_lp1_cmo_13_wd = reg_wdata[2:0]; + addr_hit[520]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_247_qs; + end - assign cfg_lp1_cmo_14_we = addr_hit[31] & reg_we & !reg_error; - assign cfg_lp1_cmo_14_wd = reg_wdata[2:0]; + addr_hit[521]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_248_qs; + end - assign cfg_lp1_cmo_15_we = addr_hit[32] & reg_we & !reg_error; - assign cfg_lp1_cmo_15_wd = reg_wdata[2:0]; + addr_hit[522]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_249_qs; + end - assign cfg_lp1_cmo_16_we = addr_hit[33] & reg_we & !reg_error; - assign cfg_lp1_cmo_16_wd = reg_wdata[2:0]; + addr_hit[523]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_250_qs; + end - assign cfg_lp1_cmo_17_we = addr_hit[34] & reg_we & !reg_error; - assign cfg_lp1_cmo_17_wd = reg_wdata[2:0]; + addr_hit[524]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_251_qs; + end - assign cfg_lp1_cmo_18_we = addr_hit[35] & reg_we & !reg_error; - assign cfg_lp1_cmo_18_wd = reg_wdata[2:0]; + addr_hit[525]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_252_qs; + end - assign cfg_lp1_cmo_19_we = addr_hit[36] & reg_we & !reg_error; - assign cfg_lp1_cmo_19_wd = reg_wdata[2:0]; + addr_hit[526]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_253_qs; + end - assign cfg_lp1_cmo_20_we = addr_hit[37] & reg_we & !reg_error; - assign cfg_lp1_cmo_20_wd = reg_wdata[2:0]; + addr_hit[527]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_254_qs; + end - assign cfg_lp1_cmo_21_we = addr_hit[38] & reg_we & !reg_error; - assign cfg_lp1_cmo_21_wd = reg_wdata[2:0]; + addr_hit[528]: begin + reg_rdata_next[31:0] = cfg_lp1_cmo_addr_255_qs; + end - assign cfg_lp1_cmo_22_we = addr_hit[39] & reg_we & !reg_error; - assign cfg_lp1_cmo_22_wd = reg_wdata[2:0]; + addr_hit[529]: begin + reg_rdata_next[0] = lp1_cmo_commit_0_qs; + end - assign cfg_lp1_cmo_23_we = addr_hit[40] & reg_we & !reg_error; - assign cfg_lp1_cmo_23_wd = reg_wdata[2:0]; + addr_hit[530]: begin + reg_rdata_next[0] = lp1_cmo_commit_1_qs; + end - assign cfg_lp1_cmo_24_we = addr_hit[41] & reg_we & !reg_error; - assign cfg_lp1_cmo_24_wd = reg_wdata[2:0]; + addr_hit[531]: begin + reg_rdata_next[0] = lp1_cmo_commit_2_qs; + end - assign cfg_lp1_cmo_25_we = addr_hit[42] & reg_we & !reg_error; - assign cfg_lp1_cmo_25_wd = reg_wdata[2:0]; + addr_hit[532]: begin + reg_rdata_next[0] = lp1_cmo_commit_3_qs; + end - assign cfg_lp1_cmo_26_we = addr_hit[43] & reg_we & !reg_error; - assign cfg_lp1_cmo_26_wd = reg_wdata[2:0]; + addr_hit[533]: begin + reg_rdata_next[0] = lp1_cmo_commit_4_qs; + end - assign cfg_lp1_cmo_27_we = addr_hit[44] & reg_we & !reg_error; - assign cfg_lp1_cmo_27_wd = reg_wdata[2:0]; + addr_hit[534]: begin + reg_rdata_next[0] = lp1_cmo_commit_5_qs; + end - assign cfg_lp1_cmo_28_we = addr_hit[45] & reg_we & !reg_error; - assign cfg_lp1_cmo_28_wd = reg_wdata[2:0]; + addr_hit[535]: begin + reg_rdata_next[0] = lp1_cmo_commit_6_qs; + end - assign cfg_lp1_cmo_29_we = addr_hit[46] & reg_we & !reg_error; - assign cfg_lp1_cmo_29_wd = reg_wdata[2:0]; + addr_hit[536]: begin + reg_rdata_next[0] = lp1_cmo_commit_7_qs; + end - assign cfg_lp1_cmo_30_we = addr_hit[47] & reg_we & !reg_error; - assign cfg_lp1_cmo_30_wd = reg_wdata[2:0]; + addr_hit[537]: begin + reg_rdata_next[0] = lp1_cmo_commit_8_qs; + end - assign cfg_lp1_cmo_31_we = addr_hit[48] & reg_we & !reg_error; - assign cfg_lp1_cmo_31_wd = reg_wdata[2:0]; + addr_hit[538]: begin + reg_rdata_next[0] = lp1_cmo_commit_9_qs; + end - assign cfg_lp1_cmo_32_we = addr_hit[49] & reg_we & !reg_error; - assign cfg_lp1_cmo_32_wd = reg_wdata[2:0]; + addr_hit[539]: begin + reg_rdata_next[0] = lp1_cmo_commit_10_qs; + end - assign cfg_lp1_cmo_33_we = addr_hit[50] & reg_we & !reg_error; - assign cfg_lp1_cmo_33_wd = reg_wdata[2:0]; + addr_hit[540]: begin + reg_rdata_next[0] = lp1_cmo_commit_11_qs; + end - assign cfg_lp1_cmo_34_we = addr_hit[51] & reg_we & !reg_error; - assign cfg_lp1_cmo_34_wd = reg_wdata[2:0]; + addr_hit[541]: begin + reg_rdata_next[0] = lp1_cmo_commit_12_qs; + end - assign cfg_lp1_cmo_35_we = addr_hit[52] & reg_we & !reg_error; - assign cfg_lp1_cmo_35_wd = reg_wdata[2:0]; + addr_hit[542]: begin + reg_rdata_next[0] = lp1_cmo_commit_13_qs; + end - assign cfg_lp1_cmo_36_we = addr_hit[53] & reg_we & !reg_error; - assign cfg_lp1_cmo_36_wd = reg_wdata[2:0]; + addr_hit[543]: begin + reg_rdata_next[0] = lp1_cmo_commit_14_qs; + end - assign cfg_lp1_cmo_37_we = addr_hit[54] & reg_we & !reg_error; - assign cfg_lp1_cmo_37_wd = reg_wdata[2:0]; + addr_hit[544]: begin + reg_rdata_next[0] = lp1_cmo_commit_15_qs; + end - assign cfg_lp1_cmo_38_we = addr_hit[55] & reg_we & !reg_error; - assign cfg_lp1_cmo_38_wd = reg_wdata[2:0]; + addr_hit[545]: begin + reg_rdata_next[0] = lp1_cmo_commit_16_qs; + end - assign cfg_lp1_cmo_39_we = addr_hit[56] & reg_we & !reg_error; - assign cfg_lp1_cmo_39_wd = reg_wdata[2:0]; + addr_hit[546]: begin + reg_rdata_next[0] = lp1_cmo_commit_17_qs; + end - assign cfg_lp1_cmo_40_we = addr_hit[57] & reg_we & !reg_error; - assign cfg_lp1_cmo_40_wd = reg_wdata[2:0]; + addr_hit[547]: begin + reg_rdata_next[0] = lp1_cmo_commit_18_qs; + end - assign cfg_lp1_cmo_41_we = addr_hit[58] & reg_we & !reg_error; - assign cfg_lp1_cmo_41_wd = reg_wdata[2:0]; + addr_hit[548]: begin + reg_rdata_next[0] = lp1_cmo_commit_19_qs; + end - assign cfg_lp1_cmo_42_we = addr_hit[59] & reg_we & !reg_error; - assign cfg_lp1_cmo_42_wd = reg_wdata[2:0]; + addr_hit[549]: begin + reg_rdata_next[0] = lp1_cmo_commit_20_qs; + end - assign cfg_lp1_cmo_43_we = addr_hit[60] & reg_we & !reg_error; - assign cfg_lp1_cmo_43_wd = reg_wdata[2:0]; + addr_hit[550]: begin + reg_rdata_next[0] = lp1_cmo_commit_21_qs; + end - assign cfg_lp1_cmo_44_we = addr_hit[61] & reg_we & !reg_error; - assign cfg_lp1_cmo_44_wd = reg_wdata[2:0]; + addr_hit[551]: begin + reg_rdata_next[0] = lp1_cmo_commit_22_qs; + end - assign cfg_lp1_cmo_45_we = addr_hit[62] & reg_we & !reg_error; - assign cfg_lp1_cmo_45_wd = reg_wdata[2:0]; + addr_hit[552]: begin + reg_rdata_next[0] = lp1_cmo_commit_23_qs; + end - assign cfg_lp1_cmo_46_we = addr_hit[63] & reg_we & !reg_error; - assign cfg_lp1_cmo_46_wd = reg_wdata[2:0]; + addr_hit[553]: begin + reg_rdata_next[0] = lp1_cmo_commit_24_qs; + end + + addr_hit[554]: begin + reg_rdata_next[0] = lp1_cmo_commit_25_qs; + end + + addr_hit[555]: begin + reg_rdata_next[0] = lp1_cmo_commit_26_qs; + end + + addr_hit[556]: begin + reg_rdata_next[0] = lp1_cmo_commit_27_qs; + end + + addr_hit[557]: begin + reg_rdata_next[0] = lp1_cmo_commit_28_qs; + end - assign cfg_lp1_cmo_47_we = addr_hit[64] & reg_we & !reg_error; - assign cfg_lp1_cmo_47_wd = reg_wdata[2:0]; + addr_hit[558]: begin + reg_rdata_next[0] = lp1_cmo_commit_29_qs; + end - assign cfg_lp1_cmo_48_we = addr_hit[65] & reg_we & !reg_error; - assign cfg_lp1_cmo_48_wd = reg_wdata[2:0]; + addr_hit[559]: begin + reg_rdata_next[0] = lp1_cmo_commit_30_qs; + end - assign cfg_lp1_cmo_49_we = addr_hit[66] & reg_we & !reg_error; - assign cfg_lp1_cmo_49_wd = reg_wdata[2:0]; + addr_hit[560]: begin + reg_rdata_next[0] = lp1_cmo_commit_31_qs; + end - assign cfg_lp1_cmo_50_we = addr_hit[67] & reg_we & !reg_error; - assign cfg_lp1_cmo_50_wd = reg_wdata[2:0]; + addr_hit[561]: begin + reg_rdata_next[0] = lp1_cmo_commit_32_qs; + end - assign cfg_lp1_cmo_51_we = addr_hit[68] & reg_we & !reg_error; - assign cfg_lp1_cmo_51_wd = reg_wdata[2:0]; + addr_hit[562]: begin + reg_rdata_next[0] = lp1_cmo_commit_33_qs; + end - assign cfg_lp1_cmo_52_we = addr_hit[69] & reg_we & !reg_error; - assign cfg_lp1_cmo_52_wd = reg_wdata[2:0]; + addr_hit[563]: begin + reg_rdata_next[0] = lp1_cmo_commit_34_qs; + end - assign cfg_lp1_cmo_53_we = addr_hit[70] & reg_we & !reg_error; - assign cfg_lp1_cmo_53_wd = reg_wdata[2:0]; + addr_hit[564]: begin + reg_rdata_next[0] = lp1_cmo_commit_35_qs; + end - assign cfg_lp1_cmo_54_we = addr_hit[71] & reg_we & !reg_error; - assign cfg_lp1_cmo_54_wd = reg_wdata[2:0]; + addr_hit[565]: begin + reg_rdata_next[0] = lp1_cmo_commit_36_qs; + end - assign cfg_lp1_cmo_55_we = addr_hit[72] & reg_we & !reg_error; - assign cfg_lp1_cmo_55_wd = reg_wdata[2:0]; + addr_hit[566]: begin + reg_rdata_next[0] = lp1_cmo_commit_37_qs; + end - assign cfg_lp1_cmo_56_we = addr_hit[73] & reg_we & !reg_error; - assign cfg_lp1_cmo_56_wd = reg_wdata[2:0]; + addr_hit[567]: begin + reg_rdata_next[0] = lp1_cmo_commit_38_qs; + end - assign cfg_lp1_cmo_57_we = addr_hit[74] & reg_we & !reg_error; - assign cfg_lp1_cmo_57_wd = reg_wdata[2:0]; + addr_hit[568]: begin + reg_rdata_next[0] = lp1_cmo_commit_39_qs; + end - assign cfg_lp1_cmo_58_we = addr_hit[75] & reg_we & !reg_error; - assign cfg_lp1_cmo_58_wd = reg_wdata[2:0]; + addr_hit[569]: begin + reg_rdata_next[0] = lp1_cmo_commit_40_qs; + end - assign cfg_lp1_cmo_59_we = addr_hit[76] & reg_we & !reg_error; - assign cfg_lp1_cmo_59_wd = reg_wdata[2:0]; + addr_hit[570]: begin + reg_rdata_next[0] = lp1_cmo_commit_41_qs; + end - assign cfg_lp1_cmo_60_we = addr_hit[77] & reg_we & !reg_error; - assign cfg_lp1_cmo_60_wd = reg_wdata[2:0]; + addr_hit[571]: begin + reg_rdata_next[0] = lp1_cmo_commit_42_qs; + end - assign cfg_lp1_cmo_61_we = addr_hit[78] & reg_we & !reg_error; - assign cfg_lp1_cmo_61_wd = reg_wdata[2:0]; + addr_hit[572]: begin + reg_rdata_next[0] = lp1_cmo_commit_43_qs; + end - assign cfg_lp1_cmo_62_we = addr_hit[79] & reg_we & !reg_error; - assign cfg_lp1_cmo_62_wd = reg_wdata[2:0]; + addr_hit[573]: begin + reg_rdata_next[0] = lp1_cmo_commit_44_qs; + end - assign cfg_lp1_cmo_63_we = addr_hit[80] & reg_we & !reg_error; - assign cfg_lp1_cmo_63_wd = reg_wdata[2:0]; + addr_hit[574]: begin + reg_rdata_next[0] = lp1_cmo_commit_45_qs; + end - assign cfg_lp1_cmo_addr_0_we = addr_hit[81] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_0_wd = reg_wdata[31:0]; + addr_hit[575]: begin + reg_rdata_next[0] = lp1_cmo_commit_46_qs; + end - assign cfg_lp1_cmo_addr_1_we = addr_hit[82] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_1_wd = reg_wdata[31:0]; + addr_hit[576]: begin + reg_rdata_next[0] = lp1_cmo_commit_47_qs; + end - assign cfg_lp1_cmo_addr_2_we = addr_hit[83] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_2_wd = reg_wdata[31:0]; + addr_hit[577]: begin + reg_rdata_next[0] = lp1_cmo_commit_48_qs; + end - assign cfg_lp1_cmo_addr_3_we = addr_hit[84] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_3_wd = reg_wdata[31:0]; + addr_hit[578]: begin + reg_rdata_next[0] = lp1_cmo_commit_49_qs; + end - assign cfg_lp1_cmo_addr_4_we = addr_hit[85] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_4_wd = reg_wdata[31:0]; + addr_hit[579]: begin + reg_rdata_next[0] = lp1_cmo_commit_50_qs; + end - assign cfg_lp1_cmo_addr_5_we = addr_hit[86] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_5_wd = reg_wdata[31:0]; + addr_hit[580]: begin + reg_rdata_next[0] = lp1_cmo_commit_51_qs; + end - assign cfg_lp1_cmo_addr_6_we = addr_hit[87] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_6_wd = reg_wdata[31:0]; + addr_hit[581]: begin + reg_rdata_next[0] = lp1_cmo_commit_52_qs; + end - assign cfg_lp1_cmo_addr_7_we = addr_hit[88] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_7_wd = reg_wdata[31:0]; + addr_hit[582]: begin + reg_rdata_next[0] = lp1_cmo_commit_53_qs; + end - assign cfg_lp1_cmo_addr_8_we = addr_hit[89] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_8_wd = reg_wdata[31:0]; + addr_hit[583]: begin + reg_rdata_next[0] = lp1_cmo_commit_54_qs; + end - assign cfg_lp1_cmo_addr_9_we = addr_hit[90] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_9_wd = reg_wdata[31:0]; + addr_hit[584]: begin + reg_rdata_next[0] = lp1_cmo_commit_55_qs; + end - assign cfg_lp1_cmo_addr_10_we = addr_hit[91] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_10_wd = reg_wdata[31:0]; + addr_hit[585]: begin + reg_rdata_next[0] = lp1_cmo_commit_56_qs; + end - assign cfg_lp1_cmo_addr_11_we = addr_hit[92] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_11_wd = reg_wdata[31:0]; + addr_hit[586]: begin + reg_rdata_next[0] = lp1_cmo_commit_57_qs; + end - assign cfg_lp1_cmo_addr_12_we = addr_hit[93] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_12_wd = reg_wdata[31:0]; + addr_hit[587]: begin + reg_rdata_next[0] = lp1_cmo_commit_58_qs; + end - assign cfg_lp1_cmo_addr_13_we = addr_hit[94] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_13_wd = reg_wdata[31:0]; + addr_hit[588]: begin + reg_rdata_next[0] = lp1_cmo_commit_59_qs; + end - assign cfg_lp1_cmo_addr_14_we = addr_hit[95] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_14_wd = reg_wdata[31:0]; + addr_hit[589]: begin + reg_rdata_next[0] = lp1_cmo_commit_60_qs; + end - assign cfg_lp1_cmo_addr_15_we = addr_hit[96] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_15_wd = reg_wdata[31:0]; + addr_hit[590]: begin + reg_rdata_next[0] = lp1_cmo_commit_61_qs; + end - assign cfg_lp1_cmo_addr_16_we = addr_hit[97] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_16_wd = reg_wdata[31:0]; + addr_hit[591]: begin + reg_rdata_next[0] = lp1_cmo_commit_62_qs; + end - assign cfg_lp1_cmo_addr_17_we = addr_hit[98] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_17_wd = reg_wdata[31:0]; + addr_hit[592]: begin + reg_rdata_next[0] = lp1_cmo_commit_63_qs; + end - assign cfg_lp1_cmo_addr_18_we = addr_hit[99] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_18_wd = reg_wdata[31:0]; + addr_hit[593]: begin + reg_rdata_next[0] = lp1_cmo_commit_64_qs; + end - assign cfg_lp1_cmo_addr_19_we = addr_hit[100] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_19_wd = reg_wdata[31:0]; + addr_hit[594]: begin + reg_rdata_next[0] = lp1_cmo_commit_65_qs; + end - assign cfg_lp1_cmo_addr_20_we = addr_hit[101] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_20_wd = reg_wdata[31:0]; + addr_hit[595]: begin + reg_rdata_next[0] = lp1_cmo_commit_66_qs; + end - assign cfg_lp1_cmo_addr_21_we = addr_hit[102] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_21_wd = reg_wdata[31:0]; + addr_hit[596]: begin + reg_rdata_next[0] = lp1_cmo_commit_67_qs; + end - assign cfg_lp1_cmo_addr_22_we = addr_hit[103] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_22_wd = reg_wdata[31:0]; + addr_hit[597]: begin + reg_rdata_next[0] = lp1_cmo_commit_68_qs; + end - assign cfg_lp1_cmo_addr_23_we = addr_hit[104] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_23_wd = reg_wdata[31:0]; + addr_hit[598]: begin + reg_rdata_next[0] = lp1_cmo_commit_69_qs; + end - assign cfg_lp1_cmo_addr_24_we = addr_hit[105] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_24_wd = reg_wdata[31:0]; + addr_hit[599]: begin + reg_rdata_next[0] = lp1_cmo_commit_70_qs; + end - assign cfg_lp1_cmo_addr_25_we = addr_hit[106] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_25_wd = reg_wdata[31:0]; + addr_hit[600]: begin + reg_rdata_next[0] = lp1_cmo_commit_71_qs; + end - assign cfg_lp1_cmo_addr_26_we = addr_hit[107] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_26_wd = reg_wdata[31:0]; + addr_hit[601]: begin + reg_rdata_next[0] = lp1_cmo_commit_72_qs; + end - assign cfg_lp1_cmo_addr_27_we = addr_hit[108] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_27_wd = reg_wdata[31:0]; + addr_hit[602]: begin + reg_rdata_next[0] = lp1_cmo_commit_73_qs; + end - assign cfg_lp1_cmo_addr_28_we = addr_hit[109] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_28_wd = reg_wdata[31:0]; + addr_hit[603]: begin + reg_rdata_next[0] = lp1_cmo_commit_74_qs; + end - assign cfg_lp1_cmo_addr_29_we = addr_hit[110] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_29_wd = reg_wdata[31:0]; + addr_hit[604]: begin + reg_rdata_next[0] = lp1_cmo_commit_75_qs; + end - assign cfg_lp1_cmo_addr_30_we = addr_hit[111] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_30_wd = reg_wdata[31:0]; + addr_hit[605]: begin + reg_rdata_next[0] = lp1_cmo_commit_76_qs; + end - assign cfg_lp1_cmo_addr_31_we = addr_hit[112] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_31_wd = reg_wdata[31:0]; + addr_hit[606]: begin + reg_rdata_next[0] = lp1_cmo_commit_77_qs; + end - assign cfg_lp1_cmo_addr_32_we = addr_hit[113] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_32_wd = reg_wdata[31:0]; + addr_hit[607]: begin + reg_rdata_next[0] = lp1_cmo_commit_78_qs; + end - assign cfg_lp1_cmo_addr_33_we = addr_hit[114] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_33_wd = reg_wdata[31:0]; + addr_hit[608]: begin + reg_rdata_next[0] = lp1_cmo_commit_79_qs; + end - assign cfg_lp1_cmo_addr_34_we = addr_hit[115] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_34_wd = reg_wdata[31:0]; + addr_hit[609]: begin + reg_rdata_next[0] = lp1_cmo_commit_80_qs; + end - assign cfg_lp1_cmo_addr_35_we = addr_hit[116] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_35_wd = reg_wdata[31:0]; + addr_hit[610]: begin + reg_rdata_next[0] = lp1_cmo_commit_81_qs; + end - assign cfg_lp1_cmo_addr_36_we = addr_hit[117] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_36_wd = reg_wdata[31:0]; + addr_hit[611]: begin + reg_rdata_next[0] = lp1_cmo_commit_82_qs; + end - assign cfg_lp1_cmo_addr_37_we = addr_hit[118] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_37_wd = reg_wdata[31:0]; + addr_hit[612]: begin + reg_rdata_next[0] = lp1_cmo_commit_83_qs; + end - assign cfg_lp1_cmo_addr_38_we = addr_hit[119] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_38_wd = reg_wdata[31:0]; + addr_hit[613]: begin + reg_rdata_next[0] = lp1_cmo_commit_84_qs; + end - assign cfg_lp1_cmo_addr_39_we = addr_hit[120] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_39_wd = reg_wdata[31:0]; + addr_hit[614]: begin + reg_rdata_next[0] = lp1_cmo_commit_85_qs; + end - assign cfg_lp1_cmo_addr_40_we = addr_hit[121] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_40_wd = reg_wdata[31:0]; + addr_hit[615]: begin + reg_rdata_next[0] = lp1_cmo_commit_86_qs; + end - assign cfg_lp1_cmo_addr_41_we = addr_hit[122] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_41_wd = reg_wdata[31:0]; + addr_hit[616]: begin + reg_rdata_next[0] = lp1_cmo_commit_87_qs; + end - assign cfg_lp1_cmo_addr_42_we = addr_hit[123] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_42_wd = reg_wdata[31:0]; + addr_hit[617]: begin + reg_rdata_next[0] = lp1_cmo_commit_88_qs; + end - assign cfg_lp1_cmo_addr_43_we = addr_hit[124] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_43_wd = reg_wdata[31:0]; + addr_hit[618]: begin + reg_rdata_next[0] = lp1_cmo_commit_89_qs; + end - assign cfg_lp1_cmo_addr_44_we = addr_hit[125] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_44_wd = reg_wdata[31:0]; + addr_hit[619]: begin + reg_rdata_next[0] = lp1_cmo_commit_90_qs; + end - assign cfg_lp1_cmo_addr_45_we = addr_hit[126] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_45_wd = reg_wdata[31:0]; + addr_hit[620]: begin + reg_rdata_next[0] = lp1_cmo_commit_91_qs; + end - assign cfg_lp1_cmo_addr_46_we = addr_hit[127] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_46_wd = reg_wdata[31:0]; + addr_hit[621]: begin + reg_rdata_next[0] = lp1_cmo_commit_92_qs; + end - assign cfg_lp1_cmo_addr_47_we = addr_hit[128] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_47_wd = reg_wdata[31:0]; + addr_hit[622]: begin + reg_rdata_next[0] = lp1_cmo_commit_93_qs; + end - assign cfg_lp1_cmo_addr_48_we = addr_hit[129] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_48_wd = reg_wdata[31:0]; + addr_hit[623]: begin + reg_rdata_next[0] = lp1_cmo_commit_94_qs; + end - assign cfg_lp1_cmo_addr_49_we = addr_hit[130] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_49_wd = reg_wdata[31:0]; + addr_hit[624]: begin + reg_rdata_next[0] = lp1_cmo_commit_95_qs; + end - assign cfg_lp1_cmo_addr_50_we = addr_hit[131] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_50_wd = reg_wdata[31:0]; + addr_hit[625]: begin + reg_rdata_next[0] = lp1_cmo_commit_96_qs; + end - assign cfg_lp1_cmo_addr_51_we = addr_hit[132] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_51_wd = reg_wdata[31:0]; + addr_hit[626]: begin + reg_rdata_next[0] = lp1_cmo_commit_97_qs; + end - assign cfg_lp1_cmo_addr_52_we = addr_hit[133] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_52_wd = reg_wdata[31:0]; + addr_hit[627]: begin + reg_rdata_next[0] = lp1_cmo_commit_98_qs; + end - assign cfg_lp1_cmo_addr_53_we = addr_hit[134] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_53_wd = reg_wdata[31:0]; + addr_hit[628]: begin + reg_rdata_next[0] = lp1_cmo_commit_99_qs; + end - assign cfg_lp1_cmo_addr_54_we = addr_hit[135] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_54_wd = reg_wdata[31:0]; + addr_hit[629]: begin + reg_rdata_next[0] = lp1_cmo_commit_100_qs; + end - assign cfg_lp1_cmo_addr_55_we = addr_hit[136] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_55_wd = reg_wdata[31:0]; + addr_hit[630]: begin + reg_rdata_next[0] = lp1_cmo_commit_101_qs; + end - assign cfg_lp1_cmo_addr_56_we = addr_hit[137] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_56_wd = reg_wdata[31:0]; + addr_hit[631]: begin + reg_rdata_next[0] = lp1_cmo_commit_102_qs; + end - assign cfg_lp1_cmo_addr_57_we = addr_hit[138] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_57_wd = reg_wdata[31:0]; + addr_hit[632]: begin + reg_rdata_next[0] = lp1_cmo_commit_103_qs; + end - assign cfg_lp1_cmo_addr_58_we = addr_hit[139] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_58_wd = reg_wdata[31:0]; + addr_hit[633]: begin + reg_rdata_next[0] = lp1_cmo_commit_104_qs; + end - assign cfg_lp1_cmo_addr_59_we = addr_hit[140] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_59_wd = reg_wdata[31:0]; + addr_hit[634]: begin + reg_rdata_next[0] = lp1_cmo_commit_105_qs; + end - assign cfg_lp1_cmo_addr_60_we = addr_hit[141] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_60_wd = reg_wdata[31:0]; + addr_hit[635]: begin + reg_rdata_next[0] = lp1_cmo_commit_106_qs; + end - assign cfg_lp1_cmo_addr_61_we = addr_hit[142] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_61_wd = reg_wdata[31:0]; + addr_hit[636]: begin + reg_rdata_next[0] = lp1_cmo_commit_107_qs; + end - assign cfg_lp1_cmo_addr_62_we = addr_hit[143] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_62_wd = reg_wdata[31:0]; + addr_hit[637]: begin + reg_rdata_next[0] = lp1_cmo_commit_108_qs; + end - assign cfg_lp1_cmo_addr_63_we = addr_hit[144] & reg_we & !reg_error; - assign cfg_lp1_cmo_addr_63_wd = reg_wdata[31:0]; + addr_hit[638]: begin + reg_rdata_next[0] = lp1_cmo_commit_109_qs; + end - assign lp1_cmo_commit_0_we = addr_hit[145] & reg_we & !reg_error; - assign lp1_cmo_commit_0_wd = reg_wdata[0]; + addr_hit[639]: begin + reg_rdata_next[0] = lp1_cmo_commit_110_qs; + end - assign lp1_cmo_commit_1_we = addr_hit[146] & reg_we & !reg_error; - assign lp1_cmo_commit_1_wd = reg_wdata[0]; + addr_hit[640]: begin + reg_rdata_next[0] = lp1_cmo_commit_111_qs; + end - assign lp1_cmo_commit_2_we = addr_hit[147] & reg_we & !reg_error; - assign lp1_cmo_commit_2_wd = reg_wdata[0]; + addr_hit[641]: begin + reg_rdata_next[0] = lp1_cmo_commit_112_qs; + end - assign lp1_cmo_commit_3_we = addr_hit[148] & reg_we & !reg_error; - assign lp1_cmo_commit_3_wd = reg_wdata[0]; + addr_hit[642]: begin + reg_rdata_next[0] = lp1_cmo_commit_113_qs; + end - assign lp1_cmo_commit_4_we = addr_hit[149] & reg_we & !reg_error; - assign lp1_cmo_commit_4_wd = reg_wdata[0]; + addr_hit[643]: begin + reg_rdata_next[0] = lp1_cmo_commit_114_qs; + end - assign lp1_cmo_commit_5_we = addr_hit[150] & reg_we & !reg_error; - assign lp1_cmo_commit_5_wd = reg_wdata[0]; + addr_hit[644]: begin + reg_rdata_next[0] = lp1_cmo_commit_115_qs; + end - assign lp1_cmo_commit_6_we = addr_hit[151] & reg_we & !reg_error; - assign lp1_cmo_commit_6_wd = reg_wdata[0]; + addr_hit[645]: begin + reg_rdata_next[0] = lp1_cmo_commit_116_qs; + end - assign lp1_cmo_commit_7_we = addr_hit[152] & reg_we & !reg_error; - assign lp1_cmo_commit_7_wd = reg_wdata[0]; + addr_hit[646]: begin + reg_rdata_next[0] = lp1_cmo_commit_117_qs; + end - assign lp1_cmo_commit_8_we = addr_hit[153] & reg_we & !reg_error; - assign lp1_cmo_commit_8_wd = reg_wdata[0]; + addr_hit[647]: begin + reg_rdata_next[0] = lp1_cmo_commit_118_qs; + end - assign lp1_cmo_commit_9_we = addr_hit[154] & reg_we & !reg_error; - assign lp1_cmo_commit_9_wd = reg_wdata[0]; + addr_hit[648]: begin + reg_rdata_next[0] = lp1_cmo_commit_119_qs; + end - assign lp1_cmo_commit_10_we = addr_hit[155] & reg_we & !reg_error; - assign lp1_cmo_commit_10_wd = reg_wdata[0]; + addr_hit[649]: begin + reg_rdata_next[0] = lp1_cmo_commit_120_qs; + end - assign lp1_cmo_commit_11_we = addr_hit[156] & reg_we & !reg_error; - assign lp1_cmo_commit_11_wd = reg_wdata[0]; + addr_hit[650]: begin + reg_rdata_next[0] = lp1_cmo_commit_121_qs; + end - assign lp1_cmo_commit_12_we = addr_hit[157] & reg_we & !reg_error; - assign lp1_cmo_commit_12_wd = reg_wdata[0]; + addr_hit[651]: begin + reg_rdata_next[0] = lp1_cmo_commit_122_qs; + end - assign lp1_cmo_commit_13_we = addr_hit[158] & reg_we & !reg_error; - assign lp1_cmo_commit_13_wd = reg_wdata[0]; + addr_hit[652]: begin + reg_rdata_next[0] = lp1_cmo_commit_123_qs; + end - assign lp1_cmo_commit_14_we = addr_hit[159] & reg_we & !reg_error; - assign lp1_cmo_commit_14_wd = reg_wdata[0]; + addr_hit[653]: begin + reg_rdata_next[0] = lp1_cmo_commit_124_qs; + end - assign lp1_cmo_commit_15_we = addr_hit[160] & reg_we & !reg_error; - assign lp1_cmo_commit_15_wd = reg_wdata[0]; + addr_hit[654]: begin + reg_rdata_next[0] = lp1_cmo_commit_125_qs; + end - assign lp1_cmo_commit_16_we = addr_hit[161] & reg_we & !reg_error; - assign lp1_cmo_commit_16_wd = reg_wdata[0]; + addr_hit[655]: begin + reg_rdata_next[0] = lp1_cmo_commit_126_qs; + end - assign lp1_cmo_commit_17_we = addr_hit[162] & reg_we & !reg_error; - assign lp1_cmo_commit_17_wd = reg_wdata[0]; + addr_hit[656]: begin + reg_rdata_next[0] = lp1_cmo_commit_127_qs; + end - assign lp1_cmo_commit_18_we = addr_hit[163] & reg_we & !reg_error; - assign lp1_cmo_commit_18_wd = reg_wdata[0]; + addr_hit[657]: begin + reg_rdata_next[0] = lp1_cmo_commit_128_qs; + end - assign lp1_cmo_commit_19_we = addr_hit[164] & reg_we & !reg_error; - assign lp1_cmo_commit_19_wd = reg_wdata[0]; + addr_hit[658]: begin + reg_rdata_next[0] = lp1_cmo_commit_129_qs; + end - assign lp1_cmo_commit_20_we = addr_hit[165] & reg_we & !reg_error; - assign lp1_cmo_commit_20_wd = reg_wdata[0]; + addr_hit[659]: begin + reg_rdata_next[0] = lp1_cmo_commit_130_qs; + end - assign lp1_cmo_commit_21_we = addr_hit[166] & reg_we & !reg_error; - assign lp1_cmo_commit_21_wd = reg_wdata[0]; + addr_hit[660]: begin + reg_rdata_next[0] = lp1_cmo_commit_131_qs; + end - assign lp1_cmo_commit_22_we = addr_hit[167] & reg_we & !reg_error; - assign lp1_cmo_commit_22_wd = reg_wdata[0]; + addr_hit[661]: begin + reg_rdata_next[0] = lp1_cmo_commit_132_qs; + end - assign lp1_cmo_commit_23_we = addr_hit[168] & reg_we & !reg_error; - assign lp1_cmo_commit_23_wd = reg_wdata[0]; + addr_hit[662]: begin + reg_rdata_next[0] = lp1_cmo_commit_133_qs; + end - assign lp1_cmo_commit_24_we = addr_hit[169] & reg_we & !reg_error; - assign lp1_cmo_commit_24_wd = reg_wdata[0]; + addr_hit[663]: begin + reg_rdata_next[0] = lp1_cmo_commit_134_qs; + end - assign lp1_cmo_commit_25_we = addr_hit[170] & reg_we & !reg_error; - assign lp1_cmo_commit_25_wd = reg_wdata[0]; + addr_hit[664]: begin + reg_rdata_next[0] = lp1_cmo_commit_135_qs; + end - assign lp1_cmo_commit_26_we = addr_hit[171] & reg_we & !reg_error; - assign lp1_cmo_commit_26_wd = reg_wdata[0]; + addr_hit[665]: begin + reg_rdata_next[0] = lp1_cmo_commit_136_qs; + end - assign lp1_cmo_commit_27_we = addr_hit[172] & reg_we & !reg_error; - assign lp1_cmo_commit_27_wd = reg_wdata[0]; + addr_hit[666]: begin + reg_rdata_next[0] = lp1_cmo_commit_137_qs; + end - assign lp1_cmo_commit_28_we = addr_hit[173] & reg_we & !reg_error; - assign lp1_cmo_commit_28_wd = reg_wdata[0]; + addr_hit[667]: begin + reg_rdata_next[0] = lp1_cmo_commit_138_qs; + end - assign lp1_cmo_commit_29_we = addr_hit[174] & reg_we & !reg_error; - assign lp1_cmo_commit_29_wd = reg_wdata[0]; + addr_hit[668]: begin + reg_rdata_next[0] = lp1_cmo_commit_139_qs; + end - assign lp1_cmo_commit_30_we = addr_hit[175] & reg_we & !reg_error; - assign lp1_cmo_commit_30_wd = reg_wdata[0]; + addr_hit[669]: begin + reg_rdata_next[0] = lp1_cmo_commit_140_qs; + end - assign lp1_cmo_commit_31_we = addr_hit[176] & reg_we & !reg_error; - assign lp1_cmo_commit_31_wd = reg_wdata[0]; + addr_hit[670]: begin + reg_rdata_next[0] = lp1_cmo_commit_141_qs; + end - assign lp1_cmo_commit_32_we = addr_hit[177] & reg_we & !reg_error; - assign lp1_cmo_commit_32_wd = reg_wdata[0]; + addr_hit[671]: begin + reg_rdata_next[0] = lp1_cmo_commit_142_qs; + end - assign lp1_cmo_commit_33_we = addr_hit[178] & reg_we & !reg_error; - assign lp1_cmo_commit_33_wd = reg_wdata[0]; + addr_hit[672]: begin + reg_rdata_next[0] = lp1_cmo_commit_143_qs; + end - assign lp1_cmo_commit_34_we = addr_hit[179] & reg_we & !reg_error; - assign lp1_cmo_commit_34_wd = reg_wdata[0]; + addr_hit[673]: begin + reg_rdata_next[0] = lp1_cmo_commit_144_qs; + end - assign lp1_cmo_commit_35_we = addr_hit[180] & reg_we & !reg_error; - assign lp1_cmo_commit_35_wd = reg_wdata[0]; + addr_hit[674]: begin + reg_rdata_next[0] = lp1_cmo_commit_145_qs; + end - assign lp1_cmo_commit_36_we = addr_hit[181] & reg_we & !reg_error; - assign lp1_cmo_commit_36_wd = reg_wdata[0]; + addr_hit[675]: begin + reg_rdata_next[0] = lp1_cmo_commit_146_qs; + end - assign lp1_cmo_commit_37_we = addr_hit[182] & reg_we & !reg_error; - assign lp1_cmo_commit_37_wd = reg_wdata[0]; + addr_hit[676]: begin + reg_rdata_next[0] = lp1_cmo_commit_147_qs; + end - assign lp1_cmo_commit_38_we = addr_hit[183] & reg_we & !reg_error; - assign lp1_cmo_commit_38_wd = reg_wdata[0]; + addr_hit[677]: begin + reg_rdata_next[0] = lp1_cmo_commit_148_qs; + end - assign lp1_cmo_commit_39_we = addr_hit[184] & reg_we & !reg_error; - assign lp1_cmo_commit_39_wd = reg_wdata[0]; + addr_hit[678]: begin + reg_rdata_next[0] = lp1_cmo_commit_149_qs; + end - assign lp1_cmo_commit_40_we = addr_hit[185] & reg_we & !reg_error; - assign lp1_cmo_commit_40_wd = reg_wdata[0]; + addr_hit[679]: begin + reg_rdata_next[0] = lp1_cmo_commit_150_qs; + end - assign lp1_cmo_commit_41_we = addr_hit[186] & reg_we & !reg_error; - assign lp1_cmo_commit_41_wd = reg_wdata[0]; + addr_hit[680]: begin + reg_rdata_next[0] = lp1_cmo_commit_151_qs; + end - assign lp1_cmo_commit_42_we = addr_hit[187] & reg_we & !reg_error; - assign lp1_cmo_commit_42_wd = reg_wdata[0]; + addr_hit[681]: begin + reg_rdata_next[0] = lp1_cmo_commit_152_qs; + end - assign lp1_cmo_commit_43_we = addr_hit[188] & reg_we & !reg_error; - assign lp1_cmo_commit_43_wd = reg_wdata[0]; + addr_hit[682]: begin + reg_rdata_next[0] = lp1_cmo_commit_153_qs; + end - assign lp1_cmo_commit_44_we = addr_hit[189] & reg_we & !reg_error; - assign lp1_cmo_commit_44_wd = reg_wdata[0]; + addr_hit[683]: begin + reg_rdata_next[0] = lp1_cmo_commit_154_qs; + end - assign lp1_cmo_commit_45_we = addr_hit[190] & reg_we & !reg_error; - assign lp1_cmo_commit_45_wd = reg_wdata[0]; + addr_hit[684]: begin + reg_rdata_next[0] = lp1_cmo_commit_155_qs; + end - assign lp1_cmo_commit_46_we = addr_hit[191] & reg_we & !reg_error; - assign lp1_cmo_commit_46_wd = reg_wdata[0]; + addr_hit[685]: begin + reg_rdata_next[0] = lp1_cmo_commit_156_qs; + end - assign lp1_cmo_commit_47_we = addr_hit[192] & reg_we & !reg_error; - assign lp1_cmo_commit_47_wd = reg_wdata[0]; + addr_hit[686]: begin + reg_rdata_next[0] = lp1_cmo_commit_157_qs; + end - assign lp1_cmo_commit_48_we = addr_hit[193] & reg_we & !reg_error; - assign lp1_cmo_commit_48_wd = reg_wdata[0]; + addr_hit[687]: begin + reg_rdata_next[0] = lp1_cmo_commit_158_qs; + end - assign lp1_cmo_commit_49_we = addr_hit[194] & reg_we & !reg_error; - assign lp1_cmo_commit_49_wd = reg_wdata[0]; + addr_hit[688]: begin + reg_rdata_next[0] = lp1_cmo_commit_159_qs; + end - assign lp1_cmo_commit_50_we = addr_hit[195] & reg_we & !reg_error; - assign lp1_cmo_commit_50_wd = reg_wdata[0]; + addr_hit[689]: begin + reg_rdata_next[0] = lp1_cmo_commit_160_qs; + end - assign lp1_cmo_commit_51_we = addr_hit[196] & reg_we & !reg_error; - assign lp1_cmo_commit_51_wd = reg_wdata[0]; + addr_hit[690]: begin + reg_rdata_next[0] = lp1_cmo_commit_161_qs; + end - assign lp1_cmo_commit_52_we = addr_hit[197] & reg_we & !reg_error; - assign lp1_cmo_commit_52_wd = reg_wdata[0]; + addr_hit[691]: begin + reg_rdata_next[0] = lp1_cmo_commit_162_qs; + end - assign lp1_cmo_commit_53_we = addr_hit[198] & reg_we & !reg_error; - assign lp1_cmo_commit_53_wd = reg_wdata[0]; + addr_hit[692]: begin + reg_rdata_next[0] = lp1_cmo_commit_163_qs; + end - assign lp1_cmo_commit_54_we = addr_hit[199] & reg_we & !reg_error; - assign lp1_cmo_commit_54_wd = reg_wdata[0]; + addr_hit[693]: begin + reg_rdata_next[0] = lp1_cmo_commit_164_qs; + end - assign lp1_cmo_commit_55_we = addr_hit[200] & reg_we & !reg_error; - assign lp1_cmo_commit_55_wd = reg_wdata[0]; + addr_hit[694]: begin + reg_rdata_next[0] = lp1_cmo_commit_165_qs; + end - assign lp1_cmo_commit_56_we = addr_hit[201] & reg_we & !reg_error; - assign lp1_cmo_commit_56_wd = reg_wdata[0]; + addr_hit[695]: begin + reg_rdata_next[0] = lp1_cmo_commit_166_qs; + end - assign lp1_cmo_commit_57_we = addr_hit[202] & reg_we & !reg_error; - assign lp1_cmo_commit_57_wd = reg_wdata[0]; + addr_hit[696]: begin + reg_rdata_next[0] = lp1_cmo_commit_167_qs; + end - assign lp1_cmo_commit_58_we = addr_hit[203] & reg_we & !reg_error; - assign lp1_cmo_commit_58_wd = reg_wdata[0]; + addr_hit[697]: begin + reg_rdata_next[0] = lp1_cmo_commit_168_qs; + end - assign lp1_cmo_commit_59_we = addr_hit[204] & reg_we & !reg_error; - assign lp1_cmo_commit_59_wd = reg_wdata[0]; + addr_hit[698]: begin + reg_rdata_next[0] = lp1_cmo_commit_169_qs; + end - assign lp1_cmo_commit_60_we = addr_hit[205] & reg_we & !reg_error; - assign lp1_cmo_commit_60_wd = reg_wdata[0]; + addr_hit[699]: begin + reg_rdata_next[0] = lp1_cmo_commit_170_qs; + end - assign lp1_cmo_commit_61_we = addr_hit[206] & reg_we & !reg_error; - assign lp1_cmo_commit_61_wd = reg_wdata[0]; + addr_hit[700]: begin + reg_rdata_next[0] = lp1_cmo_commit_171_qs; + end - assign lp1_cmo_commit_62_we = addr_hit[207] & reg_we & !reg_error; - assign lp1_cmo_commit_62_wd = reg_wdata[0]; + addr_hit[701]: begin + reg_rdata_next[0] = lp1_cmo_commit_172_qs; + end - assign lp1_cmo_commit_63_we = addr_hit[208] & reg_we & !reg_error; - assign lp1_cmo_commit_63_wd = reg_wdata[0]; + addr_hit[702]: begin + reg_rdata_next[0] = lp1_cmo_commit_173_qs; + end - assign lp1_cmo_status_0_re = addr_hit[209] & reg_re & !reg_error; + addr_hit[703]: begin + reg_rdata_next[0] = lp1_cmo_commit_174_qs; + end - assign lp1_cmo_status_1_re = addr_hit[210] & reg_re & !reg_error; + addr_hit[704]: begin + reg_rdata_next[0] = lp1_cmo_commit_175_qs; + end - assign lp1_cmo_status_2_re = addr_hit[211] & reg_re & !reg_error; + addr_hit[705]: begin + reg_rdata_next[0] = lp1_cmo_commit_176_qs; + end - assign lp1_cmo_status_3_re = addr_hit[212] & reg_re & !reg_error; + addr_hit[706]: begin + reg_rdata_next[0] = lp1_cmo_commit_177_qs; + end - assign lp1_cmo_status_4_re = addr_hit[213] & reg_re & !reg_error; + addr_hit[707]: begin + reg_rdata_next[0] = lp1_cmo_commit_178_qs; + end - assign lp1_cmo_status_5_re = addr_hit[214] & reg_re & !reg_error; + addr_hit[708]: begin + reg_rdata_next[0] = lp1_cmo_commit_179_qs; + end - assign lp1_cmo_status_6_re = addr_hit[215] & reg_re & !reg_error; + addr_hit[709]: begin + reg_rdata_next[0] = lp1_cmo_commit_180_qs; + end - assign lp1_cmo_status_7_re = addr_hit[216] & reg_re & !reg_error; + addr_hit[710]: begin + reg_rdata_next[0] = lp1_cmo_commit_181_qs; + end - assign lp1_cmo_status_8_re = addr_hit[217] & reg_re & !reg_error; + addr_hit[711]: begin + reg_rdata_next[0] = lp1_cmo_commit_182_qs; + end - assign lp1_cmo_status_9_re = addr_hit[218] & reg_re & !reg_error; + addr_hit[712]: begin + reg_rdata_next[0] = lp1_cmo_commit_183_qs; + end - assign lp1_cmo_status_10_re = addr_hit[219] & reg_re & !reg_error; + addr_hit[713]: begin + reg_rdata_next[0] = lp1_cmo_commit_184_qs; + end - assign lp1_cmo_status_11_re = addr_hit[220] & reg_re & !reg_error; + addr_hit[714]: begin + reg_rdata_next[0] = lp1_cmo_commit_185_qs; + end - assign lp1_cmo_status_12_re = addr_hit[221] & reg_re & !reg_error; + addr_hit[715]: begin + reg_rdata_next[0] = lp1_cmo_commit_186_qs; + end - assign lp1_cmo_status_13_re = addr_hit[222] & reg_re & !reg_error; + addr_hit[716]: begin + reg_rdata_next[0] = lp1_cmo_commit_187_qs; + end - assign lp1_cmo_status_14_re = addr_hit[223] & reg_re & !reg_error; + addr_hit[717]: begin + reg_rdata_next[0] = lp1_cmo_commit_188_qs; + end - assign lp1_cmo_status_15_re = addr_hit[224] & reg_re & !reg_error; + addr_hit[718]: begin + reg_rdata_next[0] = lp1_cmo_commit_189_qs; + end - assign lp1_cmo_status_16_re = addr_hit[225] & reg_re & !reg_error; + addr_hit[719]: begin + reg_rdata_next[0] = lp1_cmo_commit_190_qs; + end - assign lp1_cmo_status_17_re = addr_hit[226] & reg_re & !reg_error; + addr_hit[720]: begin + reg_rdata_next[0] = lp1_cmo_commit_191_qs; + end - assign lp1_cmo_status_18_re = addr_hit[227] & reg_re & !reg_error; + addr_hit[721]: begin + reg_rdata_next[0] = lp1_cmo_commit_192_qs; + end - assign lp1_cmo_status_19_re = addr_hit[228] & reg_re & !reg_error; + addr_hit[722]: begin + reg_rdata_next[0] = lp1_cmo_commit_193_qs; + end - assign lp1_cmo_status_20_re = addr_hit[229] & reg_re & !reg_error; + addr_hit[723]: begin + reg_rdata_next[0] = lp1_cmo_commit_194_qs; + end - assign lp1_cmo_status_21_re = addr_hit[230] & reg_re & !reg_error; + addr_hit[724]: begin + reg_rdata_next[0] = lp1_cmo_commit_195_qs; + end - assign lp1_cmo_status_22_re = addr_hit[231] & reg_re & !reg_error; + addr_hit[725]: begin + reg_rdata_next[0] = lp1_cmo_commit_196_qs; + end - assign lp1_cmo_status_23_re = addr_hit[232] & reg_re & !reg_error; + addr_hit[726]: begin + reg_rdata_next[0] = lp1_cmo_commit_197_qs; + end - assign lp1_cmo_status_24_re = addr_hit[233] & reg_re & !reg_error; + addr_hit[727]: begin + reg_rdata_next[0] = lp1_cmo_commit_198_qs; + end - assign lp1_cmo_status_25_re = addr_hit[234] & reg_re & !reg_error; + addr_hit[728]: begin + reg_rdata_next[0] = lp1_cmo_commit_199_qs; + end - assign lp1_cmo_status_26_re = addr_hit[235] & reg_re & !reg_error; + addr_hit[729]: begin + reg_rdata_next[0] = lp1_cmo_commit_200_qs; + end - assign lp1_cmo_status_27_re = addr_hit[236] & reg_re & !reg_error; + addr_hit[730]: begin + reg_rdata_next[0] = lp1_cmo_commit_201_qs; + end - assign lp1_cmo_status_28_re = addr_hit[237] & reg_re & !reg_error; + addr_hit[731]: begin + reg_rdata_next[0] = lp1_cmo_commit_202_qs; + end - assign lp1_cmo_status_29_re = addr_hit[238] & reg_re & !reg_error; + addr_hit[732]: begin + reg_rdata_next[0] = lp1_cmo_commit_203_qs; + end - assign lp1_cmo_status_30_re = addr_hit[239] & reg_re & !reg_error; + addr_hit[733]: begin + reg_rdata_next[0] = lp1_cmo_commit_204_qs; + end - assign lp1_cmo_status_31_re = addr_hit[240] & reg_re & !reg_error; + addr_hit[734]: begin + reg_rdata_next[0] = lp1_cmo_commit_205_qs; + end - assign lp1_cmo_status_32_re = addr_hit[241] & reg_re & !reg_error; + addr_hit[735]: begin + reg_rdata_next[0] = lp1_cmo_commit_206_qs; + end - assign lp1_cmo_status_33_re = addr_hit[242] & reg_re & !reg_error; + addr_hit[736]: begin + reg_rdata_next[0] = lp1_cmo_commit_207_qs; + end - assign lp1_cmo_status_34_re = addr_hit[243] & reg_re & !reg_error; + addr_hit[737]: begin + reg_rdata_next[0] = lp1_cmo_commit_208_qs; + end - assign lp1_cmo_status_35_re = addr_hit[244] & reg_re & !reg_error; + addr_hit[738]: begin + reg_rdata_next[0] = lp1_cmo_commit_209_qs; + end - assign lp1_cmo_status_36_re = addr_hit[245] & reg_re & !reg_error; + addr_hit[739]: begin + reg_rdata_next[0] = lp1_cmo_commit_210_qs; + end - assign lp1_cmo_status_37_re = addr_hit[246] & reg_re & !reg_error; + addr_hit[740]: begin + reg_rdata_next[0] = lp1_cmo_commit_211_qs; + end - assign lp1_cmo_status_38_re = addr_hit[247] & reg_re & !reg_error; + addr_hit[741]: begin + reg_rdata_next[0] = lp1_cmo_commit_212_qs; + end - assign lp1_cmo_status_39_re = addr_hit[248] & reg_re & !reg_error; + addr_hit[742]: begin + reg_rdata_next[0] = lp1_cmo_commit_213_qs; + end - assign lp1_cmo_status_40_re = addr_hit[249] & reg_re & !reg_error; + addr_hit[743]: begin + reg_rdata_next[0] = lp1_cmo_commit_214_qs; + end - assign lp1_cmo_status_41_re = addr_hit[250] & reg_re & !reg_error; + addr_hit[744]: begin + reg_rdata_next[0] = lp1_cmo_commit_215_qs; + end - assign lp1_cmo_status_42_re = addr_hit[251] & reg_re & !reg_error; + addr_hit[745]: begin + reg_rdata_next[0] = lp1_cmo_commit_216_qs; + end - assign lp1_cmo_status_43_re = addr_hit[252] & reg_re & !reg_error; + addr_hit[746]: begin + reg_rdata_next[0] = lp1_cmo_commit_217_qs; + end - assign lp1_cmo_status_44_re = addr_hit[253] & reg_re & !reg_error; + addr_hit[747]: begin + reg_rdata_next[0] = lp1_cmo_commit_218_qs; + end - assign lp1_cmo_status_45_re = addr_hit[254] & reg_re & !reg_error; + addr_hit[748]: begin + reg_rdata_next[0] = lp1_cmo_commit_219_qs; + end - assign lp1_cmo_status_46_re = addr_hit[255] & reg_re & !reg_error; + addr_hit[749]: begin + reg_rdata_next[0] = lp1_cmo_commit_220_qs; + end - assign lp1_cmo_status_47_re = addr_hit[256] & reg_re & !reg_error; + addr_hit[750]: begin + reg_rdata_next[0] = lp1_cmo_commit_221_qs; + end - assign lp1_cmo_status_48_re = addr_hit[257] & reg_re & !reg_error; + addr_hit[751]: begin + reg_rdata_next[0] = lp1_cmo_commit_222_qs; + end - assign lp1_cmo_status_49_re = addr_hit[258] & reg_re & !reg_error; + addr_hit[752]: begin + reg_rdata_next[0] = lp1_cmo_commit_223_qs; + end - assign lp1_cmo_status_50_re = addr_hit[259] & reg_re & !reg_error; + addr_hit[753]: begin + reg_rdata_next[0] = lp1_cmo_commit_224_qs; + end - assign lp1_cmo_status_51_re = addr_hit[260] & reg_re & !reg_error; + addr_hit[754]: begin + reg_rdata_next[0] = lp1_cmo_commit_225_qs; + end - assign lp1_cmo_status_52_re = addr_hit[261] & reg_re & !reg_error; + addr_hit[755]: begin + reg_rdata_next[0] = lp1_cmo_commit_226_qs; + end - assign lp1_cmo_status_53_re = addr_hit[262] & reg_re & !reg_error; + addr_hit[756]: begin + reg_rdata_next[0] = lp1_cmo_commit_227_qs; + end - assign lp1_cmo_status_54_re = addr_hit[263] & reg_re & !reg_error; + addr_hit[757]: begin + reg_rdata_next[0] = lp1_cmo_commit_228_qs; + end - assign lp1_cmo_status_55_re = addr_hit[264] & reg_re & !reg_error; + addr_hit[758]: begin + reg_rdata_next[0] = lp1_cmo_commit_229_qs; + end - assign lp1_cmo_status_56_re = addr_hit[265] & reg_re & !reg_error; + addr_hit[759]: begin + reg_rdata_next[0] = lp1_cmo_commit_230_qs; + end - assign lp1_cmo_status_57_re = addr_hit[266] & reg_re & !reg_error; + addr_hit[760]: begin + reg_rdata_next[0] = lp1_cmo_commit_231_qs; + end - assign lp1_cmo_status_58_re = addr_hit[267] & reg_re & !reg_error; + addr_hit[761]: begin + reg_rdata_next[0] = lp1_cmo_commit_232_qs; + end - assign lp1_cmo_status_59_re = addr_hit[268] & reg_re & !reg_error; + addr_hit[762]: begin + reg_rdata_next[0] = lp1_cmo_commit_233_qs; + end - assign lp1_cmo_status_60_re = addr_hit[269] & reg_re & !reg_error; + addr_hit[763]: begin + reg_rdata_next[0] = lp1_cmo_commit_234_qs; + end - assign lp1_cmo_status_61_re = addr_hit[270] & reg_re & !reg_error; + addr_hit[764]: begin + reg_rdata_next[0] = lp1_cmo_commit_235_qs; + end - assign lp1_cmo_status_62_re = addr_hit[271] & reg_re & !reg_error; + addr_hit[765]: begin + reg_rdata_next[0] = lp1_cmo_commit_236_qs; + end - assign lp1_cmo_status_63_re = addr_hit[272] & reg_re & !reg_error; + addr_hit[766]: begin + reg_rdata_next[0] = lp1_cmo_commit_237_qs; + end - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[31:0] = hw_barrier_qs; + addr_hit[767]: begin + reg_rdata_next[0] = lp1_cmo_commit_238_qs; end - addr_hit[1]: begin - reg_rdata_next[0] = '0; + addr_hit[768]: begin + reg_rdata_next[0] = lp1_cmo_commit_239_qs; end - addr_hit[2]: begin - reg_rdata_next[0] = '0; + addr_hit[769]: begin + reg_rdata_next[0] = lp1_cmo_commit_240_qs; end - addr_hit[3]: begin - reg_rdata_next[31:0] = spatz_cycle_qs; + addr_hit[770]: begin + reg_rdata_next[0] = lp1_cmo_commit_241_qs; end - addr_hit[4]: begin - reg_rdata_next[31:0] = cluster_boot_control_qs; + addr_hit[771]: begin + reg_rdata_next[0] = lp1_cmo_commit_242_qs; end - addr_hit[5]: begin - reg_rdata_next[3:0] = cluster_eoc_exit_qs; + addr_hit[772]: begin + reg_rdata_next[0] = lp1_cmo_commit_243_qs; end - addr_hit[6]: begin - reg_rdata_next[9:0] = cfg_l1d_spm_qs; + addr_hit[773]: begin + reg_rdata_next[0] = lp1_cmo_commit_244_qs; end - addr_hit[7]: begin - reg_rdata_next[1:0] = cfg_l1d_insn_qs; + addr_hit[774]: begin + reg_rdata_next[0] = lp1_cmo_commit_245_qs; end - addr_hit[8]: begin - reg_rdata_next[31:0] = cfg_l1d_tile_sel_0_qs; + addr_hit[775]: begin + reg_rdata_next[0] = lp1_cmo_commit_246_qs; end - addr_hit[9]: begin - reg_rdata_next[31:0] = cfg_l1d_tile_sel_1_qs; + addr_hit[776]: begin + reg_rdata_next[0] = lp1_cmo_commit_247_qs; end - addr_hit[10]: begin - reg_rdata_next[0] = l1d_spm_commit_qs; + addr_hit[777]: begin + reg_rdata_next[0] = lp1_cmo_commit_248_qs; end - addr_hit[11]: begin - reg_rdata_next[0] = l1d_insn_commit_qs; + addr_hit[778]: begin + reg_rdata_next[0] = lp1_cmo_commit_249_qs; end - addr_hit[12]: begin - reg_rdata_next[0] = l1d_flush_status_qs; + addr_hit[779]: begin + reg_rdata_next[0] = lp1_cmo_commit_250_qs; end - addr_hit[13]: begin - reg_rdata_next[3:0] = l1d_private_qs; + addr_hit[780]: begin + reg_rdata_next[0] = lp1_cmo_commit_251_qs; end - addr_hit[14]: begin - reg_rdata_next[31:0] = l1d_addr_qs; + addr_hit[781]: begin + reg_rdata_next[0] = lp1_cmo_commit_252_qs; end - addr_hit[15]: begin - reg_rdata_next[4:0] = xbar_offset_qs; + addr_hit[782]: begin + reg_rdata_next[0] = lp1_cmo_commit_253_qs; end - addr_hit[16]: begin - reg_rdata_next[0] = xbar_offset_commit_qs; + addr_hit[783]: begin + reg_rdata_next[0] = lp1_cmo_commit_254_qs; end - addr_hit[17]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_0_qs; + addr_hit[784]: begin + reg_rdata_next[0] = lp1_cmo_commit_255_qs; end - addr_hit[18]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_1_qs; + addr_hit[785]: begin + reg_rdata_next[0] = lp1_cmo_status_0_qs; end - addr_hit[19]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_2_qs; + addr_hit[786]: begin + reg_rdata_next[0] = lp1_cmo_status_1_qs; end - addr_hit[20]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_3_qs; + addr_hit[787]: begin + reg_rdata_next[0] = lp1_cmo_status_2_qs; end - addr_hit[21]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_4_qs; + addr_hit[788]: begin + reg_rdata_next[0] = lp1_cmo_status_3_qs; end - addr_hit[22]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_5_qs; + addr_hit[789]: begin + reg_rdata_next[0] = lp1_cmo_status_4_qs; end - addr_hit[23]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_6_qs; + addr_hit[790]: begin + reg_rdata_next[0] = lp1_cmo_status_5_qs; end - addr_hit[24]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_7_qs; + addr_hit[791]: begin + reg_rdata_next[0] = lp1_cmo_status_6_qs; end - addr_hit[25]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_8_qs; + addr_hit[792]: begin + reg_rdata_next[0] = lp1_cmo_status_7_qs; end - addr_hit[26]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_9_qs; + addr_hit[793]: begin + reg_rdata_next[0] = lp1_cmo_status_8_qs; end - addr_hit[27]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_10_qs; + addr_hit[794]: begin + reg_rdata_next[0] = lp1_cmo_status_9_qs; end - addr_hit[28]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_11_qs; + addr_hit[795]: begin + reg_rdata_next[0] = lp1_cmo_status_10_qs; end - addr_hit[29]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_12_qs; + addr_hit[796]: begin + reg_rdata_next[0] = lp1_cmo_status_11_qs; end - addr_hit[30]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_13_qs; + addr_hit[797]: begin + reg_rdata_next[0] = lp1_cmo_status_12_qs; end - addr_hit[31]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_14_qs; + addr_hit[798]: begin + reg_rdata_next[0] = lp1_cmo_status_13_qs; end - addr_hit[32]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_15_qs; + addr_hit[799]: begin + reg_rdata_next[0] = lp1_cmo_status_14_qs; end - addr_hit[33]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_16_qs; + addr_hit[800]: begin + reg_rdata_next[0] = lp1_cmo_status_15_qs; end - addr_hit[34]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_17_qs; + addr_hit[801]: begin + reg_rdata_next[0] = lp1_cmo_status_16_qs; end - addr_hit[35]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_18_qs; + addr_hit[802]: begin + reg_rdata_next[0] = lp1_cmo_status_17_qs; end - addr_hit[36]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_19_qs; + addr_hit[803]: begin + reg_rdata_next[0] = lp1_cmo_status_18_qs; end - addr_hit[37]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_20_qs; + addr_hit[804]: begin + reg_rdata_next[0] = lp1_cmo_status_19_qs; end - addr_hit[38]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_21_qs; + addr_hit[805]: begin + reg_rdata_next[0] = lp1_cmo_status_20_qs; + end + + addr_hit[806]: begin + reg_rdata_next[0] = lp1_cmo_status_21_qs; end - addr_hit[39]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_22_qs; + addr_hit[807]: begin + reg_rdata_next[0] = lp1_cmo_status_22_qs; end - addr_hit[40]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_23_qs; + addr_hit[808]: begin + reg_rdata_next[0] = lp1_cmo_status_23_qs; end - addr_hit[41]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_24_qs; + addr_hit[809]: begin + reg_rdata_next[0] = lp1_cmo_status_24_qs; end - addr_hit[42]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_25_qs; + addr_hit[810]: begin + reg_rdata_next[0] = lp1_cmo_status_25_qs; end - addr_hit[43]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_26_qs; + addr_hit[811]: begin + reg_rdata_next[0] = lp1_cmo_status_26_qs; end - addr_hit[44]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_27_qs; + addr_hit[812]: begin + reg_rdata_next[0] = lp1_cmo_status_27_qs; end - addr_hit[45]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_28_qs; + addr_hit[813]: begin + reg_rdata_next[0] = lp1_cmo_status_28_qs; end - addr_hit[46]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_29_qs; + addr_hit[814]: begin + reg_rdata_next[0] = lp1_cmo_status_29_qs; end - addr_hit[47]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_30_qs; + addr_hit[815]: begin + reg_rdata_next[0] = lp1_cmo_status_30_qs; end - addr_hit[48]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_31_qs; + addr_hit[816]: begin + reg_rdata_next[0] = lp1_cmo_status_31_qs; end - addr_hit[49]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_32_qs; + addr_hit[817]: begin + reg_rdata_next[0] = lp1_cmo_status_32_qs; end - addr_hit[50]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_33_qs; + addr_hit[818]: begin + reg_rdata_next[0] = lp1_cmo_status_33_qs; end - addr_hit[51]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_34_qs; + addr_hit[819]: begin + reg_rdata_next[0] = lp1_cmo_status_34_qs; end - addr_hit[52]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_35_qs; + addr_hit[820]: begin + reg_rdata_next[0] = lp1_cmo_status_35_qs; end - addr_hit[53]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_36_qs; + addr_hit[821]: begin + reg_rdata_next[0] = lp1_cmo_status_36_qs; end - addr_hit[54]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_37_qs; + addr_hit[822]: begin + reg_rdata_next[0] = lp1_cmo_status_37_qs; end - addr_hit[55]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_38_qs; + addr_hit[823]: begin + reg_rdata_next[0] = lp1_cmo_status_38_qs; end - addr_hit[56]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_39_qs; + addr_hit[824]: begin + reg_rdata_next[0] = lp1_cmo_status_39_qs; end - addr_hit[57]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_40_qs; + addr_hit[825]: begin + reg_rdata_next[0] = lp1_cmo_status_40_qs; end - addr_hit[58]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_41_qs; + addr_hit[826]: begin + reg_rdata_next[0] = lp1_cmo_status_41_qs; end - addr_hit[59]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_42_qs; + addr_hit[827]: begin + reg_rdata_next[0] = lp1_cmo_status_42_qs; end - addr_hit[60]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_43_qs; + addr_hit[828]: begin + reg_rdata_next[0] = lp1_cmo_status_43_qs; end - addr_hit[61]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_44_qs; + addr_hit[829]: begin + reg_rdata_next[0] = lp1_cmo_status_44_qs; end - addr_hit[62]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_45_qs; + addr_hit[830]: begin + reg_rdata_next[0] = lp1_cmo_status_45_qs; end - addr_hit[63]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_46_qs; + addr_hit[831]: begin + reg_rdata_next[0] = lp1_cmo_status_46_qs; end - addr_hit[64]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_47_qs; + addr_hit[832]: begin + reg_rdata_next[0] = lp1_cmo_status_47_qs; end - addr_hit[65]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_48_qs; + addr_hit[833]: begin + reg_rdata_next[0] = lp1_cmo_status_48_qs; end - addr_hit[66]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_49_qs; + addr_hit[834]: begin + reg_rdata_next[0] = lp1_cmo_status_49_qs; end - addr_hit[67]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_50_qs; + addr_hit[835]: begin + reg_rdata_next[0] = lp1_cmo_status_50_qs; end - addr_hit[68]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_51_qs; + addr_hit[836]: begin + reg_rdata_next[0] = lp1_cmo_status_51_qs; end - addr_hit[69]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_52_qs; + addr_hit[837]: begin + reg_rdata_next[0] = lp1_cmo_status_52_qs; end - addr_hit[70]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_53_qs; + addr_hit[838]: begin + reg_rdata_next[0] = lp1_cmo_status_53_qs; end - addr_hit[71]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_54_qs; + addr_hit[839]: begin + reg_rdata_next[0] = lp1_cmo_status_54_qs; end - addr_hit[72]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_55_qs; + addr_hit[840]: begin + reg_rdata_next[0] = lp1_cmo_status_55_qs; end - addr_hit[73]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_56_qs; + addr_hit[841]: begin + reg_rdata_next[0] = lp1_cmo_status_56_qs; end - addr_hit[74]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_57_qs; + addr_hit[842]: begin + reg_rdata_next[0] = lp1_cmo_status_57_qs; end - addr_hit[75]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_58_qs; + addr_hit[843]: begin + reg_rdata_next[0] = lp1_cmo_status_58_qs; end - addr_hit[76]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_59_qs; + addr_hit[844]: begin + reg_rdata_next[0] = lp1_cmo_status_59_qs; end - addr_hit[77]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_60_qs; + addr_hit[845]: begin + reg_rdata_next[0] = lp1_cmo_status_60_qs; end - addr_hit[78]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_61_qs; + addr_hit[846]: begin + reg_rdata_next[0] = lp1_cmo_status_61_qs; end - addr_hit[79]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_62_qs; + addr_hit[847]: begin + reg_rdata_next[0] = lp1_cmo_status_62_qs; end - addr_hit[80]: begin - reg_rdata_next[2:0] = cfg_lp1_cmo_63_qs; + addr_hit[848]: begin + reg_rdata_next[0] = lp1_cmo_status_63_qs; end - addr_hit[81]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_0_qs; + addr_hit[849]: begin + reg_rdata_next[0] = lp1_cmo_status_64_qs; end - addr_hit[82]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_1_qs; + addr_hit[850]: begin + reg_rdata_next[0] = lp1_cmo_status_65_qs; end - addr_hit[83]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_2_qs; + addr_hit[851]: begin + reg_rdata_next[0] = lp1_cmo_status_66_qs; end - addr_hit[84]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_3_qs; + addr_hit[852]: begin + reg_rdata_next[0] = lp1_cmo_status_67_qs; end - addr_hit[85]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_4_qs; + addr_hit[853]: begin + reg_rdata_next[0] = lp1_cmo_status_68_qs; end - addr_hit[86]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_5_qs; + addr_hit[854]: begin + reg_rdata_next[0] = lp1_cmo_status_69_qs; end - addr_hit[87]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_6_qs; + addr_hit[855]: begin + reg_rdata_next[0] = lp1_cmo_status_70_qs; end - addr_hit[88]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_7_qs; + addr_hit[856]: begin + reg_rdata_next[0] = lp1_cmo_status_71_qs; end - addr_hit[89]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_8_qs; + addr_hit[857]: begin + reg_rdata_next[0] = lp1_cmo_status_72_qs; end - addr_hit[90]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_9_qs; + addr_hit[858]: begin + reg_rdata_next[0] = lp1_cmo_status_73_qs; end - addr_hit[91]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_10_qs; + addr_hit[859]: begin + reg_rdata_next[0] = lp1_cmo_status_74_qs; end - addr_hit[92]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_11_qs; + addr_hit[860]: begin + reg_rdata_next[0] = lp1_cmo_status_75_qs; end - addr_hit[93]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_12_qs; + addr_hit[861]: begin + reg_rdata_next[0] = lp1_cmo_status_76_qs; end - addr_hit[94]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_13_qs; + addr_hit[862]: begin + reg_rdata_next[0] = lp1_cmo_status_77_qs; end - addr_hit[95]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_14_qs; + addr_hit[863]: begin + reg_rdata_next[0] = lp1_cmo_status_78_qs; end - addr_hit[96]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_15_qs; + addr_hit[864]: begin + reg_rdata_next[0] = lp1_cmo_status_79_qs; end - addr_hit[97]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_16_qs; + addr_hit[865]: begin + reg_rdata_next[0] = lp1_cmo_status_80_qs; end - addr_hit[98]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_17_qs; + addr_hit[866]: begin + reg_rdata_next[0] = lp1_cmo_status_81_qs; end - addr_hit[99]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_18_qs; + addr_hit[867]: begin + reg_rdata_next[0] = lp1_cmo_status_82_qs; end - addr_hit[100]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_19_qs; + addr_hit[868]: begin + reg_rdata_next[0] = lp1_cmo_status_83_qs; end - addr_hit[101]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_20_qs; + addr_hit[869]: begin + reg_rdata_next[0] = lp1_cmo_status_84_qs; end - addr_hit[102]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_21_qs; + addr_hit[870]: begin + reg_rdata_next[0] = lp1_cmo_status_85_qs; end - addr_hit[103]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_22_qs; + addr_hit[871]: begin + reg_rdata_next[0] = lp1_cmo_status_86_qs; end - addr_hit[104]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_23_qs; + addr_hit[872]: begin + reg_rdata_next[0] = lp1_cmo_status_87_qs; end - addr_hit[105]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_24_qs; + addr_hit[873]: begin + reg_rdata_next[0] = lp1_cmo_status_88_qs; end - addr_hit[106]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_25_qs; + addr_hit[874]: begin + reg_rdata_next[0] = lp1_cmo_status_89_qs; end - addr_hit[107]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_26_qs; + addr_hit[875]: begin + reg_rdata_next[0] = lp1_cmo_status_90_qs; end - addr_hit[108]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_27_qs; + addr_hit[876]: begin + reg_rdata_next[0] = lp1_cmo_status_91_qs; end - addr_hit[109]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_28_qs; + addr_hit[877]: begin + reg_rdata_next[0] = lp1_cmo_status_92_qs; end - addr_hit[110]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_29_qs; + addr_hit[878]: begin + reg_rdata_next[0] = lp1_cmo_status_93_qs; end - addr_hit[111]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_30_qs; + addr_hit[879]: begin + reg_rdata_next[0] = lp1_cmo_status_94_qs; end - addr_hit[112]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_31_qs; + addr_hit[880]: begin + reg_rdata_next[0] = lp1_cmo_status_95_qs; end - addr_hit[113]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_32_qs; + addr_hit[881]: begin + reg_rdata_next[0] = lp1_cmo_status_96_qs; end - addr_hit[114]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_33_qs; + addr_hit[882]: begin + reg_rdata_next[0] = lp1_cmo_status_97_qs; end - addr_hit[115]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_34_qs; + addr_hit[883]: begin + reg_rdata_next[0] = lp1_cmo_status_98_qs; end - addr_hit[116]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_35_qs; + addr_hit[884]: begin + reg_rdata_next[0] = lp1_cmo_status_99_qs; end - addr_hit[117]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_36_qs; + addr_hit[885]: begin + reg_rdata_next[0] = lp1_cmo_status_100_qs; end - addr_hit[118]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_37_qs; + addr_hit[886]: begin + reg_rdata_next[0] = lp1_cmo_status_101_qs; end - addr_hit[119]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_38_qs; + addr_hit[887]: begin + reg_rdata_next[0] = lp1_cmo_status_102_qs; end - addr_hit[120]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_39_qs; + addr_hit[888]: begin + reg_rdata_next[0] = lp1_cmo_status_103_qs; end - addr_hit[121]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_40_qs; + addr_hit[889]: begin + reg_rdata_next[0] = lp1_cmo_status_104_qs; end - addr_hit[122]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_41_qs; + addr_hit[890]: begin + reg_rdata_next[0] = lp1_cmo_status_105_qs; end - addr_hit[123]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_42_qs; + addr_hit[891]: begin + reg_rdata_next[0] = lp1_cmo_status_106_qs; end - addr_hit[124]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_43_qs; + addr_hit[892]: begin + reg_rdata_next[0] = lp1_cmo_status_107_qs; end - addr_hit[125]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_44_qs; + addr_hit[893]: begin + reg_rdata_next[0] = lp1_cmo_status_108_qs; end - addr_hit[126]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_45_qs; + addr_hit[894]: begin + reg_rdata_next[0] = lp1_cmo_status_109_qs; end - addr_hit[127]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_46_qs; + addr_hit[895]: begin + reg_rdata_next[0] = lp1_cmo_status_110_qs; end - addr_hit[128]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_47_qs; + addr_hit[896]: begin + reg_rdata_next[0] = lp1_cmo_status_111_qs; end - addr_hit[129]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_48_qs; + addr_hit[897]: begin + reg_rdata_next[0] = lp1_cmo_status_112_qs; end - addr_hit[130]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_49_qs; + addr_hit[898]: begin + reg_rdata_next[0] = lp1_cmo_status_113_qs; end - addr_hit[131]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_50_qs; + addr_hit[899]: begin + reg_rdata_next[0] = lp1_cmo_status_114_qs; end - addr_hit[132]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_51_qs; + addr_hit[900]: begin + reg_rdata_next[0] = lp1_cmo_status_115_qs; end - addr_hit[133]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_52_qs; + addr_hit[901]: begin + reg_rdata_next[0] = lp1_cmo_status_116_qs; end - addr_hit[134]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_53_qs; + addr_hit[902]: begin + reg_rdata_next[0] = lp1_cmo_status_117_qs; end - addr_hit[135]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_54_qs; + addr_hit[903]: begin + reg_rdata_next[0] = lp1_cmo_status_118_qs; end - addr_hit[136]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_55_qs; + addr_hit[904]: begin + reg_rdata_next[0] = lp1_cmo_status_119_qs; end - addr_hit[137]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_56_qs; + addr_hit[905]: begin + reg_rdata_next[0] = lp1_cmo_status_120_qs; end - addr_hit[138]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_57_qs; + addr_hit[906]: begin + reg_rdata_next[0] = lp1_cmo_status_121_qs; end - addr_hit[139]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_58_qs; + addr_hit[907]: begin + reg_rdata_next[0] = lp1_cmo_status_122_qs; end - addr_hit[140]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_59_qs; + addr_hit[908]: begin + reg_rdata_next[0] = lp1_cmo_status_123_qs; end - addr_hit[141]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_60_qs; + addr_hit[909]: begin + reg_rdata_next[0] = lp1_cmo_status_124_qs; end - addr_hit[142]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_61_qs; + addr_hit[910]: begin + reg_rdata_next[0] = lp1_cmo_status_125_qs; end - addr_hit[143]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_62_qs; + addr_hit[911]: begin + reg_rdata_next[0] = lp1_cmo_status_126_qs; end - addr_hit[144]: begin - reg_rdata_next[31:0] = cfg_lp1_cmo_addr_63_qs; + addr_hit[912]: begin + reg_rdata_next[0] = lp1_cmo_status_127_qs; end - addr_hit[145]: begin - reg_rdata_next[0] = lp1_cmo_commit_0_qs; + addr_hit[913]: begin + reg_rdata_next[0] = lp1_cmo_status_128_qs; end - addr_hit[146]: begin - reg_rdata_next[0] = lp1_cmo_commit_1_qs; + addr_hit[914]: begin + reg_rdata_next[0] = lp1_cmo_status_129_qs; end - addr_hit[147]: begin - reg_rdata_next[0] = lp1_cmo_commit_2_qs; + addr_hit[915]: begin + reg_rdata_next[0] = lp1_cmo_status_130_qs; end - addr_hit[148]: begin - reg_rdata_next[0] = lp1_cmo_commit_3_qs; + addr_hit[916]: begin + reg_rdata_next[0] = lp1_cmo_status_131_qs; end - addr_hit[149]: begin - reg_rdata_next[0] = lp1_cmo_commit_4_qs; + addr_hit[917]: begin + reg_rdata_next[0] = lp1_cmo_status_132_qs; end - addr_hit[150]: begin - reg_rdata_next[0] = lp1_cmo_commit_5_qs; + addr_hit[918]: begin + reg_rdata_next[0] = lp1_cmo_status_133_qs; end - addr_hit[151]: begin - reg_rdata_next[0] = lp1_cmo_commit_6_qs; + addr_hit[919]: begin + reg_rdata_next[0] = lp1_cmo_status_134_qs; end - addr_hit[152]: begin - reg_rdata_next[0] = lp1_cmo_commit_7_qs; + addr_hit[920]: begin + reg_rdata_next[0] = lp1_cmo_status_135_qs; end - addr_hit[153]: begin - reg_rdata_next[0] = lp1_cmo_commit_8_qs; + addr_hit[921]: begin + reg_rdata_next[0] = lp1_cmo_status_136_qs; end - addr_hit[154]: begin - reg_rdata_next[0] = lp1_cmo_commit_9_qs; + addr_hit[922]: begin + reg_rdata_next[0] = lp1_cmo_status_137_qs; end - addr_hit[155]: begin - reg_rdata_next[0] = lp1_cmo_commit_10_qs; + addr_hit[923]: begin + reg_rdata_next[0] = lp1_cmo_status_138_qs; end - addr_hit[156]: begin - reg_rdata_next[0] = lp1_cmo_commit_11_qs; + addr_hit[924]: begin + reg_rdata_next[0] = lp1_cmo_status_139_qs; end - addr_hit[157]: begin - reg_rdata_next[0] = lp1_cmo_commit_12_qs; + addr_hit[925]: begin + reg_rdata_next[0] = lp1_cmo_status_140_qs; end - addr_hit[158]: begin - reg_rdata_next[0] = lp1_cmo_commit_13_qs; + addr_hit[926]: begin + reg_rdata_next[0] = lp1_cmo_status_141_qs; end - addr_hit[159]: begin - reg_rdata_next[0] = lp1_cmo_commit_14_qs; + addr_hit[927]: begin + reg_rdata_next[0] = lp1_cmo_status_142_qs; end - addr_hit[160]: begin - reg_rdata_next[0] = lp1_cmo_commit_15_qs; + addr_hit[928]: begin + reg_rdata_next[0] = lp1_cmo_status_143_qs; end - addr_hit[161]: begin - reg_rdata_next[0] = lp1_cmo_commit_16_qs; + addr_hit[929]: begin + reg_rdata_next[0] = lp1_cmo_status_144_qs; end - addr_hit[162]: begin - reg_rdata_next[0] = lp1_cmo_commit_17_qs; + addr_hit[930]: begin + reg_rdata_next[0] = lp1_cmo_status_145_qs; end - addr_hit[163]: begin - reg_rdata_next[0] = lp1_cmo_commit_18_qs; + addr_hit[931]: begin + reg_rdata_next[0] = lp1_cmo_status_146_qs; end - addr_hit[164]: begin - reg_rdata_next[0] = lp1_cmo_commit_19_qs; + addr_hit[932]: begin + reg_rdata_next[0] = lp1_cmo_status_147_qs; end - addr_hit[165]: begin - reg_rdata_next[0] = lp1_cmo_commit_20_qs; + addr_hit[933]: begin + reg_rdata_next[0] = lp1_cmo_status_148_qs; end - addr_hit[166]: begin - reg_rdata_next[0] = lp1_cmo_commit_21_qs; + addr_hit[934]: begin + reg_rdata_next[0] = lp1_cmo_status_149_qs; end - addr_hit[167]: begin - reg_rdata_next[0] = lp1_cmo_commit_22_qs; + addr_hit[935]: begin + reg_rdata_next[0] = lp1_cmo_status_150_qs; end - addr_hit[168]: begin - reg_rdata_next[0] = lp1_cmo_commit_23_qs; + addr_hit[936]: begin + reg_rdata_next[0] = lp1_cmo_status_151_qs; end - addr_hit[169]: begin - reg_rdata_next[0] = lp1_cmo_commit_24_qs; + addr_hit[937]: begin + reg_rdata_next[0] = lp1_cmo_status_152_qs; end - addr_hit[170]: begin - reg_rdata_next[0] = lp1_cmo_commit_25_qs; + addr_hit[938]: begin + reg_rdata_next[0] = lp1_cmo_status_153_qs; end - addr_hit[171]: begin - reg_rdata_next[0] = lp1_cmo_commit_26_qs; + addr_hit[939]: begin + reg_rdata_next[0] = lp1_cmo_status_154_qs; end - addr_hit[172]: begin - reg_rdata_next[0] = lp1_cmo_commit_27_qs; + addr_hit[940]: begin + reg_rdata_next[0] = lp1_cmo_status_155_qs; end - addr_hit[173]: begin - reg_rdata_next[0] = lp1_cmo_commit_28_qs; + addr_hit[941]: begin + reg_rdata_next[0] = lp1_cmo_status_156_qs; end - addr_hit[174]: begin - reg_rdata_next[0] = lp1_cmo_commit_29_qs; + addr_hit[942]: begin + reg_rdata_next[0] = lp1_cmo_status_157_qs; end - addr_hit[175]: begin - reg_rdata_next[0] = lp1_cmo_commit_30_qs; + addr_hit[943]: begin + reg_rdata_next[0] = lp1_cmo_status_158_qs; end - addr_hit[176]: begin - reg_rdata_next[0] = lp1_cmo_commit_31_qs; + addr_hit[944]: begin + reg_rdata_next[0] = lp1_cmo_status_159_qs; end - addr_hit[177]: begin - reg_rdata_next[0] = lp1_cmo_commit_32_qs; + addr_hit[945]: begin + reg_rdata_next[0] = lp1_cmo_status_160_qs; end - addr_hit[178]: begin - reg_rdata_next[0] = lp1_cmo_commit_33_qs; + addr_hit[946]: begin + reg_rdata_next[0] = lp1_cmo_status_161_qs; end - addr_hit[179]: begin - reg_rdata_next[0] = lp1_cmo_commit_34_qs; + addr_hit[947]: begin + reg_rdata_next[0] = lp1_cmo_status_162_qs; end - addr_hit[180]: begin - reg_rdata_next[0] = lp1_cmo_commit_35_qs; + addr_hit[948]: begin + reg_rdata_next[0] = lp1_cmo_status_163_qs; end - addr_hit[181]: begin - reg_rdata_next[0] = lp1_cmo_commit_36_qs; + addr_hit[949]: begin + reg_rdata_next[0] = lp1_cmo_status_164_qs; end - addr_hit[182]: begin - reg_rdata_next[0] = lp1_cmo_commit_37_qs; + addr_hit[950]: begin + reg_rdata_next[0] = lp1_cmo_status_165_qs; end - addr_hit[183]: begin - reg_rdata_next[0] = lp1_cmo_commit_38_qs; + addr_hit[951]: begin + reg_rdata_next[0] = lp1_cmo_status_166_qs; end - addr_hit[184]: begin - reg_rdata_next[0] = lp1_cmo_commit_39_qs; + addr_hit[952]: begin + reg_rdata_next[0] = lp1_cmo_status_167_qs; end - addr_hit[185]: begin - reg_rdata_next[0] = lp1_cmo_commit_40_qs; + addr_hit[953]: begin + reg_rdata_next[0] = lp1_cmo_status_168_qs; end - addr_hit[186]: begin - reg_rdata_next[0] = lp1_cmo_commit_41_qs; + addr_hit[954]: begin + reg_rdata_next[0] = lp1_cmo_status_169_qs; end - addr_hit[187]: begin - reg_rdata_next[0] = lp1_cmo_commit_42_qs; + addr_hit[955]: begin + reg_rdata_next[0] = lp1_cmo_status_170_qs; end - addr_hit[188]: begin - reg_rdata_next[0] = lp1_cmo_commit_43_qs; + addr_hit[956]: begin + reg_rdata_next[0] = lp1_cmo_status_171_qs; end - addr_hit[189]: begin - reg_rdata_next[0] = lp1_cmo_commit_44_qs; + addr_hit[957]: begin + reg_rdata_next[0] = lp1_cmo_status_172_qs; end - addr_hit[190]: begin - reg_rdata_next[0] = lp1_cmo_commit_45_qs; + addr_hit[958]: begin + reg_rdata_next[0] = lp1_cmo_status_173_qs; end - addr_hit[191]: begin - reg_rdata_next[0] = lp1_cmo_commit_46_qs; + addr_hit[959]: begin + reg_rdata_next[0] = lp1_cmo_status_174_qs; end - addr_hit[192]: begin - reg_rdata_next[0] = lp1_cmo_commit_47_qs; + addr_hit[960]: begin + reg_rdata_next[0] = lp1_cmo_status_175_qs; end - addr_hit[193]: begin - reg_rdata_next[0] = lp1_cmo_commit_48_qs; + addr_hit[961]: begin + reg_rdata_next[0] = lp1_cmo_status_176_qs; end - addr_hit[194]: begin - reg_rdata_next[0] = lp1_cmo_commit_49_qs; + addr_hit[962]: begin + reg_rdata_next[0] = lp1_cmo_status_177_qs; end - addr_hit[195]: begin - reg_rdata_next[0] = lp1_cmo_commit_50_qs; + addr_hit[963]: begin + reg_rdata_next[0] = lp1_cmo_status_178_qs; end - addr_hit[196]: begin - reg_rdata_next[0] = lp1_cmo_commit_51_qs; + addr_hit[964]: begin + reg_rdata_next[0] = lp1_cmo_status_179_qs; end - addr_hit[197]: begin - reg_rdata_next[0] = lp1_cmo_commit_52_qs; + addr_hit[965]: begin + reg_rdata_next[0] = lp1_cmo_status_180_qs; end - addr_hit[198]: begin - reg_rdata_next[0] = lp1_cmo_commit_53_qs; + addr_hit[966]: begin + reg_rdata_next[0] = lp1_cmo_status_181_qs; end - addr_hit[199]: begin - reg_rdata_next[0] = lp1_cmo_commit_54_qs; + addr_hit[967]: begin + reg_rdata_next[0] = lp1_cmo_status_182_qs; end - addr_hit[200]: begin - reg_rdata_next[0] = lp1_cmo_commit_55_qs; + addr_hit[968]: begin + reg_rdata_next[0] = lp1_cmo_status_183_qs; end - addr_hit[201]: begin - reg_rdata_next[0] = lp1_cmo_commit_56_qs; + addr_hit[969]: begin + reg_rdata_next[0] = lp1_cmo_status_184_qs; end - addr_hit[202]: begin - reg_rdata_next[0] = lp1_cmo_commit_57_qs; + addr_hit[970]: begin + reg_rdata_next[0] = lp1_cmo_status_185_qs; end - addr_hit[203]: begin - reg_rdata_next[0] = lp1_cmo_commit_58_qs; + addr_hit[971]: begin + reg_rdata_next[0] = lp1_cmo_status_186_qs; end - addr_hit[204]: begin - reg_rdata_next[0] = lp1_cmo_commit_59_qs; + addr_hit[972]: begin + reg_rdata_next[0] = lp1_cmo_status_187_qs; end - addr_hit[205]: begin - reg_rdata_next[0] = lp1_cmo_commit_60_qs; + addr_hit[973]: begin + reg_rdata_next[0] = lp1_cmo_status_188_qs; end - addr_hit[206]: begin - reg_rdata_next[0] = lp1_cmo_commit_61_qs; + addr_hit[974]: begin + reg_rdata_next[0] = lp1_cmo_status_189_qs; end - addr_hit[207]: begin - reg_rdata_next[0] = lp1_cmo_commit_62_qs; + addr_hit[975]: begin + reg_rdata_next[0] = lp1_cmo_status_190_qs; end - addr_hit[208]: begin - reg_rdata_next[0] = lp1_cmo_commit_63_qs; + addr_hit[976]: begin + reg_rdata_next[0] = lp1_cmo_status_191_qs; end - addr_hit[209]: begin - reg_rdata_next[0] = lp1_cmo_status_0_qs; + addr_hit[977]: begin + reg_rdata_next[0] = lp1_cmo_status_192_qs; end - addr_hit[210]: begin - reg_rdata_next[0] = lp1_cmo_status_1_qs; + addr_hit[978]: begin + reg_rdata_next[0] = lp1_cmo_status_193_qs; end - addr_hit[211]: begin - reg_rdata_next[0] = lp1_cmo_status_2_qs; + addr_hit[979]: begin + reg_rdata_next[0] = lp1_cmo_status_194_qs; end - addr_hit[212]: begin - reg_rdata_next[0] = lp1_cmo_status_3_qs; + addr_hit[980]: begin + reg_rdata_next[0] = lp1_cmo_status_195_qs; end - addr_hit[213]: begin - reg_rdata_next[0] = lp1_cmo_status_4_qs; + addr_hit[981]: begin + reg_rdata_next[0] = lp1_cmo_status_196_qs; end - addr_hit[214]: begin - reg_rdata_next[0] = lp1_cmo_status_5_qs; + addr_hit[982]: begin + reg_rdata_next[0] = lp1_cmo_status_197_qs; end - addr_hit[215]: begin - reg_rdata_next[0] = lp1_cmo_status_6_qs; + addr_hit[983]: begin + reg_rdata_next[0] = lp1_cmo_status_198_qs; end - addr_hit[216]: begin - reg_rdata_next[0] = lp1_cmo_status_7_qs; + addr_hit[984]: begin + reg_rdata_next[0] = lp1_cmo_status_199_qs; end - addr_hit[217]: begin - reg_rdata_next[0] = lp1_cmo_status_8_qs; + addr_hit[985]: begin + reg_rdata_next[0] = lp1_cmo_status_200_qs; end - addr_hit[218]: begin - reg_rdata_next[0] = lp1_cmo_status_9_qs; + addr_hit[986]: begin + reg_rdata_next[0] = lp1_cmo_status_201_qs; end - addr_hit[219]: begin - reg_rdata_next[0] = lp1_cmo_status_10_qs; + addr_hit[987]: begin + reg_rdata_next[0] = lp1_cmo_status_202_qs; end - addr_hit[220]: begin - reg_rdata_next[0] = lp1_cmo_status_11_qs; + addr_hit[988]: begin + reg_rdata_next[0] = lp1_cmo_status_203_qs; end - addr_hit[221]: begin - reg_rdata_next[0] = lp1_cmo_status_12_qs; + addr_hit[989]: begin + reg_rdata_next[0] = lp1_cmo_status_204_qs; end - addr_hit[222]: begin - reg_rdata_next[0] = lp1_cmo_status_13_qs; + addr_hit[990]: begin + reg_rdata_next[0] = lp1_cmo_status_205_qs; end - addr_hit[223]: begin - reg_rdata_next[0] = lp1_cmo_status_14_qs; + addr_hit[991]: begin + reg_rdata_next[0] = lp1_cmo_status_206_qs; end - addr_hit[224]: begin - reg_rdata_next[0] = lp1_cmo_status_15_qs; + addr_hit[992]: begin + reg_rdata_next[0] = lp1_cmo_status_207_qs; end - addr_hit[225]: begin - reg_rdata_next[0] = lp1_cmo_status_16_qs; + addr_hit[993]: begin + reg_rdata_next[0] = lp1_cmo_status_208_qs; end - addr_hit[226]: begin - reg_rdata_next[0] = lp1_cmo_status_17_qs; + addr_hit[994]: begin + reg_rdata_next[0] = lp1_cmo_status_209_qs; end - addr_hit[227]: begin - reg_rdata_next[0] = lp1_cmo_status_18_qs; + addr_hit[995]: begin + reg_rdata_next[0] = lp1_cmo_status_210_qs; end - addr_hit[228]: begin - reg_rdata_next[0] = lp1_cmo_status_19_qs; + addr_hit[996]: begin + reg_rdata_next[0] = lp1_cmo_status_211_qs; end - addr_hit[229]: begin - reg_rdata_next[0] = lp1_cmo_status_20_qs; + addr_hit[997]: begin + reg_rdata_next[0] = lp1_cmo_status_212_qs; end - addr_hit[230]: begin - reg_rdata_next[0] = lp1_cmo_status_21_qs; + addr_hit[998]: begin + reg_rdata_next[0] = lp1_cmo_status_213_qs; end - addr_hit[231]: begin - reg_rdata_next[0] = lp1_cmo_status_22_qs; + addr_hit[999]: begin + reg_rdata_next[0] = lp1_cmo_status_214_qs; end - addr_hit[232]: begin - reg_rdata_next[0] = lp1_cmo_status_23_qs; + addr_hit[1000]: begin + reg_rdata_next[0] = lp1_cmo_status_215_qs; end - addr_hit[233]: begin - reg_rdata_next[0] = lp1_cmo_status_24_qs; + addr_hit[1001]: begin + reg_rdata_next[0] = lp1_cmo_status_216_qs; end - addr_hit[234]: begin - reg_rdata_next[0] = lp1_cmo_status_25_qs; + addr_hit[1002]: begin + reg_rdata_next[0] = lp1_cmo_status_217_qs; end - addr_hit[235]: begin - reg_rdata_next[0] = lp1_cmo_status_26_qs; + addr_hit[1003]: begin + reg_rdata_next[0] = lp1_cmo_status_218_qs; end - addr_hit[236]: begin - reg_rdata_next[0] = lp1_cmo_status_27_qs; + addr_hit[1004]: begin + reg_rdata_next[0] = lp1_cmo_status_219_qs; end - addr_hit[237]: begin - reg_rdata_next[0] = lp1_cmo_status_28_qs; + addr_hit[1005]: begin + reg_rdata_next[0] = lp1_cmo_status_220_qs; end - addr_hit[238]: begin - reg_rdata_next[0] = lp1_cmo_status_29_qs; + addr_hit[1006]: begin + reg_rdata_next[0] = lp1_cmo_status_221_qs; end - addr_hit[239]: begin - reg_rdata_next[0] = lp1_cmo_status_30_qs; + addr_hit[1007]: begin + reg_rdata_next[0] = lp1_cmo_status_222_qs; end - addr_hit[240]: begin - reg_rdata_next[0] = lp1_cmo_status_31_qs; + addr_hit[1008]: begin + reg_rdata_next[0] = lp1_cmo_status_223_qs; end - addr_hit[241]: begin - reg_rdata_next[0] = lp1_cmo_status_32_qs; + addr_hit[1009]: begin + reg_rdata_next[0] = lp1_cmo_status_224_qs; end - addr_hit[242]: begin - reg_rdata_next[0] = lp1_cmo_status_33_qs; + addr_hit[1010]: begin + reg_rdata_next[0] = lp1_cmo_status_225_qs; end - addr_hit[243]: begin - reg_rdata_next[0] = lp1_cmo_status_34_qs; + addr_hit[1011]: begin + reg_rdata_next[0] = lp1_cmo_status_226_qs; end - addr_hit[244]: begin - reg_rdata_next[0] = lp1_cmo_status_35_qs; + addr_hit[1012]: begin + reg_rdata_next[0] = lp1_cmo_status_227_qs; end - addr_hit[245]: begin - reg_rdata_next[0] = lp1_cmo_status_36_qs; + addr_hit[1013]: begin + reg_rdata_next[0] = lp1_cmo_status_228_qs; end - addr_hit[246]: begin - reg_rdata_next[0] = lp1_cmo_status_37_qs; + addr_hit[1014]: begin + reg_rdata_next[0] = lp1_cmo_status_229_qs; end - addr_hit[247]: begin - reg_rdata_next[0] = lp1_cmo_status_38_qs; + addr_hit[1015]: begin + reg_rdata_next[0] = lp1_cmo_status_230_qs; end - addr_hit[248]: begin - reg_rdata_next[0] = lp1_cmo_status_39_qs; + addr_hit[1016]: begin + reg_rdata_next[0] = lp1_cmo_status_231_qs; end - addr_hit[249]: begin - reg_rdata_next[0] = lp1_cmo_status_40_qs; + addr_hit[1017]: begin + reg_rdata_next[0] = lp1_cmo_status_232_qs; end - addr_hit[250]: begin - reg_rdata_next[0] = lp1_cmo_status_41_qs; + addr_hit[1018]: begin + reg_rdata_next[0] = lp1_cmo_status_233_qs; end - addr_hit[251]: begin - reg_rdata_next[0] = lp1_cmo_status_42_qs; + addr_hit[1019]: begin + reg_rdata_next[0] = lp1_cmo_status_234_qs; end - addr_hit[252]: begin - reg_rdata_next[0] = lp1_cmo_status_43_qs; + addr_hit[1020]: begin + reg_rdata_next[0] = lp1_cmo_status_235_qs; end - addr_hit[253]: begin - reg_rdata_next[0] = lp1_cmo_status_44_qs; + addr_hit[1021]: begin + reg_rdata_next[0] = lp1_cmo_status_236_qs; end - addr_hit[254]: begin - reg_rdata_next[0] = lp1_cmo_status_45_qs; + addr_hit[1022]: begin + reg_rdata_next[0] = lp1_cmo_status_237_qs; end - addr_hit[255]: begin - reg_rdata_next[0] = lp1_cmo_status_46_qs; + addr_hit[1023]: begin + reg_rdata_next[0] = lp1_cmo_status_238_qs; end - addr_hit[256]: begin - reg_rdata_next[0] = lp1_cmo_status_47_qs; + addr_hit[1024]: begin + reg_rdata_next[0] = lp1_cmo_status_239_qs; end - addr_hit[257]: begin - reg_rdata_next[0] = lp1_cmo_status_48_qs; + addr_hit[1025]: begin + reg_rdata_next[0] = lp1_cmo_status_240_qs; end - addr_hit[258]: begin - reg_rdata_next[0] = lp1_cmo_status_49_qs; + addr_hit[1026]: begin + reg_rdata_next[0] = lp1_cmo_status_241_qs; end - addr_hit[259]: begin - reg_rdata_next[0] = lp1_cmo_status_50_qs; + addr_hit[1027]: begin + reg_rdata_next[0] = lp1_cmo_status_242_qs; end - addr_hit[260]: begin - reg_rdata_next[0] = lp1_cmo_status_51_qs; + addr_hit[1028]: begin + reg_rdata_next[0] = lp1_cmo_status_243_qs; end - addr_hit[261]: begin - reg_rdata_next[0] = lp1_cmo_status_52_qs; + addr_hit[1029]: begin + reg_rdata_next[0] = lp1_cmo_status_244_qs; end - addr_hit[262]: begin - reg_rdata_next[0] = lp1_cmo_status_53_qs; + addr_hit[1030]: begin + reg_rdata_next[0] = lp1_cmo_status_245_qs; end - addr_hit[263]: begin - reg_rdata_next[0] = lp1_cmo_status_54_qs; + addr_hit[1031]: begin + reg_rdata_next[0] = lp1_cmo_status_246_qs; end - addr_hit[264]: begin - reg_rdata_next[0] = lp1_cmo_status_55_qs; + addr_hit[1032]: begin + reg_rdata_next[0] = lp1_cmo_status_247_qs; end - addr_hit[265]: begin - reg_rdata_next[0] = lp1_cmo_status_56_qs; + addr_hit[1033]: begin + reg_rdata_next[0] = lp1_cmo_status_248_qs; end - addr_hit[266]: begin - reg_rdata_next[0] = lp1_cmo_status_57_qs; + addr_hit[1034]: begin + reg_rdata_next[0] = lp1_cmo_status_249_qs; end - addr_hit[267]: begin - reg_rdata_next[0] = lp1_cmo_status_58_qs; + addr_hit[1035]: begin + reg_rdata_next[0] = lp1_cmo_status_250_qs; end - addr_hit[268]: begin - reg_rdata_next[0] = lp1_cmo_status_59_qs; + addr_hit[1036]: begin + reg_rdata_next[0] = lp1_cmo_status_251_qs; end - addr_hit[269]: begin - reg_rdata_next[0] = lp1_cmo_status_60_qs; + addr_hit[1037]: begin + reg_rdata_next[0] = lp1_cmo_status_252_qs; end - addr_hit[270]: begin - reg_rdata_next[0] = lp1_cmo_status_61_qs; + addr_hit[1038]: begin + reg_rdata_next[0] = lp1_cmo_status_253_qs; end - addr_hit[271]: begin - reg_rdata_next[0] = lp1_cmo_status_62_qs; + addr_hit[1039]: begin + reg_rdata_next[0] = lp1_cmo_status_254_qs; end - addr_hit[272]: begin - reg_rdata_next[0] = lp1_cmo_status_63_qs; + addr_hit[1040]: begin + reg_rdata_next[0] = lp1_cmo_status_255_qs; end default: begin @@ -9905,7 +37361,7 @@ endmodule module cachepool_peripheral_reg_top_intf #( - parameter int AW = 11, + parameter int AW = 13, localparam int DW = 32 ) ( input logic clk_i, diff --git a/software/snRuntime/include/cachepool_peripheral.h b/software/snRuntime/include/cachepool_peripheral.h index 9f347ab..cbca701 100644 --- a/software/snRuntime/include/cachepool_peripheral.h +++ b/software/snRuntime/include/cachepool_peripheral.h @@ -18,7 +18,7 @@ extern "C" { #define CACHEPOOL_PERIPHERAL_PARAM_NUM_TILE_SEL_REGS 2 // Number of per-core LP1 (private-L1) CMO register slots -- one per core / -#define CACHEPOOL_PERIPHERAL_PARAM_NUM_LP1_CMO_REGS 64 +#define CACHEPOOL_PERIPHERAL_PARAM_NUM_LP1_CMO_REGS 256 // Register width #define CACHEPOOL_PERIPHERAL_PARAM_REG_WIDTH 32 @@ -119,7 +119,7 @@ extern "C" { // Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), #define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_OP_FIELD_WIDTH 3 #define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_OP_FIELDS_PER_REG 10 -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_MULTIREG_COUNT 64 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_MULTIREG_COUNT 256 // Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), #define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_REG_OFFSET 0x44 @@ -697,724 +697,4564 @@ extern "C" { .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OP_63_MASK, \ .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_63_OP_63_OFFSET}) +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_64_REG_OFFSET 0x144 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_64_OP_64_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_64_OP_64_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_64_OP_64_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_64_OP_64_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_64_OP_64_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_65_REG_OFFSET 0x148 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_65_OP_65_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_65_OP_65_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_65_OP_65_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_65_OP_65_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_65_OP_65_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_66_REG_OFFSET 0x14c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_66_OP_66_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_66_OP_66_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_66_OP_66_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_66_OP_66_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_66_OP_66_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_67_REG_OFFSET 0x150 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_67_OP_67_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_67_OP_67_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_67_OP_67_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_67_OP_67_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_67_OP_67_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_68_REG_OFFSET 0x154 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_68_OP_68_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_68_OP_68_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_68_OP_68_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_68_OP_68_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_68_OP_68_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_69_REG_OFFSET 0x158 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_69_OP_69_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_69_OP_69_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_69_OP_69_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_69_OP_69_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_69_OP_69_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_70_REG_OFFSET 0x15c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_70_OP_70_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_70_OP_70_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_70_OP_70_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_70_OP_70_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_70_OP_70_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_71_REG_OFFSET 0x160 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_71_OP_71_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_71_OP_71_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_71_OP_71_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_71_OP_71_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_71_OP_71_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_72_REG_OFFSET 0x164 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_72_OP_72_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_72_OP_72_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_72_OP_72_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_72_OP_72_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_72_OP_72_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_73_REG_OFFSET 0x168 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_73_OP_73_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_73_OP_73_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_73_OP_73_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_73_OP_73_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_73_OP_73_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_74_REG_OFFSET 0x16c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_74_OP_74_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_74_OP_74_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_74_OP_74_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_74_OP_74_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_74_OP_74_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_75_REG_OFFSET 0x170 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_75_OP_75_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_75_OP_75_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_75_OP_75_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_75_OP_75_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_75_OP_75_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_76_REG_OFFSET 0x174 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_76_OP_76_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_76_OP_76_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_76_OP_76_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_76_OP_76_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_76_OP_76_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_77_REG_OFFSET 0x178 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_77_OP_77_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_77_OP_77_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_77_OP_77_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_77_OP_77_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_77_OP_77_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_78_REG_OFFSET 0x17c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_78_OP_78_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_78_OP_78_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_78_OP_78_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_78_OP_78_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_78_OP_78_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_79_REG_OFFSET 0x180 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_79_OP_79_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_79_OP_79_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_79_OP_79_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_79_OP_79_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_79_OP_79_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_80_REG_OFFSET 0x184 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_80_OP_80_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_80_OP_80_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_80_OP_80_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_80_OP_80_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_80_OP_80_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_81_REG_OFFSET 0x188 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_81_OP_81_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_81_OP_81_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_81_OP_81_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_81_OP_81_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_81_OP_81_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_82_REG_OFFSET 0x18c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_82_OP_82_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_82_OP_82_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_82_OP_82_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_82_OP_82_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_82_OP_82_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_83_REG_OFFSET 0x190 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_83_OP_83_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_83_OP_83_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_83_OP_83_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_83_OP_83_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_83_OP_83_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_84_REG_OFFSET 0x194 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_84_OP_84_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_84_OP_84_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_84_OP_84_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_84_OP_84_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_84_OP_84_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_85_REG_OFFSET 0x198 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_85_OP_85_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_85_OP_85_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_85_OP_85_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_85_OP_85_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_85_OP_85_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_86_REG_OFFSET 0x19c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_86_OP_86_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_86_OP_86_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_86_OP_86_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_86_OP_86_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_86_OP_86_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_87_REG_OFFSET 0x1a0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_87_OP_87_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_87_OP_87_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_87_OP_87_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_87_OP_87_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_87_OP_87_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_88_REG_OFFSET 0x1a4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_88_OP_88_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_88_OP_88_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_88_OP_88_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_88_OP_88_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_88_OP_88_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_89_REG_OFFSET 0x1a8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_89_OP_89_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_89_OP_89_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_89_OP_89_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_89_OP_89_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_89_OP_89_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_90_REG_OFFSET 0x1ac +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_90_OP_90_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_90_OP_90_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_90_OP_90_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_90_OP_90_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_90_OP_90_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_91_REG_OFFSET 0x1b0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_91_OP_91_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_91_OP_91_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_91_OP_91_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_91_OP_91_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_91_OP_91_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_92_REG_OFFSET 0x1b4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_92_OP_92_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_92_OP_92_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_92_OP_92_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_92_OP_92_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_92_OP_92_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_93_REG_OFFSET 0x1b8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_93_OP_93_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_93_OP_93_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_93_OP_93_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_93_OP_93_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_93_OP_93_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_94_REG_OFFSET 0x1bc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_94_OP_94_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_94_OP_94_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_94_OP_94_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_94_OP_94_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_94_OP_94_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_95_REG_OFFSET 0x1c0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_95_OP_95_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_95_OP_95_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_95_OP_95_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_95_OP_95_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_95_OP_95_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_96_REG_OFFSET 0x1c4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_96_OP_96_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_96_OP_96_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_96_OP_96_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_96_OP_96_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_96_OP_96_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_97_REG_OFFSET 0x1c8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_97_OP_97_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_97_OP_97_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_97_OP_97_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_97_OP_97_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_97_OP_97_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_98_REG_OFFSET 0x1cc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_98_OP_98_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_98_OP_98_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_98_OP_98_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_98_OP_98_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_98_OP_98_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_99_REG_OFFSET 0x1d0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_99_OP_99_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_99_OP_99_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_99_OP_99_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_99_OP_99_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_99_OP_99_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_100_REG_OFFSET 0x1d4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_100_OP_100_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_100_OP_100_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_100_OP_100_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_100_OP_100_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_100_OP_100_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_101_REG_OFFSET 0x1d8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_101_OP_101_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_101_OP_101_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_101_OP_101_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_101_OP_101_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_101_OP_101_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_102_REG_OFFSET 0x1dc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_102_OP_102_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_102_OP_102_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_102_OP_102_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_102_OP_102_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_102_OP_102_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_103_REG_OFFSET 0x1e0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_103_OP_103_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_103_OP_103_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_103_OP_103_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_103_OP_103_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_103_OP_103_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_104_REG_OFFSET 0x1e4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_104_OP_104_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_104_OP_104_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_104_OP_104_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_104_OP_104_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_104_OP_104_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_105_REG_OFFSET 0x1e8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_105_OP_105_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_105_OP_105_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_105_OP_105_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_105_OP_105_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_105_OP_105_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_106_REG_OFFSET 0x1ec +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_106_OP_106_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_106_OP_106_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_106_OP_106_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_106_OP_106_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_106_OP_106_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_107_REG_OFFSET 0x1f0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_107_OP_107_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_107_OP_107_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_107_OP_107_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_107_OP_107_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_107_OP_107_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_108_REG_OFFSET 0x1f4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_108_OP_108_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_108_OP_108_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_108_OP_108_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_108_OP_108_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_108_OP_108_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_109_REG_OFFSET 0x1f8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_109_OP_109_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_109_OP_109_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_109_OP_109_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_109_OP_109_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_109_OP_109_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_110_REG_OFFSET 0x1fc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_110_OP_110_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_110_OP_110_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_110_OP_110_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_110_OP_110_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_110_OP_110_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_111_REG_OFFSET 0x200 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_111_OP_111_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_111_OP_111_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_111_OP_111_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_111_OP_111_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_111_OP_111_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_112_REG_OFFSET 0x204 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_112_OP_112_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_112_OP_112_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_112_OP_112_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_112_OP_112_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_112_OP_112_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_113_REG_OFFSET 0x208 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_113_OP_113_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_113_OP_113_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_113_OP_113_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_113_OP_113_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_113_OP_113_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_114_REG_OFFSET 0x20c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_114_OP_114_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_114_OP_114_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_114_OP_114_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_114_OP_114_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_114_OP_114_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_115_REG_OFFSET 0x210 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_115_OP_115_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_115_OP_115_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_115_OP_115_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_115_OP_115_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_115_OP_115_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_116_REG_OFFSET 0x214 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_116_OP_116_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_116_OP_116_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_116_OP_116_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_116_OP_116_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_116_OP_116_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_117_REG_OFFSET 0x218 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_117_OP_117_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_117_OP_117_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_117_OP_117_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_117_OP_117_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_117_OP_117_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_118_REG_OFFSET 0x21c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_118_OP_118_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_118_OP_118_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_118_OP_118_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_118_OP_118_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_118_OP_118_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_119_REG_OFFSET 0x220 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_119_OP_119_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_119_OP_119_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_119_OP_119_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_119_OP_119_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_119_OP_119_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_120_REG_OFFSET 0x224 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_120_OP_120_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_120_OP_120_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_120_OP_120_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_120_OP_120_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_120_OP_120_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_121_REG_OFFSET 0x228 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_121_OP_121_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_121_OP_121_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_121_OP_121_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_121_OP_121_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_121_OP_121_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_122_REG_OFFSET 0x22c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_122_OP_122_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_122_OP_122_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_122_OP_122_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_122_OP_122_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_122_OP_122_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_123_REG_OFFSET 0x230 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_123_OP_123_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_123_OP_123_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_123_OP_123_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_123_OP_123_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_123_OP_123_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_124_REG_OFFSET 0x234 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_124_OP_124_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_124_OP_124_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_124_OP_124_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_124_OP_124_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_124_OP_124_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_125_REG_OFFSET 0x238 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_125_OP_125_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_125_OP_125_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_125_OP_125_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_125_OP_125_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_125_OP_125_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_126_REG_OFFSET 0x23c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_126_OP_126_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_126_OP_126_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_126_OP_126_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_126_OP_126_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_126_OP_126_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_127_REG_OFFSET 0x240 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_127_OP_127_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_127_OP_127_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_127_OP_127_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_127_OP_127_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_127_OP_127_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_128_REG_OFFSET 0x244 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_128_OP_128_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_128_OP_128_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_128_OP_128_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_128_OP_128_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_128_OP_128_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_129_REG_OFFSET 0x248 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_129_OP_129_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_129_OP_129_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_129_OP_129_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_129_OP_129_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_129_OP_129_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_130_REG_OFFSET 0x24c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_130_OP_130_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_130_OP_130_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_130_OP_130_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_130_OP_130_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_130_OP_130_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_131_REG_OFFSET 0x250 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_131_OP_131_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_131_OP_131_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_131_OP_131_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_131_OP_131_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_131_OP_131_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_132_REG_OFFSET 0x254 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_132_OP_132_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_132_OP_132_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_132_OP_132_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_132_OP_132_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_132_OP_132_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_133_REG_OFFSET 0x258 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_133_OP_133_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_133_OP_133_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_133_OP_133_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_133_OP_133_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_133_OP_133_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_134_REG_OFFSET 0x25c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_134_OP_134_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_134_OP_134_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_134_OP_134_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_134_OP_134_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_134_OP_134_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_135_REG_OFFSET 0x260 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_135_OP_135_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_135_OP_135_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_135_OP_135_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_135_OP_135_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_135_OP_135_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_136_REG_OFFSET 0x264 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_136_OP_136_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_136_OP_136_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_136_OP_136_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_136_OP_136_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_136_OP_136_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_137_REG_OFFSET 0x268 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_137_OP_137_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_137_OP_137_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_137_OP_137_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_137_OP_137_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_137_OP_137_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_138_REG_OFFSET 0x26c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_138_OP_138_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_138_OP_138_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_138_OP_138_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_138_OP_138_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_138_OP_138_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_139_REG_OFFSET 0x270 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_139_OP_139_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_139_OP_139_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_139_OP_139_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_139_OP_139_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_139_OP_139_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_140_REG_OFFSET 0x274 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_140_OP_140_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_140_OP_140_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_140_OP_140_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_140_OP_140_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_140_OP_140_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_141_REG_OFFSET 0x278 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_141_OP_141_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_141_OP_141_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_141_OP_141_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_141_OP_141_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_141_OP_141_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_142_REG_OFFSET 0x27c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_142_OP_142_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_142_OP_142_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_142_OP_142_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_142_OP_142_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_142_OP_142_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_143_REG_OFFSET 0x280 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_143_OP_143_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_143_OP_143_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_143_OP_143_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_143_OP_143_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_143_OP_143_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_144_REG_OFFSET 0x284 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_144_OP_144_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_144_OP_144_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_144_OP_144_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_144_OP_144_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_144_OP_144_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_145_REG_OFFSET 0x288 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_145_OP_145_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_145_OP_145_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_145_OP_145_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_145_OP_145_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_145_OP_145_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_146_REG_OFFSET 0x28c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_146_OP_146_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_146_OP_146_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_146_OP_146_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_146_OP_146_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_146_OP_146_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_147_REG_OFFSET 0x290 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_147_OP_147_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_147_OP_147_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_147_OP_147_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_147_OP_147_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_147_OP_147_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_148_REG_OFFSET 0x294 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_148_OP_148_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_148_OP_148_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_148_OP_148_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_148_OP_148_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_148_OP_148_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_149_REG_OFFSET 0x298 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_149_OP_149_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_149_OP_149_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_149_OP_149_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_149_OP_149_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_149_OP_149_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_150_REG_OFFSET 0x29c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_150_OP_150_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_150_OP_150_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_150_OP_150_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_150_OP_150_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_150_OP_150_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_151_REG_OFFSET 0x2a0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_151_OP_151_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_151_OP_151_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_151_OP_151_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_151_OP_151_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_151_OP_151_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_152_REG_OFFSET 0x2a4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_152_OP_152_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_152_OP_152_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_152_OP_152_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_152_OP_152_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_152_OP_152_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_153_REG_OFFSET 0x2a8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_153_OP_153_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_153_OP_153_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_153_OP_153_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_153_OP_153_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_153_OP_153_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_154_REG_OFFSET 0x2ac +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_154_OP_154_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_154_OP_154_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_154_OP_154_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_154_OP_154_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_154_OP_154_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_155_REG_OFFSET 0x2b0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_155_OP_155_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_155_OP_155_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_155_OP_155_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_155_OP_155_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_155_OP_155_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_156_REG_OFFSET 0x2b4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_156_OP_156_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_156_OP_156_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_156_OP_156_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_156_OP_156_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_156_OP_156_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_157_REG_OFFSET 0x2b8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_157_OP_157_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_157_OP_157_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_157_OP_157_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_157_OP_157_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_157_OP_157_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_158_REG_OFFSET 0x2bc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_158_OP_158_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_158_OP_158_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_158_OP_158_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_158_OP_158_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_158_OP_158_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_159_REG_OFFSET 0x2c0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_159_OP_159_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_159_OP_159_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_159_OP_159_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_159_OP_159_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_159_OP_159_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_160_REG_OFFSET 0x2c4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_160_OP_160_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_160_OP_160_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_160_OP_160_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_160_OP_160_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_160_OP_160_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_161_REG_OFFSET 0x2c8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_161_OP_161_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_161_OP_161_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_161_OP_161_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_161_OP_161_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_161_OP_161_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_162_REG_OFFSET 0x2cc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_162_OP_162_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_162_OP_162_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_162_OP_162_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_162_OP_162_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_162_OP_162_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_163_REG_OFFSET 0x2d0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_163_OP_163_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_163_OP_163_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_163_OP_163_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_163_OP_163_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_163_OP_163_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_164_REG_OFFSET 0x2d4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_164_OP_164_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_164_OP_164_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_164_OP_164_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_164_OP_164_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_164_OP_164_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_165_REG_OFFSET 0x2d8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_165_OP_165_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_165_OP_165_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_165_OP_165_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_165_OP_165_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_165_OP_165_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_166_REG_OFFSET 0x2dc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_166_OP_166_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_166_OP_166_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_166_OP_166_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_166_OP_166_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_166_OP_166_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_167_REG_OFFSET 0x2e0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_167_OP_167_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_167_OP_167_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_167_OP_167_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_167_OP_167_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_167_OP_167_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_168_REG_OFFSET 0x2e4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_168_OP_168_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_168_OP_168_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_168_OP_168_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_168_OP_168_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_168_OP_168_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_169_REG_OFFSET 0x2e8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_169_OP_169_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_169_OP_169_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_169_OP_169_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_169_OP_169_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_169_OP_169_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_170_REG_OFFSET 0x2ec +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_170_OP_170_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_170_OP_170_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_170_OP_170_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_170_OP_170_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_170_OP_170_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_171_REG_OFFSET 0x2f0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_171_OP_171_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_171_OP_171_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_171_OP_171_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_171_OP_171_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_171_OP_171_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_172_REG_OFFSET 0x2f4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_172_OP_172_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_172_OP_172_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_172_OP_172_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_172_OP_172_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_172_OP_172_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_173_REG_OFFSET 0x2f8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_173_OP_173_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_173_OP_173_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_173_OP_173_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_173_OP_173_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_173_OP_173_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_174_REG_OFFSET 0x2fc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_174_OP_174_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_174_OP_174_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_174_OP_174_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_174_OP_174_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_174_OP_174_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_175_REG_OFFSET 0x300 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_175_OP_175_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_175_OP_175_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_175_OP_175_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_175_OP_175_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_175_OP_175_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_176_REG_OFFSET 0x304 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_176_OP_176_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_176_OP_176_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_176_OP_176_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_176_OP_176_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_176_OP_176_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_177_REG_OFFSET 0x308 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_177_OP_177_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_177_OP_177_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_177_OP_177_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_177_OP_177_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_177_OP_177_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_178_REG_OFFSET 0x30c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_178_OP_178_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_178_OP_178_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_178_OP_178_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_178_OP_178_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_178_OP_178_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_179_REG_OFFSET 0x310 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_179_OP_179_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_179_OP_179_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_179_OP_179_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_179_OP_179_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_179_OP_179_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_180_REG_OFFSET 0x314 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_180_OP_180_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_180_OP_180_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_180_OP_180_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_180_OP_180_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_180_OP_180_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_181_REG_OFFSET 0x318 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_181_OP_181_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_181_OP_181_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_181_OP_181_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_181_OP_181_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_181_OP_181_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_182_REG_OFFSET 0x31c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_182_OP_182_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_182_OP_182_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_182_OP_182_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_182_OP_182_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_182_OP_182_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_183_REG_OFFSET 0x320 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_183_OP_183_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_183_OP_183_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_183_OP_183_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_183_OP_183_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_183_OP_183_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_184_REG_OFFSET 0x324 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_184_OP_184_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_184_OP_184_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_184_OP_184_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_184_OP_184_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_184_OP_184_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_185_REG_OFFSET 0x328 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_185_OP_185_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_185_OP_185_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_185_OP_185_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_185_OP_185_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_185_OP_185_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_186_REG_OFFSET 0x32c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_186_OP_186_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_186_OP_186_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_186_OP_186_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_186_OP_186_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_186_OP_186_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_187_REG_OFFSET 0x330 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_187_OP_187_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_187_OP_187_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_187_OP_187_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_187_OP_187_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_187_OP_187_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_188_REG_OFFSET 0x334 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_188_OP_188_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_188_OP_188_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_188_OP_188_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_188_OP_188_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_188_OP_188_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_189_REG_OFFSET 0x338 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_189_OP_189_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_189_OP_189_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_189_OP_189_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_189_OP_189_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_189_OP_189_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_190_REG_OFFSET 0x33c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_190_OP_190_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_190_OP_190_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_190_OP_190_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_190_OP_190_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_190_OP_190_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_191_REG_OFFSET 0x340 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_191_OP_191_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_191_OP_191_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_191_OP_191_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_191_OP_191_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_191_OP_191_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_192_REG_OFFSET 0x344 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_192_OP_192_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_192_OP_192_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_192_OP_192_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_192_OP_192_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_192_OP_192_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_193_REG_OFFSET 0x348 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_193_OP_193_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_193_OP_193_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_193_OP_193_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_193_OP_193_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_193_OP_193_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_194_REG_OFFSET 0x34c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_194_OP_194_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_194_OP_194_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_194_OP_194_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_194_OP_194_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_194_OP_194_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_195_REG_OFFSET 0x350 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_195_OP_195_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_195_OP_195_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_195_OP_195_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_195_OP_195_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_195_OP_195_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_196_REG_OFFSET 0x354 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_196_OP_196_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_196_OP_196_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_196_OP_196_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_196_OP_196_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_196_OP_196_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_197_REG_OFFSET 0x358 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_197_OP_197_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_197_OP_197_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_197_OP_197_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_197_OP_197_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_197_OP_197_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_198_REG_OFFSET 0x35c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_198_OP_198_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_198_OP_198_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_198_OP_198_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_198_OP_198_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_198_OP_198_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_199_REG_OFFSET 0x360 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_199_OP_199_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_199_OP_199_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_199_OP_199_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_199_OP_199_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_199_OP_199_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_200_REG_OFFSET 0x364 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_200_OP_200_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_200_OP_200_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_200_OP_200_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_200_OP_200_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_200_OP_200_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_201_REG_OFFSET 0x368 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_201_OP_201_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_201_OP_201_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_201_OP_201_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_201_OP_201_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_201_OP_201_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_202_REG_OFFSET 0x36c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_202_OP_202_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_202_OP_202_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_202_OP_202_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_202_OP_202_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_202_OP_202_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_203_REG_OFFSET 0x370 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_203_OP_203_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_203_OP_203_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_203_OP_203_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_203_OP_203_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_203_OP_203_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_204_REG_OFFSET 0x374 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_204_OP_204_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_204_OP_204_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_204_OP_204_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_204_OP_204_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_204_OP_204_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_205_REG_OFFSET 0x378 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_205_OP_205_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_205_OP_205_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_205_OP_205_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_205_OP_205_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_205_OP_205_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_206_REG_OFFSET 0x37c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_206_OP_206_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_206_OP_206_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_206_OP_206_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_206_OP_206_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_206_OP_206_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_207_REG_OFFSET 0x380 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_207_OP_207_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_207_OP_207_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_207_OP_207_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_207_OP_207_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_207_OP_207_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_208_REG_OFFSET 0x384 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_208_OP_208_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_208_OP_208_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_208_OP_208_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_208_OP_208_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_208_OP_208_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_209_REG_OFFSET 0x388 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_209_OP_209_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_209_OP_209_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_209_OP_209_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_209_OP_209_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_209_OP_209_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_210_REG_OFFSET 0x38c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_210_OP_210_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_210_OP_210_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_210_OP_210_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_210_OP_210_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_210_OP_210_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_211_REG_OFFSET 0x390 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_211_OP_211_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_211_OP_211_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_211_OP_211_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_211_OP_211_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_211_OP_211_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_212_REG_OFFSET 0x394 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_212_OP_212_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_212_OP_212_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_212_OP_212_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_212_OP_212_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_212_OP_212_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_213_REG_OFFSET 0x398 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_213_OP_213_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_213_OP_213_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_213_OP_213_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_213_OP_213_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_213_OP_213_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_214_REG_OFFSET 0x39c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_214_OP_214_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_214_OP_214_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_214_OP_214_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_214_OP_214_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_214_OP_214_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_215_REG_OFFSET 0x3a0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_215_OP_215_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_215_OP_215_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_215_OP_215_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_215_OP_215_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_215_OP_215_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_216_REG_OFFSET 0x3a4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_216_OP_216_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_216_OP_216_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_216_OP_216_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_216_OP_216_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_216_OP_216_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_217_REG_OFFSET 0x3a8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_217_OP_217_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_217_OP_217_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_217_OP_217_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_217_OP_217_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_217_OP_217_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_218_REG_OFFSET 0x3ac +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_218_OP_218_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_218_OP_218_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_218_OP_218_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_218_OP_218_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_218_OP_218_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_219_REG_OFFSET 0x3b0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_219_OP_219_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_219_OP_219_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_219_OP_219_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_219_OP_219_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_219_OP_219_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_220_REG_OFFSET 0x3b4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_220_OP_220_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_220_OP_220_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_220_OP_220_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_220_OP_220_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_220_OP_220_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_221_REG_OFFSET 0x3b8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_221_OP_221_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_221_OP_221_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_221_OP_221_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_221_OP_221_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_221_OP_221_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_222_REG_OFFSET 0x3bc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_222_OP_222_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_222_OP_222_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_222_OP_222_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_222_OP_222_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_222_OP_222_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_223_REG_OFFSET 0x3c0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_223_OP_223_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_223_OP_223_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_223_OP_223_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_223_OP_223_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_223_OP_223_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_224_REG_OFFSET 0x3c4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_224_OP_224_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_224_OP_224_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_224_OP_224_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_224_OP_224_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_224_OP_224_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_225_REG_OFFSET 0x3c8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_225_OP_225_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_225_OP_225_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_225_OP_225_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_225_OP_225_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_225_OP_225_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_226_REG_OFFSET 0x3cc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_226_OP_226_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_226_OP_226_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_226_OP_226_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_226_OP_226_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_226_OP_226_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_227_REG_OFFSET 0x3d0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_227_OP_227_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_227_OP_227_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_227_OP_227_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_227_OP_227_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_227_OP_227_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_228_REG_OFFSET 0x3d4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_228_OP_228_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_228_OP_228_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_228_OP_228_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_228_OP_228_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_228_OP_228_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_229_REG_OFFSET 0x3d8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_229_OP_229_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_229_OP_229_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_229_OP_229_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_229_OP_229_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_229_OP_229_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_230_REG_OFFSET 0x3dc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_230_OP_230_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_230_OP_230_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_230_OP_230_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_230_OP_230_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_230_OP_230_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_231_REG_OFFSET 0x3e0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_231_OP_231_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_231_OP_231_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_231_OP_231_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_231_OP_231_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_231_OP_231_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_232_REG_OFFSET 0x3e4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_232_OP_232_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_232_OP_232_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_232_OP_232_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_232_OP_232_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_232_OP_232_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_233_REG_OFFSET 0x3e8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_233_OP_233_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_233_OP_233_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_233_OP_233_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_233_OP_233_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_233_OP_233_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_234_REG_OFFSET 0x3ec +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_234_OP_234_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_234_OP_234_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_234_OP_234_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_234_OP_234_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_234_OP_234_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_235_REG_OFFSET 0x3f0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_235_OP_235_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_235_OP_235_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_235_OP_235_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_235_OP_235_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_235_OP_235_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_236_REG_OFFSET 0x3f4 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_236_OP_236_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_236_OP_236_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_236_OP_236_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_236_OP_236_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_236_OP_236_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_237_REG_OFFSET 0x3f8 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_237_OP_237_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_237_OP_237_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_237_OP_237_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_237_OP_237_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_237_OP_237_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_238_REG_OFFSET 0x3fc +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_238_OP_238_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_238_OP_238_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_238_OP_238_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_238_OP_238_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_238_OP_238_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_239_REG_OFFSET 0x400 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_239_OP_239_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_239_OP_239_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_239_OP_239_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_239_OP_239_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_239_OP_239_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_240_REG_OFFSET 0x404 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_240_OP_240_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_240_OP_240_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_240_OP_240_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_240_OP_240_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_240_OP_240_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_241_REG_OFFSET 0x408 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_241_OP_241_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_241_OP_241_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_241_OP_241_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_241_OP_241_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_241_OP_241_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_242_REG_OFFSET 0x40c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_242_OP_242_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_242_OP_242_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_242_OP_242_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_242_OP_242_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_242_OP_242_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_243_REG_OFFSET 0x410 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_243_OP_243_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_243_OP_243_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_243_OP_243_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_243_OP_243_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_243_OP_243_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_244_REG_OFFSET 0x414 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_244_OP_244_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_244_OP_244_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_244_OP_244_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_244_OP_244_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_244_OP_244_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_245_REG_OFFSET 0x418 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_245_OP_245_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_245_OP_245_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_245_OP_245_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_245_OP_245_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_245_OP_245_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_246_REG_OFFSET 0x41c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_246_OP_246_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_246_OP_246_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_246_OP_246_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_246_OP_246_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_246_OP_246_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_247_REG_OFFSET 0x420 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_247_OP_247_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_247_OP_247_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_247_OP_247_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_247_OP_247_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_247_OP_247_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_248_REG_OFFSET 0x424 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_248_OP_248_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_248_OP_248_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_248_OP_248_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_248_OP_248_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_248_OP_248_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_249_REG_OFFSET 0x428 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_249_OP_249_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_249_OP_249_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_249_OP_249_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_249_OP_249_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_249_OP_249_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_250_REG_OFFSET 0x42c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_250_OP_250_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_250_OP_250_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_250_OP_250_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_250_OP_250_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_250_OP_250_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_251_REG_OFFSET 0x430 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_251_OP_251_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_251_OP_251_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_251_OP_251_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_251_OP_251_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_251_OP_251_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_252_REG_OFFSET 0x434 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_252_OP_252_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_252_OP_252_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_252_OP_252_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_252_OP_252_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_252_OP_252_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_253_REG_OFFSET 0x438 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_253_OP_253_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_253_OP_253_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_253_OP_253_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_253_OP_253_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_253_OP_253_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_254_REG_OFFSET 0x43c +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_254_OP_254_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_254_OP_254_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_254_OP_254_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_254_OP_254_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_254_OP_254_OFFSET}) + +// Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_255_REG_OFFSET 0x440 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_255_OP_255_MASK 0x7 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_255_OP_255_OFFSET 0 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_255_OP_255_FIELD \ + ((bitfield_field32_t){ \ + .mask = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_255_OP_255_MASK, \ + .index = CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_255_OP_255_OFFSET}) + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_ADDR_FIELD_WIDTH 32 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_ADDR_FIELDS_PER_REG 1 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_MULTIREG_COUNT 256 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0_REG_OFFSET 0x444 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1_REG_OFFSET 0x448 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2_REG_OFFSET 0x44c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3_REG_OFFSET 0x450 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4_REG_OFFSET 0x454 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5_REG_OFFSET 0x458 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6_REG_OFFSET 0x45c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7_REG_OFFSET 0x460 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8_REG_OFFSET 0x464 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9_REG_OFFSET 0x468 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10_REG_OFFSET 0x46c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11_REG_OFFSET 0x470 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12_REG_OFFSET 0x474 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13_REG_OFFSET 0x478 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14_REG_OFFSET 0x47c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15_REG_OFFSET 0x480 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16_REG_OFFSET 0x484 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17_REG_OFFSET 0x488 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18_REG_OFFSET 0x48c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19_REG_OFFSET 0x490 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20_REG_OFFSET 0x494 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21_REG_OFFSET 0x498 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22_REG_OFFSET 0x49c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23_REG_OFFSET 0x4a0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24_REG_OFFSET 0x4a4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25_REG_OFFSET 0x4a8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26_REG_OFFSET 0x4ac + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27_REG_OFFSET 0x4b0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28_REG_OFFSET 0x4b4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29_REG_OFFSET 0x4b8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30_REG_OFFSET 0x4bc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31_REG_OFFSET 0x4c0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32_REG_OFFSET 0x4c4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33_REG_OFFSET 0x4c8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34_REG_OFFSET 0x4cc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35_REG_OFFSET 0x4d0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36_REG_OFFSET 0x4d4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37_REG_OFFSET 0x4d8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38_REG_OFFSET 0x4dc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39_REG_OFFSET 0x4e0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40_REG_OFFSET 0x4e4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41_REG_OFFSET 0x4e8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42_REG_OFFSET 0x4ec + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43_REG_OFFSET 0x4f0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44_REG_OFFSET 0x4f4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45_REG_OFFSET 0x4f8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46_REG_OFFSET 0x4fc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47_REG_OFFSET 0x500 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48_REG_OFFSET 0x504 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49_REG_OFFSET 0x508 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50_REG_OFFSET 0x50c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51_REG_OFFSET 0x510 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52_REG_OFFSET 0x514 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53_REG_OFFSET 0x518 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54_REG_OFFSET 0x51c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55_REG_OFFSET 0x520 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56_REG_OFFSET 0x524 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57_REG_OFFSET 0x528 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58_REG_OFFSET 0x52c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59_REG_OFFSET 0x530 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60_REG_OFFSET 0x534 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61_REG_OFFSET 0x538 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62_REG_OFFSET 0x53c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63_REG_OFFSET 0x540 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_64_REG_OFFSET 0x544 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_65_REG_OFFSET 0x548 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_66_REG_OFFSET 0x54c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_67_REG_OFFSET 0x550 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_68_REG_OFFSET 0x554 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_69_REG_OFFSET 0x558 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_70_REG_OFFSET 0x55c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_71_REG_OFFSET 0x560 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_72_REG_OFFSET 0x564 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_73_REG_OFFSET 0x568 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_74_REG_OFFSET 0x56c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_75_REG_OFFSET 0x570 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_76_REG_OFFSET 0x574 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_77_REG_OFFSET 0x578 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_78_REG_OFFSET 0x57c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_79_REG_OFFSET 0x580 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_80_REG_OFFSET 0x584 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_81_REG_OFFSET 0x588 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_82_REG_OFFSET 0x58c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_83_REG_OFFSET 0x590 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_84_REG_OFFSET 0x594 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_85_REG_OFFSET 0x598 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_86_REG_OFFSET 0x59c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_87_REG_OFFSET 0x5a0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_88_REG_OFFSET 0x5a4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_89_REG_OFFSET 0x5a8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_90_REG_OFFSET 0x5ac + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_91_REG_OFFSET 0x5b0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_92_REG_OFFSET 0x5b4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_93_REG_OFFSET 0x5b8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_94_REG_OFFSET 0x5bc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_95_REG_OFFSET 0x5c0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_96_REG_OFFSET 0x5c4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_97_REG_OFFSET 0x5c8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_98_REG_OFFSET 0x5cc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_99_REG_OFFSET 0x5d0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_100_REG_OFFSET 0x5d4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_101_REG_OFFSET 0x5d8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_102_REG_OFFSET 0x5dc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_103_REG_OFFSET 0x5e0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_104_REG_OFFSET 0x5e4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_105_REG_OFFSET 0x5e8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_106_REG_OFFSET 0x5ec + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_107_REG_OFFSET 0x5f0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_108_REG_OFFSET 0x5f4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_109_REG_OFFSET 0x5f8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_110_REG_OFFSET 0x5fc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_111_REG_OFFSET 0x600 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_112_REG_OFFSET 0x604 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_113_REG_OFFSET 0x608 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_114_REG_OFFSET 0x60c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_115_REG_OFFSET 0x610 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_116_REG_OFFSET 0x614 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_117_REG_OFFSET 0x618 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_118_REG_OFFSET 0x61c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_119_REG_OFFSET 0x620 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_120_REG_OFFSET 0x624 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_121_REG_OFFSET 0x628 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_122_REG_OFFSET 0x62c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_123_REG_OFFSET 0x630 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_124_REG_OFFSET 0x634 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_125_REG_OFFSET 0x638 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_126_REG_OFFSET 0x63c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_127_REG_OFFSET 0x640 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_128_REG_OFFSET 0x644 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_129_REG_OFFSET 0x648 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_130_REG_OFFSET 0x64c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_131_REG_OFFSET 0x650 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_132_REG_OFFSET 0x654 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_133_REG_OFFSET 0x658 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_134_REG_OFFSET 0x65c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_135_REG_OFFSET 0x660 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_136_REG_OFFSET 0x664 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_137_REG_OFFSET 0x668 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_138_REG_OFFSET 0x66c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_139_REG_OFFSET 0x670 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_140_REG_OFFSET 0x674 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_141_REG_OFFSET 0x678 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_142_REG_OFFSET 0x67c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_143_REG_OFFSET 0x680 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_144_REG_OFFSET 0x684 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_145_REG_OFFSET 0x688 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_146_REG_OFFSET 0x68c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_147_REG_OFFSET 0x690 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_148_REG_OFFSET 0x694 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_149_REG_OFFSET 0x698 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_150_REG_OFFSET 0x69c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_151_REG_OFFSET 0x6a0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_152_REG_OFFSET 0x6a4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_153_REG_OFFSET 0x6a8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_154_REG_OFFSET 0x6ac + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_155_REG_OFFSET 0x6b0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_156_REG_OFFSET 0x6b4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_157_REG_OFFSET 0x6b8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_158_REG_OFFSET 0x6bc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_159_REG_OFFSET 0x6c0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_160_REG_OFFSET 0x6c4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_161_REG_OFFSET 0x6c8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_162_REG_OFFSET 0x6cc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_163_REG_OFFSET 0x6d0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_164_REG_OFFSET 0x6d4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_165_REG_OFFSET 0x6d8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_166_REG_OFFSET 0x6dc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_167_REG_OFFSET 0x6e0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_168_REG_OFFSET 0x6e4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_169_REG_OFFSET 0x6e8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_170_REG_OFFSET 0x6ec + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_171_REG_OFFSET 0x6f0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_172_REG_OFFSET 0x6f4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_173_REG_OFFSET 0x6f8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_174_REG_OFFSET 0x6fc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_175_REG_OFFSET 0x700 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_176_REG_OFFSET 0x704 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_177_REG_OFFSET 0x708 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_178_REG_OFFSET 0x70c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_179_REG_OFFSET 0x710 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_180_REG_OFFSET 0x714 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_181_REG_OFFSET 0x718 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_182_REG_OFFSET 0x71c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_183_REG_OFFSET 0x720 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_184_REG_OFFSET 0x724 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_185_REG_OFFSET 0x728 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_186_REG_OFFSET 0x72c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_187_REG_OFFSET 0x730 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_188_REG_OFFSET 0x734 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_189_REG_OFFSET 0x738 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_190_REG_OFFSET 0x73c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_191_REG_OFFSET 0x740 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_192_REG_OFFSET 0x744 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_193_REG_OFFSET 0x748 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_194_REG_OFFSET 0x74c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_195_REG_OFFSET 0x750 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_196_REG_OFFSET 0x754 + // Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_ADDR_FIELD_WIDTH 32 -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_ADDR_FIELDS_PER_REG 1 -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_MULTIREG_COUNT 64 +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_197_REG_OFFSET 0x758 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_198_REG_OFFSET 0x75c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_199_REG_OFFSET 0x760 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_200_REG_OFFSET 0x764 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_201_REG_OFFSET 0x768 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_202_REG_OFFSET 0x76c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_203_REG_OFFSET 0x770 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_204_REG_OFFSET 0x774 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_205_REG_OFFSET 0x778 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_206_REG_OFFSET 0x77c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_207_REG_OFFSET 0x780 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_208_REG_OFFSET 0x784 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_209_REG_OFFSET 0x788 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_210_REG_OFFSET 0x78c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_211_REG_OFFSET 0x790 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_212_REG_OFFSET 0x794 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_213_REG_OFFSET 0x798 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_214_REG_OFFSET 0x79c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_215_REG_OFFSET 0x7a0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_216_REG_OFFSET 0x7a4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_217_REG_OFFSET 0x7a8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_218_REG_OFFSET 0x7ac + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_219_REG_OFFSET 0x7b0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_220_REG_OFFSET 0x7b4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_221_REG_OFFSET 0x7b8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_222_REG_OFFSET 0x7bc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_223_REG_OFFSET 0x7c0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_224_REG_OFFSET 0x7c4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_225_REG_OFFSET 0x7c8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_226_REG_OFFSET 0x7cc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_227_REG_OFFSET 0x7d0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_228_REG_OFFSET 0x7d4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_229_REG_OFFSET 0x7d8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_230_REG_OFFSET 0x7dc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_231_REG_OFFSET 0x7e0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_232_REG_OFFSET 0x7e4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_233_REG_OFFSET 0x7e8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_234_REG_OFFSET 0x7ec + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_235_REG_OFFSET 0x7f0 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_236_REG_OFFSET 0x7f4 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_237_REG_OFFSET 0x7f8 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_238_REG_OFFSET 0x7fc + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_239_REG_OFFSET 0x800 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_240_REG_OFFSET 0x804 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_241_REG_OFFSET 0x808 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_242_REG_OFFSET 0x80c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_243_REG_OFFSET 0x810 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_244_REG_OFFSET 0x814 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_245_REG_OFFSET 0x818 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_246_REG_OFFSET 0x81c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_247_REG_OFFSET 0x820 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_248_REG_OFFSET 0x824 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_249_REG_OFFSET 0x828 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_250_REG_OFFSET 0x82c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_251_REG_OFFSET 0x830 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_252_REG_OFFSET 0x834 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_253_REG_OFFSET 0x838 + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_254_REG_OFFSET 0x83c + +// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for +#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_255_REG_OFFSET 0x840 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_COMMIT_FIELD_WIDTH 1 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_COMMIT_FIELDS_PER_REG 32 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_MULTIREG_COUNT 256 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_REG_OFFSET 0x844 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_COMMIT_0_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_REG_OFFSET 0x848 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_COMMIT_1_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_REG_OFFSET 0x84c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_COMMIT_2_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_REG_OFFSET 0x850 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_COMMIT_3_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_REG_OFFSET 0x854 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_COMMIT_4_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_REG_OFFSET 0x858 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_COMMIT_5_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_REG_OFFSET 0x85c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_COMMIT_6_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_REG_OFFSET 0x860 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_COMMIT_7_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_REG_OFFSET 0x864 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_COMMIT_8_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_REG_OFFSET 0x868 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_COMMIT_9_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_REG_OFFSET 0x86c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_COMMIT_10_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_REG_OFFSET 0x870 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_COMMIT_11_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_REG_OFFSET 0x874 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_COMMIT_12_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_REG_OFFSET 0x878 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_COMMIT_13_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_REG_OFFSET 0x87c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_COMMIT_14_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_REG_OFFSET 0x880 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_COMMIT_15_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_REG_OFFSET 0x884 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_COMMIT_16_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_REG_OFFSET 0x888 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_COMMIT_17_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_REG_OFFSET 0x88c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_COMMIT_18_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_REG_OFFSET 0x890 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_COMMIT_19_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_REG_OFFSET 0x894 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_COMMIT_20_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_REG_OFFSET 0x898 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_COMMIT_21_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_REG_OFFSET 0x89c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_COMMIT_22_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_REG_OFFSET 0x8a0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_COMMIT_23_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_REG_OFFSET 0x8a4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_COMMIT_24_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_REG_OFFSET 0x8a8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_COMMIT_25_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_REG_OFFSET 0x8ac +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_COMMIT_26_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_REG_OFFSET 0x8b0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_COMMIT_27_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_REG_OFFSET 0x8b4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_COMMIT_28_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_REG_OFFSET 0x8b8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_COMMIT_29_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_REG_OFFSET 0x8bc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_COMMIT_30_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_REG_OFFSET 0x8c0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_COMMIT_31_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_REG_OFFSET 0x8c4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_COMMIT_32_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_REG_OFFSET 0x8c8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_COMMIT_33_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_REG_OFFSET 0x8cc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_COMMIT_34_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_REG_OFFSET 0x8d0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_COMMIT_35_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_REG_OFFSET 0x8d4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_COMMIT_36_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_REG_OFFSET 0x8d8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_COMMIT_37_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_REG_OFFSET 0x8dc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_COMMIT_38_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_REG_OFFSET 0x8e0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_COMMIT_39_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_REG_OFFSET 0x8e4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_COMMIT_40_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_REG_OFFSET 0x8e8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_COMMIT_41_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_REG_OFFSET 0x8ec +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_COMMIT_42_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_REG_OFFSET 0x8f0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_COMMIT_43_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_REG_OFFSET 0x8f4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_COMMIT_44_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_REG_OFFSET 0x8f8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_COMMIT_45_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_REG_OFFSET 0x8fc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_COMMIT_46_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_REG_OFFSET 0x900 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_COMMIT_47_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_REG_OFFSET 0x904 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_COMMIT_48_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_REG_OFFSET 0x908 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_COMMIT_49_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_REG_OFFSET 0x90c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_COMMIT_50_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_REG_OFFSET 0x910 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_COMMIT_51_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_REG_OFFSET 0x914 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_COMMIT_52_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_REG_OFFSET 0x918 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_COMMIT_53_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_REG_OFFSET 0x91c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_COMMIT_54_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_REG_OFFSET 0x920 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_COMMIT_55_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_REG_OFFSET 0x924 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_COMMIT_56_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_REG_OFFSET 0x928 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_COMMIT_57_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_REG_OFFSET 0x92c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_COMMIT_58_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_REG_OFFSET 0x930 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_COMMIT_59_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_REG_OFFSET 0x934 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_COMMIT_60_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_REG_OFFSET 0x938 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_COMMIT_61_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_REG_OFFSET 0x93c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_COMMIT_62_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_REG_OFFSET 0x940 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_COMMIT_63_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_64_REG_OFFSET 0x944 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_64_COMMIT_64_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_65_REG_OFFSET 0x948 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_65_COMMIT_65_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_66_REG_OFFSET 0x94c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_66_COMMIT_66_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_67_REG_OFFSET 0x950 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_67_COMMIT_67_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_68_REG_OFFSET 0x954 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_68_COMMIT_68_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_69_REG_OFFSET 0x958 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_69_COMMIT_69_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_70_REG_OFFSET 0x95c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_70_COMMIT_70_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_71_REG_OFFSET 0x960 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_71_COMMIT_71_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_72_REG_OFFSET 0x964 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_72_COMMIT_72_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_73_REG_OFFSET 0x968 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_73_COMMIT_73_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_74_REG_OFFSET 0x96c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_74_COMMIT_74_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_75_REG_OFFSET 0x970 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_75_COMMIT_75_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_76_REG_OFFSET 0x974 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_76_COMMIT_76_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_77_REG_OFFSET 0x978 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_77_COMMIT_77_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_78_REG_OFFSET 0x97c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_78_COMMIT_78_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_79_REG_OFFSET 0x980 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_79_COMMIT_79_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_80_REG_OFFSET 0x984 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_80_COMMIT_80_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_81_REG_OFFSET 0x988 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_81_COMMIT_81_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_82_REG_OFFSET 0x98c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_82_COMMIT_82_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_83_REG_OFFSET 0x990 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_83_COMMIT_83_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_84_REG_OFFSET 0x994 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_84_COMMIT_84_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_85_REG_OFFSET 0x998 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_85_COMMIT_85_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_86_REG_OFFSET 0x99c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_86_COMMIT_86_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_87_REG_OFFSET 0x9a0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_87_COMMIT_87_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_88_REG_OFFSET 0x9a4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_88_COMMIT_88_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_89_REG_OFFSET 0x9a8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_89_COMMIT_89_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_90_REG_OFFSET 0x9ac +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_90_COMMIT_90_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_91_REG_OFFSET 0x9b0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_91_COMMIT_91_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_92_REG_OFFSET 0x9b4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_92_COMMIT_92_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_93_REG_OFFSET 0x9b8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_93_COMMIT_93_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_94_REG_OFFSET 0x9bc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_94_COMMIT_94_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_95_REG_OFFSET 0x9c0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_95_COMMIT_95_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_96_REG_OFFSET 0x9c4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_96_COMMIT_96_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_97_REG_OFFSET 0x9c8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_97_COMMIT_97_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_98_REG_OFFSET 0x9cc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_98_COMMIT_98_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_99_REG_OFFSET 0x9d0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_99_COMMIT_99_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_100_REG_OFFSET 0x9d4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_100_COMMIT_100_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_101_REG_OFFSET 0x9d8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_101_COMMIT_101_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_102_REG_OFFSET 0x9dc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_102_COMMIT_102_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_103_REG_OFFSET 0x9e0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_103_COMMIT_103_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_104_REG_OFFSET 0x9e4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_104_COMMIT_104_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_105_REG_OFFSET 0x9e8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_105_COMMIT_105_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_106_REG_OFFSET 0x9ec +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_106_COMMIT_106_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_107_REG_OFFSET 0x9f0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_107_COMMIT_107_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_108_REG_OFFSET 0x9f4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_108_COMMIT_108_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_109_REG_OFFSET 0x9f8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_109_COMMIT_109_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_110_REG_OFFSET 0x9fc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_110_COMMIT_110_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_111_REG_OFFSET 0xa00 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_111_COMMIT_111_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_112_REG_OFFSET 0xa04 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_112_COMMIT_112_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_113_REG_OFFSET 0xa08 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_113_COMMIT_113_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_114_REG_OFFSET 0xa0c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_114_COMMIT_114_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_115_REG_OFFSET 0xa10 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_115_COMMIT_115_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_116_REG_OFFSET 0xa14 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_116_COMMIT_116_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_117_REG_OFFSET 0xa18 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_117_COMMIT_117_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_118_REG_OFFSET 0xa1c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_118_COMMIT_118_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_119_REG_OFFSET 0xa20 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_119_COMMIT_119_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_120_REG_OFFSET 0xa24 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_120_COMMIT_120_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_121_REG_OFFSET 0xa28 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_121_COMMIT_121_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_122_REG_OFFSET 0xa2c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_122_COMMIT_122_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_123_REG_OFFSET 0xa30 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_123_COMMIT_123_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_124_REG_OFFSET 0xa34 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_124_COMMIT_124_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_125_REG_OFFSET 0xa38 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_125_COMMIT_125_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_126_REG_OFFSET 0xa3c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_126_COMMIT_126_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_127_REG_OFFSET 0xa40 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_127_COMMIT_127_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_128_REG_OFFSET 0xa44 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_128_COMMIT_128_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_129_REG_OFFSET 0xa48 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_129_COMMIT_129_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_130_REG_OFFSET 0xa4c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_130_COMMIT_130_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_131_REG_OFFSET 0xa50 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_131_COMMIT_131_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_132_REG_OFFSET 0xa54 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_132_COMMIT_132_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_133_REG_OFFSET 0xa58 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_133_COMMIT_133_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_134_REG_OFFSET 0xa5c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_134_COMMIT_134_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_135_REG_OFFSET 0xa60 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_135_COMMIT_135_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_136_REG_OFFSET 0xa64 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_136_COMMIT_136_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_137_REG_OFFSET 0xa68 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_137_COMMIT_137_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_138_REG_OFFSET 0xa6c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_138_COMMIT_138_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_139_REG_OFFSET 0xa70 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_139_COMMIT_139_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_140_REG_OFFSET 0xa74 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_140_COMMIT_140_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_141_REG_OFFSET 0xa78 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_141_COMMIT_141_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_142_REG_OFFSET 0xa7c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_142_COMMIT_142_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_143_REG_OFFSET 0xa80 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_143_COMMIT_143_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_144_REG_OFFSET 0xa84 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_144_COMMIT_144_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_145_REG_OFFSET 0xa88 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_145_COMMIT_145_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_146_REG_OFFSET 0xa8c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_146_COMMIT_146_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_147_REG_OFFSET 0xa90 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_147_COMMIT_147_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_148_REG_OFFSET 0xa94 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_148_COMMIT_148_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_149_REG_OFFSET 0xa98 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_149_COMMIT_149_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_150_REG_OFFSET 0xa9c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_150_COMMIT_150_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_151_REG_OFFSET 0xaa0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_151_COMMIT_151_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_152_REG_OFFSET 0xaa4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_152_COMMIT_152_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_153_REG_OFFSET 0xaa8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_153_COMMIT_153_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_154_REG_OFFSET 0xaac +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_154_COMMIT_154_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_155_REG_OFFSET 0xab0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_155_COMMIT_155_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_156_REG_OFFSET 0xab4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_156_COMMIT_156_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_157_REG_OFFSET 0xab8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_157_COMMIT_157_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_158_REG_OFFSET 0xabc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_158_COMMIT_158_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_159_REG_OFFSET 0xac0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_159_COMMIT_159_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_160_REG_OFFSET 0xac4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_160_COMMIT_160_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_161_REG_OFFSET 0xac8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_161_COMMIT_161_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_162_REG_OFFSET 0xacc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_162_COMMIT_162_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_163_REG_OFFSET 0xad0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_163_COMMIT_163_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_164_REG_OFFSET 0xad4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_164_COMMIT_164_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_165_REG_OFFSET 0xad8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_165_COMMIT_165_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_166_REG_OFFSET 0xadc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_166_COMMIT_166_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_167_REG_OFFSET 0xae0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_167_COMMIT_167_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_168_REG_OFFSET 0xae4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_168_COMMIT_168_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_169_REG_OFFSET 0xae8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_169_COMMIT_169_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_170_REG_OFFSET 0xaec +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_170_COMMIT_170_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_171_REG_OFFSET 0xaf0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_171_COMMIT_171_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_172_REG_OFFSET 0xaf4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_172_COMMIT_172_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_173_REG_OFFSET 0xaf8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_173_COMMIT_173_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_174_REG_OFFSET 0xafc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_174_COMMIT_174_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_175_REG_OFFSET 0xb00 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_175_COMMIT_175_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_176_REG_OFFSET 0xb04 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_176_COMMIT_176_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_177_REG_OFFSET 0xb08 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_177_COMMIT_177_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_178_REG_OFFSET 0xb0c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_178_COMMIT_178_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_179_REG_OFFSET 0xb10 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_179_COMMIT_179_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_180_REG_OFFSET 0xb14 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_180_COMMIT_180_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_181_REG_OFFSET 0xb18 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_181_COMMIT_181_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_182_REG_OFFSET 0xb1c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_182_COMMIT_182_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_183_REG_OFFSET 0xb20 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_183_COMMIT_183_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_184_REG_OFFSET 0xb24 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_184_COMMIT_184_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_185_REG_OFFSET 0xb28 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_185_COMMIT_185_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_186_REG_OFFSET 0xb2c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_186_COMMIT_186_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_187_REG_OFFSET 0xb30 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_187_COMMIT_187_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_188_REG_OFFSET 0xb34 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_188_COMMIT_188_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_189_REG_OFFSET 0xb38 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_189_COMMIT_189_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_190_REG_OFFSET 0xb3c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_190_COMMIT_190_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_191_REG_OFFSET 0xb40 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_191_COMMIT_191_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_192_REG_OFFSET 0xb44 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_192_COMMIT_192_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_193_REG_OFFSET 0xb48 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_193_COMMIT_193_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_194_REG_OFFSET 0xb4c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_194_COMMIT_194_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_195_REG_OFFSET 0xb50 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_195_COMMIT_195_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_196_REG_OFFSET 0xb54 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_196_COMMIT_196_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_197_REG_OFFSET 0xb58 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_197_COMMIT_197_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_198_REG_OFFSET 0xb5c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_198_COMMIT_198_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_199_REG_OFFSET 0xb60 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_199_COMMIT_199_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_200_REG_OFFSET 0xb64 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_200_COMMIT_200_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_201_REG_OFFSET 0xb68 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_201_COMMIT_201_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_202_REG_OFFSET 0xb6c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_202_COMMIT_202_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_203_REG_OFFSET 0xb70 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_203_COMMIT_203_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_204_REG_OFFSET 0xb74 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_204_COMMIT_204_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_205_REG_OFFSET 0xb78 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_205_COMMIT_205_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_206_REG_OFFSET 0xb7c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_206_COMMIT_206_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_207_REG_OFFSET 0xb80 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_207_COMMIT_207_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_208_REG_OFFSET 0xb84 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_208_COMMIT_208_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_209_REG_OFFSET 0xb88 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_209_COMMIT_209_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_210_REG_OFFSET 0xb8c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_210_COMMIT_210_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_211_REG_OFFSET 0xb90 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_211_COMMIT_211_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_212_REG_OFFSET 0xb94 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_212_COMMIT_212_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_213_REG_OFFSET 0xb98 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_213_COMMIT_213_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_214_REG_OFFSET 0xb9c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_214_COMMIT_214_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_215_REG_OFFSET 0xba0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_215_COMMIT_215_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_216_REG_OFFSET 0xba4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_216_COMMIT_216_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_217_REG_OFFSET 0xba8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_217_COMMIT_217_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_218_REG_OFFSET 0xbac +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_218_COMMIT_218_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_219_REG_OFFSET 0xbb0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_219_COMMIT_219_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_220_REG_OFFSET 0xbb4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_220_COMMIT_220_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_221_REG_OFFSET 0xbb8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_221_COMMIT_221_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_222_REG_OFFSET 0xbbc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_222_COMMIT_222_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_223_REG_OFFSET 0xbc0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_223_COMMIT_223_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_224_REG_OFFSET 0xbc4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_224_COMMIT_224_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_225_REG_OFFSET 0xbc8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_225_COMMIT_225_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_226_REG_OFFSET 0xbcc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_226_COMMIT_226_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_227_REG_OFFSET 0xbd0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_227_COMMIT_227_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_228_REG_OFFSET 0xbd4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_228_COMMIT_228_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_229_REG_OFFSET 0xbd8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_229_COMMIT_229_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_230_REG_OFFSET 0xbdc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_230_COMMIT_230_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_231_REG_OFFSET 0xbe0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_231_COMMIT_231_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_232_REG_OFFSET 0xbe4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_232_COMMIT_232_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_233_REG_OFFSET 0xbe8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_233_COMMIT_233_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_234_REG_OFFSET 0xbec +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_234_COMMIT_234_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_235_REG_OFFSET 0xbf0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_235_COMMIT_235_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_236_REG_OFFSET 0xbf4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_236_COMMIT_236_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_237_REG_OFFSET 0xbf8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_237_COMMIT_237_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_238_REG_OFFSET 0xbfc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_238_COMMIT_238_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_239_REG_OFFSET 0xc00 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_239_COMMIT_239_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_240_REG_OFFSET 0xc04 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_240_COMMIT_240_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_241_REG_OFFSET 0xc08 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_241_COMMIT_241_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_242_REG_OFFSET 0xc0c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_242_COMMIT_242_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_243_REG_OFFSET 0xc10 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_243_COMMIT_243_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_244_REG_OFFSET 0xc14 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_244_COMMIT_244_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_245_REG_OFFSET 0xc18 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_245_COMMIT_245_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_246_REG_OFFSET 0xc1c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_246_COMMIT_246_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_247_REG_OFFSET 0xc20 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_247_COMMIT_247_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_248_REG_OFFSET 0xc24 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_248_COMMIT_248_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_249_REG_OFFSET 0xc28 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_249_COMMIT_249_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_250_REG_OFFSET 0xc2c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_250_COMMIT_250_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_251_REG_OFFSET 0xc30 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_251_COMMIT_251_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_252_REG_OFFSET 0xc34 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_252_COMMIT_252_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_253_REG_OFFSET 0xc38 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_253_COMMIT_253_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_254_REG_OFFSET 0xc3c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_254_COMMIT_254_BIT 0 + +// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_255_REG_OFFSET 0xc40 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_255_COMMIT_255_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_STATUS_FIELD_WIDTH 1 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_STATUS_FIELDS_PER_REG 32 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_MULTIREG_COUNT 256 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_REG_OFFSET 0xc44 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_STATUS_0_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_REG_OFFSET 0xc48 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_STATUS_1_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_REG_OFFSET 0xc4c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_STATUS_2_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_REG_OFFSET 0xc50 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_STATUS_3_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_REG_OFFSET 0xc54 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_STATUS_4_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_REG_OFFSET 0xc58 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_STATUS_5_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_REG_OFFSET 0xc5c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_STATUS_6_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_REG_OFFSET 0xc60 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_STATUS_7_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_REG_OFFSET 0xc64 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_STATUS_8_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_REG_OFFSET 0xc68 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_STATUS_9_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_REG_OFFSET 0xc6c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_STATUS_10_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_REG_OFFSET 0xc70 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_STATUS_11_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_REG_OFFSET 0xc74 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_STATUS_12_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_REG_OFFSET 0xc78 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_STATUS_13_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_REG_OFFSET 0xc7c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_STATUS_14_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_REG_OFFSET 0xc80 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_STATUS_15_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_REG_OFFSET 0xc84 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_STATUS_16_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_REG_OFFSET 0xc88 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_STATUS_17_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_REG_OFFSET 0xc8c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_STATUS_18_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_REG_OFFSET 0xc90 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_STATUS_19_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_REG_OFFSET 0xc94 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_STATUS_20_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_REG_OFFSET 0xc98 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_STATUS_21_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0_REG_OFFSET 0x144 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_REG_OFFSET 0xc9c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_STATUS_22_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_1_REG_OFFSET 0x148 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_REG_OFFSET 0xca0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_STATUS_23_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_2_REG_OFFSET 0x14c +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_REG_OFFSET 0xca4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_STATUS_24_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_3_REG_OFFSET 0x150 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_REG_OFFSET 0xca8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_STATUS_25_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_4_REG_OFFSET 0x154 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_REG_OFFSET 0xcac +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_STATUS_26_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_5_REG_OFFSET 0x158 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_REG_OFFSET 0xcb0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_STATUS_27_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_6_REG_OFFSET 0x15c +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_REG_OFFSET 0xcb4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_STATUS_28_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_7_REG_OFFSET 0x160 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_REG_OFFSET 0xcb8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_STATUS_29_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_8_REG_OFFSET 0x164 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_REG_OFFSET 0xcbc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_STATUS_30_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_9_REG_OFFSET 0x168 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_REG_OFFSET 0xcc0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_STATUS_31_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_10_REG_OFFSET 0x16c +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_REG_OFFSET 0xcc4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_STATUS_32_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_11_REG_OFFSET 0x170 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_REG_OFFSET 0xcc8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_STATUS_33_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_12_REG_OFFSET 0x174 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_REG_OFFSET 0xccc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_STATUS_34_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_13_REG_OFFSET 0x178 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_REG_OFFSET 0xcd0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_STATUS_35_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_14_REG_OFFSET 0x17c +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_REG_OFFSET 0xcd4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_STATUS_36_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_15_REG_OFFSET 0x180 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_REG_OFFSET 0xcd8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_STATUS_37_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_16_REG_OFFSET 0x184 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_REG_OFFSET 0xcdc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_STATUS_38_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_17_REG_OFFSET 0x188 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_REG_OFFSET 0xce0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_STATUS_39_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_18_REG_OFFSET 0x18c +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_REG_OFFSET 0xce4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_STATUS_40_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_19_REG_OFFSET 0x190 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_REG_OFFSET 0xce8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_STATUS_41_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_20_REG_OFFSET 0x194 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_REG_OFFSET 0xcec +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_STATUS_42_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_21_REG_OFFSET 0x198 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_REG_OFFSET 0xcf0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_STATUS_43_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_22_REG_OFFSET 0x19c +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_REG_OFFSET 0xcf4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_STATUS_44_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_23_REG_OFFSET 0x1a0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_REG_OFFSET 0xcf8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_STATUS_45_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_24_REG_OFFSET 0x1a4 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_REG_OFFSET 0xcfc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_STATUS_46_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_25_REG_OFFSET 0x1a8 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_REG_OFFSET 0xd00 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_STATUS_47_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_26_REG_OFFSET 0x1ac +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_REG_OFFSET 0xd04 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_STATUS_48_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_27_REG_OFFSET 0x1b0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_REG_OFFSET 0xd08 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_STATUS_49_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_28_REG_OFFSET 0x1b4 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_REG_OFFSET 0xd0c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_STATUS_50_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_29_REG_OFFSET 0x1b8 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_REG_OFFSET 0xd10 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_STATUS_51_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_30_REG_OFFSET 0x1bc +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_REG_OFFSET 0xd14 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_STATUS_52_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_31_REG_OFFSET 0x1c0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_REG_OFFSET 0xd18 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_STATUS_53_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_32_REG_OFFSET 0x1c4 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_REG_OFFSET 0xd1c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_STATUS_54_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_33_REG_OFFSET 0x1c8 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_REG_OFFSET 0xd20 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_STATUS_55_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_34_REG_OFFSET 0x1cc +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_REG_OFFSET 0xd24 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_STATUS_56_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_35_REG_OFFSET 0x1d0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_REG_OFFSET 0xd28 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_STATUS_57_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_36_REG_OFFSET 0x1d4 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_REG_OFFSET 0xd2c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_STATUS_58_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_37_REG_OFFSET 0x1d8 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_REG_OFFSET 0xd30 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_STATUS_59_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_38_REG_OFFSET 0x1dc +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_REG_OFFSET 0xd34 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_STATUS_60_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_39_REG_OFFSET 0x1e0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_REG_OFFSET 0xd38 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_STATUS_61_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_40_REG_OFFSET 0x1e4 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_REG_OFFSET 0xd3c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_STATUS_62_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_41_REG_OFFSET 0x1e8 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_REG_OFFSET 0xd40 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_STATUS_63_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_42_REG_OFFSET 0x1ec +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_64_REG_OFFSET 0xd44 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_64_STATUS_64_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_43_REG_OFFSET 0x1f0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_65_REG_OFFSET 0xd48 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_65_STATUS_65_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_44_REG_OFFSET 0x1f4 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_66_REG_OFFSET 0xd4c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_66_STATUS_66_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_45_REG_OFFSET 0x1f8 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_67_REG_OFFSET 0xd50 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_67_STATUS_67_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_46_REG_OFFSET 0x1fc +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_68_REG_OFFSET 0xd54 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_68_STATUS_68_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_47_REG_OFFSET 0x200 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_69_REG_OFFSET 0xd58 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_69_STATUS_69_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_48_REG_OFFSET 0x204 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_70_REG_OFFSET 0xd5c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_70_STATUS_70_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_49_REG_OFFSET 0x208 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_71_REG_OFFSET 0xd60 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_71_STATUS_71_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_50_REG_OFFSET 0x20c +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_72_REG_OFFSET 0xd64 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_72_STATUS_72_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_51_REG_OFFSET 0x210 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_73_REG_OFFSET 0xd68 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_73_STATUS_73_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_52_REG_OFFSET 0x214 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_74_REG_OFFSET 0xd6c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_74_STATUS_74_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_53_REG_OFFSET 0x218 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_75_REG_OFFSET 0xd70 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_75_STATUS_75_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_54_REG_OFFSET 0x21c +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_76_REG_OFFSET 0xd74 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_76_STATUS_76_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_55_REG_OFFSET 0x220 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_77_REG_OFFSET 0xd78 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_77_STATUS_77_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_56_REG_OFFSET 0x224 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_78_REG_OFFSET 0xd7c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_78_STATUS_78_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_57_REG_OFFSET 0x228 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_79_REG_OFFSET 0xd80 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_79_STATUS_79_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_58_REG_OFFSET 0x22c +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_80_REG_OFFSET 0xd84 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_80_STATUS_80_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_59_REG_OFFSET 0x230 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_81_REG_OFFSET 0xd88 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_81_STATUS_81_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_60_REG_OFFSET 0x234 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_82_REG_OFFSET 0xd8c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_82_STATUS_82_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_61_REG_OFFSET 0x238 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_83_REG_OFFSET 0xd90 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_83_STATUS_83_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_62_REG_OFFSET 0x23c +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_84_REG_OFFSET 0xd94 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_84_STATUS_84_BIT 0 -// Per-core cacheline address for LP1 INVAL_NLINE. Ignored for -#define CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_63_REG_OFFSET 0x240 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_85_REG_OFFSET 0xd98 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_85_STATUS_85_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_COMMIT_FIELD_WIDTH 1 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_COMMIT_FIELDS_PER_REG 32 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_MULTIREG_COUNT 64 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_86_REG_OFFSET 0xd9c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_86_STATUS_86_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_REG_OFFSET 0x244 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_COMMIT_0_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_87_REG_OFFSET 0xda0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_87_STATUS_87_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_88_REG_OFFSET 0xda4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_88_STATUS_88_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_89_REG_OFFSET 0xda8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_89_STATUS_89_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_90_REG_OFFSET 0xdac +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_90_STATUS_90_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_91_REG_OFFSET 0xdb0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_91_STATUS_91_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_92_REG_OFFSET 0xdb4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_92_STATUS_92_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_93_REG_OFFSET 0xdb8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_93_STATUS_93_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_94_REG_OFFSET 0xdbc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_94_STATUS_94_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_95_REG_OFFSET 0xdc0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_95_STATUS_95_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_96_REG_OFFSET 0xdc4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_96_STATUS_96_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_97_REG_OFFSET 0xdc8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_97_STATUS_97_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_98_REG_OFFSET 0xdcc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_98_STATUS_98_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_99_REG_OFFSET 0xdd0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_99_STATUS_99_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_100_REG_OFFSET 0xdd4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_100_STATUS_100_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_101_REG_OFFSET 0xdd8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_101_STATUS_101_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_102_REG_OFFSET 0xddc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_102_STATUS_102_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_103_REG_OFFSET 0xde0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_103_STATUS_103_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_104_REG_OFFSET 0xde4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_104_STATUS_104_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_105_REG_OFFSET 0xde8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_105_STATUS_105_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_106_REG_OFFSET 0xdec +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_106_STATUS_106_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_107_REG_OFFSET 0xdf0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_107_STATUS_107_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_108_REG_OFFSET 0xdf4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_108_STATUS_108_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_109_REG_OFFSET 0xdf8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_109_STATUS_109_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_110_REG_OFFSET 0xdfc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_110_STATUS_110_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_111_REG_OFFSET 0xe00 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_111_STATUS_111_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_112_REG_OFFSET 0xe04 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_112_STATUS_112_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_113_REG_OFFSET 0xe08 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_113_STATUS_113_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_114_REG_OFFSET 0xe0c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_114_STATUS_114_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_115_REG_OFFSET 0xe10 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_115_STATUS_115_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_116_REG_OFFSET 0xe14 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_116_STATUS_116_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_117_REG_OFFSET 0xe18 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_117_STATUS_117_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_118_REG_OFFSET 0xe1c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_118_STATUS_118_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_119_REG_OFFSET 0xe20 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_119_STATUS_119_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_120_REG_OFFSET 0xe24 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_120_STATUS_120_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_121_REG_OFFSET 0xe28 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_121_STATUS_121_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_122_REG_OFFSET 0xe2c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_122_STATUS_122_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_123_REG_OFFSET 0xe30 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_123_STATUS_123_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_124_REG_OFFSET 0xe34 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_124_STATUS_124_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_125_REG_OFFSET 0xe38 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_125_STATUS_125_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_126_REG_OFFSET 0xe3c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_126_STATUS_126_BIT 0 + +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_127_REG_OFFSET 0xe40 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_127_STATUS_127_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_REG_OFFSET 0x248 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_1_COMMIT_1_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_128_REG_OFFSET 0xe44 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_128_STATUS_128_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_REG_OFFSET 0x24c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_2_COMMIT_2_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_129_REG_OFFSET 0xe48 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_129_STATUS_129_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_REG_OFFSET 0x250 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_3_COMMIT_3_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_130_REG_OFFSET 0xe4c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_130_STATUS_130_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_REG_OFFSET 0x254 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_4_COMMIT_4_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_131_REG_OFFSET 0xe50 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_131_STATUS_131_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_REG_OFFSET 0x258 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_5_COMMIT_5_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_132_REG_OFFSET 0xe54 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_132_STATUS_132_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_REG_OFFSET 0x25c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_6_COMMIT_6_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_133_REG_OFFSET 0xe58 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_133_STATUS_133_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_REG_OFFSET 0x260 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_7_COMMIT_7_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_134_REG_OFFSET 0xe5c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_134_STATUS_134_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_REG_OFFSET 0x264 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_8_COMMIT_8_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_135_REG_OFFSET 0xe60 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_135_STATUS_135_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_REG_OFFSET 0x268 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_9_COMMIT_9_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_136_REG_OFFSET 0xe64 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_136_STATUS_136_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_REG_OFFSET 0x26c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_10_COMMIT_10_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_137_REG_OFFSET 0xe68 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_137_STATUS_137_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_REG_OFFSET 0x270 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_11_COMMIT_11_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_138_REG_OFFSET 0xe6c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_138_STATUS_138_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_REG_OFFSET 0x274 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_12_COMMIT_12_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_139_REG_OFFSET 0xe70 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_139_STATUS_139_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_REG_OFFSET 0x278 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_13_COMMIT_13_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_140_REG_OFFSET 0xe74 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_140_STATUS_140_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_REG_OFFSET 0x27c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_14_COMMIT_14_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_141_REG_OFFSET 0xe78 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_141_STATUS_141_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_REG_OFFSET 0x280 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_15_COMMIT_15_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_142_REG_OFFSET 0xe7c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_142_STATUS_142_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_REG_OFFSET 0x284 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_16_COMMIT_16_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_143_REG_OFFSET 0xe80 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_143_STATUS_143_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_REG_OFFSET 0x288 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_17_COMMIT_17_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_144_REG_OFFSET 0xe84 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_144_STATUS_144_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_REG_OFFSET 0x28c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_18_COMMIT_18_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_145_REG_OFFSET 0xe88 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_145_STATUS_145_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_REG_OFFSET 0x290 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_19_COMMIT_19_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_146_REG_OFFSET 0xe8c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_146_STATUS_146_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_REG_OFFSET 0x294 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_20_COMMIT_20_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_147_REG_OFFSET 0xe90 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_147_STATUS_147_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_REG_OFFSET 0x298 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_21_COMMIT_21_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_148_REG_OFFSET 0xe94 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_148_STATUS_148_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_REG_OFFSET 0x29c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_22_COMMIT_22_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_149_REG_OFFSET 0xe98 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_149_STATUS_149_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_REG_OFFSET 0x2a0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_23_COMMIT_23_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_150_REG_OFFSET 0xe9c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_150_STATUS_150_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_REG_OFFSET 0x2a4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_24_COMMIT_24_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_151_REG_OFFSET 0xea0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_151_STATUS_151_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_REG_OFFSET 0x2a8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_25_COMMIT_25_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_152_REG_OFFSET 0xea4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_152_STATUS_152_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_REG_OFFSET 0x2ac -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_26_COMMIT_26_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_153_REG_OFFSET 0xea8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_153_STATUS_153_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_REG_OFFSET 0x2b0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_27_COMMIT_27_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_154_REG_OFFSET 0xeac +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_154_STATUS_154_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_REG_OFFSET 0x2b4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_28_COMMIT_28_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_155_REG_OFFSET 0xeb0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_155_STATUS_155_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_REG_OFFSET 0x2b8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_29_COMMIT_29_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_156_REG_OFFSET 0xeb4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_156_STATUS_156_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_REG_OFFSET 0x2bc -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_30_COMMIT_30_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_157_REG_OFFSET 0xeb8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_157_STATUS_157_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_REG_OFFSET 0x2c0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_31_COMMIT_31_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_158_REG_OFFSET 0xebc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_158_STATUS_158_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_REG_OFFSET 0x2c4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_32_COMMIT_32_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_159_REG_OFFSET 0xec0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_159_STATUS_159_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_REG_OFFSET 0x2c8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_33_COMMIT_33_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_160_REG_OFFSET 0xec4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_160_STATUS_160_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_REG_OFFSET 0x2cc -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_34_COMMIT_34_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_161_REG_OFFSET 0xec8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_161_STATUS_161_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_REG_OFFSET 0x2d0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_35_COMMIT_35_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_162_REG_OFFSET 0xecc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_162_STATUS_162_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_REG_OFFSET 0x2d4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_36_COMMIT_36_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_163_REG_OFFSET 0xed0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_163_STATUS_163_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_REG_OFFSET 0x2d8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_37_COMMIT_37_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_164_REG_OFFSET 0xed4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_164_STATUS_164_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_REG_OFFSET 0x2dc -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_38_COMMIT_38_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_165_REG_OFFSET 0xed8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_165_STATUS_165_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_REG_OFFSET 0x2e0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_39_COMMIT_39_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_166_REG_OFFSET 0xedc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_166_STATUS_166_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_REG_OFFSET 0x2e4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_40_COMMIT_40_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_167_REG_OFFSET 0xee0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_167_STATUS_167_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_REG_OFFSET 0x2e8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_41_COMMIT_41_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_168_REG_OFFSET 0xee4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_168_STATUS_168_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_REG_OFFSET 0x2ec -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_42_COMMIT_42_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_169_REG_OFFSET 0xee8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_169_STATUS_169_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_REG_OFFSET 0x2f0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_43_COMMIT_43_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_170_REG_OFFSET 0xeec +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_170_STATUS_170_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_REG_OFFSET 0x2f4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_44_COMMIT_44_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_171_REG_OFFSET 0xef0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_171_STATUS_171_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_REG_OFFSET 0x2f8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_45_COMMIT_45_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_172_REG_OFFSET 0xef4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_172_STATUS_172_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_REG_OFFSET 0x2fc -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_46_COMMIT_46_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_173_REG_OFFSET 0xef8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_173_STATUS_173_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_REG_OFFSET 0x300 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_47_COMMIT_47_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_174_REG_OFFSET 0xefc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_174_STATUS_174_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_REG_OFFSET 0x304 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_48_COMMIT_48_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_175_REG_OFFSET 0xf00 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_175_STATUS_175_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_REG_OFFSET 0x308 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_49_COMMIT_49_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_176_REG_OFFSET 0xf04 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_176_STATUS_176_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_REG_OFFSET 0x30c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_50_COMMIT_50_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_177_REG_OFFSET 0xf08 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_177_STATUS_177_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_REG_OFFSET 0x310 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_51_COMMIT_51_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_178_REG_OFFSET 0xf0c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_178_STATUS_178_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_REG_OFFSET 0x314 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_52_COMMIT_52_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_179_REG_OFFSET 0xf10 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_179_STATUS_179_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_REG_OFFSET 0x318 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_53_COMMIT_53_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_180_REG_OFFSET 0xf14 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_180_STATUS_180_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_REG_OFFSET 0x31c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_54_COMMIT_54_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_181_REG_OFFSET 0xf18 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_181_STATUS_181_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_REG_OFFSET 0x320 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_55_COMMIT_55_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_182_REG_OFFSET 0xf1c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_182_STATUS_182_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_REG_OFFSET 0x324 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_56_COMMIT_56_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_183_REG_OFFSET 0xf20 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_183_STATUS_183_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_REG_OFFSET 0x328 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_57_COMMIT_57_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_184_REG_OFFSET 0xf24 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_184_STATUS_184_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_REG_OFFSET 0x32c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_58_COMMIT_58_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_185_REG_OFFSET 0xf28 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_185_STATUS_185_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_REG_OFFSET 0x330 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_59_COMMIT_59_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_186_REG_OFFSET 0xf2c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_186_STATUS_186_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_REG_OFFSET 0x334 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_60_COMMIT_60_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_187_REG_OFFSET 0xf30 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_187_STATUS_187_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_REG_OFFSET 0x338 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_61_COMMIT_61_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_188_REG_OFFSET 0xf34 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_188_STATUS_188_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_REG_OFFSET 0x33c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_62_COMMIT_62_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_189_REG_OFFSET 0xf38 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_189_STATUS_189_BIT 0 -// Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_REG_OFFSET 0x340 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_63_COMMIT_63_BIT 0 +// Per-core LP1 CMO status. High while this core's CMO is in flight; +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_190_REG_OFFSET 0xf3c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_190_STATUS_190_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_STATUS_FIELD_WIDTH 1 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_STATUS_FIELDS_PER_REG 32 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_MULTIREG_COUNT 64 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_191_REG_OFFSET 0xf40 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_191_STATUS_191_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_REG_OFFSET 0x344 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_STATUS_0_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_192_REG_OFFSET 0xf44 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_192_STATUS_192_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_REG_OFFSET 0x348 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_1_STATUS_1_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_193_REG_OFFSET 0xf48 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_193_STATUS_193_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_REG_OFFSET 0x34c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_2_STATUS_2_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_194_REG_OFFSET 0xf4c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_194_STATUS_194_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_REG_OFFSET 0x350 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_3_STATUS_3_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_195_REG_OFFSET 0xf50 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_195_STATUS_195_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_REG_OFFSET 0x354 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_4_STATUS_4_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_196_REG_OFFSET 0xf54 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_196_STATUS_196_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_REG_OFFSET 0x358 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_5_STATUS_5_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_197_REG_OFFSET 0xf58 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_197_STATUS_197_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_REG_OFFSET 0x35c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_6_STATUS_6_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_198_REG_OFFSET 0xf5c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_198_STATUS_198_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_REG_OFFSET 0x360 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_7_STATUS_7_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_199_REG_OFFSET 0xf60 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_199_STATUS_199_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_REG_OFFSET 0x364 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_8_STATUS_8_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_200_REG_OFFSET 0xf64 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_200_STATUS_200_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_REG_OFFSET 0x368 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_9_STATUS_9_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_201_REG_OFFSET 0xf68 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_201_STATUS_201_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_REG_OFFSET 0x36c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_10_STATUS_10_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_202_REG_OFFSET 0xf6c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_202_STATUS_202_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_REG_OFFSET 0x370 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_11_STATUS_11_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_203_REG_OFFSET 0xf70 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_203_STATUS_203_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_REG_OFFSET 0x374 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_12_STATUS_12_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_204_REG_OFFSET 0xf74 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_204_STATUS_204_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_REG_OFFSET 0x378 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_13_STATUS_13_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_205_REG_OFFSET 0xf78 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_205_STATUS_205_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_REG_OFFSET 0x37c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_14_STATUS_14_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_206_REG_OFFSET 0xf7c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_206_STATUS_206_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_REG_OFFSET 0x380 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_15_STATUS_15_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_207_REG_OFFSET 0xf80 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_207_STATUS_207_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_REG_OFFSET 0x384 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_16_STATUS_16_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_208_REG_OFFSET 0xf84 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_208_STATUS_208_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_REG_OFFSET 0x388 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_17_STATUS_17_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_209_REG_OFFSET 0xf88 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_209_STATUS_209_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_REG_OFFSET 0x38c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_18_STATUS_18_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_210_REG_OFFSET 0xf8c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_210_STATUS_210_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_REG_OFFSET 0x390 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_19_STATUS_19_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_211_REG_OFFSET 0xf90 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_211_STATUS_211_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_REG_OFFSET 0x394 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_20_STATUS_20_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_212_REG_OFFSET 0xf94 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_212_STATUS_212_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_REG_OFFSET 0x398 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_21_STATUS_21_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_213_REG_OFFSET 0xf98 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_213_STATUS_213_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_REG_OFFSET 0x39c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_22_STATUS_22_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_214_REG_OFFSET 0xf9c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_214_STATUS_214_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_REG_OFFSET 0x3a0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_23_STATUS_23_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_215_REG_OFFSET 0xfa0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_215_STATUS_215_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_REG_OFFSET 0x3a4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_24_STATUS_24_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_216_REG_OFFSET 0xfa4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_216_STATUS_216_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_REG_OFFSET 0x3a8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_25_STATUS_25_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_217_REG_OFFSET 0xfa8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_217_STATUS_217_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_REG_OFFSET 0x3ac -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_26_STATUS_26_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_218_REG_OFFSET 0xfac +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_218_STATUS_218_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_REG_OFFSET 0x3b0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_27_STATUS_27_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_219_REG_OFFSET 0xfb0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_219_STATUS_219_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_REG_OFFSET 0x3b4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_28_STATUS_28_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_220_REG_OFFSET 0xfb4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_220_STATUS_220_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_REG_OFFSET 0x3b8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_29_STATUS_29_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_221_REG_OFFSET 0xfb8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_221_STATUS_221_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_REG_OFFSET 0x3bc -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_30_STATUS_30_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_222_REG_OFFSET 0xfbc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_222_STATUS_222_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_REG_OFFSET 0x3c0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_31_STATUS_31_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_223_REG_OFFSET 0xfc0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_223_STATUS_223_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_REG_OFFSET 0x3c4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_32_STATUS_32_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_224_REG_OFFSET 0xfc4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_224_STATUS_224_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_REG_OFFSET 0x3c8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_33_STATUS_33_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_225_REG_OFFSET 0xfc8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_225_STATUS_225_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_REG_OFFSET 0x3cc -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_34_STATUS_34_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_226_REG_OFFSET 0xfcc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_226_STATUS_226_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_REG_OFFSET 0x3d0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_35_STATUS_35_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_227_REG_OFFSET 0xfd0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_227_STATUS_227_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_REG_OFFSET 0x3d4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_36_STATUS_36_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_228_REG_OFFSET 0xfd4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_228_STATUS_228_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_REG_OFFSET 0x3d8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_37_STATUS_37_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_229_REG_OFFSET 0xfd8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_229_STATUS_229_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_REG_OFFSET 0x3dc -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_38_STATUS_38_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_230_REG_OFFSET 0xfdc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_230_STATUS_230_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_REG_OFFSET 0x3e0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_39_STATUS_39_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_231_REG_OFFSET 0xfe0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_231_STATUS_231_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_REG_OFFSET 0x3e4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_40_STATUS_40_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_232_REG_OFFSET 0xfe4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_232_STATUS_232_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_REG_OFFSET 0x3e8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_41_STATUS_41_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_233_REG_OFFSET 0xfe8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_233_STATUS_233_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_REG_OFFSET 0x3ec -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_42_STATUS_42_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_234_REG_OFFSET 0xfec +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_234_STATUS_234_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_REG_OFFSET 0x3f0 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_43_STATUS_43_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_235_REG_OFFSET 0xff0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_235_STATUS_235_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_REG_OFFSET 0x3f4 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_44_STATUS_44_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_236_REG_OFFSET 0xff4 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_236_STATUS_236_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_REG_OFFSET 0x3f8 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_45_STATUS_45_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_237_REG_OFFSET 0xff8 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_237_STATUS_237_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_REG_OFFSET 0x3fc -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_46_STATUS_46_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_238_REG_OFFSET 0xffc +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_238_STATUS_238_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_REG_OFFSET 0x400 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_47_STATUS_47_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_239_REG_OFFSET 0x1000 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_239_STATUS_239_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_REG_OFFSET 0x404 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_48_STATUS_48_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_240_REG_OFFSET 0x1004 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_240_STATUS_240_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_REG_OFFSET 0x408 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_49_STATUS_49_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_241_REG_OFFSET 0x1008 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_241_STATUS_241_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_REG_OFFSET 0x40c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_50_STATUS_50_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_242_REG_OFFSET 0x100c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_242_STATUS_242_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_REG_OFFSET 0x410 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_51_STATUS_51_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_243_REG_OFFSET 0x1010 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_243_STATUS_243_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_REG_OFFSET 0x414 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_52_STATUS_52_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_244_REG_OFFSET 0x1014 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_244_STATUS_244_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_REG_OFFSET 0x418 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_53_STATUS_53_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_245_REG_OFFSET 0x1018 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_245_STATUS_245_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_REG_OFFSET 0x41c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_54_STATUS_54_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_246_REG_OFFSET 0x101c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_246_STATUS_246_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_REG_OFFSET 0x420 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_55_STATUS_55_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_247_REG_OFFSET 0x1020 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_247_STATUS_247_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_REG_OFFSET 0x424 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_56_STATUS_56_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_248_REG_OFFSET 0x1024 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_248_STATUS_248_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_REG_OFFSET 0x428 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_57_STATUS_57_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_249_REG_OFFSET 0x1028 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_249_STATUS_249_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_REG_OFFSET 0x42c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_58_STATUS_58_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_250_REG_OFFSET 0x102c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_250_STATUS_250_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_REG_OFFSET 0x430 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_59_STATUS_59_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_251_REG_OFFSET 0x1030 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_251_STATUS_251_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_REG_OFFSET 0x434 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_60_STATUS_60_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_252_REG_OFFSET 0x1034 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_252_STATUS_252_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_REG_OFFSET 0x438 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_61_STATUS_61_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_253_REG_OFFSET 0x1038 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_253_STATUS_253_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_REG_OFFSET 0x43c -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_62_STATUS_62_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_254_REG_OFFSET 0x103c +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_254_STATUS_254_BIT 0 // Per-core LP1 CMO status. High while this core's CMO is in flight; -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_REG_OFFSET 0x440 -#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_63_STATUS_63_BIT 0 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_255_REG_OFFSET 0x1040 +#define CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_255_STATUS_255_BIT 0 #ifdef __cplusplus } // extern "C" diff --git a/software/tests/CMakeLists.txt b/software/tests/CMakeLists.txt index e6f4dc4..404c9ef 100644 --- a/software/tests/CMakeLists.txt +++ b/software/tests/CMakeLists.txt @@ -70,7 +70,6 @@ include_directories(${SNRUNTIME_INCLUDE_DIRS}) # Kernels ## Vector Kernels add_library(fdotp-32b fdotp-32b/kernel/fdotp.c) -add_library(fdotp-32b-single fdotp-32b-single/kernel/fdotp.c) add_library(idotp-32b idotp-32b/kernel/idotp.c) add_library(fmatmul-32b fmatmul-32b/kernel/fmatmul.c) @@ -105,9 +104,6 @@ add_spatz_test_oneParam(fdotp-32b fdotp-32b/main.c 8192) add_spatz_test_oneParam(fdotp-32b fdotp-32b/main.c 32768) add_spatz_test_oneParam(fdotp-32b fdotp-32b/main.c 65536) -add_spatz_test_oneParam(fdotp-32b-single fdotp-32b-single/main.c 1024) -add_spatz_test_oneParam(fdotp-32b-single fdotp-32b-single/main.c 8192) - add_spatz_test_threeParam(gemv gemv/main.c 128 128 32) add_spatz_test_threeParam(gemv gemv/main.c 256 128 32) add_spatz_test_threeParam(gemv gemv/main.c 512 128 32) diff --git a/software/tests/fdotp-32b-single/data/.gitignore b/software/tests/fdotp-32b-single/data/.gitignore deleted file mode 100644 index 3005476..0000000 --- a/software/tests/fdotp-32b-single/data/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -# Generated data headers — reproduced by `make gen-data` -*.h -!layer.h diff --git a/software/tests/fdotp-32b-single/data/layer.h b/software/tests/fdotp-32b-single/data/layer.h deleted file mode 100644 index 4a68cf6..0000000 --- a/software/tests/fdotp-32b-single/data/layer.h +++ /dev/null @@ -1,150 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#pragma once - -#include - -typedef enum { FP64 = 8, FP32 = 4, FP16 = 2, FP8 = 1 } precision_t; - -/** - * @struct gemm_layer_struct - * @brief This structure contains all parameters necessary for GEMM. - * @var gemm_layer_struct::M - * Dimension of matrix product MxK * KxN - * @var gemm_layer_struct::M_p - * M divided by number of compute cores - * @var gemm_layer_struct::N - * Dimension of matrix product MxK * KxN - * @var gemm_layer_struct::K - * Dimension of matrix product MxK * KxN - * @var gemm_layer_struct::TA - * Transpose matrix A - * @var gemm_layer_struct::TB - * Transpose matrix B - * @var gemm_layer_struct::TILE_M - * Tile factor across M dimension - * @var gemm_layer_struct::TILE_N - * Tile factor across N dimension - * @var gemm_layer_struct::TILE_K - * Tile factor across K dimension - * @var gemm_layer_struct::A - * Pointer to matrix A - * @var gemm_layer_struct::B - * Pointer to matrix B - * @var gemm_layer_struct::C - * Pointer to matrix C - * @var gemm_layer_struct::ALPHA - * constant factor: A * B + ALPHA * C - * @var gemm_layer_struct::dtype - * Precision of GEMM - * @var gemm_layer_struct::expand - * Use expanding DOTP instructions - */ -typedef struct gemm_layer_struct { - uint32_t M; - uint32_t M_p; - uint32_t N; - uint32_t K; - - uint32_t TA; - uint32_t TB; - - uint32_t TILE_M; - uint32_t TILE_N; - uint32_t TILE_K; - - double *A; - double *B; - double *C; - - uint32_t ALPHA; - - precision_t dtype; - uint32_t expand; -} gemm_layer; - -/** - * @struct conv_layer_struct - * @brief This structure contains all parameters necessary for Convolutional - * layers - * @var conv_layer_struct::CO - * Number of output channels - * @var conv_layer_struct::CI - * Number of input channels - * @var conv_layer_struct::IH - * Height of input feature map - * @var conv_layer_struct::IW - * Width of input feature map - * @var conv_layer_struct::OH - * Height of output feature map - * @var conv_layer_struct::OW - * Width of output feature map - * @var conv_layer_struct::FH - * Height of filter - * @var conv_layer_struct::FW - * Width of filter - * @var conv_layer_struct::pad - * Padding on all sides - * @var conv_layer_struct::ifmap - * Pointer to input feature map - * @var conv_layer_struct::weights - * Pointer to weights - * @var conv_layer_struct::ofmap - * Pointer to output feature map - * @var conv_layer_struct::TILE_CI - * Tiling factor of input channel - * @var conv_layer_struct::cluster2cluster - * Flag for enabling cluster 2 cluster communication - * @var conv_layer_struct::im2col - * Flag for enabling im2col + GEMM - * @var conv_layer_struct::gamma - * Pointer to gamma for BatchNorm - * @var conv_layer_struct::beta - * Pointer to beta for BatchNorm - * @var gemm_layer_struct::dtype - * Precision of Convolution layer - */ -typedef struct conv_layer_struct { - // CONV2D - uint32_t CO; - uint32_t CI; - uint32_t IH; - uint32_t IW; - uint32_t OH; - uint32_t OW; - uint32_t FH; - uint32_t FW; - uint32_t pad; - - double *ifmap; - double *weights; - double *ofmap; - - uint32_t TILE_CI; - uint32_t cluster2cluster; - uint32_t im2col; - - // BATCHNORM - double *gamma; - double *beta; - - precision_t dtype; -} conv_layer; - -/** - * @struct dotp_layer_struct - * @brief This structure contains all parameters necessary for DOTP - * layers - * @var dotp_layer_struct::M - * Length of the vectors - * @var gemm_layer_struct::dtype - * Precision of Convolution layer - */ -typedef struct dotp_layer_struct { - // DOTP - uint32_t M; - - precision_t dtype; -} dotp_layer; diff --git a/software/tests/fdotp-32b-single/kernel/fdotp.c b/software/tests/fdotp-32b-single/kernel/fdotp.c deleted file mode 100644 index e57ae15..0000000 --- a/software/tests/fdotp-32b-single/kernel/fdotp.c +++ /dev/null @@ -1,166 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#include "fdotp.h" - -static inline int fp_check(const float a, const float b) { - const float threshold = 0.01f; - - // Absolute value - float comp = a - b; - if (comp < 0) - comp = -comp; - - return comp > threshold; -} - -// 32-bit dot-product: a * b -float fdotp_v32b_lmul8(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) { - unsigned int vl; - unsigned int iter = rounds; - - float red; - - // Set the vl - asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(avl)); - - asm volatile("vle32.v v8, (%0)" ::"r"(a)); - iter --; - asm volatile("vle32.v v16, (%0)" ::"r"(b)); - asm volatile("vfmul.vv v24, v8, v16"); - - // Stripmine and accumulate a partial reduced vector - while (iter > 0) { - // Load chunk a and b - a += offset; - asm volatile("vle32.v v8, (%0)" ::"r"(a)); - b += offset; - asm volatile("vle32.v v16, (%0)" ::"r"(b)); - iter --; - - // Multiply and accumulate - asm volatile("vfmacc.vv v24, v8, v16"); - } - - // Reduce and return - asm volatile("vfredusum.vs v0, v24, v0"); - asm volatile("vfmv.f.s %0, v0" : "=f"(red)); - return red; -} - -// 32-bit dot-product: a * b -float fdotp_v32b_lmul4(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) { - unsigned int vl; - unsigned int iter = rounds; - - float red; - - // Set the vl - asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(avl)); - - asm volatile("vle32.v v8, (%0)" ::"r"(a)); - iter --; - asm volatile("vle32.v v16, (%0)" ::"r"(b)); - asm volatile("vfmul.vv v24, v8, v16"); - - // Stripmine and accumulate a partial reduced vector - do { - // Load chunk a and b - a += offset; - asm volatile("vle32.v v8, (%0)" ::"r"(a)); - b += offset; - asm volatile("vle32.v v16, (%0)" ::"r"(b)); - iter --; - - // Multiply and accumulate - asm volatile("vfmacc.vv v24, v8, v16"); - } while (iter > 0); - - // Reduce and return - asm volatile("vfredusum.vs v0, v24, v0"); - asm volatile("vfmv.f.s %0, v0" : "=f"(red)); - return red; -} - -// 32-bit dot-product: a * b -float fdotp_v32b_lmul2(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) { - unsigned int vl; - unsigned int iter = rounds; - - float red; - - // Set the vl - asm volatile("vsetvli %0, %1, e32, m2, ta, ma" : "=r"(vl) : "r"(avl)); - - asm volatile("vle32.v v8, (%0)" ::"r"(a)); - iter --; - asm volatile("vle32.v v16, (%0)" ::"r"(b)); - asm volatile("vfmul.vv v24, v8, v16"); - - // Stripmine and accumulate a partial reduced vector - do { - // Load chunk a and b - a += offset; - asm volatile("vle32.v v8, (%0)" ::"r"(a)); - b += offset; - asm volatile("vle32.v v16, (%0)" ::"r"(b)); - iter --; - - // Multiply and accumulate - asm volatile("vfmacc.vv v24, v8, v16"); - } while (iter > 0); - - // Reduce and return - asm volatile("vfredusum.vs v0, v24, v0"); - asm volatile("vfmv.f.s %0, v0" : "=f"(red)); - return red; -} - -// 32-bit dot-product: a * b -float fdotp_v32b_lmul1(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) { - unsigned int vl; - unsigned int iter = rounds; - - float red; - - // Set the vl - asm volatile("vsetvli %0, %1, e32, m1, ta, ma" : "=r"(vl) : "r"(avl)); - - asm volatile("vle32.v v8, (%0)" ::"r"(a)); - iter --; - asm volatile("vle32.v v16, (%0)" ::"r"(b)); - asm volatile("vfmul.vv v24, v8, v16"); - - // Stripmine and accumulate a partial reduced vector - do { - // Load chunk a and b - a += offset; - asm volatile("vle32.v v8, (%0)" ::"r"(a)); - b += offset; - asm volatile("vle32.v v16, (%0)" ::"r"(b)); - iter --; - - // Multiply and accumulate - asm volatile("vfmacc.vv v24, v8, v16"); - } while (iter > 0); - - // Reduce and return - asm volatile("vfredusum.vs v0, v24, v0"); - asm volatile("vfmv.f.s %0, v0" : "=f"(red)); - return red; -} diff --git a/software/tests/fdotp-32b-single/kernel/fdotp.h b/software/tests/fdotp-32b-single/kernel/fdotp.h deleted file mode 100644 index dee0958..0000000 --- a/software/tests/fdotp-32b-single/kernel/fdotp.h +++ /dev/null @@ -1,33 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Matteo Perotti - -#ifndef _FDOTPROD_H_ -#define _FDOTPROD_H_ - -inline float fdotp_v32b_lmul8(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) - __attribute__((always_inline)); - -inline float fdotp_v32b_lmul4(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) - __attribute__((always_inline)); - -inline float fdotp_v32b_lmul2(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) - __attribute__((always_inline)); - -inline float fdotp_v32b_lmul1(const float *a, const float *b, const unsigned int offset, const unsigned int avl, const unsigned int rounds) - __attribute__((always_inline)); -#endif diff --git a/software/tests/fdotp-32b-single/main copy.c b/software/tests/fdotp-32b-single/main copy.c deleted file mode 100644 index 52a4ffd..0000000 --- a/software/tests/fdotp-32b-single/main copy.c +++ /dev/null @@ -1,130 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Diyou Shen - -#include -#include -#include - -#include DATAHEADER -#include "kernel/fdotp.c" - -// Single-core baseline of fdotp-32b: the whole dot product is computed on -// core 0 only. The other cores fall straight through to `return 0`. -// -// NOTE: no cluster barriers and no l1d_xbar_config() are used here. Those -// helpers issue snrt_cluster_hw_barrier() internally and would deadlock, -// since the remaining cores never reach the barrier. -int main() { - const uint32_t num_cores = 1; - const uint32_t cid = snrt_cluster_core_idx(); - - if (cid == 0) { - const int measure_iter = 3; - - // Byte-level interleaving for DRAM (default 512b), used to keep all DRAM - // channels busy while a single core streams the whole vector. - const uint32_t Interleave = 512; - const uint32_t max_vlen = 512; - // Best LMUL setting for the current configuration - const uint32_t lmul = Interleave * 8 / max_vlen; - - // Each round computes Interleave/4 32-bit elements - const uint32_t elem_per_round = Interleave * num_cores / 4; - // How many rounds are needed to cover the whole vector? - const uint32_t rounds = - (dotp_l.M > elem_per_round) - ? ((dotp_l.M + elem_per_round - 1) / elem_per_round) - : 1; - const uint32_t dim = elem_per_round / num_cores; - - // Initialize the cache (barrier-free, safe to call from core 0 alone) - l1d_init(0); - - printf("round:%u, lmul:%u, dim:%u\n", rounds, lmul, dim); - - // Reset timer - uint32_t timer = (uint32_t)-1; - uint32_t timer_tmp, timer_iter1 = 0; - - float *a_int = dotp_A_dram + dim * cid; - float *b_int = dotp_B_dram + dim * cid; - - for (int iter = 0; iter < measure_iter; iter++) { - // Start dump - start_kernel(); - - // Start timer - timer_tmp = benchmark_get_cycle(); - - // Calculate dotp over the whole vector - float acc; - if (lmul >= 8) - acc = fdotp_v32b_lmul8(a_int, b_int, elem_per_round, dim, rounds); - else if (lmul >= 4) - acc = fdotp_v32b_lmul4(a_int, b_int, elem_per_round, dim, rounds); - else if (lmul >= 2) - acc = fdotp_v32b_lmul2(a_int, b_int, elem_per_round, dim, rounds); - else if (lmul >= 1) - acc = fdotp_v32b_lmul1(a_int, b_int, elem_per_round, dim, rounds); - else - return -3; - - // Make sure spatz has finished writing - snrt_fence_spatz(); - - result[cid] = acc; - - // End timer and keep the best runtime - timer_tmp = benchmark_get_cycle() - timer_tmp; - timer = (timer < timer_tmp) ? timer : timer_tmp; - if (iter == 0) - timer_iter1 = timer; - - stop_kernel(); - } - - // Check and display results - uint32_t performance = 1000 * 2 * dotp_l.M / timer; - uint32_t perf_iter1 = 1000 * 2 * dotp_l.M / timer_iter1; - uint32_t utilization = performance / (2 * num_cores * 4); - uint32_t util_iter1 = perf_iter1 / (2 * num_cores * 4); - write_cyc(timer); - - printf("\n----- (%d) sp fdotp (single core) -----\n", dotp_l.M); - printf("The 1st execution took %u cycles.\n", timer_iter1); - printf("The performance is %u OP/1000cycle (%u%%o utilization).\n", - perf_iter1, util_iter1); - printf("The execution took %u cycles.\n", timer); - printf("The performance is %u OP/1000cycle (%u%%o utilization).\n", - performance, utilization); - - // Each iteration recomputes the same full dot product, so result[0] - // holds a single dot product and must match the golden value directly. - if (fp_check(result[0], dotp_result)) { - printf("Check Failed!\n"); - printf("Calc:"); - snrt_printf_float(result[0]); - printf(", Exp:"); - snrt_printf_float(dotp_result); - printf("\n"); - return -1; - } - } - - return 0; -} diff --git a/software/tests/fdotp-32b-single/main.c b/software/tests/fdotp-32b-single/main.c deleted file mode 100644 index e544c74..0000000 --- a/software/tests/fdotp-32b-single/main.c +++ /dev/null @@ -1,205 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// Author: Diyou Shen - -#include -#include -#include - -#include DATAHEADER -#include "kernel/fdotp.c" - -// Single-core baseline of fdotp-32b: the whole dot product is computed on -// core 0 only. The other cores fall straight through to `return 0`. -// -// NOTE: no cluster barriers and no l1d_xbar_config() are used here. Those -// helpers issue snrt_cluster_hw_barrier() internally and would deadlock, -// since the remaining cores never reach the barrier. -int main() { - const uint32_t num_cores = 1; - const uint32_t cid = snrt_cluster_core_idx(); - - if (cid == 0) { - const uint32_t measure_iter = 3; - - /*** DRAM Parameters for Optimization ***/ - const uint32_t l2_interleave = 16; - const uint32_t l2_channel = 4; - // in bits - const uint32_t l2_lanewidth = 512; - // This is the continuous address block (bits) in DRAM - const uint32_t l2_block_size = l2_lanewidth * l2_interleave; - const uint32_t l2_block_elem = l2_block_size / 32; - - /*** Core Parameters for Optimization ***/ - const uint32_t elem_per_core = dotp_l.M / num_cores; - const uint32_t lmul_m1 = 512; - const uint32_t lmul_m1_elem = lmul_m1 / 32; - - const uint32_t lmul_max = elem_per_core / lmul_m1_elem; - uint32_t lmul; - if (lmul_max >= 8) { - lmul = 8; - } else if (lmul_max >= 4) { - lmul = 4; - } else if (lmul_max >= 2) { - lmul = 2; - } else if (lmul_max == 1) { - lmul = 1; - } else { - // if (cid == 0) { - printf("FATAL: Problem size too small!\n"); - return -2; - // } - } - - uint32_t elem_per_round = lmul * lmul_m1_elem; - // We need to reduce scrambling size while keeping all channels busy - // This is needed to reduce the loop control overhead - uint32_t rounds = dotp_l.M / elem_per_round / num_cores; - - - if ((elem_per_round * num_cores) < (l2_block_elem * l2_channel)) { - // if (cid == 0) { - printf("Warning: Current scheme cannot utilize all bandwidth!\n"); - // } - } - - // We want to map one block for one core to access - // This will make the cores visiting different DRAM channel - // Therefore, we need to scramble the L1 xbar at the same size - // Notice scrambling here is in bytes - const uint32_t l1_scramble_bits = 31 - __builtin_clz(elem_per_round*32/8); - - // Set xbar policy - l1d_xbar_config(l1_scramble_bits); - - // Now for all cores, it will execute #elem_per_round# data each round - // And then jump #elem_per_round*num_cores# elements in address for next round - uint32_t elem_jump_per_round = elem_per_round * num_cores; - - // Reset timer - uint32_t timer = (uint32_t)-1; - uint32_t timer_tmp, timer_iter1; - - // Calculate the starting points for each core - float *a_int = dotp_A_dram + cid * elem_per_round; - float *b_int = dotp_B_dram + cid * elem_per_round; - - // if (cid == 0) { - printf("lmul:%u, elem:%u, offs:%u, iter:%u\n", lmul, elem_per_round, elem_jump_per_round, rounds); - // } - - - for (int iter = 0; iter < measure_iter; iter ++) { - // Start dump - // if (cid == 0) - start_kernel(); - - // snrt_cluster_hw_barrier(); - - // Start timer - timer_tmp = benchmark_get_cycle(); - - // Calculate dotp - float acc; - - if (lmul >= 8) - acc = fdotp_v32b_lmul8(a_int, b_int, elem_jump_per_round, elem_per_round, rounds); - else if (lmul >= 4) - acc = fdotp_v32b_lmul4(a_int, b_int, elem_jump_per_round, elem_per_round, rounds); - else if (lmul >= 2) - acc = fdotp_v32b_lmul2(a_int, b_int, elem_jump_per_round, elem_per_round, rounds); - else if (lmul >= 1) - acc = fdotp_v32b_lmul1(a_int, b_int, elem_jump_per_round, elem_per_round, rounds); - else - return -3; - - result[cid] = acc; - - // Make sure spatz has finished writing - snrt_fence_spatz(); - - // Wait for all cores to finish - // snrt_cluster_hw_barrier(); - - // End timer and check if new best runtime - // if (cid == 0) { - timer_tmp = benchmark_get_cycle() - timer_tmp; - timer = (timer < timer_tmp) ? timer : timer_tmp; - if (iter == 0) - timer_iter1 = timer; - - stop_kernel(); - // } - - // // Final reduction: two-level tree with group size 4 - // const uint32_t red_group = 4; - - // // Level 1: lead core of each group accumulates its group - // if (cid % red_group == 0) { - // for (uint32_t i = 1; i < red_group && (cid + i) < num_cores; ++i) - // acc += result[cid + i]; - // result[cid] = acc; - // } - - // // snrt_cluster_hw_barrier(); - - // // Level 2: core 0 sums all group results - // if (cid == 0) { - // for (uint32_t g = red_group; g < num_cores; g += red_group) - // acc += result[g]; - // result[0] = acc; - // } - - } - - // snrt_cluster_hw_barrier(); - - // Check and display results - // if (cid == 0) { - // The timer did not count the reduction time - uint32_t performance = 1000 * 2 * dotp_l.M / timer; - uint32_t perf_iter1 = 1000 * 2 * dotp_l.M / timer_iter1; - uint32_t utilization = performance / (2 * num_cores * 4); - uint32_t util_iter1 = perf_iter1 / (2 * num_cores * 4); - write_cyc(timer); - - printf("\n----- (%d) sp fdotp -----\n", dotp_l.M); - printf("The 1st execution took %u cycles.\n", timer_iter1); - printf("The performance is %u OP/1000cycle (%u%%o utilization).\n", - perf_iter1 , util_iter1); - printf("The execution took %u cycles.\n", timer); - printf("The performance is %u OP/1000cycle (%u%%o utilization).\n", - performance, utilization); - // } - - // if (cid == 0) { - if (fp_check(result[0], dotp_result*measure_iter)) { - printf("Check Failed!\n"); - printf("Calc:"); - snrt_printf_float(result[0]); - printf(", Exp:"); - snrt_printf_float((float)(dotp_result * measure_iter)); - printf("\n"); - return -1; - } - // } - } - - return 0; -} diff --git a/software/tests/fdotp-32b-single/script/data_1024.json b/software/tests/fdotp-32b-single/script/data_1024.json deleted file mode 100644 index 96712c5..0000000 --- a/software/tests/fdotp-32b-single/script/data_1024.json +++ /dev/null @@ -1,12 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Parameters for a DOTP - -{ - kernel: "DOTP" - M: 1024, - prec: 32, - expand: 0 -} diff --git a/software/tests/fdotp-32b-single/script/data_8192.json b/software/tests/fdotp-32b-single/script/data_8192.json deleted file mode 100644 index aa351d3..0000000 --- a/software/tests/fdotp-32b-single/script/data_8192.json +++ /dev/null @@ -1,12 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Parameters for a DOTP - -{ - kernel: "DOTP" - M: 8192, - prec: 32, - expand: 0 -} diff --git a/software/tests/fdotp-32b-single/script/gen_data.py b/software/tests/fdotp-32b-single/script/gen_data.py deleted file mode 100644 index 8513133..0000000 --- a/software/tests/fdotp-32b-single/script/gen_data.py +++ /dev/null @@ -1,186 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -# Author: Matheus Cavalcante - -import numpy as np -import torch -import argparse -import pathlib -import hjson -from functools import reduce - -np.random.seed(42) -torch.manual_seed(42) - -global verbose - - -def array_to_cstr(a, fmt=float): - out = "{" - if fmt == float: - if isinstance(a, np.ndarray): - a = a.flat - if isinstance(a, torch.Tensor): - a = a.numpy().flat - for el in a: - out += "{}, ".format(el) - else: - for sign, exp, mant in zip( - a["sign"].numpy().flat, - a["exponent"].numpy().flat, - a["mantissa"].numpy().flat, - ): - value = sign * 2**7 + exp * 2**2 + mant - out += "0x{:02x}, ".format(value) - out = out[:-2] + "}" - return out - - -def emit_header_file(layer_type: str, **kwargs): - - file_path = pathlib.Path(__file__).parent.parent / "data" - emit_str = ( - "// Copyright 2023 ETH Zurich and University of Bologna.\n" - + "// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n" - + "// SPDX-License-Identifier: Apache-2.0\n\n" - + "// This file was generated automatically.\n\n" - ) - - file = file_path / ("data_" + str(kwargs["M"]) + ".h") - emit_str += emit_dotp_layer(**kwargs) - with file.open("w") as f: - f.write(emit_str) - - -def emit_dotp_layer(name="dotp", **kwargs): - vec_A = kwargs["A"] - vec_B = kwargs["B"] - result = kwargs["result"] - - m = kwargs["M"] - - layer_str = "" - layer_str += '#include "layer.h"\n\n' - layer_str += f"dotp_layer {name}_l __attribute__((section(\".data\"))) = {{\n" - layer_str += f"\t.M = {m},\n" - layer_str += f'\t.dtype = FP{kwargs["prec"]},\n' - layer_str += "};\n\n\n" - - ctypes = {"64": "double", "32": "float", "16": "__fp16", "8": "char"} - - dtype = ctypes[str(kwargs["prec"])] - if dtype != "char": - layer_str += ( - f'static {dtype} {name}_A_dram [{m}] __attribute__((section(".pdcp_src"), used)) = ' - + array_to_cstr(vec_A) - + ";\n\n\n" - ) - layer_str += ( - f'static {dtype} {name}_B_dram [{m}] __attribute__((section(".pdcp_src"), used))= ' - + array_to_cstr(vec_B) - + ";\n\n\n" - ) - layer_str += ( - f'static {dtype} {name}_result __attribute__((section(".data"))) = ' - + array_to_cstr(result) - + ";\n\n\n" - ) - layer_str += '// Global memory location to hold reduction results for each core\n' - layer_str += ( - f'{dtype} result [64] __attribute__((section(".data"))) = {{0}}' - + ";\n\n\n" - ) - else: - layer_str += ( - f"static {dtype} {name}_A_dram [{m}] = " - + array_to_cstr(kwargs["bits_A"], fmt="char") - + ";\n\n\n" - ) - layer_str += ( - f"static {dtype} {name}_B_dram [{m}] = " - + array_to_cstr(kwargs["bits_B"], fmt="char") - + ";\n\n\n" - ) - layer_str += ( - f"static {dtype} {name}_result = " - + array_to_cstr(kwargs["result"], fmt="char") - + ";\n\n\n" - ) - - return layer_str - - -def rand_data_generator(shape, prec, alt=False): - if prec == 64: - return torch.randn(shape, requires_grad=False, dtype=torch.float64), {} - elif prec == 32: - return torch.randn(shape, requires_grad=False, dtype=torch.float32), {} - elif prec == 16: - if alt: - return torch.randn(shape, requires_grad=False, dtype=torch.bfloat16), {} - else: - return torch.randn(shape, requires_grad=False, dtype=torch.float16), {} - elif prec == 8: - sign = torch.randint( - 0, 2, shape, requires_grad=False, dtype=torch.uint8 - ) # -1 or 1 - exponent = torch.randint( - 0, 16, shape, requires_grad=False, dtype=torch.uint8 - ) # < 0b01111 - mantissa = torch.randint( - 0, 4, shape, requires_grad=False, dtype=torch.uint8 - ) # can be arbitrary - bits = {"sign": sign, "exponent": exponent, "mantissa": mantissa} - # TODO: not actually correct - return ((-1.0) ** sign.double()) * (2.0 ** (exponent.double() - 15.0)) * ( - 1.0 + mantissa.double() / (2**2) - ), bits - - -def dotp(a, b): - return reduce(lambda a, b: a + b, np.multiply(a, b)) - - -def main(): - - parser = argparse.ArgumentParser(description="Generate data for kernels") - parser.add_argument( - "-c", - "--cfg", - type=pathlib.Path, - required=True, - help="Select param config file kernel", - ) - parser.add_argument("-v", "--verbose", action="store_true", help="Set verbose") - - args = parser.parse_args() - - global verbose - verbose = args.verbose - - with args.cfg.open() as f: - param = hjson.loads(f.read()) - - vec_A, bits_A = rand_data_generator((param["M"], 1), param["prec"]) - vec_B, bits_B = rand_data_generator((param["M"], 1), param["prec"]) - result = dotp(vec_A, vec_B) - - kwargs = { - "A": vec_A, - "B": vec_B, - "result": result, - "M": param["M"], - "prec": param["prec"], - "expand": param["expand"], - "bits_A": bits_A, - "bits_B": bits_B, - } - - emit_header_file("dotp", **kwargs) - - -if __name__ == "__main__": - main() diff --git a/software/tests/fdotp-32b/main.c b/software/tests/fdotp-32b/main.c index a9fc3ae..6b60792 100644 --- a/software/tests/fdotp-32b/main.c +++ b/software/tests/fdotp-32b/main.c @@ -165,6 +165,8 @@ int main() { #ifdef LP1 // Consumer: drop stale private-L1 copies of result[] (from a previous // measure_iter pass) so the peer partials are refetched fresh from L2. + snrt_fence(); + lp1_wt_flush(); lp1_inval(); snrt_fence(); #endif diff --git a/software/tests/fft-32b/main.c b/software/tests/fft-32b/main.c index 61bf17a..0d3cc25 100644 --- a/software/tests/fft-32b/main.c +++ b/software/tests/fft-32b/main.c @@ -113,7 +113,7 @@ int main() { } // In first part of calculation, we need barrier after each round - // l1_fence + // TODO: might need an L1 fence (flush) here snrt_cluster_hw_barrier(); } From 8d42ee61074ee6d5853c2cf19d60f7015a711221 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Thu, 9 Jul 2026 17:39:14 +0200 Subject: [PATCH 28/39] [SW] init FFT coherence protection --- hardware/src/cachepool_tile.sv | 2 +- software/tests/fdotp-32b/main.c | 4 +- software/tests/fft-32b/kernel/fft.c | 19 ++++++++- software/tests/fft-32b/main.c | 63 ++++++++++++++++++++++++++++- 4 files changed, 83 insertions(+), 5 deletions(-) diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index 311c3ba..01986d3 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -340,7 +340,7 @@ module cachepool_tile reqWords: 1, reqTransIdWidth: LP1TidWidth + LP1NumWordOffsetBits, reqSrcIdWidth: $clog2(LP1NrRequesters), // selects requester port (0 Spatz / 1 Snitch / 2 CMO) - victimSel: hpdcache_pkg::HPDCACHE_VICTIM_PLRU, + victimSel: hpdcache_pkg::HPDCACHE_VICTIM_RANDOM, dataWaysPerRamWord: 1, dataSetsPerRam: LP1NumSets, dataRamByteEnable: 1'b1, diff --git a/software/tests/fdotp-32b/main.c b/software/tests/fdotp-32b/main.c index 6b60792..707740f 100644 --- a/software/tests/fdotp-32b/main.c +++ b/software/tests/fdotp-32b/main.c @@ -165,8 +165,8 @@ int main() { #ifdef LP1 // Consumer: drop stale private-L1 copies of result[] (from a previous // measure_iter pass) so the peer partials are refetched fresh from L2. - snrt_fence(); - lp1_wt_flush(); + // snrt_fence(); + // lp1_wt_flush(); lp1_inval(); snrt_fence(); #endif diff --git a/software/tests/fft-32b/kernel/fft.c b/software/tests/fft-32b/kernel/fft.c index 2723e98..66a5497 100644 --- a/software/tests/fft-32b/kernel/fft.c +++ b/software/tests/fft-32b/kernel/fft.c @@ -83,15 +83,24 @@ void fft_p1 (float *src, float *buf, const float *twi, // im_l_o = (re_u_i - re_l_i) * im_twi + (im_u_i - im_l_i) * re_twi; asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(avl)); + // LP1 (private-L1) is write-through & non-coherent. The butterfly inputs + // (re/im upper/lower wings) are data another core wrote in the previous + // stage, so invalidate this core's private lines before EACH input load to + // force a miss down to the fresh copy in shared L2. (Twiddles are + // read-only constants -- no staleness -- so they are not invalidated.) + LP1_INVAL_BEFORE_LOAD(); asm volatile("vle32.v v0, (%0);" ::"r"(re_u_i)); // v0: Re upper wing re_u_i += vl; + LP1_INVAL_BEFORE_LOAD(); asm volatile("vle32.v v4, (%0);" ::"r"(re_l_i)); // v4: Re lower wing re_l_i += vl; asm volatile("vfadd.vv v16, v0, v4"); // v16: Re butterfly output upper wing asm volatile("vfsub.vv v0, v0, v4"); // v0: Re butterfly output upper wing + LP1_INVAL_BEFORE_LOAD(); asm volatile("vle32.v v8, (%0);" ::"r"(im_u_i)); // v8: Im upper wing im_u_i += vl; + LP1_INVAL_BEFORE_LOAD(); asm volatile("vle32.v v12, (%0);" ::"r"(im_l_i)); // v12: Im lower wing im_l_i += vl; @@ -99,9 +108,11 @@ void fft_p1 (float *src, float *buf, const float *twi, asm volatile("vfsub.vv v4, v8, v12"); // v4: Im butterfly output upper wing - // Load the twiddle vector + // Load the twiddle vector (read-only, no invalidate needed) + LP1_INVAL_BEFORE_LOAD(); asm volatile("vle32.v v8, (%0);" ::"r"(re_twi)); // v8: Re twi re_twi += vl; + LP1_INVAL_BEFORE_LOAD(); asm volatile("vle32.v v12, (%0);" ::"r"(im_twi)); // v12: Im twi im_twi += vl; @@ -113,18 +124,24 @@ void fft_p1 (float *src, float *buf, const float *twi, asm volatile("vfmul.vv v24, v0, v8"); asm volatile("vfnmsac.vv v24, v4, v12"); // v24: Re butterfly output // twiddled lower wing + // Flush after EACH store so the write-through output reaches shared L2 and + // becomes visible to the cores that consume it in the next stage. asm volatile("vse32.v v16, (%0)" ::"r"(re_u_o)); re_u_o += vl; + LP1_FLUSH_AFTER_STORE(); asm volatile("vse32.v v20, (%0)" ::"r"(im_u_o)); im_u_o += vl; + LP1_FLUSH_AFTER_STORE(); asm volatile("vfmul.vv v28, v0, v12"); asm volatile("vfmacc.vv v28, v4, v8"); // v28: Im butterfly output // twiddled lower wing asm volatile("vse32.v v24, (%0)" ::"r"(re_l_o)); re_l_o += vl; + LP1_FLUSH_AFTER_STORE(); asm volatile("vse32.v v28, (%0)" ::"r"(im_l_o)); im_l_o += vl; + LP1_FLUSH_AFTER_STORE(); } } diff --git a/software/tests/fft-32b/main.c b/software/tests/fft-32b/main.c index 0d3cc25..bf259be 100644 --- a/software/tests/fft-32b/main.c +++ b/software/tests/fft-32b/main.c @@ -24,6 +24,51 @@ #include #include DATAHEADER + +// LP1 (private-L1) coherency protection toggle. +// LP1 is per-core, write-through, NON-coherent. Coherency between cores is +// re-established purely in software with CMOs + fences: +// producer/release: snrt_fence_spatz(); snrt_fence(); lp1_wt_flush(); +// consumer/acquire: lp1_inval(); snrt_fence(); +// snrt_fence_spatz() (sfence.vma) is required before every flush because the +// FFT kernels write with asynchronous Spatz vector stores. +// +// Phase 1 (fft_p1) performs cross-core data swapping *at the granularity of the +// individual vector load/store*, so a single invalidate at call entry is NOT +// enough: data another core wrote is not guaranteed visible to this core's +// later loads. We therefore invalidate before *every* butterfly-input load and +// flush after *every* output store, from inside the kernel (see kernel/fft.c). +// These helpers are defined here, above the kernel include, so fft_p1 can call +// them. Phase-2 interior stays bare -- its s<->buf swaps are local to each +// core's own LP1 -- only the phase boundaries around fft_p2 are bracketed. +#define LP1 + +#ifdef LP1 +#include +// Release: make this core's write-through output visible in shared L2. +// Used both after each fft_p1 output store and at the phase-2 exit boundary. +static inline void lp1_release() { + // snrt_fence_spatz(); // wait for async Spatz vector stores to retire + snrt_fence(); + lp1_wt_flush(); // drain the write-through write buffer to L2 + snrt_fence(); +} +// Acquire: drop stale private lines so the following read misses to fresh L2. +// Used both before each fft_p1 butterfly-input load and at consumer boundaries. +static inline void lp1_acquire() { + lp1_inval(); + snrt_fence(); +} +// Per-load / per-store hooks used inside the fft_p1 kernel. +#define LP1_INVAL_BEFORE_LOAD() lp1_acquire() +#define LP1_FLUSH_AFTER_STORE() lp1_release() +#else +static inline void lp1_release() {} +static inline void lp1_acquire() {} +#define LP1_INVAL_BEFORE_LOAD() do {} while (0) +#define LP1_FLUSH_AFTER_STORE() do {} while (0) +#endif + #include "kernel/fft.c" static inline int fp_check(const float a, const float b) { @@ -103,7 +148,13 @@ int main() { for (uint32_t i = 0; i < log2_nfft1; i ++) { if (cid < active_cores) { + // fft_p1 self-protects: it invalidates before every butterfly-input + // load and flushes after every output store (cross-core swapping is + // per-load/store, not just per-call). The inter-stage barrier below + // still provides the ordering between producers and consumers. + lp1_acquire(); fft_p1(src_p1, buf_p1, twi_p1, NFFT, NTWI_P1, cid, active_cores, i, len); + lp1_release(); // each round will use half the twiddle than previous round // the first round needs re/im NFFT/2 twiddles src_p1 = (i & 1) ? samples_dram : buffer_dram; @@ -113,13 +164,18 @@ int main() { } // In first part of calculation, we need barrier after each round - // TODO: might need an L1 fence (flush) here snrt_cluster_hw_barrier(); } if (cid < active_cores) { + // Consumer acquire: phase-2 reads this core's contiguous chunk + // (samples/buffer_dram + cid*NFFTpc), whose data was produced by other + // cores under phase 1's (different) partition. Drop stale local lines. + lp1_acquire(); // Fall back into the single-core case // Each core just do a FFT on (NFFT >> stage_in_P1) data + // Phase-2 interior needs no CMOs: its s<->buf swaps stay within this + // core's own LP1. if (p2_switch) { fft_p2(buf_p2, src_p2, twi_p2, out_p2, store_idx_dram, (NFFT>>log2_nfft1), NFFT, log2_nfft2, stride, log2_nfft1, NTWI_P2); @@ -127,6 +183,8 @@ int main() { fft_p2(src_p2, buf_p2, twi_p2, out_p2, store_idx_dram, (NFFT>>log2_nfft1), NFFT, log2_nfft2, stride, log2_nfft1, NTWI_P2); } + // Producer release: publish out[] to L2 for core-0 verification. + lp1_release(); } // Wait for all cores to finish fft snrt_cluster_hw_barrier(); @@ -148,6 +206,9 @@ int main() { if (cid == 0) { if ((iter == 0) && CHECK) { + // Consumer acquire: drop core-0's stale private lines so the checks + // read the freshly-produced out[] from L2. + lp1_acquire(); // Verify the real part for (unsigned int i = 0; i < NFFT; i++) { if (fp_check(out[i], gold_out_dram[2 * i])) { From fd06fda738bd12c542e6e5428b8cf03fd0e674a1 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Fri, 10 Jul 2026 17:55:57 +0200 Subject: [PATCH 29/39] [SW] FFT data generation change from .pdcp_src to .data (DRAM) --- software/tests/fft-32b/kernel/fft.c | 21 +--- software/tests/fft-32b/main.c | 140 ++++++++++++---------- software/tests/fft-32b/script/gen_data.py | 16 +-- software/tests/fmatmul-32b/main.c | 2 +- 4 files changed, 87 insertions(+), 92 deletions(-) diff --git a/software/tests/fft-32b/kernel/fft.c b/software/tests/fft-32b/kernel/fft.c index 66a5497..1a46fb2 100644 --- a/software/tests/fft-32b/kernel/fft.c +++ b/software/tests/fft-32b/kernel/fft.c @@ -83,24 +83,15 @@ void fft_p1 (float *src, float *buf, const float *twi, // im_l_o = (re_u_i - re_l_i) * im_twi + (im_u_i - im_l_i) * re_twi; asm volatile("vsetvli %0, %1, e32, m4, ta, ma" : "=r"(vl) : "r"(avl)); - // LP1 (private-L1) is write-through & non-coherent. The butterfly inputs - // (re/im upper/lower wings) are data another core wrote in the previous - // stage, so invalidate this core's private lines before EACH input load to - // force a miss down to the fresh copy in shared L2. (Twiddles are - // read-only constants -- no staleness -- so they are not invalidated.) - LP1_INVAL_BEFORE_LOAD(); asm volatile("vle32.v v0, (%0);" ::"r"(re_u_i)); // v0: Re upper wing re_u_i += vl; - LP1_INVAL_BEFORE_LOAD(); asm volatile("vle32.v v4, (%0);" ::"r"(re_l_i)); // v4: Re lower wing re_l_i += vl; asm volatile("vfadd.vv v16, v0, v4"); // v16: Re butterfly output upper wing asm volatile("vfsub.vv v0, v0, v4"); // v0: Re butterfly output upper wing - LP1_INVAL_BEFORE_LOAD(); asm volatile("vle32.v v8, (%0);" ::"r"(im_u_i)); // v8: Im upper wing im_u_i += vl; - LP1_INVAL_BEFORE_LOAD(); asm volatile("vle32.v v12, (%0);" ::"r"(im_l_i)); // v12: Im lower wing im_l_i += vl; @@ -108,11 +99,9 @@ void fft_p1 (float *src, float *buf, const float *twi, asm volatile("vfsub.vv v4, v8, v12"); // v4: Im butterfly output upper wing - // Load the twiddle vector (read-only, no invalidate needed) - LP1_INVAL_BEFORE_LOAD(); + // Load the twiddle vector asm volatile("vle32.v v8, (%0);" ::"r"(re_twi)); // v8: Re twi re_twi += vl; - LP1_INVAL_BEFORE_LOAD(); asm volatile("vle32.v v12, (%0);" ::"r"(im_twi)); // v12: Im twi im_twi += vl; @@ -124,24 +113,18 @@ void fft_p1 (float *src, float *buf, const float *twi, asm volatile("vfmul.vv v24, v0, v8"); asm volatile("vfnmsac.vv v24, v4, v12"); // v24: Re butterfly output // twiddled lower wing - // Flush after EACH store so the write-through output reaches shared L2 and - // becomes visible to the cores that consume it in the next stage. asm volatile("vse32.v v16, (%0)" ::"r"(re_u_o)); re_u_o += vl; - LP1_FLUSH_AFTER_STORE(); asm volatile("vse32.v v20, (%0)" ::"r"(im_u_o)); im_u_o += vl; - LP1_FLUSH_AFTER_STORE(); asm volatile("vfmul.vv v28, v0, v12"); asm volatile("vfmacc.vv v28, v4, v8"); // v28: Im butterfly output // twiddled lower wing asm volatile("vse32.v v24, (%0)" ::"r"(re_l_o)); re_l_o += vl; - LP1_FLUSH_AFTER_STORE(); asm volatile("vse32.v v28, (%0)" ::"r"(im_l_o)); im_l_o += vl; - LP1_FLUSH_AFTER_STORE(); } } @@ -268,4 +251,4 @@ void fft_p2(float *s, float *buf, const float *twi, float *out, } } } -} +} \ No newline at end of file diff --git a/software/tests/fft-32b/main.c b/software/tests/fft-32b/main.c index bf259be..8c9d3f7 100644 --- a/software/tests/fft-32b/main.c +++ b/software/tests/fft-32b/main.c @@ -24,53 +24,37 @@ #include #include DATAHEADER +#include "kernel/fft.c" -// LP1 (private-L1) coherency protection toggle. -// LP1 is per-core, write-through, NON-coherent. Coherency between cores is -// re-established purely in software with CMOs + fences: +// --------------------------------------------------------------------------- +// Private-L1 (LP1) coherency protection. +// +// LP1 is the per-core, write-through, NON-coherent private cache; Snitch scalar +// AND Spatz vector accesses both go through it. Coherency between cores is +// re-established purely in software, at every cross-core producer->consumer +// handoff, with the two CMO+fence sequences below: +// // producer/release: snrt_fence_spatz(); snrt_fence(); lp1_wt_flush(); -// consumer/acquire: lp1_inval(); snrt_fence(); -// snrt_fence_spatz() (sfence.vma) is required before every flush because the -// FFT kernels write with asynchronous Spatz vector stores. +// drain this core's write-through buffer down to shared L2 so peers can see +// it. sfence.vma is mandatory first -- the FFT stores are async Spatz +// vector stores and must retire into the write buffer before we drain it. +// +// consumer/acquire: lp1_inval(); snrt_fence(); +// drop this core's stale private lines so the next reads miss down to the +// fresh copy in shared L2. // -// Phase 1 (fft_p1) performs cross-core data swapping *at the granularity of the -// individual vector load/store*, so a single invalidate at call entry is NOT -// enough: data another core wrote is not guaranteed visible to this core's -// later loads. We therefore invalidate before *every* butterfly-input load and -// flush after *every* output store, from inside the kernel (see kernel/fft.c). -// These helpers are defined here, above the kernel include, so fft_p1 can call -// them. Phase-2 interior stays bare -- its s<->buf swaps are local to each -// core's own LP1 -- only the phase boundaries around fft_p2 are bracketed. +// The cluster barrier gives ordering only, not visibility, so BOTH sides are +// required. CMOs are issued at stage / phase granularity, never per vector +// load: a whole-cache INVAL between in-flight Spatz stores races the +// outstanding stores and corrupts data. +// +// Comment out `#define LP1` to fall back to the (all-wrong) unprotected build. #define LP1 #ifdef LP1 #include -// Release: make this core's write-through output visible in shared L2. -// Used both after each fft_p1 output store and at the phase-2 exit boundary. -static inline void lp1_release() { - // snrt_fence_spatz(); // wait for async Spatz vector stores to retire - snrt_fence(); - lp1_wt_flush(); // drain the write-through write buffer to L2 - snrt_fence(); -} -// Acquire: drop stale private lines so the following read misses to fresh L2. -// Used both before each fft_p1 butterfly-input load and at consumer boundaries. -static inline void lp1_acquire() { - lp1_inval(); - snrt_fence(); -} -// Per-load / per-store hooks used inside the fft_p1 kernel. -#define LP1_INVAL_BEFORE_LOAD() lp1_acquire() -#define LP1_FLUSH_AFTER_STORE() lp1_release() -#else -static inline void lp1_release() {} -static inline void lp1_acquire() {} -#define LP1_INVAL_BEFORE_LOAD() do {} while (0) -#define LP1_FLUSH_AFTER_STORE() do {} while (0) #endif -#include "kernel/fft.c" - static inline int fp_check(const float a, const float b) { const float threshold = 0.01f; @@ -90,7 +74,7 @@ static inline int fp_check(const float a, const float b) { // 1024 -> 64 int main() { - const int measure_iter = 2; + const int measure_iter = 1; // twiddle layout: [re_p1, im_p1, re_p2, im_p2] const uint32_t num_cores = snrt_cluster_core_num(); @@ -111,10 +95,21 @@ int main() { uint32_t timer = (uint32_t)-1; uint32_t timer_tmp, timer_iter1; - // Set xbar policy - // Currently set to fully interleave (log2(512/8)) + // Set xbar policy: fully interleave at cacheline granularity. + // 6 = log2(512b / 8) = log2(64B) = the bit offset where the bank-select + // field starts; it is the finest interleave the HW allows and is independent + // of core/bank count. l1d_xbar_config() runs its own fence + cluster barriers + // and already guards the register write to core 0 internally, so it MUST be + // entered by ALL cores. The old `if (cid == 0)` guard let only core 0 reach + // those internal barriers, desynchronising the whole cluster barrier. + // if (cid == 0) { + // l1d_xbar_config(6); + // } l1d_xbar_config(6); + // Wait for all cores to finish + snrt_cluster_hw_barrier(); + // Calculate pointers for the second butterfly onwards float *src_p2 = samples_dram + cid * NFFTpc; float *buf_p2 = buffer_dram + cid * NFFTpc; @@ -148,13 +143,23 @@ int main() { for (uint32_t i = 0; i < log2_nfft1; i ++) { if (cid < active_cores) { - // fft_p1 self-protects: it invalidates before every butterfly-input - // load and flushes after every output store (cross-core swapping is - // per-load/store, not just per-call). The inter-stage barrier below - // still provides the ordering between producers and consumers. - lp1_acquire(); +#ifdef LP1 + // Consumer/acquire: this stage reads `src`, which for stage > 0 was + // written by (possibly) other cores in the previous stage. Drop stale + // private lines so the reads miss down to the fresh copy in shared L2. + lp1_inval(); + snrt_fence(); +#endif fft_p1(src_p1, buf_p1, twi_p1, NFFT, NTWI_P1, cid, active_cores, i, len); - lp1_release(); +#ifdef LP1 + // Producer/release: drain this stage's write-through output down to L2 + // so the next stage's consumers (on other cores) see it after the + // barrier. sfence.vma first: the Spatz vector stores are async and must + // retire into the write buffer before we drain it. + snrt_fence_spatz(); + snrt_fence(); + lp1_wt_flush(); +#endif // each round will use half the twiddle than previous round // the first round needs re/im NFFT/2 twiddles src_p1 = (i & 1) ? samples_dram : buffer_dram; @@ -168,10 +173,13 @@ int main() { } if (cid < active_cores) { - // Consumer acquire: phase-2 reads this core's contiguous chunk - // (samples/buffer_dram + cid*NFFTpc), whose data was produced by other - // cores under phase 1's (different) partition. Drop stale local lines. - lp1_acquire(); +#ifdef LP1 + // Consumer/acquire: phase 2 reads samples/buffer_dram + cid*NFFTpc, a + // DIFFERENT partition than phase 1 used, produced by other cores in the + // last phase-1 stage. Drop stale private lines before reading. + lp1_inval(); + snrt_fence(); +#endif // Fall back into the single-core case // Each core just do a FFT on (NFFT >> stage_in_P1) data // Phase-2 interior needs no CMOs: its s<->buf swaps stay within this @@ -183,8 +191,12 @@ int main() { fft_p2(src_p2, buf_p2, twi_p2, out_p2, store_idx_dram, (NFFT>>log2_nfft1), NFFT, log2_nfft2, stride, log2_nfft1, NTWI_P2); } - // Producer release: publish out[] to L2 for core-0 verification. - lp1_release(); +#ifdef LP1 + // Producer/release: publish out[] down to L2 for core-0 verification. + snrt_fence_spatz(); + snrt_fence(); + lp1_wt_flush(); +#endif } // Wait for all cores to finish fft snrt_cluster_hw_barrier(); @@ -197,18 +209,18 @@ int main() { timer_iter1 = timer; stop_kernel(); - } - - // All cores flush before first-iteration verification - if ((iter == 0) && CHECK) { - l1d_cluster_flush(); - } - if (cid == 0) { if ((iter == 0) && CHECK) { - // Consumer acquire: drop core-0's stale private lines so the checks - // read the freshly-produced out[] from L2. - lp1_acquire(); + l1d_flush(); + l1d_wait(); + +#ifdef LP1 + // Consumer/acquire: drop core-0's stale private lines so the checks read + // the freshly-produced out[] (now in L2/DRAM after the flush above). + lp1_inval(); + snrt_fence(); +#endif + // Verify the real part for (unsigned int i = 0; i < NFFT; i++) { if (fp_check(out[i], gold_out_dram[2 * i])) { @@ -256,4 +268,4 @@ int main() { return 1; else return 0; -} +} \ No newline at end of file diff --git a/software/tests/fft-32b/script/gen_data.py b/software/tests/fft-32b/script/gen_data.py index 88b1c92..6acd28a 100644 --- a/software/tests/fft-32b/script/gen_data.py +++ b/software/tests/fft-32b/script/gen_data.py @@ -290,25 +290,25 @@ def main(): emit_str += 'static uint32_t active_cores = {};\n\n'.format(CORES) # L1 Data - emit_str += 'float out[{}]'.format(2 * NFFT) + ' __attribute__((section(".pdcp_src"))) = { [0 ... ' + str(2 * NFFT - 1) + '] = 0 };\n' + emit_str += 'float out[{}]'.format(2 * NFFT) + ' __attribute__((section(".data"))) = { [0 ... ' + str(2 * NFFT - 1) + '] = 0 };\n' # L2 Data - emit_str += 'static float samples_dram[{}]'.format(2 * NFFT) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( + emit_str += 'static float samples_dram[{}]'.format(2 * NFFT) + ' __attribute__((section(".data"))) = {' + ', '.join( map(str, samples_reim.astype(dtype).tolist())) + '};\n' - emit_str += 'static float buffer_dram[{}]'.format(2 * NFFT) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( + emit_str += 'static float buffer_dram[{}]'.format(2 * NFFT) + ' __attribute__((section(".data"))) = {' + ', '.join( map(str, buffer_dram.astype(dtype).tolist())) + '};\n' if CORES == 1: - emit_str += 'static float twiddle_dram[{}]'.format(2 * N_TWID_P2) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( + emit_str += 'static float twiddle_dram[{}]'.format(2 * N_TWID_P2) + ' __attribute__((section(".data"))) = {' + ', '.join( map(str, twiddle_vec_reim.astype(dtype).tolist())) + '};\n' else: - emit_str += 'static float twiddle_dram[{}]'.format(2 * (CORES*N_TWID_P2 + N_TWID_P1)) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( + emit_str += 'static float twiddle_dram[{}]'.format(2 * (CORES*N_TWID_P2 + N_TWID_P1)) + ' __attribute__((section(".data"))) = {' + ', '.join( map(str, twiddle_vec_reim.astype(dtype).tolist())) + '};\n' - emit_str += 'static uint16_t store_idx_dram[{}]'.format(int(np.log2(NFFTpc / 2) * NFFTpc / 2)) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( + emit_str += 'static uint16_t store_idx_dram[{}]'.format(int(np.log2(NFFTpc / 2) * NFFTpc / 2)) + ' __attribute__((section(".data"))) = {' + ', '.join( map(str, np.array(store_delta).astype(idx_dtype).tolist())) + '};\n' emit_str += 'static uint32_t coffset_dram[{}]'.format(int( - CORES)) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join(map(str, core_offsets)) + '};\n' + CORES)) + ' __attribute__((section(".data"))) = {' + ', '.join(map(str, core_offsets)) + '};\n' emit_str += 'static float gold_out_dram[{}]'.format( - 2 * NFFT) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join(map(str, gold_out_s.astype(dtype).tolist())) + '};\n' + 2 * NFFT) + ' __attribute__((section(".data"))) = {' + ', '.join(map(str, gold_out_s.astype(dtype).tolist())) + '};\n' file_path = pathlib.Path(__file__).parent.parent / 'data' file = file_path / ('data_' + str(NFFT) + "_" + str(CORES) + ".h") diff --git a/software/tests/fmatmul-32b/main.c b/software/tests/fmatmul-32b/main.c index 3183afc..539ccc4 100644 --- a/software/tests/fmatmul-32b/main.c +++ b/software/tests/fmatmul-32b/main.c @@ -94,7 +94,7 @@ int main() { // Set xbar policy and switch to private cache mode for the matmul. // All cores will access the same B; scramble based on cacheline. l1d_xbar_config(5); - l1d_part(4); + // l1d_part(4); a = gemm_A_dram; b = gemm_B_dram; From 6233342d0c3ab56d2ca1442bcc096f0ad76ca0ad Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Mon, 13 Jul 2026 18:02:12 +0200 Subject: [PATCH 30/39] MATMUL access misalignment fix --- hardware/src/cachepool_l1_ctrl.sv | 5 +- sim/scripts/vsim_tile.tcl | 1 + software/tests/fmatmul-32b/main.c | 81 ++++++++++++++++++++++++++++++- 3 files changed, 85 insertions(+), 2 deletions(-) diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv index 50139fa..4cfbf5a 100644 --- a/hardware/src/cachepool_l1_ctrl.sv +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -414,7 +414,8 @@ module cachepool_l1_ctrl : (coal_req_write ? HPDCACHE_REQ_STORE : HPDCACHE_REQ_LOAD); // tid: pack the coalescer scatter info + shared user. l1_req[0].tid = coal_req_valid - ? pack_tid_spatz(coal_req_info.hitmap, coal_req_info.ofsts, + ? pack_tid_spatz(coal_req_addr[2+:LP1NumWordOffsetBits], + coal_req_info.hitmap, coal_req_info.ofsts, coal_meta.user.is_fpu, coal_meta.user.tile_id, coal_meta.user.core_id, coal_req_write, coal_meta.user.req_id) @@ -830,6 +831,7 @@ module cachepool_l1_ctrl endfunction function automatic hpdcache_req_tid_t pack_tid_spatz( + input word_offset_t word_offset, input logic [HitmapW-1:0] hitmap, input logic [OfstsW-1:0] ofsts, input logic is_fpu, @@ -845,6 +847,7 @@ module cachepool_l1_ctrl pack_tid_spatz[CoreIdLsb +: CoreIDWidth] = core_id; pack_tid_spatz[TileIdLsb +: TileIDWidth] = tile_id; pack_tid_spatz[IsFpuPos] = is_fpu; + pack_tid_spatz[WordOffLsb +: LP1NumWordOffsetBits] = word_offset; endfunction endmodule diff --git a/sim/scripts/vsim_tile.tcl b/sim/scripts/vsim_tile.tcl index 8f128fa..5fbc595 100644 --- a/sim/scripts/vsim_tile.tcl +++ b/sim/scripts/vsim_tile.tcl @@ -38,6 +38,7 @@ for {set c 0} {$c < 4} {incr c} { add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group ctrl ${lp1_path}/i_l1_hpdcache/hpdcache_ctrl_i/* + add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group ctrl_pe ${lp1_path}/i_l1_hpdcache/hpdcache_ctrl_i/hpdcache_ctrl_pe_i/* add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group wbuf ${lp1_path}/i_l1_hpdcache/gen_wbuf/hpdcache_wbuf_i/* add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group coalescer ${lp1_path}/i_l1_req_coalescer/* add wave -noupdate -group ${parent_grp} -group tile[$1] -group lp1[$c] -group Internal ${lp1_path}/* diff --git a/software/tests/fmatmul-32b/main.c b/software/tests/fmatmul-32b/main.c index 539ccc4..82e1796 100644 --- a/software/tests/fmatmul-32b/main.c +++ b/software/tests/fmatmul-32b/main.c @@ -19,10 +19,44 @@ #include #include #include +#include // SNRT_CACHELINE_SIZE #include DATAHEADER #include "kernel/fmatmul.c" +// --------------------------------------------------------------------------- +// Private-L1 (LP1): no coherency protection required. Verified 2026-07-13. +// +// The matmul needs none by construction: A and B are read-only shared, and each +// core writes and verifies its OWN rows of C (producer == consumer). +// +// The only cross-core state is `error_arr` (verification bookkeeping): core 0 +// publishes the pointer and every core reads it; each core writes its own slot +// and core 0 reads them all. In principle that wants a release/acquire pair. In +// practice it works unprotected, and we CONFIRMED it rather than assumed it -- +// injecting a deliberate error into core 1's partition of C, with the CMOs +// compiled out, still reports "Core 1 error 1" on core 0. The check is not blind. +// +// Why it works: the kernel streams tens of KB of matrices through each private L1, +// which evicts the small slot cachelines from core 0 long before it re-reads them, +// so its reads miss down to L2 where the peers' write-through values already sit. +// That is a CAPACITY ACCIDENT, not a guarantee. If the bookkeeping ever grows a +// fast path, or the matrices shrink below the L1, core 0 could hit its own stale +// zeros and report a silent PASS. The `#ifdef LP1` blocks below are the correct +// discipline, kept and working -- enable the define to turn them back on. +// +// NOTE the snrt_fence() before verify_matrix is deliberately NOT under LP1. It is +// Snitch/Spatz ordering, not coherence: snrt_cluster_hw_barrier() does not drain +// Spatz, so the scalar verify can otherwise read C before this core's own async +// vse32.v stores have retired. That hazard is real with or without a private L1. +// +// (The bug that actually broke this test was ALIGNMENT, not coherence -- see the +// error_ref comment below.) +// #define LP1 + +#ifdef LP1 +#include +#endif #ifndef KERNEL_SIZE #define KERNEL_SIZE 4 @@ -34,7 +68,43 @@ float *c; // Pointer to per-core error slots; allocated in main by core 0 via snrt_l1alloc. // Placed in .data so the pointer word lives at a fixed shared DRAM address. -int *error_arr __attribute__((section(".data"))); +// +// MUST occupy a whole cacheline. This object sits at the head of .data, and +// gemm_A/B/C_dram follow it with only a float's natural 4-byte alignment. A bare +// 4-byte pointer here therefore starts all three matrices at 4 mod 64: +// +// 80003940 4 error_arr +// 80003944 0x10000 gemm_A_dram <-- 4 mod 64, and the skew propagates +// +// That breaks TWO alignment assumptions at once: +// * 64B cacheline -- adjacent cores' row partitions of C false-share a line. +// * 16B LP1 coalescing window (wordWidth=128b, 4 lanes x 4B) -- Spatz's 4 lanes +// stop fitting in one window, so every vector access straddles two and the +// coalescer splits it in half. cachepool_l1_ctrl.sv's coal_be rebuilds the +// byte-enable from the LANE INDEX, which is only valid when aligned. +// +// Note `aligned(64)` on the pointer alone would NOT fix this: it would start the +// symbol on a boundary but its size is still 4, so gemm_A_dram still lands at +4. +// The padding is what does the work -- it makes the whole slot a multiple of the +// cacheline, so whatever the linker places next starts on a 64B boundary. +// int *error_arr __attribute__((section(".data"))); +// `ptr` is volatile and error_ref has external linkage on purpose: core 0 writes +// the pointer and every other core reads it. If this were `static`, the compiler +// could see that the only store is under `if (cid == 0)` and constant-fold the +// pointer to its initial NULL on every other core. +typedef struct { + int *volatile ptr; + uint8_t _pad[SNRT_CACHELINE_SIZE - sizeof(int *)]; +} error_ref_t; + +error_ref_t error_ref + __attribute__((section(".data"), aligned(SNRT_CACHELINE_SIZE))); + +_Static_assert(sizeof(error_ref_t) == SNRT_CACHELINE_SIZE, + "error_ref must occupy exactly one cacheline, or it will skew the " + "alignment of gemm_A/B/C_dram in .data"); + +#define error_arr (error_ref.ptr) // Verify the matrices int verify_matrix(float *matrix, const float *checksum, @@ -150,6 +220,15 @@ int main() { return -1; } + // NOT inside #ifdef LP1 -- this is not a coherency guard. The kernel wrote C + // with async Spatz vector stores (vse32.v), but verify_matrix reads C back with + // SCALAR loads, and snrt_cluster_hw_barrier() does not drain Spatz. Without + // this fence the verify can read C before this core's own stores have retired. + // The hazard is Snitch/Spatz ordering: it exists with or without a private L1 + // and with or without coherence. No CMO needed -- producer and consumer of C + // are the same core, so its private L1 is self-consistent once ordered. + snrt_fence(); + // Wait for all cores to finish snrt_cluster_hw_barrier(); From 8f87b20f434b219a1d981706d45fa992ff75b8f0 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Tue, 14 Jul 2026 18:23:56 +0200 Subject: [PATCH 31/39] [SW] gemv protection and fix --- Bender.lock | 14 ++--- software/tests/fft-32b/main.c | 18 +++--- software/tests/fft-32b/script/gen_data.py | 14 ++--- software/tests/gemv/main.c | 69 ++++++++++++++++++++--- 4 files changed, 86 insertions(+), 29 deletions(-) diff --git a/Bender.lock b/Bender.lock index 0b95bc1..fdc4672 100644 --- a/Bender.lock +++ b/Bender.lock @@ -42,8 +42,8 @@ packages: - scm - tech_cells_generic common_cells: - revision: 9ca8a7655f741e7dd5736669a20a301325194c28 - version: 1.39.0 + revision: 1281545696eb3fcba50ec5b4275993476a3c710e + version: 1.40.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -56,14 +56,14 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] dram_rtl_sim: - revision: fc831811ac0e1b374814f64bb7a53abd8e6171b4 + revision: null version: null source: - Git: https://github.com/pulp-platform/dram_rtl_sim.git + Path: hardware/deps/dram_rtl_sim dependencies: - axi floo_noc: - revision: f7f81e2c65c231a8fab4cf8a6e6cd2aa3efdcdb6 + revision: a7d46c0aed7475a02de94f888a25495ae74d706f version: null source: Git: https://github.com/pulp-platform/FlooNoC.git @@ -171,8 +171,8 @@ packages: - riscv-dbg - tech_cells_generic tech_cells_generic: - revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf - version: 0.2.13 + revision: 3a3de73632a06826b1bd9c65a0a2e92b32016845 + version: 0.2.14 source: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: diff --git a/software/tests/fft-32b/main.c b/software/tests/fft-32b/main.c index 8c9d3f7..b5c0ea6 100644 --- a/software/tests/fft-32b/main.c +++ b/software/tests/fft-32b/main.c @@ -147,8 +147,9 @@ int main() { // Consumer/acquire: this stage reads `src`, which for stage > 0 was // written by (possibly) other cores in the previous stage. Drop stale // private lines so the reads miss down to the fresh copy in shared L2. + lp1_wt_flush(); lp1_inval(); - snrt_fence(); + // snrt_fence(); #endif fft_p1(src_p1, buf_p1, twi_p1, NFFT, NTWI_P1, cid, active_cores, i, len); #ifdef LP1 @@ -157,7 +158,7 @@ int main() { // barrier. sfence.vma first: the Spatz vector stores are async and must // retire into the write buffer before we drain it. snrt_fence_spatz(); - snrt_fence(); + // snrt_fence(); lp1_wt_flush(); #endif // each round will use half the twiddle than previous round @@ -173,13 +174,13 @@ int main() { } if (cid < active_cores) { -#ifdef LP1 +// #ifdef LP1 // Consumer/acquire: phase 2 reads samples/buffer_dram + cid*NFFTpc, a // DIFFERENT partition than phase 1 used, produced by other cores in the // last phase-1 stage. Drop stale private lines before reading. - lp1_inval(); - snrt_fence(); -#endif + // lp1_inval(); + // snrt_fence(); +// #endif // Fall back into the single-core case // Each core just do a FFT on (NFFT >> stage_in_P1) data // Phase-2 interior needs no CMOs: its s<->buf swaps stay within this @@ -194,7 +195,7 @@ int main() { #ifdef LP1 // Producer/release: publish out[] down to L2 for core-0 verification. snrt_fence_spatz(); - snrt_fence(); + // snrt_fence(); lp1_wt_flush(); #endif } @@ -217,8 +218,9 @@ int main() { #ifdef LP1 // Consumer/acquire: drop core-0's stale private lines so the checks read // the freshly-produced out[] (now in L2/DRAM after the flush above). + lp1_wt_flush(); lp1_inval(); - snrt_fence(); + // snrt_fence(); #endif // Verify the real part diff --git a/software/tests/fft-32b/script/gen_data.py b/software/tests/fft-32b/script/gen_data.py index 6acd28a..325d9cd 100644 --- a/software/tests/fft-32b/script/gen_data.py +++ b/software/tests/fft-32b/script/gen_data.py @@ -293,22 +293,22 @@ def main(): emit_str += 'float out[{}]'.format(2 * NFFT) + ' __attribute__((section(".data"))) = { [0 ... ' + str(2 * NFFT - 1) + '] = 0 };\n' # L2 Data - emit_str += 'static float samples_dram[{}]'.format(2 * NFFT) + ' __attribute__((section(".data"))) = {' + ', '.join( + emit_str += 'static float samples_dram[{}]'.format(2 * NFFT) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( map(str, samples_reim.astype(dtype).tolist())) + '};\n' emit_str += 'static float buffer_dram[{}]'.format(2 * NFFT) + ' __attribute__((section(".data"))) = {' + ', '.join( map(str, buffer_dram.astype(dtype).tolist())) + '};\n' if CORES == 1: - emit_str += 'static float twiddle_dram[{}]'.format(2 * N_TWID_P2) + ' __attribute__((section(".data"))) = {' + ', '.join( + emit_str += 'static float twiddle_dram[{}]'.format(2 * N_TWID_P2) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( map(str, twiddle_vec_reim.astype(dtype).tolist())) + '};\n' else: - emit_str += 'static float twiddle_dram[{}]'.format(2 * (CORES*N_TWID_P2 + N_TWID_P1)) + ' __attribute__((section(".data"))) = {' + ', '.join( + emit_str += 'static float twiddle_dram[{}]'.format(2 * (CORES*N_TWID_P2 + N_TWID_P1)) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( map(str, twiddle_vec_reim.astype(dtype).tolist())) + '};\n' - emit_str += 'static uint16_t store_idx_dram[{}]'.format(int(np.log2(NFFTpc / 2) * NFFTpc / 2)) + ' __attribute__((section(".data"))) = {' + ', '.join( + emit_str += 'static uint16_t store_idx_dram[{}]'.format(int(np.log2(NFFTpc / 2) * NFFTpc / 2)) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( map(str, np.array(store_delta).astype(idx_dtype).tolist())) + '};\n' emit_str += 'static uint32_t coffset_dram[{}]'.format(int( - CORES)) + ' __attribute__((section(".data"))) = {' + ', '.join(map(str, core_offsets)) + '};\n' + CORES)) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join(map(str, core_offsets)) + '};\n' emit_str += 'static float gold_out_dram[{}]'.format( - 2 * NFFT) + ' __attribute__((section(".data"))) = {' + ', '.join(map(str, gold_out_s.astype(dtype).tolist())) + '};\n' + 2 * NFFT) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join(map(str, gold_out_s.astype(dtype).tolist())) + '};\n' file_path = pathlib.Path(__file__).parent.parent / 'data' file = file_path / ('data_' + str(NFFT) + "_" + str(CORES) + ".h") @@ -317,4 +317,4 @@ def main(): if __name__ == '__main__': - main() + main() \ No newline at end of file diff --git a/software/tests/gemv/main.c b/software/tests/gemv/main.c index 31baf21..d15a82a 100644 --- a/software/tests/gemv/main.c +++ b/software/tests/gemv/main.c @@ -20,10 +20,32 @@ #include #include #include +#include +#include // SNRT_CACHELINE_SIZE #include "kernel/gemv.c" #include DATAHEADER +// --------------------------------------------------------------------------- +// Private-L1 (LP1): this kernel DOES need coherency protection. +// +// Unlike fmatmul-32b (where each core verifies its own rows, so producer == +// consumer and no CMO is needed), here core `cid` writes result[cid*m_core ..) +// but CORE 0 VERIFIES ALL OF THEM. Producer != consumer, so the shared `result` +// buffer needs a full release/acquire pair around the barrier: +// +// producer (every core): snrt_fence(); lp1_wt_flush(); +// consumer (core 0): lp1_inval(); snrt_fence(); +// +// The acquire half is not optional cosmetics. m_core = M/num_cores is only 4 +// floats (16 B) for M=128 on 32 cores, so FOUR cores share one 64 B cacheline of +// `result`. Write-through keeps L2 correct (per-word strobes), but core 0's own +// cached copy of that line still carries cores 1-3's stale words, and nothing +// updates it. It must be invalidated before core 0 reads. +// +// A and B are read-only shared -- no protection needed for them. +// --------------------------------------------------------------------------- + #if (PREC == 64) #define T double #elif (PREC == 32) @@ -36,6 +58,19 @@ #define SNRT_NFPU_PER_CORE 4 +// The kernel output MUST NOT alias the golden reference. +// +// The original code did `result = gemv_result`, so the kernel overwrote the +// reference and fp_check(&result[j], &gemv_result[j]) then compared the array +// with ITSELF: x - x == 0, always below threshold. The test could not fail -- +// it would have reported success with the cache off and garbage in memory. +// +// Sized from the golden array so it tracks M with no extra macro. Explicitly +// cacheline-aligned, and a whole number of cachelines (M is always a multiple of +// 16 floats here), so it cannot skew the alignment of whatever the linker places +// next -- see fmatmul-32b/main.c for the hang that alignment skew caused. +static T gemv_out[sizeof(gemv_result) / sizeof(T)] + __attribute__((section(".pdcp_src"), aligned(SNRT_CACHELINE_SIZE))); static inline int fp_check(const T *a, const T *b) { const T threshold = 0.001; @@ -62,17 +97,20 @@ int main() { // We use all-private mode for this kernel l1d_xbar_config(offset); - l1d_part(4); + // l1d_part(4); - // Reset timer - unsigned int timer_start, timer_end, timer, timer_iter1; + // Reset timer. `timer` is read by the `timer_temp < timer` test on the very + // first iteration, so it must start at max, not at whatever was on the stack. + unsigned int timer_start, timer_end, timer_iter1; + unsigned int timer = (unsigned int)-1; // Unroll in M direction? int unroll_m = 0; a = gemv_A_dram; b = gemv_B_dram; - result = gemv_result; + // Output buffer, distinct from the golden gemv_result -- see gemv_out above. + result = gemv_out; // Calculate internal pointers T *a_core = a + m_core * cid; @@ -123,17 +161,34 @@ int main() { // All cores flush before first-iteration verification if (i == 0) { + // Producer / release. snrt_fence() drains this core's outstanding Spatz + // vector stores (snrt_cluster_hw_barrier() does NOT -- it is just a scalar + // load by Snitch, and Spatz is decoupled); lp1_wt_flush() then drains the + // write-through buffer so the values actually reach L2. + snrt_fence(); + lp1_wt_flush(); + l1d_cluster_flush(); + + // Consumer / acquire. Core 0 is about to read EVERY core's slice of + // `result`, so it must drop the copies in its own private L1 -- the release + // above pushed the producers' values to L2 but told core 0 nothing. Without + // this, core 0 can read stale words out of a line it false-shares with cores + // 1..3 (m_core is 16 B for M=128 on 32 cores; a line is 64 B). + // lp1_inval() drives a per-core CMO slot with no internal barrier, so it is + // safe to call from every core. + lp1_inval(); + snrt_fence(); } if (cid == 0) { if (i == 0) { for (uint32_t j = 0; j < gemv_l.M; j++) { if (fp_check(&result[j], &gemv_result[j])) { - printf("Error: ID: %i Calc", i); - snrt_printf_float(result[i]); + printf("Error: idx %u Calc:", j); + snrt_printf_float(result[j]); printf(",Exp:"); - snrt_printf_float(gemv_result[i]); + snrt_printf_float(gemv_result[j]); printf("\n"); } } From 3845add6a963f457e7a7a5a6fd6e17307696356a Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Wed, 15 Jul 2026 17:18:29 +0200 Subject: [PATCH 32/39] [SW] fmamtul data alignment, def flag clean up for multiple kernels --- software/tests/fdotp-32b/main.c | 13 +-- software/tests/fmatmul-32b/main.c | 79 +------------------ software/tests/fmatmul-32b/script/gen_data.py | 11 ++- software/tests/multi-spin-lock/main.c | 6 -- 4 files changed, 13 insertions(+), 96 deletions(-) diff --git a/software/tests/fdotp-32b/main.c b/software/tests/fdotp-32b/main.c index 707740f..73147cf 100644 --- a/software/tests/fdotp-32b/main.c +++ b/software/tests/fdotp-32b/main.c @@ -31,7 +31,7 @@ // cached (stale) copy of a peer's partial and the reduction is wrong. The // existing barriers provide the ordering; the CMOs provide the visibility. // Comment out to observe the staleness failure (discriminating check). -#define LP1 +// #define LP1 int main() { const uint32_t num_cores = snrt_cluster_core_num(); @@ -137,12 +137,10 @@ int main() { // Make sure spatz has finished writing snrt_fence_spatz(); -#ifdef LP1 // Producer: drain the write-through buffer so result[cid] reaches L2 before // the reducers read it. Fence must precede the flush. snrt_fence(); lp1_wt_flush(); -#endif // Wait for all cores to finish snrt_cluster_hw_barrier(); @@ -162,33 +160,30 @@ int main() { // Level 1: lead core of each group accumulates its group if (cid % red_group == 0) { -#ifdef LP1 // Consumer: drop stale private-L1 copies of result[] (from a previous // measure_iter pass) so the peer partials are refetched fresh from L2. // snrt_fence(); // lp1_wt_flush(); lp1_inval(); snrt_fence(); -#endif + for (uint32_t i = 1; i < red_group && (cid + i) < num_cores; ++i) acc += result[cid + i]; result[cid] = acc; -#ifdef LP1 + // Producer: expose this group's sum to core 0's level-2 pass. snrt_fence(); lp1_wt_flush(); -#endif } snrt_cluster_hw_barrier(); // Level 2: core 0 sums all group results if (cid == 0) { -#ifdef LP1 // Consumer: refetch the group leads' sums fresh from L2. lp1_inval(); snrt_fence(); -#endif + for (uint32_t g = red_group; g < num_cores; g += red_group) acc += result[g]; result[0] = acc; diff --git a/software/tests/fmatmul-32b/main.c b/software/tests/fmatmul-32b/main.c index 82e1796..ac38da8 100644 --- a/software/tests/fmatmul-32b/main.c +++ b/software/tests/fmatmul-32b/main.c @@ -24,39 +24,7 @@ #include DATAHEADER #include "kernel/fmatmul.c" -// --------------------------------------------------------------------------- -// Private-L1 (LP1): no coherency protection required. Verified 2026-07-13. -// -// The matmul needs none by construction: A and B are read-only shared, and each -// core writes and verifies its OWN rows of C (producer == consumer). -// -// The only cross-core state is `error_arr` (verification bookkeeping): core 0 -// publishes the pointer and every core reads it; each core writes its own slot -// and core 0 reads them all. In principle that wants a release/acquire pair. In -// practice it works unprotected, and we CONFIRMED it rather than assumed it -- -// injecting a deliberate error into core 1's partition of C, with the CMOs -// compiled out, still reports "Core 1 error 1" on core 0. The check is not blind. -// -// Why it works: the kernel streams tens of KB of matrices through each private L1, -// which evicts the small slot cachelines from core 0 long before it re-reads them, -// so its reads miss down to L2 where the peers' write-through values already sit. -// That is a CAPACITY ACCIDENT, not a guarantee. If the bookkeeping ever grows a -// fast path, or the matrices shrink below the L1, core 0 could hit its own stale -// zeros and report a silent PASS. The `#ifdef LP1` blocks below are the correct -// discipline, kept and working -- enable the define to turn them back on. -// -// NOTE the snrt_fence() before verify_matrix is deliberately NOT under LP1. It is -// Snitch/Spatz ordering, not coherence: snrt_cluster_hw_barrier() does not drain -// Spatz, so the scalar verify can otherwise read C before this core's own async -// vse32.v stores have retired. That hazard is real with or without a private L1. -// -// (The bug that actually broke this test was ALIGNMENT, not coherence -- see the -// error_ref comment below.) -// #define LP1 - -#ifdef LP1 #include -#endif #ifndef KERNEL_SIZE #define KERNEL_SIZE 4 @@ -66,45 +34,7 @@ float *a; float *b; float *c; -// Pointer to per-core error slots; allocated in main by core 0 via snrt_l1alloc. -// Placed in .data so the pointer word lives at a fixed shared DRAM address. -// -// MUST occupy a whole cacheline. This object sits at the head of .data, and -// gemm_A/B/C_dram follow it with only a float's natural 4-byte alignment. A bare -// 4-byte pointer here therefore starts all three matrices at 4 mod 64: -// -// 80003940 4 error_arr -// 80003944 0x10000 gemm_A_dram <-- 4 mod 64, and the skew propagates -// -// That breaks TWO alignment assumptions at once: -// * 64B cacheline -- adjacent cores' row partitions of C false-share a line. -// * 16B LP1 coalescing window (wordWidth=128b, 4 lanes x 4B) -- Spatz's 4 lanes -// stop fitting in one window, so every vector access straddles two and the -// coalescer splits it in half. cachepool_l1_ctrl.sv's coal_be rebuilds the -// byte-enable from the LANE INDEX, which is only valid when aligned. -// -// Note `aligned(64)` on the pointer alone would NOT fix this: it would start the -// symbol on a boundary but its size is still 4, so gemm_A_dram still lands at +4. -// The padding is what does the work -- it makes the whole slot a multiple of the -// cacheline, so whatever the linker places next starts on a 64B boundary. -// int *error_arr __attribute__((section(".data"))); -// `ptr` is volatile and error_ref has external linkage on purpose: core 0 writes -// the pointer and every other core reads it. If this were `static`, the compiler -// could see that the only store is under `if (cid == 0)` and constant-fold the -// pointer to its initial NULL on every other core. -typedef struct { - int *volatile ptr; - uint8_t _pad[SNRT_CACHELINE_SIZE - sizeof(int *)]; -} error_ref_t; - -error_ref_t error_ref - __attribute__((section(".data"), aligned(SNRT_CACHELINE_SIZE))); - -_Static_assert(sizeof(error_ref_t) == SNRT_CACHELINE_SIZE, - "error_ref must occupy exactly one cacheline, or it will skew the " - "alignment of gemm_A/B/C_dram in .data"); - -#define error_arr (error_ref.ptr) +int *error_arr __attribute__((section(".data"))); // Verify the matrices int verify_matrix(float *matrix, const float *checksum, @@ -220,13 +150,6 @@ int main() { return -1; } - // NOT inside #ifdef LP1 -- this is not a coherency guard. The kernel wrote C - // with async Spatz vector stores (vse32.v), but verify_matrix reads C back with - // SCALAR loads, and snrt_cluster_hw_barrier() does not drain Spatz. Without - // this fence the verify can read C before this core's own stores have retired. - // The hazard is Snitch/Spatz ordering: it exists with or without a private L1 - // and with or without coherence. No CMO needed -- producer and consumer of C - // are the same core, so its private L1 is self-consistent once ordered. snrt_fence(); // Wait for all cores to finish diff --git a/software/tests/fmatmul-32b/script/gen_data.py b/software/tests/fmatmul-32b/script/gen_data.py index 42ace34..0adab98 100755 --- a/software/tests/fmatmul-32b/script/gen_data.py +++ b/software/tests/fmatmul-32b/script/gen_data.py @@ -146,19 +146,24 @@ def emit_GEMM_layer(name="gemm", **kwargs): ctypes = {"64": "double", "32": "float", "16": "__fp16", "8": "char"} dtype = ctypes[str(kwargs["prec"])] + # aligned(64): force each matrix onto a cacheline boundary so it is + # independent of whatever the linker places before it in .data. Spatz's LP1 + # accesses assume both the 64B cacheline (false-sharing of C row partitions) + # and the 16B coalescing window (wordWidth=128b, 4 lanes x 4B) are aligned; a + # 4-byte-natural start would skew both. This is why fmatmul-32b/main.c if dtype != "char": layer_str += ( - f'static {dtype} {name}_A_dram [{m}*{k}] __attribute__((section(".data"))) = ' + f'static {dtype} {name}_A_dram [{m}*{k}] __attribute__((section(".data"), aligned(64))) = ' + array_to_cstr(mat_A) + ";\n\n\n" ) layer_str += ( - f'static {dtype} {name}_B_dram [{k}*{n}] __attribute__((section(".data"))) = ' + f'static {dtype} {name}_B_dram [{k}*{n}] __attribute__((section(".data"), aligned(64))) = ' + array_to_cstr(mat_B) + ";\n\n\n" ) layer_str += ( - f'static {dtype} {name}_C_dram [{m}*{n}] __attribute__((section(".data"))) = ' + f'static {dtype} {name}_C_dram [{m}*{n}] __attribute__((section(".data"), aligned(64))) = ' + array_to_cstr(mat_C) + ";\n\n\n" ) diff --git a/software/tests/multi-spin-lock/main.c b/software/tests/multi-spin-lock/main.c index 544b1ad..62ba7e5 100644 --- a/software/tests/multi-spin-lock/main.c +++ b/software/tests/multi-spin-lock/main.c @@ -54,8 +54,6 @@ // Critical-section entries per core. >1 is what exposes the staleness hazard. #define REPS 16 -#define LP1 - static volatile uint32_t result __attribute__((section(".data"))); spinlock_t lock; @@ -70,20 +68,16 @@ int main() { for (unsigned int r = 0; r < REPS; r++) { spin_lock(&lock, 20); -#ifdef LP1 // Acquire side: drop stale cached copies so the read of `result` is fresh. lp1_inval(); snrt_fence(); -#endif result += cid; -#ifdef LP1 // Release side: drain the write-through buffer so this update reaches L2 // before the lock is handed to the next core. Fence must precede the flush. snrt_fence(); lp1_wt_flush(); -#endif spin_unlock(&lock, 20); } From 371145379e7c0c42de1e2437eeadaf1f7dde98a3 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Fri, 17 Jul 2026 23:29:27 +0200 Subject: [PATCH 33/39] [HW] private L1 byte-enable fix --- Bender.yml | 2 +- hardware/src/cachepool_l1_ctrl.sv | 35 +++++----- software/snRuntime/include/lp1cache.h | 4 +- software/snRuntime/src/lp1cache.c | 4 +- software/tests/fft-32b/main.c | 80 +++++------------------ software/tests/fft-32b/script/gen_data.py | 4 +- 6 files changed, 46 insertions(+), 83 deletions(-) diff --git a/Bender.yml b/Bender.yml index ecb880c..fa98312 100644 --- a/Bender.yml +++ b/Bender.yml @@ -14,7 +14,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.7.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 } # Insitu-Cache: { git: "https://github.com/pulp-platform/Insitu-Cache.git", rev: zexin/cachepool_dev } - Insitu-Cache: { git: "https://github.com/HHT1228/Insitu-Cache.git", rev: hohung-multi-tile } + Insitu-Cache: { git: "https://github.com/HHT1228/Insitu-Cache.git", rev: hohung/cachepool/wt-l1 } hpdcache: { git: "https://github.com/HHT1228/cv-hpdcache.git", rev: cachepool/no_coherence } dram_rtl_sim: { git: "https://github.com/pulp-platform/dram_rtl_sim.git", rev: cachepool } floo_noc: { git: "https://github.com/pulp-platform/FlooNoC.git", rev: main } diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv index 4cfbf5a..f670960 100644 --- a/hardware/src/cachepool_l1_ctrl.sv +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -2,7 +2,7 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // -// Author: Ho Tin Hung, ETH Zurich +// Author: Ho Tin Hung, ETH Zurich // // Per-core private L1 data cache controller. // @@ -382,26 +382,28 @@ module cachepool_l1_ctrl end end - // BE for the coalesced (wide) request. - // NOTE: preserved hitmap-shift scheme (each hit lane marks its lane-width bytes - // at its lane index) rather than the coalescer's wmask, per design intent. - // Revisit with owner before switching to coal_req_wmask. - logic [WordBytes-1:0] coal_be; - always_comb begin : gen_coal_be - coal_be = '0; - for (int unsigned id = 0; id < NrLP1CoalInputs; id++) begin - if (coal_req_info.hitmap[id]) begin - coal_be |= ({LaneBytes{1'b1}} << (id * LaneBytes)); - end - end - end + // BE for the coalesced (wide) request: use the coalescer's wmask + // logic [WordBytes-1:0] coal_be; + // always_comb begin : gen_coal_be + // coal_be = '0; + // for (int unsigned id = 0; id < NrLP1CoalInputs; id++) begin + // if (coal_req_info.hitmap[id]) begin + // coal_be |= ({LaneBytes{1'b1}} << (id * LaneBytes)); + // end + // end + // end always_comb begin : gen_l1_req_spatz l1_req[0] = '0; l1_req[0].addr_offset = coal_req_addr[HPDcacheCfg.reqOffsetWidth-1:0]; l1_req[0].addr_tag = coal_req_addr[HPDcacheCfg.reqOffsetWidth +: HPDcacheCfg.tagWidth]; l1_req[0].wdata = coal_req_wdata; - l1_req[0].be = coal_be; + // Stores take the coalescer's wmask (correct slot + correct byte granularity). + // Reads keep the old hitmap-shift value: HPDcache only consumes `be` on the + // store/AMO/wbuf/uncached paths, and the coalescer leaves wmask = '0 on reads, + // so this avoids changing read behaviour while fixing the store path. + l1_req[0].be = coal_req_wmask; + // l1_req[0].be = coal_req_write ? coal_req_wmask : coal_be; l1_req[0].size = hpdcache_req_size_t'($clog2(coalescedDataWidth/8)); l1_req[0].sid = hpdcache_req_sid_t'(0); // Spatz l1_req[0].need_rsp = 1'b1; @@ -429,8 +431,9 @@ module cachepool_l1_ctrl // HPDcache requester 1 (Snitch) // /////////////////////////////////// // Snitch writes its narrow word into the wide cache word at its byte position. + // assign sn_byte_pos = l1_cache_req[SnitchPort].addr_offset % WordBytes; logic [$clog2(WordBytes)-1:0] sn_byte_pos; - assign sn_byte_pos = l1_cache_req[SnitchPort].addr_offset % WordBytes; + assign sn_byte_pos = ($clog2(WordBytes))'(cache_req_word_offset[SnitchPort] * LaneBytes); always_comb begin : gen_l1_req_snitch l1_req[1] = l1_cache_req[SnitchPort]; diff --git a/software/snRuntime/include/lp1cache.h b/software/snRuntime/include/lp1cache.h index 82be231..b29fbf0 100644 --- a/software/snRuntime/include/lp1cache.h +++ b/software/snRuntime/include/lp1cache.h @@ -1,8 +1,10 @@ -// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright 2026 ETH Zurich and University of Bologna. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +// Author: Ho Tin Hung, ETH Zurich + // Private-L1 (LP1) cache control. // // LP1 is the per-core private HPDcache (write-through, no coherence), distinct diff --git a/software/snRuntime/src/lp1cache.c b/software/snRuntime/src/lp1cache.c index 3f5bfcc..a25f069 100644 --- a/software/snRuntime/src/lp1cache.c +++ b/software/snRuntime/src/lp1cache.c @@ -1,8 +1,10 @@ -// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright 2026 ETH Zurich and University of Bologna. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 +// Author: Ho Tin Hung, ETH Zurich + #include #include diff --git a/software/tests/fft-32b/main.c b/software/tests/fft-32b/main.c index b5c0ea6..7984fcf 100644 --- a/software/tests/fft-32b/main.c +++ b/software/tests/fft-32b/main.c @@ -26,34 +26,8 @@ #include DATAHEADER #include "kernel/fft.c" -// --------------------------------------------------------------------------- -// Private-L1 (LP1) coherency protection. -// -// LP1 is the per-core, write-through, NON-coherent private cache; Snitch scalar -// AND Spatz vector accesses both go through it. Coherency between cores is -// re-established purely in software, at every cross-core producer->consumer -// handoff, with the two CMO+fence sequences below: -// -// producer/release: snrt_fence_spatz(); snrt_fence(); lp1_wt_flush(); -// drain this core's write-through buffer down to shared L2 so peers can see -// it. sfence.vma is mandatory first -- the FFT stores are async Spatz -// vector stores and must retire into the write buffer before we drain it. -// -// consumer/acquire: lp1_inval(); snrt_fence(); -// drop this core's stale private lines so the next reads miss down to the -// fresh copy in shared L2. -// -// The cluster barrier gives ordering only, not visibility, so BOTH sides are -// required. CMOs are issued at stage / phase granularity, never per vector -// load: a whole-cache INVAL between in-flight Spatz stores races the -// outstanding stores and corrupts data. -// -// Comment out `#define LP1` to fall back to the (all-wrong) unprotected build. -#define LP1 - -#ifdef LP1 #include -#endif + static inline int fp_check(const float a, const float b) { const float threshold = 0.01f; @@ -74,7 +48,7 @@ static inline int fp_check(const float a, const float b) { // 1024 -> 64 int main() { - const int measure_iter = 1; + const int measure_iter = 2; // twiddle layout: [re_p1, im_p1, re_p2, im_p2] const uint32_t num_cores = snrt_cluster_core_num(); @@ -143,24 +117,18 @@ int main() { for (uint32_t i = 0; i < log2_nfft1; i ++) { if (cid < active_cores) { -#ifdef LP1 - // Consumer/acquire: this stage reads `src`, which for stage > 0 was - // written by (possibly) other cores in the previous stage. Drop stale - // private lines so the reads miss down to the fresh copy in shared L2. - lp1_wt_flush(); + + // Consumer/acquire: Drop stale private lines + // so the reads miss down to the fresh copy in shared L2. lp1_inval(); - // snrt_fence(); -#endif + lp1_wt_flush(); + fft_p1(src_p1, buf_p1, twi_p1, NFFT, NTWI_P1, cid, active_cores, i, len); -#ifdef LP1 + // Producer/release: drain this stage's write-through output down to L2 - // so the next stage's consumers (on other cores) see it after the - // barrier. sfence.vma first: the Spatz vector stores are async and must - // retire into the write buffer before we drain it. - snrt_fence_spatz(); - // snrt_fence(); + snrt_fence(); lp1_wt_flush(); -#endif + // each round will use half the twiddle than previous round // the first round needs re/im NFFT/2 twiddles src_p1 = (i & 1) ? samples_dram : buffer_dram; @@ -174,13 +142,6 @@ int main() { } if (cid < active_cores) { -// #ifdef LP1 - // Consumer/acquire: phase 2 reads samples/buffer_dram + cid*NFFTpc, a - // DIFFERENT partition than phase 1 used, produced by other cores in the - // last phase-1 stage. Drop stale private lines before reading. - // lp1_inval(); - // snrt_fence(); -// #endif // Fall back into the single-core case // Each core just do a FFT on (NFFT >> stage_in_P1) data // Phase-2 interior needs no CMOs: its s<->buf swaps stay within this @@ -192,12 +153,11 @@ int main() { fft_p2(src_p2, buf_p2, twi_p2, out_p2, store_idx_dram, (NFFT>>log2_nfft1), NFFT, log2_nfft2, stride, log2_nfft1, NTWI_P2); } -#ifdef LP1 - // Producer/release: publish out[] down to L2 for core-0 verification. - snrt_fence_spatz(); - // snrt_fence(); + + // Producer/release: flush out[] down to L2 for core-0 verification. + snrt_fence(); lp1_wt_flush(); -#endif + } // Wait for all cores to finish fft snrt_cluster_hw_barrier(); @@ -212,17 +172,13 @@ int main() { stop_kernel(); if ((iter == 0) && CHECK) { + // Consumer/acquire: drop core-0's stale private lines + lp1_inval(); + snrt_fence(); + l1d_flush(); l1d_wait(); -#ifdef LP1 - // Consumer/acquire: drop core-0's stale private lines so the checks read - // the freshly-produced out[] (now in L2/DRAM after the flush above). - lp1_wt_flush(); - lp1_inval(); - // snrt_fence(); -#endif - // Verify the real part for (unsigned int i = 0; i < NFFT; i++) { if (fp_check(out[i], gold_out_dram[2 * i])) { diff --git a/software/tests/fft-32b/script/gen_data.py b/software/tests/fft-32b/script/gen_data.py index 325d9cd..02114b2 100644 --- a/software/tests/fft-32b/script/gen_data.py +++ b/software/tests/fft-32b/script/gen_data.py @@ -290,12 +290,12 @@ def main(): emit_str += 'static uint32_t active_cores = {};\n\n'.format(CORES) # L1 Data - emit_str += 'float out[{}]'.format(2 * NFFT) + ' __attribute__((section(".data"))) = { [0 ... ' + str(2 * NFFT - 1) + '] = 0 };\n' + emit_str += 'float out[{}]'.format(2 * NFFT) + ' __attribute__((section(".pdcp_src"))) = { [0 ... ' + str(2 * NFFT - 1) + '] = 0 };\n' # L2 Data emit_str += 'static float samples_dram[{}]'.format(2 * NFFT) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( map(str, samples_reim.astype(dtype).tolist())) + '};\n' - emit_str += 'static float buffer_dram[{}]'.format(2 * NFFT) + ' __attribute__((section(".data"))) = {' + ', '.join( + emit_str += 'static float buffer_dram[{}]'.format(2 * NFFT) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( map(str, buffer_dram.astype(dtype).tolist())) + '};\n' if CORES == 1: emit_str += 'static float twiddle_dram[{}]'.format(2 * N_TWID_P2) + ' __attribute__((section(".pdcp_src"))) = {' + ', '.join( From 546a399a36ae8d88504b05de28fd04b4cb062d01 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Mon, 20 Jul 2026 17:40:50 +0200 Subject: [PATCH 34/39] Code clean-up and composed a note --- Bender.local | 3 +- WTL1_note.md | 286 +++++++++++++ figs/hpdcache_pe_labled.jpg | Bin 0 -> 942162 bytes figs/performance_16g_tiny.jpg | Bin 0 -> 156684 bytes hardware/src/cachepool_group.sv | 55 +-- hardware/src/cachepool_group_noc_wrapper.sv | 7 +- hardware/src/cachepool_l1_ctrl.sv | 32 +- hardware/src/cachepool_tile.sv | 447 +------------------- hardware/src/spatz_cache_amo.sv | 26 +- software/tests/benchmark/mcs_lock.c | 37 +- software/tests/gemv/main.c | 33 +- 11 files changed, 328 insertions(+), 598 deletions(-) create mode 100644 WTL1_note.md create mode 100644 figs/hpdcache_pe_labled.jpg create mode 100644 figs/performance_16g_tiny.jpg diff --git a/Bender.local b/Bender.local index 2ff8279..e99a4c0 100644 --- a/Bender.local +++ b/Bender.local @@ -5,6 +5,5 @@ overrides: axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 } - Insitu-Cache: { path: "../Insitu-Cache" } - hpdcache: { path: "../cv-hpdcache" } + diff --git a/WTL1_note.md b/WTL1_note.md new file mode 100644 index 0000000..98c8afe --- /dev/null +++ b/WTL1_note.md @@ -0,0 +1,286 @@ +# CachePool — Private-L1 + AMO Work Sign-Off + +This note summarises the work done on the `hohung-multi-group` branch: adding a +per-core **private L1 data cache** in front of the existing shared distributed +cache (now the L2), adding **AMO** support through that hierarchy, and the +**runtime + kernel-side software** needed to keep data coherent across cores in +the absence of hardware coherence. + +The system stays a Snitch–Spatz many-core; the memory hierarchy is now: + +``` +Snitch scalar ─┐ + ├─▶ per-core private L1 (HPDcache, write-through) ─▶ shared distributed L2 (InSitu) ─▶ DRAMSys +Spatz lanes ───┘ +``` + +--- + +## Naming conventions + +The **existing shared-cache naming was left +untouched** — modules, signals, and files that referred to the shared +distributed cache as "L1" still say `l1` (e.g. `l1cache.c`, `l1d_*`), even though +that cache now sits *behind* the new private cache. + +The new **private** per-core cache is consistently named after **LP1** (`lp1`): +`lp1cache.{c,h}`, `lp1_inval`/`lp1_wt_flush`, the `lp1_cmo_*` peripheral +registers, and the `lp1_*` tests. + +The **only exception** is `hardware/src/cachepool_l1_ctrl.sv`, the private-cache +controller. There **"L1" means the private cache** it implements and +**"L2" means the shared cache** downstream (`l2_req_o`/`l2_rsp_i`). + +--- + +## Note on Bender + +Two dependencies in `Bender.yml` currently point at **my fork repos, not +the `pulp-platform` versions**: + +- **Insitu-Cache** → `github.com/HHT1228/Insitu-Cache.git` (rev + `hohung/cachepool/wt-l1`), in place of the commented-out + `pulp-platform/Insitu-Cache`. +- **hpdcache** → `github.com/HHT1228/cv-hpdcache.git` (rev + `cachepool/no_coherence`). + +Both forks carry changes this work depends on (the coalescer moved into the L1; +the write-through / fine-tuned HPDcache configuration). + +--- + +## Regenerating peripheral registers on a core-count change + +The per-core CMO injector has **one register slot per core** (`NumLp1CmoRegs`), +baked into `hardware/cachepool_peripheral/cachepool_peripheral_reg_{pkg,top}.sv` +and `software/snRuntime/include/cachepool_peripheral.h`. **If the core count +changes, regenerate these:** + +```bash +make update-periph-reg config= +``` + +This is crucial for the CMO calls to work. If `NumLp1CmoRegs < num_cores`, any +core with `cid >= NumLp1CmoRegs` has no decoded slot: its `LP1_CMO_STATUS` never +clears, so every `lp1_*` call on that core **spins forever** → cluster-barrier +deadlock. + +--- + +## 1. Hardware implementation + +### Private L1 data cache (`hardware/src/cachepool_l1_ctrl.sv`) + +A new per-core controller wraps one **HPDcache** (write-through, **no hardware +coherence**) as a private L1. Both Snitch scalar traffic and the Spatz vector +lanes pass through it. The controller: + +- **Coalesces the Spatz lanes** into one wide HPDcache request (`sid=0`) via the + vendored InSitu `par_coalescer`, and translates the single Snitch port into a + second HPDcache request (`sid=1`). The former per-tile Spatz coalescer/bypass + stages were removed from the shared cache and **moved into this L1**. +- **Packs all metadata that must survive the HPDcache round-trip into `tid`**, + and scatters the response back to the originating lanes. +- **Merges** HPDcache's separate mem read/write channels into a single + downstream TCDM request/response pair (`l2_req_o`/`l2_rsp_i`) that feeds the + shared L2 through the existing `tcdm_cache_interco`. +- Because L1↔L2 traffic is **cacheline-granular**, the shared L2 controller was + simplified to a single cacheline-wide core port (`WordWidth = CacheLineWidth`), + and the tile bank wiring was updated to match. + + + +### AMO support (`hardware/src/spatz_cache_amo.sv`, `cachepool_l1_ctrl.sv`) + +Atomic memory operations are supported end-to-end through the new hierarchy: + +- The L1 controller **maps Spatz/Snitch AMO ops to HPDcache uncacheable AMO ops** + (`AMOSwap/Add/And/Or/Xor/Max/Min/Maxu/Minu` and `LR/SC`) on the request path, + and re-derives the RISC-V AMO op from HPDcache's `mem` atomic encoding on the + L1→L2 path. AMOs are never coalesced and carry the hit lane's op. +- HPDcache forwards uncacheable reqeust directly to the lower hierarchy without + touching its local data. +- `spatz_cache_amo.sv` is the RMW shim in front of the shared SRAMs that executes + the atomics (LR/SC reservations at `DataWidth` granularity). +- AMOs on the cacheable path flow through HPDcache in phase 1; the Snitch AMO + path is marked uncacheable at the L1 requester. + +### Per-core CMO injector (HW side of the software CMO API) + +To let software manage coherence explicitly, each core gets a **CMO (Cache +Management Operation) injector** on HPDcache requester port 2, driven by the +cluster peripheral (`hardware/cachepool_peripheral/`): + +- A per-core register slot (`cfg_lp1_cmo`, `cfg_lp1_cmo_addr`, `lp1_cmo_commit`, + `lp1_cmo_status`) issues one CMO and reports completion, so unrelated cores + never contend on a shared trigger. +- A small FSM (`CMO_IDLE → CMO_REQ → CMO_RESP`) decodes the op and drives the + HPDcache: `FENCE` (write-through write-buffer drain), `INVAL_ALL` (invalidate + whole private L1), `INVAL_NLINE` (invalidate one line by address). +- The number of register slots (`NumLp1CmoRegs`) is **derived from the core + count** (`make update-periph-reg`) so it scales from 2g up to 16g. + +--- + +## 2. Software implementation + +Because the private L1 is **write-through with no hardware coherence**, any data +shared between cores needs explicit software coherence at the producer/consumer +boundary. The pattern throughout is: + +``` +acquire: lp1_inval() // drop stale private lines, so reads miss to fresh L2 + ... critical section / consume ... +release: snrt_fence() // drain in-flight Snitch + Spatz memory ops + lp1_wt_flush() // drain the write-through write buffer down to L2 +``` + +### Runtime CMO primitives (`software/snRuntime/{include,src}/lp1cache.c/.h`) + +Thin wrappers over the per-core CMO injector, each acting on the calling core's +own private L1 (no barrier needed — the register slot is per-core): + +| Function | Op | Purpose | +|---|---|---| +| `lp1_wt_flush()` | `FENCE` | **Release** — drain write-through write buffer to L2 | +| `lp1_inval()` | `INVAL_ALL` | **Acquire** — invalidate whole private L1 | +| `lp1_inval_line(addr)` | `INVAL_NLINE` | Invalidate the single line covering `addr` | + +Each writes op+addr to its slot, pulses `commit`, then spins on `status`. +Note on fences: `snrt_fence()` drains **both** Snitch and Spatz outstanding +memory ops; `snrt_fence_snitch()` / `snrt_fence_spatz()` are the single-engine +variants. + +### Kernel data protection + +The CMO discipline was applied to the kernels that share data across cores: + +- **fdotp-32b** (`software/tests/fdotp-32b/main.c`) — barrier-based partial-sum + reduction. Producers `snrt_fence()` + `lp1_wt_flush()` their partials; the + reducing core `lp1_inval()`s before reading, so the reduction sees fresh data. + No lock — visibility only. +- **fft-32b** (`software/tests/fft-32b/main.c`) — multi-stage butterfly. Each + phase-1 stage is bracketed with acquire (`lp1_inval` + `lp1_wt_flush`) before + the compute and release (`snrt_fence` + `lp1_wt_flush`) after, with a cluster + barrier between stages. The phase-2 interior needs no CMOs (its buffer swaps + stay within the owning core's L1). The pre-verification path on core 0 + additionally `l1d_flush()`es the shared L2. +- **spin-lock / multi-spin-lock** (`software/tests/{spin-lock,multi-spin-lock}/`) + — the classic lock case: `lp1_inval()` after acquire drops the stale + lock-protected line so the read refetches; `lp1_wt_flush()` before release + publishes the update. Multi-spin-lock (independent locks on different cores) is + the discriminating test that the per-core slotting works. +- **mcs-lock** (`software/tests/benchmark/mcs_lock.c`) — MCS queue lock protected + with the same acquire/release brackets around the node enqueue/handoff. +- **gemv** (`software/tests/gemv/main.c`) — producer/consumer protection plus an + `l1d_cluster_flush()` on the shared L2 around the result exchange. + + +--- + +## 3. New tests added + +All under `software/tests//`, registered in `software/tests/CMakeLists.txt`. + +### Private-L1 bring-up (tiered) + +- **lp1_sanity** — Tier 0 single-core smoke test: proves the system boots and one + core can drive the private-L1 scalar load/store datapath, reach UART, and + signal EOC with no coherence and nothing shared. +- **lp1_private** — Tier 1 all-cores-in-parallel test on disjoint, cacheline- + aligned per-core slices, exercising both the scalar path and the Spatz + coalescer scatter/gather through the L1 with no address ever shared. +- **lp1_eviction** — capacity/replacement test: each core hammers a working set + far larger than the L1 (and a conflict set exceeding the ways) to force + eviction and refill-after-eviction, proving it behaves like a cache, not a + buffer. +- **lp1_cmo** — single-core liveness gate for the per-core CMO injector datapath + (runtime MMIO store → peripheral reg → CMO FSM → HPDcache → done/status), + bracketing each `lp1_*` call with print markers to localise any hang. + +### AMO + +- **arith_amo** — single-core functional test of every RV32 `amo*.w` arithmetic + op plus in-cacheline word selection, verified only through L2-authoritative + paths (the AMO's returned old value, `amoor(addr,0)` as an atomic read). +- **lrsc_amo** — single-core LR/SC test that structurally triggers success and + failure cases (SC with no LR, double SC) and checks state via the SC return + code and L2-authoritative reads. + +### Cross-core coherence / locks + +- **multi-spin-lock** — the *discriminating* staleness gate: each core enters its + critical section many times so 2nd+ entries would re-read a stale private copy, + which passes only with the CMOs and fails without them. + +--- + +## 4. Performance overview + +Measured on `cachepool_fpu_16g_tiny`, comparing the baseline (no private cache) +against the design with a **4 KB private L1** per core. + +![Performance on fpu_16g_tiny, with and without the 4 KB private L1](figs/performance_16g_tiny.jpg) + +The private L1 clearly benefits the memory-intensive **FMATMUL** and **GEMV** +kernels but significantly degrades **FDOTP**: + +- **FMATMUL** — the largest win: FPU utilisation rises from **13.1% → 71.5%**. +- **GEMV** — improves from **9.0% → 17.4%**. +- **FDOTP** — utilisation drops significantly. + +The private L1 helps when data reuse lets cache hits hide memory latency (FMATMUL, +GEMV). For low-reuse, streaming kernels like FDOTP the frequent L1 misses expose +the HPDcache miss penalty, which outweighs the benefit. + +Overall, these results demonstrate that the private L1 cache has strong potential +to improve performance, and further gains are expected once the miss-penalty +behaviour is addressed. + +--- + +## 5. HPDcache miss-penalty analysis + +HPDcache is described as a "3-stage non-blocking pipeline," but for the **miss +path** it does not pipeline in the usual sense. It cannot service a new, +non-conflicting request in the same cycle that it does bookkeeping (MSHR +allocation, directory update, refill write) for an earlier request. A single load +miss therefore costs several fully-serialised cycles during which the cache +accepts nothing — the source of the unreasonably high miss cost. + +The FDOTP waveform below shows HPDcache acknowledging incoming requests on only +**4 sparse cycles out of 16** (≈25% request-side utilisation). Four cases from the +protocol-engine state machine contribute to this pattern: + +![HPDcache protocol-engine states over an FDOTP miss sequence](figs/hpdcache_pe_labled.jpg) + +- **Case 1 — Directory miss.** On a directory miss for a cacheable load, HPDcache + unconditionally inserts a bubble and deasserts `ready`, whether or not the MSHR + hits. No new request is accepted that cycle. +- **Case 2 — MSHR allocation.** The next cycle, MSHR allocation and directory + update insert another bubble. So one miss already causes at least two + consecutive blocked cycles before the refill is even processed. +- **Case 3 — Refill return.** When refill data returns, the pipeline is reserved + for the refill; core requests are blocked throughout, even ones that do not + conflict with the incoming refill. +- **Case 4 — Pending-request replay.** Requests held in the replay table are + served once the line is retrieved, go through the same pipeline, and take + priority over new core requests; `ready` is again gated during this. + +As a result, miss detection, MSHR allocation, refill handling, and request replay +are **fully serialised rather than overlapped**. HPDcache is genuinely non-blocking +or "pipelined" only under limited conditions — a cache hit, or a hit while a miss +is already outstanding; the miss-handling stages themselves are effectively +unpipelined. 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HcmV?d00001 diff --git a/hardware/src/cachepool_group.sv b/hardware/src/cachepool_group.sv index 06c9b0f..0484427 100644 --- a/hardware/src/cachepool_group.sv +++ b/hardware/src/cachepool_group.sv @@ -93,12 +93,6 @@ module cachepool_group /*** ATTENTION: `NrSramCfg` should be changed if `L1NumDataBank` and `L1NumTagBank` is changed ***/ parameter int unsigned NrSramCfg = 1, - // [LP1] Strategy-B collapse: inter-group ports no longer fan out per TCDM - // plane; the per-tile count is NumRemoteGroupPortCore * NumL2Plane. - // localparam int unsigned TotRGPorts = (NumRemoteGroupPortCore == 0) ? 0 : - // NumTilesPerGroup*NumRemoteGroupPortCore*NrTCDMPortsPerCore-1, - // localparam int unsigned NumRemoteGroupPortTile = (NumRemoteGroupPortCore == 0) ? 1 : - // NumRemoteGroupPortCore * NrTCDMPortsPerCore localparam int unsigned TotRGPorts = (NumRemoteGroupPortCore == 0) ? 0 : NumTilesPerGroup*NumRemoteGroupPortCore*NumL2Plane-1, localparam int unsigned NumRemoteGroupPortTile = (NumRemoteGroupPortCore == 0) ? 1 : @@ -642,26 +636,18 @@ module cachepool_group // Tile remote access signals // In/Out relative to the tile (out--leave a tile; in--enter a tile) - // [LP1] Strategy-B + Option-A: tile-side remote ports are cacheline-wide now, + // [LP1] tile-side remote ports are cacheline-wide now, // and the per-plane (NrTCDMPortsPerCore) xbar fan-out collapses to NumL2Plane. // Tile-side flat layout: index = j + r*NumL2Plane (j=xbar idx, r=remote slot within xbar) - // tcdm_req_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_out_req; - // tcdm_rsp_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_out_rsp; tcdm_cacheline_req_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_out_req; tcdm_cacheline_rsp_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_out_rsp; logic [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_ready, tile_remote_out_ready; - // tcdm_req_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_req; - // tcdm_rsp_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_rsp; tcdm_cacheline_req_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_req; tcdm_cacheline_rsp_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] tile_remote_in_rsp; // Xbar-side: NumL2Plane xbars, each with NumTilesPerGroup*NumRemotePortCore ports // Xbar port index = t*NumRemotePortCore + r - // tcdm_req_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_req_chan; - // tcdm_rsp_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_rsp_chan; - // tcdm_req_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_req_chan; - // tcdm_rsp_chan_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_in_rsp_chan; tcdm_cacheline_req_chan_t [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_req_chan; logic [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_req_valid, tile_remote_out_req_ready; tcdm_cacheline_rsp_chan_t [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] tile_remote_out_rsp_chan; @@ -680,12 +666,9 @@ module cachepool_group // Tile-side selection: narrow type, only carries tile_id remote_tile_sel_t [NumTilesPerGroup-1:0][NumRemotePortTile-1:0] remote_out_sel_tile; // Xbar-side selection: wider type, encodes tile_id*NumRemotePortCore + core_id%NumRemotePortCore - // local_remote_xbar_sel_t [NrTCDMPortsPerCore-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] remote_out_sel_xbar, remote_in_sel_xbar; local_remote_xbar_sel_t [NumL2Plane-1:0][NumTilesPerGroup*NumRemotePortCore-1:0] remote_out_sel_xbar, remote_in_sel_xbar; for (genvar t = 0; t < NumTilesPerGroup; t++) begin - // [LP1] j now indexes the (single) L2 plane; tile flat index = j + r*NumL2Plane. - // for (genvar j = 0; j < NrTCDMPortsPerCore; j++) begin for (genvar j = 0; j < NumL2Plane; j++) begin for (genvar r = 0; r < NumRemotePortCore; r++) begin // tile flat index: j + r*NumL2Plane @@ -909,41 +892,7 @@ module cachepool_group // Remote XBar // ------------ - // for (genvar p = 0; p < NrTCDMPortsPerCore; p++) begin : gen_remote_tile_xbar - // // Decide which tile to go - // reqrsp_xbar #( - // .NumInp (NumTilesPerGroup * NumRemotePortCore ), - // .NumOut (NumTilesPerGroup * NumRemotePortCore ), - // .PipeReg (1'b1 ), - // .RspReg (1'b1 ), - // .ExtReqPrio (1'b0 ), - // .ExtRspPrio (1'b0 ), - // .tcdm_req_chan_t (tcdm_req_chan_t ), - // .tcdm_rsp_chan_t (tcdm_rsp_chan_t ) - // ) i_tile_remote_xbar ( - // .clk_i (clk_i ), - // .rst_ni (rst_ni ), - // .slv_req_i (tile_remote_out_req_chan [p] ), - // .slv_req_valid_i (tile_remote_out_req_valid[p] ), - // .slv_req_ready_o (tile_remote_out_req_ready[p] ), - // .slv_rsp_o (tile_remote_out_rsp_chan [p] ), - // .slv_rsp_valid_o (tile_remote_out_rsp_valid[p] ), - // .slv_rsp_ready_i (tile_remote_out_rsp_ready[p] ), - // .slv_sel_i (remote_out_sel_xbar [p] ), - // .slv_rr_i ('0 ), - // .slv_selected_o (/*selection info in cid*/ ), - // .mst_req_o (tile_remote_in_req_chan [p] ), - // .mst_req_valid_o (tile_remote_in_req_valid [p] ), - // .mst_req_ready_i (tile_remote_in_req_ready [p] ), - // .mst_rsp_i (tile_remote_in_rsp_chan [p] ), - // .mst_rsp_valid_i (tile_remote_in_rsp_valid [p] ), - // .mst_rsp_ready_o (tile_remote_in_rsp_ready [p] ), - // .mst_rr_i ('0 ), - // .mst_sel_i (remote_in_sel_xbar [p] ) - // ); - // end - - // [LP1] Strategy-B collapse: a SINGLE intra-group remote crossbar (NumL2Plane = 1) + // [LP1] a SINGLE intra-group remote crossbar (NumL2Plane = 1) // carrying cacheline-wide payloads. The de-interleave above maps every tile's // remote slots onto plane 0, so this one xbar serves the whole group. reqrsp_xbar #( diff --git a/hardware/src/cachepool_group_noc_wrapper.sv b/hardware/src/cachepool_group_noc_wrapper.sv index 8566da2..8c9fbf9 100644 --- a/hardware/src/cachepool_group_noc_wrapper.sv +++ b/hardware/src/cachepool_group_noc_wrapper.sv @@ -108,10 +108,8 @@ module cachepool_group_noc_wrapper // ------------------------------------------------------------------------- // Localparams // ------------------------------------------------------------------------- - // [LP1] Strategy-B collapse: inter-group ports no longer fan out per TCDM plane; + // [LP1] inter-group ports no longer fan out per TCDM plane; // the per-tile count is NumRemoteGroupPortCore * NumL2Plane (matches cachepool_group). - // localparam int unsigned NumRemoteGroupPortTile = (NumRemoteGroupPortCore == 0) ? 1 - // : NumRemoteGroupPortCore * NrTCDMPortsPerCore; localparam int unsigned NumRemoteGroupPortTile = (NumRemoteGroupPortCore == 0) ? 1 : NumRemoteGroupPortCore * NumL2Plane; localparam int unsigned NumRemoteGroupPortGroup = NumRemoteGroupPortTile * NumTilesPerGroup; @@ -250,7 +248,7 @@ module cachepool_group_noc_wrapper assign mst_xbar_mst_sel[n] = eject_rsp[noc_port].hdr.src_port_id; end - // [LP1] Static port-to-NoC-channel mapping. After the Strategy-B collapse the + // [LP1] Static port-to-NoC-channel mapping. After the collapse the // tile emits NumRemoteGroupPortCore * NumL2Plane inter-group ports; the L2 // plane index is p % NumL2Plane, steered to NoC channel (plane % NumNoCPortsPerTile). // (With NumL2Plane == 1 every port maps to channel 0.) @@ -258,7 +256,6 @@ module cachepool_group_noc_wrapper ? $clog2(NumNoCPortsPerTile) : 1; logic [NumRemoteGroupPortTile-1:0][NocMstSelWidth-1:0] noc_mst_sel; for (genvar p = 0; p < NumRemoteGroupPortTile; p++) begin : gen_noc_mst_sel - // assign noc_mst_sel[p] = NocMstSelWidth'((p % NrTCDMPortsPerCore) % NumNoCPortsPerTile); assign noc_mst_sel[p] = NocMstSelWidth'((p % NumL2Plane) % NumNoCPortsPerTile); end diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv index f670960..e52e0a1 100644 --- a/hardware/src/cachepool_l1_ctrl.sv +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -398,10 +398,6 @@ module cachepool_l1_ctrl l1_req[0].addr_offset = coal_req_addr[HPDcacheCfg.reqOffsetWidth-1:0]; l1_req[0].addr_tag = coal_req_addr[HPDcacheCfg.reqOffsetWidth +: HPDcacheCfg.tagWidth]; l1_req[0].wdata = coal_req_wdata; - // Stores take the coalescer's wmask (correct slot + correct byte granularity). - // Reads keep the old hitmap-shift value: HPDcache only consumes `be` on the - // store/AMO/wbuf/uncached paths, and the coalescer leaves wmask = '0 on reads, - // so this avoids changing read behaviour while fixing the store path. l1_req[0].be = coal_req_wmask; // l1_req[0].be = coal_req_write ? coal_req_wmask : coal_be; l1_req[0].size = hpdcache_req_size_t'($clog2(coalescedDataWidth/8)); @@ -441,10 +437,6 @@ module cachepool_l1_ctrl l1_req[1].wdata = hpdcache_req_data_t'(cache_req_data[SnitchPort]) << (sn_byte_pos * ByteWidth); l1_req[1].be = hpdcache_req_be_t'(cache_req_strb[SnitchPort]) << sn_byte_pos; l1_req[1].tid = core_req_i[SnitchPort].q_valid ? l1_cache_req[SnitchPort].tid : '0; - // Phase 2: AMOs (incl. LR/SC) are serviced at the shared L2 by spatz_cache_amo, - // not inside this private L1. Mark them uncacheable so HPDcache routes them - // through its uncached/ATOP handler (forwards the atomic downstream) instead of - // doing a local self-update. Plain loads/stores stay cacheable WT. l1_req[1].pma.uncacheable = (cache_req_amo[SnitchPort] != AMONone); end @@ -597,16 +589,6 @@ module cachepool_l1_ctrl //////////////////////// // L2 -> L1 response // //////////////////////// - // The L2 response valid/ready handshake is (l2_rsp_i.p_valid / l2_rsp_ready_o); - // the ready rides on a separate wire (the interco's core_rsp_ready_i), not in - // tcdm_rsp_t (whose q_ready is the request grant). HPDcache's mem_resp_*_ready - // drives it, so refills/write-acks are properly back-pressured. Read/write - // responses are distinguished by p.write and steered to the matching HPDcache - // mem channel. The original HPDcache mem id is recovered by removing the - // per-private-cache offset the tile added to make ids unique towards the shared - // L2 (req_id += core_id + tile_id), i.e. req_id - core_id - tile_id. The L1 - // controller is core/tile-private and agnostic of its own ids (it reads them - // back from the echoed downstream user). always_comb begin : rsp_translation l1_mem_resp_read_valid = 1'b0; l1_mem_resp_write_valid = 1'b0; @@ -627,8 +609,7 @@ module cachepool_l1_ctrl end end - // Response ready back to the interco: HPDcache mem-resp ready for the matching - // channel. + // Response ready back to the interco: HPDcache mem-resp ready for the matching channel. assign l2_rsp_ready_o = l2_rsp_i.p.write ? l1_mem_resp_write_ready : l1_mem_resp_read_ready; @@ -658,9 +639,7 @@ module cachepool_l1_ctrl assign l1_mem_req_write_ready = __l1_mem_req_write_ready & l1_mem_req_write_both_valid; assign l1_mem_req_write_data_ready = __l1_mem_req_write_ready & l1_mem_req_write_both_valid; - // Downstream request metadata. The full HPDcache mem id rides in req_id and is - // trusted to round-trip; the tile offsets it by core_id for uniqueness across - // its private caches (undone on the response). core_id/tile_id tagged at tile. + // Downstream request metadata. always_comb begin : req_meta l1_l2_req_meta = '0; l1_l2_req_meta.is_amo = (l1_l2_req.mem_req_command == HPDCACHE_MEM_ATOMIC); @@ -680,13 +659,6 @@ module cachepool_l1_ctrl l2_req_o.q.user = l1_l2_req_meta; l2_req_o.q_valid = l1_l2_req_valid; - // Phase 2 AMO: phase 1 forced q.amo=AMONone (atomics were serviced inside - // HPDcache). Now route them to the shared-L2 spatz_cache_amo by translating - // HPDcache's AXI5-ATOP subtype back into the reqrsp amo_op_e the AMO unit reads. - // Atomics arrive with command==ATOMIC, so q.write stays 0 above: the AMO unit - // issues the operand-A read itself and generates its own write-back / SC write. - // The operand (rs2) rides on the write-data channel (mem_req_w_data) already - // aligned to the target byte offset. if (l1_l2_req.mem_req_command == HPDCACHE_MEM_ATOMIC) begin unique case (l1_l2_req.mem_req_atomic) HPDCACHE_MEM_ATOMIC_ADD : l2_req_o.q.amo = AMOAdd; diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index 01986d3..9d5e804 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -105,9 +105,6 @@ module cachepool_tile /// # SRAM Configuration rules needed: L1D Tag + L1D Data + L1D FIFO + L1I Tag + L1I Data /*** ATTENTION: `NrSramCfg` should be changed if `L1NumDataBank` and `L1NumTagBank` is changed ***/ parameter int unsigned NrSramCfg = 1, - // [LP1] Strategy-B collapse: inter-group remote ports no longer fan out per - // TCDM plane; the flat count drops to NumRemoteGroupPortCore * NumL2Plane. - // localparam int unsigned TotRGPorts = (NumRemoteGroupPortCore == 0) ? 0 : NumRemoteGroupPortCore*NrTCDMPortsPerCore-1 localparam int unsigned TotRGPorts = (NumRemoteGroupPortCore == 0) ? 0 : NumRemoteGroupPortCore*NumL2Plane-1 ) ( /// System clock. @@ -149,14 +146,6 @@ module cachepool_tile output axi_out_req_t [TileNarrowAxiPorts-1:0] axi_wide_req_o, input axi_out_resp_t [TileNarrowAxiPorts-1:0] axi_wide_rsp_i, /// Remote Tile access ports (to remote tiles) - // [LP1] Strategy-B collapse + Option-A width: the intra-group remote NoC is now - // cacheline-wide (tcdm_cacheline_*) and the flat dimension collapses to - // NumRemotePortTile = NumRemotePortCore * NumL2Plane (NumL2Plane = 1). Old - // narrow ports commented out. - // output tcdm_req_t [NumRemotePortTile-1:0] remote_req_o, - // input tcdm_rsp_t [NumRemotePortTile-1:0] remote_rsp_i, - // input tcdm_req_t [NumRemotePortTile-1:0] remote_req_i, - // output tcdm_rsp_t [NumRemotePortTile-1:0] remote_rsp_o, output tcdm_cacheline_req_t [NumRemotePortTile-1:0] remote_req_o, output remote_tile_sel_t [NumRemotePortTile-1:0] remote_req_dst_o, input tcdm_cacheline_rsp_t [NumRemotePortTile-1:0] remote_rsp_i, @@ -310,11 +299,6 @@ module cachepool_tile //////////////////////////////////////////// // Private L1 (LP1) HPDcache config & types // //////////////////////////////////////////// - // Per-core private L1 data cache (HPDcache, write-through, no coherence). - // It coalesces the core's Spatz TCDM lanes; its mem interface is the - // cacheline-wide downstream (l2_req) that feeds the shared L2 through the - // collapsed tile interco. Config/types defined here and passed to - // cachepool_l1_ctrl as parameters. // Spatz coalescer geometry localparam int unsigned NrLP1CoalInputs = NrTCDMPortsPerCore - 1; // Spatz lanes @@ -535,42 +519,22 @@ module cachepool_tile tcdm_req_t [NrTCDMPortsCores-1:0] unmerge_req; tcdm_rsp_t [NrTCDMPortsCores-1:0] unmerge_rsp; - // [LP1] cache_req/cache_rsp stay as the per-core *narrow* TCDM ports that feed - // the private L1 (gen_lp1_cache_transpose). The interco mem-side collapses to a - // single cacheline-wide plane per L2 controller (NumL2Plane = 1), so cache_xbar_* - // lose the NrTCDMPortsPerCore dimension and become tcdm_cacheline_*. + // cache_req/cache_rsp stay as the per-core *narrow* TCDM ports that feed + // the private L1 (gen_lp1_cache_transpose). tcdm_req_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_req; tcdm_rsp_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_rsp; - // tcdm_req_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_req, cache_xbar_req; - // tcdm_rsp_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_rsp, cache_xbar_rsp; + tcdm_cacheline_req_t [NumL1CtrlTile-1:0] cache_xbar_req; tcdm_cacheline_rsp_t [NumL1CtrlTile-1:0] cache_xbar_rsp; // Post-xbar gated copies. - // cache_ctrl_req : xbar output with q_valid suppressed during flush. - // cache_bank_rsp : raw response from the bank stage; q_ready is gated before - // being returned to the interco as cache_xbar_rsp. - // tcdm_req_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_ctrl_req; - // tcdm_rsp_t [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_bank_rsp; tcdm_cacheline_req_t [NumL1CtrlTile-1:0] cache_ctrl_req; tcdm_cacheline_rsp_t [NumL1CtrlTile-1:0] cache_bank_rsp; - // [LP1] Phase 1: AMOs are serviced inside the private L1 (HPDcache); the L2-side - // spatz_cache_amo is bypassed (kept instantiated-but-unused below for phase 2). - // cache_amo_* are therefore unused in the collapsed path. - // tcdm_req_t [NumL1CtrlTile-1:0] cache_amo_req; - // tcdm_rsp_t [NumL1CtrlTile-1:0] cache_amo_rsp; - // Phase 2: spatz_cache_amo is re-instantiated per L2 controller (cb) on the single - // cacheline port, between the flush-gated xbar output (cache_ctrl_req) and the bank - // spill register. The private L1 forwards AMOs downstream (uncacheable); this unit - // does the real bank-side RMW. cache_amo_* carry the unit's mem side to the bank. tcdm_cacheline_req_t [NumL1CtrlTile-1:0] cache_amo_req; tcdm_cacheline_rsp_t [NumL1CtrlTile-1:0] cache_amo_rsp; // ---- Private L1 (LP1) -> shared L1/L2 downstream (cacheline-wide) ---- - // One private L1 per core; its single mem-side downstream feeds the collapsed - // tile interco towards the shared cache (named L1 in this file). lp1_l1_req_unique - // tags a per-core id (core_id, req_id+=c) so the shared L1 round-trips it - // (recovered in the LP1 ctrl as req_id - core_id). + // One private L1 per core tcdm_cacheline_req_t [NumL1CtrlTile-1:0] lp1_l1_req, lp1_l1_req_unique; tcdm_cacheline_rsp_t [NumL1CtrlTile-1:0] lp1_l1_rsp; logic [NumL1CtrlTile-1:0] lp1_l1_rsp_ready; @@ -579,22 +543,7 @@ module cachepool_tile tcdm_rsp_t [NumLP1CacheCtrl-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_transposed; logic [NumLP1CacheCtrl-1:0][NrTCDMPortsPerCore-1:0] lp1_cache_rsp_ready, lp1_cache_req_ready; - // [LP1] Collapsed: one cacheline-wide port per L2 controller (was a 2-D - // [NumL1CtrlTile][NrTCDMPortsPerCore] fan-in feeding the in-ctrl coalescer). - // data/strb widen from DataWidth to the cacheline (the private L1 already - // coalesced upstream; the L2-side coalescer in the insitu fork is removed). - // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_valid; - // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_ready; - // tcdm_addr_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_addr; - // tcdm_user_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_meta; - // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_write; - // data_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_data; - // strb_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_req_strb; - // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_valid; - // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_ready; - // logic [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_write; - // data_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_data; - // tcdm_user_t [NumL1CtrlTile-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_meta; + // Collapsed: one cacheline-wide port per L2 controller logic [NumL1CtrlTile-1:0] cache_req_valid; logic [NumL1CtrlTile-1:0] cache_req_ready; tcdm_addr_t [NumL1CtrlTile-1:0] cache_req_addr; @@ -616,15 +565,10 @@ module cachepool_tile logic [NumL1CtrlTile-1:0][NumTagBankPerCtrl-1:0] l1_tag_bank_be; tag_data_t [NumL1CtrlTile-1:0][NumTagBankPerCtrl-1:0] l1_tag_bank_rdata; - // [LP1] Cacheline-granular L2 data banks: NumDataBankPerCtrl is now SetAssoc*BankFactor - // banks, each holding a full cache line. req/we/addr/gnt stay 1-per-bank; wdata/rdata - // widen to a cache line and be becomes a cacheline byte-mask. logic [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_req; logic [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_we; tcdm_bank_addr_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_addr; - // data_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_wdata; - // logic [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0][DataWidth/8-1:0] l1_data_bank_be; - // data_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_rdata; + cacheline_data_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_wdata; logic [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0][L1LineWidth/8-1:0] l1_data_bank_be; cacheline_data_t [NumL1CtrlTile-1:0][NumDataBankPerCtrl-1:0] l1_data_bank_rdata; @@ -689,20 +633,14 @@ module cachepool_tile logic [NrTCDMPortsCores-1:0] unmerge_pready; - // [LP1] cache_pready stays per-core narrow (LP1 core-side resp-ready, via the - // transpose). cache_xbar_pready is the interco mem-side resp-ready: one per L2 - // controller now. cache_amo_pready unused in the collapsed (AMO-in-L1) path. - // logic [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_pready, cache_xbar_pready; logic [NrTCDMPortsPerCore-1:0][NumL1CtrlTile-1:0] cache_pready; logic [NumL1CtrlTile-1:0] cache_xbar_pready; - // Phase 2: mem-side resp-ready of the per-cb spatz_cache_amo toward the bank spill. logic [NumL1CtrlTile-1:0] cache_amo_pready; // ---------------------------------------------------------------------------- - // [LP1] Old core<->interco bridge, replaced by the per-core private L1. + // Old core<->interco bridge, replaced by the per-core private L1. // The cores now drive their TCDM ports into cachepool_l1_ctrl (gen_lp1_cache); - // the LP1 downstream (lp1_l1_req_unique) feeds the collapsed interco. The old - // unmerge / cache_req reshape below is superseded and commented out. + // the LP1 downstream (lp1_l1_req_unique) feeds the collapsed interco. // ---------------------------------------------------------------------------- always_comb begin : cache_flush_protection for (int j = 0; unsigned'(j) < NrTCDMPortsCores; j++) begin @@ -746,12 +684,7 @@ module cachepool_tile end // ---------------------------------------------------------------------------- - // [LP1] Per-core private L1 data cache (HPDcache, write-through, no coherence). - // Core side: the core's NrTCDMPortsPerCore TCDM ports (Spatz lanes [0..N-2] + - // Snitch [N-1]). The LP1 coalesces/translates internally and exposes ONE - // cacheline-wide downstream (lp1_l1_req / lp1_l1_rsp) to the shared L1/L2. - // The core is always ready to accept responses (matches the legacy - // unmerge_pready = 1'b1 convention), so core_rsp_ready_i is tied high. + // Per-core private L1 data cache // ---------------------------------------------------------------------------- for (genvar c = 0; c < NumLP1CacheCtrl; c++) begin : gen_lp1_cache cachepool_l1_ctrl #( @@ -843,13 +776,7 @@ module cachepool_tile ); end - // [LP1] Tag each private L1 downstream with a globally-unique id so the shared - // L1/L2 can round-trip it. core_id selects the response path in the interco - // (input port == core_id); tile_id marks this tile (for remote response - // routing). req_id += core_id + tile_id offsets the HPDcache mem id so that - // ids from different private caches (across cores AND remote tiles, which are - // mutually agnostic) stay distinct towards the shared L2 (which keys on - // req_id). The LP1 ctrl recovers the original via req_id - core_id - tile_id. + // Tag each private L1 downstream with a globally-unique id for (genvar c = 0; c < NumLP1CacheCtrl; c++) begin : gen_lp1_l1_req_unique logic [CoreIDWidth-1:0] c_id; assign c_id = c[CoreIDWidth-1:0]; @@ -911,10 +838,9 @@ module cachepool_tile // Same flat layout as remote ports: flat = j + r * NrTCDMPortsPerCore. // Total count: NumRemoteGroupPortCore * NrTCDMPortsPerCore. - // [LP1] Single L2 plane: count drops to NumRemoteGroupPortCore * NumL2Plane, and + // Single L2 plane: count drops to NumRemoteGroupPortCore * NumL2Plane, and // the interco-side signals are cacheline-wide (Option A). The external ports // (remote_group_req_t) are already cacheline-wide via the pkg typedef. - // localparam int unsigned NumRemoteGroupPortTile = NumRemoteGroupPortCore * NrTCDMPortsPerCore; localparam int unsigned NumRemoteGroupPortTile = NumRemoteGroupPortCore * NumL2Plane; // Internal TCDM-style (cacheline-wide) signals going to/from the interco. @@ -929,7 +855,7 @@ module cachepool_tile if (NumRemoteGroupPortCore > 0) begin : gen_remote_group_ports always_comb begin - // [LP1] j now indexes the (single) L2 plane; flat de-interleave uses NumL2Plane. + // j now indexes the (single) L2 plane; flat de-interleave uses NumL2Plane. for (int j = 0; j < NumL2Plane; j++) begin for (int r = 0; r < NumRemoteGroupPortCore; r++) begin automatic int unsigned flat = j + r * NumL2Plane; @@ -1043,11 +969,10 @@ module cachepool_tile assign rg_interco_out_dst = '0; end - /// [LP1] Strategy-B collapse: the 5-plane (NrTCDMPortsPerCore) interco fan-out + /// Collapse: the 5-plane (NrTCDMPortsPerCore) interco fan-out /// becomes a SINGLE cacheline-wide plane (NumL2Plane = 1). The core side is now /// the per-core private-L1 downstreams (lp1_l1_req_unique), and the mem side /// drives one cacheline port per L2 controller (cache_xbar_*, no plane index). - /// Remote/inter-group slots are de-interleaved by NumL2Plane (so flat = r). for (genvar j = 0; j < NumL2Plane; j++) begin : gen_cache_xbar // Collect the NumRemotePortCore remote slots for this plane. tcdm_cacheline_req_t [NumRemotePortCore-1:0] xbar_remote_req_gated; @@ -1093,45 +1018,11 @@ module cachepool_tile assign xbar_remote_group_out_rsp [r] = rg_interco_out_rsp [flat]; assign rg_interco_out_pready [flat] = xbar_remote_group_out_pready[r]; end - - // tcdm_cache_interco #( - // .NumTiles (NumTiles ), - // .NumCores (NrCores ), - // .NumCache (NumL1CtrlTile ), - // .NumTotCache (NumL1CacheCtrl ), - // .NumRemotePort (NumRemotePortCore ), - // .NumRemoteGroupPort (NumRemoteGroupPortCore ), - // .NumTilesPerGroup (NumTilesPerGroup ), - // .AddrWidth (TCDMAddrWidth ), - // .TileIDWidth (TileIDWidth ), - // .tcdm_req_t (tcdm_req_t ), - // .tcdm_rsp_t (tcdm_rsp_t ), - // .tcdm_req_chan_t (tcdm_req_chan_t ), - // .tcdm_rsp_chan_t (tcdm_rsp_chan_t ) - // ) i_cache_xbar ( - // .clk_i ( clk_i ), - // .rst_ni ( rst_ni ), - // .tile_id_i ( tile_id_i ), - // .dynamic_offset_i ( dynamic_offset ), - // .private_start_addr_i ( private_start_addr_i ), - // .num_private_cache_i ( num_private_cache ), - // .core_req_i ({xbar_remote_group_in_req, xbar_remote_req_gated, cache_req [j]}), - // .core_rsp_ready_i ({xbar_remote_group_in_pready, xbar_remote_in_pready, cache_pready [j]}), - // .core_rsp_o ({xbar_remote_group_in_rsp, xbar_remote_rsp_xbar, cache_rsp [j]}), - // .tile_sel_o ( xbar_remote_req_dst ), - // .remote_group_sel_o ( xbar_remote_group_out_dst ), - // .mem_req_o ({xbar_remote_group_out_req, xbar_remote_req_o, cache_xbar_req [j]}), - // .mem_rsp_ready_o ({xbar_remote_group_out_pready, xbar_remote_out_pready, cache_xbar_pready[j]}), - // .mem_rsp_i ({xbar_remote_group_out_rsp, xbar_remote_rsp_i, cache_xbar_rsp [j]}) - // ); - // [LP1] New collapsed, cacheline-wide interco for the single L2 plane. // Core side : the NumL1CtrlTile per-core private-L1 downstreams // (lp1_l1_req_unique), already coalesced & id-tagged. // Mem side : one cacheline port per L2 controller (cache_xbar_*), no // plane index (NumL2Plane = 1). - // Routing math is identical to before (width-agnostic, Option A); only the - // data/strb width and the port multiplicity change. tcdm_cache_interco #( .NumTiles (NumTiles ), .NumCores (NrCores ), @@ -1164,35 +1055,7 @@ module cachepool_tile ); end else begin : gen_no_remote_group // No inter-group remote ports: instantiate interco without inter-group remote ports (backward-compatible). - // [LP1] Collapsed, cacheline-wide variant. Old narrow/5-plane instance below. - // tcdm_cache_interco #( - // .NumTiles (NumTiles ), - // .NumCores (NrCores ), - // .NumCache (NumL1CtrlTile ), - // .NumTotCache (NumL1CacheCtrl ), - // .NumRemotePort (NumRemotePortCore ), - // .AddrWidth (TCDMAddrWidth ), - // .TileIDWidth (TileIDWidth ), - // .tcdm_req_t (tcdm_req_t ), - // .tcdm_rsp_t (tcdm_rsp_t ), - // .tcdm_req_chan_t (tcdm_req_chan_t ), - // .tcdm_rsp_chan_t (tcdm_rsp_chan_t ) - // ) i_cache_xbar ( - // .clk_i ( clk_i ), - // .rst_ni ( rst_ni ), - // .tile_id_i ( tile_id_i ), - // .dynamic_offset_i ( dynamic_offset ), - // .private_start_addr_i ( private_start_addr_i ), - // .num_private_cache_i ( num_private_cache ), - // .core_req_i ({xbar_remote_req_gated, cache_req [j]} ), - // .core_rsp_ready_i ({xbar_remote_in_pready, cache_pready [j]} ), - // .core_rsp_o ({xbar_remote_rsp_xbar, cache_rsp [j]} ), - // .tile_sel_o ( xbar_remote_req_dst ), - // .remote_group_sel_o ( ), - // .mem_req_o ({xbar_remote_req_o, cache_xbar_req [j]}), - // .mem_rsp_ready_o ({xbar_remote_out_pready, cache_xbar_pready[j]}), - // .mem_rsp_i ({xbar_remote_rsp_i, cache_xbar_rsp [j]}) - // ); + // Collapsed, cacheline-wide variant. Old narrow/5-plane instance below. tcdm_cache_interco #( .NumTiles (NumTiles ), .NumCores (NrCores ), @@ -1225,138 +1088,6 @@ module cachepool_tile end for (genvar cb = 0; cb < NumL1CtrlTile; cb++) begin : gen_cache_connect - // Only Snitch will send out amo requests - // Ports from Spatz can bypass this module - - // [LP1] OLD per-plane AMO + spill structure. Superseded by the single - // cacheline-wide spill path below: the private L1 already coalesced the - // Spatz lanes and handles AMOs (phase 1), so there is one cacheline port per - // L2 controller and the L2-side spatz_cache_amo is bypassed. Kept for ref. - /* - for (genvar j = 0; j < NrTCDMPortsPerCore; j++) begin : gen_cache_amo_connect - if (j == NrTCDMPortsPerCore-1) begin : gen_amo - spatz_cache_amo #( - .DataWidth ( DataWidth ), - .CoreIDWidth ( CoreIDWidth ), - .tcdm_req_t ( tcdm_req_t ), - .tcdm_rsp_t ( tcdm_rsp_t ), - .tcdm_req_chan_t ( tcdm_req_chan_t ), - .tcdm_rsp_chan_t ( tcdm_rsp_chan_t ), - .tcdm_user_t ( tcdm_user_t ) - ) i_cache_amo ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .core_req_i (cache_ctrl_req [j][cb] ), - .core_rsp_ready_i (cache_xbar_pready[j][cb] ), - .core_rsp_o (cache_bank_rsp [j][cb] ), - .mem_req_o (cache_amo_req [cb] ), - .mem_rsp_ready_o (cache_amo_pready [cb] ), - .mem_rsp_i (cache_amo_rsp [cb] ) - ); - - tcdm_req_t cache_req_reg; - tcdm_rsp_t cache_rsp_reg; - - spill_register #( - .T ( tcdm_req_chan_t ), - .Bypass ( 1'b0 ) - ) i_spill_reg_cache_req ( - .clk_i , - .rst_ni ( rst_ni ), - .valid_i ( cache_amo_req[cb].q_valid ), - .ready_o ( cache_amo_rsp[cb].q_ready ), - .data_i ( cache_amo_req[cb].q ), - .valid_o ( cache_req_reg.q_valid ), - .ready_i ( cache_rsp_reg.q_ready ), - .data_o ( cache_req_reg.q ) - ); - - spill_register #( - .T ( tcdm_rsp_chan_t ), - .Bypass ( 1'b1 ) - ) i_spill_reg_cache_rsp ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( cache_rsp_reg.p_valid ), - .ready_o ( cache_rsp_ready [cb][j] ), - .data_i ( cache_rsp_reg.p ), - .valid_o ( cache_amo_rsp [cb].p_valid), - .ready_i ( cache_amo_pready[cb] ), - .data_o ( cache_amo_rsp [cb].p ) - ); - - assign cache_req_valid[cb][j] = cache_req_reg.q_valid; - assign cache_req_addr [cb][j] = cache_req_reg.q.addr; - assign cache_req_meta [cb][j] = cache_req_reg.q.user; - assign cache_req_write[cb][j] = cache_req_reg.q.write; - assign cache_req_data [cb][j] = cache_req_reg.q.data; - assign cache_req_strb [cb][j] = cache_req_reg.q.strb; - - assign cache_rsp_reg.p_valid = cache_rsp_valid[cb][j]; - assign cache_rsp_reg.q_ready = cache_req_ready[cb][j]; - assign cache_rsp_reg.p.data = cache_rsp_data [cb][j]; - assign cache_rsp_reg.p.user = cache_rsp_meta [cb][j]; - - assign cache_rsp_reg.p.write = cache_rsp_write[cb][j]; - - end else begin : gen_no_amo - // Spill registers to cut the L1 xbar → coalescer critical path, - // matching the timing budget of the Snitch AMO path above. - tcdm_req_t cache_req_reg; - tcdm_rsp_t cache_rsp_reg; - - spill_register #( - .T ( tcdm_req_chan_t ), - .Bypass ( 1'b0 ) - ) i_spill_reg_cache_req ( - .clk_i , - .rst_ni ( rst_ni ), - .valid_i ( cache_ctrl_req[j][cb].q_valid ), - .ready_o ( cache_bank_rsp[j][cb].q_ready ), - .data_i ( cache_ctrl_req[j][cb].q ), - .valid_o ( cache_req_reg.q_valid ), - .ready_i ( cache_rsp_reg.q_ready ), - .data_o ( cache_req_reg.q ) - ); - - spill_register #( - .T ( tcdm_rsp_chan_t ), - .Bypass ( 1'b1 ) - ) i_spill_reg_cache_rsp ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( cache_rsp_reg.p_valid ), - .ready_o ( cache_rsp_ready[cb][j] ), - .data_i ( cache_rsp_reg.p ), - .valid_o ( cache_bank_rsp[j][cb].p_valid ), - .ready_i ( cache_xbar_pready[j][cb] ), - .data_o ( cache_bank_rsp[j][cb].p ) - ); - - assign cache_req_valid[cb][j] = cache_req_reg.q_valid; - assign cache_req_addr [cb][j] = cache_req_reg.q.addr; - assign cache_req_meta [cb][j] = cache_req_reg.q.user; - assign cache_req_write[cb][j] = cache_req_reg.q.write; - assign cache_req_data [cb][j] = cache_req_reg.q.data; - assign cache_req_strb [cb][j] = cache_req_reg.q.strb; - - assign cache_rsp_reg.p_valid = cache_rsp_valid[cb][j]; - assign cache_rsp_reg.q_ready = cache_req_ready[cb][j]; - assign cache_rsp_reg.p.data = cache_rsp_data [cb][j]; - assign cache_rsp_reg.p.user = cache_rsp_meta [cb][j]; - assign cache_rsp_reg.p.write = cache_rsp_write[cb][j]; - - end - end - */ - - // [LP1] Single cacheline port per L2 controller. A spill register cuts the - // interco -> bank critical path (matching the old timing budget). - // Phase 2: spatz_cache_amo is re-instantiated here (one per cb) on the cacheline - // port. It serializes every access to this controller (the system-wide atomicity - // point) and performs the RMW for AMOs the private L1 forwarded uncacheable. Its - // mem side (cache_amo_*) drives the bank spill register below; plain loads/stores - // pass through it unchanged. tcdm_cacheline_req_t cache_req_reg; tcdm_cacheline_rsp_t cache_rsp_reg; @@ -1386,10 +1117,6 @@ module cachepool_tile ) i_spill_reg_cache_req ( .clk_i , .rst_ni ( rst_ni ), - // Phase 2: fed from the AMO unit's mem side instead of the xbar directly. - // .valid_i ( cache_ctrl_req[cb].q_valid ), - // .ready_o ( cache_bank_rsp[cb].q_ready ), - // .data_i ( cache_ctrl_req[cb].q ), .valid_i ( cache_amo_req[cb].q_valid ), .ready_o ( cache_amo_rsp[cb].q_ready ), .data_i ( cache_amo_req[cb].q ), @@ -1407,10 +1134,6 @@ module cachepool_tile .valid_i ( cache_rsp_reg.p_valid ), .ready_o ( cache_rsp_ready [cb] ), .data_i ( cache_rsp_reg.p ), - // Phase 2: bank response returns to the AMO unit's mem side, not the xbar. - // .valid_o ( cache_bank_rsp [cb].p_valid), - // .ready_i ( cache_xbar_pready[cb] ), - // .data_o ( cache_bank_rsp [cb].p ) .valid_o ( cache_amo_rsp [cb].p_valid), .ready_i ( cache_amo_pready[cb] ), .data_o ( cache_amo_rsp [cb].p ) @@ -1586,85 +1309,7 @@ module cachepool_tile assign l1d_insn_ready_o = flush_pending_q && (cache_flush_d == '0); for (genvar cb = 0; cb < NumL1CtrlTile; cb++) begin: gen_l1_cache_ctrl - // cachepool_cache_ctrl #( - // // Core - // .NumPorts (NrTCDMPortsPerCore ), - // .CoalExtFactor (L1CoalFactor ), - // .AddrWidth (L1AddrWidth ), - // .WordWidth (DataWidth ), - // .ByteWidth (8 ), - // .TagWidth (L1TagDataWidth ), - // // Cache - // .NumCacheEntry (L1NumEntryPerCtrl ), - // .CacheLineWidth (L1LineWidth ), - // .SetAssociativity (L1AssoPerCtrl ), - // .BankFactor (L1BankFactor ), - // // .LogDebug (0 ), - // .RefillDataWidth (RefillDataWidth ), - // // Type - // .core_meta_t (tcdm_user_t ), - // .impl_in_t (impl_in_t ), - // .refill_req_t (cache_refill_req_chan_t), - // .refill_rsp_t (cache_refill_rsp_chan_t), - // .burst_req_t (burst_req_t ) - // ) i_l1_controller ( - // .clk_i (clk_i ), - // .rst_ni (rst_ni ), - // .impl_i ('0 ), - // // Sync Control - // .cache_sync_valid_i (ctrl_sync_valid[cb] ), - // .cache_sync_ready_o (ctrl_sync_ready[cb] ), - // .cache_sync_insn_i (ctrl_sync_insn[cb] ), - // // SPM Size - // // The calculation of spm region in cache is different - // // than other modules (needs to times 2) - // // Currently assume full cache - // .bank_depth_for_SPM_i ('0 ), - // // Request - // .core_req_valid_i (cache_req_valid[cb] ), - // .core_req_ready_o (cache_req_ready[cb] ), - // .core_req_addr_i (cache_req_addr [cb] ), - // .core_req_meta_i (cache_req_meta [cb] ), - // .core_req_write_i (cache_req_write[cb] ), - // .core_req_wdata_i (cache_req_data [cb] ), - // .core_req_wstrb_i (cache_req_strb [cb] ), - // // Response - // .core_resp_valid_o (cache_rsp_valid[cb] ), - // .core_resp_ready_i (cache_rsp_ready[cb] ), - // .core_resp_write_o (cache_rsp_write[cb] ), - // .core_resp_data_o (cache_rsp_data [cb] ), - // .core_resp_meta_o (cache_rsp_meta [cb] ), - // // TCDM Refill - // .refill_req_o (cache_refill_req [cb] ), - // .refill_burst_o (cache_refill_burst [cb] ), - // .refill_req_valid_o (cache_refill_req_valid[cb] ), - // .refill_req_ready_i (cache_refill_req_ready[cb] ), - // .refill_rsp_i (cache_refill_rsp [cb] ), - // .refill_rsp_valid_i (cache_refill_rsp_valid[cb] ), - // .refill_rsp_ready_o (cache_refill_rsp_ready[cb] ), - // // Tag Banks - // .tcdm_tag_bank_req_o (l1_tag_bank_req [cb] ), - // .tcdm_tag_bank_we_o (l1_tag_bank_we [cb] ), - // .tcdm_tag_bank_addr_o (l1_tag_bank_addr [cb] ), - // .tcdm_tag_bank_wdata_o (l1_tag_bank_wdata[cb] ), - // .tcdm_tag_bank_be_o (l1_tag_bank_be [cb] ), - // .tcdm_tag_bank_rdata_i (l1_tag_bank_rdata[cb] ), - // // Data Banks - // .tcdm_data_bank_req_o (l1_data_bank_req [cb] ), - // .tcdm_data_bank_we_o (l1_data_bank_we [cb] ), - // .tcdm_data_bank_addr_o (l1_data_bank_addr [cb] ), - // .tcdm_data_bank_wdata_o(l1_data_bank_wdata[cb] ), - // .tcdm_data_bank_be_o (l1_data_bank_be [cb] ), - // .tcdm_data_bank_rdata_i(l1_data_bank_rdata[cb] ), - // .tcdm_data_bank_gnt_i (l1_data_bank_gnt [cb] ) - // ); - - // [LP1] New shared-cache (L2) controller: ONE cacheline-wide core port. - // The private L1 already coalesced the Spatz lanes upstream, so the L2-side - // coalescer (i_par_coalescer_for_spatz) is removed in the insitu fork and - // CoalExtFactor collapses to 1, WordWidth widens to the full cache line. - // The fork's core_req_*/core_resp_* interface must present this single - // cacheline port (the tile drives the scalar cache_req_*/cache_rsp_* below). + // New shared-cache (L2) controller: ONE cacheline-wide core port. cachepool_cache_ctrl #( // Core .NumPorts (1 ), @@ -1860,10 +1505,9 @@ module cachepool_tile ); end - // [LP1] Cacheline-granular: each bank is directly one cacheline-wide SRAM + // Cacheline-granular: each bank is directly one cacheline-wide SRAM // (NumDataBankPerCtrl == SetAssoc*BankFactor now), matching the L2 ctrl's - // per-bank cacheline ports. The old NumWordPerLine grouping (which packed - // narrow per-word entries into a cacheline SRAM) is no longer needed. + // per-bank cacheline ports. for (genvar bank = 0; bank < NumDataBankPerCtrl; bank++) begin : gen_l1_data_banks tc_sram_impl #( .NumWords (L1CacheWayEntry/L1BankFactor), @@ -1887,63 +1531,6 @@ module cachepool_tile assign l1_data_bank_gnt[cb][bank] = 1'b1; end - - // TODO: Should we use a single large bank or multiple narrow ones? - // for (genvar bank = 0; bank < (NumDataBankPerCtrl/NumWordPerLine); - // bank++) begin : gen_l1_data_banks - // localparam int unsigned BaseIdx = bank * NumWordPerLine; - // logic [NumWordPerLine*WordBytes-1:0] bank_be; - - // for (genvar w = 0; w < NumWordPerLine; w++) begin : gen_bank_be - // assign bank_be[w*WordBytes +: WordBytes] = l1_data_bank_be[cb][BaseIdx + w]; - // end - - // tc_sram_impl #( - // .NumWords (L1CacheWayEntry/L1BankFactor), - // .DataWidth (L1LineWidth), - // .ByteWidth (8 ), - // .NumPorts (1 ), - // .Latency (1 ), - // .SimInit ("zeros" ) - // ) i_data_bank ( - // .clk_i (clk_i ), - // .rst_ni (rst_ni ), - // .impl_i ('0 ), - // .impl_o (/* unused */ ), - // .req_i ( l1_data_bank_req [cb][BaseIdx] ), - // .we_i ( l1_data_bank_we [cb][BaseIdx] ), - // .addr_i ( l1_data_bank_addr [cb][BaseIdx] ), - // .wdata_i( l1_data_bank_wdata[cb][BaseIdx+:NumWordPerLine]), - // .be_i ( bank_be ), - // .rdata_o( l1_data_bank_rdata[cb][BaseIdx+:NumWordPerLine]) - // ); - - // assign l1_data_bank_gnt[cb][BaseIdx+:NumWordPerLine] = {NumWordPerLine{1'b1}}; - // end - - // for (genvar j = 0; j < NumDataBankPerCtrl; j++) begin : gen_l1_data_banks - // tc_sram_impl #( - // .NumWords (L1CacheWayEntry/L1BankFactor), - // .DataWidth (DataWidth), - // .ByteWidth (DataWidth), - // .NumPorts (1), - // .Latency (1), - // .SimInit ("zeros") - // ) i_data_bank ( - // .clk_i (clk_i ), - // .rst_ni (rst_ni ), - // .impl_i ('0 ), - // .impl_o (/* unused */ ), - // .req_i (l1_data_bank_req [cb][j]), - // .we_i (l1_data_bank_we [cb][j]), - // .addr_i (l1_data_bank_addr [cb][j]), - // .wdata_i(l1_data_bank_wdata[cb][j]), - // .be_i (l1_data_bank_be [cb][j]), - // .rdata_o(l1_data_bank_rdata[cb][j]) - // ); - - // assign l1_data_bank_gnt[cb][j] = 1'b1; - // end end hive_req_t [NrCores-1:0] hive_req; diff --git a/hardware/src/spatz_cache_amo.sv b/hardware/src/spatz_cache_amo.sv index 5dca308..f46f5d8 100644 --- a/hardware/src/spatz_cache_amo.sv +++ b/hardware/src/spatz_cache_amo.sv @@ -57,7 +57,6 @@ module spatz_cache_amo ); // logic idx_q, idx_d; - // Phase 2: the AMO unit now faces a cacheline-wide port (DataWidth=512) but the // atomic is still a 32-bit word. NumWords/IdxW generalize the 1-bit lane select. localparam int unsigned NumWords = DataWidth/32; localparam int unsigned IdxW = (NumWords > 1) ? $clog2(NumWords) : 1; @@ -227,28 +226,17 @@ module spatz_cache_amo mem_req_o.q = amo_req; mem_req_o.q_valid = amo_req_valid; core_ready = amo_req_ready; - // Phase 2 (WI-4a): an SC must always present its outcome on the *write* channel, + // An SC must always present its outcome on the *write* channel, // because HPDcache's uncached handler waits on mem_resp_write for an SC and decodes // success from mem_resp_w_is_atomic. A *successful* SC performs the real store; a // *failed* SC still issues a write but with zero byte-enables (a no-op store) so the // bank still returns a write ack. Hence write=1 for every SC, success or fail. - // NOTE: the zero-strb no-op store relies on the bandwidth-matched bank path - // (BurstLength==1, i.e. refill_data_width==l1d_cacheline_width) forwarding the write - // downstream and returning its B response. Under BurstLength>1 the cache_ctrl - // suppresses zero-strb writes (no response) -> a failed SC would hang; that config - // would instead need the response synthesized here. // mem_req_o.q.write = amo_req.write | (sc_successful & (amo_insn == AMOSC)); mem_req_o.q.write = amo_req.write | (amo_insn == AMOSC); mem_req_o.q.amo = AMONone; mem_req_o.q.data = amo_req.data; // Failed SC: keep it a write transaction but disable all byte-enables (no store). mem_req_o.q.strb = (amo_insn == AMOSC && !sc_successful) ? '0 : amo_req.strb; - // The bank echoes user.is_amo on its response. In phase 2 that bit must mean - // "atomic write-ack" so the L1 ctrl routes the response on the write channel and - // maps it to mem_resp_w_is_atomic -- not merely "the request was atomic". Strip it - // on the forwarded request so the old-value READ response (arith AMO / LR) is never - // mistaken for a write-ack. WriteBackAMO re-asserts it for the RMW write-back below; - // an SC carries its success/failure in is_amo (-> mem_resp_w_is_atomic). mem_req_o.q.user.is_amo = (amo_insn == AMOSC) ? sc_successful : 1'b0; amo_result_en = 1'b0; @@ -326,14 +314,10 @@ module spatz_cache_amo core_rsp_o.q_ready = core_ready; mem_rsp_ready_o = amo_rsp_ready; - // Phase 2 (WI-4a): the AMO write-back response (user.is_amo=1) used to be a purely - // internal artifact and was dropped here so the core observed a single response. - // The unit now sits below HPDcache's uncached/AMO handler, which expects BOTH an + // This unit now sits below HPDcache's uncached/AMO handler, which expects BOTH an // old-value read response AND a write ack for an arithmetic AMO (and a write-channel // response for SC). So the is_amo write-back must flow upward as that write ack - // instead of being filtered; forwarding is unconditional. The old-value read - // response no longer carries is_amo (stripped on the request above), so the two are - // unambiguous downstream (read channel vs write channel, by p.write). + // instead of being filtered; forwarding is unconditional. // if (amo_rsp_valid && mem_rsp_i.p.user.is_amo) begin // // Means we receive a response message generated by AMO, should not forward to core // core_rsp_o.p = '0; @@ -346,8 +330,6 @@ module spatz_cache_amo // Assertions // ---------- // Check that data width is legal (a power of two and at least 32 bit). - // Phase 2: the unit now faces a cacheline-wide port (DataWidth up to the L1 line - // width, e.g. 512), with the 32-bit amo.w targeting one word selected by addr[5:2]. // `ASSERT_INIT(DataWidthCheck, // DataWidth >= 32 && DataWidth <= 64 && 2**$clog2(DataWidth) == DataWidth) `ASSERT_INIT(DataWidthCheck, @@ -355,7 +337,7 @@ module spatz_cache_amo // Make sure that write is never set for AMOs. `ASSERT(AMOWriteEnable, amo_req_valid && !amo_insn inside {AMONone} |-> !amo_req.write) // Byte enable mask is correct - // Phase 2: LR arrives on the read channel and carries no byte-enables, so exclude it + // LR arrives on the read channel and carries no byte-enables, so exclude it // from the byte-mask cross-check (only RMW AMOs and SC carry an aligned strb group). // Use explicit parens around `inside`: unlike the single-element {AMONone} idiom, the // negation of a multi-element set does not survive `!`'s tighter precedence. diff --git a/software/tests/benchmark/mcs_lock.c b/software/tests/benchmark/mcs_lock.c index 15ad4b2..b703164 100644 --- a/software/tests/benchmark/mcs_lock.c +++ b/software/tests/benchmark/mcs_lock.c @@ -24,17 +24,7 @@ #include "benchmark.h" // #include "printf_lock.h" -// Private-L1 (LP1) Cache Management Operations. On the per-core private -// write-through L1 (no coherence) the MCS handshake variables (`me->locked`, -// `me->next`) are written by one core and spun on by another, so a spinner -// keeps hitting a stale cached copy and never observes the handoff. Bracket -// the handshake with lp1_inval() on the consumer (spin) side and lp1_wt_flush() -// on the producer (publish) side, ordered by snrt_fence(). Guarded by LP1_CMO -// so consumers that do not run on the private L1 are unaffected. -#define LP1_CMO -#ifdef LP1_CMO #include -#endif // Each waiter spins on its own node (aligned to keep it on a single line) struct __attribute__((aligned(MCS_CACHELINE))) mcs_node { @@ -140,21 +130,18 @@ void __attribute__((noinline)) mcs_lock_acquire(mcs_lock_t* L, int delay) { if (pred) { atomic_store_explicit(&me->locked, true, memory_order_relaxed); atomic_store_explicit(&pred->next, me, memory_order_relaxed); -#ifdef LP1_CMO - // Producer side: order the two stores above and drain the write-through - // buffer so the predecessor observes pred->next=me (and our armed locked - // flag) at L2. Fence must precede the flush (WBUF ordering). + + // Producer side: order the two stores above and drain the wbuf snrt_fence(); lp1_wt_flush(); -#endif + while (atomic_load_explicit(&me->locked, memory_order_relaxed)) { // cachepool_wait(delay); // prevent busy spinning -#ifdef LP1_CMO - // Consumer side: drop the stale private-L1 copy of `locked` so the next - // read misses and refetches the predecessor's handoff (locked=false). + + // Consumer side: drop the stale private-L1 copy lp1_inval(); snrt_fence(); -#endif + } } @@ -172,12 +159,12 @@ void __attribute__((noinline)) mcs_lock_release(mcs_lock_t* L, int delay) { if (!b) return; // or assert in debug struct mcs_node* me = &b->node; -#ifdef LP1_CMO + // Consumer side: `me->next` is published by the successor from another core; // drop the stale private-L1 copy before reading it. lp1_inval(); snrt_fence(); -#endif + struct mcs_node* succ = // atomic_load_explicit(&me->next, memory_order_acquire); atomic_load_explicit(&me->next, memory_order_relaxed); @@ -193,12 +180,12 @@ void __attribute__((noinline)) mcs_lock_release(mcs_lock_t* L, int delay) { // A successor is enqueuing; wait for linkage. do { // cachepool_wait(delay); // prevent busy spinning -#ifdef LP1_CMO + // Consumer side: refetch `me->next` fresh each spin until the successor's // linkage store is observed at L2. lp1_inval(); snrt_fence(); -#endif + // succ = atomic_load_explicit(&me->next, memory_order_acquire); succ = atomic_load_explicit(&me->next, memory_order_relaxed); } while (!succ); @@ -206,12 +193,12 @@ void __attribute__((noinline)) mcs_lock_release(mcs_lock_t* L, int delay) { // Handoff: clear the successor's locked flag. atomic_store_explicit(&succ->locked, false, memory_order_release); -#ifdef LP1_CMO + // Producer side: drain the write-through buffer so the successor spinning on // its `locked` flag observes the handoff promptly. Fence precedes the flush. snrt_fence(); lp1_wt_flush(); -#endif + mcs_bind_release_slot(b); // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); diff --git a/software/tests/gemv/main.c b/software/tests/gemv/main.c index d15a82a..3a5313c 100644 --- a/software/tests/gemv/main.c +++ b/software/tests/gemv/main.c @@ -26,26 +26,6 @@ #include "kernel/gemv.c" #include DATAHEADER -// --------------------------------------------------------------------------- -// Private-L1 (LP1): this kernel DOES need coherency protection. -// -// Unlike fmatmul-32b (where each core verifies its own rows, so producer == -// consumer and no CMO is needed), here core `cid` writes result[cid*m_core ..) -// but CORE 0 VERIFIES ALL OF THEM. Producer != consumer, so the shared `result` -// buffer needs a full release/acquire pair around the barrier: -// -// producer (every core): snrt_fence(); lp1_wt_flush(); -// consumer (core 0): lp1_inval(); snrt_fence(); -// -// The acquire half is not optional cosmetics. m_core = M/num_cores is only 4 -// floats (16 B) for M=128 on 32 cores, so FOUR cores share one 64 B cacheline of -// `result`. Write-through keeps L2 correct (per-word strobes), but core 0's own -// cached copy of that line still carries cores 1-3's stale words, and nothing -// updates it. It must be invalidated before core 0 reads. -// -// A and B are read-only shared -- no protection needed for them. -// --------------------------------------------------------------------------- - #if (PREC == 64) #define T double #elif (PREC == 32) @@ -161,22 +141,13 @@ int main() { // All cores flush before first-iteration verification if (i == 0) { - // Producer / release. snrt_fence() drains this core's outstanding Spatz - // vector stores (snrt_cluster_hw_barrier() does NOT -- it is just a scalar - // load by Snitch, and Spatz is decoupled); lp1_wt_flush() then drains the - // write-through buffer so the values actually reach L2. + // Producer / release. snrt_fence(); lp1_wt_flush(); l1d_cluster_flush(); - // Consumer / acquire. Core 0 is about to read EVERY core's slice of - // `result`, so it must drop the copies in its own private L1 -- the release - // above pushed the producers' values to L2 but told core 0 nothing. Without - // this, core 0 can read stale words out of a line it false-shares with cores - // 1..3 (m_core is 16 B for M=128 on 32 cores; a line is 64 B). - // lp1_inval() drives a per-core CMO slot with no internal barrier, so it is - // safe to call from every core. + // Consumer / acquire. Core 0 drop the copies in its own private L1 lp1_inval(); snrt_fence(); } From 9de023c7cb7058c7b65163d398d9e89159fd8878 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Mon, 20 Jul 2026 17:44:52 +0200 Subject: [PATCH 35/39] note adjust --- WTL1_note.md | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/WTL1_note.md b/WTL1_note.md index 98c8afe..99b9234 100644 --- a/WTL1_note.md +++ b/WTL1_note.md @@ -108,12 +108,10 @@ Atomic memory operations are supported end-to-end through the new hierarchy: (`AMOSwap/Add/And/Or/Xor/Max/Min/Maxu/Minu` and `LR/SC`) on the request path, and re-derives the RISC-V AMO op from HPDcache's `mem` atomic encoding on the L1→L2 path. AMOs are never coalesced and carry the hit lane's op. -- HPDcache forwards uncacheable reqeust directly to the lower hierarchy without - touching its local data. -- `spatz_cache_amo.sv` is the RMW shim in front of the shared SRAMs that executes +- The Snitch AMO path is marked uncacheable at the L1 requester. HPDcache forwards uncacheable reqeust directly to + the lower hierarchy without touching its local data. +- `spatz_cache_amo.sv` is the module in front of the shared cache that executes the atomics (LR/SC reservations at `DataWidth` granularity). -- AMOs on the cacheable path flow through HPDcache in phase 1; the Snitch AMO - path is marked uncacheable at the L1 requester. ### Per-core CMO injector (HW side of the software CMO API) From 34f053bed761bb97c51c92f01a6a031a6ea8ebb2 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Thu, 23 Jul 2026 17:39:10 +0200 Subject: [PATCH 36/39] [SW HW] re-route private L1 CMOs from peripheral to snitch CSR --- Bender.local | 3 +- Bender.lock | 12 +-- Bender.yml | 3 +- Makefile | 15 --- hardware/cachepool_peripheral/Makefile | 9 +- .../cachepool_peripheral.sv | 59 +---------- .../cachepool_peripheral_reg.hjson | 98 ------------------- hardware/src/cachepool_cc.sv | 9 ++ hardware/src/cachepool_cluster.sv | 15 +-- hardware/src/cachepool_group.sv | 14 +-- hardware/src/cachepool_group_noc_wrapper.sv | 9 +- hardware/src/cachepool_l1_ctrl.sv | 20 ++-- hardware/src/cachepool_tile.sv | 30 ++++-- software/snRuntime/include/lp1cache.h | 13 +-- software/snRuntime/src/lp1cache.c | 55 ++++------- 15 files changed, 80 insertions(+), 284 deletions(-) diff --git a/Bender.local b/Bender.local index e99a4c0..2ff8279 100644 --- a/Bender.local +++ b/Bender.local @@ -5,5 +5,6 @@ overrides: axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 } - + Insitu-Cache: { path: "../Insitu-Cache" } + hpdcache: { path: "../cv-hpdcache" } diff --git a/Bender.lock b/Bender.lock index fdc4672..8c1a32f 100644 --- a/Bender.lock +++ b/Bender.lock @@ -32,7 +32,7 @@ packages: dependencies: - common_cells cluster_icache: - revision: ce0ed94a5b95f5c76b9fa51940303fcce53f56e5 + revision: 8e574182b1ed125ec1ed1ec7f1ffc9c2096250b3 version: null source: Git: https://github.com/pulp-platform/cluster_icache.git @@ -56,14 +56,14 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] dram_rtl_sim: - revision: null + revision: fc831811ac0e1b374814f64bb7a53abd8e6171b4 version: null source: - Path: hardware/deps/dram_rtl_sim + Git: https://github.com/pulp-platform/dram_rtl_sim.git dependencies: - axi floo_noc: - revision: a7d46c0aed7475a02de94f888a25495ae74d706f + revision: 9a6972a5f9b8117506d1df8a6505ce1da2bc9084 version: null source: Git: https://github.com/pulp-platform/FlooNoC.git @@ -156,10 +156,10 @@ packages: dependencies: - tech_cells_generic spatz: - revision: null + revision: 14e3e884366ce0e4987c22c36510fa71a369a89b version: null source: - Path: hardware/deps/spatz + Git: https://github.com/HHT1228/spatz.git dependencies: - axi - axi_riscv_atomics diff --git a/Bender.yml b/Bender.yml index fa98312..fd35f57 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,8 @@ dependencies: dram_rtl_sim: { git: "https://github.com/pulp-platform/dram_rtl_sim.git", rev: cachepool } floo_noc: { git: "https://github.com/pulp-platform/FlooNoC.git", rev: main } cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: main } - spatz: { git: "https://github.com/pulp-platform/spatz.git", rev: cachepool-32b } + # spatz: { git: "https://github.com/pulp-platform/spatz.git", rev: cachepool-32b } + spatz: { git: "https://github.com/HHT1228/spatz.git", rev: hohung/cachepool-wt-l1 } workspace: checkout_dir: "./hardware/deps" diff --git a/Makefile b/Makefile index 27512de..d3dcc51 100644 --- a/Makefile +++ b/Makefile @@ -187,20 +187,6 @@ $(FLOO_NOC): install-floogen $(FLOO_CFG) clean-floonoc: rm -f $(FLOO_NOC) -######################### -# Peripheral registers # -######################### -# The LP1 (private-L1) CMO peripheral has one register slot per core. The slot -# count (NumLp1CmoRegs) is baked into the generated reg_pkg/reg_top/C-header by -# regtool, so it must be regenerated whenever the config's core count changes -- -# analogous to update-floonoc for the mesh. We force the regen (-B) because the -# generated .sv/.h are committed and may be newer than the (unchanged) schema. -PERIPH_REG_DIR ?= $(ROOT_DIR)/hardware/cachepool_peripheral - -.PHONY: update-periph-reg -update-periph-reg: - $(MAKE) -C $(PERIPH_REG_DIR) -B all NUM_LP1_CMO_REGS=$(num_cores) - ########### # DramSys # ########### @@ -441,7 +427,6 @@ help: @echo "*cache-init*: source the insitu-cache environment (requires bender checkout)" @echo "*bootrom*: compile and generate the bootrom SystemVerilog module" @echo "*update-floonoc*: regenerate FlooNoC package from FLOO_CFG (run after changing group count)" - @echo "*update-periph-reg*: regenerate the peripheral registers with NumLp1CmoRegs=num_cores (run after changing core count)" @echo "*install-floogen*: install the floogen Python tool (required by update-floonoc)" @echo "*clean-floonoc*: remove the generated FlooNoC package" @echo "" diff --git a/hardware/cachepool_peripheral/Makefile b/hardware/cachepool_peripheral/Makefile index ff8b8df..d69bc8d 100644 --- a/hardware/cachepool_peripheral/Makefile +++ b/hardware/cachepool_peripheral/Makefile @@ -15,14 +15,7 @@ PKG=cachepool_peripheral_reg_pkg.sv TOP=cachepool_peripheral_reg_top.sv CDEF=$(ROOTDIR)/software/snRuntime/include/cachepool_peripheral.h -# Number of per-core LP1 (private-L1) CMO register slots. MUST be >= the total -# core count of the target config, or cores with cid >= this value spin forever -# on LP1_CMO_STATUS (their slot is never decoded) -> cluster barrier deadlock. -# The top-level `make update-periph-reg` overrides this with the current -# config's num_cores; the default here is a safe max (256 = full 16g) for a -# standalone `make -C hardware/cachepool_peripheral`. -NUM_LP1_CMO_REGS ?= 256 -REGGEN_PARAMS := -p NumLp1CmoRegs=$(NUM_LP1_CMO_REGS) +REGGEN_PARAMS := all: $(PKG) $(TOP) $(CDEF) diff --git a/hardware/cachepool_peripheral/cachepool_peripheral.sv b/hardware/cachepool_peripheral/cachepool_peripheral.sv index 2b420cd..74d5589 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral.sv +++ b/hardware/cachepool_peripheral/cachepool_peripheral.sv @@ -15,12 +15,11 @@ module cachepool_peripheral parameter int unsigned SPMWidth = 0, // Number of tiles (used for flush controller granularity) parameter int unsigned NumTiles = 1, - // Number of cores (one per-core LP1 CMO slot). Must be <= NumLp1CmoRegs. + // Number of cores. parameter int unsigned NumCores = 1, parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, parameter type cache_insn_t = logic, - parameter type lp1_cmo_req_t = logic, /// Derived parameter *Do not override* parameter type addr_t = logic [AddrWidth-1:0], parameter type spm_size_t = logic [SPMWidth-1:0] @@ -45,11 +44,7 @@ module cachepool_peripheral output cache_insn_t l1d_insn_o, output logic l1d_insn_valid_o, input logic [NumTiles-1:0] l1d_insn_ready_i, - output logic [NumTiles-1:0] l1d_busy_o, - // Per-core private-L1 (LP1) CMO injector interface (one slot per core). - output lp1_cmo_req_t [NumCores-1:0] lp1_cmo_req_o, - output logic [NumCores-1:0] lp1_cmo_valid_o, - input logic [NumCores-1:0] lp1_cmo_done_i + output logic [NumTiles-1:0] l1d_busy_o ); cachepool_peripheral_reg2hw_t reg2hw; @@ -190,56 +185,6 @@ module cachepool_peripheral assign hw2reg.l1d_flush_status.d = (l1d_lock_q != '0); // assign l1d_busy_o = (l1d_lock_q != '0); - //////////// Private-L1 (LP1) per-core CMO //////////// - // Per-core handshake mirroring the L1D flush path above, but vectorized so - // that independent cores running unrelated critical sections issue CMOs - // without contending on a shared trigger register. Per core slot [c]: - // commit[c] & !lock[c] -> pulse valid[c], present op/addr, set lock[c], - // and self-clear the commit bit - // done[c] -> clear lock[c] - // status[c] = lock[c] (busy while a CMO is in flight) - logic [NumLp1CmoRegs-1:0] lp1_cmo_lock_d, lp1_cmo_lock_q; - - always_comb begin : lp1_cmo_cfg - lp1_cmo_lock_d = lp1_cmo_lock_q; - - // Default every register-file back-channel low (covers unused upper slots - // when NumCores < NumLp1CmoRegs). - for (int unsigned i = 0; i < NumLp1CmoRegs; i++) begin - hw2reg.lp1_cmo_commit[i].d = 1'b0; - hw2reg.lp1_cmo_commit[i].de = 1'b0; - hw2reg.lp1_cmo_status[i].d = 1'b0; - end - - // Default the per-core outputs. - lp1_cmo_req_o = '0; - lp1_cmo_valid_o = '0; - - for (int unsigned c = 0; c < NumCores; c++) begin - // Present the requested op/addr for this core's injector. - lp1_cmo_req_o[c].op = reg2hw.cfg_lp1_cmo[c].q; - lp1_cmo_req_o[c].addr = reg2hw.cfg_lp1_cmo_addr[c].q; - - // Issue when committed and not already in flight. - if (reg2hw.lp1_cmo_commit[c].q && !lp1_cmo_lock_q[c]) begin - lp1_cmo_valid_o[c] = 1'b1; - lp1_cmo_lock_d[c] = 1'b1; - hw2reg.lp1_cmo_commit[c].d = 1'b0; // self-clear the commit - hw2reg.lp1_cmo_commit[c].de = 1'b1; - end - - // Clear the lock when the injector signals completion. - if (lp1_cmo_done_i[c]) begin - lp1_cmo_lock_d[c] = 1'b0; - end - - // Busy/done status polled by the runtime. - hw2reg.lp1_cmo_status[c].d = lp1_cmo_lock_q[c]; - end - end - - `FF(lp1_cmo_lock_q, lp1_cmo_lock_d, '0, clk_i, rst_ni) - // Enable icache prefetch assign icache_prefetch_enable_o = reg2hw.icache_prefetch_enable.q; diff --git a/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson b/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson index 0a7a719..b704be8 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson +++ b/hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson @@ -9,19 +9,6 @@ type: "int", default: "2" }, - { name: "NumLp1CmoRegs", - desc: '''Number of per-core LP1 (private-L1) CMO register slots -- one per core / - per private L1. Core `cid` uses slot `cid`, so this MUST be >= the - target config's total core count; otherwise cores with cid >= this - value spin forever on LP1_CMO_STATUS (their slot is never decoded) - -> cluster barrier deadlock. This is regenerated per config by - `make update-periph-reg`, which overrides this default with num_cores - (32 for 2g/4g, 64 for *_tiny, 256 for full 16g). The default below is - only a safe max for a standalone regtool run; the block still fits the - 64 kB ClusterPeriphSize window at 256.''', - type: "int", - default: "256" - }, ], name: "cachepool_peripheral", clock_primary: "clk_i", @@ -240,90 +227,5 @@ desc: "Commit the xbar offset configurations." }] }, - // --------------------------------------------------------------------------- - // Per-core private-L1 (LP1) CMO trigger block. - // Vectorized per core (multireg, one slot per core) so that independent cores - // running unrelated critical sections can issue CMOs concurrently without - // racing on a shared trigger register. Mirrors the CFG_L1D_INSN / - // L1D_INSN_COMMIT / L1D_FLUSH_STATUS handshake, one instance per core. - // Software: core `cid` writes CFG_LP1_CMO[cid] (+ CFG_LP1_CMO_ADDR[cid] for - // INVAL_NLINE), pulses LP1_CMO_COMMIT[cid], then polls LP1_CMO_STATUS[cid]. - // --------------------------------------------------------------------------- - { - multireg: { - name: "CFG_LP1_CMO", - desc: '''Per-core LP1 CMO opcode. 0 = FENCE (write-through WBUF drain), - 1 = INVAL_ALL, 2 = INVAL_NLINE. Paired with CFG_LP1_CMO_ADDR - (INVAL_NLINE only) and triggered by LP1_CMO_COMMIT.''' - swaccess: "rw", - hwaccess: "hro", - count: "NumLp1CmoRegs", - cname: "cfg_lp1_cmo", - compact: "false", - resval: "0", - fields: [{ - bits: "2:0", - name: "OP", - desc: "CMO opcode: 0=FENCE, 1=INVAL_ALL, 2=INVAL_NLINE." - }] - } - }, - { - multireg: { - name: "CFG_LP1_CMO_ADDR", - desc: '''Per-core cacheline address for LP1 INVAL_NLINE. Ignored for - FENCE / INVAL_ALL.''' - swaccess: "rw", - hwaccess: "hro", - count: "NumLp1CmoRegs", - cname: "cfg_lp1_cmo_addr", - compact: "false", - resval: "0", - fields: [{ - bits: "31:0", - name: "ADDR", - desc: "Cacheline address for INVAL_NLINE." - }] - } - }, - { - multireg: { - name: "LP1_CMO_COMMIT", - desc: '''Per-core LP1 CMO trigger. SW writes 1 to commit the opcode in - CFG_LP1_CMO[cid]; hardware clears it to 0 once the CMO is accepted - (mirrors L1D_INSN_COMMIT).''' - swaccess: "rw", - hwaccess: "hrw", - count: "NumLp1CmoRegs", - cname: "lp1_cmo_commit", - compact: "false", - resval: "0", - fields: [{ - bits: "0", - name: "COMMIT", - desc: "Commit/trigger the CMO for this core." - }] - } - }, - { - multireg: { - name: "LP1_CMO_STATUS", - desc: '''Per-core LP1 CMO status. High while this core's CMO is in flight; - Low when idle/complete. Polled by the runtime (like - L1D_FLUSH_STATUS).''' - hwext: "true", - swaccess: "ro", - hwaccess: "hwo", - count: "NumLp1CmoRegs", - cname: "lp1_cmo_status", - compact: "false", - resval: "0", - fields: [{ - bits: "0:0", - name: "STATUS", - desc: "High for running CMO; Low for idle/complete." - }] - } - } ] } diff --git a/hardware/src/cachepool_cc.sv b/hardware/src/cachepool_cc.sv index 1950cd6..cc87a24 100644 --- a/hardware/src/cachepool_cc.sv +++ b/hardware/src/cachepool_cc.sv @@ -110,6 +110,11 @@ module cachepool_cc input tcdm_rsp_t [TCDMPorts-1:0] tcdm_rsp_i, // Core event strobes output core_events_t core_events_o, + // Per-core private-L1 (LP1) CMO trigger, driven from the core via CSR. + output logic lp1_cmo_valid_o, + output logic [2:0] lp1_cmo_op_o, + output logic [31:0] lp1_cmo_addr_o, + input logic lp1_cmo_done_i, input addr_t tcdm_addr_base_i ); @@ -211,6 +216,10 @@ module cachepool_cc .fpu_rnd_mode_o (fpu_rnd_mode ), .fpu_fmt_mode_o (fpu_fmt_mode ), .fpu_status_i (fpu_status ), + .lp1_cmo_valid_o (lp1_cmo_valid_o ), + .lp1_cmo_op_o (lp1_cmo_op_o ), + .lp1_cmo_addr_o (lp1_cmo_addr_o ), + .lp1_cmo_done_i (lp1_cmo_done_i ), .core_events_o (snitch_events ) ); diff --git a/hardware/src/cachepool_cluster.sv b/hardware/src/cachepool_cluster.sv index 775ab9c..0cd1ae3 100644 --- a/hardware/src/cachepool_cluster.sv +++ b/hardware/src/cachepool_cluster.sv @@ -202,10 +202,6 @@ module cachepool_cluster logic [NumTiles-1:0] l1d_insn_ready; logic [NumTiles-1:0] l1d_busy; logic [$clog2(NumL1CtrlTile):0] l1d_private; - // Per-core private-L1 (LP1) CMO injector bundle (one slot per core). - lp1_cmo_req_t [NumCores-1:0] lp1_cmo_req; - logic [NumCores-1:0] lp1_cmo_valid; - logic [NumCores-1:0] lp1_cmo_done; // Per-group error signals. logic [NumGroups-1:0] group_error; @@ -302,9 +298,6 @@ module cachepool_cluster .l1d_insn_valid_i ( l1d_insn_valid ), .l1d_insn_ready_o ( l1d_insn_ready[g*NumTilesPerGroup +: NumTilesPerGroup]), .l1d_busy_i ( l1d_busy [g*NumTilesPerGroup +: NumTilesPerGroup]), - .lp1_cmo_req_i ( lp1_cmo_req [g*NumCoreGroup +: NumCoreGroup] ), - .lp1_cmo_valid_i ( lp1_cmo_valid[g*NumCoreGroup +: NumCoreGroup] ), - .lp1_cmo_done_o ( lp1_cmo_done [g*NumCoreGroup +: NumCoreGroup] ), .group_xy_id_i ( group_xy_id_t'{x: gx, y: gy, port_id: 1'b0} ), @@ -766,8 +759,7 @@ module cachepool_cluster .NumCores (NumCores ), .reg_req_t (reg_req_t ), .reg_rsp_t (reg_rsp_t ), - .cache_insn_t (cache_insn_t ), - .lp1_cmo_req_t (lp1_cmo_req_t ) + .cache_insn_t (cache_insn_t ) ) i_cachepool_cluster_peripheral ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -787,10 +779,7 @@ module cachepool_cluster .l1d_insn_o (l1d_insn ), .l1d_insn_valid_o (l1d_insn_valid ), .l1d_insn_ready_i (l1d_insn_ready ), - .l1d_busy_o (l1d_busy ), - .lp1_cmo_req_o (lp1_cmo_req ), - .lp1_cmo_valid_o (lp1_cmo_valid ), - .lp1_cmo_done_i (lp1_cmo_done ) + .l1d_busy_o (l1d_busy ) ); endmodule diff --git a/hardware/src/cachepool_group.sv b/hardware/src/cachepool_group.sv index 0484427..6821088 100644 --- a/hardware/src/cachepool_group.sv +++ b/hardware/src/cachepool_group.sv @@ -145,10 +145,6 @@ module cachepool_group input logic l1d_insn_valid_i, output logic [NumTilesPerGroup-1:0] l1d_insn_ready_o, input logic [NumTilesPerGroup-1:0] l1d_busy_i, - // Per-core private-L1 (LP1) CMO injector interface (one slot per core in group). - input lp1_cmo_req_t [NumCoreGroup-1:0] lp1_cmo_req_i, - input logic [NumCoreGroup-1:0] lp1_cmo_valid_i, - output logic [NumCoreGroup-1:0] lp1_cmo_done_o, /// Inter-group remote access ports (to other groups). /// Layout: [NumTilesPerGroup-1:0][NumRemoteGroupPortTile-1:0] flattened to @@ -791,10 +787,7 @@ module cachepool_group .l1d_private_i ( l1d_private_i ), .l1d_insn_valid_i ( l1d_insn_valid_i ), .l1d_insn_ready_o ( l1d_insn_ready_o [t] ), - .l1d_busy_i ( l1d_busy_i [t] ), - .lp1_cmo_req_i ( lp1_cmo_req_i [t*NumCoresTile +: NumCoresTile] ), - .lp1_cmo_valid_i ( lp1_cmo_valid_i [t*NumCoresTile +: NumCoresTile] ), - .lp1_cmo_done_o ( lp1_cmo_done_o [t*NumCoresTile +: NumCoresTile] ) + .l1d_busy_i ( l1d_busy_i [t] ) ); end else begin : gen_tile cachepool_tile #( @@ -880,10 +873,7 @@ module cachepool_group .l1d_private_i ( l1d_private_i ), .l1d_insn_valid_i ( l1d_insn_valid_i ), .l1d_insn_ready_o ( l1d_insn_ready_o [t] ), - .l1d_busy_i ( l1d_busy_i [t] ), - .lp1_cmo_req_i ( lp1_cmo_req_i [t*NumCoresTile +: NumCoresTile] ), - .lp1_cmo_valid_i ( lp1_cmo_valid_i [t*NumCoresTile +: NumCoresTile] ), - .lp1_cmo_done_o ( lp1_cmo_done_o [t*NumCoresTile +: NumCoresTile] ) + .l1d_busy_i ( l1d_busy_i [t] ) ); end end diff --git a/hardware/src/cachepool_group_noc_wrapper.sv b/hardware/src/cachepool_group_noc_wrapper.sv index 8c9fbf9..b15b16c 100644 --- a/hardware/src/cachepool_group_noc_wrapper.sv +++ b/hardware/src/cachepool_group_noc_wrapper.sv @@ -79,10 +79,6 @@ module cachepool_group_noc_wrapper input logic l1d_insn_valid_i, output logic [NumTilesPerGroup-1:0] l1d_insn_ready_o, input logic [NumTilesPerGroup-1:0] l1d_busy_i, - // Per-core private-L1 (LP1) CMO injector interface (one slot per core in group). - input lp1_cmo_req_t [NumCoreGroup-1:0] lp1_cmo_req_i, - input logic [NumCoreGroup-1:0] lp1_cmo_valid_i, - output logic [NumCoreGroup-1:0] lp1_cmo_done_o, input impl_in_t [NrSramCfg-1:0] impl_i, output logic error_o, // XY coordinates of this group in the inter-group mesh @@ -596,10 +592,7 @@ module cachepool_group_noc_wrapper .l1d_insn_i ( l1d_insn_i ), .l1d_insn_valid_i ( l1d_insn_valid_i ), .l1d_insn_ready_o ( l1d_insn_ready_o ), - .l1d_busy_i ( l1d_busy_i ), - .lp1_cmo_req_i ( lp1_cmo_req_i ), - .lp1_cmo_valid_i ( lp1_cmo_valid_i ), - .lp1_cmo_done_o ( lp1_cmo_done_o ) + .l1d_busy_i ( l1d_busy_i ) ); endmodule diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv index e52e0a1..a59d7cb 100644 --- a/hardware/src/cachepool_l1_ctrl.sv +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -87,10 +87,10 @@ module cachepool_l1_ctrl input logic rst_ni, input logic wbuf_flush_i, - // Per-core CMO injector interface (driven by the cluster peripheral). - // lp1_cmo_valid_i pulses for one cycle to request the CMO in lp1_cmo_req_i; - // lp1_cmo_done_o pulses when the CMO has completed (used to clear the - // peripheral's per-core busy/status bit). FSM implemented in Task 3. + // Per-core CMO injector interface (driven by this core via CSR_LP1CMO). + // lp1_cmo_valid_i is held while a `csrw CSR_LP1CMO` stalls the core; it + // requests the CMO in lp1_cmo_req_i. lp1_cmo_done_o pulses when the CMO has + // completed, which releases the core's stall. input lp1_cmo_req_t lp1_cmo_req_i, input logic lp1_cmo_valid_i, output logic lp1_cmo_done_o, @@ -446,17 +446,17 @@ module cachepool_l1_ctrl ////////////////////////////////////////// // HPDcache requester 2 (CMO injector) // ////////////////////////////////////////// - // Converts the peripheral's one-cycle lp1_cmo_valid_i pulse into an HPDcache - // CMO on requester port 2, then reports completion via lp1_cmo_done_o (which - // clears the peripheral's per-core busy/status bit). Single outstanding CMO - // per core (the peripheral won't issue a new one until done), so no flow - // control is needed on the incoming pulse -- it is latched here. + // Converts the core's lp1_cmo_valid_i request (asserted by a `csrw CSR_LP1CMO` + // that stalls the core) into an HPDcache CMO on requester port 2, then reports + // completion via lp1_cmo_done_o, which releases the core's stall. The core + // holds only one CMO in flight (it is blocked until done), so no flow control + // is needed on the request -- it is latched here. // // IDLE : wait for lp1_cmo_valid_i; decode + latch op/addr. // REQ : hold l1_req_valid[2] until l1_req_ready[2] accepts the request. // RESP : wait for l1_rsp_valid[2]; pulse lp1_cmo_done_o; return to IDLE. // - // lp1_cmo_req_i.op encoding (from the peripheral register block): + // lp1_cmo_req_i.op encoding (from the core's CSR write): // 0 = FENCE (write-through WBUF drain), 1 = INVAL_ALL, 2 = INVAL_NLINE localparam int unsigned CmoReqId = 2; diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index 9d5e804..8615d1c 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -174,12 +174,6 @@ module cachepool_tile input logic l1d_insn_valid_i, output logic l1d_insn_ready_o, input logic l1d_busy_i, - // Per-core private-L1 (LP1) CMO injector interface (one slot per core). - input lp1_cmo_req_t [NumCoresTile-1:0] lp1_cmo_req_i, - input logic [NumCoresTile-1:0] lp1_cmo_valid_i, - output logic [NumCoresTile-1:0] lp1_cmo_done_o, - - /// SRAM Configuration Ports, usually not used. input impl_in_t [NrSramCfg-1:0] impl_i, @@ -543,6 +537,17 @@ module cachepool_tile tcdm_rsp_t [NumLP1CacheCtrl-1:0][NrTCDMPortsPerCore-1:0] cache_rsp_transposed; logic [NumLP1CacheCtrl-1:0][NrTCDMPortsPerCore-1:0] lp1_cache_rsp_ready, lp1_cache_req_ready; + // Per-core private-L1 (LP1) CMO trigger, sourced from each core's CSR (i.e. + // the CSR-driven path that replaces the peripheral one). core i owns l1_ctrl i. + logic [NumLP1CacheCtrl-1:0] core_cmo_valid; + logic [NumLP1CacheCtrl-1:0] core_cmo_done; + logic [NumLP1CacheCtrl-1:0][2:0] core_cmo_op; + logic [NumLP1CacheCtrl-1:0][31:0] core_cmo_addr; + lp1_cmo_req_t [NumLP1CacheCtrl-1:0] core_cmo_req; + for (genvar c = 0; c < NumLP1CacheCtrl; c++) begin : gen_core_cmo_req + assign core_cmo_req[c] = '{op: core_cmo_op[c], addr: core_cmo_addr[c]}; + end + // Collapsed: one cacheline-wide port per L2 controller logic [NumL1CtrlTile-1:0] cache_req_valid; logic [NumL1CtrlTile-1:0] cache_req_ready; @@ -725,10 +730,11 @@ module cachepool_tile .rst_ni (rst_ni ), .wbuf_flush_i (1'b0 ), - // Per-core CMO injector (slot c = this core) - .lp1_cmo_req_i (lp1_cmo_req_i [c]), - .lp1_cmo_valid_i (lp1_cmo_valid_i [c]), - .lp1_cmo_done_o (lp1_cmo_done_o [c]), + // Per-core CMO injector (slot c = this core), now CSR-driven from the core. + // op/addr from the core are packed into the lp1_cmo_req_t the ctrl expects. + .lp1_cmo_req_i (core_cmo_req [c]), + .lp1_cmo_valid_i (core_cmo_valid [c]), + .lp1_cmo_done_o (core_cmo_done [c]), // Core side (NrTCDMPortsPerCore narrow TCDM ports for this core) .core_req_i (cache_req_transposed [c]), @@ -1616,6 +1622,10 @@ module cachepool_tile .tcdm_req_o (tcdm_req_wo_user ), .tcdm_rsp_i (tcdm_rsp[TcdmPortsOffs +: TcdmPorts]), .core_events_o (core_events[i] ), + .lp1_cmo_valid_o (core_cmo_valid[i] ), + .lp1_cmo_op_o (core_cmo_op[i] ), + .lp1_cmo_addr_o (core_cmo_addr[i] ), + .lp1_cmo_done_i (core_cmo_done[i] ), .tcdm_addr_base_i (tcdm_start_address ) ); for (genvar j = 0; j < TcdmPorts; j++) begin : gen_tcdm_user diff --git a/software/snRuntime/include/lp1cache.h b/software/snRuntime/include/lp1cache.h index b29fbf0..233340a 100644 --- a/software/snRuntime/include/lp1cache.h +++ b/software/snRuntime/include/lp1cache.h @@ -9,19 +9,16 @@ // // LP1 is the per-core private HPDcache (write-through, no coherence), distinct // from the shared distributed L1D controlled in l1cache.h. These primitives -// drive the per-core CMO (Cache Management Operation) injector so software can -// bracket a critical section: +// issue a per-core CMO (Cache Management Operation) directly from the core via a +// custom CSR (CSR_LP1CMO); the write blocks in hardware until the CMO completes, +// so no status polling is needed. Use them to bracket a critical section: // // amoswap acquire (L2) -> lp1_inval() -> CS -> lp1_wt_flush() -> release (L2) // // Each core acts on its own private L1; call from the core that owns the -// critical section (no barrier -- the register slot is per-core). +// critical section (the CSR is core-local, so no barrier is needed). -#include "encoding.h" -#include "cachepool_peripheral.h" -#include "team.h" - -extern __thread struct snrt_team *_snrt_team_current; +#include void lp1_wt_flush(); // release: drain write-through write buffer void lp1_inval(); // acquire: invalidate the whole private L1 diff --git a/software/snRuntime/src/lp1cache.c b/software/snRuntime/src/lp1cache.c index a25f069..bac959d 100644 --- a/software/snRuntime/src/lp1cache.c +++ b/software/snRuntime/src/lp1cache.c @@ -6,62 +6,43 @@ // Author: Ho Tin Hung, ETH Zurich #include -#include // Software critical-section support for the per-core private L1 (HPDcache). -// Each core owns one register slot [cid] (multireg, stride 4 bytes) so that -// independent cores running unrelated critical sections never contend on a -// shared trigger. A CMO is issued by writing op+addr, pulsing commit, then -// polling status (busy while the injector has a request in flight). +// A CMO is issued directly from the core by writing the custom CSR CSR_LP1CMO; +// the write stalls the core until the CMO has completed at the HPDcache, so no +// commit/status handshake is needed (contrast the earlier peripheral path). // -// op encoding (must match cmo_decode() in cachepool_l1_ctrl.sv): -// 0 = FENCE (write-through WBUF drain -- "flush" under WT policy) -// 1 = INVAL_ALL (invalidate the whole private L1) -// 2 = INVAL_NLINE (invalidate the cacheline covering addr) +// CSR map (must match snitch_pkg.sv / cachepool_l1_ctrl.sv): +// CSR_LP1CMOADDR (0xBC1) : cacheline address for INVAL_NLINE. +// CSR_LP1CMO (0xBC2) : write value = op; the write blocks until done. +// op encoding: 0 = FENCE (write-through WBUF drain -- "flush" under WT) +// 1 = INVAL_ALL (invalidate the whole private L1) +// 2 = INVAL_NLINE (invalidate the cacheline covering addr) #define LP1_CMO_OP_FENCE 0u #define LP1_CMO_OP_INVAL_ALL 1u #define LP1_CMO_OP_INVAL_LINE 2u -// Issue one CMO on this core's slot and block until the injector completes. -static inline void lp1_cmo(uint32_t op, uint32_t addr) { - uint32_t cid = snrt_cluster_core_idx(); - uint64_t base = _snrt_team_current->root->cluster_mem.end; - - volatile uint32_t *op_reg = - (uint32_t *)(base + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_0_REG_OFFSET + - cid * 4); - volatile uint32_t *addr_reg = - (uint32_t *)(base + CACHEPOOL_PERIPHERAL_CFG_LP1_CMO_ADDR_0_REG_OFFSET + - cid * 4); - volatile uint32_t *commit_reg = - (uint32_t *)(base + CACHEPOOL_PERIPHERAL_LP1_CMO_COMMIT_0_REG_OFFSET + - cid * 4); - volatile uint32_t *status_reg = - (uint32_t *)(base + CACHEPOOL_PERIPHERAL_LP1_CMO_STATUS_0_REG_OFFSET + - cid * 4); - - *op_reg = op; - *addr_reg = addr; - // Trigger the injector. The peripheral self-clears commit and raises status. - *commit_reg = 1; - // Wait until the CMO has been accepted and completed by the HPDcache. - while (*status_reg) { - } +// Issue one CMO on this core's private L1 and block until it completes. The +// "memory" clobber also keeps the compiler from reordering loads/stores across +// the CMO, preserving the acquire/release ordering the caller relies on. +static inline void lp1_cmo(uint32_t op) { + asm volatile("csrw 0xBC2, %0" ::"r"(op) : "memory"); } // Release side of a critical section: make all prior private-L1 writes visible // downstream (drain the write-through write buffer) before the L2 release AMO. void lp1_wt_flush() { - lp1_cmo(LP1_CMO_OP_FENCE, 0); + lp1_cmo(LP1_CMO_OP_FENCE); } // Acquire side of a critical section: drop any stale lines so the first reads // inside the section miss and refetch fresh data from L2. void lp1_inval() { - lp1_cmo(LP1_CMO_OP_INVAL_ALL, 0); + lp1_cmo(LP1_CMO_OP_INVAL_ALL); } // Invalidate a single cacheline covering addr (finer-grained than lp1_inval). void lp1_inval_line(uint32_t addr) { - lp1_cmo(LP1_CMO_OP_INVAL_LINE, addr); + asm volatile("csrw 0xBC1, %0" ::"r"(addr) : "memory"); + lp1_cmo(LP1_CMO_OP_INVAL_LINE); } From f1890c25d0dc917c9520249056b0eb9fea7d870a Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Fri, 24 Jul 2026 12:11:18 +0200 Subject: [PATCH 37/39] [HW Bender Makefile] Periph-related clean-up and remove bender local override --- Bender.local | 2 -- hardware/cachepool_peripheral/Makefile | 8 +++----- hardware/cachepool_peripheral/cachepool_peripheral.sv | 2 -- hardware/src/cachepool_cluster.sv | 1 - 4 files changed, 3 insertions(+), 10 deletions(-) diff --git a/Bender.local b/Bender.local index 2ff8279..d563553 100644 --- a/Bender.local +++ b/Bender.local @@ -5,6 +5,4 @@ overrides: axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 } - Insitu-Cache: { path: "../Insitu-Cache" } - hpdcache: { path: "../cv-hpdcache" } diff --git a/hardware/cachepool_peripheral/Makefile b/hardware/cachepool_peripheral/Makefile index d69bc8d..dc79b69 100644 --- a/hardware/cachepool_peripheral/Makefile +++ b/hardware/cachepool_peripheral/Makefile @@ -15,15 +15,13 @@ PKG=cachepool_peripheral_reg_pkg.sv TOP=cachepool_peripheral_reg_top.sv CDEF=$(ROOTDIR)/software/snRuntime/include/cachepool_peripheral.h -REGGEN_PARAMS := - all: $(PKG) $(TOP) $(CDEF) $(PKG): $(SCHEMA) - $(PYTHON3) $(REGTOOL) $(REGGEN_PARAMS) -r -t $(dir $@) $< + $(PYTHON3) $(REGTOOL) -r -t $(dir $@) $< $(TOP): $(SCHEMA) - $(PYTHON3) $(REGTOOL) $(REGGEN_PARAMS) -r -t $(dir $@) $< + $(PYTHON3) $(REGTOOL) -r -t $(dir $@) $< %.h: $(SCHEMA) - $(PYTHON3) $(REGTOOL) $(REGGEN_PARAMS) -D -o $@ $< + $(PYTHON3) $(REGTOOL) -D -o $@ $< $(CLANG_FORMAT) -i $@ diff --git a/hardware/cachepool_peripheral/cachepool_peripheral.sv b/hardware/cachepool_peripheral/cachepool_peripheral.sv index 74d5589..8077342 100644 --- a/hardware/cachepool_peripheral/cachepool_peripheral.sv +++ b/hardware/cachepool_peripheral/cachepool_peripheral.sv @@ -15,8 +15,6 @@ module cachepool_peripheral parameter int unsigned SPMWidth = 0, // Number of tiles (used for flush controller granularity) parameter int unsigned NumTiles = 1, - // Number of cores. - parameter int unsigned NumCores = 1, parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, parameter type cache_insn_t = logic, diff --git a/hardware/src/cachepool_cluster.sv b/hardware/src/cachepool_cluster.sv index 0cd1ae3..e75ff20 100644 --- a/hardware/src/cachepool_cluster.sv +++ b/hardware/src/cachepool_cluster.sv @@ -756,7 +756,6 @@ module cachepool_cluster .AddrWidth (AxiAddrWidth ), .SPMWidth ($clog2(L1NumSet)), .NumTiles (NumTiles ), - .NumCores (NumCores ), .reg_req_t (reg_req_t ), .reg_rsp_t (reg_rsp_t ), .cache_insn_t (cache_insn_t ) From 324fa1021a104f89430bef00a69ada31a496d511 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Fri, 24 Jul 2026 12:12:50 +0200 Subject: [PATCH 38/39] [Bender] bender.lock local dep replaced --- Bender.lock | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Bender.lock b/Bender.lock index 8c1a32f..988b6a9 100644 --- a/Bender.lock +++ b/Bender.lock @@ -97,10 +97,10 @@ packages: dependencies: - common_cells hpdcache: - revision: null + revision: 957e6f9b30dd5516b57cca3326f3f32e4357cf1b version: null source: - Path: ../cv-hpdcache + Git: https://github.com/HHT1228/cv-hpdcache.git dependencies: [] idma: revision: 28a36e5e07705549e59fc33db96ab681bc1ca88e @@ -115,10 +115,10 @@ packages: - obi - register_interface insitu-cache: - revision: null + revision: 129174e095db1f64136a02735ea9617dc2e29d6c version: null source: - Path: ../Insitu-Cache + Git: https://github.com/HHT1228/Insitu-Cache.git dependencies: - axi - common_cells @@ -156,7 +156,7 @@ packages: dependencies: - tech_cells_generic spatz: - revision: 14e3e884366ce0e4987c22c36510fa71a369a89b + revision: 6170425f91422aa1daa3b9d8e34cda41f2c05b32 version: null source: Git: https://github.com/HHT1228/spatz.git From 566dec5e8a9ae4ee440e3ffd792f979d50a90225 Mon Sep 17 00:00:00 2001 From: HHT1228 Date: Thu, 30 Jul 2026 15:22:51 +0200 Subject: [PATCH 39/39] [HW] HW code clean-up and cachepool_hpd_pkg created --- Bender.yml | 2 + hardware/src/cachepool_hpd_pkg.sv | 133 ++++++++++++++++++++++++++ hardware/src/cachepool_l1_ctrl.sv | 98 +++++++------------ hardware/src/cachepool_pkg.sv | 2 - hardware/src/cachepool_tile.sv | 153 ++++-------------------------- 5 files changed, 183 insertions(+), 205 deletions(-) create mode 100644 hardware/src/cachepool_hpd_pkg.sv diff --git a/Bender.yml b/Bender.yml index fd35f57..e3b216d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -43,6 +43,8 @@ sources: - hardware/bootrom/bootrom.sv # Level 1 - hardware/src/cachepool_pkg.sv + # Private L1 (LP1) HPDcache config & shared types — after cachepool_pkg, before its users + - hardware/src/cachepool_hpd_pkg.sv - hardware/src/cachepool_cc.sv # Private L1 data cache (per-core HPDcache wrapper) — must precede the tile - hardware/src/cachepool_l1_ctrl.sv diff --git a/hardware/src/cachepool_hpd_pkg.sv b/hardware/src/cachepool_hpd_pkg.sv new file mode 100644 index 0000000..bbb43f2 --- /dev/null +++ b/hardware/src/cachepool_hpd_pkg.sv @@ -0,0 +1,133 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Ho Tin Hung, ETH Zurich +// +// Private L1 (LP1) HPDcache configuration, geometry and type definitions. +// +// Everything the per-core private-L1 datapath needs to agree on lives here so +// that the tile (cachepool_tile) and the controller (cachepool_l1_ctrl) share a +// single definition instead of threading ~30 `parameter type`s across the +// hierarchy. All inputs resolve to global package constants +// (cachepool_pkg / spatz_pkg / hpdcache_pkg), so this content is elaboration- +// time constant and does not depend on any module instance. + +`include "hpdcache_typedef.svh" + +package cachepool_hpd_pkg; + import cachepool_pkg::*; + import hpdcache_pkg::*; + + // Physical-address width seen by the private L1 (TCDM address space). + localparam int unsigned TCDMAddrWidth = 32; + + //////////////////////////////////////////// + // Private L1 (LP1) HPDcache config & types // + //////////////////////////////////////////// + + // Spatz coalescer geometry + localparam int unsigned NrLP1CoalInputs = NrTCDMPortsPerCore - 1; // Spatz lanes + localparam int unsigned LP1ExtPorts = NrLP1CoalInputs; + localparam int unsigned LP1WordWidth = 128; // HPDcache word width + localparam int unsigned LP1NrBitsCoalOffset = $clog2(LP1WordWidth/spatz_pkg::DataWidth); // coalescer offset_t width + localparam int unsigned LP1NumWordOffsetBits = $clog2(LP1WordWidth/spatz_pkg::DataWidth); // tid word-offset field + localparam int unsigned LP1CoalInfoWidth = LP1ExtPorts + LP1ExtPorts*LP1NrBitsCoalOffset; + localparam int unsigned LP1ReqIdWidth = $clog2(NumSpatzOutstandingLoads); + localparam int unsigned LP1TidWidth = CoreIDWidth + TileIDWidth + LP1ReqIdWidth + 2 + LP1CoalInfoWidth; // +2: is_fpu, write; tile_id+core_id round-tripped + localparam int unsigned LP1NrRequesters = 3; // Spatz(coalesced) + Snitch + CMO injector + localparam int unsigned LP1NumSets = 16; + localparam int unsigned LP1NumWays = 4; + localparam int unsigned LP1NumWordsPerLine = 4; + + localparam hpdcache_pkg::hpdcache_user_cfg_t HPDcacheUserCfg = '{ + nRequesters: LP1NrRequesters, + paWidth: TCDMAddrWidth, + wordWidth: LP1WordWidth, + sets: LP1NumSets, + ways: LP1NumWays, + clWords: LP1NumWordsPerLine, + reqWords: 1, + reqTransIdWidth: LP1TidWidth + LP1NumWordOffsetBits, + reqSrcIdWidth: $clog2(LP1NrRequesters), // selects requester port (0 Spatz / 1 Snitch / 2 CMO) + victimSel: hpdcache_pkg::HPDCACHE_VICTIM_RANDOM, + dataWaysPerRamWord: 1, + dataSetsPerRam: LP1NumSets, + dataRamByteEnable: 1'b1, + accessWords: LP1NumWordsPerLine, + mshrSets: 4, + mshrWays: 4, + mshrWaysPerRamWord: 4, + mshrSetsPerRam: 4, + mshrRamByteEnable: 1'b1, + mshrUseRegbank: 1'b1, + cbufEntries: 2, + refillCoreRspFeedthrough: 1'b1, + refillFifoDepth: 2, + wbufDirEntries: 4, + wbufDataEntries: 4, + wbufWords: 4, + wbufTimecntWidth: 3, + rtabEntries: 4, + flushEntries: 2, + flushFifoDepth: 2, + memAddrWidth: L1AddrWidth, + // memIdWidth: LP1TidWidth, + memIdWidth: $clog2(NumSpatzOutstandingLoads), + memDataWidth: L1LineWidth, + wtEn: 1'b1, // write-through + wbEn: 1'b0, + lowLatency: 1'b1, + eccEn: 1'b0, + eccScrubberEn: 1'b0 + }; + localparam hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg = hpdcacheBuildConfig(HPDcacheUserCfg); + + // The metadata type used to restore the information from req to rsp. + // (extended with `amo` for the private-L1 datapath) + typedef struct packed { + tcdm_user_t user; + logic write; + hpdcache_req_op_t amo; + } tcdm_meta_t; + + // HPDcache request-side typedefs + typedef logic [HPDcacheCfg.tagWidth-1:0] hpdcache_tag_t; + typedef logic [HPDcacheCfg.u.wordWidth-1:0] hpdcache_data_word_t; + typedef logic [HPDcacheCfg.u.wordWidth/8-1:0] hpdcache_data_be_t; + typedef logic [HPDcacheCfg.reqOffsetWidth-1:0] hpdcache_req_offset_t; + typedef hpdcache_data_word_t [HPDcacheCfg.u.reqWords-1:0] hpdcache_req_data_t; + typedef hpdcache_data_be_t [HPDcacheCfg.u.reqWords-1:0] hpdcache_req_be_t; + typedef logic [HPDcacheCfg.u.reqSrcIdWidth-1:0] hpdcache_req_sid_t; + typedef logic [HPDcacheCfg.u.reqTransIdWidth-1:0] hpdcache_req_tid_t; + `HPDCACHE_TYPEDEF_REQ_T(hpdcache_req_t, hpdcache_req_offset_t, hpdcache_req_data_t, + hpdcache_req_be_t, hpdcache_req_sid_t, hpdcache_req_tid_t, hpdcache_tag_t); + `HPDCACHE_TYPEDEF_RSP_T(hpdcache_rsp_t, hpdcache_req_data_t, hpdcache_req_sid_t, hpdcache_req_tid_t); + typedef logic [HPDcacheCfg.u.wbufTimecntWidth-1:0] hpdcache_wbuf_timecnt_t; + + // HPDcache memory-side typedefs (L1 -> L2 mem channels) + typedef logic [HPDcacheCfg.u.memAddrWidth-1:0] hpdcache_mem_addr_t; + typedef logic [HPDcacheCfg.u.memIdWidth-1:0] hpdcache_mem_id_t; + typedef logic [HPDcacheCfg.u.memDataWidth-1:0] hpdcache_mem_data_t; + typedef logic [HPDcacheCfg.u.memDataWidth/8-1:0] hpdcache_mem_be_t; + `HPDCACHE_TYPEDEF_MEM_REQ_T(hpdcache_mem_req_t, hpdcache_mem_addr_t, hpdcache_mem_id_t); + `HPDCACHE_TYPEDEF_MEM_RESP_R_T(hpdcache_mem_resp_r_t, hpdcache_mem_id_t, hpdcache_mem_data_t); + `HPDCACHE_TYPEDEF_MEM_REQ_W_T(hpdcache_mem_req_w_t, hpdcache_mem_data_t, hpdcache_mem_be_t); + `HPDCACHE_TYPEDEF_MEM_RESP_W_T(hpdcache_mem_resp_w_t, hpdcache_mem_id_t); + + // Spatz request coalescer types. downstream_info_t MUST match + // par_coalescer_top's internal struct exactly: + // { down_id_t id; logic[ExtPorts] hitmap; offset_t[ExtPorts] ofsts; + // info_t[ExtPorts] infos; logic bypass_coalescer } + // with down_id_t = logic, offset_t = logic[$clog2(Down/Up)-1:0], info_t = tcdm_meta_t. + typedef logic [LP1NrBitsCoalOffset-1:0] lp1_offset_t; + typedef logic [LP1NumWordOffsetBits-1:0] word_offset_t; + typedef struct packed { + logic id; + logic [LP1ExtPorts-1:0] hitmap; + lp1_offset_t [LP1ExtPorts-1:0] ofsts; + tcdm_meta_t [LP1ExtPorts-1:0] infos; + logic bypass_coalescer; + } downstream_info_t; + +endpackage diff --git a/hardware/src/cachepool_l1_ctrl.sv b/hardware/src/cachepool_l1_ctrl.sv index a59d7cb..593dc13 100644 --- a/hardware/src/cachepool_l1_ctrl.sv +++ b/hardware/src/cachepool_l1_ctrl.sv @@ -20,9 +20,9 @@ // No cache coherence is implemented here. Write-through narrows but does not // close the cross-core shared-data window; that is accepted for now. // -// Coalescer metadata has no package; all coalescer-facing types (tcdm_meta_t, -// downstream_info_t, word_offset_t, ...) are defined at the tile and passed in -// as parameters. +// The HPDcache config and all coalescer-facing types (HPDcacheCfg, tcdm_meta_t, +// downstream_info_t, word_offset_t, hpdcache_*_t, ...) live in cachepool_hpd_pkg +// and are imported below, shared with cachepool_tile. `include "axi/typedef.svh" `include "common_cells/assertions.svh" `include "common_cells/registers.svh" @@ -32,56 +32,33 @@ module cachepool_l1_ctrl import cachepool_pkg::*; + import cachepool_hpd_pkg::*; import hpdcache_pkg::*; import reqrsp_pkg::*; #( // Core-side topology - parameter int unsigned NrTCDMPortsPerCore = 5, // Spatz lanes + 1 Snitch - parameter int unsigned DataWidth = 32, // narrow (per-lane) data width + + // Spatz lanes + 1 Snitch + parameter int unsigned NrTCDMPortsPerCore = 5, + // narrow (per-lane) data width + parameter int unsigned DataWidth = 32, parameter int unsigned ByteWidth = 8, - // tid / coalescer geometry (must match the types below) - parameter int unsigned LP1NumWordOffsetBits = 2, // $clog2(wordWidth/DataWidth) - parameter int unsigned LP1NrBitsCoalOffset = 2, // bits per coalescer ofst entry - // (lane count is NrLP1CoalInputs, derived below) + // tid / coalescer geometry (must match the types below)s + // $clog2(wordWidth/DataWidth) + parameter int unsigned LP1NumWordOffsetBits = 2, + // bits per coalescer ofst entry + parameter int unsigned LP1NrBitsCoalOffset = 2, - parameter hpdcache_cfg_t HPDcacheCfg = '0, parameter type wbuf_timecnt_t = logic, // Core-side TCDM request/response parameter type l1_cache_req_t = logic, parameter type l1_cache_rsp_t = logic, - // Coalescer payload types (defined at tile) - parameter type tcdm_meta_t = logic, // { tcdm_user_t user; logic write; hpdcache_req_op_t amo; } - parameter type downstream_info_t = logic, // par_coalescer_top downstream info struct - parameter type word_offset_t = logic, // logic[LP1NumWordOffsetBits-1:0] - // Downstream (L2) TCDM request/response parameter type l2_cache_req_t = logic, - parameter type l2_cache_rsp_t = logic, - - // HPDcache request interface types - parameter type hpdcache_tag_t = logic, - parameter type hpdcache_data_word_t = logic, - parameter type hpdcache_data_be_t = logic, - parameter type hpdcache_req_offset_t = logic, - parameter type hpdcache_req_data_t = logic, - parameter type hpdcache_req_be_t = logic, - parameter type hpdcache_req_sid_t = logic, - parameter type hpdcache_req_tid_t = logic, - parameter type hpdcache_req_t = logic, - parameter type hpdcache_rsp_t = logic, - - // HPDcache memory interface types - parameter type hpdcache_mem_addr_t = logic, - parameter type hpdcache_mem_id_t = logic, - parameter type hpdcache_mem_data_t = logic, - parameter type hpdcache_mem_be_t = logic, - parameter type hpdcache_mem_req_t = logic, - parameter type hpdcache_mem_req_w_t = logic, - parameter type hpdcache_mem_resp_r_t = logic, - parameter type hpdcache_mem_resp_w_t = logic + parameter type l2_cache_rsp_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -106,7 +83,7 @@ module cachepool_l1_ctrl // Downstream (L2) TCDM interface output l2_cache_req_t l2_req_o, input l2_cache_rsp_t l2_rsp_i, - output logic l2_rsp_ready_o, // response ready -> interco core_rsp_ready_i + output logic l2_rsp_ready_o, // Performance events output logic evt_cache_write_miss_o, @@ -147,10 +124,10 @@ module cachepool_l1_ctrl //////////////// // PARAMETERS // //////////////// - localparam int unsigned NrLP1CoalInputs = NrTCDMPortsPerCore - 1; // Spatz lanes - localparam int unsigned SnitchPort = NrTCDMPortsPerCore - 1; // last port - localparam int unsigned coalescedDataWidth = HPDcacheCfg.u.wordWidth; // wide word - localparam int unsigned LaneBytes = DataWidth / ByteWidth; // bytes per lane word + localparam int unsigned NrLP1CoalInputs = NrTCDMPortsPerCore - 1; + localparam int unsigned SnitchPort = NrTCDMPortsPerCore - 1; + localparam int unsigned coalescedDataWidth = HPDcacheCfg.u.wordWidth; + localparam int unsigned LaneBytes = DataWidth / ByteWidth; localparam int unsigned WordBytes = coalescedDataWidth / ByteWidth; // tid layout (one fixed, non-overlapping scheme), MSB -> LSB: @@ -164,7 +141,8 @@ module cachepool_l1_ctrl localparam int unsigned HitmapW = NrLP1CoalInputs; localparam int unsigned OfstsW = NrLP1CoalInputs * LP1NrBitsCoalOffset; localparam int unsigned CoalInfoW = HitmapW + OfstsW; - localparam int unsigned TidUserW = CoreIDWidth + TileIDWidth + ReqIdW + 2; // {is_fpu,tile_id,core_id,write,req_id} + // {is_fpu,tile_id,core_id,write,req_id} + localparam int unsigned TidUserW = CoreIDWidth + TileIDWidth + ReqIdW + 2; localparam int unsigned HitmapLsb = 0; localparam int unsigned OfstsLsb = HitmapW; localparam int unsigned ReqIdLsb = CoalInfoW; @@ -233,7 +211,7 @@ module cachepool_l1_ctrl hpdcache_mem_req_t l1_mem_req_read, l1_mem_req_write, l1_l2_req; hpdcache_mem_req_w_t l1_mem_req_write_data; logic l1_mem_req_read_valid, l1_mem_req_read_ready; - logic l1_mem_req_write_valid, l1_mem_req_write_ready, __l1_mem_req_write_ready; + logic l1_mem_req_write_valid, l1_mem_req_write_ready, l1_mem_req_write_gnt; logic l1_mem_req_write_data_valid, l1_mem_req_write_data_ready; logic l1_mem_req_write_both_valid; logic l1_l2_req_valid; @@ -311,7 +289,7 @@ module cachepool_l1_ctrl // Coalescer info payload (carried per lane, returned with the response). assign cache_req_info[i].user.core_id = cache_req_coreid[i]; - assign cache_req_info[i].user.tile_id = cache_req_tileid[i]; // round-tripped for core rsp + assign cache_req_info[i].user.tile_id = cache_req_tileid[i]; assign cache_req_info[i].user.is_amo = (cache_req_amo[i] != AMONone); assign cache_req_info[i].user.req_id = cache_req_reqid[i]; assign cache_req_info[i].user.is_fpu = cache_req_is_fpu[i]; @@ -382,26 +360,14 @@ module cachepool_l1_ctrl end end - // BE for the coalesced (wide) request: use the coalescer's wmask - // logic [WordBytes-1:0] coal_be; - // always_comb begin : gen_coal_be - // coal_be = '0; - // for (int unsigned id = 0; id < NrLP1CoalInputs; id++) begin - // if (coal_req_info.hitmap[id]) begin - // coal_be |= ({LaneBytes{1'b1}} << (id * LaneBytes)); - // end - // end - // end - always_comb begin : gen_l1_req_spatz l1_req[0] = '0; l1_req[0].addr_offset = coal_req_addr[HPDcacheCfg.reqOffsetWidth-1:0]; l1_req[0].addr_tag = coal_req_addr[HPDcacheCfg.reqOffsetWidth +: HPDcacheCfg.tagWidth]; l1_req[0].wdata = coal_req_wdata; l1_req[0].be = coal_req_wmask; - // l1_req[0].be = coal_req_write ? coal_req_wmask : coal_be; l1_req[0].size = hpdcache_req_size_t'($clog2(coalescedDataWidth/8)); - l1_req[0].sid = hpdcache_req_sid_t'(0); // Spatz + l1_req[0].sid = hpdcache_req_sid_t'(0); l1_req[0].need_rsp = 1'b1; l1_req[0].phys_indexed = 1'b1; l1_req[0].pma.uncacheable = 1'b0; @@ -488,7 +454,7 @@ module cachepool_l1_ctrl l1_req[CmoReqId].addr_tag = cmo_addr_q[HPDcacheCfg.reqOffsetWidth +: HPDcacheCfg.tagWidth]; l1_req[CmoReqId].sid = hpdcache_req_sid_t'(CmoReqId); l1_req[CmoReqId].tid = '0; - l1_req[CmoReqId].need_rsp = 1'b1; // required: how we learn it completed + l1_req[CmoReqId].need_rsp = 1'b1; l1_req[CmoReqId].phys_indexed = 1'b1; l1_req[CmoReqId].pma.uncacheable = 1'b0; l1_req[CmoReqId].pma.io = 1'b0; @@ -556,7 +522,7 @@ module cachepool_l1_ctrl // per-lane response ready drains the coalescer's resp FIFOs (which absorb the // un-back-pressurable HPDcache core response). for (genvar i = 0; i < NrLP1CoalInputs; i++) begin : gen_spatz_resp - assign core_rsp_o[i].q_ready = cache_req_ready[i]; // request grant (also on core_req_ready_o) + assign core_rsp_o[i].q_ready = cache_req_ready[i]; assign coal_resp_ready[i] = core_rsp_ready_i[i]; assign core_rsp_o[i].p_valid = coal_resp_valid[i]; assign core_rsp_o[i].p.data = coal_resp_data[i]; @@ -628,7 +594,7 @@ module cachepool_l1_ctrl .flush_i (1'b0), .rr_i (1'b1), .req_i ({l1_mem_req_read_valid, l1_mem_req_write_both_valid}), - .gnt_o ({l1_mem_req_read_ready, __l1_mem_req_write_ready}), + .gnt_o ({l1_mem_req_read_ready, l1_mem_req_write_gnt}), .data_i ({l1_mem_req_read, l1_mem_req_write}), .req_o (l1_l2_req_valid), .gnt_i (l2_rsp_i.q_ready), @@ -636,8 +602,8 @@ module cachepool_l1_ctrl .idx_o () ); - assign l1_mem_req_write_ready = __l1_mem_req_write_ready & l1_mem_req_write_both_valid; - assign l1_mem_req_write_data_ready = __l1_mem_req_write_ready & l1_mem_req_write_both_valid; + assign l1_mem_req_write_ready = l1_mem_req_write_gnt & l1_mem_req_write_both_valid; + assign l1_mem_req_write_data_ready = l1_mem_req_write_gnt & l1_mem_req_write_both_valid; // Downstream request metadata. always_comb begin : req_meta @@ -690,8 +656,8 @@ module cachepool_l1_ctrl assign dummy_pma[i].uncacheable = 1'b0; assign dummy_pma[i].io = 1'b0; assign dummy_pma[i].wr_policy_hint = HPDCACHE_WR_POLICY_WT; - assign core_req_abort[i] = 1'b0; // phys-indexed: never abort - assign core_req_tag[i] = '0; // phys-indexed: tag in req + assign core_req_abort[i] = 1'b0; + assign core_req_tag[i] = '0; end hpdcache #( diff --git a/hardware/src/cachepool_pkg.sv b/hardware/src/cachepool_pkg.sv index ca5162b..b5d70d0 100644 --- a/hardware/src/cachepool_pkg.sv +++ b/hardware/src/cachepool_pkg.sv @@ -495,8 +495,6 @@ package cachepool_pkg; } remote_group_user_t; // Inter-group remote (FlooNoC) payload carries cacheline-wide L1->L2 traffic. - // (was: narrow_data_t / narrow_strb_t for the old 32b core->L2 path) - // `REQRSP_TYPEDEF_ALL(remote_group, narrow_addr_t, narrow_data_t, narrow_strb_t, remote_group_user_t) `REQRSP_TYPEDEF_ALL(remote_group, narrow_addr_t, cacheline_data_t, cacheline_strb_t, remote_group_user_t) // XY mesh coordinates for a group. port_id selects the eject port (always 0 for single-link). diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index 8615d1c..113044e 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -14,6 +14,7 @@ /// Tile implementation for CachePool module cachepool_tile import cachepool_pkg::*; + import cachepool_hpd_pkg::*; import spatz_pkg::*; import hpdcache_pkg::*; import fpnew_pkg::fpu_implementation_t; @@ -196,8 +197,8 @@ module cachepool_tile // localparam int unsigned CoreIDWidth = cf_math_pkg::idx_width(NrCores); localparam int unsigned TCDMMemAddrWidth = $clog2(TCDMDepth); - // Enlarge the address width for Spatz due to cache - localparam int unsigned TCDMAddrWidth = 32; + // Enlarged address width for Spatz due to cache; single source in + // cachepool_hpd_pkg (imported), also used as the private-L1 HPDcache paWidth. localparam int unsigned BanksPerSuperBank = AxiDataWidth / DataWidth; localparam int unsigned NrSuperBanks = NrBanks / BanksPerSuperBank; @@ -290,113 +291,13 @@ module cachepool_tile typedef logic [$clog2(L1NumSet)-1:0] tcdm_bank_addr_t; - //////////////////////////////////////////// - // Private L1 (LP1) HPDcache config & types // - //////////////////////////////////////////// - - // Spatz coalescer geometry - localparam int unsigned NrLP1CoalInputs = NrTCDMPortsPerCore - 1; // Spatz lanes - localparam int unsigned LP1ExtPorts = NrLP1CoalInputs; - localparam int unsigned LP1WordWidth = 128; // HPDcache word width - localparam int unsigned LP1NrBitsCoalOffset = $clog2(LP1WordWidth/DataWidth); // coalescer offset_t width - localparam int unsigned LP1NumWordOffsetBits = $clog2(LP1WordWidth/DataWidth); // tid word-offset field - localparam int unsigned LP1CoalInfoWidth = LP1ExtPorts + LP1ExtPorts*LP1NrBitsCoalOffset; - localparam int unsigned LP1ReqIdWidth = $clog2(NumSpatzOutstandingLoads); - localparam int unsigned LP1TidWidth = CoreIDWidth + TileIDWidth + LP1ReqIdWidth + 2 + LP1CoalInfoWidth; // +2: is_fpu, write; tile_id+core_id round-tripped - localparam int unsigned LP1NrRequesters = 3; // Spatz(coalesced) + Snitch + CMO injector - localparam int unsigned LP1NumSets = 16; - localparam int unsigned LP1NumWays = 4; - localparam int unsigned LP1NumWordsPerLine = 4; - - localparam hpdcache_pkg::hpdcache_user_cfg_t HPDcacheUserCfg = '{ - nRequesters: LP1NrRequesters, - paWidth: TCDMAddrWidth, - wordWidth: LP1WordWidth, - sets: LP1NumSets, - ways: LP1NumWays, - clWords: LP1NumWordsPerLine, - reqWords: 1, - reqTransIdWidth: LP1TidWidth + LP1NumWordOffsetBits, - reqSrcIdWidth: $clog2(LP1NrRequesters), // selects requester port (0 Spatz / 1 Snitch / 2 CMO) - victimSel: hpdcache_pkg::HPDCACHE_VICTIM_RANDOM, - dataWaysPerRamWord: 1, - dataSetsPerRam: LP1NumSets, - dataRamByteEnable: 1'b1, - accessWords: LP1NumWordsPerLine, - mshrSets: 4, - mshrWays: 4, - mshrWaysPerRamWord: 4, - mshrSetsPerRam: 4, - mshrRamByteEnable: 1'b1, - mshrUseRegbank: 1'b1, - cbufEntries: 2, - refillCoreRspFeedthrough: 1'b1, - refillFifoDepth: 2, - wbufDirEntries: 4, - wbufDataEntries: 4, - wbufWords: 4, - wbufTimecntWidth: 3, - rtabEntries: 4, - flushEntries: 2, - flushFifoDepth: 2, - memAddrWidth: L1AddrWidth, - // memIdWidth: LP1TidWidth, - memIdWidth: $clog2(NumSpatzOutstandingLoads), - memDataWidth: L1LineWidth, - wtEn: 1'b1, // write-through - wbEn: 1'b0, - lowLatency: 1'b1, - eccEn: 1'b0, - eccScrubberEn: 1'b0 - }; - localparam hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg = hpdcacheBuildConfig(HPDcacheUserCfg); - - // The metadata type used to restore the information from req to rsp. - // (extended with `amo` for the private-L1 datapath) - typedef struct packed { - tcdm_user_t user; - logic write; - hpdcache_req_op_t amo; - } tcdm_meta_t; - - // HPDcache request-side typedefs - typedef logic [HPDcacheCfg.tagWidth-1:0] hpdcache_tag_t; - typedef logic [HPDcacheCfg.u.wordWidth-1:0] hpdcache_data_word_t; - typedef logic [HPDcacheCfg.u.wordWidth/8-1:0] hpdcache_data_be_t; - typedef logic [HPDcacheCfg.reqOffsetWidth-1:0] hpdcache_req_offset_t; - typedef hpdcache_data_word_t [HPDcacheCfg.u.reqWords-1:0] hpdcache_req_data_t; - typedef hpdcache_data_be_t [HPDcacheCfg.u.reqWords-1:0] hpdcache_req_be_t; - typedef logic [HPDcacheCfg.u.reqSrcIdWidth-1:0] hpdcache_req_sid_t; - typedef logic [HPDcacheCfg.u.reqTransIdWidth-1:0] hpdcache_req_tid_t; - `HPDCACHE_TYPEDEF_REQ_T(hpdcache_req_t, hpdcache_req_offset_t, hpdcache_req_data_t, - hpdcache_req_be_t, hpdcache_req_sid_t, hpdcache_req_tid_t, hpdcache_tag_t); - `HPDCACHE_TYPEDEF_RSP_T(hpdcache_rsp_t, hpdcache_req_data_t, hpdcache_req_sid_t, hpdcache_req_tid_t); - typedef logic [HPDcacheCfg.u.wbufTimecntWidth-1:0] hpdcache_wbuf_timecnt_t; - - // HPDcache memory-side typedefs (L1 -> L2 mem channels) - typedef logic [HPDcacheCfg.u.memAddrWidth-1:0] hpdcache_mem_addr_t; - typedef logic [HPDcacheCfg.u.memIdWidth-1:0] hpdcache_mem_id_t; - typedef logic [HPDcacheCfg.u.memDataWidth-1:0] hpdcache_mem_data_t; - typedef logic [HPDcacheCfg.u.memDataWidth/8-1:0] hpdcache_mem_be_t; - `HPDCACHE_TYPEDEF_MEM_REQ_T(hpdcache_mem_req_t, hpdcache_mem_addr_t, hpdcache_mem_id_t); - `HPDCACHE_TYPEDEF_MEM_RESP_R_T(hpdcache_mem_resp_r_t, hpdcache_mem_id_t, hpdcache_mem_data_t); - `HPDCACHE_TYPEDEF_MEM_REQ_W_T(hpdcache_mem_req_w_t, hpdcache_mem_data_t, hpdcache_mem_be_t); - `HPDCACHE_TYPEDEF_MEM_RESP_W_T(hpdcache_mem_resp_w_t, hpdcache_mem_id_t); - - // Spatz request coalescer types. downstream_info_t MUST match - // par_coalescer_top's internal struct exactly: - // { down_id_t id; logic[ExtPorts] hitmap; offset_t[ExtPorts] ofsts; - // info_t[ExtPorts] infos; logic bypass_coalescer } - // with down_id_t = logic, offset_t = logic[$clog2(Down/Up)-1:0], info_t = tcdm_meta_t. - typedef logic [LP1NrBitsCoalOffset-1:0] lp1_offset_t; - typedef logic [LP1NumWordOffsetBits-1:0] word_offset_t; - typedef struct packed { - logic id; - logic [LP1ExtPorts-1:0] hitmap; - lp1_offset_t [LP1ExtPorts-1:0] ofsts; - tcdm_meta_t [LP1ExtPorts-1:0] infos; - logic bypass_coalescer; - } downstream_info_t; + /////////////////////////////////////////////// + // Private L1 (LP1) HPDcache config & types // + // // + // Moved to cachepool_hpd_pkg (imported above) // + // and shared with cachepool_l1_ctrl so the // + // HPDcache config/types have one definition. // + /////////////////////////////////////////////// // Regbus peripherals. `AXI_TYPEDEF_ALL(axi_mst, addr_t, id_mst_t, data_t, strb_t, user_t) @@ -653,7 +554,7 @@ module cachepool_tile unmerge_req[j].q = tcdm_req[j].q; unmerge_req[j].q_valid = tcdm_req[j].q_valid; unmerge_pready[j] = 1'b1; - + /***** RSP *****/ tcdm_rsp[j].p = unmerge_rsp[j].p; tcdm_rsp[j].p_valid = unmerge_rsp[j].p_valid; @@ -692,39 +593,20 @@ module cachepool_tile // Per-core private L1 data cache // ---------------------------------------------------------------------------- for (genvar c = 0; c < NumLP1CacheCtrl; c++) begin : gen_lp1_cache + // HPDcache config & types (HPDcacheCfg, hpdcache_*_t, tcdm_meta_t, + // downstream_info_t, word_offset_t, ...) are imported from cachepool_hpd_pkg + // by both this tile and cachepool_l1_ctrl, so they no longer need threading. cachepool_l1_ctrl #( .NrTCDMPortsPerCore (NrTCDMPortsPerCore ), .DataWidth (DataWidth ), .ByteWidth (8 ), .LP1NumWordOffsetBits (LP1NumWordOffsetBits ), .LP1NrBitsCoalOffset (LP1NrBitsCoalOffset ), - .HPDcacheCfg (HPDcacheCfg ), .wbuf_timecnt_t (hpdcache_wbuf_timecnt_t), .l1_cache_req_t (tcdm_req_t ), .l1_cache_rsp_t (tcdm_rsp_t ), - .tcdm_meta_t (tcdm_meta_t ), - .downstream_info_t (downstream_info_t ), - .word_offset_t (word_offset_t ), .l2_cache_req_t (tcdm_cacheline_req_t ), - .l2_cache_rsp_t (tcdm_cacheline_rsp_t ), - .hpdcache_tag_t (hpdcache_tag_t ), - .hpdcache_data_word_t (hpdcache_data_word_t ), - .hpdcache_data_be_t (hpdcache_data_be_t ), - .hpdcache_req_offset_t (hpdcache_req_offset_t ), - .hpdcache_req_data_t (hpdcache_req_data_t ), - .hpdcache_req_be_t (hpdcache_req_be_t ), - .hpdcache_req_sid_t (hpdcache_req_sid_t ), - .hpdcache_req_tid_t (hpdcache_req_tid_t ), - .hpdcache_req_t (hpdcache_req_t ), - .hpdcache_rsp_t (hpdcache_rsp_t ), - .hpdcache_mem_addr_t (hpdcache_mem_addr_t ), - .hpdcache_mem_id_t (hpdcache_mem_id_t ), - .hpdcache_mem_data_t (hpdcache_mem_data_t ), - .hpdcache_mem_be_t (hpdcache_mem_be_t ), - .hpdcache_mem_req_t (hpdcache_mem_req_t ), - .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t ), - .hpdcache_mem_resp_r_t (hpdcache_mem_resp_r_t ), - .hpdcache_mem_resp_w_t (hpdcache_mem_resp_w_t ) + .l2_cache_rsp_t (tcdm_cacheline_rsp_t ) ) i_lp1_cache ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -816,9 +698,6 @@ module cachepool_tile tcdm_cacheline_rsp_t [NumRemotePortTile-1:0] remote_rsp_xbar; always_comb begin : remote_flush_protection - // for (int j = 0; j < NrTCDMPortsPerCore; j++) begin - // for (int r = 0; r < NumRemotePortCore; r++) begin - // automatic int unsigned flat = j + r * NrTCDMPortsPerCore; for (int r = 0; r < NumRemotePortTile; r++) begin remote_req_gated[r].q = remote_req_i[r].q; remote_req_gated[r].q_valid = remote_req_i[r].q_valid; @@ -1061,7 +940,7 @@ module cachepool_tile ); end else begin : gen_no_remote_group // No inter-group remote ports: instantiate interco without inter-group remote ports (backward-compatible). - // Collapsed, cacheline-wide variant. Old narrow/5-plane instance below. + // Collapsed, cacheline-wide data width. tcdm_cache_interco #( .NumTiles (NumTiles ), .NumCores (NrCores ),