From 0802593695e127087618fe2df3771e468aa9a774 Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Tue, 8 Sep 2026 17:23:36 +0100 Subject: [PATCH 1/4] Add Armv8.1-M targets. These targets assume you have the DSP and LOB extensions enabled, as the Cortex-M55 and Cortex-M85 do. The LOB extension allows for much tighter loops, and hence higher performance. --- compiler/rustc_target/src/spec/mod.rs | 2 + .../spec/targets/thumbv81m_main_none_eabi.rs | 28 +++++ .../targets/thumbv81m_main_none_eabihf.rs | 31 +++++ src/bootstrap/src/core/sanity.rs | 2 + src/doc/rustc/src/SUMMARY.md | 1 + src/doc/rustc/src/platform-support.md | 2 + .../src/platform-support/arm-none-eabi.md | 1 + .../thumbv8.1m.main-none-eabi.md | 111 ++++++++++++++++++ .../thumbv8m.main-none-eabi.md | 63 ---------- tests/assembly-llvm/targets/targets-elf.rs | 6 + 10 files changed, 184 insertions(+), 63 deletions(-) create mode 100644 compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabi.rs create mode 100644 compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabihf.rs create mode 100644 src/doc/rustc/src/platform-support/thumbv8.1m.main-none-eabi.md diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs index 6c7f5a7772323..7c13ba699932a 100644 --- a/compiler/rustc_target/src/spec/mod.rs +++ b/compiler/rustc_target/src/spec/mod.rs @@ -1528,6 +1528,8 @@ supported_targets! { ("thumbv8m.base-none-eabi", thumbv8m_base_none_eabi), ("thumbv8m.main-none-eabi", thumbv8m_main_none_eabi), ("thumbv8m.main-none-eabihf", thumbv8m_main_none_eabihf), + ("thumbv8.1m.main-none-eabi", thumbv81m_main_none_eabi), + ("thumbv8.1m.main-none-eabihf", thumbv81m_main_none_eabihf), ("armv7a-none-eabi", armv7a_none_eabi), ("thumbv7a-none-eabi", thumbv7a_none_eabi), diff --git a/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabi.rs b/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabi.rs new file mode 100644 index 0000000000000..54f04ed1d8770 --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabi.rs @@ -0,0 +1,28 @@ +// Targets the Cortex-M55/-M85 processors (Armv8.1-M Mainline architecture profile), +// without the Floating Point extension. + +use crate::spec::{Arch, CfgAbi, FloatAbi, Target, TargetMetadata, TargetOptions, base}; + +pub(crate) fn target() -> Target { + Target { + llvm_target: "thumbv8.1m.main-none-eabi".into(), + metadata: TargetMetadata { + description: Some("Bare ARMv8.1-M Mainline with DSP and LOB".into()), + tier: Some(2), + host_tools: Some(false), + std: Some(false), + }, + pointer_width: 32, + data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), + arch: Arch::Arm, + + options: TargetOptions { + cfg_abi: CfgAbi::Eabi, + llvm_floatabi: Some(FloatAbi::Soft), + // We assume you have the DSP and LOB extensions (which are technically optional). + features: "+dsp,+lob".into(), + max_atomic_width: Some(32), + ..base::arm_none::opts() + }, + } +} diff --git a/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabihf.rs new file mode 100644 index 0000000000000..55a6c6ddaf494 --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabihf.rs @@ -0,0 +1,31 @@ +// Targets the Cortex-M55/-M85 processors (Armv8.1-M Mainline architecture profile), +// with the Floating Point extension. +// +// It does not assume you have M-Profile Vector Extensions (aka Helium) + +use crate::spec::{Arch, CfgAbi, FloatAbi, Target, TargetMetadata, TargetOptions, base}; + +pub(crate) fn target() -> Target { + Target { + llvm_target: "thumbv8.1m.main-none-eabihf".into(), + metadata: TargetMetadata { + description: Some("Bare ARMv8.1-M Mainline, hardfloat, with DSP and LOB".into()), + tier: Some(2), + host_tools: Some(false), + std: Some(false), + }, + pointer_width: 32, + data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), + arch: Arch::Arm, + + options: TargetOptions { + cfg_abi: CfgAbi::EabiHf, + llvm_floatabi: Some(FloatAbi::Hard), + // The Cortex-M55 and Cortex-M85 both have FPv5-D16 double-precision FPUs + // We also assume you have the DSP and LOB extensions (which are technically optional). + features: "+dsp,+fp-armv8d16,+lob".into(), + max_atomic_width: Some(32), + ..base::arm_none::opts() + }, + } +} diff --git a/src/bootstrap/src/core/sanity.rs b/src/bootstrap/src/core/sanity.rs index ac44a4dfca9b1..1d9542021e234 100644 --- a/src/bootstrap/src/core/sanity.rs +++ b/src/bootstrap/src/core/sanity.rs @@ -37,6 +37,8 @@ pub struct Finder { const STAGE0_MISSING_TARGETS: &[&str] = &[ // just a dummy comment so the list doesn't get onelined "aarch64-unknown-qtee", + "thumbv8.1m.main-none-eabihf", + "thumbv8.1m.main-none-eabi", ]; /// Minimum version threshold for libstdc++ required when using prebuilt LLVM diff --git a/src/doc/rustc/src/SUMMARY.md b/src/doc/rustc/src/SUMMARY.md index 953789648485b..a8dd4b66b44ae 100644 --- a/src/doc/rustc/src/SUMMARY.md +++ b/src/doc/rustc/src/SUMMARY.md @@ -67,6 +67,7 @@ - [thumbv7m-none-eabi](./platform-support/thumbv7m-none-eabi.md) - [thumbv8m.base-none-eabi](./platform-support/thumbv8m.base-none-eabi.md) - [thumbv8m.main-none-eabi\*](./platform-support/thumbv8m.main-none-eabi.md) + - [thumbv8.1m.main-none-eabi\*](./platform-support/thumbv8.1m.main-none-eabi.md) - [armebv7r-none-eabi{,hf}](platform-support/armebv7r-none-eabi.md) - [arm\*-unknown-linux-\*](./platform-support/arm-linux.md) - [armeb-unknown-linux-gnueabi](platform-support/armeb-unknown-linux-gnueabi.md) diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md index 2321dec16b8eb..fc71e94211268 100644 --- a/src/doc/rustc/src/platform-support.md +++ b/src/doc/rustc/src/platform-support.md @@ -448,6 +448,8 @@ target | std | host | notes [`thumbv8m.base-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv8M Baseline with NuttX [`thumbv8m.main-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv8M Mainline with NuttX [`thumbv8m.main-nuttx-eabihf`](platform-support/nuttx.md) | ✓ | | ARMv8M Mainline with NuttX, hardfloat +[`thumbv8.1m.main-none-eabi`](platform-support/thumbv8.1m.main-none-eabi.md) | * | | Bare Armv8.1-M Mainline, with DSP and LOB +[`thumbv8.1m.main-none-eabihf`](platform-support/thumbv8.1m.main-none-eabi.md) | * | | Bare Armv8.1-M Mainline, hardfloat, with DSP and LOB [`wasm64-unknown-unknown`](platform-support/wasm64-unknown-unknown.md) | ? | | WebAssembly [`wasm32-wali-linux-musl`](platform-support/wasm32-wali-linux.md) | ? | | WebAssembly with [WALI](https://github.com/arjunr2/WALI) [`x86_64-apple-tvos`](platform-support/apple-tvos.md) | ✓ | | x86 64-bit tvOS diff --git a/src/doc/rustc/src/platform-support/arm-none-eabi.md b/src/doc/rustc/src/platform-support/arm-none-eabi.md index 4a6c4783f6d7b..3e3b6a6c44e2e 100644 --- a/src/doc/rustc/src/platform-support/arm-none-eabi.md +++ b/src/doc/rustc/src/platform-support/arm-none-eabi.md @@ -26,6 +26,7 @@ their own document. - [`thumbv7em-none-eabi` and `thumbv7em-none-eabihf`](thumbv7em-none-eabi.md) - [`thumbv8m.base-none-eabi`](thumbv8m.base-none-eabi.md) - [`thumbv8m.main-none-eabi` and `thumbv8m.main-none-eabihf`](thumbv8m.main-none-eabi.md) + - [`thumbv8.1m.main-none-eabi` and `thumbv8.1m.main-none-eabihf`](thumbv8.1m.main-none-eabi.md) - *Legacy* Arm Architectures - None diff --git a/src/doc/rustc/src/platform-support/thumbv8.1m.main-none-eabi.md b/src/doc/rustc/src/platform-support/thumbv8.1m.main-none-eabi.md new file mode 100644 index 0000000000000..67fd5c2badfe4 --- /dev/null +++ b/src/doc/rustc/src/platform-support/thumbv8.1m.main-none-eabi.md @@ -0,0 +1,111 @@ +# `thumbv8.1m.main-none-eabi` and `thumbv8.1m.main-none-eabihf` + +* **Tier: 3** +* **Library Support:** core and alloc (bare-metal, `#![no_std]`) + +Bare-metal target for CPUs in the Mainline [Armv8.1-M] architecture family, +supporting a subset of the [T32 ISA][t32-isa]. + +Processors in this family include the: + +* [Arm Cortex-M55][cortex-m55] +* [Arm Cortex-M85][cortex-m85] + +This target assumes your processor supports the *DSP* and *Low-Overhead Branch* extensions. + +See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all +`arm-none-eabi` targets, in particular the difference between the `eabi` and +`eabihf` ABI. + +[t32-isa]: https://developer.arm.com/Architectures/T32%20Instruction%20Set%20Architecture +[Armv8.1-M]: https://developer.arm.com/documentation/ddi0553/latest/ +[cortex-m55]: https://developer.arm.com/Processors/Cortex-M55 +[cortex-m85]: https://developer.arm.com/Processors/Cortex-M85 + +## Target maintainers + +- [Rust Embedded Devices Working Group Arm Team](https://github.com/rust-embedded/wg?tab=readme-ov-file#the-arm-team) +- [arm-maintainers][arm_maintainers] ([rust@arm.com][arm_email]) + - Use `@rustbot ping arm-maintainers` to ping us + +[arm_maintainers]: https://github.com/rust-lang/team/blob/master/teams/arm-maintainers.toml +[arm_email]: mailto:rust@arm.com + +## Target CPU and Target Feature options + +See [the bare-metal Arm +docs](arm-none-eabi.md#target-cpu-and-target-feature-options) for details on how +to use these flags. + +### Table of supported CPUs for `thumbv8.1m.main-none-eabi` + +| CPU | FPU | DSP | MVE | Target CPU | Target Features | +| ----------- | --- | --- | --------- | ------------- | --------------------- | +| Unspecified | No | No | No | None | None | +| Cortex-M55 | No | Yes | No | `cortex-m55` | `-fpregs,-mve` | +| Cortex-M55 | DP | Yes | No | `cortex-m55` | `-mve` | +| Cortex-M55 | No | Yes | Int | `cortex-m55` | `-fpregs,-mve.fp,+mve`| +| Cortex-M55 | DP | Yes | Int | `cortex-m55` | `-mve.fp` | +| Cortex-M55 | DP | Yes | Int+Float | `cortex-m55` | None | +| Cortex-M85 | No | Yes | No | `cortex-m85` | `-fpregs,-mve` | +| Cortex-M85 | DP | Yes | No | `cortex-m85` | `-mve` | +| Cortex-M85 | No | Yes | Int | `cortex-m85` | `-fpregs,-mve.fp,+mve`| +| Cortex-M85 | DP | Yes | Int | `cortex-m85` | `-mve.fp` | +| Cortex-M85 | DP | Yes | Int+Float | `cortex-m85` | None | + +### Table of supported CPUs for `thumbv8.1m.main-none-eabihf` + +| CPU | FPU | DSP | MVE | Target CPU | Target Features | +| ----------- | --- | --- | --------- | ------------- | --------------------- | +| Unspecified | DP | No | No | None | None | +| Cortex-M55 | DP | Yes | No | `cortex-m55` | `-mve` | +| Cortex-M55 | DP | Yes | Int | `cortex-m55` | `-mve.fp` | +| Cortex-M55 | DP | Yes | Int+Float | `cortex-m55` | None | +| Cortex-M85 | DP | Yes | No | `cortex-m85` | `-mve` | +| Cortex-M85 | DP | Yes | Int | `cortex-m85` | `-mve.fp` | +| Cortex-M85 | DP | Yes | Int+Float | `cortex-m85` | None | + +*Technically* you can use this hard-float ABI on a CPU which has no FPU but does +have Integer MVE, because MVE provides the same set of registers as the FPU +(including `s0` and `d0`). The particular set of flags that might enable this +unusual scenario are currently not recorded here. + +
+ +Never use the `-fpregs` *target-feature* with the `thumbv8.1m.main-none-eabihf` +target as it will cause compilation units to have different ABIs, which is +unsound. + +
+ +### M-Profile Vector Extensions + +The M-Profile Vector Extensions (also known as MVE, and marketed as "Helium") allow the processor to perform SIMD operations. MVE is available in either *integer-only* or *integer-and-float* variants. This target does not assume MVE support by default, but it can be added by specifying a *target-cpu*, or using certain *target-features* (noted below). + +### Arm Cortex-M55 + +The target CPU is `cortex-m55`. + +* Has an optional double-precision FPU that also supports half-precision FP16 + values + * support is enabled by default with this *target-cpu* the 'eabihf' target + * disable support using the `-fpregs` *target-feature* (`eabi` only) +* Has optional support for M-Profile Vector Extensions + * The appropriate feature for the MVE is either `mve` (integer) or `mve.fp` + (float) + * `mve.fp` is enabled by default on this *target-cpu* + * disable using `-mve.fp` (disable float MVE) or `-mve` (disable all MVE) + +### Arm Cortex-M85 + +The target CPU is `cortex-m85`. + +* Has an optional double-precision FPU that also supports half-precision FP16 + values + * support is enabled by default with this *target-cpu* or the 'eabihf' target + * disable support using the `-fpregs` *target-feature* (`eabi` only) +* Has optional support for M-Profile Vector Extensions + * The appropriate feature for the MVE is either `mve` (integer) or `mve.fp` + (float) + * `mve.fp` is enabled by default on this *target-cpu* + * disable using `-mve.fp` (disable float MVE) or `-mve` (disable all MVE) diff --git a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md index 29233fb92b799..9d89a12b6c900 100644 --- a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md +++ b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md @@ -10,8 +10,6 @@ Processors in this family include the: * [Arm Cortex-M33][cortex-m33] * [Arm Cortex-M35P][cortex-m35p] -* [Arm Cortex-M55][cortex-m55] -* [Arm Cortex-M85][cortex-m85] See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all `arm-none-eabi` targets, in particular the difference between the `eabi` and @@ -21,8 +19,6 @@ See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all [Armv8-M]: https://developer.arm.com/documentation/ddi0553/latest/ [cortex-m33]: https://developer.arm.com/Processors/Cortex-M33 [cortex-m35p]: https://developer.arm.com/Processors/Cortex-M35P -[cortex-m55]: https://developer.arm.com/Processors/Cortex-M55 -[cortex-m85]: https://developer.arm.com/Processors/Cortex-M85 ## Target maintainers @@ -52,16 +48,6 @@ to use these flags. | Cortex-M35P | No | Yes | No | `cortex-m35p` | `-fpregs` | | Cortex-M35P | SP | No | No | `cortex-m35p` | `-dsp` | | Cortex-M35P | SP | Yes | No | `cortex-m35p` | None | -| Cortex-M55 | No | Yes | No | `cortex-m55` | `-fpregs,-mve` | -| Cortex-M55 | DP | Yes | No | `cortex-m55` | `-mve` | -| Cortex-M55 | No | Yes | Int | `cortex-m55` | `-fpregs,-mve.fp,+mve`| -| Cortex-M55 | DP | Yes | Int | `cortex-m55` | `-mve.fp` | -| Cortex-M55 | DP | Yes | Int+Float | `cortex-m55` | None | -| Cortex-M85 | No | Yes | No | `cortex-m85` | `-fpregs,-mve` | -| Cortex-M85 | DP | Yes | No | `cortex-m85` | `-mve` | -| Cortex-M85 | No | Yes | Int | `cortex-m85` | `-fpregs,-mve.fp,+mve`| -| Cortex-M85 | DP | Yes | Int | `cortex-m85` | `-mve.fp` | -| Cortex-M85 | DP | Yes | Int+Float | `cortex-m85` | None | ### Table of supported CPUs for `thumbv8m.main-none-eabihf` @@ -72,17 +58,6 @@ to use these flags. | Cortex-M33 | SP | Yes | No | `cortex-m33` | None | | Cortex-M33P | SP | No | No | `cortex-m35p` | `-dsp` | | Cortex-M33P | SP | Yes | No | `cortex-m35p` | None | -| Cortex-M55 | DP | Yes | No | `cortex-m55` | `-mve` | -| Cortex-M55 | DP | Yes | Int | `cortex-m55` | `-mve.fp` | -| Cortex-M55 | DP | Yes | Int+Float | `cortex-m55` | None | -| Cortex-M85 | DP | Yes | No | `cortex-m85` | `-mve` | -| Cortex-M85 | DP | Yes | Int | `cortex-m85` | `-mve.fp` | -| Cortex-M85 | DP | Yes | Int+Float | `cortex-m85` | None | - -*Technically* you can use this hard-float ABI on a CPU which has no FPU but does -have Integer MVE, because MVE provides the same set of registers as the FPU -(including `s0` and `d0`). The particular set of flags that might enable this -unusual scenario are currently not recorded here.
@@ -113,41 +88,3 @@ The target CPU is `cortex-m35p`. * Has an optional single precision FPU * support is enabled by default with this *target-cpu* * disable support using the `-fpregs` *target-feature* (`eabi` only) - -### Arm Cortex-M55 - -The target CPU is `cortex-m55`. - -* Has DSP extensions - * support is controlled by the `dsp` *target-feature* - * enabled by default with this *target-cpu* -* Has an optional double-precision FPU that also supports half-precision FP16 - values - * support is enabled by default with this *target-cpu* - * disable support using the `-fpregs` *target-feature* (`eabi` only) -* Has optional support for M-Profile Vector Extensions - * Also known as *Helium Technology* - * Available with only integer support, or both integer/float support - * The appropriate feature for the MVE is either `mve` (integer) or `mve.fp` - (float) - * `mve.fp` is enabled by default on this target CPU - * disable using `-mve.fp` (disable float MVE) or `-mve` (disable all MVE) - -### Arm Cortex-M85 - -The target CPU is `cortex-m85`. - -* Has DSP extensions - * support is controlled by the `dsp` *target-feature* - * enabled by default with this *target-cpu* -* Has an optional double-precision FPU that also supports half-precision FP16 - values - * support is enabled by default with this *target-cpu* - * disable support using the `-fpregs` *target-feature* (`eabi` only) -* Has optional support for M-Profile Vector Extensions - * Also known as *Helium Technology* - * Available with only integer support, or both integer/float support - * The appropriate feature for the MVE is either `mve` (integer) or `mve.fp` - (float) - * `mve.fp` is enabled by default on this target CPU - * disable using `-mve.fp` (disable float MVE) or `-mve` (disable all MVE) diff --git a/tests/assembly-llvm/targets/targets-elf.rs b/tests/assembly-llvm/targets/targets-elf.rs index 075863c673045..d5e56bcae7d8d 100644 --- a/tests/assembly-llvm/targets/targets-elf.rs +++ b/tests/assembly-llvm/targets/targets-elf.rs @@ -652,9 +652,15 @@ //@ revisions: thumbv8m_main_none_eabi //@ [thumbv8m_main_none_eabi] compile-flags: --target thumbv8m.main-none-eabi //@ [thumbv8m_main_none_eabi] needs-llvm-components: arm +//@ revisions: thumbv81m_main_none_eabi +//@ [thumbv81m_main_none_eabi] compile-flags: --target thumbv8.1m.main-none-eabi +//@ [thumbv81m_main_none_eabi] needs-llvm-components: arm //@ revisions: thumbv8m_main_none_eabihf //@ [thumbv8m_main_none_eabihf] compile-flags: --target thumbv8m.main-none-eabihf //@ [thumbv8m_main_none_eabihf] needs-llvm-components: arm +//@ revisions: thumbv81m_main_none_eabihf +//@ [thumbv81m_main_none_eabihf] compile-flags: --target thumbv8.1m.main-none-eabihf +//@ [thumbv81m_main_none_eabihf] needs-llvm-components: arm //@ revisions: wasm32_unknown_emscripten //@ [wasm32_unknown_emscripten] compile-flags: --target wasm32-unknown-emscripten //@ [wasm32_unknown_emscripten] needs-llvm-components: webassembly From 1f797a76969c642f344ba16d198308336b484913 Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Wed, 9 Sep 2026 16:35:16 +0100 Subject: [PATCH 2/4] Add new Armv8.1-M targets to `ignore_target_names` --- src/tools/tier-check/src/main.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/tools/tier-check/src/main.rs b/src/tools/tier-check/src/main.rs index 6c27a2ec442c5..c4348c4d572c9 100644 --- a/src/tools/tier-check/src/main.rs +++ b/src/tools/tier-check/src/main.rs @@ -49,6 +49,8 @@ fn main() { "thumbv8m.base-none-eabi", "thumbv8m.main-none-eabi", "thumbv8m.main-none-eabihf", + "thumbv8.1m.main-none-eabi", + "thumbv8.1m.main-none-eabihf", "thumbv8m.base-nuttx-eabi", "thumbv8m.main-nuttx-eabi", "thumbv8m.main-nuttx-eabihf", From 35f53f8fb404cf79973a757ce7c3b81856a31e7f Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Wed, 9 Sep 2026 16:35:49 +0100 Subject: [PATCH 3/4] Remove DSP column from Armv8.1-M platform page We assume the DSP is present so the column isn't useful --- .../thumbv8.1m.main-none-eabi.md | 44 +++++++++---------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/src/doc/rustc/src/platform-support/thumbv8.1m.main-none-eabi.md b/src/doc/rustc/src/platform-support/thumbv8.1m.main-none-eabi.md index 67fd5c2badfe4..6f7a07b16e0aa 100644 --- a/src/doc/rustc/src/platform-support/thumbv8.1m.main-none-eabi.md +++ b/src/doc/rustc/src/platform-support/thumbv8.1m.main-none-eabi.md @@ -39,31 +39,31 @@ to use these flags. ### Table of supported CPUs for `thumbv8.1m.main-none-eabi` -| CPU | FPU | DSP | MVE | Target CPU | Target Features | -| ----------- | --- | --- | --------- | ------------- | --------------------- | -| Unspecified | No | No | No | None | None | -| Cortex-M55 | No | Yes | No | `cortex-m55` | `-fpregs,-mve` | -| Cortex-M55 | DP | Yes | No | `cortex-m55` | `-mve` | -| Cortex-M55 | No | Yes | Int | `cortex-m55` | `-fpregs,-mve.fp,+mve`| -| Cortex-M55 | DP | Yes | Int | `cortex-m55` | `-mve.fp` | -| Cortex-M55 | DP | Yes | Int+Float | `cortex-m55` | None | -| Cortex-M85 | No | Yes | No | `cortex-m85` | `-fpregs,-mve` | -| Cortex-M85 | DP | Yes | No | `cortex-m85` | `-mve` | -| Cortex-M85 | No | Yes | Int | `cortex-m85` | `-fpregs,-mve.fp,+mve`| -| Cortex-M85 | DP | Yes | Int | `cortex-m85` | `-mve.fp` | -| Cortex-M85 | DP | Yes | Int+Float | `cortex-m85` | None | +| CPU | FPU | MVE | Target CPU | Target Features | +| ----------- | --- | --------- | ------------- | --------------------- | +| Unspecified | No | No | None | None | +| Cortex-M55 | No | No | `cortex-m55` | `-fpregs,-mve` | +| Cortex-M55 | DP | No | `cortex-m55` | `-mve` | +| Cortex-M55 | No | Int | `cortex-m55` | `-fpregs,-mve.fp,+mve`| +| Cortex-M55 | DP | Int | `cortex-m55` | `-mve.fp` | +| Cortex-M55 | DP | Int+Float | `cortex-m55` | None | +| Cortex-M85 | No | No | `cortex-m85` | `-fpregs,-mve` | +| Cortex-M85 | DP | No | `cortex-m85` | `-mve` | +| Cortex-M85 | No | Int | `cortex-m85` | `-fpregs,-mve.fp,+mve`| +| Cortex-M85 | DP | Int | `cortex-m85` | `-mve.fp` | +| Cortex-M85 | DP | Int+Float | `cortex-m85` | None | ### Table of supported CPUs for `thumbv8.1m.main-none-eabihf` -| CPU | FPU | DSP | MVE | Target CPU | Target Features | -| ----------- | --- | --- | --------- | ------------- | --------------------- | -| Unspecified | DP | No | No | None | None | -| Cortex-M55 | DP | Yes | No | `cortex-m55` | `-mve` | -| Cortex-M55 | DP | Yes | Int | `cortex-m55` | `-mve.fp` | -| Cortex-M55 | DP | Yes | Int+Float | `cortex-m55` | None | -| Cortex-M85 | DP | Yes | No | `cortex-m85` | `-mve` | -| Cortex-M85 | DP | Yes | Int | `cortex-m85` | `-mve.fp` | -| Cortex-M85 | DP | Yes | Int+Float | `cortex-m85` | None | +| CPU | FPU | MVE | Target CPU | Target Features | +| ----------- | --- | --------- | ------------- | --------------------- | +| Unspecified | DP | No | None | None | +| Cortex-M55 | DP | No | `cortex-m55` | `-mve` | +| Cortex-M55 | DP | Int | `cortex-m55` | `-mve.fp` | +| Cortex-M55 | DP | Int+Float | `cortex-m55` | None | +| Cortex-M85 | DP | No | `cortex-m85` | `-mve` | +| Cortex-M85 | DP | Int | `cortex-m85` | `-mve.fp` | +| Cortex-M85 | DP | Int+Float | `cortex-m85` | None | *Technically* you can use this hard-float ABI on a CPU which has no FPU but does have Integer MVE, because MVE provides the same set of registers as the FPU From 2efae290bc362accfa2b1e3ca8e141822c90e6f8 Mon Sep 17 00:00:00 2001 From: Jonathan Pallant Date: Sun, 13 Sep 2026 18:26:44 +0100 Subject: [PATCH 4/4] Correct target tier for Armv8.1-M targets They are Tier 3, not Tier 2. --- .../rustc_target/src/spec/targets/thumbv81m_main_none_eabi.rs | 2 +- .../rustc_target/src/spec/targets/thumbv81m_main_none_eabihf.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabi.rs b/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabi.rs index 54f04ed1d8770..1c197aef1d5ab 100644 --- a/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabi.rs +++ b/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabi.rs @@ -8,7 +8,7 @@ pub(crate) fn target() -> Target { llvm_target: "thumbv8.1m.main-none-eabi".into(), metadata: TargetMetadata { description: Some("Bare ARMv8.1-M Mainline with DSP and LOB".into()), - tier: Some(2), + tier: Some(3), host_tools: Some(false), std: Some(false), }, diff --git a/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabihf.rs index 55a6c6ddaf494..a93ba1ab47fc7 100644 --- a/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabihf.rs +++ b/compiler/rustc_target/src/spec/targets/thumbv81m_main_none_eabihf.rs @@ -10,7 +10,7 @@ pub(crate) fn target() -> Target { llvm_target: "thumbv8.1m.main-none-eabihf".into(), metadata: TargetMetadata { description: Some("Bare ARMv8.1-M Mainline, hardfloat, with DSP and LOB".into()), - tier: Some(2), + tier: Some(3), host_tools: Some(false), std: Some(false), },